Accurate Substrate Noise Analysis Based on Library Module Characterization
Subodh M. Reddy Rajeev Murgai
Fujitsu Laboratories of America, Inc.
Sunnyvale, CA, USA
subodh,murgai
@fla.fujitsu.com
Abstract
As the design complexity increases, a detailed SPICE model can-
not be used to study substrate noise injected by the digital logic
into the analog circuit in a mixed-signal system. Hence a reduced
yet accurate model is needed. Previous work [7] shows that the
current drawn by the digital circuit from the power supply has a
big impact on the substrate noise and therefore must be modeled
accurately in the reduced model. In this paper, we propose an
accurate current modeling technique based on pre-characterizing
library modules for the current drawn from the power supply as
a function of time, load capacitance, input transitions and slews.
This technique is then embedded in both pattern-dependent (PDM)
[3, 15] and pattern-independent (PIM) [7] substrate noise analy-
sis methodologies. Results on several gate-level benchmarks show
that the proposed scheme is, on average, within 4.5% of the de-
tailed BSIM3-based model for PDM and within 12% for PIM. In
contrast, the previously proposed scheme of [7] has an average
discrepancy of 176% with the detailed model for PIM.
1 Motivation
In mixed-signal designs, switching noise due to large signal
swings in the digital part can propagate through the common sub-
strate to the analog part and corrupt the sensitive analog part (Fig-
ure 1). The two major sources that contribute to substrate noise
(SN) are power supply noise and transistor leakage currents [2].
1. Power Supply Noise and Ground Bounce: When the out-
put of a gate switches, it causes current to be drawn from the
power supply network. Due to the resistance and inductance of
the power supply network, the potentials of the power supply and
ground networks change, both spatially and temporally, resulting
in power supply noise and ground bounce (also called simulta-
neous switching noise). Since substrate is directly connected to
ground node (VSS) and indirectly connected through NWELL to
the power supply (VDD), the changes in power supply and ground
network are coupled to the substrate (especially if the substrate has
low resistivity) as noise.
2. Transistor Leakage Currents: The junctions between wells
and the substrate and those between sources/drains and their re-
spective wells form reverse-biased parasitic diodes. These diodes
conduct small leakage currents, which are injected directly into the
substrate. Due to the low resistivity of the substrate these currents
change the potential of the substrate affecting analog devices that
share the same substrate.
It turns out that the power supply noise is by far the dominant
contributor to SN at the circuit level [2]. So in our work, we only
model the power supply noise.
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vdd
Package
vss
Power
Supply
vdd vss avd avs
Switching noise
generator Digital Analog
Logic Circuit Affected by substrate noise
substrate
Chip
Figure 1: Substrate noise in mixed-signal system
Shrinking feature size lets more devices to be packed on a
chip, generating higher noise. In addition, smaller devices have
smaller threshold voltages, resulting in larger sub-threshold leak-
age currents and noise. Smaller devices are also more sensitive
to noise because of reduced noise margins. Increasing switch-
ing rates and decreasing transition times are also responsible for
more transients. Due to all these deep sub-micron effects, sub-
strate noise analysis (SNA) has become a critical problem in most
mixed-signal designs.
A circuit simulator, such as SPICE, is the primary tool used by
designers for substrate noise analysis. Circuit model (also called a
reference model) consisting of accurate device, substrate and in-
terconnect models is derived. However, it is not feasible to simu-
late the reference model even for a 100K-gate design on thousands
of input vectors. With the chip complexity in millions of gates, it
is important to derive high-level methodologies and reduced cir-
cuit models (RMs) to enable an efficient yet accurate chip-level
SNA. A significant amount of research has been done on deriving
such reduced models [3, 15, 4, 5, 9, 8, 11, 10, 7]. However, each
of these works suffers from some problem: either it is not accurate
enough or is unsuitable for chip-level analysis.
Since power supply noise is the biggest contributor to the sub-
strate noise at the circuit level, one main component of the reduced
models for SNA is , the total current drawn from the power sup-
ply by the digital cells (Figure 6). Previous work [7] shows that
has a large impact on the substrate noise and therefore must be
modeled accurately. In this paper, we propose a new and highly
accurate current modeling technique based on pre-characterizing
library modules for the current drawn from the power supply. This
current is a function of time, load capacitance, input transitions
and slews. The main contributions of our work are as follows.
1. Our current waveform generation technique is more accurate
than the previous approaches based on library module char-
acterization such as [3, 15]. These approaches did not take
into account the dependence of current on the output load
 Vdd
and input slews, whereas our technique does. We model RLC Mesh
multiple input transitions and transistor switchings in the in-
ternal stages of a gate. Lvia
Package Model

2. Our approach can be embedded both in pattern-dependent Rvia

methodology (PDM) [3, 15] and pattern-independent Local Vdd

methodology (PIM) [7]. PDM simulates the circuit model Rnw Repi2 Repi2 Rnw
Substrate Network : N
on a sequence of input vectors, whereas PIM estimates the
Cnw Cnw
worst-case noise over all possible input vectors. PDM is
more accurate, but takes enormous CPU time. In contrast,Vin1 Cload Cload Vin2

PIM is faster, but less accurate. We propose new algorithms Vss Repi1 Rs1s2 Repi1 Vss
S1 S2
to embed our scheme in PDM and PIM.
Rpw Rpw
3. Package influences the substrate noise considerably. We in-
Repi3 Repi3
clude effect of package in our noise model by incorporating
a package model.
4. Results on several benchmarks show that the proposed
Local Vss
scheme is, on average, within 4.5% of the reference BSIM3- Rvia
based model for PDM and within 12% for PIM. In contrast,
Lvia
the previously proposed scheme of [7] has an average dis-
Package Model
crepancy of 176% with the reference model for PIM. RLC Mesh
Vss
The paper is organized as follows. Section 2 describes the prob-
lem addressed in this paper. The necessary background is pro-
vided in Section 3. Previous work on substrate noise analysis is Figure 2: Reference model for a design with only two inverters
summarized in Section 4. In Section 5, we present details of the
proposed scheme for accurately modeling the current drawn by
S1 S2 S3
a digital circuit from the power supply, using it to compute sub- U1 U2 U3
strate noise, and integrating the scheme into pattern-dependent and
pattern-independent SNA methodologies. Section 6 presents ex-
perimental evidence of the accuracy of our scheme. Conclusions U4 U5 U6
and directions for future work are presented in Section 7. S4 S5 S6

2 Problem Statement Figure 3: Layout-driven substrate noise model

The overall goal of this research is to derive a methodology for ac-
curate substrate noise analysis of a chip-level mixed-signal design.
In other words, given any point
in the substrate, the methodology
should be able to generate the worst time-domain and frequency-
domain voltage waveform at
. The scalability of SNA to chip-
level designs was addressed in previous works, the key ideas be-
ing use of reduced models and a pattern-independent methodol-
ogy [7]. However, the accuracy results leave a lot to be desired.
The focus of this paper is to improve the accuracy of the reduced
model. We derive an accurate time-domain waveform of the cur-
rent drawn from the power supply by the digital circuit for pattern-
dependent methodology (in which the primary input patterns are
provided), and a worst-case waveform for the pattern-independent
methodology (in which an estimate of the maximum peak-to-peak
noise over all patterns is generated). The current waveform is
then embedded in the reduced model, which is simulated to yield
the time-domain response of substrate noise or peak-to-peak sub-
strate noise. These metrics (time domain response and peak-to-
peak substrate noise) are important because any fluctuation in the
substrate reference potential changes the threshold voltage of the
devices (body effect), playing havoc with the noise margins. Ana-
log devices are especially sensitive to substrate reference potential
changes.
3 Preliminaries
The terms gate and cell refer to a gate used in the actual design. A
library module refers to a library element. In other words, a gate
or cell is an instance of a library module.
Given two consecutive clock cycles, the value pair  of a signal
 in the given design is the pair of values that  takes in the two
cycles. All possible value pairs of a signal are 00, 11, 01, and 10.
01 corresponds to a rising transition and 10 to a falling transition
on  . The slew or transition time  of a signal  is the time it
takes for  to change from 20 of VDD to 80 of VDD for a
rising transition and from 80 of VDD to 20 VDD for a falling
 denotes
transition. Given a gate with  inputs ½ through  , 
the vector of value pairs of ½ through  , and   , the vector of
input slews. The slew 
at input 
is relevant only when the
corresponding value pair 
at 
corresponds to a transition.
3.1 Reference Model
For a small design (also called a block) that can be simulated with
SPICE in reasonable CPU time, an accurate reference model can
be derived and simulated for the substrate voltage [1, 16, 13, 14, 7].
The reference model for a single cell is derived from its transistor-
level netlist and the BSIM3/BSIM4 model for each transistor. As
shown in Figure 2, the reference model also includes a substrate
network, which contains the substrate or BULK node. Reference
models for all the cells in the block are then composed based on
the layout of the block and optionally integrated with the pack-
age model to generate the complete reference model for the block.
While composing, the BULK nodes 
of adjacent cells 
in the
layout are connected through a resistance, as shown in Figure 3.

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 gate−level
circuit
logic−level static timing
input patterns simulator analysis
cycle−accurate
switching activity
current−waveform
generator
reduced model
generator
reduced
model
spice simulation
substrate voltage
Figure 4: Pattern-dependent methodology (PDM) [3]
The value of the resistance between two adjacent cells is directly
proportional to the distance between the two cells.
The reference model for a block consisting of two inverters is
shown in Figure 2. Although for simplicity we show NMOS and
PMOS transistors in each inverter, in the actual model these tran-
sistors are replaced by their BSIM3/BSIM4 models. The substrate
network for each inverter is also shown. The substrate network
contains one substrate node referred to as BULK (nodes ½ and
¾ in Figure 2). The substrate noise is measured at the BULK
node. The PMOS transistor substrate node is connected to the
BULK node through a series connection of a capacitor   and
a resistor 
¾ .   represents the reverse-biased NWELL to
P- epi layer junction diode and 
¾ represents the P- epi layer
resistance under the NWELL area. For an NMOS transistor, its
substrate node is connected to the BULK node through a resistor

½ (the P- epi layer resistance under the transistor). The BULK
nodes ½ and ¾ of the two inverters are connected with a resis-
tance  ½ ¾ . If the substrate has low resistivity and the block
is small, the resistance between BULK nodes of adjacent cells is
negligible. In other words, the BULK nodes of the cells in a small
block are effectively the same electrical node.
Each block has local VDD and local VSS nodes, which are con-
nected to the package model, which, in turn, is connected to the
external VSS and VDD lines respectively. In the package model,

 and

 are the cumulative via resistance and inductance.
The RLC mesh model is derived from the power and ground layers
in the package; the details can be found in [7].
4 Previous Work
A lot of research work has been done on modeling the substrate
noise during the design phase. A common feature of almost all
the work is the use of a reduced model for the digital circuit.
Two different substrate analysis methodologies have been pro-
posed: pattern-dependent methodology (PDM) [3, 15, 6, 4, 5] and
pattern-independent methodology (PIM) [7]. As shown in Figure
4, in PDM, we are given a digital gate-level circuit and a test-bench
consisting of input vectors. Each module in the library is simulated
with SPICE for all possible inputs, and power supply current and
substrate injection currents are extracted. The digital circuit is sim-
correspond to the decoupling capacitance cells placed in
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gate−level
circuit
static timing
timing info analysis
timing info
cell library switching current−waveform cell library
activity generator
package
model
reduced model
package
generator model
reduced
model
spice simulation
substrate voltage
Figure 5: Pattern-independent methodology (PIM) [7]
ulated for each input vector. The gates that switch and their switch-
ing times are recorded. This information is used to derive the total


current  that the digital circuit draws from the power supply.
This current is, in turn, embedded in the reduced model, which is
simulated to yield the substrate noise waveform. One big problem
with this methodology is that it may not capture the worst-case
noise pattern (when this pattern is not in the test-bench). Also, the
approach is too CPU-intensive to be practical for a full-chip analy-
sis. Another problem with some of these approaches [3, 15] is that
they do not consider package inductance and the associated power
supply noise. Also, the library module characterization carried out
in [3, 15] for the current waveform is not accurate, as it does not
take into account the gate output load and input slew. As we will
show in Figures 7 and 8, the current depends strongly on these two
parameters. [4, 5] also do not consider the dependency of noise
on the load at each gate. In [8] a time-series divided parasitic
capacitance model is proposed for time-domain power supply cur-
rent estimation. Pre-characterization technique for substrate noise
based on frequency domain analysis was presented in [12].
[7] presented a pattern-independent methodology (Figure 5)
suitable for chip-level designs that addresses some of these prob-
lems. It does not use any test-bench and is much faster than the
pattern-dependent flows. It is also based on deriving a reduced
model of the digital part of the design. The basic reduced model
of [4] (Figure 6) is used. It contains only passive circuit elements.
The presence of only passive elements and that too in a small num-
ber ensures that the circuit simulation is fast. The reduced model
consists of two parts: gate model and package model. The gate
model represents the digital gates of the circuit or block under
consideration. It contains a current source, internal capacitors and
resistors. Capacitors and resistors model transistors in the gates,
capacitance cells, and parasitics on the power/ground nets. In the
gate model, and  are the cumulative resistance and capac-
itance of transistors and wires in the block. is the average of
pull-up and pull-down turn-on resistances of the transistors. 
is the sum of all gate capacitances and wire loads in the block. 
and
 Vdd
0.06
RLC Mesh
load = 1fF
Package Model
0.05 load = 27fF
Gate Model Lvia, Rvia
0.04

I(VDD) (mA)
Substrate S
0.03
Local Vdd

Cnw
0.02
Cm Cc
Cp 0.01
Rsub
Rm Rc
I 0
Vsub
-0.01
0 200 400 600 800 1000 1200
Local Vss
TIME (ps)

  w.r.t. output load

Lvia, Rvia
Package Model Figure 7: Sensitivity of
RLC Mesh

Vss 0.06
slew = 100ps
0.05 slew = 800ps
Figure 6: Reduced model of a digital circuit with package [4, 7] 0.04

I(VDD) (mA)
0.03
0.02
the vacant areas in the layout to guard against the voltage drop. 
is the parasitic capacitance on power or ground nets.  is the 0.01
p-well substrate resistance.   is the junction capacitance be- 0
tween n-well and the substrate. The current source, , models the -0.01
total current drawn by the gates in the block from the power sup- -0.02
ply. The gate model is attached to the package model at local VDD
-0.03
and VSS. The package model is the same as that in the reference 0 200 400 600 800 1000 1200
model (Section 3.1). The reduced model is enhanced by modeling
TIME (ps)
more accurately the components that affect substrate noise more,
such as the current . First, a static timing analysis (STA) tool
generates the timing information for each gate, such as the min- Figure 8: Sensitivity of
  w.r.t. input slew
imum and maximum rise/fall arrival and transition times. This,
along with the switching activity information, is used by the cur-
rent waveform generation algorithm to construct the current wave- do not result in an output transition are ignored. In this case, even
form used in the reduced model. The current drawn by a single
switching digital gate  is modeled as  VDD  , where  is  though the magnitude of the current through the gate may be neg-

the capacitive load driven by  and  is the transition time at the
ligible, the presence of inductance may inject substantial substrate
noise.
output of  . Maximal sets of gates which can switch simultane- As a result, the discrepancy of LCB scheme vis-a-vis the refer-
ously are determined, leading to the computation of the maximum ence model can be up to 315% (Section 6).
current drawn from the power supply. This current is embedded
in the reduced model. The reduced model is simulated in SPICE
to yield the substrate noise voltage. Switching activities of various
blocks in the design are expected to be provided by the designer;
5 Module Current Characterization-
otherwise they may be deduced from a simulation test-bench. Let based (MCC) Scheme
us call the current modeling scheme of [7] load capacitance-based
(LCB). This scheme has several shortcomings. We propose an alternate scheme, the module current
1. It models the current for a switching cell as  VDD /  .   characterization-based (MCC) scheme. In this scheme,
This is an approximation of the actual charging current   we pre-characterize each library module for the current 

and can contribute significantly to the discrepancy. Also, does drawn from the power supply. This current is a function of the
not include the current through the NMOS when both NMOS and input value-pair vector  , the input slew vector 
 , and the output
PMOS are conducting. load. Previous work that uses library module characterization
2. The current waveform is initially modeled as a rectangular pulse only considered the dependence of the current on the input value
with magnitude . Later, after the current for the entire design is pairs, but not on output load and input slews [3, 15, 4, 5].
derived, the discontinuities are smoothed by replacing steps with
ramps. The impact of this approximation on
  noise could
be significant. 5.1 Accurate Module Current Model
3. LCB scheme only models switching at the output stage of a
To illustrate the dependence of the current drawn by a cell from the


cell. It ignores the current contribution of internal stages that are
switching. power supply   on the output load  , input slews   , and
4. Also, substrate noise contribution due to switching inputs that input value-pair vector  , we used an inverter from an industrial

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 0.16 ing HSPICE for a set of discrete input slews (½  ¾       ) and
0.14
A
B
output load values (½  ¾      ). Let   

  
  denote
0.12
the current waveform corresponding to the module  for an input
value-pair vector   , input slew vector  and output load  . Note
I(VDD) (mA)

0.1
that the time  is discretized as well, and the current value is stored
0.08 for each discrete time point.
0.06
0.04
5.3 Current Waveform Generation for a Gate
0.02
0 Assume we have a gate  in the design, driving a load  . Let 
be an instance of the library module . Let   denote the input
-0.02
0 200 400 600 800 1000 1200 value-pair vector at time  (with respect to the clock edge). For
TIME (ps)
simplicity, assume that only one input  of  makes a transition
with slew  . This information can be obtained by logic simula-
Figure 9: Sensitivity of
  w.r.t. input transition. Curve tion and timing analysis. We wish to compute   

     ,
 is for rising input and curve  for falling input. the current drawn by  from VDD as a function of time.
Let  lie between 
and 
·½ . Let  lie between 
and  ·½ . We derive   

     from the pre-computed

0.11 library. Figure 7 shows the dependence of   for the
 and pre-stored waveforms   


  
  ,    
  
·½   ,

inverter on the output load  of the inverter. Here, the inverter


  
  ·½ , and   
  

  
·½   ·½ using linear inter-
input has a rising transition with a slew (i.e., transition time) of polation.1 For simplicity, we write  for   , since only  makes
800ps. Two values of  are tried: 1fF, which generates solid curve a transition. Linear interpolation is performed for all discretized


for   and 27fF, which generates a dotted curve. From the time points in the characterization data. Then, we shift the re-


figure, we can see that the peak value of   is reduced by  sulting waveform   

     to the right by  to obtain the
almost a factor of 1.7, as  changes from 1fF to 27fF. desired current waveform.


Figure 8 shows the dependence of   on the input slew. 
Here,  is fixed at 1fF and the input makes a rising transition. We
tried two different slew values: 100ps and 800ps. The solid curve 5.4 Current Waveform Generation for a De-
is for slew of 100ps, and dotted curve for slew of 800ps. Not only sign


is the peak value of   different, but also the time at which
We now describe how the current waveform is generated for the
the peak happens and the shape (slope) of the waveform.
entire design. Since the mechanisms are different for pattern-
Finally, Figure 9 shows current waveforms with two different
dependent and pattern-independent methodologies, we describe
input transitions  (rising) and  (falling) with same slew of
them separately.
800ps and a fixed  of 27fF. The 4-fold difference in the peak
current and different peak times imply that we should characterize
current waveforms for each possible input value pair. 5.4.1 Pattern-dependent Methodology
These graphs show that if any of input slew, output load or input
value pairs are ignored while modeling the current, a substantial Given a sequence of input vectors, we use a logic simulator (VCS)
error will be incurred in the peak and slope of the current, both of to determine the logic value pair at each signal  in the design
which will affect the magnitude of the substrate noise, through as a function of time. The simulator also generates the signal ar-
and

 phenomena respectively. rival time at  whenever  makes a transition. The slew at 
is obtained using a static timing analysis tool (e.g., PrimeTime).
After obtaining the input value pairs, input slews and output load
5.2 Module Current Characterization for each gate  at each relevant arrival time, the current waveform
for  is generated using the method of Section 5.3. If multiple
Based on the above discussion, for a given library module, we
need to characterize the current drawn by it as a function of the
output load, input slews and value pairs at the inputs. We identify
the ranges of values (i.e., minimum and maximum values) for both
output load  and input slews   . A set of uniformly-spaced dis-
crete points is picked for each range. For instance, the output load
range is spanned by discrete points (½  ¾      ), and input slew
range by (½  ¾       ). For a given library module  with  in-
puts ½ through  , all possible input value pairs are generated.
Each input 
can either make a rising transition with slew 
or
falling transition with slew 
or stay constant. Multiple inputs
can make transitions. However, the transitions of all the switching
inputs are assumed to start at the same time. In other words, all
inputs of  are switching and have different arrival times, the av-
erage arrival time  is computed and used as described in Section
5.3. Finally, the current waveforms for all the gates in the design
are added up to yield the current drawn by the entire design from
the power supply.
5.4.2 Pattern-independent Methodology
In PIM, the basic approach is the same as in [7], except for the
current waveform generation algorithm. Based on the switching
activity, gates in the design are divided into two sets, depending
on their transition direction (i.e., rising or falling). The goal is to
generate the maximum (or worst-case) substrate noise. For each
overlapping transitions are adjusted such that the arrival times of
these transitions are aligned to start at the same time point, which
is the average of the overlapping arrival times. For each input
value-pair vector 

 , the current waveform  is generated us-
gate  , this is done by maximizing the voltage   at the BULK

1
If  is greater than  or less than ½ , or if  is greater than
 or less than ½ , we use extrapolation.

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 0.14
Non-Optimized
Optimized
0.12

0.1

0.08
I(VDD) (mA)

Tech. Lib Layout SPICE

.lib Information PIN locations
Library
0.06
Library Pre−Characterization

0.04

0.02 SPICE
Run PrimeTime Library
To obtain pin/wire
0 loads

-0.02
0 0.05 0.1 0.15 0.2 no Library
Layout Info Available Characterization
TIME (ns)
yes
Estimate Size

Figure 10: Accuracy of storage-optimized current waveform

1. Calculation of Rm and Cm values Library

 


2. Calculation of Cnw and Rsub values Characterization
3. Parasitic Power to Ground cap
node  of  :    
   , where and
are 4. Calculation of Decoupling caps
5. Obtain current waveform
Data

the effective resistance and inductance of the via and the package using module characterization data


(Figure 2). Note that   can be computed if   is known.



  will be known if the input value pairs, input slews and out- no

put load of  are known. The minimum and maximum input slew With Package

values are taken from the static timing analyzer. The output load yes

is known from the design and the layout. To determine the input Create Package

value pairs, we consider all combinations that result in the desired

output transition at  . For instance, assume that an OR gate  with SPICE file

inputs ½ and ¾ is making a rising transition in the circuit. This

can correspond to either ½ 
and ¾ rising, or ¾ and 
½ rising, or both ½ and ¾ rising. We restrict ourselves to only
those pre-characterized current waveforms for the library module Figure 11: Flow for creating MCC reduced model
of  which correspond to these three input value pairs. We se-
lect the waveform which maximizes the objective function   .
Once the current waveform for each gate is known, the circuit cur-
rent is computed by summing up the gate waveforms.
6 Simulation Results
6.1 Module Current Characterization
We characterize all modules in the technology library for current.
Note that this characterization needs to be done once for a given
library. We used four discrete values for output load capacitance:
1fF, 27fF, 81fF, and 162fF; and two values for slew: 100ps and
800ps. These values were picked after studying the characteristics
of several circuits designed in the 0.11 Fujitsu technology. Fi-
nally, for a given library module, all possible input value-pairs are
used. HSPICE is run for each combination to measure the current
drawn from VDD. The resulting current waveform (as a function
of discrete time points) is then stored. This procedure is repeated
for each library module.
One problem with a straightforward implementation of the
above methodology is that huge amount of disk space is needed
to store the characterization data for the entire library. To optimize
the storage requirements, we approximate the original HSPICE
waveform by selecting only a subset of the discrete time points.
The selected points satisfy one of the following two conditions:
1) The difference in the current values at the time point and the
previous time point is at least 50%; 2) The difference in the slopes
of the present line segment and the previous segment is at least
20%. This technique could reduce the disk requirement by more
than a factor of 3. For instance, for an inverter, the disk space
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necessary to store all the waveforms before any optimization was
26KB. With optimization, the disk space needed got reduced to
8KB. Figure 10 shows the original and the storage-optimized cur-
rent waveforms for an inverter for falling transition at the input. It
can be seen that the two waveforms are almost identical.
6.2 Substrate Noise
In this section, we demonstrate the accuracy of the reduced model
of Figure 6, where is computed using the MCC scheme. We
compare the reduced model with the reference model of Figure
2 with respect to the substrate noise. Since reference models for
large circuits cannot be simulated due to exorbitant CPU times, the
reduced model can only be validated for relatively small circuits.
We generated several adder circuits, with sizes ranging from about
50 to 1000 gates. The target technology is 0.11, with VDD
= 1.2V. For each circuit, the reference and reduced models were
generated automatically with programs we have developed. Since
these are small designs, the resistances between BULK nodes were
set to zero, thereby merging them into one. It is at this node that
the substrate voltage was measured for the design. The flow-chart
for creating the reduced model is shown in Figure 11. To study the
impact of the package, the software has an option to include or ex-
clude the package model in the noise model. For the experiments
reported here, the noise models include the package model.
 ckt gate Noise (mV) CPU (sec)
cnt ref red %  ref red speed-up
model-gen sim total VCS model-gen sim total
c1 58 3.11
-4.30 2.98 20 47.86 67.86 3.8 31 12.96 47.76 1.4
c2 97 4.80
6.98 5.14 20 62.94 82.94 3.6 36 13.42 53.02 1.6
c3 201 10.62
-3.88 10.21 20 124.16 144.16 3.5 52 13.30 68.8 2.1
c4 409 23.13
-4.70 22.04 21 265.56 286.56 3.9 83 13.64 100.54 2.9
c5 617 32.38
-1.17 32.00 22 422.03 444.03 4.2 114 13.59 131.79 3.4
c6 825 39.37
6.88 42.08 23 599.90 622.9 4.4 144 13.91 162.31 3.8
c7 929 44.01
3.75 45.66 23 673.88 696.88 4.6 159 13.83 177.43 3.9
avg  4.52
Noise: peak-to-peak substrate voltage; ref: reference model; red: MCC reduced model
 
Noise % = Noise(red) Noise(ref)
Noise(ref)  
CPU model-gen: time to generate HSPICE model; CPU sim: time to simulate HSPICE model
CPU VCS: time to run VCS & get value pairs and arrival times; CPU speed-up = total CPU(ref)/total CPU(MCC red)

Table 1: Substrate noise results for MCC scheme in PDM

3 2.5
REF REF
MCC MCC
2.5 2

1.5
2

V(SBULK) (mV)
1
I(VDD) (mA)

1.5
0.5
1
0
0.5
-0.5

0 -1

-0.5 -1.5
4 4.2 4.4 4.6 4.8 5 4 4.2 4.4 4.6 4.8 5
TIME (ns) TIME (ns)

Figure 12: Current waveforms for 5-bit adder (c1): reference Figure 13: Substrate noise waveforms for 5-bit adder (c1): ref-
model vs. MCC reduced model erence model vs. MCC reduced model

6.2.1 Pattern-dependent Methodology

Table 1 shows results for the pattern-dependent methodology. For
each circuit, both reference and reduced models were simulated
with a test-bench which included less than 10 vectors. The peak-
to-peak substrate voltage over the entire test-bench was measured
and compared. The table shows the name of the circuit, the num-
ber of gates, and the peak-to-peak substrate noise using the refer-
ence model (column ref) and the reduced model (column red). The
percentage discrepancy between the reference and reduced models
with respect to the peak noise is shown in the last column (% ).

The maximum absolute is 6.98%. That is very encouraging and
shows that the new reduced model is indeed very accurate.
Figures 12 and 13 show the results of applying MCC scheme
for a 5-bit adder circuit (c1 in Table 1). Figure 12 shows the cur-
rent waveform through VDD for the reference model and also the
current waveform that is obtained through MCC scheme. It can
be seen that the two waveforms match very well, both in terms
of the maximum value and the shape (including the slope). One
cause of mismatches is the error due to linear interpolation. The
corresponding substrate noise waveforms at the BULK nodes are
shown in Figure 13. The solid curve is for the reference model and
the dotted line curve for the MCC reduced model.
Table 1 also shows the CPU times and their break-up for the ref-
erence and reduced models. The model generation time is almost
constant for the reference model, whereas for the MCC reduced
model, it increases with the circuit size. This is because the cur-
rent drawn from VDD is computed for each gate in MCC scheme.
On the other hand, the HSPICE simulation time increases with the
circuit size for the reference model, whereas it is almost constant
 for MCC reduced model. HSPICE simulation time is a function
of the model size. The reference model size is linear in the size of
the circuit, whereas the MCC reduced model size is independent
of the circuit size. As for the overall speed-up, it is in the range 1.4
to 3.9. We expect it to increase with the circuit size, since the sim-
ulation time for the reference model grows faster than the model
generation time for the MCC reduced model.
Although not reported in Table 1, we also simulated the refer-
ence model of the circuits without the package model. The peak-
to-peak substrate voltage was found to be, on average, 9% smaller
than when the package is included. The maximum difference was
about 15% (for c7).

Proceedings of the 19th International Conference on VLSI Design (VLSID’06)

1063-9667/06 $20.00 © 2006 IEEE
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1063-9667/06 $20.00 © 2006 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:41 from IEEE Xplore. Restrictions apply.