Design and Implementation of Low Power High Speed VLSI DSP System For Multirate Polyphase Interpolator

International Journal of Ethics in Engineering & Management Education
Website: www.ijeee.in (ISSN: 2348-4748, Volume 1, Issue 5, May2014)

221

Design and Implementation of Low Power High
Speed VLSI DSP System for Multirate Polyphase
Interpolator

Rajendra M. Rewatkar
1
Department of Electronics Engineering
1
Datta Meghe Institute of Engineering Technology and
Research, Sawangi (Meghe), Wardha-India.
rajendra.rewatkar@gmail.com

Dr. Sanjay L. Badjate
2
2
Department of Electronics and communication Engineering
S.B. Jain Institute of Engineering, Management and
Research, Nagpur-India
s_badjate@rediffmail.com

Abstract: Interpolator is an important sampling device used for
Multirate filtering to provide signal processing in wireless
communication system. There are many applications in which
sampling rate must be changed. Recent advances in mobile
computing and communication applications demand low power
and high speed VLSI DSP systems. In this paper, an efficient
method has been presented to implement low power high speed
Multirate Polyphase Interpolator for wireless communication
systems. Many architecture developed for the design of low
complexity, bit parallel Multiple Constant Multiplications
operation which dominates the complexity of DSP systems.
However, major drawbacks of present approaches are either too
costly or not efficient enough. On the other hand, MCM and
digit-serial adder offer alternative low complexity designs, since
digit-serial architecture occupy less area and are independent of
the data word length. Multiple Constant Multiplications is
efficient way to reduce the number of addition and subtraction in
polyphase filter implementation. The simulation of parameters is
analyzed by using synopsis 45 nm and Xilinx. Experimental
results have shown the efficiency of the proposed technique and
the analysis of different architecture. This Multirate design
methodology is systematic and applicable to many problems.

Keywords: VLSI-Very large scale integrated circuit, VHDL-Very
high speed hardware description language, DSP-Digital Signal
Processing, FIR: Finite impulse response, FPGA: Field
Programmable gate array, MCM-Multiple Constant
Multiplication

I.INTRODUCTION:
In many practical application of DSP, there is a problem of
changing the sampling rate of a signal, either increasing or
decreasing by some amount. Telecommunication system
transmits and receives the different types of signals. There is a
requirement to process the various signals at the different rates
with corresponding bandwidth. A System that employs
multiple sampling rates in the processing of digital signals
called as Multirate digital signal processing system. In most
applications Multirate systems are used to improve the
performance and increased computational efficiency [2]. The
two basic operations in a Multirate system are decimation and
interpolation. The Multirate techniques are included to reduce
the computational complexity. The role of a filter in
decimation and interpolation is to suppress aliasing and to
remove imaging. Digital Signal Processing has become
essential to the design and implementation of high
Performance audio, video, multi-media, and communication
systems. Interpolator is utilized to increase the sampling rate
as shown in following Figure.

Fig.1.Block diagram representation of Interpolator

The efficiency of FIR filters for sampling rate conversion is
significantly improved using the Polyphase realization.
Filtering is embedded in the interpolation process and a
polyphase structure is used to simultaneously achieve the
interpolation by a given factor but running at a low data rate
[6].

Fig.2 (a-b) Block diagram representation of Polyphase Interpolator
International Journal of
Website: www.ijeee.in (ISSN: 2348

The FIR filter performs the weighted summation of input
sequence and is widely used in mobile communication
systems for channelization, channel equaliza
shaping and matched filtering due to their properties of linear
phase and absolute stability [9]. In Interpolation Multirate
filters, the normalized transition bandwidth inversely relates to
the interpolation factor L. The order of an interpola
increases as L. Polyphase is a way of doing sampling rate
conversion that leads to very efficient implementations.
Sampling rate reduction is required for efficient transmission,
and a sampling rate increase is required for the regeneration of
the speech. It can be efficiently implemented using finite
impulse response digital filters [11].It is found that efficient
implementations of low pass FIR filters could be obtained by a
process of first reducing the sampling rate, filtering, and then
increasing the sampling rate back to the original frequency.
FIR based filtering is advantageous in many digital signal
processing systems due to the possibility of exact linear phase
and freedom of stability problems. Recently, several schemes
have been proposed to reduce the arithmetic complexity of
FIR structures, e.g., sub expression sharing, multiple
multiplication and multiplier blocks [1][4].

II. DESIGN METHODOLOGY:

The digital filters employed in mobile systems must be
higher order and realized to consume less power at high speed.
Low power, High performance is two most important criteria
for many signal processing system designs. Particularly, real
time multimedia applications; there have been many
approaches to achieve this goal at different implementation
level. We have introduced a new architecture based low power
and high performance design technique. i.e. Multirate
approach and combine it along with DSP techniq
shifting, carry look ahead and folding to design several DSP
blocks like FIR and Polyphase filtering. In this paper, we
design Multirate Polyphase Interpolator in direct form,
transposed form, using MCM and Digit serial adder.
in Fig. 1, the hardware block called a multiplier block is used
to implement all coefficient multiplications. The concept of
the multiplier block is significant in both terms of
area and power because some adders and shifters can be
shared among different multiplications [6].
Fig. 3(a-b) FIR Filter structure (a) General transposed form
(b) Multiplications are replaced by a multiplier block
The digit-serial MCM operation in shift
consists of digit-serial addition and subtraction operations, and
D flip-flops for the shift operations, as opposed to the bit

Ethics in Engineering & Management Education
Website: www.ijeee.in (ISSN: 2348-4748, Volume 1, Issue 5, May
222
The FIR filter performs the weighted summation of input
sequence and is widely used in mobile communication
systems for channelization, channel equalization, pulse
shaping and matched filtering due to their properties of linear
phase and absolute stability [9]. In Interpolation Multirate
filters, the normalized transition bandwidth inversely relates to
. The order of an interpolation filter
Polyphase is a way of doing sampling rate
conversion that leads to very efficient implementations.
Sampling rate reduction is required for efficient transmission,
and a sampling rate increase is required for the regeneration of
the speech. It can be efficiently implemented using finite
impulse response digital filters [11].It is found that efficient
implementations of low pass FIR filters could be obtained by a
process of first reducing the sampling rate, filtering, and then
easing the sampling rate back to the original frequency.
FIR based filtering is advantageous in many digital signal
processing systems due to the possibility of exact linear phase
and freedom of stability problems. Recently, several schemes
sed to reduce the arithmetic complexity of
FIR structures, e.g., sub expression sharing, multiple-constant

II. DESIGN METHODOLOGY:
The digital filters employed in mobile systems must be
higher order and realized to consume less power at high speed.
Low power, High performance is two most important criteria
for many signal processing system designs. Particularly, real
applications; there have been many
approaches to achieve this goal at different implementation
level. We have introduced a new architecture based low power
and high performance design technique. i.e. Multirate
approach and combine it along with DSP techniques such as
shifting, carry look ahead and folding to design several DSP
Polyphase filtering. In this paper, we
design Multirate Polyphase Interpolator in direct form,
transposed form, using MCM and Digit serial adder. As shown
1, the hardware block called a multiplier block is used
to implement all coefficient multiplications. The concept of
significant in both terms of
area and power because some adders and shifters can be

b) FIR Filter structure (a) General transposed form
(b) Multiplications are replaced by a multiplier block
serial MCM operation in shift-add architecture
serial addition and subtraction operations, and
the shift operations, as opposed to the bit-
parallel MCM operation, where shifts are free in terms of
hardware. The complexity of the resulting realization will be
depending on three factors. First, the size, numbers, and type
of MCM blocks. Second, the n
finally the number of structural additions, i.e., the additions
that are not part of the MCM block [10]. Another concept can
be used to optimize the parameters is multiplication using
shifts, additions, and subtractions realiz
multipliers. The number of additions and subtractions can be
significantly reduced by using common partial results. As
additions and subtractions have similar complexity as
example [7], consider the constant multiplications 29
43x. Observe from Figure 4 that the sharing of partial products
3x and 5x reduces the number of operations from 6 to 4. The
decompositions of 29x and 43x

29x = (11101)
bin
x = x<<4+x<<
43x = (101011)
bin
x = x<<5+x<<

29X

43
Fig. 4. Shift add implementation of 29
sharing (b) with partial product sharing
Ethics in Engineering & Management Education
May2014)

parallel MCM operation, where shifts are free in terms of
hardware. The complexity of the resulting realization will be
depending on three factors. First, the size, numbers, and type
of MCM blocks. Second, the number of delay elements, and,
finally the number of structural additions, i.e., the additions
that are not part of the MCM block [10]. Another concept can
be used to optimize the parameters is multiplication using
additions, and subtractions realization without general
of additions and subtractions can be
significantly reduced by using common partial results. As
additions and subtractions have similar complexity as an
consider the constant multiplications 29x and
. Observe from Figure 4 that the sharing of partial products
3x and 5x reduces the number of operations from 6 to 4. The
x in binary are listed as follows:
<<3+x<<2+x ------ (I)
<<3+x<<1+x ----- (II)

43X

43 x

Fig. 4. Shift add implementation of 29x and 43x (a) without partial product
sharing (b) with partial product sharing


223

The problem of designing Polyphase interpolator has received
a great attention due to large number of multiplications. This
implementation must satisfy the enforced sampling rate
constraints of the real time DSP applications and must require
less space and power consumption. Present works have
focused on design of Multirate Polyphase interpolator by
filters, data generator latches and adder. As the coefficients of
an application specific filter are constant, the decomposition is
more efficient than employing multipliers [6]. The complexity
of FIR filters in this case is dominated by the number of
additions and multiplications [10]. The multiplier block of the
digital FIR lter in its direct form is implemented in the design
so that signicant impact on the complexity and performance
of the design will be improved. Also, Polyphase interpolator is
designed using MCM and digit serial adders which overcome
problem of complexity, design performance and producing
very low area [20]. Authors have used the above mentioned
techniques to reduce the complexity in the design. In this,
Polyphase interpolator filter with a factor of 18 is designed
using three cascaded filters. The impulse response is obtained
by convolution of three vectors with 18 ones in each, The
trade-off between additions and delay elements is circuit and
technology dependent, and, hence, should be evaluated on the
circuit level. Digit serial systems have become attractive for
digital designers in the recent years. These systems process
multiple bits of the input word, referred to as the digit size, in
one clock cycle. For a digit size of unity, the system reduces to
a bit serial, and for a digit size equal to the word length, the
system reduces to a bit parallel system. It process one whole
word of the input sample in one clock cycle, are ideal for high
speed applications [16].

III.RESULT:
I] Following figure 5(a) (d) shows direct form of Polyphase
Interpolator which uses latches in direct form, this system is
very efficient because it required very less power dissipation
and maintaining higher speed. But, this design consumed more
area.

Fig. 5(a) RTL view of Polyphase Interpolator in direct form

Fig. 5(b) Internal structure of polyphase filter
c
lkc(31:0)
r
s
t b(31:0)
h
0
(
7
:
0
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h
1
2
(
7
:
0
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h
1
5
(
7
:
0
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h
3
(
7
:
0
)
h
6
(
7
:
0
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h
9
(
7
:
0
)
x(7:0)
U1
ddfb0
c
lkc(31: 0)
r
s
t b(31: 0)
h
1
(
7
:
0
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h
1
0
(
7
:
0
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h
1
3
(
7
:
0
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h
1
6
(
7
:
0
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h
4
(
7
:
0
)
h
7
(
7
:
0
)
x(7:0)
U2
ddfb1
c
lkc(31:0)
r
s
t b(31:0)
h
1
1
(
7
:
0
)
h
1
4
(
7
:
0
)
h
1
7
(
7
:
0
)
h
2
(
7
:
0
)
h
5
(
7
:
0
)
h
8
(
7
:
0
)
x(7:0)
U3
ddfb2
eresult(31:0)
h0(7:0)
h1(7:0)
h2(7:0)
h3(7:0)
h4(7:0)
h5(7:0)
h6(7:0)
h7(7:0)
h8(7:0)
h9(7:0)
h10(7:0)
h11(7:0)
h12(7:0)
h13(7:0)
h14(7:0)
h15(7:0)
h16(7:0)
h17(7:0)
U5
con_coeff
clk
rst
d(31: 0) q(31:0) c
lk
r
s
t
U8 latch32
a(31:0) d(31: 0)
b(31:0)
c(31:0)
U6
adder3231
c0(31:0)
d(31: 0) q(31:0) c
lk
r
s
t
U9 latch32
d(31: 0) q(31:0) c
lk
r
s
t
U10 latch32
clk
filt erclk
rst
upclk
xout(7:0)
zin
U4
datagen_udf1
A(31:0) Y(31:0)
s
e
l
U7 mux321
A(31:0) Y(31:0)
s
e
l
U11 mux321
A(31:0) Y(31:0)
s
e
l
U12 mux321
d(31:0) q(31: 0) c
lk
r
s
t
U13 latch32
d(31:0) q(31: 0) c
lk
r
s
t
U14 latch32
d(31:0) q(31: 0) c
lk
r
s
t
U15 latch32
x(7:0)
h12(7:0) h9(7:0) h15(7:0)
b(31:0)
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:
0
)
U
4
m
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t
i
1
6
a
(
7
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c
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1
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(
7
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5
m
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1
6
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7
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c
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1
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7
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6
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1
6
a
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7
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3
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1
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a
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(
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1
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a
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c
(
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b
(
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2
m
u
l
t
i
1
6
BUS7626(15:0)
BUS8689(32:0)
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U31
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U32
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U33
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U34
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U35
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U26
adder1431
d(7:0) q(7:0)
c
l
k
r
s
t
U37
latch
d(7:0) q(7:0)
c
l
k
r
s
t
U38
latch
d(7:0) q(7:0)
c
l
k
r
s
t
U39
latch
d(7:0) q(7:0)
c
l
k
r
s
t
U40
latch
d(7:0) q(7:0)
c
l
k
r
s
t
U41
latch
d(7:0) q(7:0)
c
l
k
r
s
t
U42
latch
rst
clk
h0(7:0) h3(7:0) h6(7:0)
c(31:0)


224

Fig.5(c) Design waveform
Fig.5 (d) Design vision schematic of direct form interpolator
II] Following figure 6(a)-(d) shows transpose form of
Polyphase Interpolator. This design uses latches in transpose
form. Therefore, this system also required more area
maintaining moderate power dissipation and speed.

Fig. 6(a).Multirate Polyphase Interpolator in Transpose form

eresult (31:0)
h0(7:0)
h1(7:0)
h2(7:0)
h3(7:0)
h4(7:0)
h5(7:0)
h6(7:0)
h7(7:0)
h8(7:0)
h9(7:0)
h10(7:0)
h11(7:0)
h12(7:0)
h13(7:0)
h14(7:0)
h15(7:0)
h16(7:0)
h17(7:0)
U5
con_coeff
c
lkc(31: 0)
r
s
t
b(31: 0)
h
0
(
7
:
0
)
h
1
2
(
7
:
0
)
h
1
5
(
7
:
0
)
h
3
(
7
:
0
)
h
6
(
7
:
0
)
h
9
(
7
:
0
)
x(7:0)
U1
dtfb0
c
lkc(31: 0)
r
s
t b(31:0)
h
1
(
7
:
0
)
h
1
0
(
7
:
0
)
h
1
3
(
7
:
0
)
h
1
6
(
7
:
0
)
h
4
(
7
:
0
)
h
7
(
7
:
0
)
x(7:0)
U2
dtfb1
c
lkc(31:0)
r
s
t
b(31:0)
h
1
1
(
7
:
0
)
h
1
4
(
7
:
0
)
h
1
7
(
7
:
0
)
h
2
(
7
:
0
)
h
5
(
7
:
0
)
h
8
(
7
:
0
)
x(7:0)
U3
dtfb2
clk
rst
d(31:0) q(31:0) c
lk
r
s
t
U8 latch32
a(31:0) d(31:0)
b(31:0)
c(31:0)
U6
adder3231
c0(31:0)
d(31:0) q(31: 0) c
lk
r
s
t
U9 latch32
d(31:0) q(31:0) c
lk
r
s
t
U10 latch32
clk
filterclk
rst
upclk
xout(7:0)
zin
U4
datagen_udf1
A(31: 0) Y(31:0)
s
e
l
U7 mux321
A(31: 0) Y(31:0)
s
e
l
U11 mux321
A(31: 0) Y(31:0)
s
e
l
U12 mux321
d(31:0) q(31:0) c
lk
r
s
t
U13 l atch32
d(31:0) q(31:0) c
lk
r
s
t
U14 l atch32
d(31:0) q(31:0) c
lk
r
s
t
U15 l atch32
x(7:0)
h12(7:0) h9(7:0) h15(7:0)
b(31:0)
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
4
m
u
l
t
i
1
6
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
5
m
u
l
t
i
1
6
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
6
m
u
l
t
i
1
6
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
3
m
u
l
t
i
1
6
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
1
m
u
l
t
i
1
6
a
(
7
:
0
)
c
(
1
3
:
0
)
b
(
7
:0
)
U
2
m
u
l
t
i
1
6
BUS7626(15:0)
BUS8689(32:0)
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U31
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U32
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U33
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U34
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U35
adder1431
a
(
1
3
:
0
)
c(31:0)
b(31:0)
U26
adder1431
rst
clk
h0(7:0) h3(7:0) h6(7:0)
c(31:0) d(31:0) q(31:0) c
lk
r
s
t
U7 latch32
d(31:0) q(31:0) c
lk
r
s
t
U8 latch32
d(31:0) q(31:0) c
lk
r
s
t
U9 latch32
d(31:0) q(31:0) c
lk
r
s
t
U10 latch32
d(31:0) q(31:0) c
lk
r
s
t
U11 latch32
d(7:0) q(7:0)
c
lk
r
s
t
U37
latch


225


Fig.6(d) Design vision schematic of Polyphase Interpolator in Transpose
form
III] Authors efforts are directed towards reduction of area at
great extend succeeded by using MCM of Multirate Polyphase
Interpolator. This design consumed moderate power.

Fig. 7(a).Multirate Polyphase Interpolator using multiple constant
multiplications

clk
rst
d(31:0)
q(31:0) c
l
k
r
s
t
U8
latch32
a(31:0) d(31:0)
b(31:0)
c(31:0)
U6
adder3231
c0(31:0)
d(31:0)
q(31:0) c
l
k
r
s
t
U9
latch32
d(31:0)
q(31:0) c
l
k
r
s
t
U10
l atch32
clk
filterclk
rst
upclk
xout(7:0)
zin
U4
datagen_udf1
A( 31:0) Y(31:0)
s
e
l
U7
mux321
A(31:0) Y(31:0)
s
e
l
U11
mux321
A(31:0) Y(31:0)
s
e
l
U12
mux321
d( 31:0)
q(31:0) c
l
k
r
s
t
U13
latch32
d( 31:0)
q(31:0) c
l
k
r
s
t
U14
latch32
d( 31:0)
q(31:0) c
l
k
r
s
t
U15
latch32
c
l
k
c(31:0)
r
s
t b( 31:0)
x(7:0)
U3
dmcmb0
c
l
k
c(31:0)
r
s
t b(31:0)
x(7:0)
U1
dmcmb1
c
l
k
c(31:0)
r
s
t b(31:0)
x(7:0)
U2
dmcmb2
Y(31:0)
U5
contout321
x(7:0)
b(31:0)
BUS8689(32:0)
a
(1
3
:0
)
c(31:0)
b(31:0)
U31
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U32
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U33
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U34
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U35
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U26
adder1431
rst
clk
c(31:0) d(31:0) q(31:0) c
lk
rs
t
U7 l atch32
d(31:0) q(31:0) c
lk
rs
t
U8 latch32
d(31:0) q(31:0) c
lk
rs
t
U9 latch32
d(31:0) q(31:0) c
lk
rs
t
U10 latch32
d(7:0) q(7:0)
c
lk
rs
t
d(31:0) q(31:0) c
lk
rs
t
U11 latch32
U37
latch
a
(7
:0
)
y
(1
3
:0
)
U
7
5
m
u
l
h
0
a
(7
:0
)
y
(1
3
:0
)
U
7
8
m
u
l
h
3
a
(7
:0
)
y
(1
3
:0
)
U
7
6
m
u
l
h
4
a
(7
:0
)
y
(1
3
:0
)
U
7
7
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
7
9
m
u
l
h
2
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
l
b
y
1
x(7:0)
b(31:0)
BUS7626(15:0)
BUS8689(32:0)
a
(1
3
:0
)
c(31:0)
b(31:0)
U31
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U32
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U33
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U34
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U35
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U26
adder1431
d(7:0) q(7:0)
c
lk
rs
t
U37
latch
rst
clk
c(31:0) d(31:0) q(31:0) c
lk
rs
t
U7 l atch32
d(31:0) q(31:0) c
lk
rs
t
U8 latch32
d(31:0) q(31:0) c
lk
rs
t
U9 latch32
d(31:0) q(31:0) c
lk
rs
t
U10 latch32
d(31:0) q(31:0) c
lk
rs
t
U11 latch32
a
(7
:0
)
y
(1
3
:0
)
U
7
7
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
7
8
m
u
l
h
3
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
2
m
u
l
h
0
x(7:0)
b(31:0)
BUS8689(32:0)
a
(1
3
:0
)
c(31:0)
b(31:0)
U31
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U32
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U33
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U34
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U35
adder1431
a
(1
3
:0
)
c(31:0)
b(31:0)
U26
adder1431
d(7:0) q(7:0)
c
lk
rs
t
U37
latch
rst
clk
c(31:0) d(31:0) q(31:0) c
lk
rs
t
U7 l atch32
d(31:0) q(31:0) c
lk
rs
t
U8 latch32
d(31:0) q(31:0) c
lk
rs
t
U9 latch32
d(31:0) q(31:0) c
lk
rs
t
U10 l atch32
d(31:0) q(31:0) c
lk
rs
t
U11 latch32
a
(7
:0
)
y
(1
3
:0
)
U
7
9
m
u
lh
2
a
(7
:0
)
y
(1
3
:0
)
U
7
7
m
u
lh
1
a
(7
:0
)
y
(1
3
:0
)
U
7
6
m
u
lh
4
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
lb
y
1
a
(7
:0
)
y
(1
3
:0
)
U
3
m
u
lh
0
a
(7
:0
)
y
(1
3
:0
)
U
4
m
u
lh
3


226


Fig.7(d) Design vision schematic of polyphase Interpolator using multiple
constant multiplication
IV] Following figure 8(a)-(d) shows transpose form of
Polyphase Interpolator which uses MCM & digit serial adder.
This system required less area and maintaining higher speed.

Fig. 8(a) Multirate Polyphase Interpolator using MCM & Digit
serial adder

c
l
k
c( 31:0)
c
l
k
s
h
l
o
a
d
r
s
t
s
e
l
s
e
l
_
s
u
m
c
o
u
t
b(31:0)
s
e
l
b
it
s
(
3
:
0
)
x(7:0)
U16
dmcmdsb0
c
l
k
c(31:0)
c
l
k
s
h
l
o
a
d
r
s
t
s
e
l
s
e
l
_
s
u
m
c
o
u
t
b( 31:0)
s
e
l
b
it
s
(
3
:
0
)
x(7:0)
U17
dmcmdsb1
c
l
k
c(31:0)
c
l
k
s
h
l
o
a
d
r
s
t
s
e
l
s
e
l
_
s
u
m
c
o
u
t
b( 31:0)
s
e
l
b
it
s
(
3
:
0
)
x(7:0)
U18
dmcmdsb2
rst
clk
c
lk
adderclk
r st
clksh
load
sel
sel_sumcount
selbits(3:0)
U54
adderfsm1
a
y b
sel
U38
mux211
Y(31:0)
U19
contout321
clk
sout(7:0)
r
s
t
U1
datadumpgen2
clk upclk
r st zin
U2
clkseq2
d(31:0) q(31:0) c
l
k
r
s
t
U8
l atch32
a(31:0) d(31:0)
b(31:0)
c(31:0)
U6
adder3231
c0(31:0)
d(31:0) q(31:0) c
l
k
r
s
t
U9
latch32
d(31:0)
q(31:0) c
l
k
r
s
t
U10
latch32
A(31:0) Y( 31:0)
s
e
l
U7
mux321
A(31:0) Y(31:0)
s
e
l
U11
mux321
A(31:0) Y(31:0)
s
e
l
U12 mux321
d(31:0) q(31:0) c
l
k
r
s
t
U13
latch32
d(31:0)
q(31:0) c
l
k
r
s
t
U14
latch32
d(31:0)
q(31:0) c
l
k
r
s
t
U15
latch32
x(7:0)
c(31:0)
a
(7
:0
)
y
(1
3
:0
)
a
(7
:0
)
y
(1
3
:0
)
a
(7
:0
)
y
(1
3
:0
)
a
(7
:0
)
y
(1
3
:0
)
a
(7
:0
)
y
(1
3
:0
)
U
7
5
m
u
l
h
0
U
7
8
m
u
l
h
3
U
7
6
m
u
l
h
4
U
7
7
m
u
l
h
1
U
7
9
m
u
l
h
2
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
l
b
y
1
b(31:0)
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U18
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U19
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U20
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U21
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U22
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U23
a
d
d
e
r
m
o
d
i
1
clk
rst
sel_sumcout
sel
load
clksh
selbits(3:0)
x(7:0)
c(31:0) b(31:0)
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U18
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U19
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U20
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U21
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U22
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U23
a
d
d
e
r
m
o
d
i
1
clk
rst
sel_sumcout
sel
load
clksh
selbits(3:0)
a
(7
:0
)
y
(1
3
:0
)
U
7
7
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
7
8
m
u
l
h
3
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
2
m
u
l
h
0


227

Fig.8 (b) Internal structure of Polyphase Filter

Fig.8(d) Design vision schematic of Polyphase Interpolator using MCM
and digit serial adder
The Multirate Polyphase Interpolator is implemented on
FPGA cyclone II device which shown complete setup of the
design as follows:

Fig. 9 Complete set up of design of Multirate Polyphase Interpolator
showing output 10011100101
TABLE 1

Type
Area[um
2
]
Power
(uw)
Speed
(MHz)
Direct Form 31921 113 205.634
Transpose Form 37511 222 106.315
Using MCM 14747 220 103.189
Using MCM and
Digit Serial Adder 23178 413 151.579

Following graphs shown comparative analysis of parameters
of Multirate Polyphase Interpolator using different techniques
x(7:0)
c(31:0) b(31:0)
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U18
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U19
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U20
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U21
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U22
a
d
d
e
r
m
o
d
i
1
c
lk
dout(31:0)
c
lk
s
h
lo
a
d
rs
t
s
e
l
s
e
l_
s
u
m
c
o
u
t
O1(31:0)
O
2
(1
3
:0
)
s
e
lb
its
(3
:0
)
U23
a
d
d
e
r
m
o
d
i
1
clk
rst
sel_sumcout
sel
load
clksh
selbits(3:0)
a
(7
:0
)
y
(1
3
:0
)
U
7
9
m
u
l
h
2
a
(7
:0
)
y
(1
3
:0
)
U
7
7
m
u
l
h
1
a
(7
:0
)
y
(1
3
:0
)
U
7
6
m
u
l
h
4
a
(7
:0
)
y
(1
3
:0
)
U
1
m
u
l
b
y
1
a
(7
:0
)
y
(1
3
:0
)
U
3
m
u
l
h
0
a
(7
:0
)
y
(1
3
:0
)
U
4
m
u
l
h
3


228

Graph 1

Graph 2

Graph 3

Graph 4
0
5000
10000
15000
20000
25000
30000
35000
40000
Area[um
2
]
area[um^2]
0
50
100
150
200
250
300
350
400
450
Power[uW]
power[uW]
0
50
100
150
200
250
Speed [MHz]
speed [MHz]
0
5000
10000
15000
20000
25000
30000
35000
Area[um^2]
power[uW]
speed [MHz]


229

IV.CONCLUSION:

Authors have presented the different optimization techniques
and methodology for Multirate Polyphase Interpolator. We
have used Active-HDL and Quartus-II for the simulation and
done the synthesis of the design on FPGA platform. The
parameters are analyzed by using synopsis 45 nm and Xilinx
software. Multirate Polyphase Interpolator is designed in its
direct form, Transpose form, using MCM and using Digit
serial adder which provides power, area and speed for system.
The results are given separately and comparison in tabulation
form found satisfactory. Physical testing verified that
implementation worked correctly. MCM and digit serial adder
technique reduces the area of the system to a great extent and
overcome problem of complexity, design performance. Direct
form of Multirate Polyphase Interpolator is best suited for
implementation of DSP system which requires very less power
dissipation maintaining higher speed. The proposed
methodology provides a systematic way to derive low power,
high speed system.

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