LAYOUT DESIGN OF CASCODE CURRENT

MIRROR WITH IMPROVED CURRENT

MISMATCH

D. Dhawan
1
D. Boolchandani
2
V. Sahula
2


Abstract
The performance of analog Metal-Oxide-Semiconductor (MOS) integrated circuits
depends heavily upon the element of matching accuracy. Matching accuracy of current
mirror is especially important in analog IC performance. Layout techniques and device
size are believed to be the major factors that can improve the matching behavior to a
large extent. Though this information is important, there have been limited studies or
research done on these two factors. In this paper, we propose a new layout technique for
cascode current mirror based on proposal of Lan et al [1999] for simple current mirror.
The new layout for Cascode current mirror improves the matching characteristics in the
presence of parameter gradient. Effects of threshold gradient across a transistors active
area on the matching characteristics of current mirrors are discussed. New and the
existing layouts of cascode current mirror are compared using SPICE simulations for
threshold voltage gradients at all angles across the active area. Results show a
significant improvement in matching characteristics of the proposed structures for
cascode current mirror over what is achievable with existing layout techniques.

1 Introduction
As the field of VLSI (Very Large-Scale Integrated Circuit) design advances,
the demand for higher precision analog circuit design also grows inevitably. The
realization of any precision analog circuit design has to begin with a thorough
understanding of the matching behavior of the devices because the performance
of the analog circuits depends heavily on the matching of the devices.
Presently, the most popular technology for realizing microcircuits makes use
of Metal-Oxide-Semiconductor Field Effect (MOSFET) transistors, and it is
expected to remain the dominant IC technology for the foreseeable future. Thus,
the study of the matching behavior of MOS transistors remains important
because the performance of analog MOS integrated circuits depends heavily
upon the element of matching accuracy; refer Lakshmikumar et al (1986).
Device layout technique and device size are two important factors that affect the
matching behavior of any design of MOS analog circuits. The layout of
integrated circuits is the central problem in high-density chip design. There is
one mismatch component present in MOS devices which is not present in
bipolar transistors, and that is the mismatch of the threshold voltage. Threshold
voltage mismatch is a strong function of process cleanliness and uniformity, and

1
Pursuing M.E. in Microelectronics, Project Assistant (SMPD VLSI), Department of
ECE, Malaviya Regional Engineering College, Jaipur. erdeepakdhawan@yahoo.co.in
2
Senior Lecturers, Department of ECE, Malaviya Regional Engineering College, Jaipur.
dbool@ieee.org, sahula@ieee.org
2
can be substantially improved by the use of Interdigitized, Common Centroid,
and Fin type geometry proposed by Lan et al [1999]. Integrated circuit design
engineers rarely have control over the fabrication process, and the only way to
compensate for the effects of process variations is to use clever layout
techniques.

2 Sources of mismatch
The first common type of mismatch that exists in MOS transistors is the
Threshold Voltage Mismatch. The threshold voltage of a transistor may be
expressed as
C
I
qD
C
f
Q
C
B
Q
B MS T
V ? ? ? ? ? ? ? 2
where ?
MS
is the gate-semiconductor work function difference, ?
B
is the Fermi
potential in the bulk, Q
B
is the depletion charge density, Q
f
is the fixed oxide
charge density, q is the electron charge, D
I
is the threshold adjust implant dose,
and C is the gate oxide capacitance per unit area. In the above equation, the last
term accounts for an ion implantation step that is provided to adjust V
T0
to a
desired value and is known as the threshold adjust implant. The implanted ions
are assumed to have delta function profile at the silicon-silicon dioxide interface
as discussed in Sze (1981). The standard deviation of V
T
may be determined if
one can find the standard deviations of the various terms on the right-hand side
of the above equation. The Fermi potential ?
B
has a logarithmic dependence on
the substrate doping, and ?
MS
has a similar dependence on doping in the
substrate and in the polysilicon gate. Hence these terms may be regarded as
constants not contributing to any mismatch, see Lakshmikumar et al (1986). The
major contributor to threshold voltage mismatch behavior is the non-uniform
distribution of the dopant atoms in the bulk region. However, in a well-
controlled process the non-uniform distribution of the fixed oxide charges has
negligible effect on threshold voltage mismatch. The second common type of
mismatch that exists in the MOS transistor is conductance-constant mismatch.
The conductance constant is given by
L
W
C K ? ?
where, ? is the channel mobility, C is the oxide capacitance, W is the channel
width, and L is channel length. The mismatch in conductance (K) due to edge
variation is proportional to [1/ (L)
2
+ 1/ (W)
2
]
1/2
. The variation in the gate oxide
capacitance is found to be a common contributing factor to the mismatches in V
T

and K. This concludes that there is dependence between the mismatches in V
T

and K. The mismatch in Drain Current indicates the mismatches in the
Threshold Voltage and Conductance Constant. Generally, MOS transistors will
be operating in the saturation region in analog circuits. Therefore, it is
interesting to look at the drain current equation, as expressed below in terms of
V
T
and K in the saturation region.
? ?
2
2
T
V
GS
V
K
I ? ?
From the above equation, one can see that the value of the drain current of a
MOS device mismatch in drain current is due to mismatches in threshold voltage
3


A A B B A A B B
A B B A B B A A
and conductance constant, refer Lakshmikumar et al (1986). The matching
characteristics of current mirrors and differential amplifiers can be attributed to
systematic and random variations in both geometric parameters and process
parameters. The random variations are easy to model and tradeoffs can be made
between area and performance to compensate for random variations in these
parameters. Systematic variations include mobility (), C
OX
, threshold voltage
(V
T
) and ? variations. In this paper, only V
T
variations have been considered for
various layouts to compare matching characteristics.

3 Layout techniques for improving mismatch
Digital circuits typically use minimum-size devices for high speed, low area
and low power. This is not true for analog circuits which sometimes need
transistors with large width and length in order to increase gain and reduce
noise. Such large devices are more likely to be affected by process variations
across the IC, this situation being critical for matched components. Different
method are used to reduce the effect of process variations are interdigitized,
common centroid, and fin type layouts. The idea is to partition the large devices
into smaller pieces and then physically alternate the small pieces such that their
relative distance is reduced. For example, let us consider two large transistors
that need to be matched are made out of four smaller pieces, AAAA and BBBB,
with each letter representing one unit. If the two are placed adjacent as in Figure
1(a) but grouped then the distance between their centers will be 4 units, hence
a large possible variation. But, if the two are interlaced as in Figure 1(b), then
there is small possible variation.






Figure 1 Layout structures- (a) Simple (b) Interdigitized
The relative distance between the centers is now only 1 unit, for a four
times reduction in process variation. The variation can be completely
compensated for linear gradients by using so-called common-centroid
configurations in which the pieces are arranged such that the two centers (or
centroids) coincide.







Figure 2 Layout structure- Common Centroid
(a)
(b)




A A A A B B B A
A A A A B B B B
4
Interestingly, there are several way in which this can be done, one of the
options is shown in Figure 2. In this figure, a two-dimensional arrangement
with several rows and columns a possible configuration (the one we use) is
shown.
4 Modeling V
T
variations
The parameter gradients are modeled in a distributed way through the active
devices themselves. The matching characteristics are usually a strong function of
the angle of the threshold voltage gradient across a die and for any angle, the
effects of the threshold gradient for the common centroid layout is small. The
widely used approach for predicting the effects of the threshold gradient is based
upon deriving an equivalent threshold voltage as in Pelgrom [1989], for the
devices as given by Equation 1.
Area Active
area active
dxdy Y X
T
V
Teq
V
_
_
) , ( ?
? Equation 1
If the threshold gradient amplitude is a and the gradient direction is ? as
indicated in Figure 4 (a), it follows that Equation set 2 is valid for a simple
current mirror structure shown in Figure 4 (a) whose circuit schematic is shown
in Figure 3.
?
?
? ?
?
?
?
?
cos
2
sin
2
3
2
cos
2
sin
2
1
L
H
D
W
TN
V
T
V
L W
TN
V
T
V
?
? ?
? ?
? ?
?
?
?
? ?
?
?
?
?
?
?
Equation set 2
where D
H
is the minimum separation, usually 3 lambda, between the two drain
diffusions, D1 and D2, V
T1
and V
T2
are the threshold voltages of the two
transistors and V
TN
is the threshold voltage at the base point O in Figure 4 (a).
The equivalent V
T
from Equation 1 is applied to find threshold voltages of four
transistors layouts as common centroid Type I and Type II shown in Figure 4
(b). The expressions for these V
T
s are given in Equation set 3.
? ? ?
?
cos
2
3
/
sin
4
.
1
?
?
?
?
?
?
?
? ? ? ?
L
S V
D
W
TN
V
T
V
? ? ? ? cos
2
. 3
/
sin
4
. 3
2
?
?
?
?
?
?
?
?
?
?
?
?
? ? ? ? ?
L
S V
D
W
H
D
TN
V
T
V Equation set 3
?
?
?
?
cos
2
.
sin
4
.
3
L W
TN
V
T
V ? ? ? ?
?
? ? cos
2
..
sin
4
. 3
4
L W
H
D
TN
V
T
V ? ? ? ?
?
?
?
?
?
?

where V
T1
and V
T4
correspond to the two unit transistors of Transistor One
and V
T2
and V
T3
correspond to the two unit transistors of Transistor Two.
where D
V/S
means either D
V
or D
S
. D
V
and D
S
are the minimum required
distances between the two channels as shown in Figure 4 (b). For a fair
comparison, mismatch for all the structures were measured with the same active
area, W/L and D
H
. Mismatch is defined as follows.
5
% 100
1
1 2
?
?
?
D
I
D
I
D
I
Mismatch



(a) (b)
Figure 3 Current Mirror circuits (a) Basic (b) Cascode



(a) Simple Technique (b) Common Centroid Type I & Type II
Figure 4 Existing techniques for layout of current mirror

5 Improved layout structure for Cascode current mirror
Let us consider cascode current mirror (CCM) circuit shown in Figure 3 (b).
Interdigitized and common centroid layout techniques for this CCM are shown
in Figure 5. A new layout for cascode that offers improvement over what is
achievable with the common centroid technique is shown in Figure 6. The
proposed technique attempts to minimize the mismatch, at which common
centroid structures exhibit maximum mismatch. The expressions in Equation set
4 were used to plot the mismatch for the mirror layouts along with following
range of variables: 0 = ? = 360, V
TN
=0.8V, a=0.5mV/um, W=15um, L=5um,
and D
H
=3um. By observing
Figure 7 and Figure 8, it can be inferred that the proposed technique improves the
matching performance over what is achievable with the common centroid
layouts.

6


(a) Simple (b) Common Centroid
Figure 5 Layout Techniques for cascode current mirror






















Figure 6 Proposed Layout structure- Fin type cascode
Table 1 summarizes the results regarding current mismatch in different
layouts of cascode current mirror that have been simulated. The results have
been obtained for a linear gradient of 0.5mV/um.
D3 D4
D4 D3
D3
D4
D3 VT12
S

VT11
VT15
VT16
VT13
VT VT10
VT14
D4
D1 D2
D2 D1
D1
D2
D1 VT
S
1,2
VT
VT
VT
VT
VT VT
VT
D2
7
? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ?
? ? ? ?
? ? ? ?
? ? ? ?
? ? ? ?
cos
8
3
1
2 sin
2
8
, cos
8
1
sin
2
7
cos
2
sin
8
1
6
, cos
2
sin
8
3
1
2
5
cos
8
1
sin
2
3
2
1
3
4
cos
8
3
1
2 sin
2
3
2
1
3
3
cos
2
3
2
1
3 sin
8
3
1
2
2
cos
2
3
2
1
3 sin
8
1
1
?
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W
H
D L
L
TN
V
T
V
W
H
D L
L
TN
V
T
V
L W
H
D L
TN
V
T
V
L W
H
D L
TN
V
T
V
W
H
D L
L W
H
D
TN
V
T
V
W
H
D L
L W
H
D
TN
V
T
V
L W
H
D
W
H
D L
TN
V
T
V
L W
H
D
W
H
D L
TN
V
T
V
? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ?
? ? ? ?
? ? ? ?
? ? ? ?
? ? ? ?
cos
8
3
2 sin
2
16
, cos
8
sin
2
15
cos
2
sin
8
14
, cos
2
sin
8
3
2
13
cos
8
sin
2
3
2
3
12
cos
8
3
2 sin
2
3
2
3
11
cos
2
3
2
3 sin
8
3
2
10
cos
2
3
2
3 sin
8
9
?
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? ? ? ? ? ?
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? ? ?
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?
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?
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? ?
?
? ? ? ? ?
?
?
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? ? ? ? ? ?
W
H
D L
L
TN
V
T
V
W
H
D L
L
TN
V
T
V
L W
H
D L
TN
V
T
V
L W
H
D L
TN
V
T
V
W
H
D L
L W
H
D
TN
V
T
V
W
H
D L
L W
H
D
TN
V
T
V
L W
H
D
W
H
D L
TN
V
T
V
L W
H
D
W
H
D L
TN
V
T
V
Equation set 4(DH1 is the minimum separation, between the two drain diffusions)


(a) Simple layout (b) Common centroid
Figure 7 Relative current mismatch (Cascode current mirror)

8

Figure 8 Current mismatch in proposed layout structure of Figure 6
Table 1 Comparison of various layout




6 Conclusions
We have obtained a lot better matching characteristics for CCM using Fin-
type layout over the simple layout, Interdigitized, Common Centroid layout
structure. We have observed simulation results showing an improvement in
matching in the presence of linear gradient for the test structures. A comparison
of the performance of several layout structures shows substantial differences in
the sensitivity of the mirror gain due to parameter gradients. The disadvantage of
the proposed technique is the requirement of more silicon-area.

References
Felt, E. et. al (1994). Measurement and Modeling of MOS Transistor Current
mismatch in Analog IC's, Proc. ACM, pp. 272-277.
Lakshmikumar, K. R. (1986). Characterization and Modeling of Mismatch in
MOS Transistors for Precision Analog Design, IEEE J. of Solid State
Circuits, Vol.SC-21, No.6.
Lan, F. M., Tammineedi, A. K. and Geiger, R. L. (1999). A New Current
Mirror Layout Technique for Improved Matching Characteristics, In Proc.
MWSCAS, Las Cruces, Aug.
Pelgrom, M. J. M. et al (1989). Matching properties of MOS transistors, IEEE J.
of Solid State Circuits, Vol SC-24, pp. 1433-1439.
Sze, S. M. (1981), Physics of Semiconductor Devices. 2nd ed: Wiley, New
York.
Layout Type Drain Curren mismatch(%)
Simple 6.0
Interdigitized Type I 0.4
Interdigitized Type II 3.2
Common Centroid 0.6
Fin Type 5?10
-03