Vietnam National University

Integrated Circuit Design Research and Education Center

DIGITAL INTEGRATED CIRCUIT
DESIGN FLOW
Teacher: Nguyn Hng Qun
(Specification and Coding Engineer)
Email: quan.nguyenhung@icdrec.edu.vn

Do not copy and only use for this course
(2)
Product in Mind
CONTENTS
Degital IC design flow
Basic conceptions
Microcontroller and Programmable logic devices
difference
MCU
PLDs
Digital IC structure
Combinational circuit
Sequential circuit
Timing paths
Examples and practices
Vietnam National University
Integrated Circuit Design Research and Education Center
DIGITAL IC DESIGN FLOW
Digital Integrated Circuit Design Flow
(4)
Product in Mind
Digital IC Design Flow

SPECIFICATION
REQUEST
VERIFICATION
PHYSICAL DESIGN
FABRICATION
APPLICATION
Soft IP
Hard IP
Chip
Products
MARKET
(5)
Product in Mind
Specification, Verification and Physical
Design Flow
Research
High-level Design
Low-level Design
Coding
Block-level Check
RTL-level Simulation
Gate-level Simulation
VERIFICATION
FPGA Test
SPECIFICATION
PHYSICAL
DESIGN
PHYSICAL
DESIGN
Synthesis
Pre-layout Timing
Palce and Route
Post-layout Timing
Physical Verification
FABRICATION
VERIFICATION
SPECIFICATION
VERIFICATION
PHYSICAL DESIGN
specification model
(6)
Product in Mind
Specification Model (Reference)
Modeling the design structure
SpecC
Base on C language
Do not develop
The tools is limited
SystemC
Base on C++ language
Developing
Many tools

(7)
Product in Mind
Specification Tools
Microsoft Word: specification description, user guide
Microsoft Visio: design structure
Microsoft Excel: memory and register map
Notepad++ or EmEditor: Coding
XEmacs: Auto-connection
LEDA (Synopsys): RTL code checker
Quartus (Altera), ISE Design Suite (Xilinx): Checking,
Compiling and Simulating on FPGA
VCS (Synopsys) or ModelSim (Mentor): Simulating at
block level

(8)
Product in Mind
Verification Tools
VCS (Synopsys)
ModelSim (Mentor Graphic)
(9)
Product in Mind
Phisical Design Tools
Design Compiler (Synopsys): compiling RTL code
IC Compiler (Synopsys): layout
PrimeTime (Synopsys): checking the design timing
Hercules (Synopsys): checking the physical design
(DRC Design Rule Check and LVS Layout Versus
Schematic)

More references: http://www.synopsys.com/Tools
(10)
Product in Mind
Reference website
http://verilog.renerta.com/ Verilog help online
http://www.asic-world.com/ Verilog, VHDL, System
Verrilog examples, tutorials and books
http://www.fpga4fun.com/ presents the some little
projects, such as I2C, PCI, SPI, RS-232,
http://opencores.org/ supplies the open IP cores
http://www.freemodelfoundry.com/ supplies free models
http://www.chipestimate.com/ and http://www.design-
reuse.com/
http://www.eetimes.com/ news
http://icdesignvn.com/ the Vietnam IC and
microelectronic forum
Vietnam National University
Integrated Circuit Design Research and Education Center
BASIC CONCEPTIONS
Digital Integrated Circuit Design Flow
(12)
Product in Mind
IC (chip) types
Analog IC (Amplifier, comparator, )
Digital IC (logic IC (74XX family), encoder, )
Mixed-signal IC (microcontroller)
(13)
Product in Mind
Analog chip and Digital chip
continuous discrete
block design
circuit design
physical design
(layout)
Analog
Digital
base on Transistor,
capacitor, resistor,
base on logic cells
(14)
Product in Mind
ASIC and FPGA
ASIC Application Specific Integrated Circuit
Do not change specific application (Ex: MCU chip,
CAN controller chip, )
FPGA - Field Programmable Gate Array
Creating the desire specific application (Ex: FPGA
chip can be MCU, CAN controller, LED driver, )
ASIC
Full custom capability
(from specification to manufacturing)
Lower unit costs
Smaller form factor
(the optimal size)
FPGA
Faster time-to-market
Simpler design process
(the fewer number of steps)
Reprogramability
(15)
Product in Mind
Intellectual Property (IP) Core
Soft IP
The synthesizable RTL code (Verilog or VHDL)
Model files (behavior model) to test and simulate
Example testbenchs
User guide files
Hard IP
GDS (Graphic Data System) file to manufacture
lef (library exchange format physical form of I/O and
metal layer) and lib (timing, power, I/O capacitance value)
files to synthesise
model files to test and simulate
user guide files
(16)
Product in Mind
Fabrication Technology
2013
Vietnam chip
2004
Vietnam IC factory
1999
In 1965 Gordon Moore, wrote a paper
entitled "Cramming more components
onto integrated circuits". Moore
observed that "The complexity for
minimum component cost has
increased at a rate of roughly a factor
of two per year". This is known as
Moore's law, the number of
components per IC double every
year.

Moore's law was later amended to,
the number of components per IC
doubles every 18 months.
Vietnam National University
Integrated Circuit Design Research and Education Center
MCU AND PLDS DIFFERENCE
Digital Integrated Circuit Design Flow
(18)
Product in Mind
Microcontroller - MCU
ASIC
Program language: Assembly, C/C++
Software program
Configurating the register map
Serial implementation
(19)
Product in Mind
Programmable Logic Devices - PLDs
non ASIC
Program language: hardware description language (Verilog HDL
or VHDL)
hardware program
Configurating the inter-connections
Parallel implementation
Vietnam National University
Integrated Circuit Design Research and Education Center
DIGITAL IC STRUCTURE
Digital Integrated Circuit Design Flow
(21)
Product in Mind
Contents
Combination circuit
Concept
Signal delay
Popular circuits
Sequential circuit
Concept
Popular circuits
Timing
Vietnam National University
Integrated Circuit Design Research and Education Center
DIGITAL IC STRUCTURE
(COMBINATION CIRCUIT)
Digital Integrated Circuit Design Flow
(23)
Product in Mind
Combination Circuit
Non-sequential circuit
Only contain the logic gates without the memory
elements
in3
in1
en
in0
in2
01
00
sel[1:0]
in3
in1
in0
in2
(24)
Product in Mind
Combination circuit (cont)
Do not store the previous value
The output value is only dependent on the current input
value
Do not use the feedback line in the combination circuit
(why?)
(25)
Product in Mind
Signal delay
Delay of the difference signals is different
The difference delays generate
The input race
The output glitch
the signal bus
(state of FSM, address bus,
data bus)
How is these restrained?
(26)
Product in Mind
Popular circuits
mutiplexer/de-multiplexer
encoder/decoder
adder
(27)
Product in Mind
Multiplexer and De-multiplexer
MUX 4-1
SEL1 SEL0 OUT
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
DE-MUX 1-4
SEL1 SEL0 OUT3 OUT2 OUT1 OUT0
0 0 IN 0 0 0
0 1 0 IN 0 0
1 0 0 0 IN 0
1 1 0 0 0 IN
Application?
(28)
Product in Mind
Encoder and Decoder
0 = 1,3 = 3

10

+ 32

= 2

0(3

1 +31)
1 = (2,3) = 3

21

+ 32

= 1

0(3

2 +32)
Problem of
this simple
encoder?
(29)
Product in Mind
Priority Encoder
Problem of this priority
encoder 4-to-2?
Inputs Outputs
D3 D2 D1 D0 Q1 Q0
0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1
0 0 0 0 X X
Exercise: Design the priority encoder 8-to-3 and
decoder 3-to-8
1/ Truth table
2/ SOP expression of the outputs
3/ Structure diagram
4/ Coding based on the structure diagram
Application?
(30)
Product in Mind
1-bit Half and full adder
Half adder




Full adder
a b cout s
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
a b cin cout s
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1
(31)
Product in Mind
n-bit Adder Ripple carry

Problem?
(32)
Product in Mind
n-bit Adder Carry Look-Ahead
CLA adder: generating the special circuit to calculate
the carry flag
CLA 4-bit
(33)
Product in Mind
n-bit Adder Carry Look-Ahead (cont)
Carry generator value is generated by ai and bi
value is generated by the
previous propagation
(34)
Product in Mind
n-bit Adder Carry Look-Ahead (cont)
Carry generator
Problem?
(35)
Product in Mind
n-bit Adder Carry Look-Ahead (cont)
Combining the Ripple Carry method and CLA method
by connecting the small CLA adders
Vietnam National University
Integrated Circuit Design Research and Education Center
DIGITAL IC STRUCTURE
(SEQUENTIAL CIRCUIT)
Digital Integrated Circuit Design Flow
(37)
Product in Mind
Concept
What is sequential
circuit?
Sequential circuit = Logic circuit
+ memory elements
This understanding is allowed
but it is not the origin
understanding
(38)
Product in Mind
Concept (cont)
The output is dependent not only on the present inputs
to the device, but also on past inputs or previous
outputs
This is sequential circuit
How is this circuit
understood?
Where is it used?
(39)
Product in Mind
D Latch
SR NOR latch
D latch based on the SR NOR latch
D latch based on the SR NAND latch
SR NAND latch
(40)
Product in Mind
D Latch (cont)
Can be used to store one bit of information.
D latch is a level triggering device.
The clock pulse is high, then the output Q follows the
input D.
The clock input is low, the last state of the D input is
trapped and held in the latch.
(41)
Product in Mind
D Flip-Flop
Can be used to store one bit of information.
D Flip-Flop is an edge triggering device
The output Q follows the input D at the rising or falling
edge.
The value of Q is held untill the next rising or falling edge.
(42)
Product in Mind
D Flip-Flop

when clock = 0 when clock changes from 0 to 1 clock = 1, data changes from 0 to 1
(43)
Product in Mind
Compares D Latch & D Flip-Flop
Many logic synthesis tool use only D Flip-Flop and D
Latch (Why are JK FF and T FF not used?)
D Latch D Flip-Flop
Triggering Level Edge
Circuit size Small Large
Delay and power
consumption
Little More
Application Temporary buffer Register
(44)
Product in Mind
JK Latch/Flip-Flop is not used popularly
Two inputs

Race between Q and CLK => high
frequency
Two inputs

The area and the power
consumed is more than D
FF
(45)
Product in Mind
T Latch/Flip-Flop is not used popularly
More switching activity n
comparison with the D flip-flop

Race between Q and CLK
=> high frequency
master-slave T flip-flop
area and power consumption
Why?
D flip-flop is the
best choice
(46)
Product in Mind
Flip-Flop applications
Register
Counter
FIFO (First In First Out)
LIFO (Last In First Out)
SRAM (Synchronous RAM)
Finite State Machine (FSM)
These problems will be
presented the next time
(47)
Product in Mind
Setup time and hold time
When using FFs to design the sequential circuit, we
must care a timing window around the clocking event
during which the synchronous input must remain stable
and unchanged to be recognized
What must steps be
cared?
Negative hold time
Negative setup time
Invalid timing
Vietnam National University
Integrated Circuit Design Research and Education Center
TIMING PATHS
Digital Integrated Circuit Design Flow
(49)
Product in Mind
Concepts
Timing path is the important concept. The timing
analysis tool finds and analyzes all of the timing paths in
the design.
Each path has a startpoint and an endpoint
The startpoint of a path (or the data launch point) is a
clock pin of a sequential element or an input port of the
design.
The endpoint of a path (or the data capture point) is a
data input pin of a sequential element or an output port of
the design.
(50)
Product in Mind
Timing path types

Path 1: Starts at an input port and ends at the data
input of a sequential element
Path 2: Starts at the clock pin of a sequential element
and ends at the data input of a sequential element
Path 3: Starts at the clock pin of a sequential element
and ends at an output port
Path 4: Starts at an input port and ends at an output
port
Dont have the
feedback line
(51)
Product in Mind
Reducing the
The purpose of the timing path values

How to reduce the
delay of the critical
path?
Vietnam National University
Integrated Circuit Design Research and Education Center