High Speed Data Generation for Optical Inter-Satellite Link

Kaushik Nagaraj , Abhishek S.M., Adwaita Goswami, A.S.Laxmi Prasad

Indian Space Research Organization (ISRO)
Laboratory for Electro-Optics Systems (LEOS)
Bangalore
Email: kaushikstan@gmail.com; abhi1931@gmail.com

Abstract:
Remote Sensing satellites orbiting in low earth
orbit LEO generate large volume of data that needs
to be communicated. However, their visibility to
ground is limited. Free space optical communication
between a remote sensing satellite in the LEO and a
communication satellite in the GEO can be a
favorable approach. Subsequently, the GEO satellite
relays the data to ground station. Optical Inter-
satellite links can be established between two Geo-
stationary (GEO) satellites, between a Low Earth
Orbiting (LEO) satellite and a GEO, or between a
deep space probe and a GEO or LEO. The use of
optical signals as information carriers in satellite
communication system becomes attractive because of
their ability to provide very high-speed
communications with data rates in the order of Gbps
(Giga bit per second) without any mutual
interference. Optical inter-satellite communication
system requires laser devices, high gain optical
antennas, highly sensitive signal detectors. Data
generated on the LEO satellite needs to be converted
to high data rates in order for it to be compatible
with the optical devices being used for
communication. Currently a laboratory level
demonstration of inter satellite link at 1.25Gbps is
under progress at LEOS. Data at this high speed
needs to be generated and fed to this demonstration
model at transmitter end. The current paper gives a
method to convert the data generated from a
computer to be read out through a PCI Bus, convert
it to a higher data rate of 155.52 Mbps (Mega bits
per second) as one of the channel of the high data
rate simulator card and at the same time taking into
consideration the conversion of various logic levels
so that the final output is compatible with the ECL
(Emitter Coupled Logic) logic level.
1. INTRODUCTION
Optical Inter-satellite Link is the link
established between two satellites in order to
facilitate communication between the two satellites.
Enormous amount of data available on the Low Earth
Orbit Satellites (LEO) need to be communicated to
the ground. However, their visibility to the ground is
limited. A simple approach around this problem
would be to set up a link between the LEO satellite
and the Geostationary (GEO) satellite and transfer
data to the GEO satellite. Since the GEO satellite is
constantly in the visible range to the ground, the data
from the GEO satellite can be communicated to the
ground. The use of an optical link in such
applications instead of a RF link provides many
advantages. Through optical link, very high data rates
can be achieved. It also aids in keeping the system
compact, thereby, reducing the weight of the system.
Hence, the cost of the system is low. The power
needed for transmission is less compared to RF
systems. In optical inter satellite link, data is
transmitted using modulated optical signal. The data
at higher rate in the LEOS demonstration model is
generated by multiplexing data at lower speeds. The
data gets multiplexed through a card called as the
serializer card, it is critical to make the incoming data
(to the serializer card) compatible with the standard
input specifications of the serializer card. The input
to the serializer card requires a data rate of
155.52Mbps and the data to be in the Emitter
Coupled Logic (ECL) level.
The data from a computer can be standardized
to the specifications mentioned above through a
scheme as described in Figure 1. The basic principle
of this block diagram is to convert the input data to
the required data rate using a Digital Input/Output
(DIO) Card and to convert the Transistor-Transistor
Logic (TTL) level to Low Voltage Positive Emitter
Coupled Logic (LVPECL) level using a Translator.

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Figure 1. BLOCK DIAGRAM
The data from the computer is obtained through the
Peripheral Component Interconnect (PCI) bus. The 8-
bit data is read out using a DIO card with the
necessary control and handshake signals. The DIO
card has an in-built memory in order to bring about
the desired data rate conversion. The input clock to
the DIO is 155.52 / 8 = 19.44 MHz. this clock
dividing is brought about by using the counter. The
output of the DIO card is at a data rate of 19.44 Mbps
and in TTL level. This 8-channel parallel data is
given to a TTL-to-ECL Translator; the output of
which is given to a Parallel-in Serial-out (PISO) Shift
Register. The output of shift register is serial data at
the rate of 155.52 Mbps, ECL. In order to bring about
the conversion from ECL to LVPECL, a combination
of resistors and capacitors with proper pull up
voltages are used.
2. HARDWARE DESCRIPTION
2.1. CIRCUIT
The circuit diagram is given in Figure 2.The
data from the computer is read through the PCI Bus
at the rate of 19.44 Mbps; TTL logic level. The rate
at which the data is read from the PCI bus can be
controlled by programming the DIO card by
software. The DIO has a provision to accept the clock
from an external source as well as from its in-built
clock. The DIO has to be configured to operate in the
external clock mode. The clock input to the DIO is
19.44 Mbps. This is the rate at which the 8 channel
parallel data reaches the PISO Shift register, thereby,
giving a serial data at the rate of 19.44 * 8 = 155.52
Mbps. With the help of the control signals and the
handshake signals, it becomes possible for us to
obtain an output from the DIO at a data rate of
155.52 Mbps.
The data from the DIO needs to be converted to
ECL logic level as TTL cannot support high data
rates. This can be brought about with the help of an
8-bit TTL-to-ECL Translator. The output of the
translator is ECL logic level and data has a rate of
19.44 Mbps. This is given to an 8-bit Parallel-in
Serial-out Shift Register. The Shift Register has a
clock input of 155.52 MHz that is tapped from the
‘serializer card’. The data is given out serially from
the shift register at the rate of the input clock
frequency which is 155.52 Mbps.
A 4-bit ECL counter is made to operate in the
count-down mode so that it can be used as a clock
divider. The output of the counter is C0, C1, C2, C3.
C3 is left unused since the tapped clock needs to be
divided by 8 and not by 16. The tapped clock from
the serializer card is given as input to this counter
which divides it by 8 to provide us with a clock rate
of 19.44 MHz. This clock is used as clock input to
the DIO card and the translator. The counter is also
used to set-reset the select lines required for Parallel
load and serial shift in the shift register.
The ECL data at the rate of 155.52 Mbps is
converted to LVPECL using pull-up resistance
network. A fanout buffer has been used to assist in
pulse shaping ;i.e, to reconstruct certain pulses that
may have become distorted. A 6-bit ECL-to-TTL
Translator has been used to generate the handshake
signal for the DIO card. Only one channel of this
translator is utilized. The input to this translator is C2
output of the counter and a signal labeled as REQ is
obtained. This REQ signal serves as a handshake
between the DIO and the conversion card.
Impedance mismatching due to different load
on different ICs can be an enormous problem when
operating at high frequencies. This can be countered
by using termination between the devices.
Termination is combination of pull up resisters that
are attached to each line. By choosing the correct
combination of the resistor values, proper termination
can be achieved and radiation losses can be
minimized.
To implement the above circuit, it is suggested
to use standard IC’s that are easily available in the
market. This paper suggests the use of IC’s of the
100xxx series. The next section on propagation delay
has been explained by taking into consideration the
IC’s of the above mentioned series.
2.2. PROPAGATION DELAY
Propagation delay is inevitable when a signal
has to traverse through an IC. Even very small delays
can lead to undesirable results when dealing with
high data rates. With the help of necessary logic gates
and flip flops, we generate signals that take the
propagation delay into account and generate the
desired outputs.
The foremost important factor is that the
total propagation delay of all the devices put together
must not exceed the duration of 8 clock pulses. If it
does then, the data being read out of the conversion
card will not be correct and there will be
unacceptable loss of data. This is because; the first
byte of data at the last stage of the conversion card
needs to be read out before the next byte of data
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overwrites it. As explained in the next section on
timing diagrams, it is wise to take the worst case
scenario into account. This means that the maximum
propagation delay of all the IC’s has been considered.
Figure 2. CIRCUIT DIAGRAM
2.3. TERMINATION
ECL outputs are bipolar junction transistors (BJT)
configured as emitter followers. To maintain their
fast switching rates, these emitter followers should
operate in the forward active region at all times,
requiring them to source current at all times. ECL
inputs have large impedance (typically around 75 kΩ)
that does not allow for the necessary current sourcing
by the ECL output. Instead, this current sourcing is
achieved by terminating the ECL output through a
resistor, Rt, to a voltage, VTT, such that
VTT = VCC – 2.0V
Rt = Z0
where Z0 is the characteristic impedance of the
transmission line connecting the ECL output to Rt.
ECL outputs are typically 50 Ω, thus the terminating
resistor as well as the transmission line’s
characteristic should be approximately 50 Ω.
2.4. TIMING DIAGRAM
The timing diagram for the circuit
mentioned above is shown in Figure 3. The diagram
shows a clock of frequency 155.52 Mbps. It should
be noted that only one bit is transferred per clock
cycle. CLK is the clock with time period of
1 / 155.52Mbps = 6.43 ns and 50% duty cycle. Thus
the high time and low time are 3.2ns. C0, C1, C2 are
the counter outputs. There is a propagation delay of
2.5 ns at the counter. C2 is passed through the 6-
channel translator (100325) and given as the
handshake signal to the DIO card. This signal has a
propagation delay of 4.7 ns.
On reception of this handshake signal, the
DIO sends the data to the conversion card. The
maximum propagation delay of the DIO is 30 ns.
Hence, the data is received after 30ns at the
conversion card. At this instant, it is necessary to
instruct the ECL-to-TTL translator (100329) to read
the data. This is brought about by ANDing the
counter outputs as C2’ AND C1 AND C0’. On
receipt of this signal, the translator outputs the data to
the input of the shift register.
With the proper combination of the select
lines of the shift register, it can be made to operate in
the load mode and the serial shift mode. A low on the
select lines S1 and S0 will read out the parallel
latched data serially.
3. SOFTWARE INVOLVED
The DIO card is software programmable and
needs to be programmed to control the data
input/output. The ports on the DIO can be configured
as all input ports or all output ports or some as input
ports and some as output ports. There will be specific
registers for this purpose. It is necessary to program 8
parts as input and 8 ports as output. Also, there is a
need to generate the necessary control signals and the
handshake signals so that the output is at the data rate
of 19.44 Mbps. The data needs to be read into the
DIO when data is ready given the previous data has
been sent out through the output ports. Another
possibility is the occurrence of the overflow of the
buffer in the DIO leading to the reading of wrong
data at the output ports.
When the input data rate is less than the output
data rate, there is a possibility of buffer underflow.
So, to prevent this, handshake signals must be
generated between the DIO card and the circuit card.
DIO has many modes of operation. The modes
selected should be operable at 19.44 MHz.
Data from the computer can be of many format
types. All these formats have certain headers that
contain information pertaining to the data it contains.
The information from these headers must be
extracted and utilized for writing the proper software
such that the data is sent out or read by the DIO card
in an orderly manner. The extraction of the headers is
done writing a separate program to this effect.
4. DESIGN ISSUES
Some of the critical problems that are most
likely to arise and needs to be addressed are that of
impedance mismatching and propagation delay
involved in the devices. These have been dealt with
in the above sections.
Clock source is another problem. This paper talks
about the clock being tapped from the serializer card.
However, it is always the data generator card
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 that gives the clock to the subsequent devices. The
card also has a provision for generating the clock
from a crystal that is on-board the conversion card.
There is a possibility of timing mismatches
when the data is transferred. These mismatches,
though, very small, can accumulate and cause bit
errors. It is important to test where these errors occur
and modify the software program accordingly.

5. CONCLUSION
A method to bring about data generation
for Optical Inter-Satellite Link has been proposed.
The various high speed design issues have been
highlighted and ways to counter some of these
problems have also been briefly discussed.

6. REFERENCES

[1] Ryan J. Pirkl, “ECL Design Guide”,

Propagation Group, Georgia Institute of
Technology, May 18, 2005.

[2] Paul Shockman, “Termination of ECL Devices

with EF (Emitter Follower)Output Structure, ON
Semiconductor Logic Applications Engineering.

[3] Ranjith.R, Adwaita Goswami, P.Raghu Babu and

A.S.Laxmiprasad, “Technology and Design needs for
Optical Inter-Satellite Link (OISL)”.

[4] Laxmiprasad A.S., R.Ranjith, P.Raghubabu,

J.A.Kamalakar, “Optical Inter-Satellite Link (OISL)
Figure 3. TIMING DIAGRAM for Remote Sensing Satellites” in SPIE Proceedings
on Asia Pacific Remote Sensing, Panaji, Goa, India,
November – 2006.