AD8351

Low Distortion
Differential RF/IF Amplifier
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 2004 Analog Devices, Inc. All rights reserved.
FEATURES
3 dB Bandwidth of 2.2 GHz for A
V
= 12 dB
Single Resistor Programmable Gain
0 dB A
V
26 dB
Differential Interface
Low Noise Input Stage 2.7 nV/Hz @ A
V
= 10 dB
Low Harmonic Distortion
79 dBc Second @ 70 MHz
81 dBc Third @ 70 MHz
OIP3 of 31 dBm @ 70 MHz
Single-Supply Operation: 3 V to 5.5 V
Low Power Dissipation: 28 mA @ 5 V
Adjustable Output Common-Mode Voltage
Fast Settling and Overdrive Recovery
Slew Rate of 13,000 V/s
Power-Down Capability
10-Lead MSOP Package
APPLICATIONS
Differential ADC Drivers
Single-Ended-to-Differential Conversion
IF Sampling Receivers
RF/IF Gain Blocks
SAW Filter Interfacing
FUNCTIONAL BLOCK DIAGRAM
VOCM
VPOS
OPHI
OPLO
COMM
PWUP
RGP1
INHI
INLO
RGP2
AD8351
BIAS CELL
GENERAL DESCRIPTION
The AD8351 is a low cost differential amplifier useful in RF and
IF applications up to 2.2 GHz. The voltage gain can be set from
unity to 26 dB using a single external gain resistor. The AD8351
provides a nominal 150 differential output impedance. The
excellent distortion performance and low noise characteristics of
this device allow for a wide range of applications.
The AD8351 is designed to satisfy the demanding performance
requirements of communications transceiver applications. The
device can be used as a general-purpose gain block, an ADC driver,
0 5 10 15 20 25 30 35
2
3
+
RG
AD8351
100nF
100nF
25
25
AD6645
14-BIT ADC
INHI
INLO
200
AD8351
AD8351 WITH 10 dB OF
GAIN DRIVING THE
AD6645 (R
L
= 1k)
ANALOG INPUT: 70MHz
ENCODE : 80MHz
SNR : 69.1dB
FUND : 1.1dBFS
HD2 : 78.5dBc
HD3 : 80.7dBc
THD : 75.9dBc
SFDR : 78.2dBc
0
10
20
40
30
50
60
70
80
90
120
100
130
110
and a high speed data interface driver, among other functions. The
AD8351 can also be used as a single-ended-to-differential
amplifier with similar distortion products as in the differential
configuration. The exceptionally good distortion performance
makes the AD8351 an ideal solution for 12-bit and 14-bit IF
sampling receiver designs.
Fabricated in ADIs high speed XFCB process, the AD8351
has high bandwidth that provides high frequency performance
and low distortion. The quiescent current of the AD8351 is 28 mA
typically. The AD8351 amplifier comes in a compact 10-lead
MSOP package and will operate over the temperature range
of 40C to +85C.
REV. B
REV. B 2
AD8351SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth GAIN = 6 dB, V
OUT
1.0 V p-p 3,000 MHz
GAIN = 12 dB, V
OUT
1.0 V p-p 2,200 MHz
GAIN = 18 dB, V
OUT
1.0 V p-p 600 MHz
Bandwidth for 0.1 dB Flatness 0 dB GAIN 20 dB, V
OUT
1.0 V p-p 200 MHz
Bandwidth for 0.2 dB Flatness 0 dB GAIN 20 dB, V
OUT
1.0 V p-p 400 MHz
Gain Accuracy Using 1% Resistor for R
G
, 0 dB A
V
20 dB 1 dB
Gain Supply Sensitivity V
S
5% 0.08 dB/V
Gain Temperature Sensitivity 40C to +85C 3.9 mdB/C
Slew Rate R
L
= 1 k, V
OUT
= 2 V Step 13,000 V/s
R
L
= 150 , V
S
= 2 V Step 7,500 V/s
Settling Time 1 V Step to 1% <3 ns
Overdrive Recovery Time V
IN
= 4 V to 0 V Step, V
OUT
10 mV <2 ns
Reverse Isolation (S12) 67 dB
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode
Voltage Adjustment Range 1.2 to 3.8 V
Max Output Voltage Swing 1 dB Compressed 4.75 V p-p
Output Common-Mode Offset 40 mV
Output Common-Mode Drift 40C to +85C 0.24 mV/C
Output Differential Offset Voltage 20 mV
Output Differential Offset Drift 40C to +85C 0.13 mV/C
Input Bias Current 15 A
Input Resistance
1
5 k
Input Capacitance
1
0.8 pF
CMRR 43 dB
Output Resistance
1
150
Output Capacitance
1
0.8 pF
POWER INTERFACE
Supply Voltage 3 5.5 V
PWUP Threshold 1.3 V
PWUP Input Bias Current PWUP at 5 V 100 A
PWUP at 0 V 25 A
Quiescent Current 28 32 mA
(V
S
= 5 V, R
L
= 150 , R
G
= 110 (A
V
= 10 dB), f = 70 MHz, T = 25C, parameters
specified differentially, unless otherwise noted .)
REV. B
AD8351
3
Parameter Conditions Min Typ Max Unit
NOISE/DISTORTION
10 MHz
Second/Third Harmonic
Distortion
2
R
L
= 1 k, V
OUT
= 2 V p-p 95/93 dBc
R
L
= 150 , V
OUT
= 2 V p-p 86/71 dBc
Third-Order IMD R
L
= 1 k, f1 = 9.5 MHz, f2 = 10.5 MHz,
V
OUT
= 2 V p-p Composite 90 dBc
R
L
= 150 , f1 = 9.5 MHz, f2 = 10.5 MHz,
V
OUT
= 2 V p-p Composite 70 dBc
Output Third-Order Intercept f1 = 9.5 MHz, f2 = 10.5 MHz 33 dBm
Noise Spectral Density (RTI) 2.65 nV/Hz
1 dB Compression Point 13.5 dBm
70 MHz
Second/Third Harmonic
Distortion
2
R
L
= 1 k, V
OUT
= 2 V p-p 79/81 dBc
R
L
= 150 , V
OUT
= 2 V p-p 65/66 dBc
Third-Order IMD R
L
= 1 k, f1 = 69.5 MHz, f2 = 70.5 MHz,
V
OUT
= 2 V p-p Composite 85 dBc
R
L
= 150 , f1 = 69.5 MHz, f2 = 70.5 MHz,
V
OUT
= 2 V p-p Composite 69 dBc
Output Third-Order Intercept f1 = 69.5 MHz, f2 = 70.5 MHz 31 dBm
Noise Spectral Density (RTI) 2.70 nV/Hz
1 dB Compression Point 13.3 dBm
140 MHz
Second/Third Harmonic
Distortion
2
R
L
= 1 k, V
OUT
= 2 V p-p 69/69 dBc
R
L
= 150 , V
OUT
= 2 V p-p 54/53 dBc
Third-Order IMD R
L
= 1 k, f1 = 139.5 MHz, f2 = 140.5 MHz,
V
OUT
= 2 V p-p Composite 79 dBc
R
L
= 150 , f1 = 139.5 MHz, f2 = 140.5 MHz,
V
OUT
= 2 V p-p Composite 67 dBc
Output Third-Order Intercept f1 = 139.5 MHz, f2 = 140.5 MHz 29 dBm
Noise Spectral Density (RTI) 2.75 nV/Hz
1 dB Compression Point 13 dBm
240 MHz
Second/Third Harmonic
Distortion
2
R
L
= 1 k, V
OUT
= 2 V p-p 60/66 dBc
R
L
= 150 , V
OUT
= 2 V p-p 46/50 dBc
Third-Order IMD R
L
= 1 k, f1 = 239.5 MHz, f2 = 240.5 MHz,
V
OUT
= 2 V p-p Composite 76 dBc
R
L
= 150 , f1 = 239.5 MHz, f2 = 240.5 MHz,
V
OUT
= 2 V p-p Composite 62 dBc
Output Third-Order Intercept f1 = 239.5 MHz, f2 = 240.5 MHz 27 dBm
Noise Spectral Density (RTI) 2.90 nV/Hz
1 dB Compression Point 13 dBm
NOTES
1
Values are specified differentially.
2
See Applications section for single-ended-to-differential performance.
Specifications subject to change without notice.
REV. B
4
AD8351
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8351 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
PWUP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 320 mW

JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C
Operating Temperature Range . . . . . . . . . . . . 40C to +85C
Storage Temperature Range . . . . . . . . . . . . . 65C to +150C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
1
AD8351
PWUP
RGP1
INHI
INLO
RGP2
VOCM
VPOS
OPHI
OPLO
COMM
2
3
4
5
10
9
8
7
6
TOP VIEW
(Not to Scale)
ORDERING GUIDE
Model Temp. Range Package Description Package Option Branding
AD8351ARM 40C to +85C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351ARM-R2 40C to +85C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351ARM-REEL7 40C to +85C 10-Lead MSOP, 7" Tape and Reel RM-10 JDA
AD8351-EVAL Evaluation Board
PIN FUNCTION DESCRIPTIONS
Pin No. Name Function
1 PWUP Apply a positive voltage (1.3 V V
PWUP
VPOS ) to activate device.
2 RGP1 Gain Resistor Input 1.
3 INHI Balanced Differential Input. Biased to midsupply, typically ac-coupled
4 INLO Balanced Differential Input. Biased to midsupply, typically ac-coupled.
5 RGP2 Gain Resistor Input 2.
6 COMM Device Common. Connect to low impedance ground.
7 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled.
8 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled.
9 VPOS Positive Supply Voltage. 3 V to 5.5 V.
10 VOCM Voltage applied to this pin sets the common-mode voltage at both the input and output.
Typically decoupled to ground with a 0.1 F capacitor.
REV. B
AD8351
5
FREQUENCY (MHz)
1 10000
G
A
I
N

(
d
B
)
0
10 100 1000
20
15
10
5
5
R
G
= 20
R
G
= 80
R
G
= 200
TPC 1. Gain vs. Frequency for a 150 Differential Load
(A
V
= 6 dB, 12 dB, and 18 dB)
R
G
()
35
10 10k
G
A
I
N

(
d
B
)
25
15
5
5
10
100 1k
30
20
10
0
R
L
= OPEN
R
L
= 1k
R
L
= 150
TPC 2. Gain vs. Gain Resistor, R
G
(f = 100 MHz,
R
L
= 150 , 1 k, and Open)
TEMPERATURE (C)
10.75
50 110
G
A
I
N

(
R
L

=

1
k

)

(
d
B
)
10.50
10.00
9.50
9.25
30 50
10.25
9.75
10 10 30 70 90
9.00
G
A
I
N

(
R
L

=

1
5
0

)

(
d
B
)
10.50
10.00
9.50
9.25
10.25
9.75
TPC 3. Gain vs. Temperature at 100 MHz (A
V
= 10 dB)
(V
S
= 5 V, T = 25C, unless otherwise noted.)
FREQUENCY (MHz)
30
1 10000
G
A
I
N

(
d
B
)
5
10 100 1000
25
20
15
10
0
R
G
= 10
R
G
= 50
R
G
= 200
TPC 4. Gain vs. Frequency for a 1 k Differential Load
(A
V
= 10 dB, 18 dB, and 26 dB)
FREQUENCY (MHz)
0.8
1 1000
G
A
I
N

F
L
A
T
N
E
S
S

(
d
B
)
0.4
0
0.4
0.8
1.0
10 100
0.6
0.2
0.2
0.6
0.5
0.1
0.3
0.7
0.9
0.7
0.3
0.1
0.5
0.9
1.0
R
L
= 150
R
L
= 1k
R
L
= 150
R
L
= 1k
TPC 5. Gain Flatness vs. Frequency
(R
L
= 150 and 1 k, A
V
=10 dB)
FREQUENCY (MHz)
0 1000
I
S
O
L
A
T
I
O
N

(
d
B
)
70
90
60
80
10
0
50
40
30
20
100 200 300 400 500 600 700 800 900
TPC 6. Isolation vs. Frequency (A
V
= 10 dB)
Typical Performance Characteristics
REV. B
6
AD8351
FREQUENCY (MHz)
0 250
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
V
P
O
S

=

5
V
)

(
d
B
c
)
70
90
60
80
50
40
30
25 50 75 100 125 150 175 200 225
100
45
55
65
75
85
95
105
115
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
V
P
O
S

=

3
V
)

(
d
B
c
)
HD2
HD3
HD3
HD2
DIFFERENTIAL INPUT
TPC 7. Harmonic Distortion vs. Frequency for 2 V p-p
into R
L
= 1 k (A
V
= 10 dB, at 3 V and 5 V Supplies)
FREQUENCY (MHz)
0 250
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
V
P
O
S

=

5
V
)

(
d
B
c
)
40
60
30
50
20
10
0
25 50 75 100 125 150 175 200 225
70
20
30
40
50
60
70
80
90
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
V
P
O
S

=

3
V
)

(
d
B
c
)
80
90
100
110
HD3
HD2
HD2
HD3
DIFFERENTIAL INPUT
TPC 8. Harmonic Distortion vs. Frequency for 2 V p-p into
R
L
= 150 (A
V
= 10 dB, at 3 V and 5 V Supplies)
FREQUENCY (MHz)
0 250
N
O
I
S
E

S
P
E
C
T
R
A
L

D
E
N
S
I
T
Y

(
n
V
/


H
z
)
2.80
2.70
2.85
2.75
2.90
2.95
3.00
50 100 150 200
2.65
2.60
2.55
2.50
TPC 9. Noise Spectral Density (RTI) vs. Frequency
(R
L
= 150 , 5 V Supply, A
V
= 10 dB)
FREQUENCY (MHz)
0 100
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
d
B
c
)
70
80
65
75
60
55
50
10 40 60 80
85
90
95
100
20 30 50 70 90
HD3
HD3
HD2
SINGLE-ENDED INPUT
TPC 10. Harmonic Distortion vs. Frequency for 2 V p-p
into R
L
= 1 k Using Single-Ended Input (A
V
= 10 dB)
FREQUENCY (MHz)
0 100
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

(
d
B
c
)
70
80
65
75
60
55
50
10 40 60 80
85
90
95
100
20 30 50 70 90
HD2
HD3
SINGLE-ENDED INPUT
TPC 11. Harmonic Distortion vs. Frequency for 2 V p-p
into R
L
= 150 Using Single-Ended Input (A
V
= 10 dB)
FREQUENCY (MHz)
0 250
2.80
2.70
2.85
2.75
2.90
2.95
3.00
50 100 150 200
2.65
2.60
2.55
2.50
N
O
I
S
E

S
P
E
C
T
R
A
L

D
E
N
S
I
T
Y

(
n
V
/



H
z
)
TPC 12. Noise Spectral Density (RTI) vs. Frequency
(R
L
= 150 , 3 V Supply, A
V
= 10 dB)
REV. B
AD8351
7
FREQUENCY (MHz)
0 250
8
4
10
6
12
14
16
25 50 75 100 125 150 175 200 225
2
0
O
U
T
P
U
T

1
d
B

C
O
M
P
R
E
S
S
I
O
N

(
d
B
m
)
R
L
= 150
VPOS = 5V
R
L
= 1k
R
L
= 150
VPOS = 3V
R
L
= 1k
TPC 13. Output Compression Point, P1 dB, vs. Frequency
(R
L
= 150 and 1 k, A
V
= 10 dB, at 3 V and 5 V Supplies)
GAIN RESISTOR ()
0 1000 100
8
4
10
6
12
14
16
2
0
O
U
T
P
U
T

1
d
B

C
O
M
P
R
E
S
S
I
O
N

(
d
B
m
)
VPOS = 5V
VPOS = 3V
TPC 14. Output Compression Point, P1 dB, vs. R
G
(f =
100 MHz, R
L
= 150 , A
V
= 10 dB, at 3 V and 5 V Supplies)
OUTPUT 1dB COMPRESSION (dB)
1
3
.
2
9
1
3
.
3
1
1
3
.
3
3
1
3
.
3
4
1
3
.
3
0
1
3
.
3
2
1
3
.
3
5
1
3
.
3
6
1
3
.
3
7
1
3
.
3
8
1
3
.
3
9
1
3
.
4
0
1
3
.
4
1
TPC 15. Output Compression Point Distribution
(f = 70 MHz, R
L
= 150 , A
V
= 10 dB)
FREQUENCY (MHz)
0 250
90
85
95
80
75
70
25 50 75 100 125 150 175 200 225
T
H
I
R
D
-
O
R
D
E
R

I
M
D

(
d
B
c
)
TPC 16. Third-Order Intermodulation Distortion vs.
Frequency for a 2 V p-p Composite Signal into R
L
= 1 k
(A
V
= 10 dB, at 5 V Supplies)
FREQUENCY (MHz)
0 250
70
65
75
60
55
50
25 50 75 100 125 150 175 200 225
T
H
I
R
D
-
O
R
D
E
R

I
M
D

(
d
B
c
)
TPC 17. Third-Order Intermodulation Distortion
vs. Frequency for a 2 V p-p Composite Signal into
R
L
= 150 (A
V
= 10 dB, at 5 V Supplies)
THIRD-ORDER INTERMODULATION DISTORTION (dBc)
68.0 68.2 68.4 68.6 68.6 68.8 69.0 69.2 69.4 69.6 69.8
TPC 18. Third-Order Intermodulation Distortion
Distribution (f = 70 MHz, R
L
= 150 , A
V
= 10 dB)
REV. B
8
AD8351
FREQUENCY (MHz)
10 1000 100
2000
1000
2500
1500
3000
3500
4000
500
0
I
M
P
E
D
A
N
C
E

M
A
G
N
I
T
U
D
E

(

)
0
25
50
75
100
P
H
A
S
E

(
d
e
g
)
TPC 19. Input Impedance vs. Frequency
FREQUENCY (MHz)
0 1000 100
120
100
130
110
140
150
160
I
M
P
E
D
A
N
C
E

M
A
G
N
I
T
U
D
E

(

)
30
15
10
5
0
I
M
P
E
D
A
N
C
E

P
H
A
S
E

(
d
e
g
)
20
25
TPC 20. Output Impedance vs. Frequency
FREQUENCY (MHz)
0 250
8
6
10
4
2
0
25 50 75 100 125 150 175 200 225
P
H
A
S
E

(
d
e
g
)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
G
R
O
U
P

D
E
L
A
Y

(
p
s
)
12
14
16
18
TPC 21. Phase and Group Delay (A
V
= 10 dB, at 5 V Supplies)
10MHz
3GHz
3GHz
10MHz
WITH
50
TERMINATIONS
WITHOUT
TERMINATIONS
500MHz
500MHz
TPC 22. Input Reflection Coefficient vs. Frequency
(R
S
= R
L
= 100 with and without 50 Terminations)
3GHz
10MHz
500MHz
TPC 23. Output Reflection Coefficient vs.
Frequency (R
S
= R
L
= 100 )
FREQUENCY (MHz)
80
20
0 1000
C
M
R
R

(
d
B
)
100 10
R
L
= 1k
R
L
= 150
70
60
40
50
30
TPC 24. Common-Mode Rejection Ratio,
CMRR (R
S
= 100 )
REV. B
AD8351
9
TIME (ns)
15 25
0.2
0.6
0
0.4
0.2
0.4
0.6
16 17 18 19 20 21 22 23 24
V
O
L
T
A
G
E

(
V
)
0pF
2pF
10pF
5pF
TPC 25. Transient Response under Capacitive
Loading (R
L
= 150 , C
L
= 0 pF, 2 pF, 5 pF, 10 pF)
TIME (ns)
0
5.0
5 10 15 20 25 30 35 40
O
U
T
P
U
T

(
V
)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
TPC 26. 2 Output Overdrive Recovery (R
L
= 150 , A
V
= 10 dB)
TIME (ns)
0 50
3
5 10 15 20 25 30 35 40 45
V
O
L
T
A
G
E

(
V
)
2
1
0
1
2
3
V
OUT
V
IN
TPC 27. Overdrive Recovery Using Sinusoidal Input
Waveform R
L
= 150 (A
V
= 10 dB, at 5 V Supplies)
TIME (ns)
0
V
O
L
T
A
G
E

(
V
)
0.75
0.25
0.50
1.00
1.00
0.50
0
0.25
0.75
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
TPC 28. Large Signal Transient Response for a
1 V p-p Output Step (A
V
= 10 dB, R
IP
= 25 )

TIME (ns)
0 15
5
3 6 9 12
S
E
T
T
L
I
N
G

(
%
)
2
1
0
1
2
5
3
4
4
3
TPC 29. 1% Settling Time for a 2 V p-p Step
(A
V
= 10 dB, R
L
= 150 )
REV. B
10
AD8351
BASIC CONCEPTS
Differential signaling is used in high performance signal chains,
where distortion performance, signal-to-noise ratio, and low power
consumption is critical. Differential circuits inherently provide
improved common-mode rejection and harmonic distortion perfor-
mance as well as better immunity to interference and ground noise.
VOCM 10
VPOS 9
OPHI
8
OPLO
7
COMM
6
1 PWUP
RGP1
2
INHI
3
INLO
4
RGP2
5
R
G
BALANCED
SOURCE
R
L
A
A
2A
Figure 1. Differential Circuit Representation
Figure 1 illustrates the expected input and output waveforms for
a typical application. Usually the applied input waveform will be
a balanced differential drive, where the signal applied to the INHI
and INLO pins are equal in amplitude and differ in phase by 180.
In some applications, baluns may be used to transform a single-
ended drive signal to a differential signal. The AD8351 may also be
used to transform a single-ended signal to a differential signal.
GAIN ADJUSTMENT
The differential gain of the AD8351 is set using a single external
resistor, R
G
, which is connected between Pins 2 and 5. The gain
can be set to any value between 0 dB and 26 dB using the resistor
values specified in TPC 2, with common gain values provided in
Table I. The board traces used to connect the external gain resis-
tor should be balanced and as short as possible to help prevent
noise pickup and to ensure balanced gain and stability. The low
frequency voltage gain of the AD8351 can be modeled as

A
R R R R
R R R R R R
V
V
V
L G F L
G L G L F G
OUT
IN
=
( ) +
+ + + ( ) + ( )
=
5 6 9 2
4 6 19 5 39
. .
. .
where: R
F
is 350 (internal).
R
L
is the single-ended load resistance.
R
G
is the gain setting resistor.
Table I. Gain Resistor Selection for Common Gain Values
(Load Resistance Is Specified as Single-Ended)
Gain, A
V
R
G
(R
L
= 75 ) R
G
(R
L
= 500 )
0 dB 680 2 k
6 dB 200 470
10 dB 100 200
20 dB 22 43
COMMON-MODE ADJUSTMENT
The output common-mode voltage level is the dc offset voltage
present at each of the differential outputs. The ac signals are of
equal amplitude with a 180 phase difference but are centered
at the same common-mode voltage level. The common-mode
output voltage level can be adjusted from 1.2 V to 3.8 V by
driving the desired voltage level into the VOCM pin, as illus-
trated in Figure 2.

VOCM 10
VPOS 9
OPHI
8
OPLO
7
COMM
6
1 PWUP
RGP1
2
INHI
3
INLO
4
RGP2
5
R
G
BALANCED
SOURCE
R
L
0.1F
V
S
V
OCM
1.2V
TO
3.8V
C
DECL
0.1F
Figure 2. Common-Mode Adjustment
INPUT AND OUTPUT MATCHING
The AD8351 provides a moderately high differential input
impedance of 5 k. In practical applications, the input of the
AD8351 will be terminated to a lower impedance to provide an
impedance match to the driving source, as depicted in Figure 3.
The terminating resistor, R
T
, should be as close as possible to
the input pins in order to minimize reflections due to imped-
ance mismatch. The 150 output impedance may need to be
transformed to provide the desired output match to a given
load. Matching components can be calculated using a Smith
Chart or by using a resonant approach to determine the match-
ing network that results in a complex conjugate match. The
input and output impedances and reflection coefficients are
provided in TPCs 19, 20, 22, and 23. For additional informa-
tion on reactive matching to differential sources and loads, refer
to the Applications section of the AD8350 data sheet.
Figure 3 illustrates a SAW (surface acoustic wave) filter inter-
face. Many SAW filters are inherently differential, allowing for a
low loss output match. In this example, the SAW filter requires
a 50 source impedance in order to provide the desired center
frequency and Q. The series L shunt C output network provides
a 150 to 50 impedance transformation at the desired frequency
of operation. The impedance transformation is illustrated on a Smith
Chart in Figure 4.
It is possible to drive a single-ended SAW filter simply by con-
necting the unused output to ground using the appropriate
terminating resistance. The overall gain of the system will be
reduced by 6 dB due to the fact that only half of the signal will
be available to the input of the SAW filter.
BALANCED
SOURCE
R
S
R
S
R
S
= R
T
R
T
R
T
0.1F
0.1F
R
G
0.1F
0.1F
150
C
P
8pF
L
S
27nF
L
S
27nF
50
190MHz SAW
VPOS
AD8351
Figure 3. Example of Differential SAW Filter Interface (f
C
= 190 MHz)
REV. B
AD8351
11
200
0
50 150
SERIES L
SHUNT C
500
100
50
25
10
200
100
500
50
25
10
Figure 4. Smith Chart Representation of SAW
Filter Output Matching Network
50
50
AD8351
R
G
0.1F
25
R
F
0.1F
0.1F
R
L
0.1F
Figure 5. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-to-
differential gain block, as illustrated in Figure 5. The input signal
is ac-coupled and applied to the INHI input. The unused input is
ac-coupled to ground. The values of C1 through C4 should be
selected such that their reactances are negligible at the desired
frequency of operation. To balance the outputs, an external feed-
back resistor, R
F
, is required. To select the gain resistor and the
feedback resistor, refer to Figures 6a and 6b. From Figure 6a,
select an R
G
for the required dB gain at a given load. Next, select
from Figure 6b an R
F
resistor for the selected R
G
and load.
Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. TPCs 10
and 11 show the second and third harmonic distortion perfor-
mance when driving the input of the AD8351 using a single-ended
50 source.
R
G
()
0 1000
G
A
I
N

(
d
B
)
10
0
15
5
35
20
25
30
100
R
L
= 500
R
L
= 1000
R
L
= 150
Figure 6a. Gain Selection
R
G
()
0 1000
R
F

(
k

)
2
0
3
1
7
4
5
6
100
R
L
= 150
R
L
= 1000
R
L
= 500

Figure 6b. Feedback Resistor Selection
ADC DRIVING
The circuit in Figure 7 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D
converter. For optimum performance, the AD6645 and the
AD8351 are driven differentially. The resistors R1 and R2 present
a 50 differential input impedance to the source with R3 and R4
providing isolation from the A/D input. The gain setting resistor
for the AD8351 is R
G
. The AD6645 presents a 1 k differential
load to the AD8351 and requires a 2.2 V p-p differential signal
between AIN and AIN for a full-scale output. This AD8351
circuit then provides the gain, isolation, and source matching for
the AD6645. The AD8351 also provides a balanced input, not
provided by the balun, to the AD6645, which is essential for
second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (10) of the
AD8351 to the VREF pin of the AD6645 sets the common-mode
output voltage of the AD8351 at 2.4 V. This voltage is bypassed
with a 0.1 F capacitor. Increasing the gain of the AD8351 will
increase the system noise and thus decrease the SNR but will
not significantly affect the distortion. The circuit in Figure 7 can
provide SFDR performance of better than 90 dBc with a 10 MHz
input and 80 dBc with a 70 MHz input at a gain of 10 dB.
BALANCE
50
SOURCE
25
100nF
25
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25 DIGITAL
OUT
AD6645
AIN
AIN VREF
Figure 7. ADC Driving Application Using Differential Input
The circuit of Figure 8 represents a single-ended input to differ-
ential output configuration of the AD8351 driving the AD6645.
In this case, R1 provides the input impedance. R
G
is the gain
setting resistor. The resistor R
F
is required to balance the output
voltages required for second-order cancellation by the AD6645
and can be selected using a chart. (See the Single-Ended-to-
Differential Operation section.) The circuit depicted in Figure 8
can provide SFDR performance of better than 90 dBc with a
10 MHz input and 77 dBc with a 70 MHz input.
REV. B
12
AD8351
SINGLE-
ENDED
50
SOURCE
R1
50
100nF
25 100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25 DIGITAL
OUT
AD6645
AIN
AIN VREF
100nF
R
F
Figure 8. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications
where it is desirable to select multiple high speed signals. The
isolation of each device when in a disabled state (PWUP pin pulled
low) is about 60 dBc for the maximum input level of 0.5 V p-p out
to 100 MHz. The low output noise spectral density allows for a
simple implementation as depicted in Figure 9. The PWUP inter-
face can be easily driven using most standard logic interfaces. By
using an N-bit digital interface, up to N devices can be controlled.
Output loading effects and noise need to be considered when using
a large number of input signal paths. Each disabled AD8351 pre-
sents approximately a 700 load in parallel with the 150 output
source impedance of the enabled device. As the load increases due
to the addition of N devices, the distortion performance will degrade
due to the heavier loading. Distortion better than 70 dBc can be
achieved with four devices muxed into a 1 k load for signal fre-
quencies up to 70 MHz.
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 1
OPLO
OPHI
BIT 1
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT 2
OPLO
OPHI
BIT 2
PWUP
AD8351
INHI
R
G
RGP1
RGP2
INLO
SIGNAL
INPUT N
OPLO
OPHI
BIT N
PWUP
MUX
OUTPUT
LOAD
N-BIT
DIGITAL
INTERFACE
Figure 9. Using Several AD8351s to Form an
N-Channel Analog MUX
I/O CAPACITIVE LOADING
Input or output direct capacitive loading greater than a few pico-
farads can result in excessive peaking and/or oscillation outside
the pass band. This results from the package and bond wire induc-
tance resonating in parallel with the input/output capacitance of
the device and the associated coupling that results internally
through the ground inductance. For low resistive load or source
resistance, the effective Q is lower, and higher relative capaci-
tance termination(s) can be allowed before oscillation or excessive
peaking occurs. These effects can be eliminated by adding series
input resistors (R
IP
) for high source capacitance, or series output
resistors (R
OP
) for high load capacitance. Generally less than
25 is all that is required for I/O capacitive loading greater than
~2 pF. The higher the C, the smaller the R parasitic suppression
resistor required. In addition, R
IP
also helps to reduce low gain
in-band peaking, especially for light resistive loads.

AD8351
R
L
1k
C
STRAY
C
STRAY
R
IP
R
IP
R
G
R
OP
R
OP
C
L
C
L
Figure 10. Input and Output Parasitic Suppression
Resistors, R
IP
and R
OP
, Used to Suppress
Capacitive Loading Effects
Due to package parasitic capacitance on the R
G
ports, high R
G
values (low gain) cause high ac-peaking inside the pass band,
resulting in poor settling in the time domain. As an example,
when driving a 1 k load, using 25 for R
IP
reduces the peaking
by ~7 dB for R
G
equal to 200 (A
V
= 10 dB) (see Figure 11).

Figure 11. Reducing Gain Peaking with Parasitic
Suppressing Resistors (R
IP
= 25 , R
L
= 1 k)
REV. B
AD8351
13
It is important to ensure that all I/O, ground, and R
G
port traces
be kept as short as possible. In addition, it is required that the
ground plane be removed from under the package. Due to the
inverse relationship between the gain of the device and the value
of the R
G
resistor, any parasitic capacitance on the R
G
ports can
result in gain-peaking at high frequencies. Following the precau-
tions outlined in Figure 12 will help to reduce parasitic board
capacitance, thus extending the devices bandwidth and reducing
potential peaking or oscillation.
COPLANAR
WAVEGUIDE
OR STRIP
2
1
3
4
5
9
10
8
7
6
R
T
R
IP
R
T
R
IP
R
G
R
OP
R
OP
Hi-Z
AGND
AGND
Figure 12. General Description of Recommended
Board Layout for High-Z Load Conditions
TRANSMISSION LINE EFFECTS
As noted, stray transmission line capacitance, in combination with
package parasitics, can potentially form a resonant circuit at high
frequencies, resulting in excessive gain peaking. R
F
transmission
lines connecting the input and output networks should be designed
such that stray capacitance is minimized. The output single-ended
source impedance of the AD8351 is dynamically set to a nominal
value of 75 . Therefore, for a matched load termination, the
characteristic impedance of the output transmission lines should be
designed to be 75 . In many situations, the final load impedance
may be relatively high, greater than 1 k. It is suggested that the
board be designed as shown in Figure 12 for high impedance load
conditions. In most practical board designs, this requires that
the printed-circuit board traces be dimensioned to a small width
(~5 mils) and that the underlying and adjacent ground planes are
far enough away to minimize capacitance.
Typically the driving source impedance into the device will be
low and terminating resistors will be used to prevent input reflec-
tions. The transmission line should be designed to have the
appropriate characteristic impedance in the low-Z region. The
high impedance environment between the terminating resistors
and device input pins should not have ground planes under-
neath or near the signal traces. Small parasitic suppressing
resistors may be necessary at the device input pins to help desensitize
(de-Q) the resonant effects of the device bond wires and
surrounding parasitic board capacitance. Typically, 25 series
resistors (size 0402) adequately de-Q the input system without a
significant decrease in ac performance.
Figure 13 illustrates the value of adding input and output series
resistors to help desensitize the resonant effects of board parasitics.
Overshoot and undershoot can be significantly reduced with the
simple addition of R
IP
and R
OP
.
TIME (ns)
0 4
V
O
L
T
A
G
E

(
V
)
0.5
1.5
0
1.0
1.5
0.5
1 3
1.0
2
R
IP
= R
OP
= 25
NO R
IP
OR R
OP
R
OP
= 25
Figure 13. Step Response Characteristics with and
without Input and Output Parasitic Suppression Resistors
CHARACTERIZATION SETUP
The test circuit used for 150 and 1 k load testing is provided
in Figure 14. The evaluation board uses balun transformers to
simplify interfacing to single-ended test equipment. Balun effects
need to be removed from the measurements in order to accu-
rately characterize the performance of the device at frequencies
exceeding 1 GHz.
The output L-pad matching networks provide a broadband
impedance match with minimum insertion loss. The input
lines are terminated with 50 resistors for input impedance
matching. The power loss associated with these networks needs
to be accounted for when attempting to measure the gain of the
device. The required resistor values and the appropriate inser-
tion loss and correction factors used to assess the voltage gain
are provided in Table II.
Table II. Load Conditions Specified Differentially
Conversion
Total Factor
Load Insertion 20 log (S21)
Condition R1 R2 Loss to 20 log (A
V
)
150 43.2 86.6 5.8 dB 7.6 dB
1 k 475 52.3 15.9 dB 25.9 dB
BALANCED
SOURCE
R
S
50
0.1nF
0.1nF
100nF
R
LOAD
R
S
50
R
T
50
R
T
50
50 CABLE
50 CABLE
AD8351
DUT
R1
100nF
50 CABLE
50 CABLE
R1
R2
R2
50
50
50 TEST
EQUIPMENT
Figure 14. Test Circuit
REV. B
14
AD8351
EVALUATION BOARD
An evaluation board is available for experimentation. Various
parameters such as gain, common-mode level, and input and
output network configurations can be modified through minor
resistor changes. The schematic and evaluation board artwork
are presented in Figures 15, 16, and 17.
Figure 16. Component Side Layout
Figure 17. Component Side Silkscreen
2
1
3
4
5
9
10
8
7
6
PWUP VOCM
RGP1 VPOS
INHI OPHI
INLO OPLO
RGP2 COMM
AD8351
10 PIN mSOIC
R2
24.9
R1
100
R7
0
R5
0
R8
0
R4
24.9
R3
OPEN
R12
0
J1
RF_IN+
J2
RF_IN
R15
0
R16
0
C6
100nF
C7
100nF
R10
61.9
T2
1:1
ETC1-1-13
(MACOM)
R14
0
R13
OPEN
R11
61.9
R9
61.9
J3
RF_OUT+
J4
RF_OUT
C3
0.1F
R6
OPEN
R17
0
C2
100nF
AGND
VPOS
E
N
B
L
V
C
O
M
V
P
O
S
A
C
O
M
P1
R18
0
W1
C4
100nF
C5
100nF
T1
1:1
ETC1-1-13
(MACOM)
C10
100nF
C9
100nF
T3
1:1
ETC1-1-13
(MACOM)
J5
TEST IN2
T4
1:1
ETC1-1-13
(MACOM)
J6
TEST OUT2
Figure 15. Evaluation Board Schematic
REV. B
AD8351
15
Table III. Evaluation Board Configuration Options
Component Function Default Condition
P1-1, P1-2, Supply and Ground Pins. Not Applicable
VPOS, AGND
P1-3 Common-Mode Offset Pin. Allows for monitoring or adjustment of the Not Applicable
output common-mode voltage.
W1, R7, P1-4, R17, R18 Device Enable. Configured such that switch W1 disables the device when W1 = Installed
Pin 1 is set to ground. Device can be disabled remotely using Pin 4 of R7 = 0 (Size 0603)
header P1. R17 = R18 = 0 (Size 0603)
R2, R3, R4, R5, R8, R12, Input Interface. R3 and R12 are used to ground one side of the differential R2 = R4 = 24.9 (Size 0805)
T1, C4, C5 drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio R3 = Open (Size 0603)
balun used to transform a single-ended input into a balanced differential R5 = R8 = R12 = 0
signal. R2 and R4 are used to provide a differential 50 input termination. (Size 0603)
R5 and R8 can be increased to reduce gain peaking when driving from a high C4 = C5 = 10 0 nF (Size 0603)
source impedance. The 50 termination provides an insertion loss of 6 dB. T1 = Macom
TM
ETC1-1-13
C4 and C5 are used to provide ac coupling.
R9, R10, R11, R13, R14, Output Interface. R13 and R14 are used to ground one side of the differential R9 = R10 = 61.9 (Size 0603)
R15, R16, T2, C4, C5, output interface for single-ended applications. T2 is a 1-to-1 impedance ratio R11 = 61.9 (Size 0603)
C6, C7 balun used to transform a balanced differential signal into a single-ended R13 = Open (Size 0603)
signal. R9, R10, and R11 are provided for generic placement of matching R14 = 0 (Size 0603)
components. R15 and R16 allow additional output series resistance when R15 = R16 = 0 (Size 0402)
driving capacitive loads. The evaluation board is configured to provide a C4 = C5 = 100 nF (Size 0603)
150 to 50 impedance transformation with an insertion loss of 9.9 dB. C6 = C7 = 100 nF (Size 0603)
C4 through C7 are used to provide ac coupling. T2 = Macom ETC1-1-13
R1 Gain Setting Resistor. Resistor R1 is used to set the gain of the device. R1 = 100 (Size 0603)
Refer to TPC 2 when selecting gain resistor. When R1 is 100 , the
overall system gain of the evaluation board will be approximately 6 dB.
C2 Power Supply Decoupling. The supply decoupling consists of a 100 nF C2 = 100 nF (Size 0805)
capacitor to ground.
R6, C3, P1-3 Common-Mode Offset Adjustment. Used to trim common-mode output R6 = 0 (Size 0603)
level. By applying a voltage to Pin 3 of header P1, the output common- C3 = 0.1 F (Size 0805)
mode voltage can be directly adjusted. Typically decoupled to ground
using a 0.1 F capacitor.
T3, T4, C9, C10 Calibration Networks. Calibration path provided to allow for compensation T3 = T4 = Macom
of the insertion loss of the baluns and the reactance of the coupling capacitors. ETC1-1-13
C9 = C10 = 100 nF
(Size 0603)
REV. B
C
0
3
1
4
5

2
/
0
4
(
B
)
16
AD8351
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.23
0.08
0.80
0.60
0.40
8
0
0.15
0.00
0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5 1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Revision History
Location Page
2/04Data Sheet changed from REV. A to REV. B.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3/03Data Sheet changed from REV. 0 to REV. A.
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15