FET

Introduction
A transistor is a linear semiconductor device that
controls current with the application of a lower-power
electrical signal. Transistors may be roughly grouped into
two major divisions: bipolar and field-effect.

A Field-Effect Transistor is a device utilizing a small
voltage to control current.
All field-effect transistors are unipolar rather than
bipolar devices. That is, the main current through them is
comprised either of electrons through an N-type
semiconductor or holes through a P-type semiconductor.
This becomes more evident when a physical diagram of the
device is seen:



A FET is a voltage-controlled device. A d so, its output
characteristics are controlled by input voltage and not
input current.







CLASSIFICATION

Depending upon the constructional features and operating
principles, FETs are broadly classified into two types of
field-effect transistors.

1) Junction Field Effect Transistor (JFET)
2) Metal Oxide Semiconductor Field Effect Transistor
(MOSFET) or Insulated Gate Field-Effect Transistor
(IGFET).


Both of these types can further be divided into n-
channel and p-channel.

This can be better understood through the tree-structure
diagram given below.



<Tree diagram, approx. half page>





STRUCTURE OF FET

The Field Effect Transistor can further be divided,
depending upon their structure, into following two
categories:

(i) p-channel FET
(ii) n-channel FET

The basic construction of an n-channel FET is shown in the
figure given below.
It consists of an n-type semiconductor substrate (a very
lightly doped bar which is used as a channel) with two p-
type heavily doped regions diffused on opposite sides of
its middle part.
The p-type region forms two p-n junctions. The space
between the junctions (i.e.; n-type region) is called
a Channel. Both the p-type regions are connected
internally and a single wire is taken out in the form
of a terminal called the Gate (G). The electrical
connections are made to both the ends of the n-type
semiconductor and are taken out in the form of two
terminals called the Drain (D) and the Source (S).


Thus a typical structure of a junction field-effect
transistor consists of four basic elements:

Source: The source S is the terminal through which the
majority carriers enter the bar. Conventional current
entering the bar at S is designated by I
s.


Drain: The drain D is the terminal through which the
majority carriers leave the bar. Conventional currents
entering the bar at D are designated by I
D
. The drain to
source voltage V
DS
is positive when drain is more positive
than source.

Gate: On both the sides of n-type bar, heavily doped p-
region of acceptor impurities have been formed by alloying
or y diffusion, or by any other means. These impurity
regions are called the gate G. Between the gate and the
source a reverse bias voltage-V
GS
- is applied. The
conventional current entering the bar at G is designated
by I
G
.

Channel: The region of n-type material between two gate
regions is the channel through which the majority carriers
move from source to drain.








The current carriers in p-channel FET are holes while in
the n-channel FET, current is carried by the electrons.
The operation of p-channel FET is similar to that of n-
channel except that all voltages and currents are reversed
in direction.

Generally, N-channel JFETs are more commonly used than P-
channel.

With no voltage applied between gate and source, the
channel is a wide-open path for electrons to flow.
However, if a voltage is applied between gate and source
of such polarity that it reverse-biases the PN junction,
the flow between source and drain connections becomes
limited, or regulated. Maximum gate-source voltage
"pinches off" all current through source and drain, thus
forcing the JFET into cutoff mode. This behavior is due to
the depletion region of the PN junction expanding under
the influence of a reverse-bias voltage, eventually
occupying the entire width of the channel if the voltage
is great enough.

This is analogous to a flow of water through a hose-pipe.



The applied voltage V
DS
, from drain to source, is like the
water pressure that will establish the flow of
electrons (similar to water in the pipe) from the
source. The gate through an applied potential
which controls the flow of water (i.e.; here charge)
to the drain.

The drain and source terminals are made by ohmic
conductors at the end of the n-type semiconductor bar.
Majority-carriers i.e.; electrons can be made to flow
along bar by the means of voltage applied between drain
and source.

The third terminal, called Gate, is formed by electrically
connecting the source shallow p+ regions. The n-type
region between the two p+ gates is called the Channel
through which the majority carriers move between source
and drain. The top view shown below indicates how the
aluminum contacts are made by to the source, drain and
gate regions.




<Space for the diagram>



We observe that the gate regions and the channel
constitute a p-n junction which, in FET operation, is
maintained in a reverse-biased state. Of the two sides of
the reverse-biased p-n junction there is space-charge
region (the depletion region).

The current carriers have diffused across the junction,
leaving only uncovered positive ions on the n-side and
negative ions on the p-side. As the reverse bias across
the junction increases, the thickness of the region of
immobile uncovered charge increases. Its conductivity is
normally zero due to the unavailability of current
carriers. So the effective width of the channel, according
to the figure on the next page, will decrease with an
increase in the reverse bias.
At a gate-to-source voltage V
GS
=V
P
, called the pinch-off
voltage, the channel width is reduced to zero due to the
removal of all the charge carriers form the channel.
Accordingly, for a fixed drain-to-source voltage, the
drain current will be a function of the reverse-biased
voltage across the gate junction.
The term field effect describes this device because
the mechanism of current control is the effect of the
extension, with increasing reverse-bias voltage of the
field associated with the depletion region.



<Space for the diagram>








The value of drain current I
D
in the ohmic region is
obtained from the cross-sectional view of FET as shown in
the figure above. In this figure, 2a is the maximum
channel width for V
GS
=0 and decreases as V
GS
is made more
and more negative.



<Space for the diagram>


<Figure caption>: Biased n-channel FET structure showing
depletion region constricting the channel.

For very small V
DS,
the depletion region can be taken to be
uniform, so that the channel cross-sectional area A will
be constant throughout its length.
Hence A=2b(x) where 2b(x) is the channel width
corresponding to zero drain current for a specified V
GS
and
W is the channel dimension perpendicular to b-direction.


MOSFET(Metal Oxide Semiconductor Field Effect Transistor)

The MOSFET transistor has become one of the most important
devices in the design and construction of integrated
circuits for digital computers. Its thermal stability and
other general characteristics make it extremely popular in
computer circuit design.

MOSFET is further divided into n-channel and p-channel
MOSFET.
The characteristics and properties of depletion-type
MOSFETs are same as those of JFETs. But the properties of
enhancement-type MOSFET and JFET are quite different.







Difference between MOSFET and JFET

The basic difference between enhancement-type and
depletion-type MOSFETs is that in the depletion-type
MOSFET the channel is already formed while in the
enhancement-type MOSFET the channel is not initially
formed.
Another important difference is that the depletion gate is
always reverse-biased with the drain, in the depletion-
type. However, in the enhancement-type MOSFET gate is
forward biased with the drain. Thats why with increasing
the gate voltage the drain current increases i.e.; gets
enhanced. Thats why it is called enhancement MOSFET.
One more difference between them is that in MOSFET there
is no direct electrical connection between the gate and
the channel. This is due to the fact that MOSFET
transistor uses an additional insulator layer of SiO
2

which provides good electrical isolation. Thats why the
input impedance of MOSFET is very high as compared to the
JFET.


STRUCTURE OF ENHANCEMENT TYPE MOSFET

The structure of n-channel Enhancement-type MOSFET is
shown below.
The structure consists of a moderately doped p-type Si
substrate into which two heavily doped n-regions, the
source and the drain, are diffused. Between the two
regions there is a narrow region of p-type substrate,
called the channel, which is covered by insulating layer
of SiO
2
, called gate oxide.
Why is SiO
2
layer used as a dielectric?
It provides better electrical isolation between gate
and channel.
Due to better electrical isolation its input impedance
becomes very large; this is very good to overcome the
lauding effect.





<Space for diagram>








Over this oxide layer is a layer of polycrystalline
silicon (Polysilicon) electrode, referred to as the
gate. Polycrystalline silicon is silicon that is not
composed of a single crystal. Since the oxide layer is an
insulator, the DC current from the gate to channel is
essentially zero. Because of the inherently symmetry of
the structure, there is no physical distinction between
the drain and source region.



STRUCTURE OF DEPLETIONTYPE MOSFET
The main difference between the depletion-type and
enhancement-type MOSFETs is that, the former has a
physically implanted channel or, in other words, the
channel already exists in depletion-type MOSFET.
It means that If a voltage V
DS
is applied between the drain
and the source terminal, a current i
D
flows for V
GS
=0 volt.
OR, we can say that, there is no need to induce a channel,
unlike the case of enhancement MOSFET.

The diagram, in the figure (a), below shows that the
circuit symbol for n-channel depletion-type MOSFET. This
symbol differs from that of the enhancement type device in
only one respect i.e. ; the virtual line representing the
channel is solid, signifying the existence of a physical
channel.
When the Body (B) is connected to Source(S) the simplified
symbol shown in the figure (b) can be used.




<Space for diagram>