LM555/NE555/SA555

Single Timer
ww w .f a irchil d se m i.c o m
Features
High Current Drive Capability (200mA)
Adjustable Duty Cycle
Temperature Stability ! 0"00#$%C
Timing &rm Sec t Hurs
Turn !! Time 'ess Than 2Sec
Applications
(recisin Timing
(ulse )eneratin
Time Delay )eneratin
Se*uential Timing
Description
The '+###%,-###%SA### is a highly stable cntrller
capable ! prducing accurate timing pulses" .ith
mnstable peratin/ the time delay is cntrlled by ne
e0ternal resistr and ne capacitr" .ith astable peratin/
the !re*uency and duty cycle are accurately cntrlled 1ith
t1 e0ternal resistrs and ne capacitr"
8-DIP
1
8-SOP
1
Internal Block Diagram
GND
1
R R R
8 Vcc
Trigger 2
Comp.
Discharging Tr.
7
Discharge
Output 3
OutPut
Stage
!
Comp.
"
Thresho#$
Reset %
Vre&
Contro#
'
Vo#tage
Rev. 1.0.2
2002 Fairchild Semiconductor Corporation
!"""#$%"""#SA"""
&
A'solute !a(imum )atings *+
A
, &"-.
Parameter S/m'ol 0alue 1nit
Supply Voltage VCC 16 V
Lead Temperature Soldering 10!ec" T
L#$% &00 C
'o(er %i!!ipation '
% 600 m)
*perating Temperature Range
L+,,,-.#,,,
S$,,,
T*'R
0 / 010
230 / 04,
C
Storage Temperature Range T
ST5 26, / 01,0 C
2
!"""#$%"""#SA"""
%lectrical -haracteristics
T$ 6 2,C7 VCC 6 , / 1,V7 unle!! other(i!e !peci8ied"
Parameter S/m'ol -onditions !in. +/p. !a(. 1nit
Supply Voltage V
CC 2 3., 2 16 V
Supply Current 9
1
Lo( Sta:le" ;
CC
VCC 6 ,V7 RL 6 2 & 6 m$
V
CC
6 1,V7 R
L
6 2 1., 1, m$
Timing #rror 9
2
+ono!ta:le"
;nitial $ccuracy
%ri8t (ith Temperature
%ri8t (ith Supply Voltage
$CC<R
t-T
t-VCC
R
$
6 1= to100=
C 6 0.1F
2 1.0
,0
0.1
&.0
0.,
>
ppm-C
>-V
Timing #rror 9
2
$!ta:le"
;ntial $ccuracy
%ri8t (ith Temperature
%ri8t (ith Supply Voltage
$CC<R
t-T
t-VCC
R$ 6 1= to 100=
C 6 0.1F
2
2.2,
1,0
0.&
2 >
ppm-C
>-V
Control Voltage VC
V
CC
6 1,V ?.0 10.0 11.0 V
V
CC
6 ,V 2.6 &.&& 3.0 V
Thre!hold Voltage VT@
VCC 6 1,V 2 10.0 2 V
V
CC
6 ,V 2 &.&& 2 V
Thre!hold Current 9
&
;
T@ - 2 0.1 0.2, $
Trigger Voltage VTR
VCC 6 ,V 1.1 1.61 2.2 V
V
CC
6 1,V 3., , ,.6 V
Trigger Current ;
TR
V
TR
6 0V 0.01 2.0 $
Re!et Voltage VRST - 0.3 0.1 1.0 V
Re!et Current ;
RST - 0.1 0.3 m$
Lo( *utput Voltage V*L
VCC 6 1,V
;S;.A 6 10m$
;S;.A 6 ,0m$
2 0.06
0.&
0.2,
0.1,
V
V
V
CC
6 ,V
;
S;.A
6 ,m$
2 0.0, 0.&, V
@igh *utput Voltage V
*@
VCC 6 1,V
;S*<RC# 6 200m$
;S*<RC# 6 100m$ 12.1,
12.,
1&.&
2 V
V
V
CC
6 ,V
;S*<RC# 6 100m$
2.1, &.& 2 V
Ri!e Time o8 *utput tR - 2 100 2 n!
Fall Time o8 *utput t
F - 2 100 2 n!
%i!charge Lea=age Current ;
LA5 - 2 20 100 n$
$otes3
1. Supply current (hen output i! high i! typically 1m$ le!! at VCC 6 ,V
2. Te!ted at V
CC
6 ,.0V and V
CC
6 1,V
&. Thi! (ill determine maBimum value o8 R$ 0 RC 8or 1,V operation7 the maB. total R 6 20+7 and 8or ,V operation the
maB. total R 6 6.1+
C
a
p
a
c
i
t
a
n
c
e
(
u

)
1
4
!"""#$%"""#SA"""
Application Information
Ta:le 1 :elo( i! the :a!ic operating ta:le o8 ,,, timerD
+a'le 5. Basic Operating +a'le
+hreshold 0oltage
*0
th
.*PI$ 6.
+rigger 0oltage
*0
tr
.*PI$ &.
)eset*PI$ 4. Output*PI$ 2.
Discharging +r.
*PI$ 7.
%onEt care %onEt care Lo( Lo( *.
Vth F 2Vcc - & Vth F 2Vcc - & @igh Lo( *.
Vcc - & G Vth G 2 Vcc - & Vcc - & G Vth G 2 Vcc - & @igh 2 2
Vth G Vcc - & Vth G Vcc - & @igh @igh *FF
.hen the l1 signal input is applied t the reset terminal/ the timer utput remains l1 regardless ! the threshld vltage r
the trigger vltage" 2nly 1hen the high signal is applied t the reset terminal/ timer3s utput changes accrding t
threshld vltage and trigger vltage"
.hen the threshld vltage e0ceeds 2%4 ! the supply vltage 1hile the timer utput is high/ the timer3s internal discharge
Tr" turns n/ l1ering the threshld vltage t bel1 5%4 ! the supply vltage" During this time/ the timer utput is
maintained l1" 'ater/ i! a l1 signal is applied t the trigger vltage s that it becmes 5%4 ! the supply vltage/ the
timer3s internal discharge Tr" turns !!/ increasing the threshld vltage and driving the timer utput again at high"
5. !onosta'le Operation
0Vcc
3 4
R$
1*
2
Trigger
R#S#T Vcc
1*
%;SC@
1
2 TR;5
& *<T
RL
5.%
1
T@R#S
6
C1
C*.T
,
C2
1*
*
1*
+1
1*
+2
1*
+3
1*
+'
1*
+%
1*
+3
1*
+2
1*
+1
1*
*
1*
1
1*
2
Time De#a,(s)
Figure 5. !onoata'le -ircuit Figure &. )esistance and -apacitance 8s.
+ime dela/*td.
Figure 2. 9a8eforms of !onosta'le Operation
(R
-
.2R
/
)
C
a
p
a
c
i
t
a
n
c
e
(
u

)
&igure 5 illustrates a mnstable circuit" 6n this mde/ the timer generates a !i0ed pulse 1henever the trigger vltage !alls
bel1 7cc%4" .hen the trigger pulse vltage applied t the 82 pin !alls bel1 7cc%4 1hile the timer utput is l1/ the
timer3s internal !lip9!lp turns the discharging Tr" !! and causes the timer utput t becme high by charging the e0ternal
capacitr C5and setting the !lip9!lp utput at the same time"
The vltage acrss the e0ternal capacitr C5/ 7
C5
increases e0pnentially 1ith the time cnstant t:;
A
<C and reaches
27cc%4 at td:5"5;
A
<C" Hence/ capacitr C5 is charged thrugh resistr ;
A
" The greater the time cnstant ;
A
C/ the lnger
it ta=es !r the 7
C5
t reach 27cc%4" 6n ther 1rds/ the time cnstant ;
A
C cntrls the utput pulse 1idth"
.hen the applied vltage t the capacitr C5 reaches 27cc%4/ the cmparatr n the trigger terminal resets the !lip9!lp/
turning the discharging Tr" n" At this time/ C5 begins t discharge and the timer utput cnverts t l1"
6n this 1ay/ the timer perating in mnstable repeats the abve prcess" &igure 2 sh1s the time cnstant relatinship
based
n ;
A
and C" &igure 4 sh1s the general 1ave!rms during mnstable peratin"
6t must be nted that/ !r nrmal peratin/ the trigger pulse vltage needs t maintain a minimum ! 7cc%4 be!re the timer
utput turns l1" That is/ althugh the utput remains una!!ected even i! a di!!erent trigger pulse is applied 1hile the utput
is high/ it may be a!!ected and the 1ave!rm nt perate prperly i! the trigger pulse vltage at the end ! the utput pulse
remains at bel1 7cc%4" &igure > sh1s such timer utput abnrmality"
Figure 4. 9a8eforms of !onosta'le Operation *a'normal.
&. Asta'le Operation
0Vcc
1**
R
$
3 4
1*
R#S#T Vcc
%;SC@
1
1
2 TR;5
RC
T@R#S 6
*.1
& *<T
RL
5.%
1
C*.T ,
C1
C2
*.*1
10+3
1**m 1 1* 1** 11 1*1 1**1
re2uenc,(34)
Figure ". Asta'le -ircuit
Figure 6. -apacitance and )esistance 8s. Fre:uenc/
? e
Figure 7. 9a8eforms of Asta'le Operation
An astable timer peratin is achieved by adding resistr ;
@
t &igure 5 and cn!iguring as sh1n n &igure #" 6n astable
peratin/ the trigger terminal and the threshld terminal are cnnected s that a sel!9trigger is !rmed/ perating as a
multi
vibratr" .hen the timer utput is high/ its internal discharging Tr" turns !! and the 7
C5
increases by e0pnential
!unctin 1ith the time cnstant (;AA;@)<C"
.hen the 7
C5
/ r the threshld vltage/ reaches 27cc%4/ the cmparatr utput n the trigger terminal becmes high/
resetting the &%& and causing the timer utput t becme l1" This in turn turns n the discharging Tr" and the C5
discharges
thrugh the discharging channel !rmed by ;
@
and the discharging Tr" .hen the 7
C5
!alls bel1 7cc%4/ the cmparatr
utput n the trigger terminal becmes high and the timer utput becmes high again" The discharging Tr" turns !! and
the
7
C5
rises again"
6n the abve prcess/ the sectin 1here the timer utput is high is the time it ta=es !r the 7
C5
t rise !rm 7cc%4 t 27cc%4/
and the sectin 1here the timer utput is l1 is the time it ta=es !r the 7
C5
t drp !rm 27cc%4 t 7cc%4" .hen timer
utput
is high/ the e*uivalent circuit !r charging capacitr C5 is as !ll1sB
;
A
;
@
7cc
C5 7c5(09):7cc%4
dv
c1
V
cc
? V( 02)
C
1
999
dt
999 : 99
R
999
A R
( 1 )
9999999 99999999999999999999999999
$ C
V
C1
( 00) : V
CC
&
( 2 )
V
C1
t :


2

999

t

2 ?
999999999999999999999999999999999999


( R
$
A R
C
) C1

( & )
(

)
V
CC

1
&

Since the duratin ! the timer utput high state(t
H
) is the amunt ! time it ta=es !r the 7
C5
(t) t reach 27cc%4/
999999
C1
: V
99999
2
$
&

t
@

2

2
2 ? 999999999999999999999999999999999999

( R
$
A R
C
) C1

: 999 V
CC
: V
CC

1 ? 999 e
( 3 )

V
C1
( t )
&

&

t
@
: C
1
(R
$
A R
C
);n2 : 0.6?&( R
$
A R
C
)C
1
( ,)
The e*uivalent circuit !r discharging capacitr C5 1hen timer utput is l1 as !ll1sB
;
@
C5 7
C5
(09):27cc%4 ;
D
dv
C1
9999999999 A 99999999
1
99999999 V :
0
( 6 )
C
1
999
dt 9 R
$
A R
C
2
999
2 999999999999999
t
99999999999999999
( R
$
A R
%
)C1 ( 1 ) V
C1
( t )
e
CC
Since the duratin ! the timer utput l1 state(t
'
) is the amunt ! time it ta=es !r the 7
C5
(t) t reach 7cc%4/
t
L
999999999999999999999999999
9999999999
1 2
( R
$
A R
%
)C1
999 V
CC
: 999 V
e
( 4 )
& &
CC
t
L
: C
1
( R
C
A R
%
);n2 : 0.6?&( R
C
A
R
%
)C
1
(? )
Since ;D is nrmally ;@CC;D althugh related t the siDe ! discharging Tr"/
t':0"EF4;@C5 (50)
Cnse*uently/ i! the timer perates in astable/ the perid is the same 1ith
3T:t
H
At
'
:0"EF4(;AA;
@
)C
5
A0"EF4;
@
C
5
:0"EF4(;
A
A2;
@
)C
5
3 because the perid is the sum ! the charge time and discharge
time" And since !re*uency is the reciprcal ! the perid/ the !ll1ing applies"
8reHuency7 8 :
1
: 99999999999 1.33 9999999
99 ( 11)
999 99999999999999999999
T ( R A 2R
C
)C
1
2. Fre:uenc/ di8ider
@y adjusting the length ! the timing cycle/ the basic circuit ! &igure 5 can be made t perate as a !re*uency divider" &igure
G" illustrates a divide9by9three circuit that ma=es use ! the !act that retriggering cannt ccur during the timing cycle"
Figure 8. 9a8eforms of Fre:uenc/ Di8ider Operation
4. Pulse 9idth !odulation
The timer utput 1ave!rm may be changed by mdulating the cntrl vltage applied t the timer3s pin # and changing
the re!erence ! the timer3s internal cmparatrs" &igure F" illustrates the pulse 1idth mdulatin circuit"
.hen the cntinuus trigger pulse train is applied in the mnstable mde/ the timer utput 1idth is mdulated accrding
t the signal applied t the cntrl terminal" Sine 1ave as 1ell as ther 1ave!rms may be applied as a signal t the cntrl
terminal" &igure 50 sh1s an e0ample ! pulse 1idth mdulatin 1ave!rm"
.Vcc
Trigger
Output
>
;-S-T
2 T;6)
4 2HT
G
7cc
I
D6SCH
E
TH;-S
R
-
5nput
),D
5
C2,T # C
Figure ;. -ircuit for Pulse 9idth !odulation Figure 5<. 9a8eforms of Pulse 9idth !odulation
". Pulse Position !odulation
6! the mdulating signal is applied t the cntrl terminal 1hile the timer is cnnected !r astable peratin as in &igure 55/
the timer becmes a pulse psitin mdulatr"
6n the pulse psitin mdulatr/ the re!erence ! the timer3s internal cmparatrs is mdulated 1hich in turn mdulates
the timer utput accrding t the mdulatin signal applied t the cntrl terminal"
&igure 52 illustrates a sine 1ave !r mdulatin signal and the resulting utput pulse psitin mdulatin B h1ever/ any
1ave shape culd be used"
.Vcc
2
Output
4
>
;-S-T
T;6)
2HT
G
7cc
D6SCH
TH;-S
R
-
I
R
/
E
6o$u#ation
),D
5
C2,T # C
Figure 55. -ircuit for Pulse Position !odulation Figure 5&. 9a8eforms of pulse position modulation
6. inear )amp
.hen the pull9up resistr ;A in the mnstable circuit sh1n in &igure 5 is replaced 1ith cnstant current surce/ the
7
C5 increases linearly/ generating a linear ramp" &igure 54 sh1s the linear ramp generating circuit and &igure 5>
illustrates the generated linear ramp 1ave!rms"
0Vcc
R#
R1
3 4
2
*utput
R#S#T Vcc
%;SC@
1
TR;5
I1
T@R#S
6
R2
& *<T
5.%
1
C1
C*.T
,
C2
Figure 52. -ircuit for inear )amp Figure 54. 9a8eforms of inear )amp
6n &igure 54/ current surce is created by (,( transistr J5 and resistr ;5/ ;2/ and ;-"
V
CC
? V
#
;
C
: 999999
R
9999999 9 (12) 9999999999999
#
@ere7 V
# i!
R
2
: A
999999999999999999999V
( 1& )
V
#
V
C# R
1
A R
2
CC
&r e0ample/ i! 7cc:5#7/ ;
-
:20=/ ;5:#=./ ;2:50=/ and
7
@-
:0"I7/ 7
-
:0"I7A507:50"I7
6c:(5#950"I)%20=:0"25#mA
.hen the trigger is started in a timer cn!igured as sh1n in &igure 54/ the current !l1ing t capacitr C5 becmes a
cnstant current generated by (,( transistr and resistrs"
Hence/ the 7
C
is a linear ramp !unctin as sh1n in &igure 5>" The gradient S ! the linear ramp !unctin is de!ined as
!ll1sB
V
p ? p
S :
9999999999999999
T
( 13 )
Here the 7p9p is the pea=9t9pea= vltage"
6! the electric charge amunt accumulated in the capacitr is divided by the capacitance/ the 7
C
cmes ut as
!ll1sB
7:J%C (5#)
The abve e*uatin divided n bth sides by T gives us
V I T
999 :
999999999999
( 16 )
T C
and may be simpli!ied int the !ll1ing e*uatin"
S:6%C (5I)
6n ther 1rds/ the gradient ! the linear ramp !unctin appearing acrss the capacitr can be btained by using the
cnstant current !l1ing thrugh the capacitr"
6! the cnstant current !l1 thrugh the capacitr is 0"25#mA and the capacitance is 0"02u&/ the gradient ! the ramp
!unctin at bth ends ! the capacitr is S : 0"25#m%0"022u : F"II7%ms"
?
.
6
0
0
.
&
1
4

+
$
J
?
.
2
0

0
.
2
0
0
.
&
6
2

0
.
0
0
4
0
.
1
?
0
.
0
&
1

"
0
.
3
6

0
.
1
0
0
.
0
1
4

0
.
0
0
3
2
.
,
3
0
.
1
0
0
1
.
,
2
3

0
.
1
0
0
.
0
6
0

0
.
0
0
3
!echanical Dimensions
Package
Dimensions in millimeters
8-DIP
6.30 0.20
0.2,2 0.004
K1 K4
K3 K,
1.62
0.&00
,.04
0.200
+$J
&.30 0.20 0.&&
&.&0 0.&0
0.1&0 0.012
0.1&3 0.004
0.01&
+;.
6.00 0.&0
0.2&6 0.012
,
.
1
&
0
.
2
0
2


+
$
J
3
.
?
2

0
.
2
0
0
.
1
?
3

0
.
0
0
4
+
$
J
0
.
1
0
+
$
J
0
.
0
0
3
1
.
2
1
0
.
0
,
0
0
.
,
6

"
0
.
0
2
2
0
.
3
1

0
.
1
0
0
.
0
1
6

0
.
0
0
3
!echanical Dimensions Continued"
Package
Dimensions in millimeters
8-SOP
1.,, 0.20
0.061 0.004
+;.
0.1/0.2,
0.003/0.001
K1 K4
K3 K,
1.40
+$J
0.011
&.?, 0.20
0.1,6 0.004
0.,0 0.20
0.020 0.004
,.12
0.22,
Ordering Information
Product $um'er Package Operating +emperature
L+,,,C. 42%;'
0 / 010C
L+,,,C+ 42S*'
Product $um'er Package Operating +emperature
.#,,,. 42%;'
0 / 010C
.#,,,% 42S*'
Product $um'er Package Operating +emperature
S$,,, 42%;'
230 / 04,C
S$,,,% 42S*'
2002 Fairchild Semiconductor Corporation
DIS-AI!%)
F$;RC@;L% S#+;C*.%<CT*R R#S#RV#S T@# R;5@T T* +$A# C@$.5#S );T@*<T F<RT@#R .*T;C# T* $.L
'R*%<CTS @#R#;. T* ;+'R*V# R#L;$C;L;TL7 F<.CT;*. *R %#S;5.. F$;RC@;L% %*#S .*T $SS<+# $.L
L;$C;L;TL $R;S;.5 *<T *F T@# $''L;C$T;*. *R <S# *F $.L 'R*%<CT *R C;RC<;T %#SCR;C#% @#R#;.M
.#;T@#R %*#S ;T C*.V#L $.L L;C#.S# <.%#R ;TS '$T#.T R;5@TS7 .*R T@# R;5@TS *F *T@#RS.
IF% S1PPO)+ POI-=
F$;RC@;L%NS 'R*%<CTS $R# .*T $<T@*R;O#% F*R <S# $S CR;T;C$L C*+'*.#.TS ;. L;F# S<''*RT %#V;C#S
*R SLST#+S );T@*<T T@# #J'R#SS )R;TT#. $''R*V$L *F T@# 'R#S;%#.T *F F$;RC@;L% S#+;C*.%<CT*R
C*R'*R$T;*.. $! u!ed hereinD
1. Li8e !upport device! or !y!tem! are device! or !y!tem!
(hich7 a" are intended 8or !urgical implant into the :ody7
or :" !upport or !u!tain li8e7 and c" (ho!e 8ailure to
per8orm (hen properly u!ed in accordance (ith
in!truction! 8or u!e provided in the la:eling7 can :e
rea!ona:ly eBpected to re!ult in a !igni8icant inPury o8 the
u!er.
2. $ critical component in any component o8 a li8e !upport
device or !y!tem (ho!e 8ailure to per8orm can :e
rea!ona:ly eBpected to cau!e the 8ailure o8 the li8e
!upport device or !y!tem7 or to a88ect it! !a8ety or
e88ectivene!!.
((( . 8a ir ch il d!em i. com
1-16-02 0.0m 001
Stoc=K%SBBBBBBBB