FPGA Implementation of CORDIC based

Area Efficient Adaptive Equalizers

Thesis Submitted in Partial Fulfillment of the

Requirements for the Degree
of

MASTER OF TECHNOLOGY
IN
MICROELECTRONICS AND VLSI DESIGN

By
V.Ramanjaneyulu
(Roll No: 03EC6402)

Under the Guidance of

Prof. M.Chakraborty

DEPARTMENT OF ELECTRONICS & ELECTRICAL

COMMUNICATION ENGINEERING
INDIAN INSTITUTE OF TECHNOLOGY
KHARAGPUR–721302, INDIA
 CERTIFICATE

This is to certify that the thesis entitled “FPGA

Implementation of Cordic based Area Efficient Adaptive
Equalizers” is an authentic record of the work carried out by
V.Ramanjaneyulu (Roll No. 03EC6402) under my guidance and
supervision. The thesis is submitted to the Department of Electronics
and Electrical Communication Engineering, Indian Institute of
Technology, Kharagpur, India, in partial fulfillment of the requirements
for the award of the degree of Master of Technology in
Microelectronics and VLSI design during the academic year 2004-
05.
It is further certified that the work embodied in the project has
not been submitted to any other University or Institute for the award of
any degree or diploma.

(Prof. M.Chakraborty)
Department of E&ECE,
Indian Institute of Technology,
Date: Kharagpur
– 721302.
 ACKNOWLEDGEMENTS

It brings me immense pleasure to express my deepest sense of

gratitude to my guide Prof. M.Chakraborty for his expert guidance
and support throughout the project work. His suggestions and
invaluable ideas provided the platform to the whole project work. In
spite of his extremely busy schedule, I have always found him
accessible for suggestions and discussions. I look at him with great
respect for his profound knowledge and relentless pursuit for
perfection. His ever-encouraging attitude and help has been
immensely valuable. I would also like to thank Prof. A.S.Dhar for
helping me a lot during the part of my M.Tech course. I would like to
thank my friends, P.V.V.Satyanarayana, T.Deepak and
K.Venkateswara Rao, for their help in simulation.
I would like to express my thanks to all faculty members, my
classmates and all my friends in IIT Kharagpur for their support.
Nothing would have been possible without the support of my family
members, who have been backing throughout my life, who have been
a constant sense of inspiration and whose blessings made me achieve
what I aspired for.
ABSTRACT

The objective of this thesis is design and implementation of CORDIC based Area
Efficient Transversal Adaptive Equalizers. To achieve a CORDIC based structure, the
LMS algorithm is reformulated by representing each tap weight by equivalent rotational
angles. Unlike the conventional LMS algorithm, the rotational angles rather than the tap
weights are updated directly. This new algorithm, namely, the Trigonometric LMS
(TLMS) algorithm is used to update the filter co-efficients of the equalizer. To achieve a
high throughput, the basic architecture is fully pipelined, by introducing some delay in
the weight update equation of the TLMS algorithm, resulting in the so-called Delayed
TLMS algorithm. The architecture is folded and operated with an internal clock faster
than the incoming symbol rate. The convergence performance of the algorithm depends
on adaptation delay and step size. Careful selection of these factors is made to achieve
fast convergence and high throughput.
Two area-efficient architectures are proposed which implement the DTLMS
algorithm - one architecture uses error gradient in weight updating and the other
architecture uses signed version of the DTLMS algorithm. The former requires a
multiplier and the latter does not. These architectures use CORDIC blocks instead of
multipliers in the filter and hence are more efficient in terms of internal numerical errors
and power consumption. The internal blocks of the architecture are designed and the
architectures are implemented on FPGA XCV400. The convergence performance of the
proposed architectures is found to be quite satisfactory, even for high data rate
applications like HIPERLAN.
List of figures

Fig 1.1 A digital communication system

Fig 2.2 Block diagram representation of a statistical filtering problem

Fig 3.1 Block diagram of adaptive linear transversal equalizer

Fig 3.2.1 Architecture of TLMS based Adaptive Equalizer

Fig 3.2.2 Area efficient architecture using DTLMS algorithm

Fig 3.3. Area efficient architecture using sign-data DTLMS algorithm

Fig 3.4.1 Dataflow at FIFO F1

Fig 3.4.2 Dataflow at accumulator

Fig 3.5.1 Internal configuration of CORDIC block

Fig 3.5.2 Internal structure of Pipelined CORDIC Unit (PCU)

Fig 3.6.1 Critical path in decision mode

Fig 3.6.2 Critical path reduction by retiming

Fig 4.3.1 Illustration of the multiplication process

Fig 4.3.2 Module “B” used in designing the multiplier

Fig 4.3.3 Module “A” used in designing the multiplier

Fig 4.3.4 Generation of Sout and Cout

Fig 4.3.5 Architecture of 16-bit multiplier

Fig 4.3.6 Generation of the partial product

Fig 4.3.7 Generation of Xout and Yout

Fig 4.4.1 Block diagram of the quantizer

Fig 4.4.2 Logic diagram of quantizer

Fig 4.6 Control signals generator

Fig 5.2 Convergence performance of the DTLMS based equalizer

Fig 5.3 Convergence performance of the sign DTLMS based equalizer

Fig 5.4.1 Convergence performance of DTLMS algorithm simulated in Verilog HDL

Fig 5.4.2 Convergence performance of sign-data DTLMS algorithm simulated in Verilog

HDL

Fig 5.5 FPGA design flow

Fig 5.5.1 Output waveform of Adaptive equalizer using DTLMS – before convergence

Fig 5.5.2 Output waveform of Adaptive equalizer using DTLMS – at convergence

Fig 5.5.3 Output waveform of Adaptive equalizer using DTLMS – after convergence

Fig 5.5.4 Output waveform of Adaptive equalizer using DTLMS – in Decision directed
mode

Fig 5.5.5 RTL Schematic of the adaptive equalizer using DTLMS

Fig 5.5.6 Complete routed design in FPGA editor

Fig 5.5.7 Output waveform of Adaptive equalizer using sign-data DTLMS – before
convergence

Fig 5.5.8 Output waveform of Adaptive equalizer using sign-data DTLMS - at

convergence

Fig 5.5.9 Output waveform of Adaptive equalizer using sign-data DTLMS - after
convergence

Fig 5.5.10 Output waveform of Adaptive equalizer using sign-data DTLMS – in Decision
directed mode

Fig 5.5.11 RTL schematic of the adaptive equalizer without multiplier

Fig 5.5.12 Complete routed design of multiplier less adaptive equalizer in FPGA editor
Fig 5.5.13 Overall design on FPGA to test the functionality on board

Fig 5.5.14 2-bit symbol generator

Fig 5.5.15 four tap channel

List of tables

Table 4.2 Required internal word length and no: of iterations of CORDIC block

Table 4.3.1 Operation on multiplicand of modified booth algorithm

Table 4.3.2 Truth table for generation of partial product

Table 4.4.1 Input-output relationship of the quantizer

Table 4.4.2 Truth table of the quantizer

 List of contents
1. Introduction 1

2. Trigonometric formulation of the LMS algorithm

2.1 Introduction 5
2.2 LMS Algorithm 5
2.3 The Proposed TLMS Algorithm 10
2.4 Cordic Algorithm 11
2.5 Signed-regressor Algorithm 14

3. Area Efficient Architectures

3.1 Introduction 15
3.2 Area Efficient Architecture based on DTLMS Algorithm 15
3.3 Multiplier less area efficient adaptive equalizer 18
3.4 Dataflow 20
3.5 Basic CORDIC processor 23
3.6 Critical path reduction 25

4. Internal Design of the Area Efficient Architectures

4.1 Introduction 27
4.2 Design of the Pipelined Cordic Unit 27
4.3 Design of the Pipelined Multiplier 29
4.4 Design of the Quantizer 38
4.5 Error calculation 40
4.6 Control signals generator 40
5. Simulation and Implementation results
5.1 Introduction 42
5.2 Convergence performance of the equalizer using DTLMS
algorithm simulated in MATLAB 42
5.3 Convergence performance of the sign version of DTLMS
algorithm simulated in Matlab 43
5.4 Convergence performance of the two equalizers simulated in
VerilogHDL 43
5.5 Implementation details 44
5.6 On board functional verification of the equalizer 57

6. Conclusion 59

References 60

Appendix 61