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Abstract - Paper presents one way for power STATCOM acts as a sinusoidal, with fundamental
quality conditioning. This way means parallel frequency, voltage source, therefore described con-
connection of the STATCOM circuits with the ditioner makes possible to get:
network, therefore it is possible to “isolate” load i) sinusoidal source current;
from source and vice versa. Described condi- ii) reactive power compensation;
tioner makes possible to get: i) sinusoidal source iii) load voltage stabilization;
current; ii) reactive power compensation; iii) load iv) balanced source in conditions of the unbal-
voltage stabilization; iv) balanced source in con- anced load.
ditions of the unbalanced load. As STATCOM, Because STATCOM has to “produce” sinusoidal
the four level cascade based VSI has been used. voltage, multilevel Voltage Source Inverters (VSI)
To confirm results of the theoretical analysis are the perfect solution in this case [10]-[11]. Onto
some experimental results were presented. Addi- needs of the STATCOM, four-level cascade based
tional, control algorithm, to shape six-step output VSI inverter was developed [12].
voltage is proposed.
STATCOM
Udc1 T5 T5' T5'' VSI 2L
C/2
C
N C/2
T6 T6' T6''
VSI 3L1
L1 Udc2 T1 T2
C
T3 T4 VSI 3L2
L2 T1' T2'
C
Udc2
T3'' T4''
L1 UL1-2 L2 L3
T1 L
UL1
R
Load
N
Basic blocks of this type of inverter there are age values were accepted Udc2 and Udc1. All three
conventional three-phase inverter (T5-T6; T5’-T6’; one-phase bridges with unipolar modulation are
T5’’-T6’’), as well as tree one-phase bridges (T1- shaping three-step output voltage (VSI 3L), mean-
T4), (T1’-T4’), (T1’’-T4’’) from which every one is while three-phase bridge with bipolar modulation
connected in series with half-bridge of the three- shapes two-step phase voltage (UVSI 2L). Fig.3 pre-
phase inverter. Individual modules require isolated sents formation of the phase-to-phase output voltage
supply source. During registration even supply volt- UL1-2. It is a sum of voltages on one-phase of the in-
which is sum of output voltages first (VSI 2L) and
second (VSI 3L1) inverter with bipolar and unipolar
modulations and in result of this it is for-even-level
quasi-sinusoidal curve (when Udc1=Udc2).
Triangular signal
Sine waveform
UVSI 3L1
UVSI 2L
Fig.3. Voltage curves presenting phase-to-phase vol-
tage construction (from above: Ref2 – two step UL1
inverter phase-to-phase output voltage VSI 2L,
Ch2- three-level inverter output voltage VSI
3L2, Ch4 three-level inverter output voltage VSI
3L1, Ch1 – cascade multi-level inverter phase- Fig.5. Inverter bridges voltages summation to show
to-phase output voltage UL1-2) formulation of the four-level phase voltage
In system presented in Fig.4. difference signal VSI 3L1 VSI 3L2 VSI 3L3
between current reference value iZ and real value iL
is given to proportional-integrating (PI) regulator.
Exit signal of this regulator is compared with three
triangular signals with frequencies of the commutat- VSI 2L
ing switches and with even amplitudes. Triangular
signals are shifted in relation to itself with amplitude PWM follow-
value as it is in Fig. 5. Result of comparison is given up modulator
to the comparator, which forms steering impulses
with modulated widths. Arrangements possess con-
stant switching frequency. Fig.6. Experimental model view of the multi-level
cascade topology inverter.
GNP
Udc
regulator PI
+
iz
+ FN
+
iL
Q Q Q
komparator T3 T5 T2
/Q /Q /Q ,u L
T1 T6 T4
Fig.5 presents inverter output voltage for one phase, Fig.7. Reference signal and load current, RL load.
cies. Triangular signals are shifted in relation to it-
self with value of amplitude how it shows Fig.11.a).
Principle of operation of the control algorithm is
similar how in Fig.4, with this that additionally on
exit of comparator logical arrangement was applied.
GNP GNP
Udc
Udc
regulator PI -
- +
iz - +
- +
- +
iL +
FN
Q Q Q Q Q
komparator /Q /Q /Q /Q /Q
a) T1 T2 T3 T4 T5 T6
uL
Sine waveform
b)
T1
b)
T2
T3
T4
T5
T6
c) UVSI 3L1
Fig.9. Phase-to-phase voltages of the proposed four-
level VSI a) with PWM, b) without PWM. UVSI
c)
b)