Getting Started with Allegro PCB SI

SigXplorer L Series
Product Version 15.7
June 2006
19912007 Cadence Design Systems, Inc. All rights reserved.
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Allegro PCB SI SigXplorer contains technology licensed from, and copyrighted by: Apache Software
Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA 2000-2005, Apache Software Foundation.
Sun Microsystems, 4150 Network Circle, Santa Clara, CA 95054 USA 1994-2007, Sun Microsystems,
Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 1989, 1991,
Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics
Corporation, 2001, Regents of the University of California. Daniel Stenberg, 1996 - 2006, Daniel
Stenberg. UMFPACK 2005, Timothy A. Davis, University of Florida, (davis@cise.ulf.edu). Ken Martin, Will
Schroeder, Bill Lorensen 1993-2002, Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute
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Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 3 Product Version 15.7
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Getting information about how to use
Allegro PCB SigXplorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Getting to Know the User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The Topology Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Parameters Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Measurements Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Results Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Moving Up to Allegro PCB SI SigXplorer XL anf GXL Series . . . . . . . . . . . . . . . . . . . . . 21
2
Extracting a Net from the PCB Database. . . . . . . . . . . . . . . . . . . . . . 23
Specifying the Board Stack Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Identifying DC Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Specifying Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Assigning Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
What is an Extended Net (Xnet)? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Auditing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3
Editing The Circuit Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Adding Parts to the Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Wiring the Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Setting Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Controlling Your View of the Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Contents
Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 4 Product Version 15.7
4
Simulation Strategies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Exploration Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Verication Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Setting Default Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Setting Analysis Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Setting Stimuli and Running Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Simulation and Analysis Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 5 Product Version 15.7
1
Introduction
Allegro PCB SI Board option L and L SigXplorer are entry-level interconnect analysis tools
available as an add-on option to the Allegro PCB Design L Series.
The SigXplorer L Series lets you easily create and edit a virtual prototype of a net topology.
You can simulate the circuit topology and examine the simulation results. After analyzing the
simulation results, you can explore different circuit topologies by repositioning parts and
modifying the parameters and part models of the circuit, adjusting the simulation setup, then
resimulating. You can repeat this process multiple times to experiment with various what-if
scenarios until the desired results are realized. Topology les and their attributes can be
saved and reused later.
SigXplorer graphically displays simulation results as waveforms and spreadsheet data.
Waveforms are displayed in SigWave. Simulation data is displayed in the Results
spreadsheet in the integrated spreadsheet. From SigWave, you can manipulate, print, and
save a waveformle. Fromthe integrated spreadsheet, you can print the resulting simulation
data, or export it to a data le that can be read by external spreadsheet programs.
With SigXplorer you can create a topology fromscratch, open a saved topology le, or extract
a circuit topology on-the-y from an existing Allegro PCB Design database.
The graphical user interface lets you modify topology element parameters and placement.
Common circuit simulation models for topology elements are available from model libraries
and may be added to a topology using the integrated model browser.
PCB
Editor
Database
Database
Setup
Advisor
SigXplorer
SigWave
Design Flow
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 6 Product Version 15.7
Important
This document describes basic functionality in Allegro PCB SI SigXplorer Board
option L and L (and in the Allegro PCB Design L Series). If you are running other
versions of SigXplorer or Allegro PCB, information described here may not apply.
The terms SigXplorer and PCBDesign used in the balance of this document refer
to the products comprising the Allegro PCB SI SigXplorer L Series and the Allegro
PCB Design L Series respectively. Instances in which functionality is exclusive to
one product offering is specied.
Getting information about how to use
Allegro PCB SigXplorer
The SigXplorer documentation set consists of online help and online books. All
documentation is accessible from the SigXplorer help menu.
Refer to... for this level of information
Getting Started with Allegro PCB
SigXplorer (this book)
This book is for users who know how to use the
PCB Design but are new to the signal integrity
eld.
A light introduction to the major features of
SigXplorer including net extraction, reection
simulation, and analysis.
This book can be viewed online in Acrobat, but
the organization, type size and screen captures
are optimized for hard-copy print.
Allegro PCB SI SigXplorer
Tutorial
This book complements Getting Started by
guiding you through a series of exercises that
lead to optimized placement based on signal
exploration and analysis.
This book can be viewed online in Acrobat, but
the organization, type size and screen captures
are optimized for hard-copy print.
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 7 Product Version 15.7
Getting to Know the User Interface
SigXplorer encompasses ve views of your circuit topology.
The topology canvas (graphical editor) occupies the upper-part of the window. It provides you
with a view of the circuit topology. The remaining views occupy the lower-part of the editor
(the spreadsheet) and become active by clicking on the appropriate tab. With the exception
of the Results spreadsheet, all views can be edited.
Allegro PCB SigXplorer
online help in CDSDoc
Online help provides a more in-depth look at
SigXplorer and signal integrity concepts.
Online help is organized by procedures,
concepts, interactive eld-level help, and
reference.
Use this view... To...
Canvas Add parts and models and graphically wire the circuit
Parameters Specify parameters for elements in the topology
Measurements Specify measurements to capture during the reection
simulation
Results Display the data resulting from the simulation
Command Monitor the simulation as it progresses or to enter
commands
Refer to... for this level of information
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 8 Product Version 15.7
The upper- and lower-parts of the editor can be sized independently. For example, as you
construct the circuit topology, you may want to resize the canvas to give you more real estate.
Conversely, you may want to size the other views when you set up simulation measurements
and parameters or view simulation results.
The upper- and lower-parts of the editor also exhibit focus. For example, if you click in the
lower-part of the editor, and zoom-in, youll see fewer cells (at a larger magnication) in the
spreadsheet; the zoom-factor in the top-part of the editor remains unchanged. Conversely,
you can click the top-part of the editor to resize the view of the canvas.
Important
You can click View Zoom to Fit to reset the view scale so that the entire topology
ts onto the canvas.
Command access through menus
Click tab to select a
spreadsheet view:
- Parameters
- Measurements
- Results
- Command
Command access through icons
Drag vertically to
resize the canvas-
or spreadsheet-
view
Topology
Canvas
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 9 Product Version 15.7
The Topology Canvas
In the topology canvas, you graphically develop and edit circuit topologies. You can add
symbols that represent simulation models to the topology. You can move, copy, and delete
part symbols as necessary. Additionally, you can rotate discrete parts. The cleanup
command aligns the symbols orthogonally. Rounding out the topology editing commands are
zoom control (view) and annotation (note).
The topology canvas is synchronized with the Parameters spreadsheet. As you select a
symbols parameter in the canvas, its eld is highlighted in the spreadsheet. As you modify
the parameter in the spreadsheet, the value updates on the symbol in the canvas.
synchronized with:
Parameter View
Canvas View
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 10 Product Version 15.7
Parameters Spreadsheet
Use the Parameters spreadsheet to modify values associated with individual topology
elements and to set global circuit parameters
The Parameters spreadsheet is also synchronized with the topology canvas. As you modify
the parameter in the spreadsheet, the value updates on the symbol in the canvas view.
The Attribute column displays an expandable tree view of the attributes associated with the
circuit topology itself circuit, as well as lists of the attributes associated with each part in the
circuit.
You can edit attribute values in any cell with a white background by clicking in the cell
containing the attribute value. For attributes in which you have a pre-dened choice of
possible values, a menu appears from which you can select an option.
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 11 Product Version 15.7
Your topology may contain the following circuit and design attributes:
Model Type Circuit Element Denable Attributes
ESpiceDevice Capacitor
Inductor
Resistor
User-denable Discrete
Value (value initially derived
from library defaults)
GenericElement Capacitor
Connector
Diode
Inductor
Resistor
Voltage Source
User-denable Discrete
Value
AnyIOcell all CDS models bufferModel
DifferentialPart Differential input/output
models
bufferModel
threshold input/output
IbisDevice IOCells with pin-specic
package parasitics
bufferModel
IOCell IbisInput
IbisIO
IbisIO_OpenPullup
IbisIO_OpenPullDown
IbisOutput
IbisOutput_OpenPullup
IbisOutput_OpenPullDown
bufferModel
Interconnect Tline
TlineCoupled
Propagation Delay/Length
Impedance
trace Geometry
velocity
Differential Impedance
Diff. Propagation Delay
Differential Velocity
Impedance
PropagationDelay
trace Geometry
velocity
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 12 Product Version 15.7
Microstrip_1
Stripline_1
Microstrip_broadside_2
Stripline_broadside_2
Microstrip_broadside_2S
Stripline_broadside_2S
Dielectric Loss Tangent
Dielectric Loss Tangent
Dielectric Thickness
Length
trace Conductivity
trace thickness
trace width
Dielectric Constant
Dielectric Loss Tangent
Dielectric Thickness
Length
trace conductivity
trace thickness
trace width
Offset
trace width2
Offset
trace width2
Dielectric Thickness
Trace Thickness
trace Width
offset
Termination DualClamp
HiClamp
LowClamp
Max Delay
Thresh Voltage High
Thresh Voltage Low
Voltage High
Voltage Low
Threshold Voltage
Max Delay
Voltage
Model Type Circuit Element Denable Attributes
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 13 Product Version 15.7
RC Max Delay
Capacitance
Resistance
Voltage
Series MaxDelay
Resistance
Shunt
Thevenin
MaxDelay
Resistance
Voltage
Max Delay
Resistance High
Resistance Low
Voltage High
Voltage Low
Model Type Circuit Element Denable Attributes
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 14 Product Version 15.7
Measurements Spreadsheet
Use the Measurements spreadsheet to select which reection measurements to capture
during the simulation. Once simulation is complete, each measurement that you choose
appears when you switch to the Results spreadsheet.
Expand/
collapse
button
Click
measurements
All On
or
All Off
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 15 Product Version 15.7
Results Spreadsheet
View the simulation results as both data displayed in the Results spreadsheet and as
waveforms viewed with SigWave.
Discrete values
displayed in
results
spreadsheet
Waveform
resultsdisplayed
in SigWave
Think of SigWave as
a virtual oscilloscope
where you can
graphically examine
resulting simulation
waveforms. You can
also save and
compare waveforms
for further analysis.
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 16 Product Version 15.7
Command Spreadsheet
Use the Command view to view messages issued by SigXplorer and optionally to enter
commands.
SigXplorer Commands
SigXplorer lets you choose commands in the following ways:
I Choose from the pull-down menus
I Click an icon in the toolbar
I Type in a keyboard shortcut
I Type in the command name in the console line
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
File New Create a new topology le Alt-fn
Cntrl-n
new
File Open Open a topology le Alt-fo
Cntrl-o
open
Click Command
Enter
commands here
System
messages
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 17 Product Version 15.7
File Example Open a new topology
template
File Save Save current topology le Alt-fs
Cntrl-s
save
File Save As Save current topology le
under a different name
Alt-fa saveas
File Export
Spreadsheet
(L version)
Export simulation data to a
spreadsheet application
Alt-fe spreadsheet
export
File Update
Constraint
Manager
(Board option L
version)
Update the database with the
topology template you have
applied to a net or a group of
nets
File Append
(Board option L
version)
Append a topology to the
active topology
File Import
Measurement
(Board option L
version)
Import a custom
measurements (.dat) le
associated with another
topology
File Import
Sweep Case
(Board option L
version)
Import sweep case data that
was previously saved
File Export
Measurement
(Board option L
version)
Create a custom
measurements (.dat) le
containing all the custom
measurements dened for
the topology
File Export
Spreadsheet
(Board option L
version)
Open the Save As le
browser to display
spreadsheet tabbed text (.txt)
le
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 18 Product Version 15.7
File Print
Canvas Setup
Set up plot parameters Alt-fu
File Print
Canvas
Print the topology symbols
and connections
Alt-fp print
File Print
Spreadsheet
Print the topology
parameters, measurements,
or simulation results
Alt-fr plot
File Script Records a script containing
mouse picks
Alt-fc script
File Exit Exit SigXplorer Alt-fx exit
View Zoom by
Window
Display an area of the
topology by selecting a
starting and ending point.
Click to anchor the starting
point, drag across the area,
and click to dene the end
point.
The view of the topology then
focuses around this area.
Alt-vw
F8
zoom points
View Zoom Fit Display the entire topology in
the canvas
Alt-vf
F9
zoom t
View Zoom
Center
Center the view of the
topology relative to where
you click
Alt-vc zoom center
View Zoom In Display an enlarged view of
the topology
Alt-vi
F10
zoom in
View Zoom Out Display an reduced view of
the topology
Alt-vo
F11
zoom out
View Zoom
Previous
Display an reduced view of
the topology
Alt-v v zoom previous
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 19 Product Version 15.7
Edit Undo Undo last action Alt-eu sxundo
Edit Canvas
Move
Select move element mode Alt-em canvas move
Edit Canvas
Copy
Select copy element mode Alt-ec canvas copy
Edit Canvas
Delete
Select delete element mode Alt-ed canvas delete
Edit Canvas
Rotate
Select rotate element mode Alt-er canvas rotate
Edit Canvas
Mirror
(Board option L
version)
Mode for selecting Current
Probe elements in the
topology canvas and
mirroring them
Edit Add Part Add a design element from
the part browser
Alt-ea add part
Edit Note Add, edit, or delete an
annotation
Alt-en note
Edit Transform
For Constraint
Manager
(Board option L
version)
Condition a topology for use
in Constraint Manage
Edit Cleanup Uniformly align elements in
the topology
Alt-el canvas
cleanup
Set Constraints
(Board option L
version)
Display the Set Topology
Constraints dialog box for
modifying topology constraint
values
Set Defaults Set default values for
topology elements
Alt-sd prefs
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 20 Product Version 15.7
Set Strobe Pins
(Board option L
version)
Display the Set Strobe Pin
Groups dialog box where you
can mark and group strobe
and data pins
Set Vectors
(Board option L
version)
Display the Vector Set
Operations dialog where you
can save a snapshot of all
IOCell stimuli and
parameters in the topology
as a named vector set
Set Optional
Pins
(Board option L
version)
Specify optional pins in a
topology in order to map to a
net or Xnet that does not
have the same number of
pins as the net/Xnet you are
mapping from.
Analyze
Libraries
Access the model libraries Alt-al signal library
Analyze
Preferences
Set analysis preferences Alt-ap signal options
Analyze
Simulate
Start a reection simulation Alt-as signal simulate
Analyze
Simulate
Continue
(Board option L
version)
Continue a paused
simulation sweep using the
simulation parameters set
with the Analysis
Preferences dialog box
Analyze (S)
Generation
(Board option L
version)
Generate S-Parameter data
for use in time domain
analysis
Analyze
Channel Analysis
(Board option L
version)
Simulate large bit streams to
accurately determine eye
closure and jitter
characteristics
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 21 Product Version 15.7
Moving Up to Allegro PCB SI SigXplorer XL anf GXL
Series
You can upgrade from the L Series of Allegro PCB SigXplorer to the XL and GXL Series and
realize the benets of a full constraint-driven, high-speed interconnect exploration and
analysis environment that supports the following advanced features:
I Advanced Analysis
crosstalk
reection
EMI
user-denable custom measurements
I Parametric sweeps and simulation sampling
I Custom stimuli denition (including random bit patterns) for IOCell excitation
I Advanced Models
clocked IOCells
differential pairs
coupled traces
I Topology template les to enforce a constraint-driven implementation of the physical
layout in the PCB Design.
Analyze Reset
Sim Data
Resets the simulation
environment and reloads
libraries
Alt-ar signal reset
Help
Documentation
Access online documentation
and Web sites
Alt-hh
F1
help
Help About
SigXplorer
Display version number of
SigXplorer
Alt-ha about
Menu Pick Function
Keyboard
Shortcut
Console
Command
Icon
Getting Started with Allegro PCB SI SigXplorer L Series
Introduction
June 2006 22 Product Version 15.7
Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 23 Product Version 15.7
2
Extracting a Net from the PCB Database
Before you can perform signal integrity analysis in SigXplorer, you must extract an unrouted
net (pre-route analysis) or a routed net (post-route analysis) from your design in the PCB
Design.
The Database Set Up Advisor (Tools Setup Advisor in the PCB Design) is a utility used
to bridge the physical design representation in the PCB Design with the equivalent electrical
design representation in SigXplorer by guiding you through the steps necessary to ensure a
clean net extraction from the PCB Design database.
Physical
view in
PCB
Design
Electrical
view in
SigXplorer
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 24 Product Version 15.7
The following sections take you through the database setup requirements. The advisor is
organized by the following modules:
Once you successfully complete the Audit phase of the Database Setup Advisor, choose
Tools Topology Extract.
The Topology Template dialog box appears.
Select a net and click View to extract the net topology from the PCB Design database and
explore it within SigXplorer. This net is now considered clean (extractable) and does not
require you to repeat the setup process for subsequent extraction with the Topology Extract
command in the PCB Design.
In this module... You will...
Cross-section Edit the type and characteristics of the varied material layers
in the layout.
DC Nets Identify which nets in the layout are to be connected to a
constant DC voltage value that you specify.
Devices Provide information about the devices in the layout, such as
class (IC, IO, Discrete) and pin usage (BI, IN, OUT).
SI Models Assign electrical models to components in the layout.
SI Audit Audit specic nets in the layout to verify that they are set up
properly for extraction and simulation.
Click View to
launch
SigXplorer with
the selected net
Select net from
list or click on the
net in the PCB
design
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 25 Product Version 15.7
Specifying the Board Stack Up
To accurately model routed traces, you must properly dene the board cross section.
The material characteristics of the layer stack up include the following:
I Layer Material
FR-4
Copper
Other materials
I Layer Type
Bonding-Wire (signal layers)
Conductive (signal layers)
Plane (power/ground layers)
Dielectric (insulating layers)
I Layer Thickness
Units
I Layer Characteristics
Conductivity
Dielectric Constant
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 26 Product Version 15.7
The advisor guides you to the layer cross-section dialog box where you dene the stack up.
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 27 Product Version 15.7
Identifying DC Nets
You must dene the voltage associated with a particular DC net.
You should set the net GND to a voltage value, such as 0. This is important during extraction
for the following reasons:
I It will prevent SigXplorer from trying to mistakenly extract a net with hundreds of pins
(such as VCC) into the topology canvas.
I If you have a shunt (parallel) termination to a DC net, SigXplorer will recognize the DC
net as a 'termination voltage' and insert the correct voltage source into the circuit (such
as at the far end of the resistor).
You may get warnings if the CLASS attributes of your devices are not dened properly, but you
can resolve these warnings when you specify devices in the next module.
You can use the lter to quickly nd a class of nets. For example, in the following
design...
Filter Expression Selectable Nets
v* VCC,VSS
G* GND
* All nets
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 28 Product Version 15.7
Specifying Device Information
To extract an appropriate topology, SigXplorer needs information about the devices on a net.
For example, if a device is a connector, then the proper device type needs to be specied so
that the appropriate component symbol is displayed in SigXplorer.
SigXplorer derives information about a device through the following properties:
I CLASS
IC
To designate an active IBIS-modeled component
IO
To designate a connector
DISCRETE
To designate a passive ESPICE-modeled component such as a resistor, resistor
pack, inductor, or capacitor
I PINUSE
UNSPEC
Used on devices assigned an IO or a DISCRETE CLASS
IN
Used on a receiver pin assigned an IC CLASS
OUT
Used on a driver pin assigned an IC CLASS
BI
Used on a driver-receiver pin assigned an IC CLASS, such as on a bi-directional
bus
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 29 Product Version 15.7
In addition to specifying the correct CLASS and PINUSE properties, you can let SigXplorer
automatically set the values for discrete components in the design. This allows appropriate
electrical models to be generated for these devices.
Click browse to
invoke component
lter to select
individual or groups
of components
Specify auto-
generated values for
discretes.
Value in PCB Design
device denition
overrides default
values
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 30 Product Version 15.7
Assigning Signal Models
You can assign signal models to the parts in your design. Fromthe Signal Model Assignment
dialog box, you can do the following:
I For ICs, you can assign IbisDevice models so that the appropriate package parasitics
and IOCells (driver/receiver models) extract into SigXplorer. This is an optional step; if
you do not make explicit model assignments for ICs, default models will be used. Once
in SigXplorer, you can easily substitute specic IOCell models for various IC pins in your
topology.
I For discretes, you can automatically generate models. This is important if you want to
extract and analyze signals with termination. It becomes even more important if you want
to extract extended nets (Xnets) into SigXplorer
What is an Extended Net (Xnet)?
In the PCB design, a physical net that passes through discrete components is divided into
individual segments, or subnets. The same physical net in the PCB design is represented by
an equivalent electrical view (topology), called an extended net (Xnet) when extracted into
SigXplorer.The Xnet maintains its connectivity by extracting information from the device and
interconnect models that are associated with the net.
For example, two nets connected through a series terminator are considered a single
electrical Xnet. It is essential to properly model the series resistor due to the fact that the
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 31 Product Version 15.7
circuit extractor uses the resistors model to derive the electrical connectivity through the
resistor to link the two nets together correctly.
I Edit or delete any of these automatically generated models, or create new models and
assign them directly to specic devices.
This automatically models discrete devices based on the following precedence: (1) the values
specied in the device denition (in the PCBdatabase); and (2), information that you specied
in the previous module, when you set up the devices.
Each part in the PCB database has a device type and a reference designator. You can assign
signal models by device type or refdes. Use the former for more global assignments and
automatic assignments to discretes; use the latter for more specic assignments.
Signal Model Assignment Dialog Box - Devices Tab
Device
Click to automatically
generate simulation
models for two-pindiscrete
devices
Model
RefDes
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 32 Product Version 15.7
Signal Model Assignment Dialog Box - RefDes Pins Tab
Auditing the Design
The audit (SigNoise Setup Report) provides additional detail when troubleshooting
problem nets. You may wish to run this on (1) any nets that you are unable to extract and
simulate; or (2), specic nets at the beginning of the process, to help isolate those setup
issues.
The SigNoise Setup Report contains the following three sections:
To nd serious setup problems (Errors), the following conditions are examined:
I Zero thickness layers in the layerstack
I Nets with POWER or GROUND pins, but no VOLTAGE property
I Nets with POWER or GROUND pins or VOLTAGE property, but no shape or
VOLTAGE_SOURCE pin
I No VOLTAGE property on any net
Errors A list of setup tasks you must perform to avoid serious problems
Warnings A list of setup tasks that will enhance accuracy
Information Information about the design, including existing setup data
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 33 Product Version 15.7
I Nets with no drivers or receivers, and no pins attached to a component with an
ESpiceDevice SIGNAL_MODEL reference
I No working interconnect library
I Default IOCells that do not exist in any open device library
I Components with a SIGNAL_MODEL reference that does not exist in any open device
library
I Model versions
I Referenced device models that do not pass dmlcheck. Audit Report will list problem
models, but actual errors will appear in SigNoise log window.
I Pin signal_model parameters in IBISDevice pinmap do not match PCB Design pinuse
I PCB Design component pins not found in IBISDevice pinmap (other than NC pins)
I Components with PCB Design TERMINATOR_PACK property not assigned an
ESpiceDevice SIGNAL_MODEL property
To nd setup problems that might hinder accuracy (Warnings), the following conditions are
examined:
I Default settings in the layerstack
I Components that have no SIGNAL_MODEL property
The following design information is reported:
I Layerstack information
I Number of nets and components
I Assigned models, including the library le
A Sample SigNoise Setup Report
******************************************************************************
Allegro PCB SI 15.5
(c) Copyright 2005 Cadence Design Systems, Inc.
DesignLink: There is no active DesignLink.
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 34 Product Version 15.7
Date : June 17 12:16:21 2005
******************************************************************************
INFO >> The victim net(s) checked are:
TUTBOARD1 ADDRESS0
******************************************************************************
INFO >> Geometry window = 10mil
******************************************************************************
INFO >> No neighbor nets were found.
******************************************************************************
ERROR >> Device(s) with no signal model:
Component DeviceType Design
--------- ---------- ------
U37 MCM-BASE TUTBOARD1
******************************************************************************
WARNING >> Pin(s) with default models:
Pin Name Model Name Net Name Component Design
-------- ---------- -------- -------- ------
C1 CDSDefaultTristate ADDRESS0 U37 TUTBOARD1
******************************************************************************
INFO >> List of assigned buffer models:
Model Name Net Name Pin Name Component Design
---------- -------- -------- --------- ------
CDSDefaultTristate ADDRESS0 C1 U37 TUTBOARD1
******************************************************************************
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 35 Product Version 15.7
INFO >> List of components:
Component DeviceType Class Design Signal Model
--------- ---------- ----- ------ ------------
U37 MCM-BASE IC TUTBOARD1 unassigned
******************************************************************************
INFO >> LayerStack Information For <tutboard1.brd>...
Type Material Name Dielectric
Constant
Electrical
Conductivity
(mho/cm)
Thickness
(mil)
Shield
--------------------------------------------------------------------------------------------------------------------------
SURFACE
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
DIELECTRIC
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
SURFACE
AIR
PLATED_COPPER_FOIL
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
PLATED_COPPER_FOIL
AIR
-
TOP
-
GND
-
IS1
-
IS2
-
VCC
-
BOTTOM
-
1.000000
-
4.500000
-
4.500000
-
4.500000
-
4.500000
-
4.500000
-
1.000000
0.000000
343000.000000
0.000000
595900.000000
0.000000
595900.000000
0.000000
595900.000000
0.000000
595900.000000
0.000000
343000.000000
0.000000
0.000000
2.100000
5.500000
1.200000
6.000000
1.200000
30.000000
1.200000
6.000000
1.200000
5.500000
2.100000
0.000000
-
No
-
Yes
-
No
-
No
-
Yes
-
No
-
Getting Started with Allegro PCB SI SigXplorer L Series
Extracting a Net from the PCB Database
June 2006 36 Product Version 15.7
Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 37 Product Version 15.7
3
Editing The Circuit Topology
Adding Parts to the Topology
You add parts (discretes, IO buffers, packages) to the topology using the Parts Browser in
SigXplorer. Before you can add parts, you must make themavailable by specifying the signal
integrity model libraries (.dml les) that you want to use through the use of the Signal
Analysis Library Browser. The signal integrity model libraries contain electrical models for
components that subsequently appear in the Model Browser. Access the dialog box from
the Analyze Libraries... menu selection.
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 38 Product Version 15.7
You add a part to the topology canvas by selecting it in the Model Browser (the part symbol
attaches to the end of your cursor) and dragging it to the canvas. This puts you in add part
mode where the part is instantiated with each click that you make in the canvas.
Wiring the Topology
Once you add parts to the topology, you can manipulate the parts symbol with the Move,
Copy, and Delete commands fromthe Edit menu. You can also rotate discrete parts. These
commands are modal. For example, if you choose Edit Delete, any symbol that you click
will be discarded until you change the editing mode.
Once you wire the circuit, you can choose Edit Cleanup to assert an orthogonal alignment
of symbols. You can also annotate the canvas by choosing Edit Note.
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 39 Product Version 15.7
Figure 3-1 Topology Wiring Techniques
Drag the wire from the
source pin of one symbol to
the target pin of the next
symbol
Double-click the target pin,
or click on the pin followed by
an off-pin click on the canvas
to end the connection
Click the source pin on the
symbol to begin the
connection
Select symbols from the
model browser and place on
canvas in a semi-orderly
arrangement
Finish wiring the topology
Organize the topology
(cleanup command) to
assert a left-to-right,
top-to-bottom appearance
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 40 Product Version 15.7
Setting Parameter Values
In the Parameter spreadsheet, you dene global circuit attributes, such as transmission
line delay mode (based on time or length) and user revision number, as well as individual
circuit element design attributes that consist of single or multiple arguments.
When fully expanded, you click in the attribute value eld to enter a single value for discretes
and voltage sources or multiple values for ideal transmission lines and trace symbols.
Click to expand/
collapse circuit or
design attributes
Click to expand/
collapse circuit or
design attributes
Click to highlight
attribute value eld
to invoke a single
value ll-in or a
multiple value dialog
box
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 41 Product Version 15.7
Resistors, voltage sources, inductors, and capacitors accept single-value arguments in the
appropriate units; transmission line and trace models accept multiple arguments. The
argument to an IO cell is a buffer model.
Multiple
Values
Discrete
Value
IO Buffer
Model
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 42 Product Version 15.7
Controlling Your View of the Topology
SigXplorer lets you control your view of the editor by choosing Zoom commands. Zooming
affects the focus of the editor, whether it is the canvas or the spreadsheet. For example, if you
click in the canvas, the zoom affects your view of the canvas. Conversely, if you click the
spreadsheet, zoom affects your view of the spreadsheet.
From the View menu, click . . . To . . .
Zoom by Window (points) Display an area of the topology by selecting a starting
and ending point.
Click to anchor the starting point, drag across the
area, and click to dene the end point.
The view of the topology then focuses around this
area.
Zoom Fit Display the entire topology in the canvas.
Zoom Center Center the view of the topology relative to where you
click.
Zoom In Display an enlarged view of the topology.
Zoom Out Display an reduced view of the topology.
Zoom Previous Displays the previously zoomed view of the topology.
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 43 Product Version 15.7
Panning
You can also hold down the right mouse button and drag to pan the topology at the current
zoom factor.
Getting Started with Allegro PCB SI SigXplorer L Series
Editing The Circuit Topology
June 2006 44 Product Version 15.7
Getting Started with Allegro PCB SI SigXplorer L Series
June 2006 45 Product Version 15.7
4
Simulation Strategies
Use Models
Most users of SigXplorer employ one of the following use models.
I Exploration
I Verication
Explore
Implement
Verify Verify
Verify
Correct
A
L
L
E
G
R
O
S
I
G
N
A
L
E
X
P
L
O
R
E
R
S
I
G
N
A
L
E
X
P
L
O
R
E
R
Verify
Verication Use Model Exploration Use Model
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 46 Product Version 15.7
With the exploration use model, you focus on up-front exploration before the board is placed
and routed. With verication, you focus on correcting problems in the post-route stage. Each
use model is described in the sections that follow.
Exploration Use Model
This use model can be characterized as Explore -> Implement -> Verify. You start by
placing critical high-speed components. Board cross-section and material type are usually
known. Restrictive form factors such as edge connectors, card slots, mounting holes, and
microprocessor chip-set location must also be considered. A netlist is available.
You then extract a selected net (ratsnest) fromthe board layout into SigXplorer for exploration
and topology development. This unrouted interconnect is modeled on Manhattan distance
estimates based on your initial placement.
You simulate and analyze the topology, making trade-off decisions that involve:
I target impedance.
I min/max length (or propagation delay).
I pin ordering.
I termination strategy (and location on net).
When acceptable results are realized, you then note what changes need to be made in the
board design. Board modication can be achieved by:
I adding components (terminators, etc.).
I swapping components.
I moving components.
I moving nets on microstrip layers to stripline layers.
I adding shield or etch layers to the stackup.
I varying trace geometry.
I re-routing to a new pin order.
A subset of the exploration use model is a pure exploration strategy where you start topology
exploration with a clean canvas before any physical design is started. This is benecial with
new designs, as opposed to derivatives of existing designs.
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 47 Product Version 15.7
Exploration Design Flow
Place critical
components in layout
Extract ratsnest from
layout
Simulate
Examine results
Document changes to
drive board layout
Revise board layout
Modify topology
Place remaining
components in layout
Iterative process in
SigXplorer
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 48 Product Version 15.7
Verication Use Model
This use model can be characterized as Verify -> Correct -> Verify. You start by extracting
a suspect net (routed trace) from a fully placed and routed board layout into SigXplorer for
analysis. This interconnect is modeled on routed trace and via characteristics based on actual
placement.
You then simulate and analyze the topology, making trade-off decisions that involve:
I target impedance.
I min/max length (or propagation delay).
I pin ordering.
I termination strategy (and location on net).
When acceptable results are realized, you then note what changes need to be made in the
board design. Board modication can be achieved by:
I adding components (terminators, etc.).
I swapping components.
I moving components.
I moving nets on microstrip layers to stripline layers.
I adding shield or etch layers to the stackup.
I varying trace geometry.
I re-routing to a new pin order.
You then ripup and reroute the suspect net and repeat the simulation and analysis cycle in
SigXplorer.
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 49 Product Version 15.7
Verication Design Flow
Extract routed trace
from layout
Simulate
Examine results
Document changes to
drive board layout
Revise board layout
Re-extract
Iterative process in
SigXplorer
Modify Topology
Verify
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 50 Product Version 15.7
Setting Default Parameter Values
Several circuit elements in the Model Browser have default parameters associated with
them (you choose Set Defaults to edit them). Regardless of the defaults, you can
edit individual parameters for circuit elements in the Parameters spreadsheet.
Specify default
parameters for
part symbols
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 51 Product Version 15.7
Setting Analysis Preferences
SigXplorer lets you set a number of preferences that control how analysis is performed (you
choose Analysis Preferences to edit them). You should specify these preferences before
you execute a simulation.
Specify preferences to
govern the analysis
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 52 Product Version 15.7
Setting Stimuli and Running Simulations
Once you have added all the parts to (or extracted the parts into) the topology, you must
select a type of stimulus (pulse, rise, quiet hi, quiet lo, or fall) for the
selected driver. You can specify only one IOCell at a time to be the driver. All other IOCells
must be set to tri-state.
You examine the simulation results in the SigXplorer spreadsheet and in SigWave. Upon
completion of the simulation, the Results spreadsheet becomes active, showing discrete
values for the measurements that you specied. Additionally, SigWave appears showing
waveforms.
Simulation and Analysis Checklist
Process
Step
Activity Comments
Command
(in Allegro PCB
Design)
1 Extract net from PCB
database.
SigXplorer needs the
following information:
I Stack-up
I DC nets
I Device CLASS and
PINUSE
I Signal integrity
models assignedtoall
parts (optional for ICs)
Tools Topology
Extract
Tools Setup Advisor
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 53 Product Version 15.7
Click the stimulus on
the IOCell to invoke
the stimulus editor
Specify Pulse, Rise,
Fall, Quiet Hi, or
Quiet Lo for the
driver; Tri-state for
receivers
Launch the
simulator by
menu- or icon
Analyze the
results:
Results
Spreadsheet
or
Waveform View
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 54 Product Version 15.7
2 Edit the Topology Modify the circuit by
adding and wiring parts.
Modify individual parts by
specifying attributes in the
parameter
spreadsheet.
Perform what-if analysis
by varying:
I min/max length
I pin ordering
I target impedance
(trace width, trace
length, distance from
ground planes,
stackup)
I termination strategy
and location on net
Edit Add Part
Edit Canvas Move
Edit Canvas Copy
Edit Canvas Delete
Edit Canvas Rotate
Edit Cleanup
3 Set up for simulation Optionally, specify default
values for topology
elements (discretes,
voltage sources,
terminations, trace and
transmission lines).
Set Defaults
Specify analysis
preferences.
Specify reection
measurements in the
Measurements
spreadsheet.
Analyze Preferences
Process
Step
Activity Comments
Command
(in Allegro PCB
Design)
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 55 Product Version 15.7
4 Simulate Specify a stimulus type for
the selected active driver
(pulse, rise, fall).
Specify tri-state for
all receivers.
Analyze Simulate
5 Analyze View simulation results for
ight times, noise margin,
and overshoot in the
Results spreadsheet and
in SigWave.
6 Document changes Once you achieve the
desired simulation results,
you must document the
changes you made to the
topology (Step 2).
Edit Note
File Print Canvas
File Print
Spreadsheet
7 Modify the design in the
PCB Editor
Implement the changes
from Step 6, then repeat
Steps 1 - 7 to verify a
sound design.
Process
Step
Activity Comments
Command
(in Allegro PCB
Design)
Getting Started with Allegro PCB SI SigXplorer L Series
Simulation Strategies
June 2006 56 Product Version 15.7