International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

ISSN: 2231-5381 http://www.ijettjournal.org Page 4259

Pulse Triggered Flip-Flops Power Optimization
Techniques for Future Deep Sub Micron
Applications
Venkateswarlu. Padidapu
#1
, Paritala. Aditya Ratna Chowdary
*2
, Kalli.Siva Nagi Reddy
#3

#
P.G Student , VLSI Design , VRS&YRN College of Engineering & Technology
Chirala, Andhra Pradesh, India.
*
Assistant Professor and HOD of ECE , ECE Department (VLSI Design) , VRS&YRN College of Engineering & Technology
Chirala, Andhra Pradesh, India.
#
Associate Professor and HOD of ECE , ECE Department, Sridevi Womens Engineering College
Hyderabad, Andhra Pradesh, India.

Abstract In this paper a new technique is proposed based on
the comparison between Conventional Transistorized Flip-flop
and Data transition Look ahead D flip flop here we are checking
the working of Low Power Pulse Trigger Flip-Flop with
conditional pulse enhancement (PFF) and Implicit Pulsed Data
Close to Output (IP-DCO) after that we are analysing the
characteristic comparison using power & area constraints after
that we are proposing a flip-flop named as Low power Negative
Edge Triggered Flip-Flop Design with reduced number of
transistors which will reduce the overall power area as well as
delay. The simulations are done using Micro wind & DSCH
analysis software tools and the result between all those types are
listed below. Our proposed system simulations are done under
50nm technology and the results are tabulated below. In that our
proposed system is showing better output than the other flip-
flops compared here.

Keywords Flip-flop; pulse triggered flip flops, Low Power,
Pulse-Triggered flip-flops, IP-DCO, HLFF, MHLFF, and
SCCER.
I. INTRODUCTION
Flip-Flops and latches are the basic elements for storing
information. One latch or Flip-Flop can store one bit of
information. The main difference between latches and flip-
flops is that for latches, their outputs are constantly affected
by their inputs as long as the enable signal is asserted. In other
words, when they are enabled, their content changes
immediately when their input change. Flip-flops, on the other
hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually
the controlling clock signal. After the rising or falling edge of
the clock, the flip-flop content remains constant even.
Transitions on the inputs of a flip-flop may or may not lead to
a state change. When input transitions do not change the State,
the internal switching inside the flip-flop consumes some
power. On the other hand, when the input transitions do
change the state, a large amount of power is consumed. There
are number of flip-flops which are shown in Figure 1. The
major differences in these flip-flop types are the number of
inputs they have and how they change state. For each type,
there are also different variations that enhance their
operations. Figure 2 (a), (b) illustrates the difference between
positive edge triggered flip flop and an active high latch. As it
can be seen in this figure, possible changes of input can be
seen at the output of the latch while it is transparent .The
performance of a flip-flop is measured by three important
timings and delays: propagation delay (Clock-to-Output),
setup time and hold time. They reflect in the systemlevel
performance of the Flip-Flops. Setup time and hold time
define the relationship between the clock and input data as
shown in the Figure 2 (c).Setup time and hold time describe
the timing requirements on the D input of a Flip-Flop with
respect to the Clk input. Setup and hold time define a window
of time which the D input must be valid and stable in order to
assure valid data on the Q output. Setup Time (Tsu) Setup
time is the time that the D input must be valid before the Flip-
Flop samples. Hold Time (Th) Hold time is the time that D
input must be maintained valid after the Flip-Flop samples.
Propagation Delay (Tpd) Propagation delay is the time that
takes to the sampled D input to propagate to the Q output.
Pulse-triggered FF (P-FF) has been considered a popular
alternative to the conventional masterslave-based FF in the
applications of high-speed operations. Besides the speed
advantage, its circuit simplicity is also beneficial to lowering
the power consumption of the clock tree system. A P-FF
consists of a pulse generator for generating strobe signals and
a latch for data storage. Since triggering pulses generated on
the transition edges of the clock signal are very narrow in
pulse width, the latch acts like an edge-triggered FF. The
circuit complexity of a P-FF is simplified since only one latch,
as opposed to two used in conventional masterslave
configuration, is needed.


International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

ISSN: 2231-5381 http://www.ijettjournal.org Page 4260



Fig. 1 Flip-Flop Tree Diagram


Fig. 2 (a) Active High latch b) Positive EdgeTriggered Flip-flop



Fig. 2 (c) Timing Diagram.

P-FFs also allow time borrowing across clock cycle
boundaries and feature a zero or even negative setup time. P-
FFs are thus less sensitive to clock jitter. Despite these
advantages, pulse generation circuitry requires delicate pulse
width control in the face of process variation and the
configuration of pulse clock distribution network. Depending
on the method of pulse generation, P-FF designs can be
classified as implicit or explicit. In an implicit-type P-FF, the
pulse generator is a built-in logic of the latch design, and no
explicit pulse signals are generated. In an explicit-type P-FF,
the designs of pulse generator and latch are separate. Implicit
pulse generation is often considered to be more power
efficient than explicit pulse generation. This is because the
former merely controls the discharging path while the latter
needs to physically generate a pulse train. Implicit-type
designs, however, face a lengthened discharging path in latch
design, which leads to inferior timing characteristics. The
situation deteriorates further when low-power techniques such
as conditional capture, pre-charge, and discharge, or
conditional data mapping are applied. Due to that the
transistors of pulse generation logic are often enlarged to
assure that the generated pulses are sufficiently wide to trigger
the data capturing of the latch. Explicit-type P-FF designs face
a similar pulse width control issue, but the problem is further
complicated in the presence of a large capacitive load, e.g.,
when one pulse generator is shared among several latches.
Hiroshi Kawaguchi and Takayasu Sakurai In [1] has
proposed a reduced clock-swing flip-flop (RCSFF) which is
composed of a reduced swing clock driver and a special flip-
flop which embodies the leak current cutoff mechanism. The
RCSFF can reduce the clock systempower of a VLSI system
down to one-third compared to the conventional flip -flop.
The RCSFF is composed of a true single -phase master-latch
and a cross-coupled NAND slave-latch. The master-latch is a
current-latch-type sense-amplifier. The salient feature of the
RCSFF is that it can accept a reduced voltage swing due to the
single-phase nature of the flip-flop.

This paper is organized as follows. In Section II, Existing
pulse-triggered flip-flops are explained. In Section III
Proposed design is shown. In Section IV Section discusses the
simulation results. The paper ends with conclusion.



Fig. 3 Block diagramof Pulse triggered flip flop
II. EXISTING PULSE-TRIGGERED FLIP-FLOPS
In implicit type flip-flops the clock distribution circuit is a
built in logic and there is no need for an external circuitry for
the clock division and distribution. Implicit type flip-flops has
two parts, a clock distribution network or clock tree and a
latch for data storage. Several low power techniques are
available which can be applied to the pulse flip-flops they are
conditional enhancement, conditional capture and conditional
data mapping. Implicit-type designs, however, face a
lengthened discharging path in latch design, which leads to
inferior timing characteristics. The situation deteriorates
further when low-power techniques such as conditional
capture, conditional pre-charge, conditional discharge, or
conditional data mapping are applied. As a consequence, the
transistors of pulse generation logic are often enlarged to
assure that the generated pulses are sufficiently wide to trigger
International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

ISSN: 2231-5381 http://www.ijettjournal.org Page 4261

the data capturing of the latch. Mainly Three conventional
implicit pulse flip-flops are discussed in this section.
A. Conventional IP-DCO (implicit pulsed-Data Close to
Output)
Implicit pulse generation is often considered to be more
power efficient than explicit pulse generation. This is because
the former merely controls the discharging path while the
latter needs to physically generate a pulse train. Implicit-type
designs, however, face a lengthened discharging path in latch
design, which leads to inferior timing characteristics [1]. In
digital circuit design, large proportion contributes to
synchronous design and they are operated based on the clock
signal to reduce the complexity of the circuit design. In the
design of sequential circuits, a major challenge is the design
of an efficient D flip-flop (DFF). Several static/dynamic DFF
architectures have been proposed in [1]-[10]. The topology
comparison commences with the conventional single edge
triggered flip -flop SET [1] typically latch data either at the
positive or negative edge of the clock. A SET FF can be
configured to operate as master slave latch by cascading the
sequential structure but it is incompetent as half of the clock
edges are wasted, while the full implementation cost of the
complete clock is endured. Next topology is double Edge
Triggered flip-flop DET, which can be triggered at the
positive as well as the negative edges. The implicit type flip-
flop generates the pulse inside the flip-flop. The circuit
diagramof ip-DCO is shown in the Figure 3.1. In ip-DCO the
clock signal and complement of the clock signal generates a
narrow pulse of short pulse width [6]. During this pulse the
output follows the input. First, during the rising edge, NMOS
transistor s N2 and N3 are turned on. If data remains high,
node x will be discharged on every rising edge of the clock.
This leads to a large switching power. The other problem is
that node x controls two larger MOS transistors (P2 and N5).
The large capacitive load to node x causes speed and
power performance degradation. When the x as denoted
floating node, The node x controls two larger transistors P2
and N5, this leads to large capacitive load to node x causes
power performance degradation. Some conventional implicit-
type P-FF designs, which are used as the reference designs in
later performance comparisons, are first reviewed. A state-of-
the-art P-FF design, named ip-DCO, is given in Fig. 1(a) [6].
It contains an AND logic-based pulse generator and a semi-
dynamic structured latch design. Inverters I5 and I6 are used
to latch data and inverters I7 and I8 are used to hold the
internal node. The pulse generator takes complementary and
delay skewed clock signals to generate a transparent window
equal in size to the delay by inverters I1-I3. Two practical
problems exist in this design. First, during the rising edge,
NMOS transistors N2 and N3 are turned on. If data remains
high, node will be discharged on every rising edge of the
clock. This leads to a large switching power. The other
problemis that node controls two larger MOS transistors (P2
and N5). The large capacitive load to node causes speed and
power performance degradation.


Fig. 4 Circuit Diagramof IP - DCO Flip-Flop
B. Hybrid Latch Flip-Flop (HLFF)
The Hybrid Latch Flip-Flop is a functionality based on
generating explicit transparency window where the transition
occurred. This occurrence is greatly reduces the complexity of
the locking systemresults in small delay and small area. The
hybrid latch flip-flop falls under hybrid category which has
impressive delay property and can have negative setup time.
HLFF is a static and single edge triggered Flip-flop, which
consumes more power, Existence of redundant transition in
internal node in HLFF indicate s more power consumption. It
is similar to latch because it can provide a soft clock edge
which allows for slack passing and minimize the effect of
clock skew on cycle time. The circuit diagram of HLFF is
shown in the figure 2. This structure is basically a level
sensitive latch which is clocked with an internally generated
sharp pulse, which generates at the positive edge of the clock
using clock and delayed version of clock. The number of
transistors in HLFF is higher and it has one to one glitch leads
to wasting of power. HLFF has very simple structure but
internal transition increase the total power consumption of
flip-flop. Every time, the input is high a glitch is generated,
regardless of previous state of the output Furthermore, the
transistors in stack degrade the performance of the logic. The
main advantage of HLFF structure has the soft edge property,
i.e., its robustness to clock Skew. One of the major drawbacks
of the hybrid design in general is the positive hold time Hence
we are going for the Modified designs of HLFF and it does
not useful for low power application, since its power
consumption limits its utilization.


International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

ISSN: 2231-5381 http://www.ijettjournal.org Page 4262


Fig. 5 Circuit Diagramof Hybrid Latch Flip-Flop
C. Modified Hybrid Latch Flip-flop (MHLLF)
The Modified Version of Hybrid Latch Flip-Flop is also
falls under the hybrid category of flip flop that has impressive
delay property and can have negative setup time with brief
transparency period. The given bellow diagramis modified
version of HLFF flip flop that has Lower number of
transistors as well as less power consumption.
It is by employing a static latch structure presented in [11].
Node X is no longer pre charged periodically by the clock
signal. A weak pull-up transistor P1 controlled by the Ff
output signal Q is used to maintain the node X level at high
when Q is zero and which eliminates the unnecessary
discharging problems at the node X. However, it encounters a
longer Data-to-Q (D-to-Q) delay during 0 to 1 transitions
becau7se node X is not Pre-charged. The transistors N3 and
N4 are required to enhance the discharging capability.
Another drawback of this design is that node x becomes
floating when output Q and input Data both equal to 1.If Node
X is drifted froman intact 1then extra Dc power emerges.

Fig. 6 Circuit Diagramof MHLLF

D. SCCER (Single Ended Conditional Capture Energy
Recovery)
SCCER is a design which is a modification over the ip-
DCO design. It uses a conditional discharged technique in
which the discharge path is controlled by eliminating the
switching activity when the input stays in stable HIGH. In
this design, the back to back inverters which are used instead
of pull up and pull down resistors is replaced by a weak pull
up transistor MP1 and inverter to reduce the load capacitance
of node. The series connection of two NMOS transistors MN1
and MN2 is used in the discharge path. An extra NMOS
transistor MN3 is used to eliminate the unwanted switching
activity.
Fig.7 shows SCCER with clock gating implemented by
changing the inverter with the NOR gate. The NOR gate has
two inputs: the clock signal and the enable signal. In the active
mode, the enable signal is low so the NOR gate behaves just
like an inverter and the flip-flop operates just like the original
flip-flop. In the idle state, The enable signal is set to high
which disables the internal clock by setting the output of the
NOR gate to be zero. This turns off the pull down path (mn2)
and prevents any evaluation of the data. Hence, not only the
internal clock is stopped (clock power saving) but also all the
internal switching is prevented (power saving on data
circuits). Typical waveforms for SCCER flip-flop with clock
gating are shown in the Fig.7. The skewed inverter was
replaced by a NOR gate. The skew direction for the NOR gate
should remain as that in the original inverter gate (skewed for
high to low transition; pull-down network stronger than pull-
up). Power dissipated by SCCER during the active mode for
different switching activities. Table shows the power
dissipated when clock gating is applied during the Deep
Submicron mode for different switching activities. Results
show that power savings of more than 1000 times are made
due to clock gating.
Table shows us the overhead due to implementation of
clock gating; there is no Power overhead for implementing
clock gating and a negligible delay penalty. We do not have
power overhead as we use minimumsized transistors for the
NOR gate and also reduction in the short circuit power
dissipated on the logic gates connected to the Sinusoidal clock
Our results show that we save 99.9% of power with clock
gating during idle states when compared to the flip flop
without clock gating. SCCER with clock gating shows power
savings without any probability of Deep Submicron mode.
Further savings are possible if there is some probability of
Deep Submicron mode. Therefore, SCCER with clock gating
is a better flip flop than the original SCCER without clock
gating.


International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

ISSN: 2231-5381 http://www.ijettjournal.org Page 4263


Fig. 7 Circuit Diagramof SCCER
By comparing implicit type P-FF designs with ip-DCO,
HLFF, MHLFF and SCCER, the P-FFs consumes much
power compared to the other types of flip flops. P-FF has been
considered as popular alternative to the conventional Master -
slave based FF in the applications of high speed operations
[1]. According to ip-DCO, it is the glitch free circuit and it is
the fastest implicit type P-FF designs under analysis but it
consumes much power. For improved P-ff design, named
MHLFF, in this the advantage is lower number of transistors
& less power consumption because by avoiding unnecessary
internal node transition but the delay is increased ip -DCO to
MHLFF and having glitches at the output. In energy recovery
FF like SCCER achieved very low power compared to
MHLFF but it contains more glitches & delay is further
increased from MHLFF to SCCER. Finally, in SCCER
consumes less power but delay is increased.
III. PROPOSED PULSE-TRIGGERED FLIP-FLOPS
The proposed design, as shown in Fig.8, adopts two
measures to overcome the problems associated with existing
Pulse Triggered FF designs. The first one is reducing the
number of NMOS transistors stacked in the discharging path.
The second one is supporting a mechanismto conditionally
enhance the pull down strength when input data is 1. Refer
to Fig.8; the upper part latch design is similar to SCCER
design [12]. As opposed to the transistor stacking design in
Fig. 4 and 6, transistor N2 is removed fromthe discharging
path.
Transistor N2, and N3, forms a 2 input, pass transistor
logic (PTL)-based AND gate [13], [14] to control the
discharge of transistor N1. Since the 2 inputs to the AND
logic are mostly complementary (except during the transition
edges of the clock), the output node X is kept at zero most of
the time. When both input signals equal to 0 (during the
falling edges of the clock), temporary floating at node X is
basically harmless. At the rising edges of the clock, the both
transistors N2 and N3 are turned ON and combined to pass a
weak logic high to node _, which then turns on transistor N1
by a time span defined by the delay inverter I1. The switching
power at node X can be reduced due to a diminished voltage
swing. Unlike the MHLLF design [11], where the discharge
control signal is driven by a single transistor, parallel
conduction of two NMOS transistors (N2 and N3) speeds up
the operations of pulse generation. With this design measure,
the number of stacked transistors along the discharging path is
reduced and the sizes of transistors N1-N5 can be reduced also.
In this design, the longest discharging path is formed when
input data is 1 while the Q bar output is 1. To enhance the
discharging under this condition, transistor P3 is added.
Transistor P3 is normally turned off because node x is pulled
high most of the time. It steps in when node x is discharged to
v (t p) below the v (d d). This provides additional boost to
node z (from v
dd
-v
th
to v
dd
). The generated pulse is taller,
which enhances the pull-down strength of transistor N1. After
the rising edge of the clock, the delay inverter I1 drives node x
back to zero through transistor N3 to shut down the
discharging path.
The voltage level of Node x rises and turns off transistor P3
eventually. With the intervention of P3, the width of the
generated discharging pulse is stretched out. This means to
create a pulse with sufficient width for correct data capturing,
a bulky delay inverter design, which constitutes most of the
power consumption in pulse generation logic, is no longer
needed. It should be noted that this conditional pulse
enhancement technique takes effects only when the FF output
Q data change from 0 to 1. The leads to a better power
performance than those schemes using an indiscriminate pulse
width enhancement approach. Another benefit of this
conditional pulse enhancement scheme is the reduction in
leakage power due to shrunken transistors in the critical
discharging path and in the delay inverter.




Fig. 8 P-FF design with pulse control scheme
International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

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A. Proposed Low Power Clocked Pass Transistor flip-flop
The Idea of designing the Pass transistor logic family
circuit uses only one clocking transistor so that it will be
consuming less power in the clock network by comparing
with all other circuits. This designs are having only 6
Transistors (excluding the NOT gates). So these designs have
much reduced power and area when compared to the other
designs. Due to the reduced no of transistor count we can
reduce the delay thus we can reduce the overall switching
delay and power, area consumption. So these circuits acts as
flip-flops when compared to other flip-flops design.
IV. SIMULATION RESULTS
The power consumption results are summarized in Table I.
Due to a shorter discharging path and the employment of a
conditional pulse enhancement scheme, the power
consumption of the proposed design is the lowest in all test
patterns.
Table I gives the leakage power consumption comparison
of these FF designs in a standby mode (clock signal is gated).
For a fair comparison, we assume the output Q as 0 when
input data is 1 to exclude the extra power consumption
coming from the discharging of the internal node .For
different clock and input data combinations, the proposed
design enjoys the minimum leakage power consumption,
which is mainly attributed to the reduction in the transistor
sizes along the discharging path. Compared to the
conventional TGFF design, the average leakage power is
reduced. All though significant fluctuations in pulse width and
height are observed, the unique conditional pulse
enhancement scheme works well in all cases. The simulations
are done using Micro wind & DSCH analysis software tools
and the result between all those types are listed below.



Fig.9: P-FF design with pulse control scheme in DSCH




Fig. 10 Simulation waveforms of p-ff



Fig. 11 Clocked Pass Transistor flip-flop



Fig. 12 Simulation waveforms (power characteristics) of Clocked Pass
Transistor flip-flops

International Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 9- September 2013

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Fig.13: Lay out diagramof p-ff

TABLE I
COMPARING THE FLIP-FLOP CHARACTERISTICS

V. CONCLUSIONS
In this Paper we tend to project the low power pulse
triggered FF design by employing two new design measures.
The first one successfully reduces the number of transistors
stacked along the discharging path by incorporating a PTL-
based AND logic. The second one supports conditional
enhancement to the height and width of the discharging pulse
so that the size of the transistors in the pulse generation circuit
can be kept minimum. Simulation results indicate that the
proposed design excels rival designs in performance indexes
such as power, D-to-Q delay, and PDP. Coupled with these
design merits is a longer hold-time requirement inherent in
pulse-triggered FF designs. However, hold-time violations are
much easier to fix in circuit design compared with the failures
in speed or power. Therefore our projected systemhas less
power and space constraints similarly because it has an
awfully low power duration systemwhich is able to result in
improvement within the case implementation in future
systems.
The simulations are done using Micro wind & DSCH
analysis software tools and the result between all those types
are listed below.
ACKNOWLEDGMENT
I express my truthful obligations to my guide and well-
wisher, Mr. Pritala. Aditya Ratna, M.Tech, Assistant
Professor, HOD of ECE for their bright guidance and useful
suggestions, which helped me in this project.
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P-FF Ip-
DCO
MHLLF SCCER Proposed
No. of
Transistor
23 19 17 19
Avg. power
(max.
activity)
68.5 68.8 52.3 44.5
Avg. power
(low activity)
57.3 65.5 49.7 35
Avg. power
(all zero)
mW
68.3 60.9 47.2 38.5
Avg. power
(all one) mW
40 50.8 40 35.5
Power delay
product (J)
2.07 1.85 2.7 0.75
Energy delay
product
(Ws
2
)
4.28 3.42 7.29 0.56
Setup
time(ps)
-35.8 8.3 -58.1 -39.7
Hold
time(ps)
47.4 82.2 59.3 85.1
Min data to
Q Delay(ps)
118.75 177.1 112.9 107.2
Clock tree
power W
6.41 7.82 12.58 8.03
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