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The impact of fringing field on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that a high-k gate dielectric degrades the device performance, in contrast with its n-channel counterpart, where the same has been reported to yield better performance.
The impact of fringing field on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that a high-k gate dielectric degrades the device performance, in contrast with its n-channel counterpart, where the same has been reported to yield better performance.
The impact of fringing field on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper. It is observed that a high-k gate dielectric degrades the device performance, in contrast with its n-channel counterpart, where the same has been reported to yield better performance.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO.
2, FEBRUARY 2012 277
The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High- Gate Dielectric Abhijit Mallik, Senior Member, IEEE, and Avik Chattopadhyay AbstractDetailed investigation, with the help of extensive de- vice simulations, of the effects of varying the dielectric constant of the gate dielectric on the device performance of a p-channel tunnel eld-effect transistor (p-TFET) is reported for the rst time in this paper. It is observed that the fringing eld arising out of a high- gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance. The impact of the fringing eld is found to be larger for a p-TFET with higher source doping. It is also found that the qualitative nature of the impact of the fringing eld does not change with dimension scaling. On the other hand, the higher electric eld due to increased oxide capacitance is found to be benecial for a p-TFET when a high- gate dielectric is used in it, as expected. It is also found that a low- spacer is benecial for a p-TFET, similar to that reported for an n-TFET of similar structure. Index TermsBand-to-band tunneling (BTBT), fringe-induced barrier lowering (FIBL), fringing eld, high- and low- di- electrics, tunnel eld-effect transistor (TFET). I. INTRODUCTION P OWER management has become the most crucial issue in further scaling of complementary metal oxidesemiconductor (MOS) technology. Due to dimension scaling, severe short-channel effects, such as drain-induced barrier lowering, result in substantial increase in leakage cur- rent. Moreover, the fundamental physical limit of (kT/q). ln10 (60 mV/dec at room temperature) on subthreshold swing S of a conventional MOS eld-effect transistor (MOSFET) poses a major roadblock in further scaling of its power supply voltage. In the search for an alternative device with low S, which is essential to maintain a high ON-state current I ON with an ac- ceptable OFF-state leakage current I OFF , for further extending the Moores law, a tunnel eld-effect transistor (TFET) shows great promise [1][8]. The device exploits a band-to-band Manuscript received September 7, 2011; revised October 14, 2011; accepted October 21, 2011. Date of publication November 16, 2011; date of current ver- sion January 25, 2012. This work was supported by the Department of Science and Technology, Government of India, under Grant SR/S3/EECE/0021/2009. The review of this paper was arranged by Editor R. Huang. The authors are with the Department of Electronic Science, University of Calcutta, Kolkata 700 009, India (e-mail: abhijit_mallik1965@yahoo.co.in; avikjoy@yahoo.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TED.2011.2173937 tunneling (BTBT) mechanism to overcome the subthreshold swing limitation of a conventional MOSFET. Both the theoreti- cal and experimental results showthat S can be much lower than 60 mV/dec for a TFET [6], [7]. Although the early reported TFETs suffered from low values of I ON , the same has been reported to dramatically improve by use of a SiGe [9], [10] or Ge [11] in the source region, double-gate (DG) architecture [10], [12], a thin silicon body [13], etc. It is well known that the fringing eld arising out of a high- dielectric causes fringing-induced barrier lowering (FIBL) [14]. Such FIBL has been reported to improve the device perfor- mance of an n-channel TFET (n-TFET) [15]. However, when used as a spacer for an n-TFET, the same deteriorates the device performance [15][17]. Very little is, however, reported in the literature on the impact of either a high- gate dielectric or a spacer on the device performance of a p-channel TFET (p-TFET). In this paper, we report a comprehensive investiga- tion on the impact of varying the dielectric constant of both the gate dielectric and the spacer on the device performance of a p-TFET. Moreover, we report the effects of varying the source doping concentration on the gate dielectric dependence of the device characteristics for a p-TFET. Furthermore, the impact of scaling on the gate dielectric dependence of the device characteristics is also investigated. II. DEVICE STRUCTURES AND SIMULATIONS Two-dimensional device simulations are done for the DG silicon p-TFET structure, as shown in Fig. 1, using the Version 5.11.24.C Silvaco ATLAS device simulator. Unless otherwise mentioned, the device dimensions, as shown in Fig. 1, are used for our simulations. Gate leakage is neglected in our simula- tions. The source and drain contacts are made of aluminum, and the gate contact is made of a metal for which the work function is 5.41 eV. Unless otherwise mentioned, the source and the drain are made of highly doped (1 10 20 atom/cm 3 ) n- and p-type regions, respectively. Gaussian doping prole with a doping gradient of 2 nm/dec is used for both the source and the drain. The intermediate channel region is made of a moderately doped (1 10 17 atom/cm 3 ) p-type layer. The simu- lated doping prole and the location of the metallurgical source- channel junction are shown in Fig. 2. The results presented here are obtained by using a nonlocal BTBT model combined with a band-gap-narrowing model and a quantum density-gradient model. 0018-9383/$26.00 2011 IEEE 278 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012 Fig. 1. Device structure for a DG p-TFET. Fig. 2. Simulated doping prole and location of the metallurgical junction for the device, as shown in Fig. 1. III. RESULTS AND DISCUSSIONS A. Effects of Variation in the Gate Dielectric Constant The purpose of using a high- gate dielectric in CMOS tech- nology is to achieve lower equivalent oxide thickness (EOT) without enhancing the gate leakage. This is achieved by increas- ing the value of the gate dielectric while keeping its physical thickness constant. In doing so, a high- dielectric induces a higher electrical eld at the surface due to the increased oxide capacitance. The impact of such higher electric eld at the surface is investigated by keeping the physical thickness of the gate dielectric constant, as done in [12] and [16] for an n-TFET. On the other hand, the fringing eld arising out of a high- gate dielectric causes FIBL [14]. Although such FIBL is known to degrade the performance of a conventional MOSFET [14], [18], it actually helps improve the performance of an n-TFET [15]. The impact of such fringing eld arising out of a high- gate dielectric in a p-TFET is studied by keeping the EOT of the gate dielectric constant, as done in [15] for an n-TFET. 1) Impact of Fringing Field (Constant EOT): We rst inves- tigate the impact of the fringing eld arising out of a high- gate dielectric by keeping the EOT of the gate dielectric constant. The effects of varying the value of the gate dielectric on the transfer characteristics at drain-to-source voltage V DS = 1 V of the p-TFET, as shown in Fig. 1, with a drawn gate length L = 50 nm and EOT = 2 nm, are shown in Fig. 3(a). No spacer is used in this case. The values of the gate dielectric used are 3.9, 7.5, 21, 50, 100, and 200. It may be noted that, although a Fig. 3. Impact of varying the value of the gate dielectric for the device in Fig. 1 with L = 50 nm and EOT = 2 nm but without a spacer. (a) Transfer characteristics at V DS = 1 V. (b) Variation of V T and I ON with the value. symmetric device structure is used for the simulations, only the p-type branch is shown in Fig. 3(a) for simplicity. The values of threshold voltage V T and I ON for different values of the gate dielectric are extracted from the transfer characteristics in Fig. 3(a) and are plotted in Fig. 3(b) as a function of the value. In this paper, the constant current (10 7 A/m) method is used for extracting V T , and I ON is assumed to be the value of drain current I D corresponding to a gate-to-source voltage V GS swing of 1 V from the point where the current changes from p-i-n leakage to tunneling. It is observed in Fig. 3 that an increase in the value, except from = 100 to 200, results in corresponding degradation of device performance in terms of both V T and I ON . An improvement in both V T and I ON is observed for = 200, compared with that for = 100. This is in contrast with that reported for an n-TFET, where an increase in the value of the gate dielectric results in improvement of the device performance [15], except when is relatively low. When is increased from 3.9 to 21, a deterioration and improvement in I D have been reported in [15] for relatively low and high values of V GS , respectively. We have also veried that the qualitative results presented in this paper for I ON do not change when the same is extracted at a constant gate overdrive voltage V GT = V GS V T . The simulated electron energy band diagram for the p-TFET biased at V GS = V DS = 1 V at a distance of 1 nm below the top oxidesemiconductor interface is shown in Fig. 4 for MALLIK AND CHATTOPADHYAY: IMPACT OF FRINGING FIELD ON PERFORMANCE OF p-TFET 279 Fig. 4. Simulated energy band diagram near the tunneling junction at a depth of 1 nm from the oxidesemiconductor interface as a function of the value of the gate dielectric at V GS = V DS = 1 V. different values of the gate dielectric. The band diagram is shown only around the tunneling junction. In a p-TFET, the BTBT of holes occurs from the source to the channel, resulting in the drain current. This is equivalent to the BTBT of electrons from the valance band of the channel, which is henceforth referred to as the tunnel source, into the conduction band of the source, which is henceforth referred to as the tunnel destination. The potential barrier formed by the band gap of the semiconductor across which the tunneling takes place is henceforth referred to as the tunneling junction. The fringing eld arising out of a high- dielectric causes fringe-induced barrier lowering for an n-channel device [14]. In contrast, it is observed in Fig. 4 that the bands are pushed up in energy when the value of the gate dielectric is increased in the case of a p-TFET, which is simply due to the use of opposite polarity (negative) of the gate bias in such devices. The fringing eld in the device is shown in Fig. 5 for two different values of the gate dielectric, corresponding to SiO 2 and HfO 2 . It is observed in Fig. 5 that the fringing eld in the source near the gate edge is larger for a device with a high- gate dielectric, compared with that with a low- dielectric. As a result, as evident in Fig. 4, the impact of the fringing eld is found to be larger near the gate edge than the rest of the device. It is also evident in Fig. 4 that, when the value is increased from 3.9 to 100, the amount by which the energy bands are pushed up, which is henceforth referred to as the impact of fringing eld, becomes larger for the tunnel destination than that for the tunnel source. This results in a larger value of the minimum tunnel width and a correspondingly smaller value of the maximum electric eld across the tunneling junction, when the value of the gate dielectric is increased from 3.9 to 100, as can be veried in Fig. 6. This, in turn, causes degradation of the device performance for increasing the value of the gate dielectric up to = 100, as observed in Fig. 3. It is also noticed in Fig. 4 that an increase in the value results in a corresponding shift in the location of the tunneling junction toward the source. Due to a signicant shift in the location of the tunneling junction when the value is increased from 100 to 200, the impact of the fringing eld, which is always maximum at the gate edge, becomes larger on the tunnel source than that on the tunnel destination. As a result, an improvement in the device Fig. 5. Fringing eld plot for the p-TFET biased at V GS = V DS = 1 V for two different values of the gate dielectric of EOT = 2 nm. (a) = 3.9. (b) = 21. Fig. 6. Minimum tunnel width and maximum electric eld across the tunnel- ing junction for the p-TFET biased at V GS = V DS = 1 V for different values of the gate dielectric of the same EOT. performance is observed in Fig. 3 when the value is increased from 100 to 200. 2) Impact of Varying the Source Doping: We now see the impact of varying the source doping concentration on the gate- dielectric dependence of the device performance. The device structure, as shown in Fig. 1, with L = 50 nm and EOT = 2 nm but without a spacer, as in the previous case, is simulated for two different values of the source doping concentration as 3 10 20 and 5 10 19 atoms/cm 3 . For each of the source doping concentrations, the transfer characteristic is plotted in Fig. 7 for 280 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012 Fig. 7. Transfer characteristics at V DS = 1 V showing the impact of varying the source doping concentration on the gate-dielectric dependence of p-TFET characteristics. No spacer is used in this case. The EOT of the gate dielectric is kept constant at 2 nm. Fig. 8. Impact of varying the source doping concentration on the simulated energy band diagram near the tunneling junction of the p-TFETs with different gate dielectrics biased at V GS = V DS = 1 V. two different values of the gate dielectric, corresponding to SiO 2 and HfO 2 . The corresponding energy band diagrams at V GS = V DS = 1 V are shown in Fig. 8. For a given value of , it is observed in Fig. 7 that an increase in the source doping concentration results in corresponding improvement in the device performance, as expected. This is simply due to the fact that a relatively higher source doping not only causes more band lowering of the tunnel destination but it also reduces the source depletion and, hence, less depletion width, as evident in Fig. 8. As a result, the minimum value of the tunnel width is reduced, and the maximum electric eld is increased across the tunneling junction. It is, however, interesting to note that, in Fig. 7, a relatively lower source doping reduces the gate- dielectric dependence of the device performance, which is in contrast with that intuitively expected. This can be attributed to the combined inuence of the following two: First, a decrease in the source doping concentration results in corresponding shift in the location of the tunneling junction toward the source, which is due to larger source depletion for lower source doping, as evident in Fig. 8. Second, a larger impact of the fringing eld arising out of the gate dielectric is observed at the gate edge than the rest of the device, as can also be veried in Fig. 8. As a result, for a device with higher source doping, the impact of the fringing eld across the tunneling junction is found to be much larger on the tunnel destination, compared with that on Fig. 9. Plot showing the variations of V T and I ON with the value of the gate dielectric for a p-TFET with L = 30 nm and EOT = 1 nm. The inset shows the plot for a p-TFET with L = 100 nm and EOT = 4 nm. the tunnel source. This, in turn, results in signicant widening of the tunnel width, thereby degrading the device performance drastically. In contrast, due to a shift in the location of the tunneling junction toward the source for a device with lower source doping, the impact of the fringing eld on the tunnel source partly compensates its impact on the tunnel destination. As a result, the gate-dielectric dependence of the device char- acteristics is somewhat reduced when a relatively lower source doping concentration is used. 3) Impact of Device Scaling: The impact of device scaling on the gate-dielectric dependence of p-TFET characteristics is now investigated. For this purpose, device simulation is done for two different p-TFETs: one with L = 100 nm and EOT = 4 nm and the other with L = 30 nm and EOT = 1 nm. All other device dimensions and parameters are kept the same as in the previous case. Fig. 9 shows the plot of V T and I ON as a function of the value of the gate dielectric for the device with L = 30 nm and EOT = 1 nm, whereas the inset of Fig. 9 shows the plot for the device with L = 100 nm and EOT = 4 nm. It is evident in Fig. 9 that the qualitative nature of the impact of fringing eld does not change with dimension scaling. An increase in value, except from = 100 to 200, results in corresponding degradation of the device performance in terms of both V T and I ON for both the devices, similar to that observed in Fig. 3(b) for a device with L = 50 nm and EOT = 2 nm. In addition, an improvement in both V T and I ON is observed for = 200, compared with that for = 100 in Fig. 9 for both the devices, similar to that observed in Fig. 3(b). The TFET characteristics are known to be independent of the channel length down to about 20 nm [9], [21], [22]. A careful examination of I ON values in Fig. 9, however, reveals that I ON increases with decreasing channel length for a given k value of the gate dielectric. We have veried that such increase in I ON is due to the scaling of the EOT in our devices. I ON has been found to be less sensitive to channel length scaling when the EOT is kept at the same value, which is in consistence with the reported results. 4) Impact of Higher Electric Field (Constant Physical Thickness): We now investigate the impact of the higher elec- tric eld at the surface of a p-TFET, when a high- gate dielectric is used in it, by keeping the physical thickness of the gate dielectric constant. For this purpose, device simulation is MALLIK AND CHATTOPADHYAY: IMPACT OF FRINGING FIELD ON PERFORMANCE OF p-TFET 281 Fig. 10. V T and I ON as a function of the value of the gate dielectric of 3-nm physical thickness for a p-TFET with L = 50 nm but without a spacer. done for a p-TFET, as shown in Fig. 1, with L = 50 nm, for varying values of the gate dielectric with a physical thickness of 3 nm. The values used in this case are 3.9, 7.5, 21, and 29. No spacer is used in this case also, as earlier. The values of V T and I ON are extracted for different values of the gate dielectric from the simulated transfer characteristics. Fig. 10 shows the plot of V T and I ON as a function of the value of the gate dielectric. It is observed in Fig. 10 that the device performance is improved, both in terms of I ON and V T , when a high- gate dielectric of the same physical thickness is used in a p-TFET. A high- gate dielectric of the same physical thickness has larger oxide capacitance that is expected to increase the tunneling probability as per [12, eq. (4)], which was originally derived in [19] for silicon-on-insulator MOSFETs. To verify it, we plot in Fig. 11 the simulated electron energy band diagram around the tunneling junction for the p-TFET biased at V GS = 0.6 V and V DS = 1 V at a distance of 1 nm below the top oxidesemiconductor interface for different values of the gate dielectric of the same physical thickness. Increasing the value of the gate dielectric, of the same physical thickness, results in higher surface electric eld under the gate. As a result, a larger impact of the high- gate dielectric is observed in Fig. 11 for the tunnel source, compared with that for the tunnel destination. This results in better device performance for higher value of the gate dielectric of the same physical thickness, as observed in Fig. 10. It may also be noted that, when the value of the gate dielectric is increased while keeping its physical thickness constant, the impact of the higher electric eld due to increased oxide capacitance, which results in improved device performance, dominates over that of the fringing eld, which results in degraded performance, as observed earlier. B. Effects of Variation in the Spacer Dielectric Constant The impact of a spacer on the device performance of a p-TFET is studied by varying the value of the spacer while keeping its width xed at 50 nm for the device structure, as shown in Fig. 1, with L = 50 nm. A silicon dioxide of 1-nm thickness is used as the gate insulator in this case. The values of the spacer used are 3.9, 7.5, 21, and 50. The effects of varying the value of the spacer on the transfer characteristics of the p-TFET are shown in Fig. 12. The device characteristic Fig. 11. Simulated energy band diagram near the tunneling junction at a depth of 1 nm from the oxidesemiconductor interface as a function of the value of the gate dielectric of 3-nm physical thickness at V GS = 0.6 V and V DS = 1 V. Fig. 12. Impact of varying the value of the spacer on the transfer character- istics for the device in Fig. 1 with L = 50 nm. The inset shows the variations of V T and I ON with the value of the spacer. Silicon dioxide of 1-nm thickness is used as the gate dielectric in this case. for a p-TFET without a spacer is also shown in Fig. 12 for comparison. The values of V T and I ON are extracted from the transfer characteristics in Fig. 12, and plotted in the inset of Fig. 12 as a function of the value of the spacer. It is evident in Fig. 12 that an increase in the value of the spacer results in a corresponding degradation of the device performance, in terms of both V T and I ON , of a p-TFET. This is very similar to that reported in [17] for an n-TFET of similar structure. The impact of the fringing eld arising out of the spacer is expected to be larger for the source (tunnel destination) than that for the channel (tunnel source) for such a p-TFET structure that causes degradation of the device performance when the value of the spacer is increased. Virani et al. [20] proposed an advanced dual- spacer tech- nology for an n-TFET consisting of a 2-nm-wide high- inner spacer adjacent to the gate and an 8-nm-wide low- outer spacer for a 20-nm-gate-length device, which has been found to improve the device performance of such devices. Moreover, it has also been reported in [20] that the fringing eld out of a high- gate dielectric deteriorates the performance of an n-TFET, in the presence of such a dual- spacer, which is in contrast to that reported in [15] for a relatively simple n-TFET structure. It may be mentioned here that, in this pa- per, the impact of a high- gate dielectric and a spacer on 282 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 2, FEBRUARY 2012 the device performance is investigated for a relatively simple p-TFET structure, similar to that used in [12], [15][17] for an n-TFET, to develop basic understanding on this subject. Since it is done, it is now open for the researchers to take up a study to investigate the impact of a similar dual- spacer technology for a p-TFET. IV. CONCLUSION A systematic investigation of the impact of the fringing eld arising out of a high- gate dielectric on the device performance of a p-TFET has been made. The fringing eld arising out of a high- gate dielectric has been found to deteriorate the perfor- mance of a p-TFET, in contrast with its n-channel counterpart, where it has been reported to improve the performance. It has also been found that the fringing eld arising out of a high- gate dielectric has greater impact for a p-TFET with higher source doping concentration. In addition, the qualitative nature of the impact of fringing eld has been found to be independent of dimension scaling. The impact of a spacer on a p-TFET, however, has been found to be very similar to that on an n-TFET of similar structure, as reported earlier. Our ndings can be a guide for the design of a p-TFET for complementary TFET applications. REFERENCES [1] W. M. Reddick and G. A. J. Amaratunga, Silicon surface tunnel transis- tor, Appl. Phys. Lett., vol. 67, no. 4, pp. 494497, Jul. 1995. [2] J. Koga and A. Toriumi, Three-terminal silicon surface junction tunnel- ing device for room temperature operation, IEEE Electron Device Lett., vol. 20, no. 10, pp. 529531, Oct. 1999. [3] C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, Lateral interband tunneling transistor in silicon-on-insulator, Appl. Phys. Lett., vol. 84, no. 10, pp. 17801782, Mar. 2004. [4] W. Hansch, C. Fink, J. Schulze, and I. Eisele, A vertical MOS-gated Esaki tunneling transistor in silicon, Thin Solid Films, vol. 369, no. 1/2, pp. 387389, Jul. 2000. [5] W. Hansch, P. Borthen, J. Schulze, C. Fink, T. Sulima, and I. Eisele, Performance improvement in vertical surface tunneling transistors by a boron surface phase, Jpn. J. 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Lee, Scaling the Si MOSFET: From bulk to SOI to bulk, IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 17041710, Jul. 1992. [20] H. G. Virani, R. B. R. Adari, and A. Kottantharayil, Dual- spacer device architecture for the improvement of performance of silicon n-channel tunnel FETs, IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2410 2417, Oct. 2010. [21] K. Boucart and A. M. Ionescu, A new denition of threshold voltage in Tunnel FETs, Solid State Electron., vol. 52, no. 9, pp. 13181323, Sep. 2008. [22] C. Sandow, J. Knoch, C. Urban, Q.-T. Zhao, and S. Mantl, Impact of elec- trostatics and doping concentration on the performance of silicon tunnel eld-effect transistors, Solid State Electron., vol. 53, no. 10, pp. 1126 1129, Oct. 2009. Abhijit Mallik (M00SM06) received the M.Sc. degree in electronic science from the University of Calcutta, Kolkata, India, in 1989 and the Ph.D. de- gree in electrical engineering from Indian Institute of Technology (IIT), Bombay, India, in 1994. His Ph.D. dissertation was on reoxidized nitrided ox- ide metaloxidesemiconductor (MOS) devices for radiation-hard applications. He played a key role in developing a radiation- hard chip going up to 1 Mrad(Si) while he was with IIT, Bombay. From 1994 to 1995, he was a Postdoc- toral Fellow with the Department of Electrical Engineering, Yale University, New Haven, CT, where he worked on process development and interface characterization of jet-vapor-deposited (JVD) silicon nitride as an alternative gate insulator for ultralarge-scale-integration applications. He was with the Department of Electronics and Communication Engineering, Kalyani Govern- ment Engineering College, Kalyani, India, for ten years before joining the University of Calcutta, Kolkata, India, in 2007, where he is currently a Professor with the Department of Electronic Science. His research interests include the physics, technology, characterization, and modeling of both classical and novel complementary metaloxidesemiconductor devices. Dr. Mallik is currently the Vice-Chairperson of the IEEE Electron Devices Society Calcutta Chapter. Avik Chattopadhyay received the B.Tech. degree in electronics and communication engineering from West Bengal University of Technology, Kolkata, India, in 2006 and the M.Tech. degree in very large scale integration design, in 2009, from the University of Calcutta, Kolkata, where he is currently working toward the Ph.D. degree, with nanoelectronics as the area of specialization, in the Department of Elec- tronic Science. From 2006 to 2007, he was with Cognizant Tech- nology Solutions Pvt. Ltd., Kolkata, as a Program- mer Analyst. His current research interests include novel complementary metaloxidesemiconductor devices such as tunnel eld-effect transistors.