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515

The Future of the PCB Arnold Wiemers Introduction Preliminary information: The CAD layouters and the
The Future of the PCB
Arnold Wiemers
Introduction
Preliminary information:
The CAD layouters and the assembly developers may practically
receive any PCB quality they demand.
The PCB manufacturers as well do not have to worry: The PCB will
also be in demand in future.
The tendency is evident: The PCB will become more complex and
more universal (figure 1, figure 2). However, already at this point,
the first drop of bitterness casts a cloud over the enthusiasm: The
PCB will also become more sensitive and more expensive.
To explain the technological developments, I would like to give you
an overview of the essential aspects by which the production of
multilayer boards is influenced. This overview will indicate which
variation ranges of materials, galvanic surface-finishes, mechani-
cal treatments and image structures are available. It will reveal in-
dispensable organization principles to be exactly considered, if the
construction and specification of a PCB by a layouter is to be suc-
cessful.
Figure 1:
Development of
the conductive
pattern structures
300
250
200
150
100
50
89
90
91
92
93
94
95
96
97
98
99
Year
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Conductive pattern structures in µm
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516

The Future of the PCB Figure 2: Development of the pad and track geometries 300
The Future of the PCB
Figure 2:
Development of
the pad and track
geometries
300
200
200
200
100
80
1600
600
500
400
200
100
SIL/DIL
SMD
Fine-Pitch
MCM/COB
Pad and track geometries (µm)
We do not talk about the really big sensations here, but the stand-
ard products are interesting which will define the daily work of the
layouter, of the PCB manufacturers and of the assembly providers
in one or two years.
These products will be 4, 6, or 8-layer boards as carrier for COB or
MCMs or simply as normal, real PCBs.
One interesting aspect is the indication of the actual possibilites of
the development of 200 µm to 150 µm, 100 µm and finally 50 µm-
structures (figures 3 and 4).
The reference is an assumed PCB, a multilayer board with a con-
ductive pattern structure of a track-width and of a track-distance of
150 µm.
Due to the current discussions concerning high-technology in the
field of the PCB production, a 150 µm-PCB should nowadays be a
common standard product for each PCB manufacturer. The tech-
nical specification of an assembly of such parameters as well
should not cause any problems for the CAD designers.
However, we will see: There are some questions which still require
some answers.
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The Future of the PCB Figure 3: Carrier module for COB / flip-chip 80µm Flip-chip
The Future of the PCB
Figure 3: Carrier
module for COB /
flip-chip
80µm
Flip-chip on carrier module
MFT: Example: flip-chip
Figure 4:
Switching module
with COB
80µm
Switching module with COB
MFT: Example: COB-module
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518

The Future of the PCB

Base materials The appropriate material for an electronic circuit has actually to be chosen BEFORE starting with the layout. The discussions regarding electromagnetic compatibility, high- speed circuits and impedance-control has already been linked with the technical features of the material assuming that the layouter is familiar with material parameters like Tg-value (glass transition temperature), eR-value (dielectric feature) and material composi- tion (glass fabric, resin content, chemical classification of matter. The layouter must also know the prices (figure 5).

Figure 5: Base materials for PCBs

Group

Composition

Tg

ε r

Relative

 

costs

 

Bismaleinimide triazine resin with silica glass

180-

3.9-

 

BT

220

4.9

5.3

CE

Cyanate ester with silica glass

230

3.6

4.5

CEM1

Paper phenolic core with FR4-outer layers

130

4.7

0.95

CEM3

Glass mat (or glass felt) core with FR4-outer layers

130

5.2

0.95

FR2

Phenolic resin paper

105

4.7

0.73

FR3

Epoxy paper

110

4.9

0.85

   

135-

 

1

FR4

Epoxy glass fibre laminate

170

4.7

Reference

FR5

Epoxy glass fibre laminate with crosslinked resin system

160

4.6

1.4

PD

Polyimide resin with aramide-reinforcement

260

3.5

6.5

PTFE

Polytetrafluoroethylene with glass or ceramics

240-

2.2-

32-78

280

10.2

CHn

High-interlaced hydrocarbons with ceramics

 

4.5-

 

300

9.8

90

The PCB manufacturer's logistics has to ensure a stockpiling in time. This is not a simple task because the variety of material types, material thicknesses and copper clads may lead to an ex- ploding stock.

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The Future of the PCB The list of possible inner layer combinations makes this aspect
The Future of the PCB
The list of possible inner layer combinations makes this aspect
more obvious (figure 6). However, if these stocks can be reduced
due to future orders, will become more and more doubtful.
Whereas base laminates are durable for years, some prepreg
types can only be stockpiled for several months. If the prepregs are
not used within this period of time, they will have to be eliminated.
Over-stock prepregs would produce a delamination of the multilay-
er board and the product could therefore not be used.
A
far more complex task for the PCB manufacturer is to adapt the
production processes to the different characteristics of the base
materials which are based on the altered combination of chemical
basic substances.
It
cannot be taken for granted that the contacting of complex multi-
layer levels on FR4 (glass) is of the same quality than on PTFE
(glass/ceramics) or on PD (polyimide + aramide). In particular, if
the frequently very different and decisive resin proportions and
qualities of the materials are also taken into account.
Figure 6:
Laminates for
multilayer board
inner layers
Laminate
Prepregs
Cu-clad
0.050
0.050
0.005
0.060
0.060
0.009
0.075
0.100
0.017
0.100
0.200
0.035
0.200
0.070
0.250
0.105
0.360
0.460
0.710
0.930
1.000
1.130
1.430
1.860
Laminates are indicated
1.930
without Cu-clad
2.330
Multilayer board laminates
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520

 

The Future of the PCB

 

It can also not be taken for granted that these different materials can be drilled without reducing the quality of the hole walls and without reducing the reliability of the solder resists to adhere to the surface.

The fact that base materials for PCBs can be produced in such an individual form is very much a point in the favour of the PCB man- ufacturers. The actual solution, however, was found by the part- ners of the PCB manufacturers, the chemical and material manufacturers. Their contribution to this success was the most im- portant one.

Conductive

The miniaturization of the components also requires miniaturized conductive pattern resolutions. The structure exposure therefore be- comes a considerable challenge.

pattern

 

structuring

In the general opinion, if the problem is solved to expose track- widths and track-distances of 80 µm or even 50 µm, all subsequent production steps are inferior.

This is unfortunately NOT the case.

 

The laminating of the photo laminate (before) and the etching of the structures (afterwards) belong to the production process of the con- ductive pattern structuring.

Films (standard), glass master plates (scarcely) and laser machines (even more rarely) are available as exposure tools. If diazofilms (copies of the original plot) were used in the past, black films (origi- nal plots) are now commonly used. The extraordinary quality of these films allows structures up to 60 µm. If this threshold range can- not be reached, the common hardware (exposure devices) and the ambient conditions (clean-room conditions) are often the reason for this.

In case of laser machines, the limit is near 40 µm. Decisive for the better results of the laser exposure, compared with the film, is the register accuracy to the drilling pattern (optical registration), the fea- sibility of reproduction (no misalignments), the generally smaller me- chanical tolerances (reception systems, no vacuum fixing), and the fact that some production steps are no longer needed (figure 7).

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521

The Future of the PCB

The photo laminate has to take up the image structure during the ex- posure and must completely "store" it. Due to the exposure process, the molecular structure of the laminate changes - it cures. It is nec- essary that the curing is effected homogenously over the total thick- ness of the photo laminate to receive a fine, sharp-contoured conductive pattern which is also stable at the edges. An increase in the light energy (scattering) is not sufficient. Thinner photo laminates with a thickness of 20 up to 25 µm (the standard is 38 µm) will ensure these demands. Unfortunately, these thin lami- nates are only rarely available at the moment (figure 8).

Figure 7:

Comparison between diazofilm, black film and laser direct imaging

Time

24h

10h

3h

Tolerance

0.1mm

0.1mm

0.03mm

Expose conductive pattern

Register film

Laminate PCBs

Plate PCBs

Drill PCBs

Retouch diazofilm

Produce diazofilm

Measure film

Verify film

Develop film

Produce photo plots

Documentation

CAM processing

required not required

Diazofilm

Black film

Laser

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The Future of the PCB Figure 8: Comparison between 38 µm and 20 µm laminate
The Future of the PCB
Figure 8:
Comparison
between 38 µm
and 20 µm
laminate
Standard
Exposure
200ym
200ym
38
µm photo laminate
17
µm copper clad
100 µm inner layers
Exposure
Superfine-line
100ym
100ym
20
µm photo laminate
5 µm copper clad
50
µm inner layers
Structure exposure
Finally, the etching process decides, if the structuring of the con-
ductive pattern is successful. This production step is the most un-
popular one for each PCB manufacturer, if the layout demands
tracks and distances smaller than 150 µm. The defined application
(spraying) of the liquid etchant on the PCB and the subsequent re-
moval (washing) cannot be carried out so precisely as demanded
even by computer-controlled machines. The losses of 10 up to 30
µm regarding structures to be produced are definitly unpleasant in
superfine-line or in super-microfine-line technology.
Holes + vias
The drilling of PCBs is THE current subject, i.e, the connection of
selective layers of a multilayer board (figure 9). The discussion in-
dicates the necessity to assign at least a rough classification sys-
tem to the circulating terms.
Functional classes
"Holes" are used for the reception of components or for the fixing
of the future assembly (either in the terminal device or in the as-
sembly machine).
A hole goes through every layer of a PCB.
A hole may take over the function of a via.
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The Future of the PCB Figure 9: Different via types for PCBs Via 0.25 up
The Future of the PCB
Figure 9: Different
via types for
PCBs
Via 0.25
up to 0.10 mm
1.0
BS
0.8
I2
0.6
I3
0.4
I4
0.2
I5
0.0
LS
Standard
Buried Vias
Blind Vias
Via types in UTMs for MFT
Vias ensure the signal flow over several layers of a PCB.
A
via connects at least 2, more than 2, but at best all layers of a
PCB.
A
via should never take over the function of a hole.
a via connects ALL layers of a PCB, then it is called a "through-
via".
If
a via connects two or more than two layers but not all layers of a
PCB, it is called a "partial via".
If
There are two variants of partial vias: as "blind via" or as a "buried
via".
Blind vias ALWAYS connect one or several - but not all - inner lay-
ers of a multilayer board to an outer layer.
Buried vias connect 2 or more layers inside the multilayer board,
however, they NEVER produce any contact to an outer layer.
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524

 

The Future of the PCB

 

Mechanical classes

The term "micro via" indicates that the mechanical diameter of this via is considerably smaller than 100 µm. The threshold range is ap- prox. 50 µm.

From 100 µm on vias are called via.

 

Production technological classes

"Laser vias" are partial vias which are technically produced by a la- ser. Two adjacent layers may be connected. This technology can be applied for common base materials. Through-vias are not pos- sible.

"Photo vias" are partial vias which are produced by the phototech- nical structuring and the subsequent galvanotechnical build-up of the laminate between adjacent layers. The isolation of the individ- ual, electronically active layers is effected by the laminate. The possible applications and the stability of this technology are subject to intensive research.

"Plasma etching" in a plasma atmosphere produces partial vias, if appropriate materials are used. This technique cannot be applied for standard base materials. Through-vias are not possible.

"Micro holes" are mechanically produced as usual. Available drill- ing tools have diameters up to minimum 0.1 mm. Therefore, both partial and through-vias can conventionally be drilled.

These technologies are altogether a treasure of alternatives at the disposal of the PCB manufacturer and among which the CAD de- signer may have the choice. -

Or so it seems at first sight.

 

In practice, the via technologies have only the value of the sphere to which they are related. Regarding blind vias, a rule says that the via-depth should not exceed the via-diameter. Otherwise, the gal- vanotechnical connection of the individual signal levels is problem- atic and not reliable. Due to this reason, the via-depth and the via- diameter must also be adapted to each other in case of "through- vias" (relation approx. 6 : 1).

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The Future of the PCB

 

In case of laser vias, photo vias or during plasma etching, only two adjacent layers may be connected. Necessary vias over more than 2 layers or required through-vias must still be drilled mechanically so that a combination of technologies becomes necessary.

Without doubt, all connecting processes contribute to a considerable increase in the density of image structures on the PCB.

Surface-finishes Additional connection technologies regarding the classic soldering process are nowadays the bonding and - relatively new - the glue- ing of components on the PCB. For each individual technology, there are very good solutions.

 

The requirements, however, increase, if different connection tech- niques are to be combined on one PCB because the components are not otherwise available or the reduced space requires such measures. A variety of surface-finishes with different features are available (figure 10). Due to SMD components with fine-pitch dis- tances, plane surface-finishes are required. When choosing a sur- face-finish, the costs should not be neglected.

The good, old "tin lead" surface-finish cannot be recommended an- ymore, because the surface is too bended. This surface-finish is not expensive, it should, however, only be used for THT compo- nents or in combination with SMD components in a grid distance not less than 1.27 mm.

"Hot-air-leveling" is still a favourable alternative as well for standard SMDs (pitch-distance = 1.27 mm), with its process related surface roughness of 10 - 20 µm, however, too undefined.

"Nickel" is an alternative in case of mechanically loaded surface- finishes, if switching functions are directly guided via the surface. The soldering behaviour, however, is always temperamental.

"Copper" is generally not worth discussing. The advantage of the OSP variant "Entek+" is that it is not expensive.

"Immersion tin" offers a plane surface and is inexpensive. The process can be easily handled within the production, the results, however, are not completely free of surprises.

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The Future of the PCB

"Immersion gold" and "galvanic gold" offer a considerably better quality of the surface-finish.

The gold layer is 0.05 - 0.2 µm in case of immersion gold and 1.5 µm in case of galvanic gold. The gold is applied on nickel. Both var- iants are easy to be soldered. Immersion gold is suitable for bond- ing aluminium wires which are adapted ON the nickel surface- finish. Gold will then be the corrosion protection. These surface-finishes are extraordinarily suitable for the glueing technique, if bright-copper is applied beneath the gold layer be- cause therefore the surface roughness is improved from > 4µm to < 1 µm.

"Immersion bond gold (reductive)" and "galvanic bond gold" are especially adapted to the bonding technique. The thickness of the gold layers is 0.3 - 0.6 µm in case of "immersion bond gold" and 1 - 2 µm in case of "galvanic bond gold". The bonding is carried out by gold wires IN the gold surface-finish. This gold as well is applied on nickel.

Figure 10:

Galvanic surface- finishes for PCBs

Galvanic surfaces

Connection technique

Relative

Sol-

Bon-

Glu-

costs

dering

ding

eing

Tin lead

Tin lead   +- - 1.00
 

+-

-

1.00

Bond gold (immer- sion)

Bond gold (immer- sion) + Au + + 1.50

+

Au +

+

1.50

Bond gold (galvanic)

Bond gold (galvanic) + Au + + 3.00

+

Au +

+

3.00

Entek+

Entek+   +- - 1.00
 

+-

-

1.00

Gold (immersion)

Gold (immersion) + Al + + 1.15

+

Al +

+

1.15

Gold (galvanic)

Gold (galvanic) + Al + + 1.70

+

Al +

+

1.70

Hot-Air leveling

Hot-Air leveling   +- - 1.00
 

+-

-

1.00

Copper

Copper   +- - 0.90
 

+-

-

0.90

Nickel

Nickel   +- - 1.00
 

+-

-

1.00

Tin (immersion)

Tin (immersion)   +- + 0.90
 

+-

+

0.90

In addition to the general definition of galvanic surface-finishes, there are also several metallizations which mainly take over the functions of solder depots completely replacing the solder paste print before the assembly process.

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Surface-finish combinations, "tin lead" for example with "partial gilding", are more rarely used at present. The reduced costs do not justify the the complicated production process, especially in case of smaller series.

All things considered, the scope of galvanic surface-finishes is suf- ficient. In the opinion of the PCB manufacturers, the problems can be found during the further processing in the assembly technology. The variety of the surface-finishes consequently requires a variety of assembly preparations and of soldering techniques to be used. There is still a demand for harmonization.

Lacquers + pastes The lacquers used in the PCB production are wrongly in the shad- ow of the ubiquitously discussed high-technology.

 

The solder mask is generally assumed as a kind of solder resist.

Its technical features, however, are considerably more impressing. The lacquers have a high density, they are resistant to scratches and have a sparkover voltage up to the range over 100KV/mm. The dielectric characteristics of these substances are frequently ig- nored. On an epoxy basis, they have an eR-value of approx. 4.5 which is a constructive quality regarding EMC requirements. The phototechnical treatment allows a structural resolution with link- widths about 100 µm (figure 11) so that the sensitive spaces of a 400µm-pitch of SMD-ICs may be covered which considerably con- tributes to the prevention of short-circuits.

The limit of the silkscreen is now 1.0 mm for text height-sizes and 180 µm for text line widths. An identification print would otherwise be impossible for many SMD layouts.

Also printable on the PCB is the "peelable solder resist" for protect- ing zones which are not allowed to absorb tin during the soldering process, the "via filling mask" for stabilizing the depression during the in-circuit test and the "carbon conductive lacquer" for the partial conductivity of the PCB's surface-finish. The "solder paste mask" is generally used for SMD-PCBs for applying the solder before the reflow soldering process.

Less known is the print of "resistances" and "capacities" in discrete values directly on the inner layers of multilayer boards.

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The Future of the PCB Within permissible tolerances, component and assembly costs are therefore saved.
The Future of the PCB
Within permissible tolerances, component and assembly costs are
therefore saved. Moreover, additional space is gained on the outer
layers. The techniques are well-tested, however, there are only eco-
nomical in case of larger series.
Figure 11:
Threshold ranges
for the application
of solder mask
Standard
Superfine-line
1.27mm
0.635mm
0.4mm
100ym
50ym
50ym
470ym
235ym
100ym
Solder mask
Testability The electronic test of the PCB without assemblies is now a weak
point in the production process since the image structures have
been reduced to 150µm and even less.
The reason for this is not the continuously repeated discussion, if
and how it is possible to test against Gerber data. This would be
the second step anyway. The dilemma is revealed in the first step,
the mechanical adaptation of the PCB to ensure the contact be-
tween the PCB pads and the testing machine.
The "pin adapter" has been a good solution for a long time. Each
pad is contacted with the tip of a pin which basis is situated within
the test field of the machine.
The test field contains pins in a grid of 1.27 mm. If the distance
from pad to pad on a PCB smaller than 1.27 mm, the pins will have
to be aligned to the adjacent grid point within the test field.
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0.3mm
0.2mm
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The Future of the PCB

 

In

case of a pad distance smaller than 0.8 mm or in case of densely

packed high-performance ICs, the excursion of the pins is so im- mense that the contact between PCB and test field is interrupted. Or, the pins are so dense that they touch and therefore provoke in- correct error-messages.

A

pin adapter for a high-dense PCB is really a little piece of art. The

test time of 1 - 2 seconds is unequalled. The production costs of 1.000 - 3.000,- DM are, however, too high for prototypes and small-

er series, and too much time as well, one or several days, is need- ed for installing the device.

An alternative for the complete and simultaneous test of all con- nection points is the "translator". The adaptation is effected via a foil "translating" between test piece and machine. The foil is elec- trically neutral, it becomes however conductive due the the pres- sure in the Z-axis. Since the pads on the PCB are 20 - 30 µm above the PCB level, the required conductive compaction is partially produced. The con- tact to the testing machine is mechanically established via an inter- mediate adapter. This method is well-tested, good and quick. However, it is too complicated and not economical in case of pro- totypes and smaller series.

An elegant solution would be the "flying-probe" or "finger tester". One or several motor pairs each control a contact pin and place it on the PCB pad. The pads to be tested are activated one after the other and measured against each other or against a fixed ref- erence. The adapter exists only virtually in this system as a software programme, no mechanical installation is required. The time needed for preparations is 1 - 3 hours and fine-pitch compo- nents can be reliably tested. However, a relatively long test time is required: For complex boards 30 minutes or even more may be necessary. And even this system must be correctly aligned if the areas to be tested are below 100 µm because the tolerance of the positioning accuracy will then lead to misleading error messages.

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In order to recognize production errors even in advance, "AOI-test- ers" are increasingly used. These devices compare the image of a PCB or of an inner layer of a multilayer board with a stored refer- ence or with stored data by means of optical record systems. The final product, the complete multilayer board, can therefore not be tested.

The PCB manufacturer has to cope with the deficit that the testing technology is not perfect. However, to be able to offer a sufficient testing in spite of this fact, the strategy of combined tests is used. This may signify that high-density zones are tested by a finger-test- er and zones of lower densities by a pin adapter. It may also be ap- propriate to test dense zones by an automatic device and high- density zones manually and optically by a camera system.

It is not very pleasant if zones which cannot be tested are ignored.

Special PCBs

Representing numerous unspectacular innovations, the efforts in the fields of the sensor and cooling technology should be men- tioned.

There are different possibilities to control the heat development on an active assembly. The heat transfer via a loop of liquids WITHIN the PCB is the general option. In combination with a micro pump, the heat is absorbed by the liquids in the heat-generating zones, trans- ported to cooling zones and carried-off to the ambient air by control- led thermovias.

For measuring and generating defined electromagnetic fields, sen- sor coils on thin laminates are appropriate.The production of these coils and sensors can be realized with considerable smaller toler- ances by means of PCB technologies than by the conventional winding technique. It is also remarkable that PCBs will have quite a different quality in this case. They are not only carriers for component but a compo- nent themselves.

Tolerances

The official (acc. to DIN) tolerance of 100 µm is permissible in the PCB production. The conductive pattern and the solder mask may have this misalignment to the drilling pattern reference.

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Many elementary design-rules are based on this tolerance defini- tion.

"100 µm" do not seem very impressing. In connection with other rules for the qualitative judgement of a PCB, however, the result may be some remarkable restrictions.

Example:

 

"Annular rings of vias". Basically, an annular ring around a via has to be closed and has to be 100 µm at the thinnest section. To en- sure that in case of a misalignment of 100 µm, the annular ring is still 100 µm wide, the annular ring must be defined with 200 µm.

Since the ring is circulatory, the result for a pad to a via is that it has to be 400 µm larger than the via diameter to be drilled (figure 12).

Due to these defaults, there is an inappropriate loss of space for the tracks in case of vias < 0.4 mm. This tolerance must be reduced at least to the half. Therefore, the standards have to be changed from 100 µm to 50 µm and the register accuracy during the produc- tion of PCBs must be improved from 100 µm to 50 µm.

Figure 12:

 
Tolerance 100 µm Tolerance 50 µm Standard Superfine-line Via Via 0.5 - 0.6mm 0.2 -
Tolerance 100 µm
Tolerance 50 µm
Standard
Superfine-line
Via
Via
0.5
- 0.6mm
0.2
- 0.3mm
Pad
Pad
0.9
- 1.0mm
0.4
- 0.5mm
200µm
100µm
100µm
50µm
Fit-tolerances for vias

Tolerances for the annular rings of vias

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The Future of the PCB

 

Second example:

The "pressing of multilayer boards". The tolerance is ± 10 % of the total thickness and does not determine how these 10 % are to be distributed on the laminates and prepregs. According to this defini- tion, a multilayer board with an intended thickness of 1.5 mm will be o.k, if the final thickness is in the range between 1.35 and 1.65. This may be accepted from the mechanical point of view, but there will be considerable restrictions, if impedances are taken into ac- count because the optimum operation range is exceeded from a thickness tolerance of 7 % on. Therefore, the pressing tolerance must not exceed ± 7%.

Filing systems The technical discussions being in the centre of attention usually conceal the requirement regarding strict, reliable, reproducable fil- ing systems in the background.

 

The PCB may NOT follow its way, if the data storage, the documen- tation, the design-rules, the operating instructions, the file-logistics or the multilayer board construction instructions are incorrect. Without any systems, the necessary arrangement and coordina- tion cannot be successful neither between customer and manufac- turer nor within the production process.

Many manufacturers have an archive of 20,000 jobs with approx. 400,000 individual data sets. Each data access has therefore to be unequivocal. There are different possible solutions to create a file system to meet this requirement (figure 13).

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Figure 13: File syntax for CAM / data processing archives

ILF5D044 . MB

syntax for CAM / data processing archives ILF5D044 . MB File name ILF5D044.MB ILF5D044.I2 . Extension
syntax for CAM / data processing archives ILF5D044 . MB File name ILF5D044.MB ILF5D044.I2 . Extension

File name

ILF5D044.MB

ILF5D044.I2

.

Extension

Both files belong to the same layout (solder mask and inner layer). (solder mask and inner layer).

WIE6B124.LS

ABC4H069.LS

The files belong to different layouts, however, they both describe the conductive pattern for the solder side however, they both describe the conductive pattern for the solder side

Extension

Contents

Format

AB

Peelable sold. resist comp. side

Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm Gerber 3.2mm

VB

Via filling mask Silkscreen Solder mask Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Conductive pattern Solder mask

comp. side

DB

comp. side

MB, MBN

comp. side

BS, BSN

comp. side

I2, I2N

inner layer

I3, I3N

inner layer

I4, I4N

inner layer

I5, I5N

inner layer

I6, I6N

inner layer

I7, I7N

inner layer

I8, I8N

inner layer

I9, I9N

inner layer

LS, LSN

solder side

ML, MLN

solder side

DL

Silkscreen

solder side

VL

Via filling mask

solder side

AL

Peelable sold. resist solder side

Z1/Z2

Drilling programme

UM

Outline plan

ZZM

Dimensioned outline plan

DRI/NDK

Drilling programme

In case of multilayer boards, the freedom to combine the material in nearly any desired stack-up has caused a variety of construction types for the design (figure 14). There is no clear registration of these construction types, there are no official rules and hardly pub- lished catalogues. The PCB manufactures are mostly surprised by the speed of this development. However, it is mainly their job to in- form their clients about possibilities and impossibilities regarding the individual case.

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The Future of the PCB Figure 14: Example of a multilayer stack- up Multilayer construction
The Future of the PCB
Figure 14:
Example of a
multilayer stack-
up
Multilayer construction type
8M13FR4I5I25K17K35
mm Material
(0.050 HFPrepreg type :
File
Mounting
106)
(0.060 Prepreg type
(0.100 Prepreg type
: 1080)
: 2125)
0.017
Copper
*.BS
0.060
Prepreg
0.100
Prepreg
0.035
Copper
*.I2(N)
0.050
FR4
A1
0.035
Copper
*.I3(N)
0.050
HFPrepreg
0.017
Copper
*.I4(N)
0.250
FR4
A2
0.017
Copper
*.I5(N)
0.100
Prepreg
B
0.060
Prepreg
0.017
Copper
*.I6(N)
0.250
FR4
A3
0.017
Copper
*.I7(N)
0.100
Prepreg
0.060
Prepreg
0.017
Copper
*.LS
Pressed
1.18 - 1.33
mm
Final thickness
(incl. solder mask)
Tin lead
1.26 - 1.42
1.29 - 1.45
mm
Hot-air
mm
Gold
1.25 -
1.41
mm
Multilayer stack-up plan
Conclusion No. 1 If you have been involved with PCBs for years and if you have wit-
nessed its technological evolution, you are fascinated if you look
back.
Once called simple and being very unpopular as an additional cost
factor within the calculation system of an assembly, the PCB has
made its way.
It does practically not exist anymore as a pure component carrier.
The PCB itself became a component of complex electronics a long
time ago and its technical features cannot be exchanged at will any
longer. The PCB requires and deserves our attention, our sympa-
thy, our understanding and, last but not least, our respect.
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If you nowadays design an electronic circuit without showing this respect towards the PCB, you will act with negligence or, in any case, not very clever.

You will ignore the possibilities resulting due to the numerous vari- eties of the materials, surface-finishes, conductive pattern structur- ings and of the connecting alternatives.

The miniaturization with tracks and vias to 100, 80 or even 50 µm regularly produces speculations: What will come next? - 20 µm? 10 or even 5 µm?

Maybe! I do not guess so.

 

The PCB is not the missing link to the hybrid circuit or to the micro- chip of the 70s. It will always do what has marked its character: to keep together autonomous components as a whole and to create connections.

This will also be the case, when its status as a mechanical-electronic precision component is generally accepted by everyone. This will probably be the last milestone of its evolution.

Afterwards, different things will come with different names.

The question regarding "the future of the PCB" has therefore found several answers.

However, there are obviously still two further questions to be an- swered.

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The first question is:

What is the future of the PCB manufacturer?

 

The PCB manufacturers do not welcome the present technological development with arms wide open. The lean years seem to be over but even the best enterprises did not escape unscathed. The de- mand of the market for variety, quality and short deadlines creates an incredible pressure.

Some manufacturers still guess, others already know: To be in the position to offer all variants of the new PCB, investments will have to be made which seem completely absurd regarding the (almost) empty tills and the moderate profits. It is not only necessary to re- place existing, old machines against new ones which do the same, of course better, quicker and less expensive (figure 15).

This cycle is not new and the PCB manufacturers are quite used to this process. Now it is also necessary to invest in machines which have not been used and which will become necessary IN ADDITION to the other machinery.

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Figure 15:

Machines and investments

 

to be used for

Production technology

 

Superfine-

line

Super-

Standard

microfine-

line

CNC without Z-axis control CNC with Z-axis control

yes

Partially

no

yes

yes

yes

X-ray drilling machine

yes

yes

yes

Film exposure Glass master exposure Laser direct imaging

yes

Partially

no

yes

yes

Partially

yes

yes

yes

Clean-room technology

yes

yes

yes

AOI-tester

yes

yes

yes

Standard multilayer press Process-controlled multilayer press

yes

Partially

no

yes

yes

yes

Standard electroplating Process-controlled electroplating

yes

Partially

no

yes

yes

yes

Etching (alkaline) Etching (acid)

yes

Partially

Partially

yes

yes

yes

Solder mask (screen printing) Solder mask (film/foil)

yes

Partially

no

yes

yes

yes

Pin adapter, resolution 1/10" Pin adapter, resolution 1/20" Electronic test (translator/probe)

yes

no

no

yes

Partially

no

yes

yes

yes

Machines and technology for super-microfine-lines

A simple example is the contour treatment. It is common to mill contours. Now, the scoring of contours is also a variant. The scor- ing maching, however, may not replace the milling machine which, some years ago, replaced the parallel shears. Now, a scoring ma- chine AND a milling machine is necessary. Only then, the custom- ers demand for a combined scoring-milling assembly panel can be satisfied.

Second example: A pin tester is required for the electronic test. But, IN ADDITION; a flying-probe tester is necessary in case of mi- crofine-line PCBs. These examples depend on the investment capacity of an enter- prise.

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The requirements on the galvanotechnical surface-finish variants are totally different. Galvanic baths are very susceptible to rest pe- riods. They cannot be activated or deactivated within a longer pe- riod of time to quickly carry out a gilding or a tinning. If these baths are only rarely used, their balance will be upset. They cannot be used any longer and economical deficits will be the consequence.

If the PCB manufacturer intends to follow the way of the product, there will be only one alternative: Cooperation!

This is very hard for an industry which was able to produce inde- pentently for decades and which procured base materials but nev- er needed considerable industrial services. But that is not all: Many services cannot be obtained neutrally but only by a competitor who was a fierce rival in the fight for customers not long ago. These service enterprises must now be logistically integrated in the inter- nal organization. Many company policies will therefore be turned upside down.

Other companies take another appropriate measure as a result of these changes and start to specialize. They either produce only single-sided or double-sided PCBs, or only multilayer boards or only 6 or 8-layer board or only rigid-flexible circuits or only up to a number of 100 pieces or from 100 pieces on.

This is very economical because the machines are used in the best possible way. It is obvious that a specialist for single-sided PCBs is always less ex- pensive than a company which also produces multilayer boards which require a perfect plating, measuring places and laser direct imaging systems which have to be sufficiently used and correctly maintained and serviced.

Parallel to the investment and specialization concerning machines, the most urgent problem ist the training and further education of the personnel. The technical sequences change, it would be fatal, if the staff did not. The requirements on the CAM data processing are con- siderable. They cannot be fulfilled, if there are no instructions based on generally accepted and respected design-rules.

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Conclusion No. 2 Gently but firmly, the PCB takes along on its way its own manufac- turers and designers. Its sensitivity, differentiation and variety is transferred to the people who have to deal with it and to the enter- prises which are connected to it.

 

The necessity to cooperate, however, offers the chance of a new enterprise culture. The PCB manufacture changes from a product to a project which can be only carried out successfully, if it is based on a partnership.

No, it would definitely not be easier; neither for the PCB manufac- turer, nor for the customers. The current calculations DM*dm2 are now invalid. This kind of specification is too superficial.

Even the wish that PCB types, if single or double-sided, in any quantities, if protoype or series, are available from one manufac- turer cannot be fulfilled any longer on a long term basis. The nec- essary specialization will not allow this anymore.

In many fields, the specialization itself will require new coopera- tions. The series manufacturer has to find an arrangement with the prototype manufacturer because it is appropriate to have the pro- totype data as a basis as these data have been tried and tested in the pre-production. Therefore, a data exchange is necessary. This requires though a clear coordination during the formal transfer and an agreement regarding common design-rules and a common data format. (I will not comment the subject "common data format". Everyone knows that I prefer the "Gerber" format.)

Of course, the PCB will become more expensive. The investments in expensive machinery which can not be fully used because there are too many product variants hardly leave no other choice.

However, there will also be no reduced delivery times. The time saved by technology and rationalization get lost on the way to and from the external service companies.

Regarding these aspects, that's all for the PCB and the manufac- turers. However, one authority is still missing.

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The second addtional question:

"What is the future of the CAD layout designer?"

 

The conflict exists. On its way, the PCB has taken along the lay- outer more than he/she is actually aware of.

Basic decisions, for which there are partially or completely no cur- rent experience values, must be made with every new layout. The combination between mechanics, electronics, EMC, function and costs will be so individual that the original task, the layout, will almost be inferior.

The most important support is surprisingly the component manu- facturer. They have ensured the constant reduction of the pin dis- tances for the last years. However, the escape to MCMs and COB indicates that the development of the mechanical adaptation has come to an end. The bonding of chips on carriers makes the limits obvious. The opposite force of the possible measures are the ap- propriate measures.

Regarding the layout, the problems are concentrated on the selec- tion of the correct material appropriate for the surface-finish, appro- priate for the track-width, appropriate for the vias and appropriate for the multilayer construction type. The freedom of the layouter is determined by the function, on the one hand, and by the costs of the assembly, on the other hand.

The layouter will not be in the position to decide independently. The decisions will depend as well more than ever on the constructive cooperation with the PCB manufacturer and with the assembly pro- ducer and on the internal organization.

The layouter will be in charge of the classification of layouts and of the precise technical specification of the PCB.

The layouter has to adopt the sensitivity of the functional compo- nent "PCB".

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Conclusion No. 3

Paradoxically, the layouter is restricted by the variety of options.

There is finally the material with the correct ε r -value, but it cannot be used because it is too expensive.

There is eventually enough space due to signal lines of 150 µm. But there is also a power supply on the same layer always placed on 70 µm of copper, which now cannot exceed 17 µm.

Now, the optimal multilayer stack-up is available for the layouter with 50 µm-laminates, which offers an excellent broadband decou- pling, however, just his/her supplier is (still) not able to process these laminates.

More?

 

Multilayer boards out of favourable CEM material? It does not work because it is a compound laminate.

 

Bondpads which are tested by the manufacturer by means of pin adapters? It does not work because the surface-finish of the pads will be dam- aged by the adaption.

Tracks with widths of 100 µm in 35 µm copper? It does not work because it cannot be etched.

 

A 10-layer board, 1.8 mm thick with through-vias of 0.1 mm? It does not work because it cannot be reliably plated.

Then, is there at least some help, a training, further education?

This is also not possible, there is none.

 

But that is a completely different story.

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Final word

 

The way the PCB, its manufacturers and its designers will have to go, will be paved with all technical extras. Many of them are neces- sary, progressive and rightly successful.

 

However, the question "how many varieties are actually neces- sary?", is legitimate.

It must be possible to discuss if the faith in an increasing technical complication as the best solution, will sometimes unnoticed turn into a superstition.

Therefore, the miniaturization of the components is generally indi- cated as the cause for the miniaturization of the vias and of the conductive patterns.

That is not completely true!

 

Decisive is, how the connections between the individual compo- nents are made. This task is often completely left to the autorouters of the CAD system.

The machines are certainly quicker than we are, but, I do not be- lieve that they are more intelligent.

It is absolutely important to talk about technolgy.

 

However, do not let us completely ignore the strategies, the ideas and the creativity which - also - distinguishes us as human beings.

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