Design Of Floating Point Multiplier

Dept. of ECE, PESIT Page 1

CONTENTS
TITLE PAGE NO.
1. INTRODUCTION 3
2. FLOATING POINT REPRESENTATION 4
3. FLOATING POINT MULTIPLICATION ALGORITHM 6
4. DESIGN OF FLOATING POINT MULTIPLIER 7
4.1. Sign-bit calculation 7
4.2. Unsigned adder 7
4.3. Bias subtraction 8
4.4. Unsigned multiplier 8
4.5. Normalizer 9
4.6. Overflow/underflow detection 9
5. VHDL CODE 10
6. SIMULATION RESULT 13
7. CONCLUSION 13
8. REFERENCES 14


Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 2
ABSTRATCT
Multiplying floating point numbers is a critical requirement for DSP applications
involving large dynamic range. This seminar focuses only on single precision normalized binary
interchange format targeted for Spartan-3 (SP-3) based on VHDL. It handles overflow and
underflow cases. It handles the overflow and underflow cases. Rounding is not implemented to
give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit.

Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 3

1. INTRODUCTION
Floating point numbers are one possible way of representing real numbers in binary
format, the IEEE 754 standard represents two different floating point formats, Binary
interchange format and Decimal interchange format. Multiplying floating point numbers is a
critical requirement for DSP applications. This seminar focuses only on single precision
normalized binary interchange format.
It consists of a one bit sign (S), an eight bit exponent (E), and a twenty three bit
fraction (M or Mantissa). An extra bit is added to the fraction to form what it called the
Significand. If the exponent is greater than 0 and smaller than 255, and there is 1 in the MSB of
the significand then the number is said to be normalize number.
Multiplying two numbers in floating point format is done by adding the exponent
of the two numbers then subtracting the bias from their result, and multiplying the signiaficand
of the two numbers, and calculating the sign by XORing the sign of the two numbers. Exponent
addition, significand multiplication, and results sign bit calculation are independent and are
done in parallel.
Xilinx ISE Design suite 14.2 & Modelsim 6.3 for VHDL programming and
simulation process.


Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 4
2. Floating Point Representation
Fig 2.1 shows the floating point representation in binary format in single precision
and double precision. But this seminar focuses only on single precision floating point format.

Fig 2.1
The IEEE 754 32-bit single precision floating point number representation is as
show in fig 2.2 below

Fig 2.2 IEEE 754 format representation

So the number -9.5 can be represented as follows,
Design Of Floating Point Multiplier
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The number, in binary, must be normalized. So the integer part must
always be equal to 1. The exponent, an integer value, is not represented in 2s complement, but
as a biased representation i.e. after the addition of bias 127 into the exponent.
Lets suppose a multiplication of 2 floating point numbers A & B, where A= -18.0
and B=9.5, so binary representation of the operands is as follows:
A = -10010.000
B=+1001.1
Normalized representation of the operands:
A=-1.001x2
4


B=+1.0011x2
3

IEEE-754 format representation of the operands:
A=1 10000011 00100000000000000000000
B=0 10000010 00110000000000000000000


Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 6

3. Floating Point Multiplication Algorithm
Following steps are followed to multiply two floating point numbers:
- Multiply the significand of the two numbers.
- Add the exponents of the two numbers.
- From the added exponent result remove the bias 127 (E1+E2-Bias).
- Sign bit is obtained by XOR-ing the MSB of two numbers
- Then normalize the result.
- Check for the underflow/overflow occurrence.
The whole process can be shown as a bock diagram as following fig 3.1


Fig 3.1 Block diagram of floating point multiplier

Design Of Floating Point Multiplier
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4. Design Of Floating Point Multiplier

4.1 Sign Bit Calculation
Multiplying two numbers result is a negative sign if one of the can be obtained
by XOR-ing the sign of two inputs. Fig 4.1 shows the truth table of a sign bit calculator-XOR
gate.

Fig 4.1 Sign bit calculator XOR gate

4.2 Unsigned Adder (For Exponent Addition)

The unsigned adder is responsible for adding the exponent of the first input to the
exponent of the second input and after that subtract the Bias (127) from the addition result (i.e.
A_exponent + B_exponent - Bias). The result of this stage is called as the intermediate exponent.

Fig 4.2 Unsigned Adder
Design Of Floating Point Multiplier
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The ripple carry adder is used to add the two input exponents. A ripple carry adder is a chain of
cascaded full adders and one half adder; each full adder has three inputs (A, B, Ci ) and two
outputs (S,Co). The addition produces an 8-bit sum (S7 to S0) and a carry bit (Co,7). These bits
are concatenated to form a 9-bit addition result (S8 to S0) from which the bias is subtracted. The
bias is subtracted using an array of ripple borrow subtractors.
4.3 Bias Subtraction
Subtract the bias constant (127 = 001111111) from unsigned exponent adder
result for this, two zero subtractors (ZS) and seven one subtractors (OS) are used. S0..S7 is
the unsigned adder result (9 bit). T = 001111111 is the Bias constant. Bias subtractor result is R
= S-T.


Fig 4.3 Bias Subtractor

4.4 Unsigned Multiplier (For Significand Multiplication)
The unit is responsible for multiplying the unsigned significand and placing the
decimal point in the multiplication product. The result of significand multiplication will be called
as the intermediate product (IP).
The unsigned significand multiplication is done on 24 bit. It will result into 48-bit.
From the 48-bit result of the multiplication only the most significant bits are useful, after
normalization (elimination of the most significant 1), we get the 23-bit mantissa of the result.
This normalization can lead to a correction of the result's exponent.
Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 9

4.5 Normalizer

The result of the significand multiplication (Intermediate Product) must be
normalized to have a leading 1 just to the left of the decimal point (i.e. in the bit 46 in the
intermediate product). Since the inputs are normalized numbers then the intermediate product
has the leading one at bit 46 or 47. If the leading one is at bit 46 (i.e. to the left of the decimal
point) then the intermediate product is already a normalized number and no shift is needed. If the
leading one is at bit 47 then the intermediate product is shifted to the right and the exponent is
incremented by 1.

4.6 Overflow/Underflow Detection

Overflow/underflow means that the results exponent is to large or too small to be
represented in the exponent field. The exponent result must be 8 bits in size, and must be
between 1 and 254 otherwise the value is not normalized one.
An overflow may occur while adding the two exponents or during normalization.
Overflow due to exponent addition may be compensated during subtraction of the bias; resulting
in a normal output value (normal operation). An underflow may occur while subtracting the bias
to form intermediate exponent.
If the intermediate exponent < 0 then its an underflow that can never be
compensated; if the intermediate exponent = 0 then its an underflow that may be compensated
during normalization by adding 1 to it. When an overflow occurs an overflow flag signal goes
high and the result turns to infinity (sign determined according to the sign of the inputs). When
an underflow occurs underflow flag goes high and the result turns to Zero (sign determined
according to the sign of the inputs).

Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 10
5. VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity FPMUL is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
z : out STD_LOGIC_VECTOR (31 downto 0));
end FPMUL;
architecture Behavioral of FPMUL is

begin
process(x,y)
variable x_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable x_exp : STD_LOGIC_VECTOR (7 downto 0);
variable x_sign : STD_LOGIC;
variable y_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable y_exp : STD_LOGIC_VECTOR (7 downto 0);
variable y_sign : STD_LOGIC;
variable z_mantissa : STD_LOGIC_VECTOR (22 downto 0);
variable z_exp : STD_LOGIC_VECTOR (7 downto 0);
variable z_sign : STD_LOGIC;
variable int : STD_LOGIC;
variable int2 : STD_LOGIC_VECTOR (47 downto 0);
variable exp_sum : STD_LOGIC_VECTOR (8 downto 0);
begin
x_mantissa := x(22 downto 0);
x_exp := x(30 downto 23);
x_sign := x(31);
y_mantissa := y(22 downto 0);
y_exp := y(30 downto 23);
Design Of Floating Point Multiplier
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y_sign := y(31);
-- inf*0 is not tested (result would be NaN)
if (x_exp = 255 or y_exp = 255) then
-- inf*x or x*inf
z_exp := "11111111";
z_mantissa := (others => '0');
z_sign := x_sign xor y_sign;
elsif (x_exp=0 or y_exp=0) then
-- 0*x or x*0
z_exp := (others => '0');
z_mantissa := (others => '0');
z_sign := '0';
else
int2 := ('1' & x_mantissa) * ('1' & y_mantissa);
-- ar1gs in Q23 result in Q46
if (int2(47)='1') then
-- >=2, shift left and add one to exponent
z_mantissa := int2(46 downto 24) + int2(23); -- with rounding
int := '1';
else
z_mantissa := int2(45 downto 23) + int2(22); -- with rounding
int := '0';
end if;
-- calculate exponent
exp_sum := ('0' & x_exp) + ('0' & y_exp) + int - 127;
if (exp_sum(8)='1') then
if (exp_sum(7)='0') then -- overflow condition
Design Of Floating Point Multiplier
Dept. of ECE, PESIT Page 12
z_exp := "11111111";
z_mantissa := (others => '0');
z_sign := x_sign xor y_sign;
else
z_exp := (others => '0'); -- underflow condition
z_mantissa := (others => '0');
z_sign := '0';
end if;
else
z_exp := exp_sum(7 downto 0); -- normal condition
z_sign := x_sign xor y_sign;
end if;
end if;
z(22 downto 0) <= z_mantissa;
z(30 downto 23) <= z_exp;
z(31) <= z_sign;
end process;
end Behavioral;


Design Of Floating Point Multiplier
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6. Simulation Result


7. Conclusion
This Seminar represents format, design and simulation of a floating point
multiplier that supports the IEEE 754-2008 binary with Xilinx ISE 14.4 and simulation results
tested on ModelSim.

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8. References

[1] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.

[2] B. Fagin and C. Renard, Field Programmable Gate Arrays and FloatingPoint Arithmetic,
IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365367, 1994.

[3] N. Shirazi, A. Walters, and P. Athanas, Quantitative Analysis ofFloating Point Arithmetic
on FPGA Based Custom Computing Machines, Proceedings of the IEEE Symposium on
FPGAs for CustomComputing Machines (FCCM95), pp.155162, 1995.

[4] L. Louca, T. A. Cook, and W. H. Johnson, Implementation of IEEESingle Precision
Floating Point Addition and Multiplication on FPGAs,Proceedings of 83 the IEEE Symposium
on FPGAs for CustomComputing Machines (FCCM96), pp. 107116, 1996.