Translate Schaum

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i \f20 \fs24 \cf0 SCHUM'S{\b0 \fs24 OUTLINE}{\b0 OF }
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\par}{\phpg\posx2781\pvpg\posy1016\absw5813\absh3085 \sl-488 \par\b\i \f20 \fs24
\cf0 \fi37 {\i0 \fs44 DIGITAL}{\i0 \fs44 PRINCIPLES }

\cf0 \fi1590 {\i0 \fs30 Third}{\i0 \fs29 Edition }\par
}
{\phpg\posx3733\pvpg\posy6069\absw3587\absh272 \b \f20 \fs24 \cf0 \b \f20 \fs24
\cf0 ROGER{\fs23 L.}{\fs23 TOKHEIM,} M.S. \par
}
{\phpg\posx2593\pvpg\posy12322\absw5743\absh1330 \b \f20 \fs22 \cf0 \fi1074 \b \
f20 \fs22 \cf0 SCHAUM'S OUTLINE{\fs22 SEiRIES }
\par}{\phpg\posx2593\pvpg\posy12322\absw5743\absh1330 \sl-260 \b \f20 \fs22 \cf0
\fi2142 {\fs19 McGraw-Hill }
{\b0 \fs18 New}{\b0 \fs18 York}{\b0 \fs18
San}{\b0 \fs18 Francisco}{\b0 \
fs18
Washington,}{\b0 \fs19 D.C.}{\b0 \fs18 Auckland}{\b0 \fs18
Bogota
}
\fi318 {\b0 \fs18 Caracas}{\b0 \fs18
Lisbon}{\b0 \fs18
London}{\b0 \fs18
Madrid}{\b0 \fs18
Mexico}{\fs17 City}{\b0 \fs18
Milan }
\fi872 {\b0 \fs18 Montreal}{\b0 \fs18
New}{\b0 \fs18 Delhi}{\b0 \fs18
Sa
n}{\b0 \fs18 Juan}{\b0 \fs18
Singapore }
\fi1692 {\b0 \fs18 Sydney}{\b0 \fs18
Tokyo}{\b0 \fs18
Torontcl }\par
}
{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \f20 \fs18 \cf0 \f20 \fs18 \cf0
ROGER{\b \fs19
L.}{\fs19 TOKHEIM} holds{\b \fs19
B.S.,}{\b \fs19 M.S
.,} and Ed.S. degrees from
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-235 \f20 \fs18 \cf0 St.
Cloud State University and the University{\fs19 of} Wisconsin-Stout. H
e{\fs18 is }
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-238 \f20 \fs18 \cf0 the
author{\fs18 of}{\i \fs19 Digital}{\i \fs19 Electronics} and its companion
{\i \fs19 Activities}{\i \fs19 Manual}{\i \fs19 for }
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-244 \f20 \fs18 \cf0 {\i
\fs19 Digital}{\i \fs19 Electronics,}{\i \fs19 Schaum}{\b \f10 \fs15 's}{\i
\fs19 Outline}{\fs18 of}{\i \fs19 Microprocessor}{\i \fs19 Fundamentals,} an
d
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-229 \f20 \fs18 \cf0 num
erous other instructional materials on science and technology.{\b\i \f10
\fs17 An }
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-246 \f20 \fs18 \cf0 exp
erienced educator at the secondary and college levels, he is presently
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-231 \f20 \fs18 \cf0 an
instructor of Technology Education and Computer Science at Henry
\par}{\phpg\posx2139\pvpg\posy2986\absw7184\absh1719 \sl-235 \f20 \fs18 \cf0 Sib
ley High School, Mendota Heights, Minnesota. \par
}
Schaum's Outline{\fs15 of} Theory and Problems{\b \fs15 of }
\par}{\phpg\posx2161\pvpg\posy5713\absw6783\absh1264 \sl-194 \f20 \fs15 \cf0 DIG
ITAL PRINCIPLES
\par}{\phpg\posx2161\pvpg\posy5713\absw6783\absh1264 \sl-207 \par\f20 \fs15 \cf0
Copyright{\i \f30 \fs16 0}{\fs14 1994,}{\fs14 1988,}{\fs14 1980} by The McG
raw-Hill Companies, Inc. All Rights Reserved. Printed
\par}{\phpg\posx2161\pvpg\posy5713\absw6783\absh1264 \sl-205 \f20 \fs15 \cf0 {\f
s14 in} the United States{\fs14 of} America. Except{\fs14 as} permitted unde
r the Copyright Act{\fs14 of}{\fs14 1976,} no part{\fs14 of }
\par}{\phpg\posx2161\pvpg\posy5713\absw6783\absh1264 \sl-193 \f20 \fs15 \cf0 thi
s publication may be reproduced{\fs14 or} distributed in any form{\fs14 or} b
y any means,{\fs14 or} stored in{\b a} data

\par}{\phpg\posx2161\pvpg\posy5713\absw6783\absh1264 \sl-202 \f20 \fs15 \cf0 bas
e{\fs14 or} retrieval system. without the prior written permission{\fs14 of} t
he publisher. \par
}
{\phpg\posx2173\pvpg\posy7463\absw258\absh162 \f20 \fs14 \cf0 \f20 \fs14 \cf0 7{
\fs14 8 }\par
}
{\phpg\posx2467\pvpg\posy7460\absw3896\absh166 \f20 \fs14 \cf0 \f20 \fs14 \cf0 9
{\fs14 10}{\f10 \fs13 1}{\f10 \fs13 1}{\fs14 12}{\b 13}{\b \f10 \fs13
14}{\fs14 15}{\f10 \fs13 16}{\fs14 17}{\fs14 I8}{\f10 \fs13 19}{\fs14
20}{\b \fs14 BAW}{\b \fs14 BAW}{\fs14 99 }\par
}
\cf0 ISBN{\f30 \fs22 0-07-0b5050-0 }
\par}{\phpg\posx2159\pvpg\posy7712\absw2786\absh929 \sl-195 \par\b \f10 \fs19 \c
f0 {\b0 \f20 \fs15 Sponsoring}{\b0 \f20 \fs15 Editor:}{\b0 \f20 \fs15 John}{\
b0 \f20 \fs15 Aliano }
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\b0 \f20 \fs15 Production}{\b0 \f20 \fs15 Supervisor:}{\b0 \f20 \fs15 Denise}
{\b0 \f20 \fs15 Puryear }
\b0 \f20 \fs15 Editing}{\b0 \f20 \fs15 Supervisor:}{\b0 \f20 \fs15 Patty}{\b0
\f20 \fs15 Andrews }\par
}
\cf0 Library{\fs15 of} Congress Cataloging-in-Publication{\fs15 Data }
\b0 Tokheim,}{\b0 Roger}{\fs15 L. }
\par}{\phpg\posx2167\pvpg\posy9425\absw4944\absh529 \sl-192 \b \f20 \fs15 \cf0 \
fi330 {\b0 Schaum's}{\b0 outline}{\b0 \fs15 of}{\b0 theory}{\b0 and}{\b0
problems}{\b0 of}{\b0 digital}{\b0 prinicples/by }\par
}
Roger{\b \fs15 L.} Tokheim-3rd
\par}{\phpg\posx2341\pvpg\posy10009\absw1707\absh718 \sl-195 \f20 \fs15 \cf0 \fi
314 p.
cm.-(Schaum's
157 Includes index.
158 {\b \fs15 ISBN} 0-07-065050-0 \par
}
ed.
22 outline series) \par
}
{\phpg\posx2333\pvpg\posy10799\absw3341\absh512 \f20 \fs15 \cf0 \fi178 \f20 \fs1
5 \cf0 1.{\fs15 Digital}{\fs15 electronics.}{\b \fs15
I.}{\fs15 'Title.}{
\fs15
11.}{\fs15 Series. }
s15 TK7868.D5T66}{\fs15
1994 }
\par}{\phpg\posx2333\pvpg\posy10799\absw3341\absh512 \sl-201 \f20 \fs15 \cf0 {\b
62}{\b \fs15 1.38}15{\fs15 -dc20 }\par
}
3-64
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02 {\b \fs15 CIP }\par
}
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{\phpg\posx2179\pvpg\posy11787\absw4193\absh517 \b\i \f20 \fs27 \cf0 \b\i \f20 \
fs27 \cf0 McGraw-Hill
0 \fi1242 {\i0 \fs14 A}{\b0\i0 \fs14 Division}{\b0 \f10 \fs13 of}{\b0\i0 \fs15
The}{\fs15 McGraw-HiU}{\b0\i0 \fs14 Companies }\par
}
{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \f20 \fs18 \cf0 \fi410 \f20 \fs
18 \cf0 Digital electronics is a rapidly growing technology. Digital circuits ar
e used in
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-239 \f20 \fs18 \cf0 \f
i45 most new consumer products, industrial equipment and controls, a
nd office,
i49 medical, military, and communications equipment. This expanding use{\
fs19 of} digital
i50 circuits is the result of the development of inexpensive integrated circ
uits and the
i51 application{\fs18 of} display, memory, and computer technology.
i382 {\i \fs19 Schaum's}{\i \fs19 Outline}{\i \fs18 of}{\i \fs19 Digitd}{\i
\fs19 Principles} provides inforrnation necessary to lead
i32 the reader through the solution{\fs19 of} those problems in digital elect
ronics one might
i27 encounter as a student, technician, engineer, or hobbyist. While the pr
inciples{\b \fs19 of }
i32 the subject are necessary, the Schaum's Outline philosophy is dedicated to s
howing
i28 the student how to apply the principles of digital electronics thr
ough practical
i28 solved problems. This new edition now contains over{\fs19 1000} solved an
d supplemen\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-238 \f20 \fs18 \cf0 \f
i24 tary problems.
i382 The third edition{\fs18 of}{\i \fs19 Schaum's}{\i \fs19 Outline}{\i
\fs19 of}{\i \fs19 Digital}{\i \fs19 Principles} contains many{\fs19 of
}
i24 the same topics which made the first two editions great successes. Slig
ht changes
i28 have been made in many{\fs19 of} the traditional topics to reflect the tec
hnological trend
i24 toward using more{\fs19 CMOS,} NMOS, and{\fs19 PMOS} integrated circuit
s. Several micro\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-238 \f20 \fs18 \cf0 \f
i24 processor/microcomputer-related topics have been included, reflecting the
current
i24 practice of teaching a microprocessor course after or with digital
electronics.{\b A }
i24 chapter detailing the characteristics of TTL and CMOS devices along with sev
eral
i24 interfacing topics has been added. Other display technologies such as liquid
-crystal
i21 displays (LCDs) and vacuum fluorescent (VF) displays have been given expan
ded
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-237 \f20 \fs18 \cf0 co
verage. The chapter on microcomputer memory has been revised with adde
d
verage{\fs19 of} hard and optical disks. Sections on programmable logic arra
ys{\b \fs19 (PLA), }
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-238 \f20 \fs18 \cf0 ma
gnitude comparators, demultiplexers, and Schmitt trigger devices have be
en
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-233 \f20 \fs18 \cf0 ad
ded.
i370 The topics outlined in this book were carefully selected to coinc
ide with
urses taught at the upper high school, vocational-Iechnical school, te
chnical
llege, and beginning collcge level. Several{\fs18 of} the most widely used te
xtbooks in
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-239 \f20 \fs18 \cf0 di
gital electronics were analyzed. The topics and problems included
in this
i22 Schaum's Outline reflect those encountered in standard textbooks.
i368 {\i \fs19 Schuiini's}{\i \fs19 Outline}{\i \fs19 of}{\i \fs19 Digital
}{\i \fs19 Principles,} Third Edition, begins with number
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-232 \f20 \fs18 \cf0 sy
stems and digital codes and continues with logic gates and combinational
logic
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-235 \f20 \fs18 \cf0 ci
rcuits.{\fs19 It} then details the characteristics{\fs19 of} both TTL and CMO
S{\fs19 ICs,} along with
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-239 \f20 \fs18 \cf0 va
rious interfacing topics. Next encoders, decoders, and display drivers
are ex\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-244 \f20 \fs18 \cf0 pl
ored, along with LED, LCD, and VF seven-segment displays. Various arithmetic
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-235 \f20 \fs18 \cf0 ci
rcuits are examined. It then covers flip-flops, other rnultivibrators, and seque
ntial
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-232 \f20 \fs18 \cf0 lo
gic, followed by counters and shift registers. Next semiconductor and
bulk
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-237 \f20 \fs18 \cf0 st
orage memories are explored. Finally, niultiplexers, demultiplexers, latches
and
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-235 \f20 \fs18 \cf0 bu
ffers, digital data transmission, magnitude comparators, Schmitt trigger device
s,
d programmable logic arrays are investigated. The book stresses the us
e of
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-235 \f20 \fs18 \cf0 in
dustry-standard digital{\fs19 ICs} (both TTL and CMOS){\fs18 so} that the
reader becomes
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-237 \f20 \fs18 \cf0 fa
miliar with the practical hardware aspects of digital electronics. Most circui
ts in
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-239 \f20 \fs18 \cf0 th
is Schaum's Outline can be wired using standard digital{\fs18 ICs. }
i362 {\b \fs19 I} wish to thank my{\fs19 son} Marshall for his many hour
s of typing, proofreading,
d testing circuits to make this book as accurate as possible. Finally,{\b I} e
xtend{\fs18 my }
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-243 \f20 \fs18 \cf0 ap
preciation to other family members Daniel and Carrie for their help
and
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-227 \f20 \fs18 \cf0 pa
tience.
\par}{\phpg\posx1655\pvpg\posy2091\absw7783\absh11076 \sl-241 \par\f20 \fs18 \cf
0 \fi5078 {\b \fs19 ROGER}L.{\fs19 TOKHEIM }
i3502 {\f10 \fs20 ... }
i3500 {\b \f10 \fs11 111 }\par
}
}
\cf0 Chapter{\i \fs22 1 }\par
}
\cf0 NUMBERS USED IN DIGITAL ELECTRONICS.{\b0 \f10 \fs22 .................... }
\b0 \fs17 1-1}{\b0 \fs17
Introduction}{\b0 \f10 \fs22 ...................
......................... }\par
}
\par}{\phpg\posx2271\pvpg\posy3371\absw274\absh621 \sl-237 \f20 \fs17 \cf0 1-3
\par}{\phpg\posx2271\pvpg\posy3371\absw274\absh621 \sl-237 \f20 \fs17 \cf0 1-4 \
par
}
{\phpg\posx2767\pvpg\posy3302\absw5975\absh698 \f20 \fs17 \cf0 \f20 \fs17 \cf0 B
inaryNumbers{\f10 \fs22 .......................................... }
\par}{\phpg\posx2767\pvpg\posy3302\absw5975\absh698 \sl-237 \f20 \fs17 \cf0 Ikxa
decimal Numbers{\f10 \fs23 ..................................... }
\par}{\phpg\posx2767\pvpg\posy3302\absw5975\absh698 \sl-237 \f20 \fs17 \cf0 {\fs
17 2s} Complement Numbers{\f10 \fs22 .................................... }\par

}
{\phpg\posx9255\pvpg\posy2781\absw220\absh1152 \b \f20 \fs18 \cf0 \fi73 \b \f20
\fs18 \cf0 1
fi86 {\b0 \fs16 1 }
fi86 {\b0 \fs16 1 }
fi80 {\fs17 6 }
\fs17 10 }\par
}
\cf0 Chapter{\fs22 2}
BINARY CODES{\b0 \f10 \fs22 ........................
.................... }\par
}
\par}{\phpg\posx2259\pvpg\posy5049\absw274\absh835 \sl-237 \f20 \fs17 \cf0 2-4 \
par
}
{\phpg\posx2763\pvpg\posy4980\absw5973\absh913 \f20 \fs17 \cf0 \f20 \fs17 \cf0 I
ntroduction{\f10 \fs22 ............................................ }
\par}{\phpg\posx2763\pvpg\posy4980\absw5973\absh913 \sl-234 \f20 \fs17 \cf0 Weig
hted Binary Codes{\f10 \fs22 ..................................... }
\par}{\phpg\posx2763\pvpg\posy4980\absw5973\absh913 \sl-242 \f20 \fs17 \cf0 Nonw
eighted Binary Codes{\f10 \fs22 ................................... }
\par}{\phpg\posx2763\pvpg\posy4980\absw5973\absh913 \sl-237 \f20 \fs17 \cf0 Alph
anumeric Codes{\f10 \fs23 ...................................... }\par
}
\cf0 16
fi26 {\fs17 16 }
fi26 {\b0 \fs17 16 }
\b0 \fs17 20 }
\b0 \fs17 24 }\par
}
BASIC LOGIC GATES{\b0 \f10 \fs22 ....................
.................... }\par
}
-1
\par
}
Introduction{\f10 \fs22 ............................................ }
\par}{\phpg\posx2763\pvpg\posy6915\absw5967\absh1327 \sl-238 \f20 \fs17 \cf0 The
ANDGate{\f10 \fs22 .......................................... }

ORGate{\f10 \fs22 ........................................... }
NOTGate{\f10 \fs22 .......................................... }
\par}{\phpg\posx2763\pvpg\posy6915\absw5967\absh1327 \sl-235 \f20 \fs17 \cf0 Com
bining Logic Gates{\f10 \fs22 ..................................... }
\par}{\phpg\posx2763\pvpg\posy6915\absw5967\absh1327 \sl-236 \f20 \fs17 \cf0 Usi
ng Practical Logic Gates{\f10 \fs22 .................................. }\par
}
\cf0 28
fi28 {\b0 \f20 \fs17 28 }
\b0 \f20 \fs17 28 }
\b0 \f20 \fs17 31 }
\b0 \f20 \fs17 34 }
\b0 \f20 \fs17 36 }
\b0 \f20 \fs17 39 }\par
}
\cf0 Chapter{\i \f10 \fs21 4 }\par
}
\cf0 OTHER LOGIC GATES{\b0 \f10 \fs23 ....................................... }
\b0 \fs17 4-}{\b0 \fs17 1}{\b0 \fs17
Introduction}{\b0 \f10 \fs23 .......
..................................... }\par
}
-2
\par
}
The NAND Gate{\f10 \fs23 ......................................... }
NOR Gate{\f10 \fs22 .......................................... }
Exclusive-OR Gate{\f10 \fs22 ..................................... }
Exclusive-NORGate{\f10 \fs22 ................................... }
\par}{\phpg\posx2761\pvpg\posy9536\absw5979\absh1555 \sl-231 \f20 \fs17 \cf0 Con
verting Gates When Using Inverters{\f10 \fs23 .......................... }
\par}{\phpg\posx2761\pvpg\posy9536\absw5979\absh1555 \sl-244 \f20 \fs17 \cf0 NAN
D as a Universal Gate{\f10 \fs23 .................................. }
ng Practical Logic Gates{\f10 \fs22 .................................. }\par
}
\cf0 48
\b0 \fs17 48 }
\b0 \fs17 48 }
\b0 \fs17 50 }
\b0 \fs17 52 }
\b0 \fs17 54 }
\b0 \fs17 55 }
\b0 \fs17 58 }
\b0 \fs17 60 }\par
}
\cf0 Chapter{\f30 \fs23 5}
SIMPLIFYING LOGIC CIRCUITS: MAPPING{\b0 \f10 \f
s23 ...................... }\par
}
5-1
\f10 \fs16 5-4 }
\par
}
Introduction{\f10 \fs23 ............................................ }
\par}{\phpg\posx2755\pvpg\posy12170\absw5966\absh2009 \sl-229 \f20 \fs17 \cf0 Su
m-of-Products Boolean Expressions{\f10 \fs22 ........................... }
\par}{\phpg\posx2755\pvpg\posy12170\absw5966\absh2009 \sl-237 \f20 \fs17 \cf0 Pr
oduct-of-Sums Boolean Expressions{\f10 \fs22 ........................... }
\par}{\phpg\posx2755\pvpg\posy12170\absw5966\absh2009 \sl-245 \f20 \fs17 \cf0 Us
ing De Morgan'sTheorems{\f10 \fs23 ................................. }
ing NAND Logic{\f10 \fs23 ....................................... }
ins NOR Logic{\f10 \fs22 ........................................ }
\par}{\phpg\posx2755\pvpg\posy12170\absw5966\absh2009 \sl-231 \f20 \fs17 \cf0 Ka
rnaugh Maps{\f10 \fs23 .......................................... }
\par}{\phpg\posx2755\pvpg\posy12170\absw5966\absh2009 \sl-236 \f20 \fs17 \cf0 Ka
rnaugh Maps with Four Variables{\f10 \fs23 ............................ }
0 \fi2460 {\b \fs11 V }\par
}
\cf0 69

{\b0 \fs17 69 }
{\b0 \fs17 69 }
\fi22 {\b0 \fs17 72 }
\fi22 {\b0 \fs17 75 }
\fi22 {\b0 \fs17 77 }
\fi22 {\b0 \fs17 79 }
\fi22 {\b0 \fs17 82 }
\fi23 {\b0 \fs17 85 }\par
}
{\phpg\posx899\pvpg\posy567\absw175\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 vi \
par
}
{\phpg\posx4855\pvpg\posy597\absw1030\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 CO
NTENTS \par
}
{\phpg\posx2315\pvpg\posy1433\absw274\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 59 \par
}
{\phpg\posx2825\pvpg\posy1371\absw5963\absh263 \f20 \fs17 \cf0 \f20 \fs17 \cf0 U
sing Maps{\fs16 with} Maxterm Expressions{\f10 \fs22 ..........................
. }\par
}
-10{\fs17
Don't}{\fs17 Cares}{\fs17 on}{\fs17 Karnaugh}{\fs17 Maps}{\f1
0 \fs22 ............................... }
{\fs17
Karnaugh}{\fs17 Maps}{\fs17 with}{\fs17 Five.Variables}{\f10 \fs2
2 ............................. }\par
}
\par}{\phpg\posx9313\pvpg\posy1435\absw212\absh624 \sl-255 \f20 \fs17 \cf0 {\fs1
6 91 }
6 93 }\par
}
\cf0 Chapter{\i \fs22 6}
'ITL AND CMOS ICS: CHARACTERISTICSAND INTERFACING{
\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \
f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .} 104 \par
}
-1
16 6-8 }\par
}
Introduction{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \f
s21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21
.}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f
10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \f
.}{\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2825\pvpg\posy3075\absw6194\absh1307 \sl-237 \f20 \fs17 \cf0 Dig
ital IC Terms{\f10 \fs22 ......................................... }
\par}{\phpg\posx2825\pvpg\posy3075\absw6194\absh1307 \sl-237 \f20 \fs17 \cf0 TTL
Integrated Circuits{\f10 \fs22 ..................................... }
\par}{\phpg\posx2825\pvpg\posy3075\absw6194\absh1307 \sl-232 \f20 \fs17 \cf0 CMO
S Integrated Circuits{\f10 \fs22 ................................... }
\par}{\phpg\posx2825\pvpg\posy3075\absw6194\absh1307 \sl-232 \f20 \fs17 \cf0 Int
erfacing TTL{\fs16 and} CMOS ICs{\f10 \fs22 ............................... }
\par}{\phpg\posx2825\pvpg\posy3075\absw6194\absh1307 \sl-227 \f20 \fs17 \cf0 Int
erfacing TTL and CMOS{\fs16 with} Switches{\f10 \fs22 ........................
. }\par
}
04
\par}{\phpg\posx9233\pvpg\posy3133\absw316\absh1242 \sl-237 \f20 \fs16 \cf0 105
\par
}
nterfacing TTL/CMOS with Simple Output Devices{\f10 \fs22 .}{\f10 \fs22 .}{\f
.}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\fs16
129 }
D/A} and A/D Conversion{\f10 \fs22 ..................................}
131 \par
}
CODE CONVERSION{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}
{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0
\f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f1
0 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \f
s21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21
.}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{
\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0
\fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs
21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21 .}{\b0 \f10 \fs21
. }\par
}
-1

\par
}
Introduction.{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \
fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22
.}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\
f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \
.}{\f10 \fs22 . }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-245 \f20 \fs17 \cf0 Enc
oding{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}
{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10
\fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs2
1 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}
\fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-222 \f20 \fs17 \cf0 Dec
oding: BCD to Decimal{\f10 \fs22 .................................. }
oding: BCD-to-Seven-SegmentCode{\f10 \fs22 .......................... }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-260 \f20 \fs17 \cf0 Liq
uid-Crystal Displays{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}
{\f10 \fs21 . }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-230 \f20 \fs17 \cf0 Dri
ving LCDs{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22
.}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{
\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10
\f10 \fs22 . }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-243 \f20 \fs17 \cf0 Vac
uum Fluorescent Displays{\f10 \fs22 ................................. }
\par}{\phpg\posx2833\pvpg\posy5941\absw6176\absh1749 \sl-228 \f20 \fs17 \cf0 Dri
ving VF Displays{\fs16 with} CMOS{\f10 \fs22 ............................... }
\par
}
\cf0 140
fi28 {\b0 \fs16 140 }
fi28 {\b0 \fs16 140 }

fi28 {\b0 \fs16 143 }
fi34 {\b0 \fs16 147 }
fi34 {\b0 \fs16 152 }
fi36 {\b0 \fs16 154 }
fi28 {\b0 \fs17 158 }
fi34 {\b0 \fs16 161 }\par
}
\cf0 Chapter{\i \fs22 8}
BINARYARITHMETIC AND ARITHMETIC CIRCUITS{\b0 \f10
\fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs2
2 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .
}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b
0 \f10 \fs22 .}{\b0 \f10 \fs22 .} 170 \par
}
-1
17 8-5 }
16 8-6 }
\par
}
Introduction{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \f
.}{\f10 \fs22 .}{\f10 \fs22 . }
\par}{\phpg\posx2827\pvpg\posy8811\absw6196\absh1531 \sl-236 \f20 \fs17 \cf0 Bin
ary Addition{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs
22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .
}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f1
0 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs
}
\par}{\phpg\posx2827\pvpg\posy8811\absw6196\absh1531 \sl-240 \f20 \fs17 \cf0 Bin
ary Subtraction{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10
\fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2827\pvpg\posy8811\absw6196\absh1531 \sl-227 \f20 \fs17 \cf0 Par
allel Adders and Subtractors{\f10 \fs22 ............................... }
ng Full Adders{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10
\fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }
ng Adders for Subtraction{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs
0 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 . }
s16 2s} Complement Addition and Subtraction{\f10 \fs22 ......................
... }\par
}
70
17 180 }
\par
}
\cf0 Chapter{\i \f10 \fs20 9 }\par
}
\cf0 FLIP-FLOPS AND OTHER MULTMBRATORS{\b0 \f10 \fs22 ..................... }\
par
}
9-1
s16 9-2 }
s16 9-3 }
s16 9-4 }
s16 9-5 }
s17 9-6 }
s16 9-7 }
s16 9-8 }\par
}

7 \cf0 Introduction{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{
\fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2813\pvpg\posy11443\absw6239\absh1745 \sl-244 \f20 \fs17 \cf0 RS
Flip.Flop{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22
\f10 \fs22 .}{\f10 \fs22 . }
i22 Clocked{\b\i RS} Flip.Flop{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\
f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2813\pvpg\posy11443\absw6239\absh1745 \sl-234 \f20 \fs17 \cf0 DF
lip-Flop{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21
\f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2813\pvpg\posy11443\absw6239\absh1745 \sl-234 \f20 \fs17 \cf0 JK
FliP.FlOP{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22
\f10 \fs22 .}{\f10 \fs22 . }
\par}{\phpg\posx2813\pvpg\posy11443\absw6239\absh1745 \sl-237 \f20 \fs17 \cf0 Tr
iggering{\b \fs16 of} Flip.Flops{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\
f10 \fs21 .}{\f10 \fs21 . }
\par}{\phpg\posx2813\pvpg\posy11443\absw6239\absh1745 \sl-220 \f20 \fs17 \cf0 As
table Multivibrators-Clocks{\f10 \fs22 .}{\f10 \fs22 .}{\f10 \fs22 .}{\f10
\f10 \fs22 .}{\f10 \fs22 . }
i26 Monostable Multivibrators{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10
{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 .}{\f10 \fs21 . }\par
}
\cf0 204
\fi27 {\b0 \fs16 204 }
\fi27 {\b0 \fs16 204 }
\fi30 {\b0 \fs16 206 }
\fi27 {\b0 \fs16 209 }
\fi27 {\b0 \fs16 212 }
\fi27 {\b0 \fs16 217 }
\fi27 {\b0 \fs16 220 }
\fi30 {\b0 \fs16 224 }\par
}
NTENTS \par
}
{\phpg\posx9397\pvpg\posy535\absw222\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 vii
\par
}
\cf0 Chapter{\i \fs22 10} COUNTERS{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0
.}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\
b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \
f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 . }
\fi1202 {\b0 \fs17 10-1}{\b0 \fs17
Introduction}{\b0 \f10 \fs22 ...........
................................. }
\fi1201 {\b0 \fs17 10-2}{\b0 \fs17
Ripplecounters}{\b0 \f10 \fs22 ........
.................................. }
\fi1207 {\b0 \fs17 10-3}{\b0 \fs17
Parallel}{\b0 \fs17 Counters}{\b0 \f10 \
fs23 ......................................... }
\fi1207 {\b0 \fs17 10-4}{\b0 \fs17
Other}{\b0 \fs17 Counters}{\b0 \f10 \fs2
2 .......................................... }
\fi1201 {\b0 \fs17 10-5}{\b0 \fs17
TTL}{\b0 \fs17 IC}{\b0 \fs17 Counters}{
\b0 \f10 \fs22 ......................................... }
\fi1202 {\b0 \fs17 10-6}{\b0 \fs17
CMOS}{\b0 \fs17 IC}{\b0 \fs17 Counters}
{\b0 \f10 \fs22 ....................................... }
\fi1201 {\b0 \fs17 10-7}{\b0 \fs17
Frequency}{\b0 \fs17 Division:}{\b0 \fs
17 The}{\b0 \fs17 Digital}{\b0 \fs17 Clock}{\b0 \f10 \fs22 .................
.......... }\par
}
\cf0 230
fi27 {\b0 \fs17 230 }
fi27 {\b0 \fs17 230 }
fi27 {\b0 \fs17 234 }
fi27 {\b0 \fs17 236 }
fi26 {\b0 \fs17 240 }
fi27 {\b0 \fs17 245 }
fi26 {\b0 \fs17 251 }\par
}
\cf0 Chapter{\i \f30 \fs23 11} SHIm REGISTERS{\b0 \f10 \fs22 ...............
........................... }
\fi1204 {\b0 \fs17 11-1}{\b0 \fs17
Introduction}{\b0 \f10 \fs23 ............
................................ }
\fi1203 {\b0 \fs17 11-2}{\b0 \fs17
Serial-Load}{\b0 \fs17 Shift}{\b0 \fs17
Register}{\b0 \f10 \fs22 ................................... }
\fi1203 {\b0 \fs17 11-3}{\b0 \fs17
Parallel-Load}{\b0 \fs17 Shift}{\b0 \fs1
7 Register}{\b0 \f10 \fs22 .................................. }
\fi1198 {\b0 \fs17 11-4}{\b0 \fs17
TTL}{\b0 \fs17 Shift}{\b0 \fs17 Registe
rs}{\b0 \f10 \fs22 ........................................ }
\fi1203 {\b0 \fs17 11-5}{\b0 \fs17
CMOS}{\b0 \fs17 Shift}{\b0 \fs17 Regist
ers}{\b0 \f10 \fs23 .}{\b0 \f10 \fs23 .}{\b0 \f10 \fs23 .}{\b0 \f10 \fs23 .}{
f10 \fs23 .}{\b0 \f10 \fs23 .}{\b0 \f10 \fs23 .}{\b0 \f10 \fs23 .}{\b0 \f10
3 . }\par
}
\cf0 260
fi35 {\b0 \fs17 260 }
fi35 {\b0 \fs17 261 }
fi33 {\b0 \fs17 264 }
fi35 {\b0 \fs17 268 }
fi33 {\b0 \fs17 271 }\par
}
\cf0 Chapter{\i \f10 \fs20 12} MICROCOMPUTERMEMORY{\b0 \f10 \fs22 ..........
....................... }
\fi1197 {\b0 \fs17 12-1}{\b0 \fs17
Introduction}{\b0 \f10 \fs22 ...........
................................. }
\fi1197 {\b0 \fs17 12-2}{\b0 \fs17
Random-Access}{\b0 \fs17 Memory}{\b0 \fs
17 (RAM)}{\b0 \f10 \fs22 ............................... }
\fi1198 {\b0 \fs17 12-3}{\b0 \fs17
Read-Only}{\b0 \fs17 Memory}{\b0 \fs17
(ROM)}{\b0 \f10 \fs22 .................................. }
\fi1198 {\b0 \fs17 12-4}{\b0 \fs17
Programmable}{\b0 \fs17 Read-Only}{\b0 \
fs17 Memory}{\b0 \f10 \fs22 ............................. }
\fi1197 {\b0 \fs17 12-5}{\b0 \fs17
Microcomputer}{\b0 \fs17 Bulk}{\b0 \fs1
7 Storage}{\b0 \f10 \fs23 ................................. }\par
}
\cf0 279
fi35 {\b0 \fs17 279 }
fi33 {\b0 \fs17 280 }
fi33 {\b0 \fs17 286 }
fi35 {\b0 \fs17 293 }
fi33 {\b0 \fs17 300 }\par
}
\cf0 Chapter{\i \fs21 13} OTHER DEVICES AND TECHNIQUES{\b0 \f10 \fs22 .....
...................... }
\fi1197 {\b0 \fs17 13-}{\fs17 1}{\b0 \fs17
Introduction}{\b0 \f10 \fs22 ..
.......................................... }
\fi1196 {\b0 \fs17 13-2}{\b0 \fs17
Data}{\b0 \fs17 Selector/Multiplexers}{\
b0 \f10 \fs23 .................................. }
\fi1196 {\b0 \fs17 13-3}{\b0 \fs17
Multiplexing}{\b0 \fs17 Displays}{\b0 \f
10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \
fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22
.}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}
{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0
\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 . }
\fi1196 {\b0 \fs17 13-4}{\b0 \fs17
Demultiplexers}{\b0 \f10 \fs22 ........
.................................. }
\fi1196 {\b0 \fs17 13-5}{\b0 \fs17
Latches}{\b0 \fs17 and}{\b0 \fs17 Three
-State}{\b0 \fs17 Buffers}{\b0 \f10 \fs23 ............................... }
\fi1197 {\b0 \fs17 13-6}{\b0 \fs17
Digital}{\b0 \fs17 Data}{\b0 \fs17 Tran
smission}{\b0 \f10 \fs22 ................................... }
\fi1196 {\b0 \fs17 13-7}{\b0 \fs17
Programmable}{\b0 \fs17 Logic}{\b0 \fs1
7 Arrays}{\b0 \f10 \fs23 .................................. }\par
}
3-8
17 13-9 }\par
}
Magnitude Comparator{\f10 \fs23 ..................................... }
\par}{\phpg\posx2711\pvpg\posy10310\absw5971\absh479 \sl-234 \f20 \fs17 \cf0 Sch
mitt Trigger Devices{\f10 \fs22 ..................................... }\par
}
\cf0 309
fi35 {\b0 \fs17 309 }
fi33 {\b0 \fs17 309 }
fi33 {\b0 \fs17 313 }
fi35 {\b0 \fs17 316 }
fi35 {\b0 \fs17 319 }
fi35 {\b0 \fs17 324 }
fi35 {\b0 \fs17 326 }
fi33 {\b0 \fs17 335 }
fi30 {\fs17 341 }\par
}
\cf0 INDEX{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \f
f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10
2 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .}{\b0 \f10 \fs22 .
}{\b0 \f10 \fs22 . }\par
}
47 \par
}
}
5 \cf0 Chapter{\fs54 1 }
{\b \fs33 Numbers}{\b \fs33 Used}{\b \fs33 in}{\b \fs33 Digital}{\b \fs33 El
ectronics }\par
}
\cf0 1-1{\fs19
INTRODUCTION }
fi355 {\b0 \fs19 The}{\b0 \fs19 decimal}{\b0 \fs19 number}{\b0 \fs19 system}{
\b0 \fs19 is}{\b0 \fs19 familiar}{\b0 \fs19 to}{\b0 \fs19 everyone.}{\b0 \fs
19 This}{\b0 \fs19 system}{\b0 \fs19 uses}{\b0 \fs19 the}{\b0 \fs19 symbols
}{\b0 \fs19 0,}{\b0 \fs19 1,}{\b0 \fs19 2,}{\b0 \fs19 3,} 4,{\b0 \fs19 5,}{
\b0 6, }
\b0 \fs19 7,}{\b0 \fs19 8,}{\b0 \fs19 and}{\b0 \fs19 9.}{\b0 \fs19 The}{\b0
\fs19 decimal}{\b0 \fs19 system}{\b0 \fs19 also}{\b0 \fs19 has}{\b0 \fs19
a}{\b0 \fs19 place-value}{\b0 \fs19 characteristic.}{\b0 \fs19 Consider
}{\b0 \fs19 the}{\b0 \fs19 decimal}{\b0 \fs19 number }
\b0 238.}{\b0 \fs19 The}{\b0 \fs19 8}{\b0 \fs19 is}{\b0 \fs19 in}{\b0 \fs19
the}{\b0 \fs18 1s}{\b0 \fs19 position}{\b0 \fs19 or}{\b0 \fs19 place.}{\b0
\fs19 The}{\b0 3}{\b0 \fs19 is}{\b0 \fs19 in}{\b0 \fs19 the}{\b0 \fs19 10s
}{\b0 \fs19 position,}{\b0 \fs19 and}{\b0 \fs19 therefore}{\b0 \fs19 the}{\b
0 \fs19 three}{\b0 \fs19 10s}{\b0 \fs19 stand }
\b0 \fs19 for}{\b0 30}{\b0 \fs19 units.}{\b0 \fs19 The}{\b0 2}{\b0 \fs19 is
}{\b0 \fs19 in}{\b0 \fs19 the}{\b0 100s}{\b0 \fs19 position}{\b0 \fs19 and}{
\b0 \fs19 means}{\b0 \fs19 two}{\b0 \fs19 loos,}{\b0 \fs19 or}{\b0 \fs19 2,
OO}{\b0 \fs19 units.}{\b0 \fs19 Adding}{\b0 \fs19 200}{\b0 \f10 \fs29 +}{\b0
\fs19 30}{\b0 \f10 \fs29 +}{\b0 \fs19 8}{\b0 \fs19 gives }
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\b0 \fs19 mal}{\b0 \fs19 (base}{\b0 16)}{\b0 \fs19 and}{\b0 \fs19 octal}{
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}
\cf0 1-2 BINARY NUMBERS
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fi362 {\b0 \fs19 Counting}{\b0 \fs19 in}{\b0 \fs19 binary}{\b0 \fs19 is}{\
b0 \fs19 illustrated}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 1-1.}{\b0 \fs19
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its }
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hat}{\b0 2}{\b0 \fs19 is}{\b0 \fs19 added}{\b0 \fs19 to}{\b0 \fs19 the}{\
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\b0 \fs19 Three}{\b0 \fs19 other}{\b0 \fs19 binary}{\b0 \fs19 place}{\b0 \fs
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16s}{\b0 \fs19 places).}{\b0 \fs19 Note}{\b0 \fs19 that}{\b0 \fs19 each
}
\b0 \fs19 larger}{\b0 \fs19 place}{\b0 \fs19 value}{\b0 \fs19 is}{\b0 \fs19
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19 place}{\b0 22,}{\b0 \fs19 the }
\b0 \fs19 8s}{\b0 \fs19 place}{\fs19 23,}{\b0 \fs19 and}{\b0 \fs19 the}{\b0
16s}{\b0 \fs19 place}{\fs27 z4.}{\b0 \fs19 It}{\b0 \fs19 is}{\b0 \fs19 cus
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}{\b0 \fs19 memorize}{\b0 \fs19 at}{\b0 \fs19 least}{\b0 \fs19 the}{\b0 \fs1
9 binary }
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s19 one,}{\b0 \fs19 one)}{\b0 \fs19 or}{\b0 \fs19 decimal}{\b0 \fs19 15. }
fi362 {\b0 \fs19 Consider}{\b0 \fs19 the}{\b0 \fs19 number}{\b0 \fs19 shown}
{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 1-2a.}{\b0 \fs19 This}{\b0 \fs19 figure
}{\b0 \fs19 shows}{\b0 \fs19 how}{\b0 \fs19 to}{\b0 \fs19 convert}{\b0 \fs19
the}{\b0 \fs19 binary}{\b0 10011}{\b0 \fs19 (say: }
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}{\b0 \fs19 the }
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s19 then}{\b0 \fs19 equals}{\b0 \fs19 a}{\b0 \fs19 decimal}{\b0 19. }
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}{\b0 \fs19 the}{\b0 \fs19 same}{\b0 \fs19 procedure,}{\b0 \fs19 each}{\
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decimal}{\b0 \fs19 point}{\b0 \fs19 in}{\b0 \fs19 decimal }
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b0 \fs19 when}{\b0 \fs19 working}{\b0 \fs19 with}{\b0 \fs19 whole}{\b0 \fs19
binary}{\b0 \fs19 numbers. }
fi362 {\b0 \fs19 What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 value}{\b0 \fs1
9 of}{\b0 \fs19 the}{\b0 \fs19 number}{\b0 111?}{\b0 \fs19 It}{\b0 \fs19 c
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nd}{\b0\i \f10 \fs17 b. }
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}
{\phpg\posx841\pvpg\posy13718\absw3954\absh404 \f20 \fs19 \cf0 \f20 \fs19 \cf0 n
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6 \fs18 2}{\f10 \fs29 +}{\dn006 \fs18 0.5}{\f10 \fs28 + }\par
}
0.125{\f10 \fs14 =} 14.625{\fs19 in}{\fs19 decimal. }
701 {\fs19 I }\par
}
{\phpg\posx851\pvpg\posy543\absw146\absh217 \b \f20 \fs19 \cf0 \b \f20 \fs19 \cf
0 2 \par
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{\phpg\posx3271\pvpg\posy553\absw4000\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 NU
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{\phpg\posx8889\pvpg\posy545\absw830\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 [CH
AP. 1 \par
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{\phpg\posx3927\pvpg\posy1625\absw633\absh5148 \f20 \fs17 \cf0 \f20 \fs17 \cf0 D
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9 count
\fi315 {\fs17 0 }
31 1
17 2
23 {\f10 \fs16 3 }
15 4
23 5
17 6
21 {\f10 \fs16 7 }
21 {\b \fs16 8 }
17 {\fs16 9 }
45 10
45 11
45 12
49 13
45 14
45 15
43 16
45 17
45 18
49 19 \par
}
7 \cf0 Binary count
16s{\fs17
8s}
4s
2s
1s
\fi1533 {\fs16 0 }
1557 {\b \f10 \fs15 1 }\par
}
\cf0 1
1 1
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1 1
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1 1
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\cf0 1
2 1
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1 1
5 1
\par}{\phpg\posx5770\pvpg\posy3265\absw136\absh3670
1 1
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16 0 }
17 0 }\par
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5 {\fs17 1 }
4 {\fs17 0 }
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2 {\fs17 1 }
4 {\fs17 1 }
3 {\fs17 0 }
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3 {\fs17 1 }
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3 {\fs17 0 }
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\cf0 0
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\sl-256 \f20 \fs17 \cf0 {\fs
\sl-260 \f20 \fs17 \cf0 0
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\sl-257 \f20 \fs17 \cf0 {\fs
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6 {\fs17 0 }
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6 {\fs17 0 }
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{\phpg\posx4043\pvpg\posy8929\absw325\absh1324 \b\i \f20 \fs17 \cf0 \fi44 \b\i \
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{\phpg\posx4941\pvpg\posy8989\absw184\absh123 \b \f20 \fs10 \cf0 \b \f20 \fs10 \
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{\phpg\posx1523\pvpg\posy9244\absw91\absh102 \b \f10 \fs8 \cf0 \b \f10 \fs8 \cf0
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{\phpg\posx1675\pvpg\posy8985\absw928\absh1270 \f20 \fs17 \cf0 \f20 \fs17 \cf0 P
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{\phpg\posx4941\pvpg\posy9429\absw193\absh570 \f20 \fs16 \cf0 \f20 \fs16 \cf0 8s
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\par}{\phpg\posx5791\pvpg\posy9437\absw210\absh567 \sl-214 \par\f10 \fs15 \cf0 \
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{\phpg\posx4309\pvpg\posy10494\absw186\absh106 \i \f10 \fs9 \cf0 \i \f10 \fs9 \c
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{\phpg\posx4927\pvpg\posy11057\absw188\absh118 \b\i \f20 \fs10 \cf0 \b\i \f20 \f
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1
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{\phpg\posx7887\pvpg\posy9215\absw73\absh118 \f10 \fs10 \cf0 \f10 \fs10 \cf0 > \
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{\phpg\posx7012\pvpg\posy10196\absw128\absh184 \f20 \fs16 \cf0 \f20 \fs16 \cf0 +
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fi43 {\f10 \fs15 1 }\par
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{\phpg\posx7893\pvpg\posy9653\absw873\absh419 \f10 \fs35 \cf0 \f10 \fs35 \cf0 .{
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9 \par
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cf0 point \par
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{\phpg\posx7732\pvpg\posy10201\absw110\absh177 \f10 \fs15 \cf0 \f10 \fs15 \cf0 =
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Powers{\fs16 of}{\fs17 2 }
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\fs16 \cf0 24
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\fi23 {\b0 \f10 \fs27 + }\par
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s
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{\phpg\posx7411\pvpg\posy11051\absw174\absh932 \i \f20 \fs11 \cf0 \fi23 \i \f20
\fs11 \cf0 20
\par}{\phpg\posx7411\pvpg\posy11051\absw174\absh932 \sl-202 \par\i \f20 \fs11 \c
f0 {\i0 \fs15 Is }
f0 {\b\i0 \fs16 0 }\par
}
\cf0 -Binary
\par}{\phpg\posx7799\pvpg\posy11877\absw866\absh453 \sl-294 \f20 \fs17 \cf0 {\f1
0 \fs14 =}{\fs16
46 }\par
}
{\phpg\posx9003\pvpg\posy11877\absw431\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 p
oint \par
}
{\phpg\posx2515\pvpg\posy12454\absw5857\absh1111 \b\i \f10 \fs14 \cf0 \fi1779 \b
\i \f10 \fs14 \cf0 (h){\b0\i0 \f20 \fs15 Binary-to-decimal}{\b0\i0 \f20 \fs15
conversion }
\par}{\phpg\posx2515\pvpg\posy12454\absw5857\absh1111 \sl-356 \b\i \f10 \fs14 \c
f0 \fi1547 {\i0 \f30 \fs18 lOollz}{\b0\i0 \fs13 ==}{\i0 \fs14 1910}{\b0\i0 \
f20 \fs16
101}{\i0 \fs15 1}{\i0 \fs15 1}{\i0 \fs15 0}{\i0 \fs15
2}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs17 4610 }
4 \cf0 {\f20 \fs13 (}{\f20 \fs13 c}{\f20 \fs13 )}{\b0\i0 \f20 \fs15 Summary}{
\b0\i0 \f20 \fs15 of}{\b0\i0 \f20 \fs15 conversions}{\b0\i0 \f20 \fs15 and}{\
b0\i0 \f20 \fs15 use}{\b0\i0 \f20 \fs15 of}{\b0\i0 \f20 \fs15 small}{\b0\i0
\f20 \fs15 subscripts}{\b0\i0 \f20 \fs15 to}{\b0\i0 \f20 \fs15 indicate}{\b0
\i0 \f20 \fs15 radix}{\b0\i0 \f20 \fs14 of}{\b0\i0 \f20 \fs15 number }
4 \cf0 \fi2436 {\i0 \f20 \fs17 Fig.}{\i0 \fs15 1-2 }\par
}
0 CHAP.{\b0 \fs17 11 }\par
}
MBERS USED{\fs17 IN}{\fs17 DIGITAL} ELECTRONICS \par
}
{\phpg\posx9587\pvpg\posy534\absw146\absh221 \b \f20 \fs19 \cf0 \b \f20 \fs19 \c
f0 3 \par
}
\par
}
\par
}
{\phpg\posx1563\pvpg\posy1549\absw917\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Po
wers of2 \par
}
\par
}
{\phpg\posx1551\pvpg\posy2409\absw641\absh522 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Bi
nary
\par}{\phpg\posx1551\pvpg\posy2409\absw641\absh522 \sl-184 \par\f20 \fs16 \cf0 D
ecimal \par
}
cf0 1
\par}{\phpg\posx2959\pvpg\posy2426\absw110\absh506 \sl-184 \par\b \f20 \fs14 \cf
0 {\b0 \fs16 8 }\par
}
\par
}
\cf0 22
f0 {\b0 \fs16 4s }
f0 \fi43 {\fs14 1 }
f0 \fi42 {\b0 \fs16 4 }\par
}
\par
}
'
{\fs16 2s }
\fi73 {\b \fs14 1 }
{\fs16 2 }\par
}
\cf0 2 O
\fi72 {\fs16 Is }
\fi64 {\b \fs14 0 }
0 \fs26 + }\par
}
!2'
{\fs16 0.5s }
\fi61 {\b \fs14 1 }
{\fs16 0.5 }\par
}
{\phpg\posx6495\pvpg\posy1763\absw411\absh181 \f10 \fs15 \cf0 \f10 \fs15 \cf0 -\par
}
f0 . \par
}
\fs15 \cf0 1/z2
f0 {\b0 \f20 \fs16 0.25s }

f0 \fi191 {\f20 \fs14 0 }
fi27 {\b0 \fs26 + }\par
}
6 \cf0 1 p 3
{\fs16 0.125s }
\fi287 {\b \fs14 1 }
{\fs16 0.125}{\f10 \fs14
=}{\fs16
14.625 }\par
}
\cf0 Fig.{\f10 \fs15 1-3}{\b0 \fs16
Binary-to-decimal}{\b0 \fs16 conversion
}\par
}
\cf0 Convert the decimal number{\fs18 87} to a binary number. Figure{\fs1
8 1-4} shows a convenient method for
\par}{\phpg\posx851\pvpg\posy3802\absw8992\absh1275 \sl-232 \f20 \fs18 \cf0 maki
ng this conversion. The decimal number{\fs18 87} is first divided by 2, leaving
{\fs18 43} with a remainder of 1.
remainder{\fs18 is} important and is recorded at the right. It becomes the
{\b \fs18 LSB} in the binary number.
quotient{\fs18 (43)} then is transferred as shown by the arrow and becomes the
dividend. The quotients
\par}{\phpg\posx851\pvpg\posy3802\absw8992\absh1275 \sl-230 \f20 \fs18 \cf0 are
repeatedly divided by 2 until the quotient becomes{\fs18 0} with a remainder
{\fs18 of}{\fs18 1,} as in the last line{\fs18 of }
\par}{\phpg\posx851\pvpg\posy3802\absw8992\absh1275 \sl-241 \f20 \fs18 \cf0 Fig.
{\fs18 1-4.} Near the bottom the figure shows that decimal{\fs18 87} equals
binary{\fs18 1010111. }\par
}
{\phpg\posx3603\pvpg\posy5625\absw995\absh406 \f10 \fs21 \cf0 \f10 \fs21 \cf0 -+
{\f20 \fs16 2}{\dn006 \fs13 =}{\f20 \fs35 4" }\par
}
cf0 I.SB \par
}
; \par
}
{\phpg\posx4357\pvpg\posy5811\absw1131\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 r
emainder of{\b \f10 \fs15 1 }\par
}
3{\f30 \fs12 i}{\i \fs17 2}{\f10 \fs14 =} f l remainder of{\fs16 1 }\par
}
{\f10 \fs22 -+}{\fs17 2 }\par
}
{\phpg\posx3395\pvpg\posy6406\absw968\absh761 \f10 \fs59 \cf0 \f10 \fs59 \cf0 +7
\par
}
{\f20 \fs16 10}{\f20 \fs16 remainder}{\f20 \fs16 of}{\f20 \fs16 1 }\par

}
\par
}
{\f10 \fs13 -+}{\fs16 2}{\f10 \fs14 = }\par
}
emainder of{\fs16 0}{\f10 \fs20 - }\par
}
\f20 \fs16 5}{\fs13 -+}{\f20 \fs16 2}{\fs14 =}{\f20 \fs16
2}{\f20 \fs16
remainder}{\f20 \fs16 of}{\b \fs15 1 }
{\f20 \fs16 2}{\f30 \fs12 i}{\f20 \fs16 2}{\fs13 =}{\f20 \fs16
1}{\f20 \
fs16 remainder}{\b \f20 \fs16 of}{\f20 \fs16 0}{\b\dn006 \fs11 -1 }\par
}
{\phpg\posx3473\pvpg\posy7521\absw893\absh339 \f10 \fs28 \cf0 \f10 \fs28 \cf0 F--l \par
}
1
10 {\fs88 I}{\fs88 I}{\fs89 I }\par
}
0 MSH \par
}
\par
}
f0 0 \par
}
f0 1 \par
}
15 \cf0 01 \par
}
f0 1 \par
}
\cf0 Fig.{\f10 \fs15 1-4}{\b0 \fs16
Decimal-to-binary}{\b0 \fs16 conversion
}\par
}
\cf0 Convert the decimal number{\fs18 0.375} to a binary number. Figur
e{\fs18 1-51} illustrates one method{\fs18 of }
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-236 \f20 \fs18 \cf0 perf
orming this task. Note that the decimal number{\fs18 (0.375)} is being{
\fs18 multiplied} by{\fs18 2.} This leaves a
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-239 \f20 \fs18 \cf0 prod
uct of{\fs18 0.75.} The{\fs18 0} from the integer place{\fs18 (1s} place) be
comes the bit nearest the binary point. The
18 0.75} is then multiplied by{\fs18 2,} yielding{\fs18 1.50.} The carry{\fs1

8 of}{\fs18 1}to the integer{\fs18 (1s} place) is the next bit in the
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-230 \f20 \fs18 \cf0 bina
ry number. The 0.50 is then multiplied by{\fs18 2,} yielding a product{\
fs18 of}{\fs18 1.00.} The carry{\fs18 of} 1{\fs18 in} the
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-233 \f20 \fs18 \cf0 inte
ger place is the final 1 in the binary number. When the product is{\fs18 1.0
0,} the conversion process is
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-242 \f20 \fs18 \cf0 comp
lete. Figure{\fs18 1-5a} shows a decimal{\fs18 0.375} being converted into a
binary equivalent{\fs18 of}{\fs18 0.011. }
68 Figure{\fs18 1-5b} shows the decimal number{\fs18 0.84375} being Con
verted into binary. Again note that
18 0.84375} is multiplied by 2. The integer of each product is placed below,
forming the binary number.
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-230 \f20 \fs18 \cf0 When
the product reaches 1.00, the conversion is complete. This problem shows
a decimal{\fs18 0.84375 }
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-241 \f20 \fs18 \cf0 bein
g converted to binary{\fs18 0.11011. }
72 Consider the decimal number{\fs18 5.625.} Converting this number to binary i
nvolves{\fs19 two} processes. The
ger part{\fs18 of} the number{\i \fs19 (5)} is processed by{\fs18 repeated
}{\fs18 division} near the top in Fig.{\fs18 1-6.} Decimal{\fs19 5} is
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-229 \f20 \fs18 \cf0 conv
erted to a binary{\fs18 101.}The fractional part{\fs18 of} the decimal number{
\fs18 (.625)} is converted to binary .101
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-243 \f20 \fs18 \cf0 at t
he bottom in Fig.{\fs18 1-6.}The fractional part is converted to binary throug
h the{\fs18 repeated}{\fs18 multiplication }
\par}{\phpg\posx845\pvpg\posy9672\absw9081\absh3622 \sl-230 \f20 \fs18 \cf0 proc
ess. The integer and fractional sections are then combined to show th
at decimal{\fs18 5.625} equals
ry{\fs18 101.101. }\par
}
{\dn006 \f10 \fs22 +}{\dn006 2}{\dn006 \f10 \fs13 =5---}{\i \f30 \fs32 -1 }\
par
}
{\fs16 remainder}{\fs16 of}{\fs16 1 }
\fi900 {\b \fs14 87,,-l }\par
}
{\phpg\posx6971\pvpg\posy8416\absw111\absh332 \f10 \fs13 \cf0 \f10 \fs13 \cf0 "
{\b \f20 \fs14 1 }\par
}
cf0 1, \par
}
0 4 \par
}
}
AP.{\fs16 1 }\par
}
0 \fs11 \cf0 1
\b0 \f20 \fs16 0.6875}{\fs14
x}{\f20 \fs17 2}{\b0 \fs13 =}{\b0 \f20 \fs1
6 1.375 }\par
}
.375
0.75
{\i \fs16 0.50 }\par
}
{\phpg\posx6901\pvpg\posy2437\absw303\absh1057 \f10 \fs14 \cf0 \f10 \fs14 \cf0 x
{\f20 \fs17 2 }
{\dn006 x}{\f20 \fs16 2 }
{\b\dn006 x}{\f20 \fs17 2 }\par
}
{\f20 \fs16 0.75 }
={\fs15 1.50 }
={\fs15 1.00 }\par
}
.751 \par
}
f0 1 \par
}
{\phpg\posx1307\pvpg\posy2451\absw935\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 0.
375{\f10 \fs14 x} 2{\f10 \fs14 = }\par
}
.7;{\f10 \fs14
x}{\fs16 2}{\f10 \fs14 =}{\fs32 i }\par
}
\par
}
{\phpg\posx8217\pvpg\posy3664\absw55\absh166 \f10 \fs14 \cf0 \f10 \fs14 \cf0 . \
par
}
{\phpg\posx8449\pvpg\posy3664\absw73\absh166 \f10 \fs14 \cf0 \f10 \fs14 \cf0 * \
par
}
\par
}
par
}
\par
}
\cf0 0.84375,0={\fs14
.1}{\fs14
1}
0
f0 \fi486 {\i \fs14 (}{\i \fs14 h}{\i \fs14 ) }\par
}
cf0 1
1, \par
}
\cf0 Fig.{\fs17 1-5}{\b0 \fs17
Fractional}{\b0 \fs17 decimal-to-binary}{\b
0 \fs17 conversions }
f0 \fi240 {\b0\i \fs16 5}{\b0 \f10 \fs21 +}{\b0\dn006 2}{\b0 \f10 \fs14 =}{\
b0 2}{\b0 \fs17 remainder}{\b0 \fs17 of}{\b0 \fs16 1 }\par
}
s35 \cf0 c--l
{\b0\i0 \f20 \fs16 2}{\b0\i0 \f10 \fs20 +}{\b0\i0 \f20 \fs16 2}{\b0\i0 \f10 \
fs14 =}{\b0\i0 \f20 \fs16 1}{\b0\i0 \f20 \fs17 remainder}{\b0\i0 \f20 \fs17
of}{\b0\i0 \f20 \fs16 0 }
{\b0 \fs35 5----1 }\par
}
{\fs21 +}{\dn006 \f20 \fs16 2}{\fs13 =}{\f20 \fs16 0}{\f20 \fs17 remainder}
{\f20 \fs17 of} 1 \par
}
11 \par
}
0.625{\f10 \fs15 x}{\b\i \fs17 2}{\f10 \fs14 =}{\fs17 1.25 }
{\fs17 0.25}{\f10 \fs15
x}{\b\i 2}{\f10 \fs14 =}{\i \fs17 0.50 }
184 {\f10 \fs33 i---' }
{\i \fs17 0.50}{\b \f10 \fs15
x} 2{\f10 \fs14 =}{\f10 \fs16 1.00 }\par
}
\par
}
\cf0 Fig.{\fs16 1-6}{\b0 \fs17
Decimal-to-binary}{\b0 \fs17 conversion }\pa
r
}
cf0 SOLVED PROBLEMS
\par}{\phpg\posx861\pvpg\posy9074\absw3942\absh828 \sl-356 \b \f10 \fs17 \cf0 \f
i106 {\fs17 1.1}{\b0 \f20 \fs19
The}{\b0 \f20 \fs19 binary}{\b0 \f20 \fs19
number}{\b0 \f20 \fs19 system}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 the}{\b0 \f
20 \fs19 base }
i602 {\f20 \fs17 Solution: }\par
}
{\phpg\posx5567\pvpg\posy9417\absw2302\absh221 \f20 \fs19 \cf0 \f20 \fs19 \cf0 s

ystem and has a radix{\fs19 of }\par
}
par
}
The binary number system is the base{\fs17 2} system and has a radix of{\f
s17 2. }\par
}
The term bit means
\fs17 Solution: }
364 {\fs17 Bit}{\fs17 means}{\fs17 binary}{\fs17 digit. }\par
}
when dealing with binary numbers. \par
}
cf0 1.2 \par
}
cf0 1.3 \par
}
How would you say the number{\fs18 1001} in{\b\i \fs18 (}{\b\i \fs18 a}{\b\
i \fs18 )}binary and{\b\i \fs18 (}{\b\i \fs18 b}{\b\i \fs18 )}decimal?
\fs17 Solution: }
355 {\fs17 The}{\fs17 number}{\fs17 1001}{\fs17 is}{\fs17 pronounced}{\fs1
7 as}{\fs17 follows:}{\i \f10 \fs14
(a)}{\fs17 one,}{\fs17 zero,}{\fs1
7 zero,}{\fs17 one;}{\i \fs17
(b)}{\fs17 one}{\fs17 thousand}{\fs17
and}{\fs17 one. }\par
}
The number{\fs18 l}{\fs18 l}{\fs18 O}{\fs18 l}{\fs18 o} is a base
\fs17 Solution: }\par
}
umber. \par
}
cf0 1.4 \par
}
The number{\fs16 l}{\fs16 l}{\fs16 O}{\fs16 ,}{\fs16 o} is{\b a} base
10 number, as indicated by the small 10 after the number. \par
}
0 CHAP.{\b0 13 }\par
}
}

f0 5 \par
}
f0 1.5 \par
}
{\phpg\posx1485\pvpg\posy1388\absw4494\absh765 \f20 \fs19 \cf0 \f20 \fs19 \cf0 W
rite the base 2 number one, one, zero, zero, one.
\fs16 Solution: }
74 {\fs17 11001}{\b\dn006 \fs11 2 }\par
}
\cf0 1.6{\b0 \fs19
Convert}{\b0 \fs19 the}{\b0 \fs19 following}{\b0 \fs19
binary}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 decimal
}{\b0 \fs19 equivalents: }
fi490 {\b0\i \f10 \fs16 (a)}{\b0 \fs19
001100}{\i \fs19
(b)}{\b0 \fs19
000011}{\i \fs18
(c)}{\b0 \fs19
011100}{\i \fs19
(}{\i \fs19 d}{\i \fs
19 )}{\b0 \fs19
111100}{\b0\i \fs19
(e)}{\b0 \fs19
101010}{\b0\i \f30
\fs21 (f)}{\b0 \fs19 111111 }
fi490 {\i \fs17 (}{\i \fs17 g}{\i \fs17 )}{\b0 \fs19
100001}{\i \fs19
(h
)}{\b0 \fs19
111000 }
fi500 {\fs16 Solution: }
fi858 {\b0 \fs17 Follow}{\b0 \fs17 the}{\b0 \fs17 procedure}{\b0 \fs17
sh
own}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17
1-2.}{\b0 \fs17 The}{\b0 \
fs17 decimal}{\b0 \fs17 equivalents}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \f
s17 binary}{\b0 \fs17 numbers}{\b0 \fs17
are}{\b0 \fs17 as }
fi492 {\b0 \fs17 follows: }\par
}
s14 \cf0 ( a ){\b0\i0 \f20 \fs17
001100,}{\b0\i0 \fs15 =}{\b0\i0 \f20 \fs1
7 1zl0 }
{\b0 \f20 \fs17 (b)}{\b0\i0 \f20 \fs17
000011,}{\b0\i0 \fs14 =}{\i0 \f20 \
fs17 3,, }\par
}
\cf0 (c){\i0 \f20 \fs17
011100,}{\i0 \fs13 =}{\i0 \f20 \fs17 28,O }
\par}{\phpg\posx3407\pvpg\posy4283\absw1592\absh389 \sl-215 \i \f10 \fs15 \cf0 {
\b \fs16 (}{\b \fs16 d}{\b \fs16 )}{\i0 \f20 \fs17
111100,}{\i0 \fs14 =}{
\b\i0 \f20 \fs17 601, }\par
}
cf0 (e) \par
}
01010,{\f10 \fs14 =} 42,, \par
}
s18 \cf0 (f){\b0\i0 \f20 \fs17
111111,}{\b0\i0 \f10 \fs13 =}{\i0 \f20 \fs17
63,, }\par
}
\cf0 (8){\b0 \fs17
100001,}{\b0 \f10 \fs14 =}{\b0 \fs17 33,, }

\i \fs17 (}{\i \fs17 h}{\i \fs17 )}{\b0 \fs17
111000,}{\b0 \f10 \fs14 =}{
\b0 \fs17 56,, }\par
}
cf0 1.7 \par
}
1110001111,{\f10 \fs14 = }
}
\par
}
{\phpg\posx1853\pvpg\posy5852\absw5225\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 F
ollow the procedure shown in Fig.{\fs17 1-2.}{\fs17
11110001111,}{\f1
0 \fs13 =}{\fs17 19351,. }\par
}
cf0 1.8 \par
}
1100.011,{\f10 \fs14 = }
}
\par
}
ollow the procedure shown in Fig.{\fs17 1-3. }\par
}
100.011,{\f10 \fs14 =} 28.375,,. \par
}
cf0 1.9 \par
}
10011.10011,{\f10 \fs14 = }
}
cf0 10 \par
}
ollow the procedure shown in Fig.{\fs17 1-3. }\par
}
0011.10011,{\f10 \fs13 =} 51.59375,,. \par
}
f0 1.10 \par
}
010101010.1~{\f10 \fs15 = }
}
\par
}
ollow the procedure shown in Fig.{\fs17 1-3.}{\fs17
1010101010.1,}{\f1
0 \fs14 =}{\fs17 682.5,,. }\par
}
\cf0 1.11{\b0 \fs19
decimal}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 bina
ry}{\b0 \fs19 equivalents: }
fi590 {\b0\i \f10 \fs16 (a)}{\fs19
64,}{\b0\i
(b)}{\b0 \fs19
100,}{\i \
fs19
(}{\i \fs19 c}{\i \fs19 )}{\b0 \fs19
111,}{\i \fs19
(}{\i \fs19
d}{\i \fs19 )}{\b0 \fs19
145,}{\b0\i \fs19
(e)}{\b0 \fs19
255,}{\b0\i
\f30 \fs21 (f)}{\b0\i \fs19 500. }
fi950 {\b0 \fs17 Follow}{\b0 \fs17 the}{\b0 \fs17 procedure}{\b0 \fs17
sh
own}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17
1-4.}{\b0 \fs17 The}{\b0 \
fs17 binary}{\b0 \fs17 equivalents}{\b0 \fs17 of}{\b0 \fs17
the}{\b0 \f
s17 decimal}{\b0 \fs17 numbers}{\b0 \fs17 are}{\b0 \fs17 as }\par
}
follows:
s16 (a)}{\fs17
64,,}{\f10 \fs14 =}{\fs17 1000000, }
\i \fs17 (b)}{\fs17
100,,}{\f10 \fs14 =}{\fs17 1100100, }\par
}
\cf0 (c){\i0 \f20 \fs16
lll,,}{\i0 \fs13 =}{\i0 \f20 \fs17 1101111, }
\par}{\phpg\posx3683\pvpg\posy11931\absw1838\absh387 \sl-214 \i \f10 \fs15 \cf0
{\b \fs16 (}{\b \fs16 d}{\b \fs16 )}{\i0 \f20 \fs17
145,,}{\i0 \fs14 =}{
\i0 \f20 \fs17 10010001, }\par
}
fs17 \cf0 (e){\b0\i0 \f10 \fs16
25!&,}{\b0\i0 \f10 \fs14
=}{\b0\i0 1111
1111, }
0 {\f30 \fs17 (f)}{\b0\i0 500,,}{\b0\i0 \f10 \fs14 =}{\b0\i0 111110100, }\p
ar
}
\cf0 1.12{\b0 \fs17
34.7510}{\b0 \f10 \fs14 = }
fi590 {\fs16 Solution: }\par
}
\par
}
Follow the procedure shown in Fig.{\fs17 1-6.}{\fs17
34.75,,}{\f10 \f
s13 =}{\fs17 1OOOl0.11,. }\par
}
0 6 \par
}
MBERS USED{\fs18 IN} DIGITAL ELECTRONICS \par
}
f0 [CHAP.{\fs15 1 }\par
}
f0 1.13 \par
}
18 \cf0 25.25,,{\b0\i0 \fs17 = }
{\i0 \f20 \fs17 Solution: }\par
}
{\phpg\posx2943\pvpg\posy1442\absw91\absh150 \b\i \f10 \fs12 \cf0 \b\i \f10 \fs1
2 \cf0 2 \par
}
\cf0 Follow{\fs17 thc}{\fs17 proccdurc}{\fs17 shown}{\fs17 in}{\fs17 Fi
g.}{\fs15 1.6.}{\f10 \fs16
2S.2S1,,}{\b0 \f10 \fs14 =}{\f10 \fs15 1}{\fs
17 IoO1.01}{\i\dn006 \f10 \fs11 2}{\i\dn006 \f10 \fs11 . }\par
}
f0 1.14 \par
}
\cf0 27.1875,,{\b0 \fs14 = }
\f20 \fs17 Solution: }\par
}
f0 2 \par
}
\cf0 Follow thc proccdurc shown in{\fs16 Fig.}{\f10 \fs15 1-6.}{\f10 \fs
16
27.187s1,,}{\b0 \f10 \fs13 =}{\f10 \fs15 1}{\f10 \fs15 1}{\f10 \fs15 0
}{\f10 \fs15 1}{\fs17 1.OOlI}{\b0\dn006 \f10 \fs11 ?. }\par
}
\cf0 1-3{\f20 \fs19
HEXADECIMAL}{\f20 \fs19 NUhlBERS }
fi352 {\f30 \fs21 The}{\b0 \f20 \fs19 hexadecimal}{\b0 \f20 \fs20 number}{\b0
\f20 \fs19 system}{\b0 \f20 \fs19 has}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 rad
ix}{\b0 \f20 \fs19 of}{\fs16 16.}{\b0 \f20 \fs18 It}{\b0 \f20 \fs19 is}{\b
0 \f20 \fs19 referred}{\fs15 to}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 the}{\b0
\i \fs17 h}{\b0\i \fs17
e}{\i \fs17 16}{\i \f20 \fs18 rtirnibvr}{\i \f2
0 \fs19 sysiern. }
\b0 \f20 \fs19 It}{\b0 \f20 \fs20 uscs}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 sy
mbols}{\b0 \f20 \fs19 0-9,}{\fs18 A,}{\f30 \fs23 B,}C.{\fs18 D.}{\b0 \f20 \f
s20 E,}{\b0 \f20 \fs19 and}{\f30 \fs21 F}{\fs16 as}{\b0 \f20 \fs19 shown}{\
b0 \f20 \fs19 in}{\b0 \f20 \fs19 thc}{\b0 \f20 \fs19 hexadecinial}{\b0 \f20 \
fs19 coluniri}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 table}{
\b0 \f20 \fs19 in}{\f20 \fs17 Fig. }
fi24 {\fs18 1-7.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 letter}{\fs18 A}{\b0 \f
20 \fs19 stands}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 count}
{\b0 \f20 \fs20 of}{\fs17
10.}{\f30 \fs21 B}{\b0 \f20 \fs19 for}{\fs17
11,}{\i \f20 \fs19 C}{\b0 \f20 \fs19 for}{\fs17 12,}{\f30 \fs21 D}{\b0 \f
20 \fs19 for}{\fs17 13,}{\b0 \f20 \fs20 E}{\b0 \f20 \fs19 for}{\fs17 14,}
{\b0 \f20 \fs19 and}{\f20 \fs20 F}{\b0 \f20 \fs19 for}{\fs17 15.}{\b0 \f20
\fs19 Thc }
\b0 \f20 \fs19 advantage}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \f
s19 hexadecimal}{\b0 \f20 \fs19 system}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19
its}{\b0 \f20 \fs19 usefulness}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 conver
ting}{\b0 \f20 \fs19 dircctly}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 a}{\b0
\f20 \fs19 4-bit}{\b0 \f20 \fs19 binary }
\b0 \f20 \fs19 numbcr.}{\b0 \f20 \fs20 Notc}{\b0 \f20 \fs19 in}{\b0 \f20 \fs1
9 thc}{\b0 \f20 \fs19 shaded}{\b0 \f20 \fs19 section}{\b0 \f20 \fs19 of}{\b0
\f20 \fs19 Fig.}{\fs17 1-7}{\b0 \f20 \fs19 that}{\b0 \f20 \fs19 each}{\b0
\f20 \fs19 4-bit}{\b0 \f20 \fs19 binary}{\b0 \f20 \fs19 nunibcr}{\b0 \f20 \f
s19 froni}{\f30 \fs16 oo(K)}{\b0 \f20 \fs19 to}{\fs18 11}{\fs18 11}{\b0 \f2
0 \fs19 can }
\f30 \fs20 be}{\b0 \f20 \fs19 represented}{\f30 \fs19 by}{\fs16 a}{\b0 \f20
\fs19 unique}{\b0 \f20 \fs19 hexadecimal}{\b0 \f20 \fs19 digit. }\par
}
{\phpg\posx891\pvpg\posy10884\absw9197\absh2208 \b \f20 \fs17 \cf0 \fi1656 \b \f
20 \fs17 \cf0 Fig. 1-7{\fs17
Counting}{\fs17 in}{\fs17 dccimal.}{\fs17 bi
nary,}{\fs17 and}{\fs17 hcxadccimal}{\fs17 numbcr}{\fs17 systcms }
cf0 \fi368 {\f30 \fs21 Look}{\b0 \fs19 at}{\b0 \fs18 the}{\b0 \fs19 linc}{\b0
\fs19 labcled}{\f10 \fs17 16}{\b0 \fs19 in}{\b0 \fs18 the}{\b0 \fs19 de
cimal}{\b0 \fs19 column}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\f10 \fs18 1-7.}{\b
0 \fs19 'Ihe}{\b0 \fs19 hexadecimal}{\b0 \fs19 cquivalent}{\b0 \fs19 is}{
\f10 \fs17 10. }
{\b0 \fs19 This}{\b0 \fs19 shows}{\b0 \fs19 that}{\b0 \fs19 thc}{\b0 \fs19
hcxadccimal}{\b0 \fs19 number}{\b0 \fs19 system}{\b0 \fs20 uses}{\b0 \fs19
the}{\b0 \fs19 placc-value}{\b0 \fs19 idea.}{\b0 \fs19 The}{\f10 \fs17 1}{
\b0 \fs20 (in}{\f10 \fs17 10J}{\b0 \fs19 stands}{\b0 \fs20 for }
\fi22 {\f10 \fs18 16}{\b0 \fs19 units,}{\b0 \fs19 whilc}{\b0 \fs19 thc}{\b0 \
fs20 0}{\b0 \fs19 stands}{\b0 \fs19 for}{\fs20 zcro}{\b0 \fs19 units. }
\fi362 {\b0 \fs20 Convert}{\b0 \fs19 the}{\b0 \fs19 hexadecimal}{\b0 \fs19
number}{\b0 \fs19 2Bb}{\b0 \fs19 into}{\f10 \fs16 a}{\b0 \fs19 decimal}
{\b0 \fs19 numbcr.}{\b0 \fs19 Figure}{\f10 \fs17 1-80}{\b0 \fs19 shows}{
\b0 \fs19 the}{\b0 \fs19 familiar }
{\b0 \fs19 process.}{\b0 \fs19 The}{\b0 \fs20 2}{\b0 \fs19 is}{\b0 \fs19
in}{\b0 \fs19 the}{\b0 \fs19 256s}{\b0 \fs19 placc}{\f10 \fs17
so}{\f1
0 \fs17
2}{\f10 \fs18 x}{\fs18 256}{\b0 \f10 \fs14 =}{\f10 \fs17 512.}{\b
0 \fs19 which}{\b0 \fs19 is}{\b0 \fs19 written}{\b0 \fs19 in}{\b0 \fs19
the}{\b0 \fs19 decimal}{\b0 \fs20 line.}{\b0 \fs19 The }
{\b0 \fs19 hexadecimal}{\b0 \fs19 digit}{\b0 \fs20 B}{\b0 \fs19 appcars}{\
b0 \fs20 in}{\b0 \fs19 thc}{\f10 \fs17
16s}{\b0 \fs19 column.}{\b0 \fs19
Notc}{\b0 \fs20 in}{\b0 \fs19 Fig.}{\f10 \fs17 1-8}{\b0 \fs19 that}{\b
0 \fs19 hexadecinial}{\f30 \fs23 B}{\b0 \fs19 corresponds }
{\b0 \fs20 to}{\b0 \fs19 decimal}{\f10 \fs17 11.}{\b0 \fs19 This}{\b0 \fs19
means}{\b0 \fs19 that}{\b0 \fs19 there}{\b0 \fs19 are}{\b0 \fs20 clcvcn}{\
f10 \fs17 16s}{\f10 \fs17 (16}{\f10 \fs15 X}{\f10 \fs17 11}{\f10 \fs19 1,}
{\b0 \fs19 yiclding}{\f10 \fs18 176.}{\b0 \fs19 I'hc}{\b0 \fs18 176}{\b0 \f
s19 is}{\b0 \fs19 added}{\b0 \fs19 into}{\b0 \fs19 the }

{\b0 \fs19 decimal}{\b0 \fs19 total}{\b0 \fs20 near}{\b0 \fs19 the}{\b0 \f
s19 bottom}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\f10 \fs17
1-8a.}{\b0 \fs19
Thc}{\f10 \fs16
1s}{\b0 \fs19 column}{\b0 \fs19 shows}{\b0 \fs19 six}{\f3
0 \fs18 Is.}{\b0 \fs19 Thc}{\b0 \fs17 6}{\b0 \fs18 is}{\f10 \fs17 added}
{\b0 \fs19 into}{\b0 \fs19 the }\par
}
{\phpg\posx897\pvpg\posy13259\absw4651\absh502 \f20 \fs19 \cf0 \f20 \fs19 \cf0 d
ccimal line. The decimal values arc added{\b \f10 \fs18 (512}{\f10 \fs26 + }
\par}{\phpg\posx897\pvpg\posy13259\absw4651\absh502 \sl-238 \f20 \fs19 \cf0 that
{\b\i \f10 \fs18 286,,} equals{\b \fs18 694,,,. }\par
}
\cf0 176{\b0 \fs24 +}{\b0 \f20 \fs18 6}{\b0\dn006 \fs14 =}{\f20 \fs19 694).
}{\b0 \f20 \fs19 yiclding} 694,(,.{\b0 \f20 \fs19 Figurc} 1-0a{\b0 \f20 \fs19
shows }\par
}
{\phpg\posx883\pvpg\posy565\absw840\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 CHAP
.{\fs17 11 }\par
}
}
{\phpg\posx9609\pvpg\posy540\absw128\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 7 \
par
}
okers{\fs16 of} 16
Place value
Hexadecimal number \par
}
56s
\fi113 {\b \f10 \fs14 2 }
\fs14 256 }
0 \fs15 - }
0 {\i \fs15 x}{\i \fs15 2 }
16 512 }\par
}
{\phpg\posx2407\pvpg\posy3047\absw636\absh188 \f20 \fs16 \cf0 \f20 \fs16 \cf0 De
cimal \par
}
\cf0 16s
\fi93 {\b \fs15 B }
53 {\f10 \fs13 16 }
\par}{\phpg\posx5273\pvpg\posy1898\absw364\absh1199 \sl-242 \f20 \fs16 \cf0 {\up
006 \f10 \fs11 x}{\f10 \fs15 - }
2 {\f10 \fs15 176 }\par

}
1 \par
}
\par
}
\par
}
\fs14 \cf0 6
i163 {\b0 I }
\par}{\phpg\posx6123\pvpg\posy2370\absw248\absh776 \sl-152 \b \f20 \fs14 \cf0 {\
b0 \f10 \fs13 x}{\b0 \f10 \fs13 6 }
b0 \f10 \fs15 - }
i116 {\b0 \fs16 6 }\par
}
{\phpg\posx6547\pvpg\posy3028\absw736\absh184 \f10 \fs12 \cf0 \f10 \fs12 \cf0 =:
{\b \f20 \fs16 6941,, }\par
}
{\phpg\posx3683\pvpg\posy3443\absw186\absh113 \i \f10 \fs9 \cf0 \i \f10 \fs9 \cf
0 ( U ) \par
}
{\phpg\posx3957\pvpg\posy3394\absw2486\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 H
exadecimal-to-decimal conversion \par
}
Powers of{\fs16 16 }
Place value
Hexadecimalnumber \par
}
{\phpg\posx5475\pvpg\posy4606\absw1411\absh84 \f10 \fs6 \cf0 \f10 \fs6 \cf0 ___.
__________- \par
}
\cf0 2{\fs16 56s }
\fi123 {\b \fs14 A }
3 {\fs15 256 }
0 \fs12 x}{\b \f10 \fs14 10 }\par
}
\cf0 1 / 1 6 '
{\fs16 .0625s }
\fi231 {\b \fs15 C }
8 {\fs14 ,062}{\b\i \f10 \fs14 5 }
6 {\f10 \fs11 x}{\f10 \fs13 1' }\par
}
{\phpg\posx5369\pvpg\posy5286\absw210\absh410 \b \f20 \fs14 \cf0 \fi47 \b \f20 \
fs14 \cf0 3
b0 \f10 \fs13 16 }\par
}
cf0 F
i93 {\b0 \fs14 I }\par
}
f0 - \par
}
3 \par
}
560{\f10 \fs27 +}{\fs22
48}{\f10 \fs26
+ }\par
}
{\phpg\posx6095\pvpg\posy5731\absw382\absh230 \f10 \fs12 \cf0 \f10 \fs12 \cf0 x{
\fs19 - }\par
}
cimal \par
}
{\phpg\posx6251\pvpg\posy5676\absw267\absh423 \f10 \fs18 \cf0 \fi21 \f10 \fs18 \
cf0 1s
\par}{\phpg\posx6251\pvpg\posy5676\absw267\absh423 \sl-243 \f10 \fs18 \cf0 {\b \
fs15 15 }\par
}
{\phpg\posx6575\pvpg\posy5827\absw861\absh316 \f10 \fs26 \cf0 \f10 \fs26 \cf0 +{
\i \f30 \fs24 6% }\par
}
{\f20 \fs16
2623.7510 }\par
}
\cf0 (h){\i0 \f20 \fs15 Fractional}{\i0 \f20 \fs15 hexadecimal-to-decimal}{\i
0 \f20 \fs15 conversion }
f0 \fi1613 {\b\i0 \f20 \fs16 Fig.}{\b\i0 \fs15 1-8 }\par
}
\cf0 Convert the hexadecimal number A3F.C to its decimal equivalent. F
igure{\fs18
1-8b} details this
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-234 \f20 \fs19 \cf0 prob
lem. First consider the 256s column. The hexadecimal digit{\b \f30 \fs20 ,4}mea
ns that 256 must be multiplied
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-241 \f20 \fs19 \cf0 by
10, resulting in{\b a} product of 2560. The hexadecimal number shows that{
\fs18 it} contains three 16s, and
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-237 \f20 \fs19 \cf0 ther
efore 16{\f10 \fs19 x} 3{\f10 \fs14 =}{\fs18 48,} which is added to the d
ecimal line. The{\fs18 1s} column contains the hexadecimal
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-232 \f20 \fs19 \cf0 digi
t F, which means{\fs18 1}{\f10 \fs14 X}{\fs18 15}{\dn006 \f10 \fs13 =}{\fs19
15.} The{\fs19 15} is added to the decimal line. The 0.0625s column conta
ins
hexadecimal digit C, which means 12{\f10 \fs14 X} 0.0625{\f10 \fs14 =} 0

.75. The 0.75 is added to the decimal line.
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-240 \f20 \fs19 \cf0 Addi
ng the contents of the decimal line (2560{\f10 \fs27 +} 48{\b \fs17 -t}{\fs1
9 15}{\f10 \fs27 +} 0.75{\dn006 \f10 \fs13 =} 2623.75) gives the decimal numbe
r
.75. Figure 1-8h converts A3F.C{\b\dn006 \fs11 16} to 2623.75,,,.
68 Now reverse the process and convert the decimal number 45 to its hexadecimal
equivalent. Figure
3 {\fs18 1-9a} details the familiar repeated divide-by-16process. The decimal nu
mber 45 is first divided by 16,
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-240 \f20 \fs19 \cf0 resu
lting in a quotient{\fs18 of} 2 with a remainder{\fs18 of} 13. The remainder{
\fs18 of} 13 (D in hexadecimal) becomes
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-241 \f20 \fs19 \cf0 the{
\fs18 LSD} of the hexadecimal number. The quotient{\fs18 (2)} is tran
sferred to the dividend position and
\par}{\phpg\posx887\pvpg\posy7358\absw9050\absh3314 \sl-230 \f20 \fs19 \cf0 divi
ded by 16.This results in a quotient{\fs18 of}{\fs18 0} with a remainder of 2.
The 2 becomes the next digit in the
\fi5107 {\b\i \fs16 2SO}{\f10 \fs22 +}{\fs16 16}{\dn006 \f10 \fs13 =}{\fs16
15}{\fs16 remainder}{\fs16 of}{\fs16 10 }\par
}
5{\f10 \fs19 +-}{\fs16 16}{\dn006 \f10 \fs13 = }\par
}
45{\f10 \fs20 -+} 16{\dn006 \f10 \fs13 =}{\f10 \fs15 2} remainder{\fs17
of} 13
i95 {\f10 \fs17 r--J }
i85 {\f10 \fs15 2}{\f10 \fs20 -+} 16{\dn006 \f10 \fs13 =}{\f10 \fs15 0} remai
nder{\fs17 of}{\fs16
2 }
0 \fi1957 {\b \f10 \fs14 451@=2 }\par
}
0 remainder of 15
\fi910 {\b \f10 \fs14 250.25 }\par
}
{\b \f20 \fs15 F }\par
}
\cf0 A{\b0 \f10 \fs7
*}{\f10 \fs14 4}{\dn006 \f10 \fs9 16 }\par
}
I \par
}
0.25{\f10 \fs14 :<} 16{\f10 \fs13 =} 4.00
133 {\f10 \fs18 .c}{\f30 \fs28 I }
10 \fs15 0.00}{\b \f30 \fs12 :K} 16{\f10 \fs14 =} 0.00

\fi63 {\fs14 (b)}{\fs15 Fractional}{\fs15 decimal-to-hexadecimal}{\fs15 con
version }\par
}
\cf0 D,, \par
}
(a){\fs15 Decimal-to-hexadecimal}{\fs15 conversion }\par
}
\cf0 Fig. 1-9 \par
}
{\phpg\posx859\pvpg\posy530\absw128\absh213 \f20 \fs19 \cf0 \f20 \fs19 \cf0 8 \p
ar
}
MBERS{\fs17 USED} IN DIGITAL ELECTRONICS \par
}
AP.{\fs17 1 }\par
}
{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \f20 \fs19 \cf0 \f20 \fs19 \cf0 h
exadecimal number. The process is complete because the integer part of
the quotient is{\fs19 0.} The
ess in Fig. 1-9a converts the decimal number 45 to the hexadecimal number 2D.
62 Convert the decimal number 250.25 to a hexadecimal number. The conversion
must be done by
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-234 \f20 \fs19 \cf0 usin
g{\fs19 two} processes as shown in Fig. 1-9b. The integer part of the decimal
number{\fs19 (250)} is converted
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-237 \f20 \fs19 \cf0 to h
exadecimal by using the repeated divide-by-16 process. The remainders of 10 (A
in hexadecimal)
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-242 \f20 \fs19 \cf0 and
15 (F in hexadecimal) form the hexadecimal whole number FA. The fractional part
of the{\fs19 250.25 }
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-232 \f20 \fs19 \cf0 is m
ultiplied by 16{\fs19 (0.25}{\i \f10 \fs15 X} 16). The result is{\fs19 4.00
.} The integer 4 is transferred to the position shown in
1-9b. The completed conversion shows the decimal number{\fs19 250.25}
equaling the hexadecimal
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-237 \f20 \fs19 \cf0 numb
er FA.4.
54 The prime advantage{\fs19 of} the hexadecimal system is its easy con
version to binary. Figure 1-10a
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-236 \f20 \fs19 \cf0 show
s the hexadecimal number{\b 3B9} being converted to binary. Note that each hexa
decimal digit forms
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-237 \f20 \fs19 \cf0 a gr
oup of four binary digits,{\fs19 or} bits. The groups of bits are then combined
to form the binary number.
\par}{\phpg\posx857\pvpg\posy1350\absw9095\absh2776 \sl-237 \f20 \fs19 \cf0 In t
his case 3B9,, equals 1110111001,. \par

}
\cf0 (a){\i0 \f20 \fs15 Hexadecimal-to-binaryconversion }\par
}
{\phpg\posx3643\pvpg\posy6552\absw3392\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 (
6) Fractional hexadecimal-to-binaryconversion \par
}
010
1000{\b
0101 }\par
}
cf0 1
f10 \fs15 A }\par
}
f10 \fs15 8 }\par
}
\par}{\phpg\posx4731\pvpg\posy7081\absw165\absh423 \sl-217 \f20 \fs21 \cf0 {\b\i
\f10 \fs16 5 }\par
}
{\phpg\posx4955\pvpg\posy7009\absw43\absh70 \b\i \f10 \fs5 \cf0 \b\i \f10 \fs5 \
cf0 0 \par
}
01010000101~{\fs13 =}{\b \fs16 A8516 }\par
}
s12 \cf0 ( c ){\b0\i0 \f20 \fs15 Binary-to-hexadecimalconversion }\par
}
\f10 \fs14 \cf0 ( d ){\b0\i0 \f20 \fs15 Fractional}{\b0\i0 \f20 \fs15 binary
-to-hexadecimalconversion }
\cf0 \fi4030 {\i0 \f20 \fs17 Fig.}{\i0 \f20 \fs17 1-10 }
\fi360 {\b0\i0 \f20 \fs19 Another}{\b0\i0 \f20 \fs19 hexadecimal-to-binary}{\b
0\i0 \f20 \fs19 conversion}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20 \fs19 detailed}
{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 Fig.}{\b0\i0 \f20 \fs19 1-106.}{\b0\
i0 \f20 \fs19 Again}{\b0\i0 \f20 \fs19 each}{\b0\i0 \f20 \fs19 hexadecimal}{\b
0\i0 \f20 \fs19 digit }
{\b0\i0 \f20 \fs19 forms}{\b0\i0 \f20 \fs19 a}{\b0\i0 \f20 \fs19 4-bit}{\b0\i
0 \f20 \fs19 group}{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20
\fs19 binary}{\b0\i0 \f20 \fs19 number.}{\b0\i0 \f20 \fs19 The}{\b0\i0 \f20 \
fs19 hexadecimal}{\b0\i0 \f20 \fs19 point}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20
\fs19 dropped}{\b0\i0 \f20 \fs19 straight}{\b0\i0 \f20 \fs19 down}{\b0\i0 \f2
0 \fs19 to}{\b0\i0 \f20 \fs19 form}{\b0\i0 \f20 \fs19 the }
{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 point.}{\b0\i0 \f20 \fs19 The}{\
b0\i0 \f20 \fs19 hexadecimal}{\b0\i0 \f20 \fs19 number}{\b0\i0 \f20 \fs19 47.
FE}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20 \fs19 converted}{\b0\i0 \f20 \fs19 to}{
\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 number}{\b
0\i0 \f20 \fs19 1000111.1111111.}{\b0\i0 \f20 \fs19 It}{\b0\i0 \f20 \fs19 is }
{\b0\i0 \f20 \fs19 apparent}{\b0\i0 \f20 \fs19 that}{\b0\i0 \f20 \fs19 hexa
decimal}{\b0\i0 \f20 \fs19 numbers,}{\b0\i0 \f20 \fs19 because}{\b0\i0 \f20
\fs19 of}{\b0\i0 \f20 \fs19 their}{\b0\i0 \f20 \fs19 compactness,}{\b0\i0

\f20 \fs19 are}{\b0\i0 \f20 \fs19 much}{\b0\i0 \f20 \fs19 easier}{\b0\i0 \
f20 \fs19 to}{\b0\i0 \f20 \fs19 write}{\b0\i0 \f20 \fs19 down }
{\b0\i0 \f20 \fs19 than}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 long}{\b0\i
0 \f20 \fs19 strings}{\b0\i0 \f20 \fs19 of}{\b0\i0 \f20 \fs19 1s}{\b0\i0 \f2
0 \fs19 and}{\i0 \f20 \fs19 OS}{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 bina
ry.}{\b0\i0 \f20 \fs19 The}{\b0\i0 \f20 \fs19 hexadecimal}{\b0\i0 \f20 \fs19
system}{\b0\i0 \f20 \fs19 can}{\b0\i0 \f20 \fs19 be}{\b0\i0 \f20 \fs19 though
t}{\b0\i0 \f20 \fs19 of}{\b0\i0 \f20 \fs19 as}{\b0\i0 \f20 \fs19 a}{\b0\i0 \f
20 \fs19 shorthand }
{\b0\i0 \f20 \fs19 method}{\b0\i0 \f20 \fs19 of}{\b0\i0 \f20 \fs19 writing}{
\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 numbers. }
\fi364 {\b0\i0 \f20 \fs19 Figure}{\b0\i0 \f20 \fs19 1-1Oc}{\b0\i0 \f20 \fs19
shows}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 num
ber}{\b0\i0 \f20 \fs19 101010000101}{\b0\i0 \f20 \fs19 being}{\b0\i0 \f20 \fs1
9 converted}{\b0\i0 \f20 \fs19 to}{\b0\i0 \f20 \fs19 hexadecimal.}{\b0\i0 \f2
0 \fs19 First}{\b0\i0 \f20 \fs19 divide }
{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 number}
{\b0\i0 \f20 \fs19 into}{\b0\i0 \f20 \fs19 4-bit}{\b0\i0 \f20 \fs19 groups
}{\b0\i0 \f20 \fs19 starting}{\b0\i0 \f20 \fs19 at}{\b0 \f20 \fs19 the}{\b0
\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 point.}{\b0\i0 \f20 \fs19 Each}{\b
0\i0 \f20 \fs19 group}{\b0\i0 \f20 \fs19 of}{\b0\i0 \f20 \fs19 four}{\b0\i
0 \f20 \fs19 bits}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20 \fs19 then }
{\b0\i0 \f20 \fs19 translated}{\b0\i0 \f20 \fs19 into}{\b0\i0 \f20 \fs19 an}
{\b0\i0 \f20 \fs19 equivalent}{\b0\i0 \f20 \fs19 hexadecimal}{\b0\i0 \f20 \fs1
9 digit.}{\b0\i0 \f20 \fs19 Figure}{\b0\i0 \f20 \fs19 1-10c}{\b0\i0 \f20 \f
s19 shows}{\b0\i0 \f20 \fs19 that}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs1
9 101010000101}{\b0\i0 \f20 \fs19 equals }
{\b0\i0 \f20 \fs19 hexadecimal}{\i0 \f20 \fs19 A85. }
\fi358 {\b0\i0 \f20 \fs19 Another}{\b0\i0 \f20 \fs19 binary-to-hexadecimal}{\b
0\i0 \f20 \fs19 conversion}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs19 illustrat
ed}{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 Fig.}{\b0\i0 \f20 \fs19 1-10d.}{\
b0\i0 \f20 \fs19 Here}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 10010.0110
1}{\b0\i0 \f20 \fs19 1}{\b0\i0 \f20 \fs19 is }
{\b0\i0 \f20 \fs19 to}{\b0\i0 \f20 \fs19 be}{\b0\i0 \f20 \fs19 translated}{\b
0\i0 \f20 \fs19 into}{\b0\i0 \f20 \fs19 hexadecimal.}{\b0\i0 \f20 \fs19 Fir
st}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \f20 \fs19 number
}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20 \fs19 divided}{\b0\i0 \f20 \fs19 into}{\b
0\i0 \f20 \fs19 groups}{\b0\i0 \f20 \fs19 of}{\b0\i0 \f20 \fs19 four}{\b0\i0
\f20 \fs19 bits,}{\b0\i0 \f20 \fs19 starting }
{\b0\i0 \f20 \fs19 at}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 binary}{\b0\i
0 \f20 \fs19 point.}{\b0\i0 \f20 \fs19 Three}{\f20 \fs19 OS}{\b0\i0 \f20 \fs1
9 are}{\b0\i0 \f20 \fs19 added}{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 the
}{\b0\i0 \f20 \fs19 leftmost}{\b0\i0 \f20 \fs19 group,}{\b0\i0 \f20 \fs19 fo
rming}{\b0\i0 \f20 \fs19 0001.}{\b0\i0 \f20 \fs19 Two}{\i0 \f20 \fs19 OS}{\b0
\i0 \f20 \fs19 are}{\b0\i0 \f20 \fs19 added}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f
20 \fs19 the }
{\b0\i0 \f20 \fs19 rightmost}{\b0\i0 \f20 \fs19 group,}{\b0\i0 \f20 \fs19 for
ming}{\b0\i0 \f20 \fs19 1100.}{\b0\i0 \f20 \fs19 Each}{\b0\i0 \f20 \fs19 grou
p}{\b0\i0 \f20 \fs19 now}{\b0\i0 \f20 \fs19 has}{\i0 \f20 \fs18 4}{\b0\i0 \f2
0 \fs19 bits}{\b0\i0 \f20 \fs19 and}{\b0\i0 \f20 \fs19 is}{\b0\i0 \f20 \fs19
translated}{\b0\i0 \f20 \fs19 into}{\b0\i0 \f20 \fs19 a}{\b0\i0 \f20 \fs19 h
exadecimal}{\b0\i0 \f20 \fs19 digit}{\b0\i0 \f20 \fs19 as }
{\b0\i0 \f20 \fs19 shown}{\b0\i0 \f20 \fs19 in}{\b0\i0 \f20 \fs19 Fig.}{\b0\i
0 \f20 \fs19 1-10d.}{\b0\i0 \f20 \fs19 The}{\b0\i0 \f20 \fs19 binary}{\b0\i0 \
f20 \fs19 number}{\b0\i0 \f20 \fs19 10010.011011}{\b0\i0 \f20 \fs19 then}{\b
0\i0 \f20 \fs19 equals}{\b0\i0 \f20 \fs19 12.6C,,. }
\fi358 {\b0\i0 \f20 \fs19 As}{\b0\i0 \f20 \fs19 a}{\b0\i0 \f20 \fs19 practi
cal}{\b0\i0 \f20 \fs19 matter,}{\b0\i0 \f20 \fs19 many}{\b0\i0 \f20 \fs19
modern}{\b0\i0 \f20 \fs19 hand-held}{\b0\i0 \f20 \fs19 calculators}{\b0\i0 \
f20 \fs19 perform}{\b0\i0 \f20 \fs19 number}{\b0\i0 \f20 \fs19 base}{\b0\i
0 \f20 \fs19 conversions. }
{\b0\i0 \f20 \fs19 Most}{\b0\i0 \f20 \fs19 can}{\b0\i0 \f20 \fs19 convert}{\b
0\i0 \f20 \fs19 between}{\b0\i0 \f20 \fs19 decimal,}{\b0\i0 \f20 \fs19 hexade
cimal,}{\b0\i0 \f20 \fs19 octal,}{\b0\i0 \f20 \fs19 and}{\b0\i0 \f20 \fs19 bi
nary.}{\b0\i0 \f20 \fs19 These}{\b0\i0 \f20 \fs19 calculators}{\b0\i0 \f20 \fs
19 can}{\b0\i0 \f20 \fs19 also}{\b0\i0 \f20 \fs19 perform }
{\b0\i0 \f20 \fs19 arithmetic}{\b0\i0 \f20 \fs19 operations}{\b0\i0 \f20 \fs19
in}{\b0\i0 \f20 \fs19 various}{\b0\i0 \f20 \fs19 bases}{\b0\i0 \f20 \fs19 (
such}{\b0\i0 \f20 \fs19 as}{\b0\i0 \f20 \fs19 hexadecimal). }\par
}
0 CHAP.{\i0 11 }\par
}
MBERS{\fs17 USED}{\fs17 IN}{\fs17 DIGITAL}{\fs17 ELECTRONICS }\par
}
f0 9 \par
}
{\phpg\posx867\pvpg\posy1344\absw6675\absh1065 \f10 \fs16 \cf0 \f10 \fs16 \cf0 S
OLVED PROBLEMS
\f20 \fs18 1.15}{\f20 \fs19
The}{\f20 \fs19 hexadecimal}{\f20 \fs19 number
}{\f20 \fs19 system}{\f20 \fs19 is}{\f20 \fs19 sometimes}{\f20 \fs19 called}
{\f20 \fs19 the}{\f20 \fs19 base }
97 {\b \f20 \fs17 Solution: }
46 {\f20 \fs17 The}{\f20 \fs17 hexadecimal}{\f20 \fs17 number}{\f20 \fs17 s
ystem}{\f20 \fs17 is}{\f20 \fs17 sometimes}{\f20 \fs17 called}{\f20 \fs17 th
e}{\f20 \fs17 base}{\f20 \fs17 16}{\f20 \fs17 system. }\par
}
{\phpg\posx7631\pvpg\posy1696\absw730\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 sy
stem. \par
}
cf0 1.16{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 16}{\b0 \fs19 symbols}
{\b0 \fs19 used}{\b0 \fs19 in}{\b0 \fs19 the}{\b0 \fs19 hexadecimal}{\b0 \fs
19 number}{\b0 \fs19 system. }
i590 {\fs17 Solution: }
i949 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 1-7.}{\b0 \fs1
7 The}{\b0 \fs17 16}{\b0 \fs17 symbols}{\b0 \fs17 used}{\b0 \fs17 in}{\b0

\fs17 the}{\b0 \fs17 hexadecimalnumber}{\b0 \fs17 system}{\b0 \fs17 are}{\
b0 \fs16 0,}{\b0 \fs17 1,2,}{\b0 \fs17 3,}{\b0 \fs17 4,}{\b0 \fs17 5,}{\b0
\fs17 6,}{\b0 \fs17 7,}{\b0 \fs17 8,}{\b0 \fs17 9, }
i586 {\b0 \fs17 A,}{\b0 \fs17 B,}{\b0 \fs17 C,}{\b0 \fs17 D,}{\b0 \fs17 E,}
{\b0 \fs17 and}{\b0 \fs17 F. }\par
}
f0 1.17 \par
}
Convert the followingwhole hexadecimal numbers to their decimal equivalents:
\f10 \fs16 (a)} C,{\fs19
(6)} 9F,{\fs18
(c)}
D52,{\i \f10 \fs18
(}{\i \f10 \fs18 d}{\i \f10 \fs18 )}{\fs19
67E,}{\i \fs19
(}{\i \fs19
e}{\i \fs19 )}{\b \fs19
ABCD. }
\fs17 Solution: }
360 {\fs17 Follow}{\fs17 the}{\fs17 procedure}{\fs17 shown}{\fs17 in}{\f
s17 Fig.}{\fs17 I-8a.}{\fs17 Refer}{\fs17 also}{\fs17 to}{\fs17 Fig.
}{\fs17 1-7.}{\fs17 The}{\fs17 decimal}{\fs17 equivalents}{\fs17 of}{\f
s17 the }
s17 hexadecimal}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 (a){\i0 \f20 \fs17
C,,}{\i0\dn006 \fs11
=}{\i0 \f20 \fs17 12,,, }
\i0 \f20 \fs17 (6)}{\i0 \f20 \fs17
9F,,}{\i0 \fs13 =}{\i0 \f20 \fs17 159,
, }\par
}
{\phpg\posx3203\pvpg\posy5787\absw831\absh194 \i \f20 \fs17 \cf0 \i \f20 \fs17 \
cf0 (c){\i0 \fs17
D52,, }\par
}
{\phpg\posx4123\pvpg\posy5787\absw665\absh194 \f10 \fs11 \cf0 \f10 \fs11 \cf0 ={
\f20 \fs17 34101, }\par
}
\cf0 ( e ){\i0 \fs17
ABCD,,}{\i0 \f10 \fs13 =}{\i0 \fs17 439811,, }\par
}
\cf0 ( d ){\i0 \f20 \fs17
67E1,}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 1662,"
}\par
}
\cf0 1.18{\b0 \fs19
hexadecimal}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 d
ecimal}{\b0 \fs19 equivalents: }
fi586 {\b0\i \f10 \fs16 (a)}{\b0 \fs19
F.4,}{\b0\i \fs18
(b)}{\b0 \fs19
D3.E,}{\b0\i \fs19
(c)}{\b0 \fs19
1111.1,}{\b0\i \f10 \fs18
(d)}{\b0
\fs19
888.8,}{\b0\i \fs19
(}{\b0\i \fs19 e}{\b0\i \fs19 )}{\b0 \fs19
EBA.C. }
fi946 {\b0 \fs17 Follow}{\b0 \fs17 the}{\b0 \fs17 procedure}{\b0 \fs17 sho
wn}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0\i \fs17 1-8b.}{\b0 \fs17 Refer}{\b
0 \fs17 also}{\b0 \fs16 to}{\b0 \fs17 Fig.}{\b0 \fs17 1-7.}{\b0 \fs17

The}{\b0 \fs17 decimal}{\b0 \fs17 equivalents}{\b0 \fs17 of}{\b0 \fs17 t
he }
fi586 {\b0 \fs17 hexadecimal}{\b0 \fs17 numbers}{\b0 \fs17 are}{\b0 \fs17 a
s}{\b0 \fs17 follows: }
fi584 {\b0\i \f10 \fs14 (a>}{\b0 \fs17
F.4,,}{\b0\dn006 \f10 \fs11
=}{\b0
\fs17 15.25,"}{\b0\i \f10 \fs14
(c)}{\b0 \fs17
1111.1,,}{\b0
\f10 \fs13 =}{\b0 \fs17 4369.0625,,}{\b0\i \fs17
(}{\b0\i \fs17 e}
{\b0\i \fs17 )}{\b0 \fs17
EBA.C16}{\b0 \f10 \fs13 =}{\b0 \fs17 3770.75,, }\
par
}
6){\fs17
D3.E1,}{\fs17
211.8751,}{\i \f10 \fs16
(d)}{\fs17
888.81,}{\fs17
2184.51, }\par
}
\cf0 1.19{\b0 \fs19
Convert}{\b0 \fs19 the}{\b0 \fs19 followingwhole}{\b0
\fs19 decimal}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19
hexadecimal}{\b0 \fs19 equivalents: }
fi584 {\b0\i \f10 \fs16 (a)}{\b0 \fs19
8,}{\b0 \fs19
(6)}{\b0 \fs19
10,
}{\b0
(c)}{\b0 \fs18
14,}{\b0\i \f10 \fs18
(d)}{\b0 \fs19
16,}{\i \
fs18
(}{\i \fs18 e}{\i \fs18 )}{\b0 \fs19
80,}{\b0\i \f30 \fs21 (f)}{\
b0\i \fs19 2560,}{\i \f30 \fs17 (8)}{\b0 \fs19 3000,}{\b0\i \fs19
(h)}{
\b0 \fs19
62,500. }
fi948 {\b0 \fs17 Follow}{\b0 \fs17 the}{\b0 \fs17 procedure}{\b0 \fs17 sho
wn}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 1-9a.}{\b0 \fs17 Refer}{\b0 \
fs17 also}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 1-7.}{\b0 \fs17 The}{
\b0 \fs17 hexadecimal}{\b0 \fs17 equivalents}{\b0 \fs17 of}{\b0 \fs17 the }
fi586 {\b0 \fs17 decimal}{\b0 \fs17 numbers}{\b0 \fs17 are}{\b0 \fs17 as}{\
b0 \fs17 follows: }\par
}
\cf0 (a){\i0 \f20 \fs17
8,,=8,, }
{\i0 \f20 \fs17 (6)}{\i0 \f20 \fs16
l}{\i0 \f20 \fs16 O}{\i0 \f20 \fs16 l}
{\i0 \f20 \fs16 0}{\i0 \fs13 =}{\b\i0 \f20 \fs17 A,, }\par
}
\cf0 (c){\i0 \fs17
141,=El, }
{\b \f10 \fs16 (}{\b \f10 \fs16 d}{\b \f10 \fs16 )}{\i0 \fs17
16,,}{\i0\dn
006 \f10 \fs11
=}{\i0 \fs17 10,, }\par
}
fs17 \cf0 ( e ){\b0\i0 \fs17
8Ol,=5O1, }
0 {\b0 \f10 \fs15 (}{\b0 \f10 \fs15 f}{\b0 \f10 \fs15 )}{\b0\i0
25601,}{\
b0\i0 \f10 \fs11 =}{\i0 \f10 \fs16 AOO,, }\par
}
{\f20 \fs15 g }\par
}
3000{\f10 \fs13
=} BB8 \par
}
fs17 \cf0 ( h ){\b0\i0 \fs17
625001,,}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17 F42
4,, }\par
}
\cf0 1.20{\b0 \fs19
9 decimal}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 hexa
decimal}{\b0 \fs19 equivalents: }
\fi586 {\b0\i \f10 \fs16 (a)}{\b0 \fs19
204.125,}{\b0\i \fs19
(b)}{\b0 \fs
19
255.875,}{\b0 \fs18
(c)}{\b0 \fs19
631.25,}{\b0\i \f10 \fs18
(}{
\b0\i \f10 \fs18 d}{\b0\i \f10 \fs18 )}{\b0 \fs19
10000.00390625. }
\fi594 {\fs17 Solution: }
\fi950 {\b0 \fs17 Follow}{\b0 \fs17 the}{\b0 \fs17 procedure}{\b0 \fs17 sho
wn}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 1-9b.}{\b0 \fs17 Refer}{\b0 \f
s17 also}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 1-7.}{\b0 \fs17 The}{\
b0 \fs17 hexadecimal}{\b0 \fs17 equivalents}{\b0 \fs17 of}{\b0 \fs17 the }
\fi590 {\b0 \fs17 decimal}{\b0 \fs17 numbers}{\b0 \fs17 are}{\b0 \fs17 as}{
\b0 \fs17 follows: }\par
}
fs14 \cf0 ( a ){\b0\i0 \f20 \fs17
204.1251,, }{\b0\i0\dn006 \fs11 =}{\b0\i0
\f20 \fs17 CC.2,, }
0 {\b0 \f20 \fs16 (b)}{\b0\i0 \f20 \fs17
255.875,,,}{\b0\i0 \fs13 =}{\b0\i0
\f20 \fs17 FF.E,, }\par
}
\cf0 ( c ){\i0 \fs17
631.25,, }\par
}
{\f20 \fs17 277.4,, }\par
}
\cf0 ( d ){\i0 \f20 \fs17
10}{\i0 \f20 \fs17 000.003}{\i0 \f20 \fs17 906}
{\i0 \f20 \fs17 25,"}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 2710.0116 }\par
}
\cf0 1.21{\b0 \fs19
hexadecimal}{\b0 \fs19 numbers}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 b
inary}{\b0 \fs19 equivalents: }
fi583 {\b0\i \f10 \fs16 (a)}{\fs19
B,}{\b0\i \fs18
(b)}{\b0 \fs19
E,}{
\b0\i \fs19
(c)}{\b0 \fs19
1C,}{\i \fs19
(}{\i \fs19 d}{\i \fs19 )}
A64,{\b0\i \fs19
(}{\b0\i \fs19 e}{\b0\i \fs19 )}{\b0 \fs19
1F.C,}{\b0
\fs23
If)}{\b0 \fs19
239.4 }\par
}
par
}
MBERS USED{\fs17 IN} DIGITAL ELECTRONICS \par
}

AP.{\fs16 1 }\par
}
\cf0 Solution:
fi360 {\b0 \fs18 Follow}{\b0 \fs16 the}{\b0 \fs18 procedure}{\b0 \fs18 shown}
{\b0 \fs17 in}{\b0 \fs18 Fig.}{\b0 1-10a}{\b0 \fs18 and}{\b0\i \fs16 b.}{
\b0 \fs18 Refer}{\b0 \fs18 also}{\b0 \fs16 to}{\b0 \fs18 Fig.}{\b0 1-7.}{\b
0 \fs18 The}{\b0 \fs18 binary}{\b0 \fs18 equivalentsof}{\b0 \fs18 the }
\b0 \fs18 hexadecimal}{\b0 \fs18 numbers}{\b0 \fs18 are}{\b0 \fs18 as}{\b0 \f
s18 follows: }\par
}
10 \cf0 ( U ) \par
}
{\phpg\posx1859\pvpg\posy2073\absw938\absh211 \f20 \fs17 \cf0 \f20 \fs17 \cf0 B,
,{\f10 \fs11
=}{\fs18 1011, }\par
}
cf0 (c) \par
}
{\phpg\posx3547\pvpg\posy2073\absw1073\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 l
C,,{\f10 \fs13 =}{\fs16 11100, }\par
}
\cf0 (b){\i0 \fs18 E,,}{\i0 \f10 \fs13 =}{\i0 \fs16 1110,}{\b \fs16
(}{\b \fs16 d}{\b \fs16 )}{\i0 \fs18 A64,,}{\i0\dn006 \f10 \fs11 =}{\i0
\fs18 101001100100, }\par
}
14 \cf0 ( e )
{\b0 \fs14 (}{\b0 \fs14 f}{\b0 \fs14 ) }\par
}
F.C,,{\f10 \fs11 =} 11111.11,
1 239.4,,{\f10 \fs11 =} 1000111001.01, \par
}
cf0 1.22{\b0 \fs18
binary}{\b0 \fs18 numbers}{\b0 \fs18 to}{\b0 \fs18 their}{\b0 \fs18 hexade
cimal}{\b0 \fs18 equivalents: }\par
}
\cf0 ( a ){\i0 \fs18
1001.1111 }
\fs18 (b)}{\i0 \fs18
10000001.1101 }
\b\i0 \fs16 Solution: }\par
}
\cf0 ( c ){\i0 \f20 \fs18
110101.O11001 }
\fs18 (}{\fs18 d}{\fs18 )}{\i0 \f20 \fs18
10000.1 }\par
}
\cf0 ( e ){\i0 \fs18
IOIOOI11.I1101}{\i0 \fs18 1 }

\i0 \f10 \fs16 (}{\f10 \fs18 f}{\i0 \f10 \fs15 )}{\i0 \fs18
1000000.000011}
{\i0 \fs18 1 }\par
}
\cf0 Follow the procedure shown{\fs16 in} Fig.{\fs16 1-1Oc} and{\b\i \f10 \fs
15 d.} Refer{\fs16 also}{\i \fs17 to} Fig. 1-7.The hexadecimal equivalents
\par}{\phpg\posx1449\pvpg\posy4213\absw8905\absh410 \sl-222 \f20 \fs18 \cf0 of t
he binary numbers are as follows: \par
}
10 \cf0 ( U ) \par
}
001.11112{\dn006 \f10 \fs13 =} 9.F1, \par
}
cf0 (c) \par
}
10101.011001,{\f10 \fs13 =}{\fs18 35-64,, }\par
}
\cf0 (b){\i0 \fs18
10000001.1101,}{\i0\dn006 \f10 \fs11 =}{\i0 \fs17 81.D,,
}{\f10 \fs16
(}{\f10 \fs16 d}{\f10 \fs16 )}{\i0 \fs16
10000.1,}{\i
0 \f10 \fs13 =}{\i0 10.8,, }\par
}
14 \cf0 ( e )
{\b0 \fs14 (J') }\par
}
0100111.111011,{\dn006 \f10 \fs13 =} A'I.EC,,
6 1000000.0000111,{\dn006 \f10 \fs11 =}{\b \fs16 40.0E1, }\par
}
\cf0 1-4{\f10 \fs17
2s} COMPLEMENT NUMBERS
fi362 {\b0 The}{\b0 2s}{\b0 complement}{\b0 method}{\b0 of}{\b0 repres
enting}{\b0 numbers}{\b0 is}{\b0 widely}{\b0 used}{\b0 in}{\b0 micro
processor-based }
\b0 equipment.}{\b0 Until}{\b0 now,}{\b0 we}{\b0 have}{\b0 assumed}{\b0 th
at}{\b0 all}{\b0 numbers}{\b0 are}{\b0 positive.}{\b0 However,}{\b0 microp
rocessors}{\b0 must }
\b0 process}{\b0 both}{\b0 positive}{\b0 and}{\b0 negative}{\b0 numbers.}{\
b0 By}{\b0 using}{\b0 2s}{\b0\i \fs18 complement}{\b0\i \fs18 representati
on,}{\b0 the}{\b0\i \fs18 sign}{\b0\i \fs18 as}{\b0\i \fs18 well}{\b0\i \fs1
8 as }
\b0\i \fs18 the}{\b0\i \fs18 magnitude}{\b0 of}{\b0 a}{\b0 number}{\b0 can}
{\b0 be}{\b0 determined. }
fi360 {\b0 Assume}{\b0 \fs18 a}{\b0 microprocessor}{\b0
register}{\b0 \fs
18 8}{\b0 bits}{\b0 wide}{\b0 such}{\b0 as}{\b0 that}{\b0 shown}{\
b0 in}{\b0 \fs18 Fig.}{\b0 1-llu.}{\b0 The}{\b0 most- }
\b0 significant}{\b0 bit}{\fs19 (MSB)}{\b0 is}{\b0 the}{\b0\i \fs18 sign}

{\b0\i \fs18 bit.}{\b0 If}{\b0 this}{\b0 bit}{\b0 is}{\b0 \fs18 0,}{\b0
then}{\b0 the}{\b0 number}{\b0 is}{\b0 \f10 \fs16 (+)}{\b0 positive.}{
\b0 However,}{\b0 if}{\b0 the }
\b0 sign}{\b0 bit}{\b0 is}{\b0 \fs19 1,}{\b0 then}{\b0 the}{\b0 numbe
r}{\b0 is}{\b0 \f10 \fs16 (-)}{\b0
negative.}{\b0 The}{\b0 other}{\b0
\fs19 7}{\b0 bits}{\b0 in}{\b0 this}{\b0 8-bit}{\b0 register}{\b0
represent }
\b0 the}{\b0 magnitude}{\b0 \fs18 of}{\b0 the}{\b0 number. }
fi366 {\b0 The}{\b0 table}{\b0 in}{\b0 Fig.}{\b0 1-llb}{\b0 shows}{\b0 th
e}{\b0 2s}{\b0 complement}{\b0 representations}{\b0 for}{\b0 some}{\b0 pos
itive}{\b0 and}{\b0 negative }
\b0 numbers.}{\b0 For}{\b0 instance,}{\b0 a}{\b0 \f10 \fs28 +}{\b0 127}{\
b0 is}{\b0 represented}{\b0 by}{\b0 the}{\b0 \fs19 2s}{\b0 complement}{
\b0 number}{\b0 01111111.}{\f10 \fs17 A}{\b0 decimal }
fi42 {\b0 \f10 \fs19 -}{\b0 128}{\b0 is}{\b0 represented}{\b0 by}{\b0 the}{
\b0 \fs19 2s}{\b0 complement}{\b0 number}{\b0 10000000.}{\b0 Note}{\b0 tha
t}{\b0\i \fs18 the}{\b0 \fs18 2s}{\b0\i \fs18 complement}{\b0\i \fs18 repre
senta- }
\b0\i \fs18 tions}{\b0 \fs18 for}{\b0\i \fs18 allpositiiie}{\b0\i \fs18 ualue
s}{\b0\i \fs18 are}{\b0\i \fs18 the}{\b0\i \fs18 same}{\b0\i \fs18 as}{\b0\i
\fs18 the}{\b0\i \fs18 binary}{\b0\i \fs18 equivalents}{\b0 for}{\b0 that
}{\b0 decimal}{\b0 number. }
fi370 {\b0 Convert}{\b0 the}{\b0 signed}{\b0 decimal}{\b0 -1}{\b0
to}
{\b0 a}{\b0 2s}{\b0 complement}{\b0 number.}{\b0 Follow}{\b0 Fig.}{\b
0 1-12}{\b0 as}{\b0 \fs17 you}{\b0 make}{\b0 the }
\b0 conversion}{\b0 in}{\b0 the}{\b0 next}{\b0 five}{\b0 steps. }
f0 \fi370 {\b0 Step}{\b0 1.}{\b0
Separate}{\b0 the}{\b0 sign}{\b0 and}{\b
0 magnitude}{\b0 part}{\b0 \fs18 of}{\b0 \f10 \fs15
-}{\b0 1.}{\b0 The}{
\b0 negative}{\b0 sign}{\b0 means}{\b0 the}{\b0 sign}{\b0 bit}{\b0 will}{
\b0 be }
fi1176 {\b0 1}{\b0 in}{\b0 the}{\b0 2s}{\b0 complement}{\b0 representation.
}
fi370 {\b0 Step}{\b0 2.}{\b0
Convert}{\b0 decimal} 1{\b0 to}{\b0 i
ts}{\b0 7-bit}{\b0 binary}{\b0 equivalent.}{\b0 In}{\b0 this}{\b0 ex
ample}{\b0 decimal}{\b0 1}{\b0 equals }
fi1158 {\b0 0000001}{\b0 in}{\b0 binary. }
fi366 {\b0 Step}{\fs18 3.}{\b0
Convert}{\b0 binary}{\b0 0000001}{\b0
to}{\b0 its}{\b0 \fs19 Is}{\b0 complement}{\b0 form.}{\b0 In}{\b0 th
is}{\b0 example}{\b0 binary}{\b0 0000001 }
fi1158 {\b0 equals}{\b0 1111110}{\b0 in}{\b0 \fs18 Is}{\b0 complement.}{\b0
Note}{\b0 that}{\b0 each}{\b0 \fs18 0}{\b0 is}{\b0 changed}{\b0 to}{\b0
a}{\b0 1}{\b0 and}{\b0 each}{\b0 1}{\b0 to}{\b0 a}{\b0 \fs18 0. }
fi366 {\b0 Step} 4.{\b0
Convert}{\b0 the}{\b0 1s}{\b0 complement}{\b0
to}{\b0 its}{\b0 \fs19 2s}{\b0 complement}{\b0 form.}{\b0 In}{\b0 this}{\
b0 example}{\b0 1s}{\b0 complement }

fi1174 {\b0 1111110}{\b0 equals}{\b0 111111}{\b0 1}{\b0 in}{\b0 2s}{\b0 comp
lement.}{\b0 Add}{\b0 \f10 \fs27 +}{\b0 \fs18 1}{\b0 to}{\b0 the}{\b0 1s}
{\b0 complement}{\b0 to}{\b0 get}{\b0 the}{\b0 2s }
fi1158 {\b0 complement}{\b0 number. }
fi366 {\b0 Step}{\b0 \fs19 5.}{\b0
The}{\b0 7-bit} 2s{\b0 complement}{\b0
number}{\b0 (1}{\b0 111111}{\b0 in}{\b0 this}{\b0 example)}{\b0 becomes}{\
b0 the}{\b0 magnitude}{\b0 part }
fi1158 {\b0 \fs19 of}{\b0 the}{\b0 entire}{\b0 8-bit}{\b0 2s}{\b0 complemen
t}{\b0 number. }
f0 {\b0 The}{\b0 result}{\b0 is}{\b0 that}{\b0 the}{\b0 signed}{\b0
decimal}{\b0 \f10 \fs15
-}{\b0 1}{\b0 equals}{\b0 111111}{\b0 \fs18 11}{\
b0 in}{\b0 2s}{\b0 complement}{\b0 notation.}{\b0 The}{\b0 2s }
\b0 complement}{\b0 number}{\b0 is}{\b0 shown}{\b0 in}{\b0 the}{\b0 regist
er}{\b0 near}{\b0 the}{\b0 top}{\b0 \fs19 of}{\b0 Fig.}{\b0 1-12. }\par
}
0 CHAP.{\b0 \fs16 11 }\par
}
MBERS USED{\fs17 IN}{\fs17 DIGITAL}{\fs17 ELECTRONICS }\par
}
\par
}
20 \fs16 \cf0 Fig. 1-11
cf0 \fi360 {\b0 \fs18 Reverse}{\b0 \fs18 the}{\b0 \fs18 process}{\b0 \fs18 an
d}{\b0 \fs18 convert}{\b0 \fs18 the}{\b0 \fs19 2s}{\b0 \fs18 complement}{\b0
\fs18 11111000to}{\b0 \fs18 a}{\b0 \fs18 signed}{\b0 \fs18 decimal}{\b0 \f
s18 number.}{\b0 \fs18 Follow }
{\b0 \fs18 Fig.}{\b0 \fs18 1-13}{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 conv
ersion}{\b0 \fs18 is}{\b0 \fs18 made}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs1
8 following}{\b0 \fs18 four}{\b0 \fs18 steps. }
\fi382 {\b0 \fs18 Step}{\b0 \fs18 1.}{\b0 \fs18
Separate}{\b0 \fs18 the}{\b
0 \fs18 sign}{\b0 \fs18 bit}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 magni
tude}{\b0 \fs18 part}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs19 2s}{\b0 \fs18
complement}{\b0 \fs18 number.}{\b0 \fs18 The}{\b0 \fs19 MSB }
\fi1174 {\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 1;}{\b0 \fs18 therefore,}{\b0 \f
s18 the}{\b0 \fs18 sign}{\b0 \fs18 of}{\b0 \fs18 decimal}{\b0 \fs18 numb
er}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \f10 \fs16 (-)}{\b0 \fs18 negative.
}
\fi382 {\b0 \fs18 Step}{\b0 \fs18 2.}{\b0 \fs18
Take}{\b0 \fs18 the}{\b0
\fs19 Is}{\b0 \fs18 complement}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18
magnitude}{\b0 \fs18 part.}{\b0 \fs18 The}{\b0 \fs18 7-bit}{\b0 \fs18 m
agnitude}{\b0 \fs18 1111000}{\b0 \fs18 equals }
\fi1170 {\b0 \fs18 0000111}{\b0 \fs18 in}{\b0 \fs19 Is}{\b0 \fs18 complement
}{\b0 \fs18 notation. }
\fi382 {\b0 \fs18 Step}{\b0 \fs19 3.}{\fs19
Add}{\b0 \f10 \fs29 +}{\b0 \fs1
8 1}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs19 Is}{\b0 \fs18 complement}{\b0 \f
s18 number.}{\b0 \fs18 Adding}{\b0 \fs18 0000111}{\b0 \fs18 to}{\b0 \fs19 1
}{\b0 \fs18 gives}{\b0 \fs18 us}{\b0 \fs19 0001000.}{\b0 \fs18 The}{\b0 \fs18
7-bit }
\fi1174 {\b0 \fs18 number}{\b0 \fs18 0001000}{\b0 \fs18 is}{\b0 \fs18 now}{\b
0 \fs18 in}{\b0 \fs18 binary. }\par
}
par
}
}
AP.{\fs17 1 }\par
}
0 \fs16 \cf0 Fig.{\f30 \fs17 1-12}{\b0 \fs17 Converting}{\b0 \fs17 a}{\b0 \f
s17 signed}{\b0 \fs17 decimal}{\b0 \fs17 number}{\b0 \fs17 to}{\b0 \fs17 a}
{\b0 \fs17 2s}{\b0 \fs17 complement}{\b0 \fs17 number }
f0 \fi360 {\b0 \fs19 Step}{\b0 \fs18 4.}{\b0 \fs19
Convert}{\b0 \fs19 th
e}{\b0 \fs19 binary}{\b0 \fs19 number}{\b0 \fs19 to}{\b0 \fs19 its}{\b0 \
fs19 decimal}{\b0 \fs19 equivalent.}{\b0 \fs19 In}{\b0 \fs19 this}{\b0 \
fs19 example,}{\b0 \fs19 binary}{\b0 \fs19 0001000 }
fi1155 {\b0 \fs19 equals}{\b0 \fs19 8}{\b0 \fs19 in}{\b0 \fs19 decimal}{\b0 \
fs19 notation.}{\b0 \fs19 The}{\b0 \fs19 magnitude}{\b0 \fs19 part}{\b0 \fs
18 of}{\b0 \fs19 the}{\b0 \fs19 number}{\b0 \fs19 is}{\b0 \fs19 8. }
f0 \fi356 {\b0 \fs19 The}{\b0 \fs19 procedure}{\b0 \fs19 in}{\b0 \fs19 Fig
.}{\b0 \fs19 1-13}{\b0 \fs19 shows}{\b0 \fs19 how}{\b0 \fs19 to}{\b0 \fs1
9 convert}{\b0 \fs19 2s}{\b0 \fs19 complement}{\b0 \fs19 notation}{\b0 \
fs19 to}{\b0 \fs19 negative}{\b0 \fs19 signed }
\b0 \fs19 decimal}{\b0 \fs19 numbers.}{\b0 \fs19 In}{\b0 \fs19 this}{\b0 \fs1
9 example,}{\b0 \fs19 2s}{\b0 \fs19 complement}{\b0 \fs19 11111000equals}{\
b0 \f10 \fs15
-}{\b0 \fs19 8}{\b0 \fs19 in}{\b0 \fs19 decimal}{\b0 \fs19 n
otation. }
fi362 {\b0 \fs19 Regular}{\b0 \fs19 binary-to-decimal}{\b0 \fs19 conversion}{
\b0 \fs19 (see}{\b0 \fs19 Fig.}{\b0 \fs19 1-4)}{\b0 \fs19 is}{\b0 \fs19 use
d}{\b0 \fs19 to}{\b0 \fs19 convert}{\b0 \fs19 2s}{\b0 \fs19 complements}{\b
0 \fs19 that}{\b0 \fs19 equal }
\b0 \fs19 positive}{\b0 \fs19 decimal}{\b0 \fs19 numbers.}{\b0 \fs19 Rememb
er}{\b0 \fs19 that,}{\b0 \fs19 for}{\b0 \fs19 positive}{\b0 \fs19 decimal}
{\b0 \fs19 numbers,}{\b0 \fs19 the}{\b0 \fs19 binary}{\b0 \fs19 and}{\b0 \
fs19 2s}{\b0 \fs19 comple- }
\b0 \fs19 ment}{\b0 \fs19 equivalents}{\b0 \fs19 are}{\b0 \fs19 the}{\b0 \fs1
9 same. }\par
}

\cf0 Fig.{\fs17 1-13}{\b0 \fs17
Converting}{\b0 \fs17 a}{\fs17 2s}{\b0 \
fs17 complement}{\b0 \fs17 number}{\b0 \fs17 to}{\b0 \fs17 a}{\b0 \fs17
signed}{\b0 \fs17 decimal}{\b0 \fs17 number }\par
}
.{\fs17 11 }\par
}
}
\par
}
{\phpg\posx845\pvpg\posy1345\absw1753\absh199 \f10 \fs17 \cf0 \f10 \fs17 \cf0 SO
LVED{\b \fs16 PROBLEMS }\par
}
cf0 1.23{\b0 \fs19
The }\par
}
\fs19 \cf0 (LSB,{\fs19 MSB)}{\b0 \fs19 of}{\b0 a}{\b0 2s}{\b0 complement}{
\b0 number}{\b0 is}{\b0 the}{\b0 sign}{\b0 bit. }
\b0 \fs17 The}{\b0 \fs17 MSB}{\b0 \fs17 (most-significant}{\b0 \fs17 bit)}{
\b0 \fs17 of}{\b0 \fs17 a}{\b0 \fs17 2s}{\b0 \fs17 complement}{\b0 \fs17
number}{\b0 \fs17 is}{\b0 \fs17 the}{\b0 \fs17 sign}{\b0 \fs17 bit. }\par
}
cf0 1.24{\b0 \fs19
The}{\b0 \fs19 2s}{\b0 \fs19 complement}{\b0 \fs19 num
ber}{\b0 \fs19 10000000is}{\b0 \fs19 equal}{\b0 \fs19 to }
i592 {\fs17 Solution: }\par
}
{\phpg\posx6513\pvpg\posy2858\absw1583\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 i
n signed decimal. \par
}
\cf0 Follow the procedure shown in Fig. 1-13. The 2s complement number
10000000 equals -128 in
\par}{\phpg\posx1443\pvpg\posy3489\absw8228\absh394 \sl-223 \f20 \fs17 \cf0 deci
mal. \par
}
cf0 1.25{\b0 \fs19
The}{\b0 \fs19 number}{\b0 \fs19 01110000}{\b0 \fs19
is}{\b0 \fs19 equal}{\b0 \fs19 to }
}
}
\cf0 The{\fs16 0} in the MSB position means this is a positive numb
er, and conversion to decimal follows the
\par}{\phpg\posx1443\pvpg\posy5231\absw8231\absh409 \sl-236 \f20 \fs17 \cf0 rule
s used in binary-to-decimal conversion. The number 01110000 is equal to{
\f10 \fs26 +} 112 in signed decimal. \par
}
cf0 1.26{\b0 \fs19
The}{\b0 \fs19 signed}{\b0 \fs19 decimal}{\b0 \fs19 nu
mber}{\b0 \fs19 +75}{\b0 \fs19 equals }
}
n %bit 2s complement. \par
}
ollow the procedure shown in Fig. 1-4. Decimal +75 equals 01001011 in 2s comp
lement and binary. \par
}
cf0 1.27{\b0 \fs19
The}{\b0 \fs19 2s}{\b0 \fs19 complement}{\b0 \fs19 num
ber}{\b0 \fs19 11110001is}{\b0 \fs19 equal}{\b0 \fs19 to }
}
}
\cf0 Follow the procedure shown in Fig. 1-13. The 2s complement number
11110001 is equal to{\f10 \fs15 -} 15 in
\par}{\phpg\posx1435\pvpg\posy8493\absw8228\absh387 \sl-215 \f20 \fs17 \cf0 sign
ed decimal. \par
}
cf0 1.28{\b0 \fs19
The}{\b0 \fs19 signed}{\b0 \fs19 decimal}{\b0 \fs19 nu
mber}{\b0 \fs19 -35}{\b0 \fs19 equals }
}
n 8-bit 2s complement. \par
}
Follow the procedure shown{\fs17 in} Fig. 1-12. Decimal -35 equals 110
11101 in 2s complement. \par
}
\cf0 1.29{\b0 \fs19
The}{\b0 \fs19 signed}{\b0 \fs19 decimal}{\b0 \fs19 n
umber}{\b0 \f10 \fs15
-}{\b0 \fs19 100}{\b0 \fs19 equals }
}
in 8-bit 2s complement. \par
}
Follow the procedure shown{\fs17 in} Fig. 1-12. Decimal{\f10 \fs19 -} 1
00 equals 10011100 in 2s complement. \par
}
\cf0 1.40{\b0 \fs19
The}{\b0 \fs19 signed}{\b0 \fs19 decimal}{\b0 \fs19 n
umber}{\b0 \fs19 +20}{\b0 \fs19 equals }
}
in 8-bit{\b \fs18 2s} complement. \par
}
Follow the procedure shown in Fig. 1-4. Decimal{\b \fs17 +20} equals 00010
100 in 2s complement and binary \par
}
0 14 \par
}
}
AP. 1 \par
}
upplementary Problems \par
}
The number system with a radix of 2{\b \fs16 is} called the
The number system with a radix of{\fs17 10} is called the
The number system with a radix of{\fs16 8} is called the
The number system with a radix of 16 is called the
A{\b\i binary}{\b\i digit}{\fs17 is} sometimes shortened and called a(
n) \par
}
number system.
\fi93 number system.
number system.
\fi90 number system.
\fi270 {\f10 \fs19 .}{\b\i
Ans.}
bit \par
}
cf0 1.31
0 1.32
0 1.33
0 1.34
0 1.35
0 1.36 \par
}
15 \cf0 Ans. \par
}
{\phpg\posx8265\pvpg\posy1833\absw508\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 bi
nary \par
}
\f20 \fs16 \cf0 Ans.{\b0\i0
decimal }
\cf0 Ans.{\b0\i0
octal }
\cf0 \fi86 Ans.{\b0\i0
hexadecimal }\par
}
\cf0 How would you pronounce the number 1101 in{\i \f10 \fs14 (a)} binary
and{\i \fs16 (}{\i \fs16 b}{\i \fs16 )}decimal?
\par}{\phpg\posx1425\pvpg\posy4113\absw5989\absh793 \sl-215 \f20 \fs16 \cf0 {\b\
i Ans.}{\b\i \fs17
(a)}one, one, zero, one{\i \fs16
(}{\i \fs16 b}{\i
\fs16 )}one thousand one hundred and one
\fi24 The number 1010, is a base{\i \f10 \fs14
(}{\i \f10 \fs14 a}{\i
\f10 \fs14 )}
number and is pronounced{\i \fs16
(}{\i \fs16 b}{
\i \fs16 ) }\par
}
s16 \cf0 Ans.{\fs16
(}{\fs16 a}{\fs16 )}{\b0\i0
2}{\b0\i0 \fs17
(6
)}{\b0\i0 one,}{\b0\i0 zero,}{\b0\i0 one,}{\b0\i0 zero }
\cf0 \fi22 {\b0\i0 Convert}{\b0\i0 the}{\b0\i0 following}{\b0\i0 binary}{\b
0\i0 numbers}{\b0\i0 to}{\b0\i0 their}{\b0\i0 decimal}{\b0\i0 equivale
nts: }
{\b0 \f10 \fs14 (a)}{\b0\i0
00001110,}{\b0 \fs16
(}{\b0 \fs16 b}{\b0 \
fs16 )}{\b0\i0
11100000,}{\fs16
(}{\fs16 c}{\fs16 )}{\b0\i0
100000
11,}{\f10 \fs16
(}{\f10 \fs16 d}{\f10 \fs16 )}{\b0\i0
10011010. }\par
}
s16 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0
00001110,}{\b0\i0\dn006 \f10 \f
s11 =}{\b0\i0 141, }
\fi536 {\b0 \fs16 (b)}{\b0\i0
11100000,}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0
224,, }\par
}
10011.11,{\f10 \fs13 = }
{\fs16 11}{\fs16 110000.001}{\fs16 1,}{\f10 \fs13 = }\par
}
s16 \cf0 ( c ){\b0\i0 \fs16
10000011,}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs16
13lIo }
{\b0 \f10 \fs16 (d)}{\b0\i0 \fs16
10011010,}{\b0\i0 \f10 \fs13 =}{\b0\i0
\fs16 I%,,, }\par
}
f0 1.37 \par
}
f0 1.38 \par
}
cf0 1.39
0 1.40
0 1.41 \par
}
s16 \cf0 Ans.{\b0\i0
51.75 }
\cf0 \fi357 Ans.{\b0\i0
240.1875 }\par
}
{\phpg\posx1443\pvpg\posy7475\absw5291\absh387 \f20 \fs16 \cf0 \f20 \fs16 \cf0 C
onver: the following decimal numbers to their binary equivalents:
\f10 \fs14 (a)}
32,{\fs17
(6)}
200,{\b\i \fs16
(}{\b\i \fs16 c}{\
b\i \fs16 )}
170,{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 d}{\b\i \f10 \fs16
)}
258. \par
}
s16 \cf0 Ans.{\fs16
(}{\fs16 a}{\fs16 )}{\b0\i0
32,,}{\b0\i0\dn006 \f10
\fs11
=}{\b0\i0 \fs17 100000, }
\fi534 {\b0 \fs16 (b)}{\b0\i0
2001,}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 11
001000, }\par
}
.875,,
\par}{\phpg\posx1447\pvpg\posy8587\absw719\absh599 \sl-227 \par\f20 \fs16 \cf0 9
99.125,, \par
}
\par
}
{\phpg\posx2915\pvpg\posy8420\absw150\absh379 \f10 \fs32 \cf0 \f10 \fs32 \cf0 ,
\par
}
s16 \cf0 ( c ){\b0\i0 \fs16
170,,,}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 \fs16
10101010, }
{\b0 \f10 (}{\b0 \f10 d}{\b0 \f10 )}{\b0\i0 \fs16
258,,,}{\b0\i0 \f10 \fs
13 =}{\b0\i0 \fs16 100000010, }\par
}
cf0 1.42
0 1.43
0 1.44 \par
}
\par
}
101000.11}{\b0\i0 1 }
\cf0 \fi88 {\fs17 Ans.}{\b0\i0
1111100111.001 }\par
}
onvert the following hexadecimal numbers to their decimal equivalents:

\f10 \fs14 (a)}
13AF,{\fs17
(6)}
25E6,{\i \fs17
(}{\i \fs17 c}{\i
\fs17 )} B4.C9,{\i \f10 \fs16
(d)}
78.D3. \par
}
s16 \cf0 Ans.{\b0 \f10 \fs13
(a)}{\b0\i0
13AE1,}{\b0\i0\dn006 \f10 \fs1
1 =}{\b0\i0 5039,(, }
\fi531 {\b0\i0 \fs17 (6)}{\b0\i0
25E6,,}{\b0\i0 \f10 \fs13 =}{\b0\i0 970
2," }\par
}
\cf0 (c){\i0 \fs16
B4.C91,}{\i0\dn006 \f10 \fs10 =}{\i0 \fs16 180.78515,,,
}
\f10 (}{\f10 d}{\f10 )}{\i0 \fs16
78.D3,,}{\i0\dn006 \f10 \fs11
=}{\i0
\fs16 120.82421}{\b\i0 \fs14 1o }\par
}
cf0 1.45 \par
}
Convert the following decimal numbers to their hexadecimal equivalents:
\f10 \fs15 (a)}
3016,{\i \fs17
(b)} 64881,{\i \fs17
(c)}
17386.
75,{\i \f10 \fs16
(d)}
9817.625. \par
}
fs16 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0
3016,"}{\b0\i0 \f10 \fs14 =}
{\b0\i0 BC8,, }
0 \fi536 {\b0\i0 \fs17 (6)}{\b0\i0
64881,,}{\b0\i0\dn006 \f10 \fs11
=}{\b
0\i0 FD71,, }\par
}
\cf0 ( c ){\i0 \fs16
17386.75,,,}{\i0\dn006 \f10 \fs11 =}{\i0 \fs16 43EA.
C,, }
{\b \f10 \fs16 (}{\b \f10 \fs16 d}{\b \f10 \fs16 )}{\i0 \fs16
9817.625,,,}
{\i0\dn006 \f10 \fs11 =}{\i0 \fs16 2659.A,, }\par
}
cf0 1.46 \par
}
Convert the following hexadecimal numbers to their binary equivalents:
\f10 \fs14 (a)}
A6,{\i \fs16
(b)}
19,{\i \fs16
(c)}
E5.04,{\i
\f10 \fs16
(d)}
1B.78. \par
}
fs16 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0
A616}{\b0\i0\dn006 \f10 \fs11
=}{\b0\i0 10100110, }
0 \fi537 {\b0 \fs17 (b)}{\b0\i0
1916}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 110
01, }\par
}
\cf0 ( c ){\i0 \fs16
135.04 }\par
}

\cf0 Ih{\b0 \f10 \fs11 =}{\b0 \fs16 11~0010~.00000~ }\par
}
\par
}
\cf0 ( d ){\i0 \f20 \fs16
1B.78,,}{\i0\dn006 \fs11 =}{\i0 \f20 \fs16 110
11.01111, }\par
}
cf0 1.47 \par
}
Convert the following binary numbers to their hexadecimal equivalents:
\f10 \fs14 (a)}
11110010,{\i \fs16
(b)}
11011001,{\i \fs17
(}{\i \f
s17 c}{\i \fs17 )}
111110.000011,{\i \f10 \fs16
(}{\i \f10 \fs16 d}{\i
\f10 \fs16 )}
10001.11111 \par
}
fs16 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0
11110010,}{\b0\i0\dn006 \f10 \
fs11 =}{\i0 \fs17 F2,, }
0 \fi534 {\b0 \fs16 (}{\b0 \fs16 b}{\b0 \fs16 )}{\b0\i0
11011001,}{\b0\i0\d
n006 \f10 \fs11 =}{\b0\i0 D9,, }\par
}
\cf0 (c){\i0 \f20 \fs16
111110.000011,}{\i0 \fs13 =}{\i0 \f20 \fs16 3E.OC
,, }
{\fs16 (}{\fs16 d}{\fs16 )}{\i0 \f20 \fs16
10001.11111,}{\i0\dn006 \fs11
=}{\i0 \f20 \fs16 ll.F8,, }\par
}
.{\fs17 11 }\par
}
MBERS{\fs17 USED} IN{\fs17 DIGITAL}{\fs17 ELECTRONICS }\par
}
\par
}
f0 1.48
\par}{\phpg\posx893\pvpg\posy1364\absw355\absh578 \sl-218 \par\b \f10 \fs15 \cf0
1.49 \par
}
hen{\b \f10 \fs16 2s} complement notation{\fs17 is} used, the{\fs17 MSB}
{\fs17 is} the \par
}
t. \par
}
17 \cf0 Ans.{\b0\i0 \fs17
sign }\par
}

onvert the following signed decimal numbers to their 8-bit{\fs17 2s} com
plement equivalents: \par
}
\fs14 \cf0 (a){\i0 \f20 \fs17
+13,}{\f20 \fs17
(b)}{\i0 \f20 \fs17
+110,}{\b\i0 \f30 \fs17 (c)}{\f20 \fs17
-25,}{\b \f20 \fs17
(}{\b \
f20 \fs17 d}{\b \f20 \fs17 )}{\i0 \f20 \fs17
-90. }
\b \f20 \fs17 Ans.}{\fs15
(a)}{\i0 \f20 \fs17
00001101}{\b \f20 \fs17
(b)}{\i0 \f20 \fs17
01101110}
(c){\i0 \f20 \fs17
11100111 }\par
}
cf0 (Id) \par
}
100110 \par
}
f0 1.50 \par
}
\cf0 Convert the following{\b \fs17 2s} complement numbers to their sign
ed decimal equivalents:
4 {\i \f10 \fs15 (a)}{\fs17
01110000,}{\i \fs16
(b)}{\fs17
00011111,}
{\i \f10 \fs15
(c)}{\fs17
11011001,}{\i \f10
(d)}{\fs17
11001000
. }
i \fs17 Ans.}{\i \f10 \fs15
(a)}{\fs17
+112}{\i \fs17
(b)}{\fs17
+31}{\i \f10 \fs14
(}{\i \f10 \fs14 c}{\i \f10 \fs14 )}{\fs17
-39}{
\i \f10 \fs16
(d)}{\fs17
-56 }\par
}
{\phpg\posx7067\pvpg\posy708\absw3101\absh649 \f10 \fs55 \cf0 \f10 \fs55 \cf0 Ch
apter{\fs52 2 }\par
}
\cf0 2-1{\fs18
INTRODUCTION }
f0 {\b0 \fs18 bistable}{\b0 \fs18 nature}{\b0 of}{\b0 \fs18 digital}{\b0 \fs1
8 electronic}{\b0 \fs18 circuits.}{\b0 \fs18 The}{\b0 \fs18 straight}{\b0 \f
s18 binary}{\b0 \fs18 code}{\b0 \fs18 was}{\b0 \fs18 discussed}{\b0 \fs18 i
n}{\b0 \fs18 Chap.}{\b0 \fs18 1.}{\b0 \fs18 Several }
\b0 \fs18 other,}{\b0 \fs18 special}{\b0 \fs18 binary}{\b0 \fs18 codes}{\b
0 \fs18 have}{\b0 \fs18 evolved}{\b0 \fs18 over}{\b0 \fs18 the}{\b0 \fs1
8 years}{\b0 \fs18 to}{\b0 \fs18 perform}{\b0 \fs18 specific}{\b0 \fs18
functions}{\b0 \fs18 in}{\b0 \fs18 digital }
\b0 \fs18 equipment.}{\b0 \fs18 All}{\b0 \fs18 those}{\b0 \fs18 codes}{\b0 \
fs18 use} OS{\b0 \fs18 and}{\b0 \fs18 Is,}{\b0 \fs18 but}{\b0 \fs18 their
}{\b0 \fs18 meanings}{\b0 \fs18 may}{\b0 \fs18 vary.}{\b0 \fs18 Several}{\b
0 \fs18 binary}{\b0 \fs18 codes}{\b0 will}{\b0 \fs18 be }
\b0 \fs18 detailed}{\b0 \fs18 here,}{\b0 \fs18 along}{\b0 \fs18 with}{\b0 \
fs18 the}{\b0 \fs18 methods}{\b0 \fs18 used}{\b0 \fs18 to}{\b0 \fs18 tra
nslate}{\b0 \fs18 them}{\b0 \fs18 into}{\b0 \fs18 decimal}{\b0 \fs18 form
.}{\b0 \fs18 In}{\b0 \fs18 a}{\b0 \fs18 digital}{\b0 \fs18 system, }

\b0 \fs18 electronic}{\b0 \fs18 translators}{\b0 \fs18 (called}{\b0\i \fs18
encoders}{\b0 \fs18 and}{\b0\i \fs18 decoders)}{\b0 \fs18 are}{\b0 \fs18 u
sed}{\b0 \fs18 for}{\b0 \fs18 converting}{\b0 \fs18 from}{\b0 \fs18 code}{\
b0 \fs18 to}{\b0 \fs18 code.}{\b0 \fs18 The }
\b0 \fs18 following}{\b0 \fs18 sections}{\b0 \fs18 will}{\b0 \fs18 detail}{\b
0 \fs18 the}{\b0 \fs18 process}{\b0 \fs18 of}{\b0 \fs18 conversion}{\b0 \fs1
8 from}{\b0 \fs18 one}{\b0 \fs18 code}{\b0 \fs18 to}{\b0 \fs18 another. }
f0 {\fs18 2-2}{\fs18
WEIGHTED}{\fs18 BINARY}{\fs18 CODES }
fi370 {\b0 \fs18 Straight}{\b0 \fs18 binary}{\b0 \fs18 numbers}{\b0 \fs18
are}{\b0 \fs18 somewhat}{\b0 \fs18 difficult}{\b0 \fs18 for}{\b0 \fs18 pe
ople}{\b0 \fs18 to}{\b0 \fs18 understand.}{\b0 \fs18 For}{\b0 \fs18 inst
ance,}{\b0 \fs18 try}{\b0 \fs18 to }\par
}
{\phpg\posx847\pvpg\posy5771\absw7802\absh419 \f20 \fs18 \cf0 \f20 \fs18 \cf0 co
nvert the binary number 10010110, to a decimal number. It turns out that 10010
110,{\dn006 \f10 \fs13 = }
\par}{\phpg\posx847\pvpg\posy5771\absw7802\absh419 \sl-231 \f20 \fs18 \cf0 takes
quite a lot of time and effort to make this conversion without a calculator. \
par
}
501,,,but it \par
}
10 \fs33 \cf0 Binary Codes
\par}{\phpg\posx1203\pvpg\posy2012\absw8800\absh1241 \sl-326 \par\par\b \f10 \fs
33 \cf0 {\b0 \f20 \fs18 Digital}{\b0 \f20 \fs18 systems}{\b0 \f20 \fs18 proc
ess}{\b0 \f20 \fs18 only}{\b0 \f20 \fs18 codes}{\b0 \f20 \fs18 consisting}
{\b0 \f20 \fs18 of}{\f20 \fs18 OS}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 1s
}{\b0 \f20 \fs18 (binary}{\b0 \f20 \fs18 codes).}{\b0 \f20 \fs18 That}{\b0
\f20 \fs18 is}{\b0 \f20 \fs18 due}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the
}\par
}
\cf0 The{\i binary-coded}{\i decimal} (BCD){\i code} makes conversion
to decimals much easier. Figure{\i 2-1 }
s the 4-bit BCD code for the decimal digits 0-9. Note that the BCD code is a wei
ghted code. The
\par}{\phpg\posx835\pvpg\posy6239\absw9393\absh2398 \sl-242 \f20 \fs18 \cf0 most
significant bit,has a weight of 8, and the least significant{\fs18 bit} has a
weight of only 1. This code is
\par}{\phpg\posx835\pvpg\posy6239\absw9393\absh2398 \sl-229 \f20 \fs18 \cf0 more
precisely known as the{\i \fs18 8421}{\i \fs19 BCD}{\i code.} The 8421 part
of the name gives the weighting{\fs18 of} each
\par}{\phpg\posx835\pvpg\posy6239\absw9393\absh2398 \sl-231 \f20 \fs18 \cf0 plac
e in the 4-bit code, There are several other BCD codes that have other weights f
or the four place
\par}{\phpg\posx835\pvpg\posy6239\absw9393\absh2398 \sl-244 \f20 \fs18 \cf0 valu
es. Because the 8421 BCD code is most popular, it is customary to refer to it s
imply as the BCD
\par}{\phpg\posx835\pvpg\posy6239\absw9393\absh2398 \sl-235 \f20 \fs18 \cf0 code
.
\fi4716 {\b \fs16 BC}{\b \fs16 I> }
526 {\fs16 Decimal }

528 {\b \f30 \fs17 8s}{\fs16 4s}{\fs16 2s}{\fs15 Is }\par
}
6 {\fs15 1 }
i \f30 \fs11 7 }
\par}{\phpg\posx4623\pvpg\posy9194\absw146\absh1952 \f20 \fs16 \cf0 {\b\i \f10 \
fs3 I }
16 3 }
16 4 }
\fs16 5 }
15 6 }
16 7 }
16 8 }
15 9 }\par
}
\par}{\phpg\posx5411\pvpg\posy9196\absw110\absh380 \sl-219 \f20 \fs16 \cf0 0 \pa
r
}
r
}
r
}
{\f10 \fs14 1 }\par
}
0{\fs16
I}{\fs16 0 }\par
}
\fs15 0 }
\fs15 0 }\par
}
\fs15 1 }
\fs15 1 }\par
}

1
3 {\f10 \fs15 1}{\fs16 0 }\par
}
0 \fs15 0 }
0 1
3 {\f10 \fs14 1 }
ar
}
0 0 \par
}
\cf0 1
0 \fs16 0 }
15 1 }
0 \fs16 0 }
5 1
0 \fs16 0 }
6 1 \par
}
20 \fs16 \cf0 Fig. 2-1{\b0 \fs16
The}{\fs16 8421}{\b0 \fs17 BCD}{\b0 code
}
cf0 \fi360 {\b0 \fs18 How}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 decimal}{\b
0 \fs18 number}{\b0 \fs19 150}{\b0 \fs18 expressed}{\b0 \fs18 as}{\b0 \fs18
a}{\b0 \fs18 BCD}{\b0 \fs18 number?}{\b0 \fs18 Figure}{\b0\i \fs18 2-2a}{
\b0 \fs18 shows}{\b0 \fs18 the}{\b0 \fs18 very}{\b0 \fs18 simple }
{\b0 \fs18 technique}{\b0 \fs18 for}{\b0 \fs18 converting}{\b0 \fs18 decimal}
{\b0 \fs18 numbers}{\b0 \fs18 to}{\b0 \fs18 BCD}{\b0 \fs18 (8421)}{\b0 \fs18
numbers.}{\b0 \fs18 Each}{\b0 \fs18 decimal}{\b0 \fs18 digit}{\b0 \fs18 is
}{\b0 \fs18 converted}{\b0 \fs18 to }
{\b0 \fs18 its}{\b0 \fs18 4-bit}{\b0 \fs18 BCD}{\b0 \fs18 equivalent}{\b0
\fs18 (see}{\b0 \fs18 Fig.}{\b0\i \fs18 2-1).}{\b0 \fs18 The}{\b0 \fs18
decimal}{\b0 \fs18 number}{\b0 \fs18 150}{\b0 \fs18 then}{\b0 \fs18 equa
ls}{\b0 \fs18 the}{\b0 \fs18 BCD}{\b0 \fs18 number }
{\b0 \fs18 000101}{\b0 \fs18 010000. }
\fi362 {\b0 \fs18 Converting}{\b0 \fs18 BCD}{\b0 \fs18 numbers}{\b0 \fs18
to}{\b0 \fs18 decimal}{\b0 \fs18 numbers}{\b0 \fs18 also}{\b0 \fs18 is}{
\b0 \fs18 quite}{\b0 \fs18 simple.}{\b0 \fs18 Figure}{\b0\i \fs18 2-26}{
\b0 \fs18
shows}{\b0 \fs18 the }

{\b0 \fs18 technique.}{\b0 \fs18 The}{\b0 \fs18 BCD}{\b0 \fs18 number}{\b0 \f
s18 10010110is}{\b0 \fs18 first}{\b0 \fs18 divided}{\b0 \fs18 into}{\b0 \fs1
8 groups}{\b0 \fs18 of}{\b0 \fs18 4}{\b0 \fs18 bits}{\b0 \fs18 starting}{\b
0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs18 point. }
{\b0 \fs18 Each}{\b0 \fs18 group}{\b0 \fs18 of}{\b0 \fs18 4}{\b0 \fs18 bit
s}{\b0 \fs18 is}{\b0 \fs18 then}{\b0 \fs18 converted}{\b0 \fs18 to}{\b0 \fs
18 its}{\b0 \fs18 equivalent}{\b0 \fs18 decimal}{\b0 \fs18 digit,}{\b0 \fs1
8 which}{\b0 \fs18 is}{\b0 \fs18 recorded}{\b0 \fs18 below.}{\b0 \fs18 The
}
{\b0 \fs18 BCD}{\b0 \fs18 number}{\b0 \fs18 10010110}{\b0 \fs18 then}{\b0 \f
s18 equals}{\b0 \fs18 decimal}{\b0 \fs18 96. }
cf0 \fi4328 {\b0 \fs18 16 }\par
}
.{\fs17 21 }\par
}
{\phpg\posx4531\pvpg\posy550\absw1446\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 BI
NARY CODES \par
}
\par
}
cimal
\par}{\phpg\posx1815\pvpg\posy1370\absw644\absh578 \sl-218 \par\f20 \fs16 \cf0 B
CD \par
}
0 ( U ) \par
}
cf0 I
\fs22 1 }\par
}
\fs22 1 }\par
}
\fs22 1 }\par
}
001{\fs16
0101}
0000 \par
}
cimal
CD \par
}
0 1 }\par
}
0 1 1 \par
}
\cf0 2
6 {\fs20 1 }
\fs15 0010 }\par
}
par
}
{\fs20 1 }\par
}
cf0 4
b0 \f20 \fs20 1 }\par
}
{\phpg\posx7803\pvpg\posy1802\absw896\absh186 \f20 \fs16 \cf0 \f20 \fs16 \cf0 lo
o0{\f10 \fs15
0100 }\par
}
ecimal-to-BCD conversion \par
}
c){\f20 \fs14 Fractional}{\f20 \fs14 decimal-to-BCD}{\f20 \fs14 conversion
}\par
}
{\phpg\posx5661\pvpg\posy2582\absw699\absh578 \f20 \fs16 \cf0 \f20 \fs16 \cf0 BC
D
ecima{\f10 \fs15 1 }\par
}
111{\f20 \fs16
0001}{\f20 \fs16
0000}{\f20 \fs16
1000 }\par
}
cf0 0 \par
}
6 7 }\par
}
6 1 }\par
}
par
}
cf0 1
6 0 }\par
}

6 8 }\par
}
D
ecinia{\fs17 I }\par
}
001{\fs16
0110. }\par
}
\fs15 9 }\par
}
cf0 1
\fs15 6 }\par
}
{\phpg\posx4035\pvpg\posy3032\absw110\absh180 \f20 \fs15 \cf0 \f20 \fs15 \cf0 *
\par
}
\cf0 (h){\i0 \fs14 BCII-to-decimal}{\i0 \fs14 conversion }\par
}
s15 \cf0 ( d ){\b0\i0 \fs14 Fractional}{\b0\i0 \fs14 BCD-to-decimal}{\b0\i0 \
fs14 conversion }\par
}
0 \fs16 \cf0 Fig.{\f10 \fs15 2-2 }
f0 \fi366 {\b0 \fs18 Figure}{\b0 \fs18 2-2c}{\b0 \fs18 illustrates}{\b0 \fs18
a}{\b0 \fs18 fractional}{\b0 \fs18 decimal}{\b0 \fs18 number}{\b0 \fs18
being}{\b0 \fs18 converted}{\b0 \fs18 to}{\b0 \fs18 its}{\b0 \fs18 BCD}{\b0
\fs18 equivalent.}{\b0 \fs18 Each }
\b0 \fs18 decimal}{\b0 \fs18 digit}{\b0 \fs18 is}{\b0 \fs18 converted}{\b0 \f
s18 to}{\b0 \fs18 its}{\b0 \fs18 BCD}{\b0 \fs18 equivalent.}{\b0 \fs18 The}
{\b0 \fs18 decimal}{\b0 \fs18 point}{\b0 \fs18 is}{\b0 \fs18 dropped}{\b0 \f
s18 down}{\b0 \fs18 and}{\b0 \fs18 becomes}{\b0 \fs18 the }
\b0 \fs18 binary}{\b0 \fs18 point.}{\b0 \fs18 Figure}{\b0 \fs18 2-2c}{\b0 \fs
18 shows}{\b0 \fs18 that}{\b0 \fs18 decimal}{\b0 \fs18 32.84}{\b0 \fs18 eq
uals}{\b0 \fs18 the}{\b0 \fs18 I3CD}{\b0 \fs18 number}{\b0 \fs18 00110010.10
000100. }
fi360 {\b0 \fs18 Convert}{\b0 \fs18 the}{\b0 \fs18 fractional}{\b0 \fs18 R
CD}{\b0 \fs18 number}{\b0 \fs18 01110001.00001000}{\b0 \fs18 to}{\b0 \fs18
its}{\b0 \fs18 decimal}{\b0 \fs18 equivalent.}{\b0 \fs18 Figure}{\b0 \fs
18 2-2d }
\b0 \fs18 shows}{\b0 \fs18 the}{\b0 \fs18 procedure.}{\b0 \fs18 The}{\b0 \f
s18 BCD}{\b0 \fs18 number}{\b0 \fs18 is}{\b0 \fs18 first}{\b0 \fs18 div
ided}{\b0 \fs18 into}{\b0 \fs18 groups}{\b0 \fs18 of}{\b0 \fs18 4}{\b0 \f
s18 bits}{\b0 \fs18 starting}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 bin
ary }
\b0 \fs18 point.}{\b0 \fs18 Each}{\b0 \fs18 group}{\b0 \fs18 of}{\b0 \fs18
four}{\b0 \fs18 bits}{\b0 \fs18 is}{\b0 \fs18 then}{\b0 \fs18 converted}{
\b0 \fs18 to}{\b0 \fs18 its}{\b0 \fs18 decimal}{\b0 \fs18 equivalent.}{\b0
\fs18 The}{\b0 \fs18 binary}{\b0 \fs18 point}{\b0 \fs18 becomes }
\b0 \fs18 the}{\b0 \fs18 decimal}{\b0 \fs18 point}{\b0 \fs18 in}{\b0 \fs18
the}{\b0 \fs18 decimal}{\b0 \fs18 number.}{\b0 \fs18 Figure}{\b0 \fs18
2-2d}{\b0 \fs18 shows}{\b0 \fs18 the}{\b0 \fs18 BCD}{\b0 \fs18 number}{
\b0 \fs18 01110001.00001000 }
\b0 \fs18 being}{\b0 \fs18 translated}{\b0 \fs18 into}{\b0 \fs18 its}{\b0 \f
s18 decimal}{\b0 \fs18 equivalent}{\b0 \fs18 of}{\b0 \fs18 71.08. }
fi360 {\b0 \fs18 Consider}{\b0 \fs18 converting}{\b0 \fs18 a}{\b0 \fs18 BC
D}{\b0 \fs18 number}{\b0 \fs18 to}{\b0 \fs18 its}{\b0 \fs18 straight}{\b
0 \fs18 binary}{\b0 \fs18 equivalent.}{\b0 \fs18 Figure}{\b0 \fs18 2-3}{
\b0 \fs18 shows}{\b0 \fs18 the }
\b0 \fs18 three-step}{\b0 \fs18 procedure.}{\b0 \fs18 Step}{\b0 \fs19 1}{\
b0 \fs18 shows}{\b0 \fs18 the}{\b0 \fs18 BCD}{\b0 \fs18 number}{\b0 \fs18
being}{\b0 \fs18 diivided}{\b0 \fs18 into}{\b0 \fs18 4-bit}{\b0 \fs18
groups}{\b0 \fs18 starting}{\b0 \fs18 from }
\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs18 point.}{\b0 \fs18 Each}{\b0 \fs18
4-bit}{\b0 \fs18 group}{\b0 \fs18 is}{\b0 \fs18 translated}{\b0 \fs18 into
}{\b0 \fs18 its}{\b0 \fs18 decimal}{\b0 \fs18 e:quivalent.Step}{\b0 \fs18 1}
{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 2-3}{\b0 \fs18 shows}{\b0 \fs18 the
}
\b0 \fs19 BCD}{\b0 \fs18 number}{\b0 \fs18 000100000011.0101}{\b0 \fs18 being
}{\b0 \fs18 translated}{\b0 \fs18 into}{\b0 \fs18 the}{\b0 \fs18 decimal}{\
b0 \fs18 number}{\b0 \fs18 103.5. }\par
}
D
ecima{\fs17 I }\par
}
{\phpg\posx4473\pvpg\posy7362\absw403\absh578 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Oo
ol
6 {\fs21 1 }
2 {\f10 \fs15 1 }\par
}
cf0 oooo
\par}{\phpg\posx5013\pvpg\posy7282\absw874\absh653 \sl-252 \i \f30 \fs25 \cf0 \f
i162 {\i0 \f20 \fs21 1 }
i142 {\i0 \f20 \fs16 0 }\par
}
011{\f10 \fs15
01011 }\par
}
cf0 1
\par}{\phpg\posx5701\pvpg\posy7567\absw187\absh397 \sl-187 \f20 \fs21 \cf0 {\i \
fs16 3 }\par
}

f0 . \par
}
cf0 1
\par}{\phpg\posx6210\pvpg\posy7567\absw225\absh397 \sl-187 \f20 \fs21 \cf0 {\i \
fs16 5 }\par
}
103{\b \f30 \fs13 t}{\fs16 2}{\f10 \fs14 =}{\fs16 51}{\fs16 remainder} o
f{\f10 \fs15 1 }
72 {\fs16 51}{\f10 \fs12 -+}{\fs16 2}{\f10 \fs14 =} 25{\fs16 remainder}{\
fs15 of} I
60 {\i \fs16 25}{\f10 \fs15 -+}{\fs16 2}{\f10 \fs14 =}{\fs16 12}{\fs16
remainder} of{\f10 \fs15 1 }
90 {\fs16 12}{\f10 \fs20 +}{\fs16 2}{\dn006 \f10 \fs14 =}{\b \fs15
6}{\fs
16 remainder} of 0
152 {\fs15 6}{\b \f30 \fs12 t}{\fs16 2}{\f10 \fs13 =}{\b\i \fs16
3}{\fs16
remainder}{\fs16 of}{\fs15 0 }\par
}
\f10 \fs22 +}{\b\i\dn006 \fs16 2}{\dn006 \f10 \fs13 = }
{\fs16 I}{\f10 \fs20 +}{\dn006 \fs16 2}{\dn006 \f10 \fs13 = }
fi143 {\fs16 Binary }\par
}
\cf0 1{\f20 \fs16 remainder}{\f20 \fs16 of}{\f20 \fs16 I }
0 \fs16 0}{\f20 \fs16 remainder}{\f20 \fs15 of}{\b 1 }\par
}
{\phpg\posx2699\pvpg\posy10374\absw1025\absh1267 \f10 \fs105 \cf0 \f10 \fs105 \c
f0 + \par
}
0.5{\f10 \fs13 x}{\fs16 2}{\f10 \fs13 =}{\fs16 i.0 }
{\fs16 0.0}{\f10 \fs13 x} 2{\f10 \fs13 =}{\fs16 0.0 }\par
}
\par
}
\cf0 1 \par
}
\par
}
I \par
}
\par
}
\par
}
\par
}
Fig.{\b \f30 \fs17 2-3}{\fs17 BCD-to-binary}{\fs16 conversion }\par
}
8 \cf0 Step 2 in Fig. 2-3 shows the integer part{\fs18 of} the decimal nuniber
being translated into binary. The
,o is converted into{\fs18 1100111,} in step 2 by the repeated divide-by-2 pr
ocedure.
360 Step 3 in Fig. 2-3 illustrates the fractional part of the decimal number bei
ng translated into binary.
{\fs18 0.510} is converted into{\fs18 0.1,} in step 3 by the repeated mul
tiply-by-2 procedure. The integer and
\par}{\phpg\posx837\pvpg\posy12284\absw8993\absh1269 \sl-232 \f20 \fs18 \cf0 fra
ctional parts of the binary number are joined. The BCD nu:mber 000100000
011.0101 then equals
binary number 1100111.1. \par
}
par
}
cf0 BINARY CODES \par
}
}
cf0 1 \par
}
0 \cf0 6 \par
}
\cf0 6 \par
}
v \par
}
w \par
}
par
}
par
}
w \par
}
\cf0 Fig. 2-4{\fs17
Binary-to-BCD}{\fs17 conversion }\par
}
\cf0 Note that it is usually more efficient to write down a figure in st
raight binary numbers than in
\par}{\phpg\posx843\pvpg\posy5052\absw9238\absh1705 \sl-241 \f20 \fs19 \cf0 BCD
numbers. Binary numbers usually contain fewer 1s and{\b \fs18 OS,} as seen in
the conversion in Fig. 2-3.
\par}{\phpg\posx843\pvpg\posy5052\absw9238\absh1705 \sl-231 \f20 \fs19 \cf0 Alth
ough longer, BCD numbers are used in digital systems when numbers must be easily
converted to
mals.
59 Translate the binary number 10001010.101 into its BCD (8421) equivale
nt. The procedure is
n in Fig.{\fs19 2-4.} The binary number is first converted to its decimal equi
valent. The binary number
1010.101 then equals 138.625,,. Each decimal digit is then translated in
to its BCD equivalent.
\par}{\phpg\posx843\pvpg\posy5052\absw9238\absh1705 \sl-231 \f20 \fs19 \cf0 Figu
re 2-4 shows decimal 138.625being converted into the BCD number 000100111000.011
000100101. \par
}
{\phpg\posx839\pvpg\posy6950\absw6231\absh434 \f20 \fs19 \cf0 \f20 \fs19 \cf0 Th
e
entire conversion, then,
translates binary
10001010.101,
0111000.011000100101. \par
}
nto
the
BCD
number \par
}
\cf0 "Binary-coded decimal (BCD)" is a general term that may apply to any one of
several codes. The
\par}{\phpg\posx843\pvpg\posy7424\absw9266\absh643 \sl-234 \f20 \fs19 \cf0 most
popular BCD code is the 8421 code. The numbers 8, 4, 2, and 1 stand for the weig
ht of each bit
\par}{\phpg\posx843\pvpg\posy7424\absw9266\absh643 \sl-242 \f20 \fs19 \cf0 in th
e 4-bit group. Examples{\fs18 of} other weighted BCD 4-bit codes are shown in F
ig. 2-5. \par
}
2{\b \f20 \fs16 1 }\par
}
cf0 BCD \par
}
cf0 422{\fs16 1 }\par
}
cf0 BCD \par
}
cf0 542{\f10 \fs15 1 }\par
}
cf0 BCD \par
}
cf0 Decimal \par
}
s{\b \f20 \fs16 4s}{\b \f20 \fs16 2s}{\b \f20 \fs16 Is}{\b \f20 \fs16
8
s}{\fs15 4s}{\fs15 2s} 1s \par
}
0
6 0}{\fs16 0 }
\par}{\phpg\posx3823\pvpg\posy9845\absw306\absh973 \sl-217 \f20 \fs16 \cf0 0 0
\par}{\phpg\posx3823\pvpg\posy9845\absw306\absh973 \sl-222 \f20 \fs16 \cf0 0 0
\fs16 0}{\f10 \fs16 1 }\par
}
ar
}
ar
}
r
}
{\b \f10 \fs15 1 }\par
}
s{\b \f20 \fs16 2s}{\b \f20 \fs16 2s}{\f20 \fs16 Is}{\b \f20 \fs16
4s}{\
b \f20 \fs16 2s} 2s{\b \f20 \fs16 Is }\par
}
s{\b \f20 \fs16 4s}{\f20 \fs17 2s}{\f20 \fs16 Is}{\i \f20 \fs16
5s}{\b
\fs14 4s}{\f20 \fs16 2s}{\f20 \fs16 Is }\par
}
\cf0 0
0 {\b \fs16 1 }
8 {\b \fs16 2 }
8 {\b\i \fs16 3 }
0 {\b \fs16 4 }
1 {\b \fs16 5 }
6 6

1 {\b\i \fs16 7 }
8 {\b \f10 \fs15 8 }
6 {\fs15 9 }
\fs16 10 }
\f10 \fs15 1}{\b \f10 \fs15 1 }
\fs16 12 }
\fs16 13 }\par
}
\par
}
0 \par
}
\fs15 \cf0 1
\b0 \f20 \fs17 0 }
\b0 \fs15 0 }\par
}
\fs15 \cf0 1
\b0 \f20 \fs17 0 }
\b0 \fs15 1 }\par
}
0 \par
}
\fs15 \cf0 1
\fi20 {\b0 \fs15 0 }
\fi20 {\b0 \fs15 0 }
{\b0 \f20 \fs16 0 }
{\b0 \f20 \fs16 0 }
\fi28 {\b0 \fs15 1 }
\fi28 {\b0 1 }\par
}
\fs15 \cf0 1
{\b0 \fs15 0 }
{\b0 \fs15 1 }
{\b0 \f20 \fs16 0 }

{\b0 \f20 \fs16 1 }
{\b0 \fs15 0 }
\fi30 {\b0 1 }\par
}
1 \par
}
\cf0 1
0 {\fs15 1 }
0 \fs16 0 }
0 \fs16 0 }\par
}
\cf0 0
4 {\fs15 0 }
0 \fs16 0 }
0 \fs16 0 }\par
}
0 \fs16 0 }\par
}
\sl-220 \f10 \fs15 \cf0 0

\sl-215 \f10 \fs15 \cf0 0
\sl-218 \f10 \fs15 \cf0 {\f2
0 \fs16 0 }\par
}
\sl-220 \f10 \fs15 \cf0 0

\sl-215 \f10 \fs15 \cf0 0
\sl-218 \f10 \fs15 \cf0 {\f2
0 \fs16 0 }\par
}
\sl-220 \f10 \fs15 \cf0 0

\sl-215 \f10 \fs15 \cf0 0
\sl-218 \f10 \fs15 \cf0 {\f2
0 \fs16 1 }\par
}
0
\sl-220 \f10 \fs15 \cf0 1

\sl-215 \f10 \fs15 \cf0 1
\sl-218 \f10 \fs15 \cf0 {\f2
\fs15 \cf0 \f10 \fs15 \cf0 0
\fs15 \cf0 \f10 \fs15 \cf0 0
\fs15 \cf0 \f10 \fs15 \cf0 1
\fs16 \cf0 \f20 \fs16 \cf0 0

\sl-218 \f20 \fs16 \cf0 {\fs
16 0}{\fs16 0 }\par
}
15 0 }
15 0 }\par
}
\sl-220 \f10 \fs15 \cf0 {\fs
15 0 }
15 0 }\par
}
\sl-220 \f10 \fs15 \cf0 {\fs
15 0 }
15 0 }\par
}
\sl-220 \f10 \fs15 \cf0 {\fs
15 1 }
15 1 }\par
}
\sl-220 \f10 \fs15 \cf0 {\fs
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }
6 {\f10 \fs15 1 }
0 \fs15 0 }
6 {\f10 \fs15 1 }
6 {\b \f10 \fs15 1 }
6 {\b \f10 \fs15 1 }
3 {\b \f10 \fs15 1 }
16 0 }\par
}
\sl-216 \f20 \fs16 \cf0 {\f1
\sl-216 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 {\fs
\fs15 \cf0 \f10 \fs15 \cf0 0
\sl-216 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 {\fs
\fs15 \cf0 \f10 \fs15 \cf0 0
\sl-216 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 {\fs
\fs15 \cf0 \f10 \fs15 \cf0 1
\sl-216 \f10 \fs15 \cf0 1

\sl-217 \f10 \fs15 \cf0 {\fs
\fs16 \cf0 \f20 \fs16 \cf0 0
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-219 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 \fi3
\sl-215 \f20 \fs16 \cf0 {\f1
\sl-222 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 \fi3
\sl-221 \f20 \fs16 \cf0 \fi3
\sl-215 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 {\fs
\fs16 \cf0 \f20 \fs16 \cf0 0
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }
4 {\f10 \fs15 0 }
0 \fs15 1 }
7 {\f10 \fs15 1 }
4 {\b \f10 \fs15 1 }
7 {\b \f10 \fs15 1 }
0 {\b \f10 \fs15 1 }
16 0 }\par
}
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-219 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 \fi2
\sl-215 \f20 \fs16 \cf0 {\f1
\sl-222 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 \fi2
\sl-221 \f20 \fs16 \cf0 \fi2
\sl-215 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 {\fs
\fs16 \cf0 \f20 \fs16 \cf0 0
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 1 }
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 0 }
\f10 \fs15 0 }
\f10 \fs15 1 }
7 {\b \f10 \fs15 1 }
16 0 }\par
}
\sl-216 \f20 \fs16 \cf0 {\f1
0 \fs15 1 }
0 \fs15 0 }
3 {\b \f10 \fs15 1 }
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 0 }
\f10 \fs15 1 }
\sl-216 \f20 \fs16 \cf0 {\f1
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-219 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-215 \f20 \fs16 \cf0 {\f1
\sl-222 \f20 \fs16 \cf0 {\f1
\sl-216 \f20 \fs16 \cf0 {\b
\sl-221 \f20 \fs16 \cf0 {\b
\sl-215 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 {\fs
\fs16 \cf0 \f20 \fs16 \cf0 0
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-219 \f20 \fs16 \cf0 \fi3
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-215 \f20 \fs16 \cf0 {\f1
\sl-222 \f20 \fs16 \cf0 {\f1
\sl-216 \f20 \fs16 \cf0 {\b
\sl-221 \f20 \fs16 \cf0 {\b
\f10 \fs15 0 }
9 {\b \f10 \fs15 1 }
16 0 }\par
}
O O J \par
}
\sl-215 \f20 \fs16 \cf0 \fi2

\sl-216 \f20 \fs16 \cf0 {\fs
\fs16 \cf0 \f20 \fs16 \cf0 O
\fs15 \cf0 \f10 \fs15 \cf0 0

15 0 }\par
}
15 0 }\par
}
15 1 }\par
}
15 1 }\par
}
15 0 }
ar
}
\sl-217 \f10 \fs15 \cf0 {\fs
15 0 }
ar
}
\sl-217 \f10 \fs15 \cf0 {\fs
15 0 }
ar
}
\sl-217 \f10 \fs15 \cf0 {\fs
\sl-220 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 0 \p
\fs15 \cf0 \f10 \fs15 \cf0 0
\sl-220 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 0 \p
\fs15 \cf0 \f10 \fs15 \cf0 0
\sl-220 \f10 \fs15 \cf0 0

\sl-217 \f10 \fs15 \cf0 0 \p
\fs15 \cf0 \f10 \fs15 \cf0 1

15 1 }
ar
}
16 0 }
0 \fs15 0 }
0 \fs15 0 }
16 0 }
7 {\f10 \fs15 1 }
5 {\f10 \fs15 1 }
5 {\f10 \fs15 1 }
5 {\b \f10 \fs15 1 }
5 {\f10 \fs15 1 }
16 0 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }\par
}
\sl-223 \f20 \fs16 \cf0 {\fs
16 0 }
0 \fs15 0 }
0 \fs15 0 }
7 {\f10 \fs15 1 }
7 {\f10 \fs15 0 }
6 {\f10 \fs15 0 }
5 {\f10 \fs15 0 }
5 {\b \f10 \fs15 0 }
7 {\f10 \fs15 1 }
16 0 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }\par
}
\sl-223 \f20 \fs16 \cf0 {\fs
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 {\fs
\sl-222 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 \fi3
\sl-217 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 \fi3
\sl-220 \f20 \fs16 \cf0 \fi3
\sl-216 \f20 \fs16 \cf0 {\fs
\sl-217 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 {\f1
\fs16 \cf0 \f20 \fs16 \cf0 0
\sl-216 \f20 \fs16 \cf0 {\f1

\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 \fi4
\sl-222 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 \fi2
\sl-217 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 \fi2
\sl-220 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 {\fs
\sl-217 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 {\f1
\fs16 \cf0 \f20 \fs16 \cf0 0
16 0 }
0 \fs15 1 }
0 \fs15 1 }
0 {\f10 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 1 }
\f10 \fs15 1 }
0 {\f10 \fs15 0 }
16 0 }
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 1 }\par
}
\sl-223 \f20 \fs16 \cf0 {\fs

\sl-216 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 \fi3
\sl-222 \f20 \fs16 \cf0 {\f1
\sl-216 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 {\f1
\sl-216 \f20 \fs16 \cf0 {\b
\sl-220 \f20 \fs16 \cf0 \fi2
\sl-216 \f20 \fs16 \cf0 {\fs
\sl-217 \f20 \fs16 \cf0 {\f1
\sl-220 \f20 \fs16 \cf0 {\f1
\sl-217 \f20 \fs16 \cf0 {\f1
\fs16 \cf0 \f20 \fs16 \cf0 0

16 1 }
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 1 }
0 \fs15 0 }
\f10 \fs15 1 }
0 \fs15 0 }
16 0 }
0 \fs15 1 }
0 \fs15 0 }
0 \fs15 1 }\par
}
\cf0 Fig. 2-5{\fs17
Three}{\fs17 weighted}{\fs17 BCD}{\fs17 codes }\par
}
.{\fs17 21 }\par
}
NARY CODES \par
}
\par
}
LVED{\fs16 PROBLEMS }\par
}
f0 2.1 \par
}
{\phpg\posx1481\pvpg\posy1723\absw2362\absh507 \f20 \fs18 \cf0 \f20 \fs18 \cf0 T
he letters BCD stand for
}
{\phpg\posx4579\pvpg\posy1705\absw91\absh229 \f10 \fs19 \cf0 \f10 \fs19 \cf0 - \
par
}
par
}
he letters BCD stand for binary-coded decimal. \par
}
f0 2.2 \par
}
Convert the following 8421 BCD numbers to their decimal equivalents:
\i \fs18 (}{\b\i \fs18 a}{\b\i \fs18 )} 1010{\i \fs18
(b)} OOOZOlll{\f1
0 \fs16
<c)} 10000110{\b\i \fs19
(}{\b\i \fs19 d}{\b\i \fs19 )} 01
01O10OOO11{\i \fs19
(}{\i \fs19 e}{\i \fs19 )} OOIIOOIO.1OO1OIOO
\f30 \fs21 (f}{\f10 \fs16 )} 0001000000000000.0101
\fs17 Solution: }
351 {\fs17 The}{\fs17 decimal}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs1
7 BCD}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 ( a ){\i0 \f20 \fs17
1010}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 ERROR}{\
i0 \f20 \fs17 (no}{\i0 \f20 \fs17 such}{\i0 \f20 \fs17 BCD}{\i0 \f20 \fs17
number) }
\f20 \fs16 (b)}{\i0 \f20 \fs17
00010111}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17
17 }
\i0 (c)}{\i0 \f20 \fs17
10000110}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 86 }\
par
}
\cf0 ( d ){\i0 \f20 \fs17

010101~000011 }{\i0\dn006 \fs11 =}{\i0 \f20 \fs17
543 }
\b \f20 \fs16 (}{\b \f20 \fs16 e}{\b \f20 \fs16 )}{\i0 \f20 \fs17
00110010.
10010100}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 32.94 }
\f30 \fs19 (f)}{\i0 \f20 \fs17 0001000000000000.0101}{\i0\dn006 \fs11 =}{\i0
\f20 \fs17 1000.5 }\par
}
f0 2.3 \par
}
onvert the following decimal numbers to their 8421{\fs19 BCD} equivalents:
i \f10 \fs16 (a)}{\b \fs18
6,}{\i \fs18
(}{\i \fs18 b}{\i \fs18 )}{\fs1
9
13,}{\b\i
(}{\b\i c}{\b\i )}{\fs19
99.9,}{\i \f10
(d)} 872.8,{
\i \fs19
(}{\i \fs19 e}{\i \fs19 )} 145.6{\i \f30 \fs21 (f)} 21.001.
\fs17 Solution: }
60 {\fs17 The}{\fs17 BCD}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs17
decimal}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs16 follows: }\par
}
\cf0 (a){\i0 \f20 \fs17
6=0110 }
\f20 \fs17 (}{\f20 \fs17 b}{\f20 \fs17 )}{\i0 \f20 \fs17
13}{\i0\dn006 \fs1
1 =}{\i0 \f20 \fs17 00010011 }\par
}
{\phpg\posx3439\pvpg\posy6694\absw205\absh168 \f10 \fs14 \cf0 \f10 \fs14 \cf0 (c
) \par
}
9.9{\f10 \fs13 =} 10011001.1001 \par
}
cf0 (I?) \par
}
45.6{\dn006 \f10 \fs11 =} 000101000101.0110 \par
}
\cf0 ( d ){\i0 \f20 \fs17
872.8}{\i0 \fs13 =}{\i0 \f20 \fs17 100001110010.
1000 }\par
}
\cf0 ( f ){\i0 \f20 \fs17
21.001}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 00100
001.000000000001 }\par
}
f0 2.4 \par
}
Convert the following binary numbers to their 8421{\fs19 BCD} equivalents:
\i \fs18 (}{\b\i \fs18 a}{\b\i \fs18 )}{\fs19
10000,}{\i \fs18
(b)} 11
100.1,{\b \f10 \fs16
Cc)}
101011.01,{\b\i \f10 \fs18
(}{\b\i \f10 \fs1
8 d}{\b\i \f10 \fs18 )}
100111.11,{\i
(}{\i e}{\i )} 1010.001,
500 111{\fs18 1}110001.

\fs17 Solution: }
355 {\fs17 The}{\fs17 BCD}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs17
binary}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
{\phpg\posx1455\pvpg\posy8152\absw301\absh215 \f10 \fs16 \cf0 \f10 \fs16 \cf0 ({
\f20 \fs19 f} ) \par
}
\cf0 (a){\i0 \f20 \fs17
10000}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 00010110
}
\f20 \fs16 (}{\f20 \fs16 b}{\f20 \fs16 )}{\i0 \f20 \fs17
11100.1}{\i0\dn006
\fs11 =}{\i0 \f20 \fs17 00101000.0101 }
\b \f20 \fs17 (}{\b \f20 \fs17 c}{\b \f20 \fs17 )}{\i0 \f20 \fs17
101011.0
1}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 01000011.00100101 }\par
}
s16 \cf0 ( d ){\b0\i0 \f20 \fs17
100111.11}{\b0\i0\dn006 \fs11 =}{\b0\i0 \f
20 \fs17 00111001.01110101 }
{\f20 \fs16 (}{\f20 \fs16 e}{\b0\i0 \f20 \fs17
1 }{\b0\i0 \f20 \fs17 0}
{\b0\i0 \f20 \fs17 10.001}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs17 000}{\b0\i0 \f20
\fs17 10000.0001}{\b0\i0 \f20 \fs17 00}{\b0\i0 \f20 \fs17 1001}{\b0\i0 \f20 \fs1
7 0}{\b0\i0 \f20 \fs17 1 }
{\b0 \f30 \fs19 (f)}{\b0\i0 \f20 \fs17
1111110001}{\b0\i0\dn006 \fs11 =}{\b
0\i0 \f20 \fs17 0001000000001001 }\par
}
cf0 2.5 \par
}
Convert the following 8421 BCD numbers to their binary equivalents:
\par}{\phpg\posx1455\pvpg\posy10139\absw6601\absh1186 \sl-238 \f20 \fs18 \cf0 {\
b\i (}{\b\i a}{\b\i )} 00011000{\i \fs19
(b)}{\fs19
01001001}{\f10 \fs
16
(c)}
0110.01110101{\i \f10 \fs18
(6)} 00110111.0101
fs18 (e)}
01100000.00100101{\i \f30 \fs20 (f,} 0001.001101110101
b \fs17 Solution: }
i360 {\fs17 The}{\fs17 binary}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs1
7 BCD}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 (a){\i0 \f20 \fs17
00011000}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 10010
}
{\f20 \fs16 (}{\f20 \fs16 b}{\f20 \fs16 )}{\i0 \f20 \fs17
01001001}{\i0\dn0
06 \fs11 =}{\i0 \f20 \fs17 110001 }
( c ){\i0 \f20 \fs17
0110.01110101}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 110.
11 }\par
}
\cf0 ( d ){\i0 \f20
00110111.0101}{\i0\dn006 \fs11 =}{\i0 \f20 100101.1
}
{\b \f20 \fs16 (}{\b \f20 \fs16 e}{\b \f20 \fs16 )}{\i0 \f20
01}{\i0 \f20 1
00000.00100101}{\i0\dn006 \fs11 =}{\i0 \f20 111100.01 }
{\f30 \fs18 (f)}{\i0 \f20 0001.001101110101}{\i0\dn006 \fs13 =}{\i0 \f20 1.0
1}{\b\i0 \fs15 1 }\par
}
cf0 2.6 \par
}
List three weighted BCD codes.
\fs17 Solution: }
350 {\fs17 Three}{\fs17 BCD}{\fs17 codes}{\fs17 are:}{\i \f10 \fs14
(a)}{
\fs17
8421}{\fs17 BCD}{\fs17 code,}{\b\i \fs17
(b)}{\fs17
4221}{\fs
17 BCD}{\fs17 code,}{\b\i \f10 \fs14
(}{\b\i \f10 \fs14 c}{\b\i \f10 \fs1
4 )}{\fs17
5421}{\fs17 BCD}{\fs17 code. }\par
}
par
}
NARY CODES \par
}
AP.{\fs16 2 }\par
}
f0 2.7 \par
}
he 4221 BCD equivalent of decimal{\fs18 98} is
\fs17 Soh}{\b \fs16 tion: }\par
}
par
}
he{\fs16 4221} BCD equivalent of decimal{\fs17 98} is{\fs16 11111110. }\
par
}
he 5421 BCD equivalent of decimal 75 is
}
par
}
f0 2.8 \par
}
f0 2.9 \par
}
7 \cf0 The{\fs16 5421} BCD equivalent of decimal{\fs17 75} is{\fs16 101
01000. }
{\fs19 What}{\fs19 kind}{\fs19 of}{\fs19 number}{\fs19 (BCD}{\fs19 or}
{\fs19 binary)}{\fs19 would}{\fs19 be}{\fs19 easier}{\fs19 for}{\fs19 a}
{\fs19 worker}{\fs19 to}{\fs19 translate}{\fs19 to}{\fs19 decimal? }
\fs16 Solution: }
365 BCD numbers are easiest to translate to their decimal equivalents.
\par
}
\cf0 2-3{\f20 \fs18
NONWEIGHTED}{\f20 \fs18 BINARY}{\f20 \fs18 CODES }
fi365 {\b0 \f20 \fs19 Some}{\b0 \f20 \fs19 binary}{\b0 \f20 \fs19 codes}{\b0
\f20 \fs19 are}{\b0 \f20 \fs19 nonweighted.}{\b0 \f20 \fs19 Each}{\b0 \f2
0 \fs19 bit}{\b0 \f20 \fs19 therefore}{\b0 \f20 \fs19 has}{\b0 \f20 \fs19
no}{\b0 \f20 \fs19 special}{\b0 \f20 \fs19 weighting.}{\b0 \f20 \fs19 Tw
o}{\b0 \f20 \fs19 such }
\b0 \f20 \fs19 nonweighted}{\b0 \f20 \fs19 codes}{\b0 \f20 \fs19 are}{\b0 \f20
\fs19 the}{\b0 \f20 \fs19 excess-3}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 Gray
}{\b0 \f20 \fs19 codes. }
fi361 {\b0 \f20 \fs19 The}{\i \f10 \fs17 excess-3}{\b0 \f20 \fs19 (XS3)}{\b0
\f20 \fs19 code}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 related}{\b0 \f20 \fs19
to}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 8421}{\b0 \f20 \fs19 BCD}{\b0 \f20
\fs19 code}{\b0 \f20 \fs19 because}{\b0 \f20 of}{\b0 \f20 \fs19 its}{\b0
\f20 \fs19 binary-coded-decimal }
\b0 \f20 \fs19 nature.}{\b0 \f20 \fs19 In}{\b0 \f20 \fs19 other}{\b0 \f20 \fs
19 words,}{\b0 \f20 \fs19 each}{\b0 \f20 \fs19 4-bit}{\b0 \f20 \fs19 group
}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 XS3}{\b0 \f20 \fs19
code}{\b0 \f20 \fs19 equals}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 specific}{\b0
\f20 \fs19 decimal}{\b0 \f20 \fs19 digit.}{\b0 \f20 \fs19 Figure}{\b0 \f20
\fs18 2-6 }
\b0 \f20 \fs19 shows}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 XS3}{\b0 \f20 \fs19
code}{\b0 \f20 \fs19 along}{\b0 \f20 \fs19 with}{\b0 \f20 \fs19 its}{\b0 \f20
\fs19 8421}{\b0 \f20 \fs19 BCD}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 decimal}
{\b0 \f20 \fs19 equivalents.}{\b0 \f20 \fs19 Note}{\b0 \f20 \fs19 that}{\b0
\f20 \fs19 the}{\b0 \f20 \fs19 XS3}{\b0 \f20 \fs19 number}{\b0 \f20 \fs19 i
s }
\b0 \f20 \fs19 always}{\i \f10 \fs18 3}{\i \f20 \fs19 more}{\b0 \f20 \fs19 t
han}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 8421}{\b0 \f20 \fs19 BCD}{\b0 \f20 \f
s19 number. }\par
}
21{\b
BCD }\par
}
s \par
}
\cf0 1s
{\fs16 OOOO }
16 OOOl }
16 0010 }
0 \fs15 001}{\b \f10 \fs15 1 }
16 0}{\fs16 100 }
16 0101 }
16 01}{\fs16 10 }
16 0111 }
3 {\fs16 1000 }
3 {\fs16 1001 }\par
}
XS3{\fs17
BCD }
\fi87 10s{\fs16
Is }
0011
0011
1
0100
1
0101
s16 0011}
0110
1
0111
1{\b \f30 \fs18 1OOO }
1
1001
1
1010
1
1011
1
1100
s16 0100}
0011
s16 0100}
0100 \par
}
cimaI \par
}
3 {\fs16 1 }
16 2 }
i \fs16 3 }

16 4 }
17 5 }
i \fs16 6 }
\fs16 7 }
16 8 }
ar
}
001
0000 \par
}
20 \fs16 \cf0 Fig.{\fs16 2-6}{\b0 \fs17
The}{\b0 \fs17 excess-3(XS3)code }
cf0 \fi366 {\b0 \fs19 Consider}{\b0 \fs19 changing}{\b0 \fs19 the}{\b0 \fs19
decimal}{\b0 \fs19 number}{\b0 \fs19 62}{\b0 \fs19 to}{\b0 \fs19 an}{\b0 \fs
19 equivalent}{\b0 \fs19 XS3}{\b0 \fs19 number.}{\b0 \fs19 Step}{\b0 \fs18
1}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 2-7a}{\b0 \fs19 shows }
{\fs18 3}{\b0 \fs19 being}{\b0 \fs19 added}{\b0 \fs19 to}{\b0 \fs19 each
}{\b0 \fs19 decimal}{\b0 \fs19 digit.}{\b0 \fs19 Step}{\b0 \fs19 2}{\b0
\fs19 shows}{\b0 \fs18 9}{\b0 \fs19 and}{\b0 \fs19 5}{\b0 \fs19 being}
{\b0 \fs19 converted}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 8421}{\b0
\fs19 BCD }
{\b0 \fs19 equivalents.}{\b0 \fs19 The}{\b0 \fs19 decimal}{\b0 \fs19 number}{
\b0 \fs18 62}{\b0 \fs19 then}{\b0 \fs19 equals}{\b0 \fs19 the}{\b0 \fs19 B
CD}{\b0 \fs19 XS3}{\b0 \fs19 number}{\b0 \fs19 10010101. }
\fi366 {\b0 \fs19 Convert}{\b0 \fs19 the}{\b0 \fs19 8421}{\b0 \fs19 BCD}{\b
0 \fs19 number}{\b0 \fs19 01000000}{\b0 \fs19 to}{\b0 \fs19 its}{\b0 \fs1
9 XS3}{\b0 \fs19 equivalent.}{\b0 \fs19 Figure}{\b0 \fs19 2-7b}{\b0 \fs1
9 shows}{\b0 \fs19 the}{\b0 \fs19 simple }
{\b0 \fs19 procedure.}{\b0 \fs19 The}{\b0 \fs19 BCD}{\b0 \fs19 number}{\b0 \
fs19 is}{\b0 \fs19 divided}{\b0 \fs19 into}{\b0 \fs19 4-bit}{\b0 \fs19 gro
ups}{\b0 \fs19 starting}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \fs19 binary}{\b0
\fs19 point.}{\b0 \fs19 Step}{\b0 \fs19 1}{\b0 \fs19 shows}{\b0 \fs19 3 }
{\b0 \fs19 (binary}{\b0 \fs19 0011)}{\b0 \fs19 being}{\b0 \fs19 added}{\b0
\fs19 to}{\b0 \fs19 each}{\b0 \fs19 4-bit}{\b0 \fs19 group.}{\b0 \fs19
The}{\b0 \fs19 sum}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 resulting}{\b
0 \fs19 XS3}{\b0 \fs19 number.}{\b0 \fs19 Figure}{\b0 \fs19 2-7b }
{\b0 \fs19 shows}{\b0 \fs19 the}{\b0 \fs19 8421}{\b0 \fs19 BCD}{\b0 \fs19 nu
mber}{\b0 \fs19 01000000}{\b0 \fs19 being}{\b0 \fs19 converted}{\b0 \fs19
to}{\b0 \fs19 its}{\b0 \fs19 equivalent}{\b0 \fs19 BCD}{\b0 \fs19 XS3}{\b0 \
fs19 number,}{\b0 \fs19 which}{\b0 \fs19 is }
{\b0 \fs19 01110011. }\par
}
.{\f10 \fs16 21 }\par
}
cf0 BINARY{\fs17 CODES }\par
}
f0 21 \par
}
cf0 Decimal \par
}
\par
}
cf0 xs3 \par
}
cf0 6 \par
}
cf0 2 \par
}
3{\fs22
+3 }
53 {\b \f20 \fs17 9}{\b \f20 \fs17
5 }
11 {\fs19 1}{\fs19
1 }
\f30 \fs17 1001}{\b \f20 \fs17
0101 }\par
}
\cf0 ( U ) \par
}
cf0 @Add \par
}
cf0 3 \par
}
{\phpg\posx3507\pvpg\posy1811\absw1940\absh371 \f10 \fs31 \cf0 \f10 \fs31 \cf0 @
{\b \f20 \fs17 Convert}{\b \f20 \fs16 to}{\b \f20 \fs17 binary }\par
}
cf0 BCD
i156 {\b0 \f10 \fs20 1 }
i40 {\fs24 xs3 }\par
}
cf0 oo00 \par
}
cf0 0100 \par
}
\cf0 +0011{\f10 \fs15
+0011 }
fi146 0111 0011 \par
}
cf0 @Add3 \par
}
-ydt{\fs72 - }\par
}
cf0 1100 \par
}
\cf0 Decimal-to-XS3conversion \par
}
\cf0 xs3
fi186 {\b0 \f30 \fs24 I }
\fs17 BCD }
fi186 {\b0 \f10 \fs19 1 }
\fs17 Decimal }\par
}
cf0 loo0 \par
}
s15 \cf0 (b){\i0 \fs15 BCD-to-XS3}{\i0 \fs15 conversion }\par
}
cf0 a \par
}
{\phpg\posx3981\pvpg\posy3123\absw2810\absh259 \f10 \fs22 \cf0 \f10 \fs22 \cf0 -{\b \f20 \fs17
Subtract}{\b \f20 \fs17 3 }\par
}
cf0 -0011
i143 0101
i287 {\b0 \f10 \fs20 1 }
i287 {\i \f10 \fs16 5 }\par
}
f20 \fs16 9 }\par
}
\cf0 Convert{\fs15 to} decimal \par
}
\f20 \fs14 \cf0 (c){\i0 \fs15 XS3-to-decimal}{\i0 \fs15 conversion }
\cf0 \fi4078 {\i0 \fs16 Fig.}{\i0 \f10 \fs16 2-7 }
\cf0 \fi368 {\b0\i0 \fs18 Consider}{\b0\i0 \fs18 the}{\b0\i0 \fs18 conversion}
{\b0\i0 \fs18 from}{\i0 \fs19 XS3}{\b0\i0 \fs18 code}{\b0\i0 \fs18 to}{\b0\i
0 \fs18 decimal.}{\b0\i0 \fs18 Figure}{\i0 \fs18 2-7c}{\b0\i0 \fs18 shows}{\
b0\i0 \fs18 the}{\i0 \fs19 XS3}{\b0\i0 \fs18 number}{\i0 \fs18 10001100 }

{\b0\i0 \fs18 being}{\b0\i0 \fs18 converted}{\b0\i0 \fs18 to}{\b0\i0 \fs18 i
ts}{\b0\i0 \fs18 decimal}{\b0\i0 \fs18 equivalent.}{\b0\i0 \fs18 The}{\b0\i0
\fs19 XS3}{\b0\i0 \fs18 number}{\b0\i0 \fs18 is}{\b0\i0 \fs18 divided}{\b0\i
0 \fs18 into}{\b0\i0 \fs18 4-bit}{\b0\i0 \fs18 groups}{\b0\i0 \fs18 starting
}{\b0\i0 \fs18 at}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 binary}{\b0\i0 \fs18 point.}{\b0\i0 \fs18 Step}{\i0 \fs18 1
}{\b0\i0 \fs18 shows}{\b0\i0 \fs18 3}{\b0\i0 \fs18 (binary}{\i0 \fs18 0011)
}{\b0\i0 \fs18 being}{\b0\i0 \fs18 subtracted}{\b0\i0 \fs18 from}{\b0\i0 \f
s18 each}{\b0\i0 \fs18 4-bit}{\b0\i0 \fs18 group.}{\b0\i0 \fs18 An}{\i0
\fs18 8421}{\b0\i0 \fs18 BCD }
{\b0\i0 \fs18 number}{\b0\i0 \fs18 results.}{\b0\i0 \fs18 Step}{\b0\i0 \fs1
8 2}{\b0\i0 \fs18 shows}{\b0\i0 \fs18 each}{\b0\i0 \fs18 4-bit}{\b0\i0 \fs
18 group}{\b0\i0 \fs18 in}{\b0\i0 \fs18 the}{\i0 \fs18 8421}{\b0\i0 \fs1
8 BCD}{\b0\i0 \fs18 number}{\b0\i0 \fs18 being}{\b0\i0 \fs18 translated}
{\b0\i0 \fs18 into}{\b0\i0 \fs18 its }
{\b0\i0 \fs18 decimal}{\b0\i0 \fs18 equivalent.}{\b0\i0 \fs18 The}{\i0 \fs19
XS3}{\b0\i0 \fs18 number}{\b0\i0 \fs18 10001100}{\b0\i0 \fs18 is}{\b0\i0 \
fs18 equal}{\b0\i0 \fs18 to}{\b0\i0 \fs18 decimal}{\b0\i0 \fs19 59}{\b0\i0 \
fs18 according}{\b0\i0 \fs18 to}{\b0\i0 \fs18 the}{\b0\i0 \fs18 procedure}{\
b0\i0 \fs18 in }
{\b0\i0 \fs18 Fig.}{\i0 \fs18 2-7c. }
\fi364 {\b0\i0 \fs18 The}{\i0 \fs19 XS3}{\b0\i0 \fs18 code}{\b0\i0 \fs18 has
}{\b0\i0 \fs18 significant}{\b0\i0 \fs18 value}{\b0\i0 \fs18 in}{\b0\i0 \fs18
arithmetic}{\b0\i0 \fs18 circuits.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 value}{\
b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 code}{\b0\i0 \fs18 lies}{\b0\
i0 \fs18 in}{\b0\i0 \fs18 its}{\b0\i0 \fs18 ease}{\b0\i0 \fs18 of }
{\b0\i0 \fs18 complementing.}{\b0\i0 \fs18 If}{\b0\i0 \fs18 each}{\b0\i0 \fs1
8 bit}{\b0\i0 \fs18 is}{\b0\i0 \fs18 complemented}{\i0 \fs18 (OS}{\b0\i0 \fs
18 to}{\b0\i0 \fs18 1s}{\b0\i0 \fs18 and}{\i0 \fs18 1s}{\b0\i0 \fs18 to}{\
i0 \fs18 OS),}{\b0\i0 \fs18 the}{\b0\i0 \fs18 resulting}{\b0\i0 \fs18 4-bit
}{\b0\i0 \fs18 word}{\b0\i0 \fs18 will}{\b0\i0 \fs18 be}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 9s}{\b0\i0 \fs18 complement}{\b0\i0 \fs18 of}{\b0\i0 \fs18 t
he}{\b0\i0 \fs18 number.}{\b0\i0 \fs18 Adders}{\b0\i0 \fs18 can}{\b0\i0 \fs1
8 use}{\i0 \fs18 9s}{\b0\i0 \fs18 complement}{\b0\i0 \fs18 numbers}{\b0\i0
\fs18 to}{\b0\i0 \fs18 perform}{\b0\i0 \fs18 subtraction. }
\fi364 {\b0\i0 \fs18 The}{\i0 \fs18 Gray}{\i0 \fs18 code}{\b0\i0 \fs18 is
}{\b0\i0 \fs18 another}{\b0\i0 \fs18 nonweighted}{\b0\i0 \fs18 binary}{\b0
\i0 \fs18 code.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 Gray}{\b0\i0 \fs18 code}
{\b0\i0 \fs18 is}{\b0\i0 \fs18 not}{\b0\i0 \fs18 a}{\b0\i0 \fs18 BCD-typ
e}{\b0\i0 \fs18 code. }
{\b0\i0 \fs18 Figure}{\b0\i0 \fs18 2-8}{\b0\i0 \fs18 compares}{\b0\i0 \fs18
the}{\b0\i0 \fs18 Gray}{\b0\i0 \fs18 code}{\b0\i0 \fs18 with}{\b0\i0 \fs18 e
quivalent}{\b0\i0 \fs18 binary}{\b0\i0 \fs18 and}{\b0\i0 \fs18 decimal}{\b0\i
0 \fs18 numbers.}{\i0 \fs19 Look}{\b0\i0 \fs18 carefully}{\b0\i0 \fs18 at}{\
b0\i0 \fs18 the }
{\b0\i0 \fs18 Gray}{\b0\i0 \fs18 code.}{\b0\i0 \fs18 Note}{\b0\i0 \fs18 that
}{\b0\i0 \fs18 each}{\b0\i0 \fs18 increase}{\b0\i0 \fs18 in}{\b0\i0 \fs18 c
ount}{\b0\i0 \fs18 (increment)}{\b0\i0 \fs18 is}{\b0\i0 \fs18 accompanied}{\b
0\i0 \fs18 by}{\i0 \fs18 only}{\i0 \fs19 I}{\i0 \fs18 bit}{\i0 \fs18 chang
ingstate. }
{\i0 \fs19 Look}{\b0\i0 \fs18 at}{\b0\i0 \fs18 the}{\b0\i0 \fs18 change}{\b0
\i0 \fs18 from}{\b0\i0 \fs18 the}{\b0\i0 \fs18 decimal}{\i0 \fs18 7}{\b0\i0
\fs18 line}{\b0\i0 \fs18 to}{\b0\i0 \fs18 the}{\b0\i0 \fs18 decimal}{\i0 \f
s18 8}{\b0\i0 \fs18 line.}{\b0\i0 \fs18 In}{\b0\i0 \fs18 binary}{\b0\i0 \fs1
8 all}{\b0\i0 \fs18 four}{\b0\i0 \fs18 bits}{\b0\i0 \fs18 change}{\b0\i0 \fs
18 state }
{\b0\i0 \fs18 (from}{\b0\i0 \fs19 0111}{\b0\i0 \fs18 to}{\b0\i0 \fs18 1000).
}{\b0\i0 \fs18 In}{\b0\i0 \fs18 this}{\b0\i0 \fs18 same}{\b0\i0 \fs18 line}{\
b0\i0 \fs18 the}{\b0\i0 \fs18 Gray}{\b0\i0 \fs18 code}{\b0\i0 \fs18 has}{\b0
\i0 \fs18 only}{\b0\i0 \fs18 the}{\b0\i0 \fs18 left}{\b0\i0 \fs18 bit}{\b0\i
0 \fs18 changing}{\b0\i0 \fs18 state}{\b0\i0 \fs18 (0100}{\b0\i0 \fs18 to}{\
b0\i0 \fs19 1100). }
{\b0\i0 \fs18 This}{\b0\i0 \fs18 change}{\b0\i0 \fs19 of}{\b0\i0 \fs18 a}
{\b0\i0 \fs18 single}{\b0\i0 \fs18 bit}{\b0\i0 \fs18 in}{\b0\i0 \fs18 th
e}{\b0\i0 \fs18 code}{\b0\i0 \fs18 group}{\b0\i0 \fs18 per}{\b0\i0 \fs18
increment}{\b0\i0 \fs18 characteristic}{\b0\i0 \fs18 is}{\b0\i0 \fs18 imp
ortant}{\b0\i0 \fs18 in}{\b0\i0 \fs18 some }
{\b0\i0 \fs18 applications}{\b0\i0 \fs18 in}{\b0\i0 \fs18 digital}{\b0\i0 \fs
18 electronics. }\par
}
\cf0 Decimal
f0 \fi309 {\f30 \fs17 0 }
fi334 {\f30 \fs17 1 }
fi309 {\f30 \fs17 2 }
fi312 {\fs17 3 }
fi305 {\f30 \fs17 4 }
fi312 {\fs16 5 }
fi305 {\fs17 6 }
fi312 {\f30 \fs17 7 }\par
}
\cf0 Binary
f0 \fi70 {\b0 \f10 \fs23 m }
fi66 {\f30 \fs18 OOOl }
fi70 {\f30 \fs17 0010 }
fi70 {\f30 \fs17 001}{\f30 \fs17 1 }
fi64 {\f30 \fs17 0}{\f30 \fs17 100 }
fi66 {\f30 \fs17 0101 }
fi63 {\f30 \fs17 0110 }

fi63 {\f30 \fs17 0111 }\par
}
\par
}
\cf0 Gray code
f0 \fi222 {\b0 \f10 \fs22 m }
fi220 {\f30 \fs19 OOOl }
fi222 {\f30 \fs17 001}{\f30 \fs17 1 }
fi222 {\f30 \fs18 00}{\f30 \fs17 10 }
fi220 {\f30 \fs17 0110 }
fi220 {\f30 \fs17 0111 }
fi216 {\f30 \fs17 0101 }
fi220 {\f30 \fs17 0100 }\par
}
\par
}
\cf0 Decimal
fi303 {\b0 \f10 \fs1 ~~ }
fi311 {\f30 \fs17 8 }
fi310 {\f30 \fs17 9 }
fi237 {\f30 \fs17 10 }
fi243 {\f30 \fs17 1}{\f30 \fs17 1 }
fi237 {\f30 \fs17 12 }
fi240 {\f30 \fs17 13 }
fi237 {\f30 \fs17 14 }
fi237 {\f30 \fs17 15 }\par
}
\par
}
\cf0 Binary
fi62 {\b0 \f10 \fs1 ~~ }
fi100 {\b0 \fs17 loo0 }
fi97 {\f30 \fs17 1001 }

fi97 {\f30 \fs17 1010 }
fi97 {\f30 \fs17 101}{\f30 \fs17 1 }
fi97 {\f30 \fs17 1100 }
fi100 {\f30 \fs17 1101 }
fi97 {\f30 \fs17 1110 }
fi97 {\f30 \fs17 1}{\f30 \fs17 1}{\f30 \fs17 1}{\f30 \fs17 1 }\par
}
\cf0 Gray code
f0 \fi252 {\f30 \fs17 1100 }
fi252 {\f30 \fs17 1101 }
fi252 {\f30 \fs17 1}{\f30 \fs17 1}{\f30 \fs17 1}{\f30 \fs17 1 }
fi252 {\f30 \fs17 1110 }
fi250 {\f30 \fs17 1010 }
fi252 {\f30 \fs17 101}{\f30 \fs17 1 }
fi252 {\f30 \fs17 1001 }
fi250 {\f30 \fs17 loo0 }\par
}
20 \fs16 \cf0 Fig.{\fs17 2-8}{\fs17
The} Gray{\fs17 code }
cf0 \fi367 {\b0 \fs18 Consider}{\b0 \fs18 converting}{\b0 \fs18 a}{\b0 \fs18
binary}{\b0 \fs18 number}{\b0 \fs18 to}{\b0 \fs18 its}{\b0 \fs18 Gray}{\b
0 \fs18 code}{\b0 \fs18 equivalent.}{\b0 \fs18 Figure}{\fs18 2-9a}{\b0 \fs1
8 shows}{\b0 \fs18 the}{\b0 \fs18 binary }
{\b0 \fs18 number}{\fs18 0010}{\b0 \fs18 being}{\b0 \fs18 translated}{\b0 \fs
18 into}{\b0 \fs18 its}{\b0 \fs18 Gray}{\b0 \fs18 code}{\b0 \fs18 equivale
nt.}{\b0 \fs18 Start}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 MSB}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs18 number. }
{\b0 \fs18 Transfer}{\b0 \fs18 this}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18
left}{\b0 \fs18 position}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 Gray}{\b0 \
fs18 code}{\b0 \fs18 as}{\b0 \fs18 shown}{\b0 \fs18 by}{\b0 \fs18 the}{\b0
\fs18 downward}{\b0 \fs18 arrow.}{\b0 \fs18 Now}{\fs18 add}{\b0 \fs18 the}
{\fs18 8s }
{\b0 \fs18 bit}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 next}{\b0 \fs18 bit}{
\b0 \fs18 over}{\b0 \fs18 (4s}{\b0 \fs18 bit).}{\b0 \fs18 The}{\b0 \fs18 su
m}{\fs18 is}{\b0 \fs18 0}{\b0 \fs18 (0}{\b0 \f10 \fs28 +}{\b0 \fs18 0}{\b0\
dn006 \f10 \fs13 =}{\b0 \fs19 0),}{\b0 \fs18 which}{\b0 \fs18 is}{\b0 \fs18
transferred}{\b0 \fs18 down}{\b0 \fs18 and}{\b0 \fs18 written}{\b0 \fs18 a
s}{\b0 \fs18 the }
{\b0 \fs18 second}{\b0 \fs18 bit}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 l
eft}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 Gray}{\b0 \fs18 code.}{\b0 \fs18
The}{\b0 \fs18 4s}{\b0 \fs18 bit}{\b0 \fs18 is}{\b0 \fs18 now}{\b0 \fs18
added}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 2s}{\b0 \fs18 bit}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs18 number. }
{\b0 \fs18 The}{\b0 \fs18 sum}{\b0 \fs18 is}{\fs18 1}{\b0 \fs18 (0}{\b0 \f10
\fs29 +}{\dn006 \fs18 1}{\b0 \f10 \fs14 =}{\fs18 1)}{\b0 \fs18 and}{\fs18
is}{\b0 \fs18 transferred}{\b0 \fs18 down}{\b0 \fs18 and}{\b0 \fs18 written
}{\b0 \fs18 as}{\b0 \fs18 ithe}{\b0 \fs18 third}{\b0 \fs18 bit}{\b0 \fs18
from}{\b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18
Gray }\par
}
par
}
cf0 BINARY CODES \par
}
}
i \par
}
nary \par
}
{\phpg\posx1771\pvpg\posy2377\absw822\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Gr
ay{\fs16 code }\par
}
0{\f10 \fs33 /;/;/A }
{\fs21 I }
\par}{\phpg\posx2951\pvpg\posy1331\absw1037\absh1131 \sl-184 \f20 \fs16 \cf0 0 \
par
}
nary \par
}
{\phpg\posx3227\pvpg\posy1941\absw856\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 su
m
sum \par
}
cf0 I
\fs21 1 }
\fs16 0 }\par
}
cf0 l
\fs21 1 }
f20 \fs16 1 }\par
}
m \par
}
cf0 l
\fs21 1 }
f20 \fs16 1 }\par
}
{\phpg\posx5535\pvpg\posy2385\absw828\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Gr
ay code \par
}
\fs33 \cf0 /;/;/;/A
\par}{\phpg\posx6745\pvpg\posy1240\absw1294\absh1220 \sl-321 \par\par\b \f10 \fs
33 \cf0 {\b0 \f20 \fs16 1 }\par
}
um
sum
sum
sum \par
}
{\phpg\posx3081\pvpg\posy2693\absw245\absh234 \f10 \fs20 \cf0 \f10 \fs20 \cf0 (4
\par
}
\cf0 !
6 {\f20 \fs21 1 }
2 {\b \f20 \fs16 1 }
{\b\i \f20 \fs15 (b) }\par
}
cf0 I
\fs21 1 }
{\f20 \fs16 I }\par
}
cf0 l
\fs21 1 }
6 0 }\par
}
cf0 l
\fs21 1 }
5 1 }\par
}
\fs16 \cf0 Fig.{\f30 \fs17 2-9}{\b0 \fs16 Binary-to-Gray}{\b0 \fs16
code
}{\b0 \fs16 conversion }
b0 \fs18 code.}{\b0 \fs18 The}{\b0 \fs18 2s}{\b0 \fs18 bit}{\b0 \fs18 is}
{\b0 \fs18 now}{\b0 \fs18 added}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18
1s}{\b0 \fs18 bit}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \f
s18 number.}{\b0 \fs18 The}{\b0 \fs18 sum}{\b0 \fs18 is}{\b0 \fs18 1}{
\b0 \fs18 (1}{\b0 \f10 \fs29 +}{\b0 \fs18 0 }\par
}
\f20 \fs18 1)}{\f20 \fs18 and}{\f20 \fs18 is }\par
}
{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \f20 \fs18 \cf0 \f20 \fs18 \cf0 t
ransferred and written as the right bit{\fs18 in} the Gray code. The bin
ary{\fs18 0010} is then equal{\fs18 to} the Gray
number 0011. This can be verified in the decimal{\fs19 2} line of the table
in Fig. 2-8.
68 The rules for converting from any binary number to its equivalent
Gray code number are{\fs19 as }
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-236 \f20 \fs18 \cf0 foll
ows:
84 1. The left bit is the same in the Gray code as{\fs19 in} the binary numb
er.
70 2. Add the{\b \fs19 MSB} to the bit on its immediate right and record t
he sum (neglect any carry) below
21 in the Gray code line.
68 {\b \fs18 3.}
Continue adding bits to the bits on their right and r
ecording sums until the{\fs18 LSB} is reached.
70 {\fs19 4.}
The Gray code number will always have the same number of bits a
s the binary number.
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-293 \f20 \fs18 \cf0 Try
these rules when converting binary 10110 to its Gray code equivalent.
Figure{\fs18 2-96} shows the
\fs19 MSB(1)} in the binary number being transferred down and written as part
of the Gray code number.
16s bit is then added to{\fs18 the} 8s bit of the binary number. T
he sum is 1 (1{\f10 \fs27 +}{\dn006 \fs18 0}{\dn006 \f10 \fs13 =}{\fs22 1
1,} which is
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-235 \f20 \fs18 \cf0 reco
rded in the Gray code (second bit from left). Next the 8s bit is added to t
he 4s bit of the binary
er. The sum is 1{\fs18 (0}{\f10 \fs28 +} 1{\dn006 \f10 \fs13 =} I), which is r
ecorded in the Gray code (third bit from the left). Next the
19 4s} bit{\fs18 is} added to the 2s bit of the binary number. The
sum is{\fs18 0} (1{\f10 \fs27 +}{\dn006 1}{\dn006 \f10 \fs13 =} 10) becau
se the carry is
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-232 \f20 \fs18 \cf0 drop
ped. The{\fs18 0} is recorded in the second position from the right in the Gr
ay code. Next the{\fs19 2s} bit is
380 {\f10 \fs14 =}{\fs18 11,} which is recorded in the Gray code
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-233 \f20 \fs18 \cf0 (rig
ht bit). The process is complete. Figure{\fs18 2-9b} shows the binary number
10110being translated into
Gray code number 11101.

68 Convert the Gray code number 1001 to its equivalent binary number.
Figure 2-10a details the
edure. First the left bit (1) is transferred down to the binary line{\fs18 t
o} form the 8s bit. The 8s bit{\fs18 of }
binary number is transferred (see arrow) up above the next Gray code bit, and t
he two are added.
sum is 1 (1{\f10 \fs29 +}{\dn006 \fs18 0}{\dn006 \f10 \fs13 =} 1), which is
written in the 4s bit place in the binary number. The{\fs18 4s} bit (1) i
s
112 {\f10 \fs13 =}{\fs18 1).} This{\fs18 1} is written{\fs18 in}{\fs18 the
} 2s place of the
ry number. The binary{\fs18 2s} bit (1) is added to the right Gray code
bit. The sum is{\fs18 0} (1{\f10 \fs26 +} 1{\dn006 \f10 \fs13 =}{\fs18 10
) }
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-237 \f20 \fs18 \cf0 beca
use the carry{\fs18 is} neglected. This{\fs18 0} is written in the 1s pl
ace of the binary number. Figure 2-10a
s the Gray code number 1001 being translated into its equivalent binar
y number 1110. This
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-244 \f20 \fs18 \cf0 conv
ersion can be verified by looking at decimal line{\fs18 14} in Fig. 2-8.
68 Convert the 6-bit Gray code number 011011 to its 6-bit binary equival
ent. Start at the left and
\par}{\phpg\posx827\pvpg\posy3814\absw9148\absh7108 \sl-249 \f20 \fs18 \cf0 foll
ow the arrows in Fig. 2-lob. Follow the procedure, remembering that a 1{\f10
\fs27 +} 1{\dn006 \f10 \fs13 =} 10. The carry{\fs18 of}{\b \fs18 1 }
is} neglected, and the{\fs18 0} is recorded on the binary line. Figure 2-106 sh
ows that the Gray code number
11 is equal to the.binary number{\fs18 010010. }\par
}
{\phpg\posx835\pvpg\posy7837\absw5453\absh419 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ad
ded to the 1s bit{\fs18 of} the binary number. The sum is{\fs18 1} (1{\f10 \fs
27 +}{\dn006 \fs18 0 }\par
}
{\phpg\posx837\pvpg\posy9470\absw5166\absh431 \f20 \fs18 \cf0 \f20 \fs18 \cf0 th
en added{\fs18 to} the next Gray code bit. The sum is 1{\fs18 (1}{\f10 \fs29
+}{\dn006 \fs18 0 }\par
}
-*{\b \f10 \fs9
1 }\par
}
s10 \cf0 -0
\fi160 {\i0 \f10 \fs15 1 }
\cf0 {\b0\i0 \f20 \fs16 sum }\par
}

{\fs20 1 }
\fs15 1- }\par
}
f0 -1
i180 {\b0 \f20 \fs16 1 }
0 \fi28 {\b0 \f20 \fs16 sum }\par
}
\cf0 I
0 \fs20 1 }
0 \fs16 0 }\par
}
\cf0 0
{\fs16 sum }\par
}
{\phpg\posx5257\pvpg\posy12133\absw828\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 G
ray{\fs16 code }\par
}
\par
}
\par
}
inary \par
}
J
\fi77 {\b \f20 \fs14 (a) }\par
}
- \par
}
inary \par
}
\cf0 (h) \par
}
\cf0 Fig.{\f10 \fs15 2-10} Gray{\b0 \fs16 code-to-binary}{\b0 \fs16
con
versions }\par
}
.{\fs17 21 }\par
}

NARY{\fs17 CODES }\par
}
f0 23 \par
}
LVED PROBLEMS \par
}
f0 2.10 \par
}
he letters and numbers{\fs19 XS3} stand for
{\b \fs17 Solution: }
61 {\fs17 XS3}{\fs17 stands}{\fs17 for}{\fs17 the}{\fs17 excess-3code. }\p
ar
}
e
fs17 Solution: }\par
}
{\phpg\posx5701\pvpg\posy1679\absw145\absh181 \f10 \fs15 \cf0 \f10 \fs15 \cf0 \par
}
de. \par
}
f0 2.11 \par
}
{\phpg\posx2459\pvpg\posy2949\absw5617\absh211 \f10 \fs9 \cf0 \f10 \fs9 \cf0 .{\
f20 \fs18 (8421,}{\f20 \fs18 XS3)}{\f20 \fs18 BCD}{\f20 \fs18 code}{\f20 \fs
18 is}{\f20 \fs18 an}{\f20 \fs18 example}{\f20 \fs18 of}{\f20 \fs18 a}{\f2
0 \fs18 nonweighted}{\f20 \fs18 code. }\par
}
he{\b XS3}{\fs17 BCD}{\fs17 code}{\fs17 is}{\fs17 an}{\fs17 example}{\fs
17 of}{\fs17 a}{\fs17 nonweighted}{\fs17 code. }\par
}
f0 2.12 \par
}
e
}
\cf0 (Gray, XS3) code is a BCD code.
{\fs17 The}{\fs17 XS3}{\fs17 code}{\fs17 is}{\fs17 a}{\fs17 BCD}{\fs17 c
ode. }\par
}
f0 2.13 \par
}

onvert the following decimal numbers to their{\fs19 XS3} code equivalents:
\f10 \fs16 (a)}{\fs18
9,}{\i \fs19
(b:)} 18,{\f10 \fs16
(c)}{\fs19
37,}{\i \f10 \fs18
(}{\i \f10 \fs18 d}{\i \f10 \fs18 )} 42,{\i \fs19
(}{\i \fs19 e}{\i \fs19 )}{\fs19
650. }
\fs17 Solution: }
60 {\fs17 The}{\fs17 XS3}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs17
decimal}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 ( a ){\i0 \fs16
9}{\i0\dn006 \f10 \fs11 =}{\i0 \fs17 1100 }
\i0 \fs17 (6)}{\i0 \fs17
18}{\i0\dn006 \f10 \fs11 =}{\i0 \fs17 0100101}{\i
0 \fs17 1 }\par
}
cf0 (c) \par
}
7{\f10 \fs13 =}{\fs16 01}101010 \par
}
s16 \cf0 ( e ){\b0\i0 \fs17
650}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 \fs17 1
00110000011 }\par
}
\cf0 ( d ){\i0 \f20 \fs17
42}{\i0 \fs13 =}{\i0 \f20 \fs17 01110101 }\par
}
f0 2.14 \par
}
\cf0 Convert the following 8421 BCD numbers to their XS3 code equivalents:
58 {\i \f10 \fs16 (a)} 0001,{\i \fs18
(b)} 0111,{\f10 \fs16
(c)}
011OOOO0,{\i \f10 \fs17
(d)} 00101001,{\i \fs19
(}{\i \fs19 e}{\i \fs19
)} IOOOOIOO.
0 \fs16 .}{\b \fs17
Solution: }
11 {\fs17 The}{\fs17 XS3}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs17
8421}{\fs17 BCD}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 ( a ){\i0 \f20 \fs17
0001}{\i0 \fs13 =}{\i0 \f20 \fs17 0100 }
\f20 \fs16 (}{\f20 \fs16 b}{\f20 \fs16 )}{\i0 \f20 \fs17
0111}{\i0 \fs13 =
}{\i0 \f20 \fs17 1010 }\par
}
cf0 (c) \par
}
1100000{\f10 \fs13 =}{\fs17 10010011 }\par
}
\cf0 ( e ){\i0 \fs17
10000100}{\i0 \f10 \fs13 =}{\i0 \fs17 10110111 }\par
}
s16 \cf0 ( d ){\b0\i0 \f20 \fs17
00101001}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs1
7 01011100 }\par
}
f0 2.15 \par
}
onvert the following XS3 numbers to their decimal equivalents:
\f10 \fs16 (}{\i \f10 \fs16 a}{\i \f10 \fs16 )} 0011,{\i \fs18
(}{\i \fs1
8 b}{\i \fs18 )} 01100100,{\b\i \fs18
(}{\b\i \fs18 c}{\b\i \fs18 )}
11001011,{\i \f10 \fs17
(d)}
10011010,{\i \fs19
(}{\i \fs19 e}{\i \fs
19 )}{\b \f30 \fs20 IOOOOIOI. }
\fs17 Solution: }
55 {\fs17 The}{\fs17 decimal}{\fs17 equivalents}{\fs17 of}{\fs17 the}{\fs1
7 XS3}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
\cf0 ( a ){\i0 \fs17
0011}{\i0 \f10 \fs13 =}{\i0 \fs16 0 }
{\fs16 (}{\fs16 h}{\fs16 )}{\i0 \fs17
01}{\i0 \fs16 100100}{\i0 \f10 \fs13
=}{\i0 \fs17 31 }\par
}
c) \par
}
11001011{\dn006 \f10 \fs11 =}{\fs16 98 }\par
}
\cf0 ( e ){\i0 \fs17
10000101}{\i0\dn006 \f10 \fs11 =}{\i0 \fs17 52 }\par
}
\cf0 ( d ){\i0 \f20 \fs17
10011010}{\i0 \fs13 =}{\i0 \f20 \fs16 67 }\par
}
cf0 2.16 \par
}
he
{\b \fs17 Solution: }\par
}
8 \cf0 (Gray,{\fs19 XS3)} code is usually used in arithmetic applications in d
igital circuits.
{\fs17 The}{\fs17 XS3}{\fs17 code}{\fs17 is}{\fs17 usually}{\fs17 used}{
\fs17 in}{\fs17 arithmetic}{\fs17 applications. }\par
}
cf0 2.17 \par
}
Convert the following straight binary numbers to their Gray code equivalents:
\i \fs18 (}{\b\i \fs18 a}{\b\i \fs18 )} 1010,{\i \fs18

(b)} 10000,{\b\i
\fs18
(}{\b\i \fs18 c}{\b\i \fs18 )} 10001,{\i \f10 \fs17
(}{\i \f10
\fs17 d}{\i \f10 \fs17 )} 10010,{\i
(}{\i e}{\i )} 10011.
\fs17 Solution: }
360 {\fs17 The}{\fs17 Gray}{\fs17 code}{\fs17 equivalents}{\fs17 of}{\fs17
the}{\fs17 binary}{\fs17 numbers}{\fs17 are}{\fs17 as}{\fs17 foIlows: }\
par
}
\cf0 ( a ){\i0 \fs17
1010}{\i0 \f10 \fs13 =}{\i0 \fs16 11}{\i0 11 }
{\b \fs16 (}{\b \fs16 b}{\b \fs16 )}{\i0 \fs17
10000}{\i0 \f10 \fs13 =}{\i
0 \fs17 11000 }\par
}
\cf0 ( c ){\i0 \fs17
10001}{\i0 \f10 \fs13 =}{\i0 \fs17 11001 }
{\b \fs17 (}{\b \fs17 d}{\b \fs17 )}{\i0 \fs17
10010}{\i0\dn006 \f10 \fs11
=}{\i0 \fs17 11011 }\par
}
fs16 \cf0 ( e ){\b0\i0 \fs17
10011}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 \fs17
11010 }\par
}
par
}
cf0 BINARY{\b0 \fs17 CODES }\par
}
}
f0 2.18 \par
}
onvert the following Gray code numbers to their straight binary equivaIents:
\fs18 (}{\i \fs18 a}{\i \fs18 )} 0100,{\b\i \fs19
(b)} 11111,{\i \fs18
(}{\i \fs18 c}{\i \fs18 )} 10101,{\i \fs18
(}{\i \fs18 d}{\i \fs18 )
} 110011,{\i \fs18
(}{\i \fs18 e}{\i \fs18 )} 011100.
\fs17 Solution: }
60 {\b \fs17 The}{\b \fs17 binary}{\b \fs17 equivalents}{\b \fs17 of}{\b \fs1
7 the}{\b \fs17 Gray}{\b \fs17 code}{\b \fs17 numbers}{\b \fs17 are}{\b
\fs17 as}{\b \fs17 follows: }\par
}
s14 \cf0 (a){\b0\i0 \f20 \fs17
0100}{\b0\i0 \fs14 =}{\b0\i0 \f20 \fs17 011
1 }
{\f20 \fs17 (b)}{\b0\i0 \f20 \fs17
11111}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs17
10101 }\par
}

s16 \cf0 ( c ){\b0\i0 \fs16
10101}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs16 11001
}
{\fs17 (}{\fs17 d}{\fs17 )}{\b0\i0 \fs16
110011}{\b0\i0 \f10 \fs14 =}{\b
0\i0 \fs16 100010 }\par
}
s16 \cf0 ( e ){\b0\i0 \fs16
011100}{\b0\i0 \f10 \fs14 =}{\b0\i0 \fs17 0101}
{\b0\i0 \fs16 11 }\par
}
f0 2.19 \par
}
The Gray code's most important characteristic{\fs18 is} that, when the
count{\fs19 is} incremented by
\par}{\phpg\posx1471\pvpg\posy3248\absw8477\absh1180 \sl-246 \f20 \fs18 \cf0 1,{
\f10 \fs19 -}(more than, only){\fs19 1} bit will change state.
\fs16 Solution: }
355 {\b \fs17 The}{\b \fs17 Gray}{\b \fs17 code's}{\b \fs17 most}{\b \fs17 i
mportant}{\b \fs17 characteristic}{\b \fs17 is}{\b \fs17 that,}{\b \fs17 whe
n}{\b \fs17 the}{\b \fs17 count}{\b \fs17 is}{\b \fs17 incremented}{\b \fs17
by}{\fs17 I,}{\b \fs17 only}{\fs16 1}{\b \fs17 bit }
\fs17 will}{\b \fs17 change}{\b \fs17 state. }\par
}
\cf0 2-4{\fs19
ALPHANUMERIC}{\fs19 CODES }
fi370 {\b0 \fs18 Binary} OS{\b0 \fs18 and}{\b0 \fs18 1s}{\b0 \fs18 have}{\
b0 \fs18 been}{\b0 \fs18 used}{\b0 \fs18 to}{\b0 \fs18 represent}{\b0 \f
s18 various}{\b0 \fs18 numbers}{\b0 \fs18 to}{\b0 \fs18 this}{\b0 \fs18
point.}{\b0 \fs18 Bits}{\b0 \fs18 can}{\b0 \fs18 also}{\b0 \fs18 be }
\b0 \fs18 coded}{\b0 \fs18 to}{\b0 \fs18 represent}{\b0 \fs18 letters}{\b0
\fs19 of}{\b0 \fs18 the}{\b0 \fs18 alphabet,}{\b0 \fs18 numbers,}{\b0 \fs
18 and}{\b0 \fs18 punctuation}{\b0 \fs18 marks.}{\b0 \fs18 One}{\b0 \fs1
8 such}{\b0 \fs18 7-bit}{\b0 \fs18 code}{\b0 \fs18 is }
\b0 \fs18 the}{\b0\i American}{\b0\i Standard}{\b0\i Code}{\b0\i for}{\b0
\i Information}{\b0\i Interchange}{\fs18 (ASCII,}{\b0 \fs18 pronounced}{\
b0 \fs18 "ask-ee"),}{\b0 \fs18 shown}{\b0 \fs18 in }
\b0 \fs18 Fig.}{\b0 \fs18 2-11.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 t
he}{\b0 \fs18 letter}{\fs18 A}{\b0 is}{\b0 \fs18 represented}{\b0 \fs18 by
}{\b0 \fs18 1000001,whereas}{\b0 \fs18 B}{\b0 \fs18 in}{\b0 \fs18 the}{\fs1
8 ASCII}{\b0 \fs18 code}{\b0 is}{\b0 1000010. }\par
}
\cf0 Character
f0 \fi166 Space
fi323 {\b0 \f10 \fs15 ! }
fi293 {\i \fs5 I}{\i \fs5 / }
f0 \fi316 {\b0 \f10 \fs15 # }

fi293 {\b0 \f10 \fs14 $ }
fi310 {\b0 \f10 \fs16 "/, }
fi288 {\b0 \f10 \fs16 & }
fi293 {\i \fs5 I }
f0 \fi293 {\b0 \f10 \fs16 ( }
fi299 {\b0 \f10 \fs16 ) }
fi293 {\b0 \f10 \fs20 * }
fi318 {\b0 \f10 \fs27 + }\par
}
9 \par
}
\cf0 I
{\i0 \f20 \fs17 0 }
\fi30 {\i0 \f20 \fs16 1 }
{\b\i0 \f20 \fs17 2 }
{\b\i0 \f20 \fs16 3 }
{\b\i0 \fs15 4 }
{\b \fs15 5 }
{\b \f20 \fs16 6 }
{\b\i0 \f20 \fs16 7 }
{\i0 \f20 \fs17 8 }
{\b\i0 \f20 \fs16 9 }\par
}
cf0 ASCII \par
}
cf0 EBCDIC \par
}
10{\f10 \fs22 m}
0100{\i \f30 \fs25 oooo }\par
}
010{\fs17
oO01 }
0010
0011
0100
s17 010}
0101
0110
0111
1oO0
1001
1010
1011
1100
1101
1110
1111
461 {\i \f30 \fs25 oooo }
Oool
0010
0011
0100
0101
0110
0111
1oO0
1001 \par
}
11 \par
}
0101
1010
1{\fs16
1111 }
1
1011
1
1011
0
1100
1
0000
1
1101
0
1101
1
1101
1
1100
0
1110
0
1011
0{\fs17
0000 }
0
1011
0{\fs17
oO01 }
784 {\f10 \fs1 ~~ }
36 {\fs16 1111}{\fs17
0000 }
36 1111
oO01 \par
}
111
\par
}
010
\par
}
1111{\fs16
0100 }
fs16 1111}{\fs16
0101 }
11{\fs16
0110 }
11{\fs16
0111 }
11{\fs16
1oO0 }
fs16 1111}{\fs16
1001 }\par
}
\cf0 Character
f0 \fi296 {\f10 \fs15 A }
fi293 {\fs17 B }
fi283 {\fs16 C }
fi296 {\fs17 D }
fi287 {\fs17 E }
fi291 {\fs17 F }
fi287 {\i \fs16 G }
fi297 {\fs17 H }
fi287 {\fs17 I }
fi281 J
fi297 {\fs17 K }
fi296 {\fs17 L }
fi296 {\fs17 M }
fi296 {\fs16 N }
fi287 {\b0\i \f10 \fs16 0 }
fi291 {\fs17 P }
fi291 {\fs21 Q }
fi293 {\f30 \fs19 R }
fi283 {\fs16 S }
fi287 {\b0 \fs17 T }
fi287 U
fi283 {\b0 \fs23 v }
fi287 {\f30 \fs25 w }
fi283 {\f30 \fs19 X }
fi287 {\f30 \fs19 Y }
fi283 {\b0 \f10 \fs21 z }\par
}
0 \fs17 \cf0 ASCII
cf0 {\b0 \fs16 100}{\b0 \fs16
oO01 }
{\b0 \fs16 100}{\b0 \fs16
0010 }
{\b0 \fs16 100}{\b0 \fs16
0011 }
{\b0 \fs16 100}{\b0 \fs16
0100 }
{\b0 \fs16 100}{\b0 \fs16
0101 }
{\b0 \fs16 100}{\b0 \fs16
0110 }
{\b0 \fs16 100}{\b0 \fs16
0111 }
{\b0 \fs16 100}{\b0 \fs16
1oO0 }

{\b0 \fs16 100}{\b0 \fs16
1001 }
{\b0 \fs16 100}{\b0 \fs16
1010 }
{\b0 \fs16 100}{\b0 \fs16
1011 }
{\b0 \fs16 100}{\b0 \fs16
1100 }
{\b0 \fs16 100}{\b0 \fs16
1101 }
{\b0 \f10 \fs16 100}{\b0 \fs16
1110 }
{\b0 \fs16 100}{\b0 \fs16
1111 }
{\b0 \fs16 101 }
}{\phpg\posx6681\pvpg\posy6827\absw1300\absh5659 \b \f20 \fs17 \cf0 \fi1 {\b0\i
\f30 \fs25 oooo }
cf0 {\b0 \fs16 101}{\b0 \fs16
oO01 }
{\b0 \fs16 101}{\b0 \fs16
0010 }
{\b0 \fs16 101}{\b0 \fs16
0011 }
{\b0 \fs16 101}{\b0 \fs16
0100 }
{\b0 \fs16 101}{\b0 \fs16
0101 }
{\b0 \fs16 101}{\b0 \fs16
0110 }
{\b0 \fs16 101}{\b0 \fs16
0111 }
{\b0 \fs16 101}{\b0 \fs16
loo0 }
{\b0 \fs16 101}{\b0 \fs16
1001 }
{\b0 \fs16 101}{\b0 \fs16
1010 }\par
}
\fs17 \cf0 EBCDIC
f0 {\b0 \fs16 1100}{\b0 \fs16
Oool }
\b0 \fs16 1100}{\b0 \fs16
0010 }
\b0 \fs16 1100}{\b0 \fs16
0011 }
\b0 \fs16 1100}{\b0 \fs16
0100 }
\b0 \fs16 1100}{\b0 \fs16
0101 }
\b0 \fs16 1100}{\b0 \fs16
0110 }
\b0 \fs16 1100}{\b0 \fs16
0111 }
\b0 \fs16 1100}{\b0 \fs16
1000 }
\b0 \fs16 1100}{\b0 \fs16
1001 }
\b0 \fs16 1101.}{\b0 \fs17

oO01 }
\b0 \fs16 1101}{\b0 \fs16
0010 }
\b0 \fs16 1101}{\b0 \fs16
0011 }
\b0 \fs16 1101}{\b0 \fs16
0100 }
\b0 \fs16 1101}{\b0 \fs16
0101 }
\b0 \fs16 1101}{\b0 \fs16
0110 }
\b0 \fs16 1101}{\b0 \fs16
0111 }
f0 {\b0 \fs16 1101}{\b0 \fs16
1000 }
\b0 \fs16 1101}{\b0 \fs16
1001 }
\b0 \fs16 1110}{\b0 \fs16
0010 }
\b0 \fs16 1110}{\b0 \fs16
0011 }
\b0 \fs16 1110}{\b0 \fs16
0100 }
\b0 \fs16 1110}{\b0 \fs16
0101 }
\b0 \fs16 1110}{\b0 \fs16
0110 }
\b0 \fs16 1110}{\b0 \fs16
0111 }
\b0 \fs16 1110}{\b0 \fs16
1000 }
\b0 \fs16 1110}{\b0 \fs16
1001 }\par
}
\cf0 Fig.{\fs16 2-11}{\fs17
Alphanumeric}{\fs17 codes }\par
}
.{\f10 \fs16 21 }\par
}
NARY{\fs17 CODES }\par
}
\par
}
he ASCII code is used extensively in small computer systems to transl
ate from the keyboard
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-237 \f20 \fs19 \cf0 char
acters to computer language. The chart in Fig. 2-11 is not{\f10 \fs17 ,a} comp
lete list of all the combinations
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-238 \f20 \fs19 \cf0 in t
he ASCII code.
64 Codes that can represent both letters and numbers are called{\b\i \f
s19
alphanumeric}{\b\i \fs19 codes.} Another
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-234 \f20 \fs19 \cf0 alph
anumeric code that is widely used is the{\b\i \fs19 Extended}{\b\i \fs1

9 Binary-Coded}{\b\i \fs19 Decimal}{\b\i \fs19 Interchange}{\b\i \fs19 C
ode }
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-237 \f20 \fs19 \cf0 (EBC
DIC, pronounced "eb-si-dik"). Part{\fs19 of} the EBCDIC code is shown in
Fig. 2-11. Note that the
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-241 \f20 \fs19 \cf0 EBCD
IC code is an 8-bit code and therefore can have more variations and characters t
han the ASCII
can have. The EBCDIC code is used in many larger computer systems.
60 The alphanumeric ASCII code is the modern code for getting informat
ion into and out of
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-231 \f20 \fs19 \cf0 micr
ocomputers. ASCII is used when interfacing computer keyboards, printers,
and video displays.
\par}{\phpg\posx841\pvpg\posy1354\absw9496\absh4324 \sl-235 \f20 \fs19 \cf0 ASCI
I has become the standard input/output code for microcomputers.
66 Other alphanumeric codes that you may encounter are:
78 {\fs18 1.} 7-bit BCDIC{\f10 \fs16 (}{\b\i \fs19 Binary-Coded}{\b\i \fs19
Decimal}{\b\i \fs19 Interchange}{\b\i \fs19 Code). }
64 2.
8-bit EBCDIC{\b\i \fs19 (Extended}{\b\i \fs19 Binary-Coded}{\b\i \
fs19 Decimal}{\b\i \fs19 Interchange}{\b\i \fs19 Code).} Used{\fs19 on}
some IBM
12 equipment.
60 {\fs19 3.}
7-bit Selectric. Used to control the spinning ball on IBM Sel
ectric typewriters.
60 {\fs18 4.}
12-bit Hollerith. Used on punched paper cards.
{\f10 \fs16 SOLVED}{\f10 \fs17 PROBLEMS }\par
}
cf0 2.20{\b0 \fs19
Binary}{\b0 \fs19 codes}{\b0 \fs19 that}{\b0 \fs19 can
}{\b0 \fs19 represent}{\b0 \fs19 both}{\b0 \fs19 numbers}{\b0 \fs19 and}{\b
0 \fs19 letters}{\b0 \fs19 are}{\b0 \fs19 called }
0 \fi598 {\fs16 Solution: }
i946 {\b0 \fs17 Alphanumeric}{\b0 \fs17 codes}{\b0 \fs17 can}{\b0 \fs17 repre
sent}{\b0 \fs17 both}{\b0 \fs17 numbers}{\b0 \fs17 and}{\b0 \fs17 letters
. }\par
}
f0 2.21 \par
}
The following are abbreviations for what?
\i \fs19 (}{\b\i \fs19 a}{\b\i \fs19 )} ASCII{\i \fs18
(b)} EBCDIC
s16 (a)}{\fs17
ASCII}{\f10 \fs14 =}{\fs17 American}{\fs17 Standard}{\fs17
Code}{\fs17 for}{\fs17 Information}{\fs17 Interchange }

\fs16 (b)}{\fs17
EBCDIC}{\f10 \fs13 =}{\fs17 Extended}{\fs17 Binary-Code
d}{\fs17 Decimal}{\fs17 Interchange}{\fs17 Code }\par
}
des. \par
}
\cf0 2.22{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 2-1
2.}{\b0 \fs19 The}{\b0 \fs19 ASCII}{\b0 \fs19 keyboard-encoder}{\b0 \fs19
output}{\b0 \fs19 would}{\b0 \fs19 be }
fi598 {\b0 \fs19 typewriter-like}{\b0 \fs19 keyboard}{\b0 \fs19 were}{\b0 \fs
19 pressed. }
f0 \fi6195 {\b0 \fs17 To }
fi5931 {\b0 \fs17 computer }\par
}
ystem \par
}
f0 MSR \par
}
f the{\fs19 K} on the \par
}
{\phpg\posx7635\pvpg\posy9979\absw1944\absh1152 \f30 \fs205 \cf0 \f30 \fs205 \cf
0 I \par
}
f0 LSB \par
}
\cf0 Solution:
\fi351 {\b0 \fs17 The}{\b0 \fs17 ASCII}{\b0 \fs17 output}{\b0 \fs17 would}{\b
0 \fs17 be}{\b0 \fs17 1001011}{\b0 \fs17 if}{\b0 \fs17 the}{\b0 \fs17 K
}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 keyboard}{\b0 \fs17 were}{\b0 \fs
17 pressed. }\par
}
0 4 \par
}
Message for keyboard operator{\dn006 \f10 \fs8
--+ }\par
}
{\dn006 \f20 \fs17 encoder }\par
}
{\phpg\posx6305\pvpg\posy11311\absw238\absh371 \f20 \fs33 \cf0 \f20 \fs33 \cf0 b
\par
}
U \par
}
nput \par
}
\cf0 L
{\fs17 output }\par
}
0 J \par
}
Fig.{\b \f10 \fs15 2-12}{\fs17
ASCII}{\fs17 keyboard-encoder}{\fs17 system
}\par
}
0 26 \par
}
NARY CODES \par
}
AP.{\fs17 2 }\par
}
cf0 2.23{\b0
Refer}{\b0 \fs19 to}{\b0 Fig.}{\b0 2-12.}{\b0 List}{\b0 th
e}{\b0 12}{\fs19 ASCII}{\b0 keyboard-encoder}{\b0 outputs}{\b0 for}{\b0 e
ntering}{\b0 the}{\b0 message}{\b0 "pay }
i603 {\b0 \fs19 $1000.00." }
i953 {\b0 \fs17 The}{\fs17 ASCII}{\b0 \fs17 codes}{\b0 \fs17 for}{\b0 \fs17
the}{\b0 \fs17 characters}{\b0 \fs17 in}{\b0 \fs17 the}{\b0 \fs17 mes
sage}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
\cf0 (a){\i0 \f20 \fs17
P}{\i0 \fs13 =}{\i0 \f20 \fs17 1010000 }
\f20 \fs17 (b)}{\b\i0 \f20 \fs17
A}{\i0 \fs13 =}{\i0 \f20 \fs17 1000001 }
\i0 (c)}{\b\i0 \f20 \fs17
Y}{\i0 \fs11 =}{\i0 \f20 \fs17 1011001 }\par
}
e
}
s16 \cf0 ( d ){\b0\i0 \f20 \fs17
Space}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs17
0100000 }
{\f20 \fs17 (}{\f20 \fs17 e}{\f20 \fs17 )}{\b0\i0 \fs15
$}{\b0\i0\dn006 \
fs11 =}{\b0\i0 \f20 \fs17 0100100 }
{\b0\i0 \f20 \fs15 (f)}{\b0\i0 \f20 \fs17
1}{\b0\i0\dn006 \fs11 =}{\b0\i0
\f20 \fs17 0110001 }\par
}
\cf0 ( g ){\i0 \f20 \fs16

O}{\i0 \fs11 =}{\i0 \f20 \fs17 OZIOOOO }
\b \f20 \fs17 (}{\b \f20 \fs17 h}{\b \f20 \fs17 )}{\i0 \f20 \fs16
0}{\i0\d
n006 \fs11 =}{\i0 \f20 \fs17 0110000 }
\b \f30 \fs17 (}{\b \f30 \fs17 i}{\b \f30 \fs17 )}{\i0 \f20 \fs17
0}{\i0\
dn006 \fs13 =}{\i0 \f20 \fs17 0110000 }\par
}
\cf0 ( j ){\i0 \fs16
.}{\i0 \fs13 =}{\i0 \f20 \fs17 OIO111O }
\b \f20 \fs17 (}{\b \f20 \fs17 k}{\b \f20 \fs17 )}{\i0 \f20 \fs17
0}{\i0\d
n006 \fs11 =}{\i0 \f20 \fs17 0110000 }
\b \f30 \fs19 (I)}{\i0 \f20 \fs17
0}{\i0\dn006 \fs13 =}{\i0 \f20 \fs17 01
10000 }\par
}
f0 2.24 \par
}
\cf0 code{\fs19 is} a 12-bit alphanumeric code used{\fs19 on} punched paper
cards.
{\fs17 The}{\fs17 12-bit}{\fs17 Hollerith}{\fs17 code}{\fs17 is}{\fs17 u
sed}{\fs17 on}{\fs17 punched}{\fs17 cards. }\par
}
f0 2.25 \par
}
e 7-bit
\par}{\phpg\posx1451\pvpg\posy4675\absw857\absh728 \sl-242 \f20 \fs18 \cf0 ers.
}
{\phpg\posx3051\pvpg\posy4674\absw6657\absh213 \f20 \fs18 \cf0 \f20 \fs18 \cf0 c
ode{\fs19 is} considered the industry standard for input/output on microcompu
t- \par
}
\cf0 The 7-bit ASCII (American Standard Code for Information Interchan
ge) code is considered the
\par}{\phpg\posx1457\pvpg\posy5543\absw8246\absh385 \sl-215 \f20 \fs17 \cf0 indu
stry standard for microcomputer inputs and outputs. \par
}
f0 2.26 \par
}
2 \cf0 Supplementary Problems
\fi30 {\f20 \fs17 Electronic}{\f20 \fs17 devices}{\f20 \fs17 that}{\f20 \fs17
translate}{\f20 \fs17 from}{\f20 \fs17 one}{\f20 \fs17 code}{\f20 \fs17
to}{\f20 \fs17 another}{\f20 \fs17 are}{\f20 \fs17 called }
i \f20 \fs17 Ans.}{\i \fs14
(a)}{\f20 \fs17
encoders}{\i \f20 \fs16
(}{\i \f20 \fs16 b}{\i \f20 \fs16 )}{\f20 \fs17
decoders }\par
}
{\phpg\posx6955\pvpg\posy7483\absw1719\absh181 \f10 \fs15 \cf0 \f10 \fs15 \cf0 -
- \par
}
cf0 ( a ) \par
}
{\phpg\posx7675\pvpg\posy7379\absw175\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 or
\par
}
cf0 ( b ) \par
}
f0 2.27 \par
}
onvert the following 8421 BCD numbers to their decimal equivalents:
\f10 \fs14 (a)}
10010000,{\i \fs16
(}{\i \fs16 b}{\i \fs16 )}
111111
11,{\fs16
(c)}
0111.0011,{\i \f10 \fs16
(}{\i \f10 \fs16 d}{\i \f10
\fs16 )}
01100001.00000101. \par
}
s17 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0
10010000}{\b0\i0\dn006 \f10 \fs
11 =}{\b0\i0 \fs16 90 }
\fi528 {\b0 \fs17 (b)}{\b0\i0
11111111}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0
ERROR}{\b0\i0 (no}{\b0\i0 such}{\b0\i0 BCD}{\b0\i0 number) }\par
}
) \par
}
111.0011{\f10 \fs11 =}{\fs17 7.3 }\par
}
\cf0 ( d ){\i0 \f20 \fs17
01100001.00000101}{\i0 \fs13 =}{\i0 \f20 \fs17 6
1.05 }\par
}
f0 2.28 \par
}
onvert the following decimal numbers to their 8421 BCD equivalents:
\f10 \fs14 (a)}
10,{\fs17
(6)}
342,{\fs16
(c)}
679.8,{\i \f10 \
fs16
(}{\i \f10 \fs16 d}{\i \f10 \fs16 )}
500.6. \par
}
s17 \cf0 Ans.{\b0 \f10 \fs13
(a)}{\b0\i0
10}{\b0\i0 \f10 \fs13 =}{\b0\i
0 00010000 }
\fi532 {\b0 \fs16 (b)}{\b0\i0
342}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 00110
1000010 }\par
}
\cf0 (c){\i0 \f20 \fs17
679.8}{\i0 \fs13 =}{\i0 \f20 \fs17 011001111001.10
00 }
\fs16 (}{\fs16 d}{\fs16 )}{\i0 \f20 \fs17
500.6}{\i0 \fs13 =}{\i0 \f20 \f
s17 010100000000.0110 }\par
}
cf0 2.29 \par
}
Convert the following binary numbers to their 8421 BCD equivalents: \par
}
\cf0 (a){\i0 \f20 \fs17
10100,}{\f20 \fs17
(}{\f20 \fs17 b}{\f20 \fs17
)}{\i0 \f20 \fs17
11011.2,}{\i0 \fs14
(c) }
{\b \f20 \fs17 Ans.}{\fs14
(a)}{\i0 \f20 \fs17
10100}{\i0\dn006 \fs11 =
}{\i0 \f20 \fs17 00100000 }\par
}
100000.01,{\i \f10 \fs16
(}{\i \f10 \fs16 d}{\i \f10 \fs16 )}
111011.11
.
561 {\b\i \fs16 (}{\b\i \fs16 c}{\b\i \fs16 )}
100000.01{\dn006 \f10 \fs11
=}{\fs16 001}10010.00100101 \par
}
\cf0 (b){\i0 \fs17
11011.1}{\i0 \f10 \fs13 =}{\i0 \fs17 00100111.0101 }\pa
r
}
\cf0 ( d ){\i0 \f20 \fs17
111011.11}{\i0\dn006 \fs11 =}{\i0 \f20 \fs17 01
011001.01110101 }\par
}
cf0 2.30 \par
}
Convert the following 8421 BCD numbers to their binary equivalents:
\f10 \fs14 (a)}
01011000,{\i \fs16
(}{\i \fs16 h}{\i \fs16 )} 000100
000000,{\fs16
(c)}
1001.01110IO1,{\b\i \f10 \fs16
(}{\b\i \f10 \fs16
d}{\b\i \f10 \fs16 )}
0011.0000011000100101. \par
}
fs17 \cf0 Ans.{\b0 \f10 \fs13
(a)}{\b0\i0
01011000}{\b0\i0\dn006 \f10 \f
s11 =}{\b0\i0 111010 }
0 \fi531 {\b0 \fs16 (b)}{\b0\i0
000100000000}{\b0\i0\dn006 \f10 \fs11 =}{\b
0\i0 1100100 }\par
}
(c){\fs17
1001.01110101}{\f10 \fs13 =}{\fs17 1001.11 }
\i \f10 \fs16 (}{\b\i \f10 \fs16 d}{\b\i \f10 \fs16 )}{\fs17
0011.00000110
00100101}{\f10 \fs13 =}{\fs17 11.0001 }\par
}
cf0 2.31
0 2.32
0 {\fs16 2.33 }\par
}
The 4221 BCD equivalent of decimal{\b \fs17 74} is

The 5421 BCD equivalent of decimal 3210{\fs16 is }\par
}
{\phpg\posx5513\pvpg\posy12347\absw73\absh229 \f10 \fs19 \cf0 \f10 \fs19 \cf0 .
\par
}
\par
}
fs17 \cf0 Ans.{\b0\i0 \fs16
1101}{\b0\i0 1000 }
\cf0 \fi177 Ans.{\b0\i0
0011001000010000 }\par
}
\cf0 The BCD code{\fs17 is} convenient when translations must be made{\
fs16 to }
\i Ans.}
decimal \par
}
(binary, decimal) numbers. \par
}
.{\fs17 21 }\par
}
NARY CODES \par
}
f0 27 \par
}
f0 2.34
2.35 \par
}
Excess-3" code is often shortened to \par
}
par
}
17 \cf0 Ans.{\i0 \fs17
XS3 }\par
}
onvert the following decimal numbers to their{\b XS3} code equivalents:
\f10 \fs15 (a)}{\b \fs17
7,}{\i \fs16
(b:)} 16,{\b\i \fs16
(c)}{\b
32,}{\b\i \fs17
(}{\b\i \fs17 d}{\b\i \fs17 )}{\b \fs17
4089. }\par
}
s17 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\i0 \fs17
7}{\b0\i0\dn006 \f10 \fs11
=}{\b0\i0 \fs17 1010 }
\fi531 {\b0 \fs17 (b)}{\b0\i0 \fs17
16}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17
01001001 }\par
}
\cf0 (c){\b\i0 \f20 \fs17
32}{\i0 \fs13 =}{\i0 \f20 \fs17 01100101 }
\b \f20 \fs17 (}{\b \f20 \fs17 d}{\b \f20 \fs17 )}{\b\i0 \f20 \fs17
4089}{\
i0\dn006 \fs11 =}{\i0 \f20 \fs17 0111001110111100 }\par
}
f0 2.36 \par
}
onvert the following XS3 numbers to their decimal equivalents:
\f10 \fs15 (a)}
1100,{\i
(b)} 10101000,{\b\i \fs16
(}{\b\i \fs16 c
}{\b\i \fs16 )}
100001110011,{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 d}{\b\
i \f10 \fs16 )}
0100z01101100101. \par
}
s17 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0 \fs17
1100}{\i0 =}{\i0 9 }
\fi531 {\b0 \fs17 (b)}{\b0\i0 \fs17
10101000}{\b0\i0 \f10 \fs13 =}{\b0\i0 \
fs17 75 }\par
}
15 \cf0 (c) \par
}
00001110011{\f10 \fs13 =}{\b \fs17 540 }\par
}
s17 \cf0 ( d ){\b0\i0 \fs17
0100101101100101}{\b0\i0 \f10 \fs13 =}{\b0\i0 \f
s17 1832 }\par
}
f0 2.37 \par
}
f0 2.38 \par
}
\cf0 Convert the following straight binary numbers to their Gray code eq
uivalents:
28 {\i \f10 \fs15 (a)}
0110,{\i
(}{\i b}{\i )} 10100,{\i \f10 \fs15
(c)}
10101,{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 d}{\b\i \f10 \fs16 )}
10110.
\i \fs17 Ans.}{\i \f10 \fs14
(a)}{\fs17
0110}{\f10 \fs13 =} 0101{\i
(b)} 10100{\f10 \fs13 =} 11110{\b\i \fs17
(}{\b\i \fs17 c}{\b\i \fs17
)}
10101{\f10 \fs13 =}{\fs17 11111}{\b\i \f10 \fs16
(d)}
10110{\f10 \f
s13 =} 11101
\fi28 Convert the following Gray code numbers to their straight binary eq
uivalents:
24 {\b\i \fs16 (}{\b\i \fs16 a}{\b\i \fs16 )} 0001,{\i \f10 \fs16
(b)}
11100,{\b\i \fs16
(c)}
10100,{\b\i \fs17
(}{\b\i \fs17 d}{\b\i \fs
17 )}
10101.
\i \fs17 Ans.}{\i \f10 \fs14

(a)}
0001{\dn006 \f10 \fs11 =} 0001{\i
(b)} 11100{\f10 \fs13 =} 10111{\b\i \fs16
(}{\b\i \fs16 c}{\b\i \fs16 )
}
10100{\f10 \fs13 =} 11000{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 d}{\b\i
\f10 \fs16 )}
10101{\f10 \fs13 =} 11001 \par
}
\cf0 EBCDIC is a(n)
\i \fs17 Ans.}{\b \fs17
8 }
\fi24 The 7-bit alphanumeric
24 computers.
\i \fs17 Ans.}
ASCIl \par
}
{\phpg\posx3397\pvpg\posy5703\absw4258\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 bit alphanumeric code used in some IBM equipment. \par
}
f0 2.39 \par
}
f0 2.40 \par
}
ode serves as the industry standard for input/output
on micro\par
}
apter{\b \f30 \fs58 3 }\par
}
0 \fs33 \cf0 Basic Logic{\fs33 Gates }
f0 {\f20 \fs19 3-1}{\f20 \fs19
INTRODUCTION }
fi360 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gate}{\b0 \f2
0 \fs18 is}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 basic}{\b0 \f20 \fs18 bui
lding}{\b0 \f20 \fs18 block}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 digital}{\b
0 \f20 \fs18 systems.}{\b0 \f20 \fs18 Logic}{\b0 \f20 \fs18 gates}{\b0 \f2
0 \fs18 operate}{\b0 \f20 \fs18 with}{\b0 \f20 \fs18 binary }
\b0 \f20 \fs18 numbers.}{\b0 \f20 \fs18 Gates}{\b0 \f20 \fs18 are}{\b0 \f20 \
fs18 therefore}{\b0 \f20 \fs18 referred}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18
as}{\b0 \f20 \fs18 binary}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gates.}{\b0
\f20 \fs18 All}{\b0 \f20 \fs18 voltages}{\b0 \f20 \fs18 used}{\b0 \f20 \fs18
with}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18 will }
\b0 \f20 \fs18 be}{\b0 \f20 \fs18 either}{\b0 \f20 \fs18 HIGH}{\b0 \f20 \fs18
or}{\b0 \f20 \fs18 LOW.}{\b0 \f20 \fs18 In}{\b0 \f20 \fs18 this}{\b0 \f2
0 \fs18 book,}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 HIGH}{\b0 \f20 \fs18 volta
ge}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 mean}{\b0 \f20 \fs18 a}{\b0 \f20 \f
s18 binary}{\b0 \f20 \fs18 1.}{\b0 \f20 \fs18 A}{\b0 \f20 \fs18 LOW}{\b0 \
f20 \fs18 voltage}{\b0 \f20 \fs18 will }
\b0 \f20 \fs18 mean}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 binary}{\b0 \f20 \fs18
0.}{\b0 \f20 \fs18 Remember}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 logic}{\b0 \
f20 \fs18 gates}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 electronic}{\b0 \f20 \fs1
8 circuits.}{\b0 \f20 \fs18 These}{\b0 \f20 \fs18 circuits}{\b0 \f20 \fs18 w
ill}{\b0 \f20 \fs18 respond}{\b0 \f20 \fs18 only}{\b0 \f20 \fs18 to }
\b0 \f20 \fs18 HIGH}{\b0 \f20 \fs18 voltages}{\b0 \f20 \fs18 (called}{\b0 \f20
\fs19 1s)}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 LOW}{\b0 \f20 \fs18 (ground)}{
\b0 \f20 \fs18 voltages}{\b0 \f20 \fs18 (called}{\f20 \fs19 OS). }
fi368 {\b0 \f20 \fs18 All}{\b0 \f20 \fs18 digital}{\b0 \f20 \fs18 systems}{\
b0 \f20 \fs18 are}{\b0 \f20 \fs18 constructed}{\b0 \f20 \fs18 by}{\b0 \f20
\fs18 using}{\b0 \f20 \fs18 only}{\b0 \f20 \fs18 three}{\b0 \f20 \fs18 b
asic}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gates.}{\b0 \f20 \fs18 These}{\b0
\f20 \fs18 basic}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18 are }
\b0 \f20 \fs18 called}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18
gate,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs19 OR}{\b0 \f20 \fs18 gate,}{\b0 \f20
\fs18 and}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 NOT}{\b0 \f20 \fs18 gate.}{\b
0 \f20 \fs18 This}{\b0 \f20 \fs18 chapter}{\b0 \f20 \fs18 deals}{\b0 \f20 \f
s18 with}{\b0 \f20 \fs18 these}{\b0 \f20 \fs18 very}{\b0 \f20 \fs18 importan
t }
\b0 \f20 \fs18 basic}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gates,}{\b0 \f20 \f
s19 or}{\b0 \f20 \fs18 functions. }
f0 {\f20 \fs18 3-2}{\f20 \fs19
THE}{\f20 \fs18 AND}{\f20 \fs19 GATE }
fi368 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 gate}{\b0 \f20 \
fs19 is}{\b0 \f20 \fs18 called}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 "all}{\
b0 \f20 \fs18 or}{\b0 \f20 \fs18 nothing"}{\b0 \f20 \fs18 gate.}{\b0 \f20 \f
s18 The}{\b0 \f20 \fs18 schematic}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{
\b0 \f20 \fs18 3-la}{\b0 \f20 \fs18 shows}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
idea}{\b0 \f20 \fs18 of }
\b0 \f20 \fs18 the}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18
The}{\b0 \f20 \fs18 lamp}{\b0\i \f20 \fs19 (}{\b0\i \f20 \fs19 Y}{\b0\i \f20
\fs19 )}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 light}{\b0 \f20 \fs18 only}{\b0
\f20 \fs18 when}{\b0 \f20 \fs18 both}{\b0 \f20 \fs18 input}{\b0 \f20 \fs18
switches}{\i \fs17 (}{\i \fs17 A}{\b0 \f20 \fs18 and}{\i \f20 \fs19 B}{\i
\f20 \fs19 )}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 closed.}{\b0 \f20 \fs18 All
}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 possible}{\b0 \f20 \fs18 combinations}{\b0 \f20 \fs18 for}{\b0
\f20 \fs18 switches}{\i \fs17 A}{\b0 \f20 \fs18 and}{\b0\i \f20 \fs19 B}{\
b0 \f20 \fs18 are}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18
Fig.}{\b0 \f20 \fs18 3-lb.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 table}{\b0 \f2
0 \fs18 in}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 figure}{\b0 \f20 \fs18 is}{\
b0 \f20 \fs18 called}{\b0 \f20 \fs18 a }
\b0 \f20 \fs18 truth}{\b0 \f20 \fs18 table.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs1
8 truth}{\b0 \f20 \fs18 table}{\b0 \f20 \fs18 shows}{\b0 \f20 \fs18 that}{\b
0 \f20 \fs18 the}{\b0 \f20 \fs18 output}{\i \f20 \fs18 (}{\i \f20 \fs18 Y}{\
i \f20 \fs18 )}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 enabled}{\b0 \f20 \fs18 (li
t)}{\b0 \f20 \fs18 only}{\b0 \f20 \fs18 when}{\b0 \f20 \fs18 both}{\b0 \f20 \
fs18 inputs}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 closed. }\par
}
a){\fs15 A}{\fs15 N}{\fs15 D} circuit{\fs15 using} switches \par
}
\cf0 Input
\par}{\phpg\posx4425\pvpg\posy8914\absw676\absh379 \sl-215 \f20 \fs16 \cf0 switc

hes \par
}
{\phpg\posx5727\pvpg\posy8914\absw548\absh379 \f20 \fs16 \cf0 \f20 \fs16 \cf0 ou
tput
5 light \par
}
\cf0 open
4 open
\par}{\phpg\posx4155\pvpg\posy10086\absw491\absh757 \sl-217 \f20 \fs16 \cf0 clos
ed
\par}{\phpg\posx4155\pvpg\posy10086\absw491\absh757 \sl-213 \f20 \fs16 \cf0 clos
ed \par
}
16 \cf0 open
i144 closed
i194 open
i144 closed
0 {\i \f10 \fs14 (b)}{\fs14 Truth}{\fs14 table }
0 \fi206 {\b \fs16 Fig.}{\b \fs17 3-1 }\par
}
o
\par}{\phpg\posx5913\pvpg\posy10062\absw325\absh803 \sl-215 \f20 \fs16 \cf0 no
1 no
\fs16 Yes }\par
}
8 \cf0 The standard logic symbol for the AND gate{\fs18 is} drawn in Fig. 3-2a.
This symbol shows the inputs
\par}{\phpg\posx843\pvpg\posy12009\absw9114\absh2196 \sl-232 \f20 \fs18 \cf0 as{
\b\i \f10 \fs18 A} and{\i B.} The output is shown as{\b\i Y.} This is the sy
mbol for a 2-input{\b AND} gate. The truth table for
2-input AND gate is shown in Fig. 3-2b. The inputs are shown as binary digits
(bits). Note that
\par}{\phpg\posx843\pvpg\posy12009\absw9114\absh2196 \sl-242 \f20 \fs18 \cf0 onl
y when both input{\b\i \f10 \fs17 A} and input{\i \fs19 B} are 1{\fs18
will} the output be 1. Binary{\fs18 0} is defined as a LOW, or
\par}{\phpg\posx843\pvpg\posy12009\absw9114\absh2196 \sl-230 \f20 \fs18 \cf0 gro
und, voltage. Binary 1 is defined as a HIGH voltage. In this book, a HIGH voltag
e will mean about
44 {\b\i \f10 \fs18 +}{\b\i \f10 \fs18 5} volts{\b \fs19 (V)}{\fs18 if} the
integrated circuits (ICs) being used are from the TTL family.
364 Boolean algebra is a form of symbolic logic that shows how logic
gates operate. A Boolean
ression is a "shorthand" method of showing what is happening in a log

ic circuit. The Boolean
ression for the circuit in Fig. 3-2 is
4364 28 \par
}
0 CHAP.{\fs17 31 }\par
}
cf0 BASIC LOGIC GATES \par
}
f0 29 \par
}
cf0 Inputs \par
}
cf0 Output \par
}
0 + \par
}
f20 \fs15 \cf0 B
{\f10 \fs13 (a)}{\i0 \fs15 AND-gate}{\i0 \fs15 symbol }
\cf0 \fi100 {\i0 \fs17 Inputs}{\i0 \fs17
Output }\par
}
6 0 }
{\fs15 1 }
{\fs15 1 }\par
}
6 1 }
5 0 }
5 1 }\par
}
{\fs15 1 }\par
}
7 \cf0 0{\f10 \fs15 =}{\b \fs17 low}{\b voltage }
809 {\f10 \fs15 1}{\f10 \fs14 =}{\b \fs17 high}{\b voltage }

\fi3715 {\i \fs14 (b)}{\b \fs15 AND}{\b \fs15 truth}{\b \fs15 table }
\fi4053 {\b \fs16 Fig.}{\b \f30 \fs17 3-2 }
\par}{\phpg\posx843\pvpg\posy4499\absw8025\absh2292 \sl-203 \par\par\f20 \fs17 \
cf0 \fi4005 {\b\i \fs19 A}{\b\i \fs19 -}{\b\i \fs19 B}{\b\i \fs19 =}{\b\i \fs
19 Y }
18 The}{\fs18 Boolean}{\fs18 expression}{\fs18 is}{\fs18 read}{\fs18 as}{\b
\i \fs18 A}{\fs19 AND}{\f10 \fs16 (.}{\fs18 means}{\fs18 AND)}{\b\i \fs19
B}{\fs18 equals}{\fs18 the}{\fs18 output}{\b\i \fs19 Y.}{\fs18 The}{\fs18
dot }
18 the}{\fs18 logic}{\fs18 function}{\fs18 AND}{\fs18 in}{\fs18 Boolean}{\f
s18 algebra,}{\b\i \fs19 not}{\fs18 multiply}{\fs18 as}{\fs18 in}{\fs18
regular}{\fs18 algebra, }\par
}
{\phpg\posx9139\pvpg\posy6575\absw630\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 me
ans \par
}
\cf0 Sometimes the dot{\f10 \fs16 (-)} is left out of the Boolean exp
ression. The Boolean expression for the
\par}{\phpg\posx829\pvpg\posy7043\absw9046\absh3058 \sl-245 \f20 \fs18 \cf0 2-in
put AND gate{\fs18 is} then:
085 {\b\i \fs18 A}{\b\i \fs18 B}{\b\i \fs18 =}{\b\i \fs18 Y }
Boolean expression reads{\b\i \fs18 A} AND{\i \fs19 B} equals the output{\
b\i \fs19 Y. }
59 A logic circuit will often have three variables. Figure 3-3a shows the
Boolean expression for a
put AND gate. The input variables are{\b\i \fs19 A}{\b\i \fs19 ,}{\b\i \fs19
B}{\b\i \fs19 ,} and{\fs18 C.} The output is shown as{\b\i \fs18 Y.} The log
ic symbol
\par}{\phpg\posx829\pvpg\posy7043\absw9046\absh3058 \sl-242 \f20 \fs18 \cf0 for
this 3-input{\b \fs18 AND} expression is drawn in Fig. 3-3b. The three inpu
ts{\b\i \f10 \fs18 (A,}{\i \fs19 B,}{\fs18 C)} are on the left{\fs19 of }
symbol. The single output{\b\i \fs19 (}{\b\i \fs19 Y}{\b\i \fs19 )}is on the
right of the symbol. The truth table in Fig. 3-3c shows the
\par}{\phpg\posx829\pvpg\posy7043\absw9046\absh3058 \sl-233 \f20 \fs18 \cf0 eigh
t possible combinations of the variables{\b\i \fs18 A}{\b\i \fs18 ,}{\i \fs1
9 B,} and{\fs19 C.} Note that the top line in the table is the
ry count{\fs18 000.} The binary count then proceeds upward to{\fs19 001,}{\f
s18 010,}{\fs18 011,}{\fs18 100,} 101,{\fs18 110,} and finally
1 111. Note that only when all inputs are 1{\fs19 is} the output of the AND
gate enabled with a{\fs18 1. }
\fi5997 {\b \fs17 Inputs}{\b \fs17
Output }\par
}
\f20 \fs16 \cf0 A . B * C = Y
\cf0 {\fs15 (a)}{\i0 \fs15 Three-variable}{\i0 \fs15 Boolean}{\i0 \fs15 expr
ession }\par
}
\cf0 :3->y \par
}
s16 \cf0 C \par
}
\cf0 Inputs \par
}
\cf0 Output \par
}
0
28 1
28 1
35 1
35 1 \par
}
0
22 0
28 0
30 1
35 1 \par
}
0
28 1
25 0
35 1 \par
}
0
s16 0 }

10 \fs15 0 }
10 \fs16 0 }
10 \fs15 0 }
43 {\f10 \fs15 1 }\par
}
\cf0 (b){\b\i0 \f20 \fs15 3-input}{\b\i0 \f20 \fs15 AND}{\b\i0 \f20 \fs15 ga
te}{\b\i0 \f20 \fs15 symbol }\par
}
\cf0 Fig.{\fs16 3-3 }\par
}
par
}
{\phpg\posx4343\pvpg\posy569\absw1899\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 BA
SIC LOGIC GATES \par
}
AP. 3 \par
}
\cf0 Consider the AND truth tables shown in Figs.{\i \fs19 3-2b} and{\
b\i \fs19 3-3c.} In each truth table the{\b\i \fs18 unique }
4 {\b\i \fs18 output} from the AND gate is a{\fs19 HIGH} only when{\i \fs19
all} inputs are{\fs19 HIGH.} Designers look at each gate's
5 unique output when deciding which gate will perform a certain task.
89 The laws of Boolean algebra govern how AND gates operate. The form
al laws for the{\b\i AND }
i \fs19 function} are:
088 {\b\i A}{\b\i *}{\b\i 0}{\b\i =}{\b\i 0 }
088 {\b\i A}{\b\i .}{\b\i l}{\b\i =}{\b\i A }
052 {\b\i A}{\b\i *}{\b\i A}{\b\i =}{\b\i A }
048 {\b\i A}{\b\i .}{\b\i A}{\b\i =}{\b\i O }
5 {\fs19 You} can prove the accuracy of these laws by referring back to the
truth table in Fig.{\fs19 3-2.} These are
0 general statements that are always true about the AND function. AND gates must
follow these laws.
0 Note the bar over the variable in the last law. The bar over the variable mean
s{\i not}{\b\i A}{\b\i ,} or the opposite
9 of{\b\i \fs19 A. }
\fi35 {\b \f10 \fs17 SOLVED}{\b \f10 \fs17 PROBLEMS }\par

}
f0 3.1 \par
}
rite the Boolean expression for a 4-input AND gate.
\fs17 Solution: }
52 {\b\i \fs17 A}{\b\i \fs17 -}{\b\i \fs17 B}{\b\i \fs17 .}{\b\i \fs17 C}{\b
\i \fs17 -}{\b\i \fs17 D}{\b\i \fs17 =}{\b\i \fs17 Y}{\fs17
or}{\b\i \fs1
7
ABCD=Y }\par
}
f0 3.2 \par
}
raw the logic symbol for a 4-input AND gate.
\fs17 Solution: }
68 {\b\i \fs17 See}{\b \fs16 Fig.}{\b \fs17 3-4. }\par
}
\cf0 Fig.{\f10 \fs15 3-4}{\b0
Symbol}{\b0 \fs17 for}{\b0 \fs17 a}{\b0 \fs1
7 4-input}{\b0 \fs17 AND}{\b0 \fs17 gate }\par
}
f0 3.3 \par
}
raw a truth table for a 4-input AND gate.
}
nputs \par
}
fs17 \cf0 C
0 {\b0\i0 0 }
0 {\b0\i0 0 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 1 }\par
}
fs17 \cf0 B

0 {\b0\i0 0 }
0 {\b0\i0 0 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 1 }\par
}
fs17 \cf0 D
0 \fi30 {\b0\i0 0 }
0 \fi30 {\b0\i0 0 }
0 \fi30 {\b0\i0 \fs16 0 }
0 \fi30 {\b0\i0 \fs16 0 }
0 \fi23 {\b0\i0 \fs16 0 }
0 \fi23 {\b0\i0 \fs16 0 }
0 \fi23 {\b0\i0 \fs16 0 }
0 \fi23 {\b0\i0 \fs16 0 }\par
}
fs17 \cf0 A
0 {\b0\i0 0 }
0 {\b0\i0 1 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 1 }
0 {\b0\i0 \fs16 0 }
0 {\b0\i0 \fs16 1 }\par
}
{\phpg\posx4883\pvpg\posy10879\absw559\absh511 \f20 \fs17 \cf0 \f20 \fs17 \cf0 o
utput
\fi223 {\b\i Y }\par
}

nputs \par
}
fs17 \cf0 C
0 \fi27 {\b0\i0 \fs16 0 }
0 \fi29 {\b0\i0 \fs16 0 }
0 \fi25 {\b0\i0 \fs16 0 }
0 \fi25 {\b0\i0 \fs16 0 }
0 \fi25 {\b0\i0 \fs16 1 }
0 \fi27 {\b0\i0 \fs16 1 }
0 \fi25 {\b0\i0 \fs16 1 }
0 \fi27 {\b0\i0 \fs16 1 }\par
}
fs17 \cf0 B
0 \fi26 {\b0\i0 \fs16 0 }
0 \fi26 {\b0\i0 \fs16 0 }
0 \fi22 {\b0\i0 \fs16 1 }
0 \fi24 {\b0\i0 \fs16 1 }
0 \fi22 {\b0\i0 \fs16 0 }
0 \fi26 {\b0\i0 \fs16 0 }
0 \fi22 {\b0\i0 \fs16 1 }
0 \fi26 {\b0\i0 \fs16 1 }\par
}
fs17 \cf0 D
0 \fi37 {\b0\i0 \fs16 1 }
0 \fi41 {\b0\i0 \fs16 1 }
0 \fi37 {\b0\i0 \fs16 1 }
0 \fi36 {\b0\i0 \fs16 1 }
0 \fi37 {\b0\i0 \fs16 1 }
0 \fi37 {\b0\i0 \fs16 1 }
0 \fi37 {\b0\i0 \fs16 1 }
0 \fi37 {\b0\i0 \fs16 1 }\par
}

fs17 \cf0 A
0 \fi25 {\b0\i0 \fs16 0 }
0 \fi24 {\b0\i0 \fs16 1 }
0 \fi20 {\b0\i0 \fs16 0 }
0 \fi23 {\b0\i0 \fs16 1 }
0 \fi20 {\b0\i0 \fs16 0 }
0 \fi25 {\b0\i0 \fs16 1 }
0 \fi20 {\b0\i0 \fs16 0 }
0 \fi25 {\b0\i0 \fs16 1 }\par
}
utput
\fi227 {\i \fs17 Y }\par
}
.{\b \fs17 31 }\par
}
}
\par
}
f0 3.4 \par
}
n Fig.{\fs18 3-5,} what would the output pulse train look like'? \par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
cf0 0
\par}{\phpg\posx5182\pvpg\posy2049\absw104\absh414 \sl-277 \i \f20 \fs14 \cf0 {\
b \fs15 c }\par
}
15 \cf0 0
b \par
}
fs13 \cf0 1
i \f20 \fs15 a }\par
}
0 \fs19 \cf0 Fig.{\fs17 3-5}{\b0 \f20 \fs17 Pulse-train}{\b0 \f20 \fs17 probl
em }
f0 {\b0 \f20 \fs16 Solution: }
fi360 {\b0 \f20 \fs17 In}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs17 3-5,}{\b0 \f20
\fs17 the}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 waveform}{\b0 \f20 \fs17
would}{\b0 \f20 \fs16 look}{\b0 \f20 \fs17 exactly}{\b0 \f20 \fs17 like}{\b
0 \f20 \fs17 the}{\b0 \f20 \fs17 input}{\b0 \f20 \fs17 waveform}{\b0 \f20 \
fs17 at}{\b0 \f20 \fs17 input}{\i \f10 \fs16 A. }\par
}
{\phpg\posx1459\pvpg\posy4009\absw911\absh381 \f20 \fs17 \cf0 \f20 \fs17 \cf0 pu
lse{\i \f10 \fs10
c1}{\f10 \fs11 =}{\fs16 1 }
\par}{\phpg\posx1459\pvpg\posy4009\absw911\absh381 \sl-210 \f20 \fs17 \cf0 pulse
{\fs16 b}{\dn006 \f10 \fs11 =} 0 \par
}
lse{\b \f10 \fs14 c}{\dn006 \f10 \fs11 =} 0
{\fs16 d}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
lse{\fs16 e}{\dn006 \f10 \fs11 =}{\fs16 1 }
{\i \f30 \fs19 f}{\i \f30 \fs19 =}{\fs16 0 }\par
}
lse{\b\i \fs15 g}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\fs16 h}{\f10 \fs13 =} 0 \par
}
f0 3.5 \par
}
n Fig.{\b \fs18 3-6,} what would the output pulse train look like? Note that
two pulse trains are being
\par}{\phpg\posx1461\pvpg\posy4865\absw8360\absh430 \sl-239 \f20 \fs18 \cf0 ANDe
d. \par
}
15 \cf0 h
{\b0\i0 \fs21 o }\par
}
5 \cf0 g \par
}

5 \cf0 f \par
}
5 \cf0 e \par
}
{\phpg\posx4037\pvpg\posy6303\absw793\absh245 \f20 \fs21 \cf0 \f20 \fs21 \cf0 o{
\f10 \fs18
o}{\f10 \fs18 J}{\f10 \fs18 i }\par
}
15 \cf0 d
\par}{\phpg\posx4883\pvpg\posy6066\absw134\absh439 \sl-151 \par\b\i \f20 \fs15 \
cf0 \fi24 {\i0 \f10 \fs13 1 }\par
}
15 \cf0 c
cf0 {\i0 \f10 \fs13 1 }\par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
0 \fs19 \cf0 Fig.{\fs17 3-6}{\b0 \f20 \fs17 Pulse-train}{\b0 \f20 \fs17 probl
em }
f0 {\f20 \fs16 Solution: }
fi355 {\b0 \f20 \fs17 In}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs16 3-6,}{\b0 \f20
\fs17 the}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 pulses}{\b0 \f20 \fs17 wo
uld}{\b0 \f20 \fs17 be}{\b0 \f20 \fs16 as}{\b0 \f20 \fs17 follows: }\par
}
lse{\fs16 a}{\dn006 \f10 \fs11 =}{\fs16 0 }
{\fs16 b}{\f10 \fs13 =}{\fs16 1 }\par
}
lse{\b \f10 \fs14 c}{\f10 \fs13 =} 0
{\fs16 d}{\f10 \fs13 =}{\fs16 1 }\par
}
lse{\fs16 e}{\f10 \fs13 =} 0
6 pulse}{\i \f30 \fs19 f=}{\fs16 0 }\par
}
lse{\fs14 g}{\dn006 \f10 \fs11 =}{\fs16 0 }
{\fs16 h}{\f10 \fs13 =} 0 \par
}
\fs18 \cf0 3-3{\fs18
THE} OR GATE
fi384 {\b0 The}{\b0 \fs19 OR}{\b0 gate}{\b0 is}{\b0 called}{\b0 the}{\b0 "
any}{\b0 or}{\b0 all"}{\b0 gate.}{\b0 The}{\b0 schematic}{\b0 in}{\b0 Fig
.}{\i \fs19 3-7a}{\b0 shows}{\b0 the}{\b0 idea}{\b0 \fs18 of}{\b0 the}{\b0

\fs19 OR }
fi27 {\b0 gate.}{\b0 The}{\b0 lamp}{\i \fs19 (}{\i \fs19 Y}{\i \fs19 )}{\b
0 will}{\b0 glow}{\b0 when}{\b0 either}{\b0 switch}{\i A}{\i \fs19 or}{
\b0 switch}{\b0\i \fs19 B}{\b0 \fs18 is}{\b0 closed.}{\b0 The}{\b0 la
mp}{\b0 will}{\b0 also}{\b0 glow }
fi23 {\b0 when}{\b0 both}{\b0 switches}{\i \fs19 A}{\b0 and}{\b0\i \fs19
B}{\b0 are}{\b0 closed.}{\b0 The}{\b0 lamp}{\b0\i \fs19 (}{\b0\i \fs19 Y}
{\b0\i \fs19 )}{\b0 will}{\b0\i \fs19 no2}{\b0 glow}{\b0 when}{\b0 both}{\
b0 switches}{\i (}{\i A}{\b0 and}{\i \fs19 B}{\i \fs19 ) }
fi30 {\b0 are}{\b0 open.}{\b0 All}{\b0 the}{\b0 possible}{\b0 switch}{\b0
combinations}{\b0 are}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0\i 3-7h.}{\b0 The}{
\b0 truth}{\b0 table}{\b0 details}{\b0 the}{\b0\i \fs19 OR }
\b0\i \fs19 function}{\b0 of}{\b0 the}{\b0 switch}{\b0 and}{\b0 lamp}{\b0
circuit.}{\b0 The}{\b0 output}{\b0 \fs18 of}{\b0 the}{\b0 \fs18 OR}{\b0 ci
rcuit}{\b0 \fs18 will}{\b0 be}{\b0 enabled}{\b0 (lamp}{\b0 lit)}{\b0 when
}
fi35 {\b0 any}{\b0 or}{\b0 all}{\b0 input}{\b0 switches}{\b0 are}{\b0 clos
ed. }\par
}
\cf0 Input
\par}{\phpg\posx6521\pvpg\posy10919\absw676\absh387 \sl-215 \f20 \fs17 \cf0 swit
ches \par
}
7 \cf0 B
\fi51 {\fs17 open }
54 {\fs17 open }
s17 closed }
s17 closed }\par
}
\f10 \fs15 \cf0 A
\cf0 \fi52 {\b0\i0 \f20 \fs17 open }
0 {\b0\i0 \f20 \fs17 closed }
0 \fi60 {\b0\i0 \f20 \fs17 open }
0 {\b0\i0 \f20 \fs17 closed }\par
}
4 1 \par
}
s14 \cf0 Y \par
}
w- \par
}
output
116 light
\fi277 {\fs16 Y }
\fi229 no
205 Yes
207 Yes
207 Yes \par
}
\cf0 Fig.{\f30 \fs17 3-7 }\par
}
par
}
cf0 BASIC{\fs17 LOGIC}{\fs17 GATES }\par
}
}
\cf0 The standard logic symbol for an{\fs18 OR} gate is drawn in Fig. 3-8a. N
ote the different shape of the
19 OR} gate. The{\fs19 OR} gate has{\fs18 two} inputs labeled{\b\i A
} and{\i \fs18 B.} The output is labeled{\i \fs18 Y.} The shorthand
\par}{\phpg\posx847\pvpg\posy1340\absw9001\absh1502 \sl-244 \f20 \fs18 \cf0 Bool
ean expression for this{\fs19 OR} function is given as{\b\i \fs18 A}{\f10 \fs
27 +}{\i\dn006 B}{\dn006 \f10 \fs13 =}{\b\i \fs18 Y.} Note that the plus{\f
10 \fs16 (}{\f10 \fs29 +}{\f10 \fs16 )} symbol means
18 OR} in Boolean algebra. The expression{\b\i (}{\b\i A}{\f10 \fs27 +}
{\i \fs18 B}{\f10 \fs14 =}{\b\i \fs18 Y}{\b\i \fs18 )} is read as{\b\i
A}{\fs18 OR}{\f10 \fs17 (+} means{\fs18 OR)}{\i B} equals
\par}{\phpg\posx847\pvpg\posy1340\absw9001\absh1502 \sl-235 \f20 \fs18 \cf0 outp
ut{\b\i \fs18 Y.} You will note that the plus sign does{\i \fs18 nut} mean
to add as it does in regular algebra.
\fi3226 {\b\i \f10 \fs13 A }\par
}
cf0 Inputs \par
}
13 \cf0 A \par
}
15 \cf0 Y \par
}
cf0 output \par

}
0 +- \par
}
\cf0 ( U ) \par
}
\cf0 OR-gate symbol \par
}
\cf0 Inputs
Output \par
}
\par
}
5 0 }
{\fs15 1 }
{\fs15 1 }\par
}
5 1 }
{\fs15 0 }
{\fs15 1 }\par
}
5 1 }
{\fs15 1 }
{\fs15 1 }\par
}
7 \cf0 0{\f10 \fs14 =}{\b low}{\b voltage }
729 {\f10 \fs15 1}{\f10 \fs14 =}{\fs16 high}{\b voltage }
\fi3717 {\i \fs15 (h)}{\b \fs15 OR}{\b \fs15 truth}{\b \fs15 table }
\fi4077 {\b \fs16 Fig.}{\b \fs16 3-8 }
\fi360 {\fs18 The}{\fs18 truth}{\fs18 table}{\fs18 for}{\fs18 the}{\fs18 2input}{\fs18 OR}{\fs18 gate}{\fs18 is}{\fs18 drawn}{\fs18 in}{\fs18 Fig.}{
\fs18 3-8b.}{\fs18 The}{\fs18 input}{\fs18 variables}{\b\i \fs18 (}{\b\i \
fs18 A}{\fs18 and}{\i \fs18 B}{\i \fs18 )}{\fs18 are }
18 given}{\fs18 on}{\fs18 the}{\fs18 left.}{\fs18 The}{\fs18 resulting}{\fs
18 output}{\b\i \fs18 (}{\b\i \fs18 Y}{\b\i \fs18 )}{\fs18 is}{\fs18 shown}
{\fs18 in}{\fs18 the}{\fs18 right}{\fs18 column}{\fs18 of}{\fs18 the}{\fs
18 table.}{\fs18 The}{\fs18 OR}{\fs18 gate}{\fs18 is }
i \fs19 enabled}{\fs18 (output}{\fs18 is}{\fs18 1)}{\fs18 anytime}{\fs18

a}{\fs18 1}{\fs18 appears}{\fs18 at}{\fs18 any}{\fs18 or}{\fs18 all}{\f
s18 of}{\fs18 the}{\fs18 inputs.}{\b \fs18 As}{\fs18 before,}{\fs18 a}{
\fs18 0}{\fs18 is}{\fs18 defined}{\fs18 as}{\fs18 a }
\fs19 LOW}{\fs18 (ground)}{\fs18 voltage.}{\b \fs18 A}{\fs18 1}{\fs18 in}{
\fs18 the}{\fs18 truth}{\fs18 table}{\fs18 represents}{\fs18 a}{\fs18 HI
GH}{\i \fs19 (+5}{\b \fs18 V)}{\fs18 voltage. }
62 {\fs18 The}{\fs18 Boolean}{\fs18 expression}{\fs18 for}{\fs18 a}{\fs18 3
-input}{\fs18 OR}{\fs18 gate}{\fs18 is}{\fs18 written}{\fs18 in}{\fs18 Fig
.}{\fs18 3-9a.}{\fs18 The}{\fs18 expression}{\fs18 reads}{\b\i \fs18 A}{\f
s18 OR }
i \fs19 B}{\fs19 OR}{\fs19 C}{\fs18 equals}{\fs18 output}{\i \fs19 Y.}{\f
s18 The}{\fs18 plus}{\fs18 sign}{\fs18 again}{\fs18 signifies}{\fs18 the}{
\fs18 OR}{\fs18 function. }
67 {\b \fs18 A}{\fs18 logic}{\fs18 symbol}{\fs18 for}{\fs18 the}{\fs18 3-in
put}{\fs18 OR}{\fs18 gate}{\fs18 is}{\fs18 drawn}{\fs18 in}{\fs18 Fig.}{\
fs18 3-9h.}{\fs18 Inputs}{\b\i \fs18 A,}{\b\i \fs18 B,}{\fs18 and}{\fs18
C}{\fs18 are}{\fs18 shown}{\fs18 on }
\fs18 the}{\fs18 left}{\fs18 of}{\fs18 the}{\fs18 symbol.}{\fs18 Output}{\b
\i \fs18 Y}{\fs18 is}{\fs18 shown}{\fs18 on}{\fs18 the}{\fs18 right}{\fs1
8 of}{\fs18 the}{\fs18 OR}{\fs18 symbol.}{\fs18 This}{\fs18 symbol}{\fs18
represents}{\fs18 some }
18 circuit}{\fs18 that}{\fs18 will}{\fs18 perform}{\fs18 the}{\fs19 OR}{\f
s18 function. }\par
}
\cf0 Inputs \par
}
1{\b \f20 \fs17
Output }\par
}
I \par
}
\f20 \fs16 \cf0 A + B + C = Y
\cf0 {\i0 \fs15 (a)}{\i0 \fs15 Three-variable}{\i0 \fs15 Boolean}{\i0 \fs15
expression }\par
}
fs16 \cf0 C
B
A
l \par
}
0
s15 0 }
31 {\fs15 1 }
31 1
36 1
36 1 \par
}
0
s15 1 }
24 {\fs15 0 }
29 0
31 1
33 1 \par
}
0
s15 0 }
s15 0 }
27 1
27 0
31 1 \par
}
s16 \cf0 Y \par
}
fs66 \cf0 A3> \par
}
\cf0 Inputs{\i \fs15 B }
fi520 {\i \fs15 C }\par
}
s15 \cf0 Y{\i0 \fs15
output }\par
}
fs15 \cf0 (b){\i0 \fs15 3-input}{\i0 OR}{\i0 \fs15 gate}{\i0 \fs15 symbol }
\par
}
fs15 \cf0 (c){\i0 \fs15 Truth}{\i0 \fs15 table}{\i0 \fs15 with}{\i0 \fs15 th
ree}{\i0 \fs15 variables }\par
}
\cf0 Fig. 3-9 \par
}
.{\b 31 }\par
}
}
\par
}
\fs18 \cf0 A{\b0 truth}{\b0 table}{\b0 for}{\b0 the}{\b0 3-input}{\b0
\fs18 OR}{\b0 gate}{\b0 is}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 3-9c.}
{\b0 The}{\b0 variables}{\i (}{\i A}{\i ,}{\i \fs18 B,}{\b0 and}{\i \fs1
9 C}{\i \fs19 )}{\b0 are }
\b0 shown}{\b0 on}{\b0 the}{\b0 left}{\b0 side}{\b0 of}{\b0 the}{\b0 tabl
e.}{\b0 The}{\b0 output}{\i \fs18 (}{\i \fs18 Y}{\i \fs18 )}{\b0 is}{\b0 l
isted}{\b0 in}{\b0 the}{\b0 right}{\b0 column.}{\b0 Anytime}{\b0 a}{\fs18
1}{\b0 appears }
\b0 at}{\b0 any}{\b0 input,}{\b0 the}{\b0 output}{\b0 will}{\b0 be}{\b0 \f
s18 1. }
fi368 {\b0 Consider}{\b0 the}{\b0 \fs18 OR}{\b0 truth}{\b0 tables}{\b0 in}
{\b0 Figs.}{\b0 \fs18 3-86}{\b0 and}{\b0 3-9c.}{\b0 In}{\b0 each}{\b0 tru
th}{\b0 table}{\b0 the}{\i unique}{\i \fs18 output}{\b0 from }
\b0 the}{\b0 \fs19 OR}{\b0 gate}{\b0 \fs18 is}{\b0 a}{\b0 LOW}{\b0 only}{
\b0 when}{\b0\i \fs18 all}{\b0 inputs}{\b0 are}{\b0 LOW.}{\b0 Designers}
{\b0 look}{\b0 at}{\b0 each}{\b0 gate's}{\b0 unique}{\b0 output }
\b0 when}{\b0 deciding}{\b0 which}{\b0 gate}{\b0 will}{\b0 perform}{\b0
a}{\b0 certain}{\b0 task. }
fi361 {\b0 The}{\b0 laws}{\b0 of}{\b0 Hoolean}{\b0 algebra}{\b0 govern}{
\b0 how}{\b0 an}{\b0 OR}{\b0 gate}{\b0 will}{\b0 operate.}{\b0 The}{\b0
formal}{\b0 laws}{\b0 \fs18 for}{\b0 the}{\b0 \fs18 OR }
\b0 function}{\b0 are: }
fi3992 {\i A}{\i d}{\i O}{\i =}{\i A }
fi3996 {\i A}{\i +}{\i l}{\i =}{\i l }
fi3956 {\i A}{\i +}{\i A}{\i =}{\i A }
fi3956 {\i A}{\i +}{\i A}{\i =}{\i l }
\b0 Looking}{\b0 at}{\b0 the}{\b0 truth}{\b0 table}{\b0 in}{\b0 Fig.}
{\b0 \fs19 3-8}{\b0 will}{\b0 help}{\b0 you}{\b0 check}{\b0 these}{\b0
laws.}{\b0 These}{\b0 general}{\b0 statements}{\b0 are }
\b0 always}{\b0 true}{\b0 of}{\b0 the}{\b0 \fs18 OR}{\b0 function.}{\b0
The}{\b0 bar}{\b0 over}{\b0 the}{\b0 last}{\b0 variable}{\b0 means}{\
i not}{\i A}{\i ,}{\b0 or}{\b0 the}{\b0 opposite}{\b0 of}{\i A. }
f0 {\b0 \f10 \fs16 SOLVED}{\b0 \f10 \fs16 PROBLEMS }\par
}
f0 3.6 \par
}
Write the 13001ean expression for a 4-input{\fs18 OR} gate.
\fs16 Solution: }
352 {\b\i\dn006 \f10 \fs15 A}{\f10 \fs25 +}{\b\i\dn006 \fs17 B}{\f10 \fs26 +}{\i\dn006 \fs16 C}{\f10 \fs25 +}{\i\dn006 \fs17 D}{\i \fs17 =}{\i \fs17 Y
}
Draw the logic symbol for a 4-input{\fs18 OR} gate.
366 {\fs16 See}{\fs16 Fig.}{\fs16 3-10. }\par
}
f0 3.7 \par
}
\cf0 Fig. 3-10{\fs17
Symbol}{\b0 \fs16 used}{\fs16 for}{\b0 \fs16 a}{\b0
\fs16 4-input}{\b0 \fs17 OR}{\b0 \fs16 gate }\par
}
f0 3.8 \par
}
raw a truth table for a 4-input{\fs18 OR} gate.
}
nputs \par
}
fs16 \cf0 C
0 \fi29 {\b0\i0 \fs17 0 }
0 {\b0\i0 0}{\b0\i0 0 }
0 {\b0\i0 O }
}{\phpg\posx3632\pvpg\posy11447\absw180\absh2100 \b\i \f20 \fs16 \cf0 \fi15 {\b0
\i0 \fs17 0 }
0 {\b0\i0 0}{\b0\i0 0 }
0 \fi23 {\b0\i0 1}{\b0\i0 1 }
0 \fi29 {\b0\i0 1 }
0 \fi21 {\b0\i0 1 }
0 \fi27 {\b0\i0 1 }\par
}
f20 \fs16 \cf0 B
\fi53 {\b0\i0 \fs17 0 }

{\b0\i0 0}{\b0\i0 0 }\par
}
fs16 \cf0 D
0 \fi21 {\b0\i0 \fs17 0 }
0 {\b0\i0 0 }
0 {\b0\i0 \fs17 0 }
}{\phpg\posx3241\pvpg\posy11447\absw181\absh2100 \b\i \f20 \fs16 \cf0 {\b0\i0 O
}
0 \fi21 {\b0\i0 0 }
0 {\b0\i0 0 }
0 \fi21 {\b0\i0 0 }
0 {\b0\i0 0 }
0 \fi21 {\b0\i0 0 }\par
}
f20 \fs16 \cf0 A
\fi76 {\b0\i0 \fs17 0 }
{\b0\i0 l}{\b0\i0 1}{\b0\i0
I }\par
}
{\fs17 1}
O{\fs17 0}
( \par
}
11
43 0
47 {\b \f30 \fs17 0 }
49 0
40 1
46 1 \par
}
1
I \par
}
ar
}
\par
}
\sl-254 \f20 \fs16 \cf0 1

\sl-257 \f20 \fs16 \cf0 0
\sl-252 \f20 \fs16 \cf0 1 \p
\fs17 \cf0 \f20 \fs17 \cf0 1

output
\fi226 {\i \fs17 Y }
232 {\fs17 0 }
215 11
252 {\fs17 1 }
211 11
243 1
251 1
244 {\fs17 1 }
252 1 \par
}
nputs \par
}
utput \par
}
1
par
}
0
par
}
0
par
}

0
par
}
{\phpg\posx5791\pvpg\posy-238\absw1467\absh3470 \f10 \fs273 \cf0 \f10 \fs273 \cf
0 - \par
}
cf0 BASIC{\fs18 LOGIC}{\f10 \fs16 GATE.!! }\par
}
n Fig.{\fs20 3-11,} what would the output pulse train look like?
\fi2587 {\b \fs15 I}{\b \fs15
1}{\b \fs15
I }
286 {\f10 \fs29 -\\- }\par
}
s18 \cf0 f{\f20 \fs16
r}{\f20 \fs16
d}{\f20 \fs16
c}{\f20 \fs16
h}{\
f20 \fs16 o }\par
}
0 \fs16 \cf0 Fig.{\f10 \fs16 3-11}{\b0 \f20 \fs17
Pulsc-train}{\b0 \f20 \fs17
problcm }
f0 {\f20 \fs17 salallan: }
fi365 {\b0 \f20 \fs17 In}{\b0 \f20 \fs17 Fig.}{\f10 \fs16 3-11.}{\b0 \f20 \fs
17 the}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 wavcform}{\b0 \f20 \fs17 wo
uld}{\b0 \f20 \fs17 look}{\b0 \f20 \fs17 exactly}{\b0 \f20 \fs17 like}{\b0
\f20 \fs17 the}{\b0 \f20 \fs17 input}{\f20 \fs17 wavcform}{\b0 \f20 \fs17
at}{\b0 \f20 \fs17 input}{\i \f10 \fs16 A. }\par
}
U k{\b \f30 \fs13 4}{\b \f10 \fs16
1 }
{\b\i \fs17 h}{\fs16
0 }\par
}
}
{\phpg\posx2705\pvpg\posy4020\absw713\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 PU
IW{\b \f30 \fs14 C }\par
}
{\phpg\posx3935\pvpg\posy4020\absw668\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 PU
kC{\b\i \f10 \fs11 C }\par
}
cf0 1 \par
}
cf0 PUlSC{\f30 \fs18 R }\par

}
17 \cf0 0 \par
}
lw{\b\i \f10 \fs23 n}{\dn006 \f10 \fs16 = }\par
}
}
cf0 1
b0 \f20 \fs16 0 }\par
}
ulv{\b \f30 \fs25 I=}{\b\dn006 \f10 \fs16 1 }\par
}
}
\cf0 9 \par
}
0 \cf0 V \par
}
n Fig.{\b \f10 \fs18 3-12,} what would the output pulse train{\b \f30 \fs20 lo
ok}{\fs19 like?} Note that{\fs19 two} prilse trains are k i n g
\fs20 ORed} together. \par
}
0 \fs16 \cf0 Fig.{\f10 \fs16 3-12}{\b0 \f20 \fs17
Pulsc-train}{\b0 \f20 \fs17
problem }
f0 {\f10 Solulion: }
fi363 {\b0 \f20 \fs17 In}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs18 3-12.}{\f20 \f
s18 thc}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 pulscs}{\b0 \f20 \fs17 woul
d}{\fs18 bc}{\f10 \fs16 as}{\b0 \f20 \fs18 follows: }\par
}
lsc{\b \f30 \fs14 U}{\b \f30 \fs14 -} I
\par}{\phpg\posx1477\pvpg\posy7744\absw922\absh399 \sl-222 \f20 \fs17 \cf0 pulsc
{\b\i \fs17 h}{\f10 \fs17 =}{\b \f10 \fs16 1 }\par
}
lsc{\b\i \f10 \fs15 c}{\b\i \f10 \fs15 -}{\b\i \f10 \fs15 0 }
fs16 pulse}{\b\i \f10 \fs17 d}{\f10 \fs14 =}{\b \f10 \fs15 1 }\par
}
ulsc{\b \f10 \fs16 e}{\b \f10 \fs16 -}{\b \f10 \fs16 1 }
\f30 \fs19 ~}{\b \f30 \fs19 U}{\b \f30 \fs19 I}{\b \f30 \fs19 W}{\i \f10 \fs1
7
f-}{\b \f10 \fs16 1 }\par
}

lsc{\b \fs17 R}{\b \fs17 -}{\b \fs17 0 }
\par}{\phpg\posx5187\pvpg\posy7744\absw963\absh399 \sl-222 \f20 \fs17 \cf0 pulw{
\b\i \fs17 h}{\b \f10 \fs15
1 }\par
}
}
cf0 3 4{\f20 \fs19
THENOTGATE }
i360 {\fs18 A}{\b0 \f20 \fs19 NOT}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs20 is}{\b
0 \f20 \fs19 also}{\b0 \f20 \fs19 callcd}{\b0 \f20 \fs19 an}{\b0 \f20 \fs20
inverter.}{\fs18 A}{\b0 \f20 \fs19 NOT}{\b0 \f20 \fs19 gate,}{\b0 \f20 \fs20
or}{\b0 \f20 \fs19 inverter,}{\b0 \f20 \fs20 is}{\b0 \f20 \fs19 an}{\b0 \f20
\fs19 unusual}{\b0 \f20 \fs19 gate.}{\f30 \fs21 The}{\b0 \f20 \fs19 NOT}{\b
0 \f20 \fs19 gate }
b0 \f20 \fs19 has}{\b0 \f20 \fs19 only}{\b0 \f20 \fs19 one}{\b0 \f20 \fs19 in
put}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 onc}{\b0 \f20 \fs19 output.}{\b0 \f2
0 \fs19 Figure}{\f20 \fs20 3-13a}{\b0 \f20 \fs19 illustrates}{\b0 \f20 \fs19
the}{\b0 \f20 \fs19 logic}{\b0 \f20 \fs18 symbol}{\b0 \f20 \fs19 for}{\b0 \
f20 \fs19 the}{\b0 \f20 \fs19 inverter,}{\b0 \f20 \fs20 or}{\b0 \f20 \fs19 N
OT }
b0 \f20 \fs19 gate. }\par
}
0 34 \par
}
{\phpg\posx8927\pvpg\posy535\absw876\absh205 \f20 \fs17 \cf0 \f20 \fs17 \cf0 (CH
AP.{\fs18 3 }\par
}
f0 3.9 \par
}
f0 3.10 \par
}
\cf0 Input{\i \f10 \fs14
A }\par
}
-D- \par
}
fs13 \cf0 (a){\i0 \f20 \fs16 NOT-pate}{\i0 \fs14 symbol }
0 \fi797 {\b0\i0 \f20 \fs25 ou;t }\par
}
s14 \cf0 Y{\i0 \fs13
OuIDUI }\par
}
\f10 \fs16 \cf0 A = A
0 {\fs14 (c)}{\i0 \f20 \fs16 NOT}{\i0 \fs15 Bookan}{\i0 \fs14 expression }\pa
r
}
s15 \cf0 A \par

}
s17 \cf0 A \par
}
s14 \cf0 0 \par
}
f0 7-- \par
}
cf0 I \par
}
s14 \cf0 0 \par
}
fs15 \cf0 ( d ){\i0 \fs15 Douhle}{\i0 \f10 \fs13 invenion }\par
}
-0- \par
}
fs17 \cf0 (r){\b0\i0 \fs17 Alternative}{\b0\i0 \fs16 inverter}{\i0 \f30 \fs17
symbol }\par
}
fs15 \cf0 (h){\i0 \fs16 NOT-pte}{\i0 \fs16 truth}{\i0 \fs16 tabk }\par
}
nput{\b\i \f10 \fs15 A }\par
}
s14 \cf0 y{\b0\i0 \f20 \fs17 Output }\par
}
\cf0 Fig.{\fs18 3-13 }\par
}
}
}
\par
}
\cf0 The process of inverting is simple. Figure{\fs19 3-13b} is the truth tabl
e for the NOT gate. The input is
\par}{\phpg\posx861\pvpg\posy1334\absw9192\absh860 \sl-242 \f20 \fs18 \cf0 alway
s changed to its opposite.{\b \fs19 If} the input is{\fs19 0,} the NOT gat
e will give its{\b\i \fs19 complement,} or opposite,
\par}{\phpg\posx861\pvpg\posy1334\absw9192\absh860 \sl-237 \f20 \fs18 \cf0 which
is{\fs19 1.} If the input to the NOT gate is a{\fs19 1,}the circuit will comp
lement it to give a{\b \fs18 0.} This inverting
\par}{\phpg\posx861\pvpg\posy1334\absw9192\absh860 \sl-237 \f20 \fs18 \cf0 is al
so called{\b\i \fs19 complementing} or{\b\i \fs19 negating.} The terms negat

ing, complementing, and inverting all mean \par
}
e same thing. \par
}
he Boolean expression for inverting is shown in Fig.{\fs19 3-1%.} The expre
ssion{\b\i \f10 \fs18 A}{\i \f30 \fs30 =A }\par
}
{\phpg\posx8715\pvpg\posy2533\absw997\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 re
ads as{\b\i A }\par
}
{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \f20 \fs18 \cf0 \f20 \fs18 \cf0 e
quals the output{\b\i \fs19 not}{\b\i A.} The bar over the{\b\i \fs19 A} m
eans to complement{\b\i \f10 \fs18 A.} Figure{\fs19 3-13d} illustrates what
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-237 \f20 \fs18 \cf0 woul
d happen if{\fs19 two} inverters were used. The Boolean expressions a
re written above the lines
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-259 \f20 \fs18 \cf0 betw
een the inverters. The input{\b\i \f10 \fs18 A} is inverted to A h o t{\b\i
\f10 \fs17 A).} The{\i \f30 \fs28 A} is then inverted again to{\fs19 form}{\i
\f30 \fs28 A }
728 is equal to the original{\b\i \f10 \fs18 A,} as shown in Fig.{\fs19 3-1
3d.} In the
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-235 \f20 \fs18 \cf0 shad
ed section below the inverters, a{\fs19 0} bit is the input. The{\fs19 0} bit
is complemented to a{\fs19 1.} The{\fs19 1} bit is
lemented again back to a{\fs19 0.} After a digital signal goes through two in
verters, it is restored to its
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-231 \f20 \fs18 \cf0 orig
inal form.
68 {\b\i \f10 \fs18 An} alternative logic symbol for the NOT gate{\fs19 or} inv
erter is shown in Fig.{\fs19 3-13e.} The{\b\i \fs19 invert}{\fs19 bubble }
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-232 \f20 \fs18 \cf0 may
be{\fs19 on} either the input or the output side of the triangular
symbol. When the invert bubble
0 appears{\fs19 on} the input side of the NOT symbol (as in Fig.{\fs
19 3-13e),} the designer is usually trying to
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-239 \f20 \fs18 \cf0 sugg
est that this is an{\b\i \fs19 active}{\i \fs19 LOW} input.{\b\i \f10 \fs
17 An} active LOW input requires a LOW to activate some
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-236 \f20 \fs18 \cf0 func
tion in the logic circuit. The alternative NOT gate symbol is commonly us
ed in manufacturer's
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-239 \f20 \fs18 \cf0 logi
c diagrams.
65 The laws of Boolean algebra govern the action{\fs19 of} the inverter, or NO
T gate. The formal Boolean
\par}{\phpg\posx853\pvpg\posy2759\absw9088\absh3783 \sl-230 \f20 \fs18 \cf0 alge
bra laws for the NOT gate are as follows:
786 {\fs24 6}{\fs24 =}{\fs24 i}{\fs26
i}{\fs26 =}{\fs26 o }
522 {\b \fs19 If}{\b\i \fs19 A}{\dn006 \f10 \fs13 =}{\fs19 1,} then{\i \fs2
4 A=O }\par
}
{\phpg\posx859\pvpg\posy3161\absw3941\absh503 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (n
ot not{\b\i \fs19 A).} The double inverted{\b\i A}{\i \f30 \fs26 (2) }\pa
r
}
f{\b\i \f10 \fs17 A}{\f10 \fs14 =}{\fs19 0,}{\fs18 then}{\i \f30 \fs27 A=
}
90 {\f10 \fs19 - }
26 {\b\i \fs24 A=A }\par
}
\par
}
{\phpg\posx859\pvpg\posy7556\absw8046\absh956 \f20 \fs19 \cf0 \f20 \fs19 \cf0 Yo
u{\fs18 can}{\fs18 check}{\fs18 these}{\fs18 general}{\fs18 statements}{\fs
18 against}{\fs18 the}{\fs18 truth}{\fs18 table}{\fs18 and}{\fs18 diagrams
}{\fs18 in}{\fs18 Fig.}{\fs19 3-13. }
\f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }
fs18 3.11}{\fs18
In}{\fs18 Fig.}{\fs19 3-14,}{\fs18 what}{\fs18 is}{\fs
18 the}{\fs18 output}{\fs18 at}{\fs18 point}{\fs17 (e)}{\fs18 if}{\fs18
the}{\fs18 input}{\fs18 at}{\fs18 point}{\i \f10 \fs16 (a)} is{\fs18 a}{\f
s18 0}{\fs18 bit? }\par
}
\cf0 Fig. 3-14{\b0
Inverter}{\b0 problem }\par
}
0 \fs17 \cf0 Solution:
\fi947 {\b0 The}{\b0 output}{\b0 at}{\b0 point}{\i \fs16 (}{\i \fs16 e}{
\i \fs16 )}{\b0 is}{\b0 a}{\b0 \fs17 0}{\b0 bit. }
cf0 {\fs18 3.12}{\b0 \fs18
What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 B
oolean}{\b0 \fs18 expression}{\b0 \fs18 at}{\b0 \fs18 point}{\b0 \fs18 (b)}
{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 3-14? }
\fi610 Solution:
\fi957 {\b0 The}{\b0 Boolean}{\b0 expression}{\b0 at}{\b0 point}{\b0\i \
fs17 (b)}{\b0 is}{\b0 A(not}{\i \f10 \fs16 A). }
cf0 {\fs18 3.13}{\b0 \fs18
What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 B
oolean}{\b0 \fs18 expression}{\b0 \fs18 at}{\b0 \fs18 point}{\fs19 (c)}{\b
0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 3-14? }
\fi606 Solution:
\fi958 {\b0 The}{\b0 Boolean}{\b0 expression}{\b0 at}{\b0 point}{\i \fs17
(}{\i \fs17 c}{\i \fs17 )}{\b0 is}{\b0 z(not}{\b0 not}{\i \f10 \fs16 A
).}{\b0 Aequals}{\i \f10 \fs15 A}{\b0 according}{\b0 to}{\b0 the}{\b0 \fs
17 laws}{\b0 \fs17 of}{\b0 \fs17 Boolean }
\fi606 {\b0 algebra. }\par
}
0 36 \par
}
SICLOGIC GATES \par
}
AP.{\b 3 }\par
}
cf0 3.14{\b0 \fs18
What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 Boolean}{
\b0 \fs18 expression}{\b0 \fs18 at}{\b0 \fs18 point}{\i \f10 \fs18 (}{\i \
f10 \fs18 d}{\i \f10 \fs18 )}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-14?
}
i606 {\fs16 Solution:}{\b0 \f10 \fs11
- }
i958 {\b0 \fs17 The}{\b0 \fs17 Boolean}{\b0 \fs17 expression}{\b0 \fs17 at}{\
b0 \fs17 point}{\i \f10 \fs15 (}{\i \f10 \fs15 d}{\i \f10 \fs15 )}{\b0 \fs17
is}{\b0 \fs17 z(not}{\b0 \fs17 not}{\b0 \fs17 not}{\i \fs16 A). }\par
}
}
{\phpg\posx6761\pvpg\posy1925\absw758\absh261 \f20 \fs17 \cf0 \f20 \fs17 \cf0 eq
uals{\i \f30 \fs25 A }\par
}
ot{\b\i \f10 \fs16 A). }\par
}
cf0 3.15{\b0 \fs18
What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 output}{\
b0 \fs18 at}{\b0 \fs18 point}{\i \f10 \fs18 (}{\i \f10 \fs18 d}{\i \f10 \fs1
8 )}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-14}{\b0 if}{\b0 \fs18 the}{
\b0 \fs18 input}{\b0 \fs18 at}{\b0 \fs18 point}{\b0\i \f10 \fs16 (a)}{\b0 \
fs18 is}{\b0 \fs18 a}{\b0 \fs18 1}{\b0 \fs18 bit? }
i966 {\b0 \fs17 The}{\b0 \fs17 output}{\b0 \fs17 at}{\b0 \fs17 point}{\i \f
s16 (}{\i \fs16 d}{\i \fs16 )}{\fs17 is}{\b0 \fs17 a}{\b0 \fs17 0}{\b0 \f
s17 bit. }\par
}
cf0 3.16{\b0 \fs18
The}{\b0 \fs18 NOT}{\b0 \fs18 gate}{\b0 \fs18 is}{\b0
\fs18 said}{\b0 \fs18 to}{\b0\i \fs18 invert}{\b0 \fs18 its}{\b0 \fs18 in
put.}{\b0 \fs18 List}{\b0 two}{\b0 \fs18 other}{\b0 \fs18 words}{\b0 \fs18
we}{\b0 \fs18 can}{\b0 \fs18 use}{\b0 \fs18 instead}{\b0 of}{\b0 \fs18 "i
nvert." }
i960 {\b0 \fs17 The}{\b0 \fs17 words}{\b0\i \fs17 complement}{\b0 \fs17 and}
{\i \fs16 negate}{\b0 \fs17 also}{\b0 \fs17 mean}{\b0 \fs16 to}{\b0 \fs17
invert. }\par
}
cf0 3.17{\b0 \fs18

The}{\b0 \fs18 NOT}{\b0 \fs18 gate}{\b0 \fs18 can}{\b0
\fs18 have }
0 \fi606 {\fs16 Solution: }\par
}
one, many) input variableh). \par
}
he NOT gate can have one input variable. \par
}
\cf0 3-5{\fs18
COMBINING}{\fs18 LOGIC} GATES
fi361 {\b0 \fs18 Many}{\b0 \fs18 everyday}{\b0 \fs18 digital}{\b0 \fs18 logic
}{\b0 \fs18 problems}{\b0 \fs18 use}{\b0 \fs18 several}{\b0 \fs18 logic}{\b0
\fs18 gates.}{\b0 \fs18 The}{\b0 \fs18 most}{\b0 \fs18 common}{\b0\i \fs18
pattern}{\b0 \fs18 of}{\b0 \fs18 gates}{\b0 \fs18 is }
\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-15a.}{\b0 \fs18
This}{\b0 \fs18 pattern}{\b0 \fs18 is}{\b0 \fs18 called}{\b0 \fs18 th
e}{\b0 \fs18 AND-OR}{\b0 \fs18 pattern.}{\b0 \fs18 The}{\b0 \fs18 output
s}{\b0 \fs19 of}{\b0 \fs18 the} AND{\b0 \fs18 gates }
\b0 \fs18 (1}{\b0 \fs18 and}{\fs18 2)}{\b0 \fs18 are}{\b0 \fs18 feeding}{\
b0 \fs18 the}{\b0 \fs18 inputs}{\b0 of}{\b0 \fs18 the}{\b0 \fs18 OR}{\
b0 \fs18 gate}{\b0 (3).}{\b0 \fs18 You}{\b0 \fs18 will}{\b0 \fs18 note}{\
b0 \fs18 that}{\b0 \fs18 this}{\b0 \fs18 logic}{\b0 \fs18 circuit}{\b0 \f
s18 has}{\b0 \fs18 three }
\b0 \fs18 inputs}{\i \fs18 (A,}{\i \fs18 B,}{\b0 \fs18 and}{\b0 \fs19 C).}{\
b0 \fs18 The}{\b0 \fs18 output}{\b0 of}{\b0 \fs18 the}{\b0 \fs18 entire}{\b
0 \fs18 circuit}{\b0 is}{\b0 \fs18 labeled}{\i \fs18 Y. }
\par}{\phpg\posx887\pvpg\posy7401\absw9120\absh2286 \sl-210 \par\par\b \f20 \fs1
8 \cf0 \fi5394 {\i \f10 \fs13 A }
f0 \fi5414 {\i \f10 \fs13 B }
f0 \fi240 {\b0 \fs14 Inputs }\par
}
\cf0 C \par
}
\cf0 C \par
}
\cf0 C \par
}
9 \cf0 ( U ) \par
}
\cf0 AND-OR{\b0 logic}{\b0 circuit }\par
}
(b){\fs14 Boolean}{\fs14 expressions}{\fs14 at}{\fs14 the}{\fs14 outputs}{
\fs15 of}{\fs14 the }
265 {\b \fs14 AND}{\fs14 gates }\par
}
(c){\fs14 Boolean}{\fs14 expression}{\fs14 at}{\fs14 the}{\fs14 output} o
f{\fs14 the}{\b \fs14 OR}{\fs14 gate }
\fi1212 {\b \fs16 Fig.}{\b \fs16 3-15 }\par
}
. 31 \par
}
}
f0 37 \par
}
\cf0 Let us first determine the Boolean expression that will describe
this logic circuit. Begin the
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-242 \f20 \fs18 \cf0 exam
ination at gate (1).This is a 2-input AND gate. The output of this gate will be{
\b\i \fs18 A}{\f10 \fs27 -}{\i \fs19 B}{\b\i \fs18 (}{\b\i \fs18 A} AND{\b\
i \fs18 B). }
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-237 \f20 \fs18 \cf0 This
expression is written at the output of gate (1) in Fig.{\i \fs18 3-15b.} Gate
(2) is also a 2-input AND gate.
output of this gate will be{\b\i \fs18 B}{\i \fs19
C}{\i (}{\i B} AND{\i
\fs18 C).} This expression is written at the output of gate (2).
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-235 \f20 \fs18 \cf0 Next
the outputs of gates (1) and{\fs19 (2)} are ORed together by gate{\i \fs1
8 (3).}Figure{\i \fs18 3-15c} shows{\b\i \fs18 AB} being
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-236 \f20 \fs18 \cf0 ORed
with{\b\i \fs18 BC.} The resulting Boolean expression is{\b\i \fs18 AB}
{\f10 \fs29 +}{\i\dn006 BC}{\dn006 \f10 \fs13 =}{\i \fs19 Y.} The Boolean
expression{\b\i \fs18 AB}{\f10 \fs28 + }
\fs19 BC}{\f10 \fs14 =}{\b\i \fs19 Y} is read as{\b\i \fs19 (}{\b\i \fs19
A} AND{\i B}{\i )} OR{\i \fs19 (}{\i \fs19 B} AND{\i \fs18 C}{\i \fs18
)} will equal a{\i 1} at output{\i \fs19 Y.} You will note that the
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-235 \f20 \fs18 \cf0 ANDi
ng is done first, and finally the ORing is done.
59 The next question arises. What is the truth table{\fs18 for} the AND
-OR logic diagram in Fig.{\i \fs18 3-15? }
232 {\i \fs19 Y.} The
ean expression tells us that if{\i \fs18 both} variables{\b\i A} AND{\i
\fs19 B} are 1, the output will be{\b \fs18 1.} Figure{\i \fs18 3-16 }
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-237 \f20 \fs18 \cf0 illu
strates that the last two lines of the truth table have{\fs18 1s} in{\i \fs18
both} the{\b\i \fs18 A} and{\i B} positions. Therefore
\par}{\phpg\posx843\pvpg\posy1341\absw9080\absh2795 \sl-239 \f20 \fs18 \cf0 an o
utput{\b \fs18 1} is placed under the{\i Y} column. \par
}
{\phpg\posx851\pvpg\posy3380\absw8302\absh439 \f20 \fs18 \cf0 \f20 \fs18 \cf0 Fi
gure{\i \fs18 3-16} will help us determine the truth table for the Bo
olean expression{\b\i \fs18 AB}{\f10 \fs28 +}{\i\dn006 \fs18 BC}{\dn006 \f10

\fs13 = }\par
}
\cf0 Fig.{\fs16 3-16}{\b0 \fs17
Complementing}{\b0 \fs17 output}{\b0 \fs17
column}{\b0 \fs17 of}{\b0 \fs17 truth}{\b0 \fs17 table}{\b0 \fs17 from}{\
b0 \fs17 a}{\b0 \fs17 Boolean}{\b0 \fs17 expression }\par
}
\cf0 The Boolean expression then goes on to say that another condition will als
o generate an output of
\fs18 1.} The expression says that{\i \fs19 B} AND{\i \fs18 C} will also
generate a{\b \fs17 1} output. Looking at the truth table, it is
\par}{\phpg\posx853\pvpg\posy9375\absw8977\absh1506 \sl-239 \f20 \fs18 \cf0 foun
d that the fifth line from the bottom has{\i \fs18 1s} in{\i \fs18 both} the{
\i \fs19 B} AND{\i \fs18 C} positions. The bottom line also
\par}{\phpg\posx853\pvpg\posy9375\absw8977\absh1506 \sl-236 \f20 \fs18 \cf0 has{
\i \fs19 1s} in{\i \fs18 both} the{\i \fs19 B} AND{\i \fs18 C} position
s. Both of these lines will generate a{\b \fs18 1} output. The bottom line
\par}{\phpg\posx853\pvpg\posy9375\absw8977\absh1506 \sl-237 \f20 \fs18 \cf0 alre
ady has a{\b \fs18 1} under the output column{\i (Y).}The fifth line up will a
lso get a{\b 1} in the output column
\fs19 (Y).}These are the only combinations that will generate{\fs18 a}{\b 1}
output. The rest{\fs18 of} the combinations are
\par}{\phpg\posx853\pvpg\posy9375\absw8977\absh1506 \sl-242 \f20 \fs18 \cf0 then
listed as{\fs18 0} outputs under column{\i \fs19 Y. }\par
}
SOLVED{\fs16 PROBLEMS }
{\b \f20 \fs18 3.18}{\f20 \fs18
What}{\f20 \fs18 is}{\f20 \fs18 the}{\f2
0 \fs18 Boolean}{\f20 \fs18 expression}{\f20 \fs18 for}{\f20 \fs18 the}{\f20
\fs18 AND-OR}{\f20 \fs18 logic}{\f20 \fs18 diagram}{\f20 \fs18 in}{\f20 \fs
18 Fig.}{\i \f20 \fs18 3-17? }
958 {\f20 \fs17 The}{\f20 \fs17 Boolean}{\f20 \fs17 expression}{\f20 \fs17
for}{\f20 \fs17 the}{\f20 \fs17 logic}{\f20 \fs17 circuit}{\f20 \fs17 sho
wn}{\f20 \fs17 in}{\f20 \fs17 Fig.}{\f20 \fs16 3-17}{\f20 \fs17 is }
\fi4190 {\i \f20 \fs21 AB}{\fs26 +}{\b\i\dn006 \f20 \fs16 AC}{\dn006 \fs11 =}
{\i\dn006 \f20 \fs17 Y }
\fi598 {\f20 \fs17 The}{\f20 \fs17 expression}{\f20 \fs17 is}{\f20 \fs17 r
ead}{\f20 \fs17 as}{\f20 \fs17 (not}{\b\i \f20 \fs16 A}{\f20 \fs17 AND}{\
i \f20 \fs17 B}{\i \f20 \fs17 )}{\f20 \fs17 OR}{\b\i \f20 \fs16 (}{\b\i \f2
0 \fs16 A}{\f20 \fs17 AND}{\f20 \fs17 C)}{\f20 \fs17 equals}{\f20 \fs17 o
utput}{\i \f20 \fs17 Y. }\par
}
0 38 \par
}
}

}
\par
}
\par
}
15 \cf0 C \par
}
14 \cf0 A
{\f20 \fs15 C }\par
}
\cf0 Fig.{\fs17 3-17}{\b0 \fs17
AND-OR}{\b0 \fs17 logic-circuitproblem }\pa
r
}
cf0 3.19{\b0 \fs19
What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 truth}{\b
0 \fs19 table}{\b0 \fs19 for}{\b0 \fs19 the}{\b0 \fs19 logic}{\b0 \fs19 dia
gram}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 3-17? }
}
s17 \cf0 A
\fi32 {\b0\i0 \fs17 0 }
\fi32 {\b0\i0 0 }
\fi32 {\b0\i0 0 }
\fi30 {\b0\i0 0 }\par
}
nputs
\fi173 {\b\i B }
05 {\fs17 0 }
03 0
05 1
05 1 \par
}
s17 \cf0 C
\fi31 {\b0\i0 \fs17 0 }
\fi27 {\b0\i0 1 }
\fi31 {\b0\i0 0 }
\fi33 {\b0\i0 1 }\par
}
utput
\fi227 Y
33 0
33 {\fs16 0 }
47 {\fs17 1 }
43 {\fs17 1 }\par
}
{\phpg\posx5723\pvpg\posy5821\absw156\absh1191 \b\i
s17 \cf0 A
\fi46 {\b0\i0 1 }
\fi43 {\b0\i0 1 }
\fi46 {\b0\i0 \fs17 1 }
\fi43 {\b0\i0 \fs17 1 }\par
}
nputs
\fi170 {\b\i B }
17 0
15 0
17 {\fs17 1 }
13 {\fs17 1 }\par
}
s17 \cf0 C
\fi49 {\b0\i0 0 }
\fi47 {\b0\i0 1 }
\fi49 {\b0\i0 \fs17 0 }
\fi42 {\b0\i0 \fs17 1 }\par
}
utput
\fi228 {\b\i Y }
33 0
44 {\fs17 1 }
\sl-260 \b\i \f20 \fs17 \cf0

\fs17 \cf0 \f20 \fs17 \cf0 O
\sl-175 \par\f20 \fs17 \cf0
\sl-340 \f20 \fs17 \cf0 \fi2
\sl-256 \f20 \fs17 \cf0 \fi2
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-256 \f20 \fs17 \cf0 \fi2
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-341 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 I
\sl-175 \par\f20 \fs17 \cf0
\sl-341 \f20 \fs17 \cf0 \fi2
\sl-254 \f20 \fs17 \cf0 \fi2
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-256 \f20 \fs17 \cf0 \fi2
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-341 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 O
\sl-178 \par\f20 \fs17 \cf0
\sl-335 \f20 \fs17 \cf0 \fi2
\sl-254 \f20 \fs17 \cf0 \fi2
\sl-260 \f20 \fs17 \cf0 \fi2
34 0
43 {\fs17 1 }\par
}
\cf0 3.20{\b0 \fs19
What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 Boolean}
{\b0 \fs19 expression}{\b0 \fs19 for}{\b0 \fs19 the}{\fs19 AND-OR}{\b0 \fs1
9 logic}{\b0 \fs19 diagram}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 3-18? }
f0 \fi2234 {\i \f10 \fs14 A }
fi2248 {\i \fs15 B }
fi2231 {\i \fs14 C }
8 \cf0 \fi7128 {\i \fs15 Y }\par
}
\cf0 Fig.{\fs16 3-18}{\b0 \fs17
AND-OR}{\b0 \fs17 logic-circuitproblem }\p
ar
}
\cf0 Solution:
\fi355 {\b0 \fs17 The}{\b0 \fs17 Boolean}{\b0 \fs17 expression}{\b0 \fs17 for
}{\b0 \fs17 the}{\b0 \fs17 logic}{\b0 \fs17 circuit}{\b0 \fs17 shown}{\b0
in}{\b0 \fs17 Fig.}{\b0 \fs17 3-18}{\b0 \fs17 is }\par
}
\cf0 The expression reads as{\b\i (}{\b\i A} AND{\b\i B}{\fs17 AND}{\b
\i \f30 \fs18 C)}OR (not{\b\i A} AND not{\b\i B}{\fs17 AND} not{\b\i
C}{\b\i )} equals output{\fs17 Y. }
{\b \fs18 3.21}{\fs19
What}{\fs19 is}{\fs19 the}{\fs19 truth}{\fs19 tabl
e}{\fs19 for}{\fs19 the}{\fs19 logic}{\fs19 diagram}{\fs19 in}{\fs19 Fig.
}{\fs19 3-18? }\par
}
.{\fs16 31 }\par
}
}
f0 39 \par
}
cf0 Solution: \par
}
\par
}
\par
}
7 1 }\par
}
7 0 }\par
}
\par
}
\par
}
\f10 \fs15 1 }\par
}
\fs17 1 }\par
}
cf0 3.22{\b0
What}{\b0 is}{\b0 the}{\b0 Boolean}{\b0 expression}{\b0 f
or}{\b0 the}{\b0 \fs19 AND-OR}{\b0 logic}{\b0 diagram}{\b0 in}{\b0 Fig.}{\
b0 \fs19 3-19? }\par
}
0 \fs16 \cf0 Fig.{\fs17 3-19}{\b0 \fs17
AND-OR}{\b0 \fs17 logic-circuit}{\
b0 \fs17 problem }
f0 Solution:
fi348 {\b0 \fs17 The}{\b0 \fs17
Boolean}{\b0 \fs17
expression}{\b0 \fs17
for}{\b0 \fs17
the}{\b0 \fs17
logic}{\b0 \fs17 circuit}{\b0 \fs17
sh
own}{\b0 \fs17
in}{\b0 \fs17
Fig.}{\b0 3-19}{\b0 \fs17 is}{\i \fs17
ABT}{\b0\i \fs17 +A'C }\par
}
24 \cf0 + x E \par
}
\i \f20 \fs17 Y.}{\f20 \fs17 The }\par
}
f0 3.23 \par
}
expression reads{\fs17 as}{\b\i \fs17 (}{\b\i \fs17 A} AND{\i B}{\fs17
AND} not{\i \fs17 C}{\i \fs17 )} OR (not{\b\i \f10 \fs16
A}{\b \fs17
AND}{\i \fs17 C}{\i \fs17 )} OR (not{\b\i \f10 \fs16
A} AND not{\b\i
B}{\b\i )} equals
\par}{\phpg\posx1439\pvpg\posy8472\absw8250\absh1263 \sl-218 \f20 \fs17 \cf0 out
put{\b\i \fs17 Y. }
{\fs18 What}{\fs18 is}{\fs18 the}{\fs18 truth}{\fs18 table}{\fs18 for}{\f
s18 the}{\fs18 logic}{\fs18 diagram}{\fs18 in}{\fs18 Fig.}{\fs19 3-19? }
}
nputs \par
}
1{\f20 \fs17
Output}{\b \fs31 I }\par
}
nputs \par
}
{\f20 \fs17
Output }\par
}
\cf0 3-6 USING PRACTICAL LOGIC GATES
fi366 {\b0 Logic}{\b0 functions}{\b0 can}{\b0 be}{\b0 implemented}{\b0 in}
{\b0 several}{\b0 ways.}{\b0 In}{\b0 the}{\b0 past,}{\b0 vacuum-tube}{\b0
and}{\b0 relay}{\b0 circuits }
\b0 performed}{\b0 logic}{\b0 functions.}{\b0 Presently}{\b0 tiny}{\i \fs
18 integrated}{\i circuits}{\b0 \fs19 (ICs)}{\b0 perform}{\fs19 as}{\b0
logic}{\b0 gates.}{\b0 These}{\fs19 ICs }
\b0 contain}{\b0 the}{\b0 equivalent}{\b0 of}{\b0 miniature}{\b0 resistor
s,}{\b0 diodes,}{\b0 and}{\b0 transistors. }\par
}
par
}
}
}
{\phpg\posx4225\pvpg\posy1890\absw453\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Pi
n{\f10 \fs14 1 }\par
}
0 \fs16 \cf0 Fig. 3-20{\fs17
14-pin}{\fs17 DIP}{\b0 \fs17 integrated}{\b0 \
fs17 circuit }
f0 \fi383 {\fs19 A}{\b0 \fs19 popular}{\b0 \fs19 type}{\b0 \fs19 of}{\fs19
IC}{\b0 \fs19 is}{\b0 \fs19 illustrated}{\b0 \fs19 in}{\b0 \fs19 Fig.}
{\b0 \fs19 3-20.}{\b0 \fs19 This}{\b0 \fs19 case}{\b0 \fs19 style}{\b0 \f
s19 is}{\b0 \fs19 referred}{\b0 \fs19 to}{\b0 \fs19 as}{\b0 \fs19 a}{\
i \fs19 dual-in-line }
\i \fs19 package}{\fs19 (DIP)}{\b0 \fs19 by}{\fs19 IC}{\b0 \fs19 manufacture
rs,}{\b0 \fs19 This}{\b0 \fs19 particular}{\fs19 IC}{\b0 \fs19 is}{\b0 \fs1
9 called}{\b0 \fs19 a}{\b0 \fs19 14-pin}{\b0 \fs19 DIP}{\b0 \fs19 integrat
ed}{\b0 \fs19 circuit. }
fi390 {\b0 \fs19 Note}{\b0 \fs19 that}{\b0 \fs19 immediately}{\i \fs19 cou
nterclockwise}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19 notch}{\b0 \fs19
on}{\b0 \fs19 the}{\fs19 IC}{\b0 \fs19 shown}{\b0 \fs19 in}{\b0 \fs19
Fig.}{\b0 \fs19 3-20}{\b0 \fs19 is}{\b0 \fs19 pin }
fi30 {\b0 \fs19 number}{\b0 \fs18 1.}{\b0 \fs19 The}{\fs18 pins}{\b0 \fs19 a
re}{\b0 \fs19 numbered}{\b0 \fs19 counterclockwise}{\b0 \fs19 from}{\b0 \fs
18 1}{\b0 \fs19 to}{\b0 \fs19 14}{\i \fs19 when}{\i \fs19 viewed}{\i \f30 \f
s18 from}{\i \fs19 the}{\i \fs19 top}{\b0 \fs19 of}{\b0 \fs19 the}{\fs19 I
C. }

fi35 {\b0 \fs19 Manufacturers}{\b0 \fs19 of}{\fs19 ICs}{\b0 \fs19 provide}{\b
0 \fs19 pin}{\b0 \fs19 diagrams}{\b0 \fs19 similar}{\b0 \fs19 to}{\b0 \fs19
the}{\b0 \fs19 one}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 3-21}{\b0 \fs19
for}{\b0 \fs19 a}{\b0 \fs19 7408}{\fs19 IC.}{\b0 \fs19 Note}{\b0 \fs19 th
at}{\b0 \fs19 this }
fi35 {\fs19 IC}{\b0 \fs19 contains}{\b0 \fs19 four}{\b0 \fs19 2-input}{\fs19
AND}{\b0 \fs19 gates;}{\b0 \fs19 thus}{\b0 \fs19 it}{\b0 \fs19 is}{\b0 \fs1
9 called}{\b0 \fs19 a}{\i \fs19 quadruple}{\i \fs19 2-input}{\i \fs19 AND}{
\i \fs19 gate.}{\b0 \fs19 Figure}{\b0 \fs19 3-21}{\b0 \fs19 shows }
fi35 {\b0 \fs19 the}{\fs19 IC}{\b0 \fs19 pins}{\b0 \fs19 numbered}{\b0 \fs19
from}{\b0 \fs19 1}{\b0 \fs19 through}{\fs19 14}{\b0 \fs19 in}{\b0 \fs19
a}{\b0 \fs19 counterclockwise}{\b0 \fs19 direction}{\b0 \fs19 from}{\b0 \fs
19 the}{\b0 \fs19 notch.}{\b0 \fs19 The}{\i \fs19 power }
fi27 {\i \fs19 connections}{\b0 \fs19 to}{\b0 \fs19 the}{\fs19 IC}{\b0 \fs19
are}{\b0 \fs19 the}{\fs19 GND}{\b0 \fs19 (pin}{\b0 \fs19 7)}{\b0 \fs19 a
nd}{\b0\i \fs19 Vcc}{\b0 \fs19 (pin}{\fs19 14)}{\b0 \fs19 pins.}{\b0 \fs19
All}{\b0 \fs19 other}{\b0 \fs19 pins}{\b0 \fs19 are}{\b0 \fs19 the}{\b0 \f
s19 inputs}{\b0 \fs19 and }
fi29 {\b0 \fs19 outputs}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 four}{\fs19
AND}{\b0 \fs19 gates.}{\b0 \fs19 The}{\fs19 7408}{\fs19 IC}{\b0 \fs19 is
}{\b0 \fs19 part}{\b0 \fs19 of}{\b0 \fs19 a}{\b0 \fs19 family}{\b0 \fs19
of}{\b0 \fs19 logic}{\b0 \fs19 devices.}{\b0 \fs19 It}{\b0 \fs19 is}{\b0
\fs19 one}{\b0 \fs19 of}{\b0 \fs19 many }\par
}
26 \cf0 qq
\par}{\phpg\posx4195\pvpg\posy5136\absw2229\absh2333 \sl-1307 \i \f30 \fs126 \cf
0 {\i0 \f20 \fs130 xp }\par
}
cf0 1Y{\fs16 3 }\par
}
\fs15 \cf0 2Y{\fs15 6 }
0 {\f20 G}{\f20
N}{\f20
D}{\f20
~ }\par
}
cf0 I
\b \f20 \fs16 Fig.}{\b \f30 \fs17 3-21}{\f20 \fs17 Pin}{\f20 \fs17 diagram}{
\f20 \fs17 for}{\f20 \fs17 a}{\b \f20 \fs17 7408}{\f20 \fs17 IC }\par
}
\par
}
s16 \cf0 B
\cf0 {\f10 \fs13 (a)}{\i0 \fs15 AND-gate}{\i0 \fs15 logic}{\i0 \fs15 symbol }
\par
}
1 \cf0 6:: \par
}

cf0 11{\fs15 4Y }\par
}
cf0 output \par
}
cf0 Inputs \par
}
{\phpg\posx5327\pvpg\posy10420\absw3574\absh2307 \f10 \fs126 \cf0 \fi1460 \f10 \
fs126 \cf0 w
\par}{\phpg\posx5327\pvpg\posy10420\absw3574\absh2307 \sl-1372 \f10 \fs126 \cf0
{\fs137 !B,}{\fs123 p }\par
}
\cf0 (7408) \par
}
fs15 \cf0 (b){\i0 \fs15 Wiring}{\i0 \fs15 an}{\i0 \fs15 AND}{\i0 \fs15 gate}
{\i0 using}{\i0 \fs15 a}{\i0 \fs14 7408}{\i0 \f10 \fs14 1C }
\cf0 \fi1033 {\i0 \fs16 Fig.}{\i0 \f30 \fs17 3-22 }\par
}
\cf0 output \par
}
\par
}
\cf0 bl. \par
}
{\phpg\posx3079\pvpg\posy11427\absw794\absh181 \f30 \fs17 \cf0 \f30 \fs17 \cf0 A
j{\b \f20 \fs13 Inputs }\par
}
\cf0 150{\f20 \fs14 R }\par
}
{\phpg\posx8443\pvpg\posy12769\absw311\absh192 \f30 \fs36 \cf0 \f30 \fs36 \cf0 L
\par
}
\par
}
0 CHAP.{\b0 \fs17 31 }\par
}
}
\par
}
evices in the transistor-transistor logic{\fs19 (TTL)} family of logic circuits
.{\fs19 TTL} devices are currently among
most popular logic devices.

65 Given the logic diagram in Fig. 3-22a, wire a circuit using a 7408 IC. A
wiring diagram for the
\par}{\phpg\posx863\pvpg\posy1351\absw9066\absh2376 \sl-241 \f20 \fs19 \cf0 circ
uit is shown in Fig. 3-226. A 5-V power supply is used with all TTL devices. The
positive{\i \fs18 (V',)}
and
\par}{\phpg\posx863\pvpg\posy1351\absw9066\absh2376 \sl-232 \f20 \fs19 \cf0 nega
tive (GND) power connections are made to pins 14 and 7. Input switches{\b\i \fs1
8 (}{\b\i \fs18 A} and{\b\i B}{\b\i )} are wired to
\par}{\phpg\posx863\pvpg\posy1351\absw9066\absh2376 \sl-243 \f20 \fs19 \cf0 pins
1 and 2 of the 7408 IC. Note that, if a switch is in the up position, a logical
{\b \f10 \fs17 3}{\f10 \fs16 (+}5 V) is applied to
input of the AND gate. At the right, a light-emitting diode (LED) a
nd 150-ohm{\i \f30 \fs29 (a) }
\par}{\phpg\posx863\pvpg\posy1351\absw9066\absh2376 \sl-234 \f20 \fs19 \cf0 resi
stor are connected to ground. If the output at pin{\fs18 3} is HIG'H{\f10 \fs16
(+}{\i \fs18 5}{\b \fs18 V),} current will flow through the
\fs19 LED.} Lighting the LED indicates a HIGH, or{\fs19 a} binary{\fs18 1,} a
t the output{\fs19 of} the AND gate.
52 The truth table in Fig. 3-23 shows the results{\fs19 of} operating the 2-in
put AND circuit. The LED in
3-22b lights only when both input switches{\b\i \fs18 (}{\b\i \fs18 A} and{
\b\i B}{\b\i )} are at{\f10 \fs30 +}{\i \fs19 5} V. \par
}
{\phpg\posx9049\pvpg\posy2784\absw660\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 li
miting \par
}
cf0 Inputs \par
}
\par
}
cf0 Output \par
}
cf0 GND
\par}{\phpg\posx3547\pvpg\posy5855\absw584\absh616 \sl-223 \b \f20 \fs17 \cf0 GN
D
i \f10 \fs16 +}{\i \f10 \fs16 5}{\b0 \fs23 v }\par
}
cf0 GND
i \f10 \fs16 +}{\i \f10 \fs16 5}{\fs23 v }
\par}{\phpg\posx4507\pvpg\posy5855\absw572\absh594 \sl-220 \b \f20 \fs17 \cf0 GN
D \par
}
\cf0 Voltage
f0 \fi90 GND
fi95 GND

fi97 GND \par
}
\fs17 \cf0 LED
\fs17 lights? }
f0 \fi157 {\fs17 no }
fi159 {\fs17 no }
fi163 {\fs17 no }\par
}
\cf0 Fig.{\fs17 3-23}{\fs17
Truth}{\fs17 table}{\fs17 {\f63 \u8364\'3f}or}
{\fs17 a}{\fs17 TTL-type}{\fs17 AND}{\fs17 gate }\par
}
\cf0 Manufacturers{\f10 \fs16 o} integrated circuits also produce other logi
c functions. Figure
-24illustrates pin
\par}{\phpg\posx851\pvpg\posy7550\absw9064\absh856 \sl-233 \f20 \fs19 \cf0 diagr
ams for{\fs18 two} basic{\fs19 TTL} ICs. Figure 3-24a is the pin diagriam for
a quadruple 2-input{\i OR} gate. In
\par}{\phpg\posx851\pvpg\posy7550\absw9064\absh856 \sl-242 \f20 \fs19 \cf0 other
words, the 7432 IC contains four 2-input OR gates. It c:ould be wired and
tested in a manner
\par}{\phpg\posx851\pvpg\posy7550\absw9064\absh856 \sl-231 \f20 \fs19 \cf0 simil
ar to the testing of the AND gate shown in Fig. 3-22b. \par
}
{\phpg\posx3329\pvpg\posy8573\absw2123\absh993 \f10 \fs83 \cf0 \f10 \fs83 \cf0 :
:fcJ \par
}
0 I Y{\i \fs9
3 }\par
}
f10 \fs9 \cf0 I A
cf0 \fi190 {\i0 I}{\i0 Y }
cf0 \fi182 {\fs8 ZA }
cf0 \fi180 {\i0 \fs9 2}{\i0 \fs9 Y }
cf0 \fi194 3A
cf0 \fi182 {\i0 3}{\i0 Y }
cf0 {\i0 \f20 \fs11 GND }\par
}
fs16 \cf0 (a){\i0 Pin}{\i0 \fs15 diagram}{\i0 \fs15 for}{\i0 \fs15 a}{\i0 \f
s15 7432}{\i0 \fs15 IC}{\fs15
(b)}{\i0 Pin}{\i0 \fs15 diagram}{\i0 \fs15
for}{\i0 \fs15 a}{\i0 \fs15 7404}{\i0 \fs15 IC }
}
9 \cf0 The 7404 IC shown in Fig. 3-24b is also a{\fs19 TTL} device. The 7404 I
C contains{\fs19 six} NOT gates, or

\par}{\phpg\posx815\pvpg\posy12261\absw9127\absh1496 \sl-241 \f20 \fs19 \cf0 inv
erters. The 7404 is described by the manufacturer as a hex inverter IC. Note
that each IC has its
\par}{\phpg\posx815\pvpg\posy12261\absw9127\absh1496 \sl-231 \f20 \fs19 \cf0 pow
er connections{\i \fs18 (V,,}
and GND). A 5-V dc power supply is alway
s used with{\fs19 TTL} logic circuits.
356 Two variations of DIP ICs are illustrated in Fig. 3-25. The integrated circ
uit shown in Fig. 3-25a
\par}{\phpg\posx815\pvpg\posy12261\absw9127\absh1496 \sl-235 \f20 \fs19 \cf0 has
{\b \fs18 16} pins with pin 1 identified by using a dot instead of a not
ch. The IC shown in Fig. 3-25b is a
\par}{\phpg\posx815\pvpg\posy12261\absw9127\absh1496 \sl-236 \f20 \fs19 \cf0 24pin DIP integrated circuit with pin{\fs18 1} located immediately counterclock
wise (when viewed from the
\par}{\phpg\posx815\pvpg\posy12261\absw9127\absh1496 \sl-240 \f20 \fs19 \cf0 top
) from the notch. \par
}
par
}
SIC{\fs17 LOGIC} GATES \par
}
AP.{\fs17 3 }\par
}
a){\fs14 16-pin}{\fs15 DIP}{\fs14 integrated}{\fs14 circuit }\par
}
s15 \cf0 (h){\b0\i0 \fs14 24-pin}{\b0\i0 \fs14 DIP}{\b0\i0 \fs14 integrated}
{\b0\i0 \fs14 circuit }\par
}
0 \fs16 \cf0 Fig.{\fs16 3-25 }
f0 \fi360 {\b0 \fs18 The}{\b0 \fs18 7408,}{\b0 \fs18 7432,}{\b0 \fs18 and}{\b
0 \fs18 7404}{\b0 \fs18 ICs}{\b0 \fs18 you}{\b0 \fs18 studied}{\b0 \fs18 in
}{\b0 \fs18 this}{\b0 \fs18 section}{\b0 \fs18 were}{\b0 \fs18 all}{\b0 \fs1
8 from}{\b0 \fs18 the}{\b0 \fs19 TTL}{\b0 \fs18 logic}{\b0 \fs18 family.}{\
b0 \fs18 The }
\b0 \fs18 newer}{\b0\i \fs19 complementary}{\b0\i \fs19 metal}{\b0\i \fs19
oxide}{\b0\i \fs19 semiconductor}{\b0 \fs18 (CMOS)}{\b0 \fs18 family}{\b0 \
fs18 of}{\b0 \fs18 ICs}{\b0 \fs18 has}{\b0 \fs18 been}{\b0 \fs18 gainin
g}{\b0 \fs18 popularity }
\b0 \fs18 because}{\b0 \fs18 of}{\b0 \fs18 its}{\b0 \fs18 low}{\b0 \fs18 p
ower}{\b0 \fs18 requirements.}{\b0 \fs18 Logic}{\b0 \fs18 gates}{\fs18 (AN
D,}{\b0 \fs19 OR,}{\b0 \fs18 and}{\b0 \fs18 NOT)}{\b0 \fs18 also}{\b0 \fs18
are}{\b0 \fs18 available}{\b0 \fs19 in}{\b0 \fs18 DIP }
\b0 \fs18 IC}{\b0 \fs18 form}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 CMOS}{\
b0 \fs18 family.}{\b0 \fs18 Typical}{\b0 \fs18 DIP}{\b0 \fs18 ICs}{\b0 \fs1
8 might}{\b0 \fs18 be}{\b0 \fs18 the}{\b0 \fs18 CMOS}{\b0 \fs18 74C08}{\b0
\fs18 quad}{\b0 \fs18 2-input}{\fs18 AND}{\b0 \fs18 gate, }

\b0 \fs18 74C04}{\b0 \fs18 hex}{\b0 \fs18 inverter,}{\b0 \fs18 or}{\b0 \fs18
the}{\b0 \fs18 74C32}{\b0 \fs18 quad}{\b0 \fs18 2-input}{\b0 \fs18 OR}
{\b0 \fs18 gate.}{\b0 \fs18 The}{\b0 \fs18 74CXX}{\b0 \fs18 series}{\b0 \
fs18 of}{\b0 \fs18 CMOS}{\b0 \fs18 gates}{\b0 \fs18 is}{\b0\i \fs18 not
}
\b0 \fs18 directly}{\b0 \fs18 compatible}{\b0 \fs18 with}{\b0 \fs18 the}{\b0
\fs19 TTL}{\b0 \fs18 7400}{\b0 \fs18 series}{\b0 \fs18 of}{\b0 \fs18 integr
ated}{\b0 \fs18 circuits. }
f0 {\b0 \f10 SOLVED}{\b0 \f10 \fs16 PROBLEMS }
\fs18 3.24}{\b0 \fs18
What}{\b0 \fs18 logic}{\b0 \fs18 function}{\b0 \fs18
is}{\b0 \fs18 performed}{\b0 \fs18 by}{\b0 \fs18 the}{\b0 \fs18 circuit}{
\b0 \fs18 illustrated}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-26? }\par
}
T \par
}
v \par
}
r \par
}
tput
6 {\b\i \fs14 Y }\par
}
\cf0 -921 \par
}
0 \cf0 0 \par
}
{\phpg\posx1987\pvpg\posy8227\absw250\absh367 \f10 \fs31 \cf0 \f10 \fs31 \cf0 -{
\dn006 \fs21 + }\par
}
}
11 \cf0 0 \par
}
cf0 4 \par
}
cf0 11 \par
}
cf0 3.25 \par
}
cf0 3.26 \par
}
6 \cf0 Solution:

\fi354 {\b0 The}{\b0 7432}{\b0 IC}{\b0 performs}{\b0 as}{\b0 a}{\b0 2-i
nput}{\b0 \fs17 OR}{\b0 gate}{\b0 when}{\b0 wired}{\b0 as}{\b0 shown}
{\b0 in}{\b0 Fig.}{\b0 3-26. }
\par}{\phpg\posx1453\pvpg\posy10843\absw8461\absh2559 \sl-294 \par\b \f20 \fs16
\cf0 {\b0 \fs18 Write}{\b0 \fs18 the}{\b0 \fs18 Boolean}{\b0 \fs18 expressio
n}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 circuit}{\b0 \fs18 shown}{\b0 \fs
18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-26. }
Solution:
\fi354 {\b0 The}{\b0 Boolean}{\b0 expression}{\b0 for}{\b0 the}{\b0 2
-input}{\b0 \fs17 OR}{\b0 function}{\b0 (Fig.}{\b0 \fs17 3-26)}{\b0 is}{
\i \f10 \fs15 A}{\b0 \f10 \fs25 +}{\i\dn006 \fs17 B}{\b0\dn006 \f10 \fs11
=}{\b0\i \fs17 Y. }
\cf0 {\b0 \fs18 What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0\i \fs19 voltage}{\b0 \
fs18 of}{\b0 \fs18 the}{\b0 \fs18 power}{\b0 \fs18 supply}{\b0 \fs18 at}{\
b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 3-26?
}{\b0 \fs18 The}{\b0 \fs18 7432}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0 \fs19 a}{\
b0 \fs19 TTL}{\b0 \fs18 device. }
Solution:
\fi354 {\b0 \fs17 TTL}{\b0 devices}{\b0 use}{\fs17 a}{\f30 \fs18 5-V}{\b0
dc}{\b0 power}{\b0 supply. }\par
}
. 31 \par
}
}
f0 43 \par
}
cf0 3.27{\b0 \fs19
If}{\b0 \fs19 both}{\b0 \fs19 switches}{\i \fs18 A}
{\b0 \fs19 and}{\i \fs19 B}{\b0 \fs19 in}{\b0 \fs18 Fig.}{\fs19 3-26}{\
b0 \fs19 are}{\b0 \fs19 in}{\b0 \fs19 the}{\i \fs19 down}{\i \fs18 posit
iori}{\b0 \fs19 (toward}{\b0 \fs19 ground)}{\b0 \fs19 the}{\b0 \fs19 outp
ut }\par
}
ED{\fs19 will}{\fs19 be }
}
lit, not lit). \par
}
hen both inputs are 0, the output of the{\fs17 OR} gate will be 0 and
the output LED will be not lit. \par
}
cf0 3.28{\b0 \fs19
In}{\b0 \fs19 Fig.}{\fs19 3-26,}{\b0 \fs19 if}{\b0 \fs
19 switch}{\i \fs18 A}{\b0 \fs19 is}{\b0 \fs19 up}{\b0 \fs19 and}{\b0 \fs
19 switch}{\i \fs19 B}{\b0 \fs19 is}{\b0 \fs19 down,}{\b0 \fs19 the}{\b0

\fs19 output}{\b0 \fs19 LED}{\b0 \fs19 will}{\b0 \fs19 be }
i603 {\b0 \fs19 lit). }
}
{\phpg\posx9051\pvpg\posy2772\absw648\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 (l
it, not \par
}
\cf0 When input{\b\i \fs17 A} is{\b \fs17 1} and input{\i B}{\fs17
is}{\fs17 0} (Fig. 3-26), the output of the{\fs17 OR} gate will{\fs16 be
}{\fs17 1} and the output
\par}{\phpg\posx1445\pvpg\posy3626\absw8258\absh388 \sl-212 \f20 \fs17 \cf0 LED
will be lit. \par
}
cf0 3.29{\b0 \fs19
Pins}{\fs19 7}{\b0 \fs19 and}{\b0 \fs18 14}{\b0 \fs19
of}{\b0 \fs19 the}{\fs19 7432} IC{\b0 \fs19 are }
}
input, output, power) connections. \par
}
ins 7 and 14 of the 7432 IC are power connections.
\fi562 {\dn006 \f10 \fs15 (}{\f10 \fs30 +}{\i \fs19 5}{\b \fs18 V,}{\fs19 GND
)}{\fs19 voltage}{\fs19 at}{\fs19 pin}{\b \fs19 4}{\fs19 of}{\fs19 the}{\b
\fs19 7432}{\fs19 IC}{\fs19 will}{\fs19 cause}{\fs19 pin}{\fs19 6}{\fs19
to}{\fs19 go}{\fs19 to}{\fs19 a}{\fs19 HIGH}{\fs19 logic }\par
}
cf0 3.30{\fs18
A }
i603 {\b0 \fs19 level. }
}
he output (pin{\b \fs16 6)} goes HIGH anytime as input (such as pin 4)
is HIGH (near{\b\i \f10 \fs16 +}{\b\i \f10 \fs16 5}{\b \fs17
V). }\par
}
cf0 3.31{\b0 \fs19
The}{\b0 \fs19 letters}{\b0 \fs19 TTL}{\b0 \fs19 stand
}{\b0 \fs19 for }
}
par
}
cf0 3.32{\b0 \fs19
The }
}
he letters TTL stand for the popular transistor-transistor logic family o

f integrated circuits.
\fi646 {\f10 \fs15 -}{\fs19 (CMOS,}{\fs19 TTL)}{\fs19 logic}{\fs19 family}{
\fs19 is}{\fs19 characterized}{\fs19 by}{\fs19 its}{\fs19 very}{\fs19 low
}{\fs19 power}{\fs19 consumption. }\par
}
he{\b CMOS} logic family is noted for its{\fs16 very} low power consumptio
n. \par
}
cf0 3.33{\b0 \fs19
Integrated}{\b0 \fs19 circuits}{\b0 \fs19 from}{\b0 \f
s19 the}{\b0 \fs19 TTL}{\b0 \fs19 and}{\b0 \fs19 CMOS}{\b0 \fs19 families }
i603 {\b0 \fs19 a}{\b0 \fs19 digital}{\b0 \fs19 circuit. }
}
can,cannot) be interchanged in \par
}
7 \cf0 TTL{\fs17 and}{\fs17 CMOS}{\b \fs17 ICs}{\fs17 cannot}{\fs17 be
}{\fs17 interchanged}{\fs17 in}{\fs17 a}{\fs17 digital}{\fs17 circuit.
}{\fs17 They}{\fs17 may}{\fs17 have}{\fs17 the}{\fs17 same}{\fs17 lo
gic }
s17 function}{\fs17 or}{\fs17 even}{\fs17 have}{\fs17 the}{\fs17 same}{\f
s17 pin}{\fs17 diagram,}{\fs17 but}{\fs17 their}{\fs17 input}{\fs17 and}
{\fs17 output}{\fs17 characteristics}{\fs17 are}{\fs17 quite}{\fs17 differ
ent. }\par
}
cf0 3.34 \par
}
f10 \fs21 \cf0 Supplementary Problems
\cf0 \fi34 {\b0 \f20 \fs17 Draw}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 logic}{\
b0 \f20 \fs17 symbol}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17
6-input}{\b0 \f20 \fs17 AND}{\b0 \f20 \fs17 gate.}{\b0 \f20 \fs17 Label
}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 inputs}{\i \fs16 A,}{\i \f20 \fs17
B,}{\i \f20 \fs17 C,}{\b0\i \f20 \fs17 D,}{\b0\i \f20 \fs17 E,}{\b0 \f20 \
fs17 and}{\i \f20 \fs17
F.}{\b0 \f20 \fs17 Label}{\b0 \f20 \fs17 the }
\fi22 {\b0 \f20 \fs17 output}{\i \f20 \fs17 Y. }
{\b0 \f20 \fs17 Ans.}{\b0 \f20 \fs17
See}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \
fs17 3-27. }
\cf0 \fi27 {\b0 \f20 \fs17 Draw}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 logic}{\
b0 \f20 \fs17 symbol}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17
7-input}{\b0 \f20 \fs17 OR}{\b0 \f20 \fs17 gate.}{\b0 \f20 \fs17 Label}
{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 inputs}{\i \f20 \fs17 A}{\i \f20 \fs17
,}{\i \f20 \fs17 B,}{\i \f20 \fs16 C,}{\b0\i \f20 \fs17 D,}{\b0\i \f20 \
fs17 E,}{\i \f20 \fs17 F}{\i \f20 \fs17 ,}{\b0 \f20 \fs17 and}{\b0 \f20 \
fs17 G.}{\b0 \f20 \fs17 Label}{\b0 \f20 \fs17 the }
\fi25 {\b0 \f20 \fs17 output}{\i \f20 \fs17 Y. }

{\b0 \f20 \fs17 Ans.}{\b0 \f20 \fs17
See}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \
fs17 3-28. }\par
}
cf0 3.35 \par
}
0 44 \par
}
SICLOGIC{\fs17 GATES }\par
}
}
fs103 \cf0 :=py
0 {\f10 \fs53 AA }\par
}
15 \cf0 B
cf0 {\fs15 E }
cf0 F \par
}
\cf0 Fig.{\f30 \fs18 3-28}{\b0 \fs17 A}{\b0 \fs17 7-input }
fi478 {\b0 \fs17 OR}{\b0 \fs17 gate }\par
}
\cf0 Describe the pulse train at output{\b\i \fs17 Y} of the AND gate
shown in Fig. 3-29, if input{\b\i \fs18 B} is 0.
i \fs17 Ans.}{\fs17
A}{\fs17 0} will disable the AND gate, and the out
put will be 0. \par
}
\f20 \fs15 \cf0 E
\cf0 \fi50 {\fs15 F }
\cf0 {\i0 \fs17 Fig.}{\i0 \f30 \fs18 3-27}{\b0\i0 \fs17 A}{\b0\i0 \fs17 6-i
nput }
0 \fi402 {\b0\i0 \fs17 AND}{\b0\i0 \fs17 gate }\par
}
)+ \par
}
f0 3.36 \par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\f30 \fs18 3-29}{\b0 \fs17 Pulse-train}{\b0 \fs17 problem }\par
}
f0 3.37 \par
}
f0 3.38 \par
}
\cf0 Describe the pulse train at output{\b\i \fs17 Y} of the AND gate
shown in Fig. 3-29{\fs17 if} input{\fs18 B} is{\fs17 1. }
\i \fs17 Am.}
The output waveform will look exactly like the input wavefor
m at input{\fs17 A} (Fig. 3-29).
\fi30 Describe the pulse train at output{\b\i \fs17 Y} of the OR gate
shown in Fig. 3-30{\fs17 if} input{\fs17 B} is{\fs17 0. }
s17 Ans.}
The output waveform will look exactly like the input waveform a
t input{\b\i \f10 \fs16 A} (Fig. 3-30). \par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\f30 \fs18 3-30}{\b0 \fs17 Pulse-train}{\b0 \fs17 problem }\par
}
cf0 3.39 \par
}
cf0 3.40 \par
}
7 \cf0 Describe the pulse train at output{\b\i \fs17 Y} of the{\fs17
OR} gate shown in Fig. 3-30{\fs17 if} input{\fs17 B} is{\fs17 1. }
b\i \fs17 Am.}
The output will always be{\fs17 1. }
0 \fi25 Write the Boolean expression{\fs17 for} the logic circuit shown i
n Fig. 3-31.
b\i \fs17 Ans.}{\b\i \fs17
A}{\b\i \fs17 .}{\b\i \fs17 B}{\b\i \fs17 +}{\
b\i \fs17 B}{\b\i \fs17 .}{\b\i \fs17 C}{\b\i \fs17 =}{\b\i \fs17 Y} or{\b
\i \fs17 AB+BC=Y }\par
}
fs15 \cf0 B+
\cf0 {\f30 \fs17 C }
\cf0 \fi37 {\i0 \fs17 Fig.}{\i0 \f30 \fs18 3-31}{\b0\i0 \fs17 AND-OR}{\b0\i0
\fs17 logic-circuit}{\b0\i0 \fs17 problem }\par
}
. 31 \par
}
}
f0 45 \par
}
f0 3.41 \par
}
\cf0 Draw the truth table for the logic circuit shown in Fig. 3-31.
i \fs17 Ans. }\par
}
1 \par
}

\cf0 I{\f20 \fs17
Output} I
{\b\i \f20 \fs17 A}{\b\i \f20 \fs17 I}{\b\i \f20 \fs17
Y}{\fs16
I}{\fs16
C }\par
}
r
}
r
}
\cf0 I{\f20 \fs17
Output }
{\b\i \f20 \fs17 A}{\b\i \f20 \fs17 I}{\b\i \f20 \fs17
Y }\par
}
cf0 C \par
}
{\phpg\posx3915\pvpg\posy2157\absw524\absh517 \f20 \fs17 \cf0 \f20 \fs17 \cf0 In
puts
fi167 {\b\i \fs17 B }\par
}
puts
}
r
}
\par
}
\par
}
\fs17 1 }\par
}
\par
}
\cf0 Write the Boolean expression for{\f10 \fs19 -t}he logic circuit show
n in Fig. 3-32.
i \fs17 Ans.}{\b\i \fs17
x}{\b\i \fs17 .}{\b\i \fs17 B}{\b\i \fs17 .}{\b\
i \fs17 c}{\b\i \fs17 +}{\b\i \fs17 B}{\b\i \fs17 -}{\b\i \fs17 c}{\b\i \fs
17 =}{\b\i \fs17 Y}{\b\i \fs17 o}{\b\i \fs17 r}{\b\i \fs17 ABC+BC=Y }\par
}
\fs23
-_ }\par
}
f0 3.42 \par
}
\cf0 Fig.{\f30 \fs17 3-32}{\b0 \fs17 AND-OR}{\b0 \fs17 logic-circuit}{\b0 \f
s17 problem }\par
}
f0 3.43 \par
}
i \fs17 Ans. }\par
}
{\f20 \fs17
Output }
\f20 \fs5 I }
82 {\b\i \f20 \fs17 Y }
03 {\f20 \fs17 1 }
02 {\f20 \fs17 1 }
02 {\f20 \fs17 1 }
86 {\f20 \fs17 0 }\par
}
\par
}
m \par
}
s17 \cf0 C
{\b0\i0 0 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }\par
}
nputs
\fi187 {\b\i \fs17 B }
95 {\fs17 0 }
95 0
95 1
97 1 \par
}
{\dn006 \f20 \fs17

Output }
\fs5 1 }
77 {\b\i \f20 \fs17 Y }
\fi386 {\f20 \fs16 0 }
86 {\f20 \fs17 0 }
86 {\f20 \fs17 0 }
86 {\f20 \fs17 0 }\par
}
s17 \cf0 A
{\b0\i0 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }\par
}
s17 \cf0 C
\fi30 {\b0\i0 \fs17 1 }
\fi28 {\b0\i0 \fs17 1 }
\fi30 {\b0\i0 \fs17 1 }
\fi28 {\b0\i0 \fs17 1 }\par
}
nputs
\fi189 {\b\i \fs17 B }
13 0
13 0
13 1
13 1 \par
}
s17 \cf0 A
{\b0\i0 \fs17 0 }
\fi21 {\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
\fi21 {\b0\i0 \fs17 1 }\par
}
\sl-136 \f10 \fs33 \cf0 {\b

\sl-220 \f10 \fs33 \cf0 \fi3
\sl-167 \par\f10 \fs33 \cf0
\sl-258 \f10 \fs33 \cf0 \fi3
\sl-260 \f10 \fs33 \cf0 \fi3
\sl-253 \f10 \fs33 \cf0 \fi3
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-333 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-253 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-335 \b\i \f20 \fs17 \cf0
\sl-258 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-253 \b\i \f20 \fs17 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 I
\sl-178 \par\f20 \fs17 \cf0
\sl-335 \f20 \fs17 \cf0 \fi2
\sl-258 \f20 \fs17 \cf0 \fi2
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-253 \f20 \fs17 \cf0 \fi2
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-335 \b\i \f20 \fs17 \cf0
\sl-258 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-253 \b\i \f20 \fs17 \cf0

cf0 3.44 \par
}
Write the Boolean expression for the logic circuit shown in Fig. 3-33.
\par
}
fs17 \cf0 Ans.{\f30 \fs23 2.B. }
}{\phpg\posx1409\pvpg\posy10719\absw1225\absh249 \b\i \f20 \fs17 \cf0 \fi0 {\b0\
dn006 \f10 \fs15 C }\par
}
fs34 \cf0 +x. {\dn006 \f20 \fs17 B}{\b0\i0 \f10 \fs26 -}{\b0 \f20 \fs33 c}{\b
0\i0 \f10 \fs25 +}{\dn006 \f20 \fs17 A}{\fs25 .B-}{\b0 \f20 \fs32 c }\par
}
{\b\i \f20 \fs17 Y}{\f20 \fs17 or }\par
}
fs34 \cf0 x&'{\f20 \fs17
+}{\f20 \fs17 x}{\f20 \fs17 B}{\f20 \fs17 c}{\b0\
i0\dn006 \f10 \fs25 +}{\f20 \fs17 A}{\f20 \fs17 B}{\f20 \fs17 c}{\b0\i0 \f10
\fs13 =}{\f20 \fs17 Y }\par
}
cf0 3.45 \par
}
\i \fs17 Ans. }\par
}
\cf0 C
{\i0 \f20 \fs17 0 }
{\i0 \f20 \fs17 0 }
{\i0 \f20 \fs17 0 }
{\i0 \f20 \fs17 0 }\par
}
Inputs
\fi170 {\b\i \fs17 B }
192 0
193 {\fs16 0 }
206 {\fs16 1 }
206 1 \par
}
fs17 \cf0 A
0 \fi33 {\b0\i0 \fs17 0 }

0 \fi41 {\b0\i0 \fs16 1 }
0 \fi33 {\b0\i0 \fs17 0 }
0 \fi41 {\b0\i0 1 }\par
}
output
\fi224 {\i \fs17 Y }
230 {\fs16 0 }
246 {\fs16 1 }
246 1
230 0 \par
}
\cf0 C
\fi27 {\b\i0 \f20 \fs16 1 }
\fi27 {\i0 \f20 \fs16 1 }
\fi27 {\i0 \f20 \fs17 1 }
\fi27 {\i0 \f20 \fs17 1 }\par
}
Inputs
\fi166 {\b\i \fs17 B }
188 {\fs16 0 }
192 {\fs16 0 }
202 1
200 {\fs16 1 }\par
}
fs17 \cf0 A
0 \fi36 {\b0\i0 \fs17 0 }
0 \fi50 {\b0\i0 \fs17 1 }
0 \fi35 {\b0\i0 \fs17 0 }
0 \fi47 {\b0\i0 \fs17 1 }\par
}
output
\fi224 {\b\i \fs17 Y }
246 {\fs16 1 }
236 {\fs16 0 }
236 0
236 0 \par
}
0 46 \par
}
}
AP. 3 \par
}
\par
}
{\phpg\posx5111\pvpg\posy3507\absw73\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 I \
par
}
cf0 1
f20 \fs11 I }\par
}
\par
}
\cf0 Fig.{\fs16 3-33}{\b0 \fs17
AND-OR}{\b0 \fs17 logic-circuit}{\b0 \fs17
problem }\par
}
f0 3.46 \par
}
\cf0 Describe the pulse train at output{\b\i Y}{\fs17 of} the{\fs17 A
ND} gate shown{\fs17 in} Fig. 3-34.
i Ans. }\par
}
lse{\b\i \fs17 a}{\f10 \fs13 =} 0
{\fs17 b}{\f10 \fs13 =}{\fs17 1 }\par
}
lse{\fs16 c}{\f10 \fs13 =} 0
{\b\i \fs17 d}{\f10 \fs14 =}{\fs17 0 }\par
}
lse e{\f10 \fs13 =} 0
fs16 pulse}{\b\i \f30 \fs19 f}{\dn006 \f10 \fs13 =}{\fs17 1 }\par
}
lse{\fs15 g}{\f10 \fs13 =} 0
{\fs17 h}{\f10 \fs13 =}{\fs17 1 }\par
}
13 \cf0 h \par
}
13 \cf0 g \par
}
3 \cf0 f \par
}
13 \cf0 e \par
}
13 \cf0 d \par
}
13 \cf0 c \par
}
13 \cf0 b \par
}
13 \cf0 a \par
}
\cf0 Fig.{\fs16 3-34}{\b0 \fs17
Pulse-train}{\b0 \fs17 problem }\par
}
f0 3.47 \par
}
\cf0 Describe the pulse train at output{\fs17 Y}{\fs17 of} the OR gate
shown in Fig. 3-35.
i Ans. }\par
}
lse{\b\i \fs16 a}{\f10 \fs13 =} 0
{\fs16 b}{\f10 \fs14 =}{\fs17 1 }\par
}
lse{\fs16 c}{\f10 \fs13 =}{\fs17 1 }
{\fs17 d}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
lse{\fs17 e}{\f10 \fs13 =}{\fs17 1 }
{\b\i \f30 \fs19 f}{\b\i \f30 \fs19 =}{\fs17 1 }\par
}
lse{\fs15 g}{\f10 \fs13 =}{\fs17 1 }
{\fs17 h}{\f10 \fs13 =}{\fs16 0 }\par

}
s13 \cf0 h \par
}
s13 \cf0 g \par
}
13 \cf0 f \par
}
s13 \cf0 e \par
}
s13 \cf0 d \par
}
s13 \cf0 c \par
}
s13 \cf0 h \par
}
s13 \cf0 a \par
}
\par
}
\cf0 Fig.{\fs16 3-35}{\b0
Pulse-train}{\b0 problem }\par
}
cf0 3.48 \par
}
\cf0 Write the Boolean expression for the logic circuit shown{\fs17 in}
Fig. 3-36.
\i \f10 \fs16 Am.}{\b\i
A}{\b\i -}{\b\i B}{\b\i -}{\b\i C}{\b\i .}{\b\i
D}{\b\i +}{\b\i x}{\b\i ?}{\b\i =}{\b\i Y}
or{\b\i ABCD+&?=Y }\par
}
0 CHAP.{\b\i0 \fs17 31 }\par
}
SIC{\fs17 LOGIC} GATES \par
}
f0 47 \par
}
f0 3.49 \par
}
20 \fs17 \cf0 Fig. 3-36{\b0 \fs17
AND-OR}{\b0 logic-circuit}{\b0 problem }
cf0 \fi30 {\b0 Draw}{\b0 the}{\b0 truth}{\b0 table}{\b0 for}{\b0 the}{\b0
logic}{\b0 circuit}{\b0 shown}{\b0 in}{\b0 Fig.} 3-36.{\b0 Note}{\b0 that

}{\b0 the}{\b0 circuit}{\b0 has}{\b0 four}{\b0 input}{\b0 variables. }
\fi25 {\b0 The}{\b0 truth}{\b0 table}{\b0 will}{\b0 have}{\b0 16}{\b0
possible}{\b0 combinations. }
{\i \f10 \fs16 Am. }\par
}
puts \par
}
s17 \cf0 C
\fi29 {\b0\i0 0 }
\fi26 {\b0\i0 \fs17 0 }
\fi30 {\b0\i0 \fs17 0 }
\fi30 {\b0\i0 \fs17 0 }
\fi30 {\b0\i0 \fs17 1 }
\fi24 {\b0\i0 \fs17 1 }
\fi30 {\b0\i0 \fs17 1 }
\fi32 {\b0\i0 \fs17 1 }\par
}
s17 \cf0 B
\fi34 {\b0\i0 0 }
\fi31 {\b0\i0 \fs17 0 }
\fi35 {\b0\i0 \fs17 1 }
\fi31 {\b0\i0 \fs17 1 }
\fi35 {\b0\i0 \fs17 0 }
\fi23 {\b0\i0 \fs17 0 }
\fi35 {\b0\i0 \fs17 1 }
\fi33 {\b0\i0 \fs17 1 }\par
}
s17 \cf0 D
\fi33 {\b0\i0 1 }
\fi31 {\b0\i0 \fs17 1 }
\fi35 {\b0\i0 \fs17 1 }
\fi39 {\b0\i0 \fs17 1 }
\fi35 {\b0\i0 \fs17 1 }

\fi35 {\b0\i0 \fs17 1 }
\fi35 {\b0\i0 \fs17 1 }
\fi42 {\b0\i0 \fs17 1 }\par
}
s17 \cf0 A
\fi39 {\b0\i0 0 }
\fi35 {\b0\i0 \fs17 1 }
\fi39 {\b0\i0 \fs17 0 }
\fi32 {\b0\i0 \fs17 1 }
\fi39 {\b0\i0 \fs17 0 }
\fi22 {\b0\i0 \fs17 1 }
\fi39 {\b0\i0 \fs17 0 }
\fi34 {\b0\i0 \fs17 1 }\par
}
f0 3.50 \par
}
he part number 74C08{\fs17 is} a quad 2-input{\b AND} gate from the \par
}
\cf0 (CMOS,TTL){\b0 \fs17 family}{\fs17 of}{\b0 \fs17 ICs. }\par
}
s17 \cf0 Am.{\b0\i0 \fs17
The}{\b0\i0 \fs17 74C08}{\b0\i0 \fs17 is}{\b0\i0
\fs17 a}{\b0\i0 \fs17 part}{\b0\i0 \fs17 number}{\b0\i0 \fs17 from}{\b0\i0
\fs17 the}{\b0\i0 \fs17 CMOS}{\b0\i0 \fs17 family}{\b0\i0 of}{\i0 \fs17 K
s.}{\b0\i0 \fs17 The}{\b0\i0 \fs17 C}{\b0\i0 \fs17 in}{\b0\i0 \fs17 the}{\b0
\i0 \fs17 center}{\i0 of}{\b0\i0 \fs17 the}{\b0\i0 \fs17 part}{\b0\i0 \fs17
number }
\fi21 {\b0\i0 \fs17 means}{\b0\i0 \fs17 the}{\b0\i0 \fs17 part}{\b0\i0 \fs17
is}{\b0\i0 \fs17 a}{\b0\i0 \fs17 CMOS-type}{\b0\i0 \fs17 IC. }\par
}
apter{\fs51 4 }\par
}
0 \fs33 \cf0 Other{\fs33 Logic} Gates
f0 {\f20 \fs18 4-1}{\f20 \fs19
INTRODUCTION }
fi355 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 most}{\b0 \f20 \fs18 complex}{\b0 \f
20 \fs18 digital}{\b0 \f20 \fs18 systems,}{\b0 \f20 \fs18 such}{\b0 \f20 \fs1
8 as}{\b0 \f20 \fs18 large}{\b0 \f20 \fs18 computers,}{\b0 \f20 \fs18 are}{\
b0 \f20 \fs18 constructed}{\b0 \f20 \fs18 from}{\b0 \f20 \fs18 basic}{\b0 \f2
0 \fs18 logic}{\b0 \f20 \fs18 gates. }
\b0 \f20 \fs18 The}{\b0 \f20 \fs18 AND,}{\b0 \f20 \fs18 OR,}{\b0 \f20 \fs18 a
nd}{\b0 \f20 \fs18 NOT}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18 are}{\b0 \f20 \f
s18 the}{\b0 \f20 \fs18 most}{\b0 \f20 \fs18 fundamental.}{\b0 \f20 \fs18 Fo
ur}{\b0 \f20 \fs18 other}{\b0 \f20 \fs18 useful}{\b0 \f20 \fs18 logic}{\b0 \f
20 \fs18 gates}{\b0 \f20 \fs18 can}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 made }
\b0 \f20 \fs18 from}{\b0 \f20 \fs18 these}{\b0 \f20 \fs18 fundamental}{\b0 \
f20 \fs18 devices.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 other}{\b0 \f20 \fs
18 gates}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 called}{\b0 \f20 \fs18 the}
{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 gate,}{\b0 \f20 \fs18 the}{\b0 \f20 \
fs18 NOR}{\b0 \f20 \fs18 gate,}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 exclusive-OR}{\b0 \f20 \fs18 gate,}{\b0 \f20 \fs18 and}{\b0 \f2
0 \fs18 the}{\b0 \f20 \fs18 exclusive-NOR}{\b0 \f20 \fs18 gate.}{\b0 \f20 \
fs18 At}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 end}{\b0 \f20 \fs18 of}{\b0 \f2
0 \fs18 this}{\b0 \f20 \fs18 chapter,}{\b0 \f20 \fs18 you}{\b0 \f20 \fs18 w
ill}{\b0 \f20 \fs18 know}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 logic }
\b0 \f20 \fs18 symbol,}{\b0 \f20 \fs18 truth}{\b0 \f20 \fs18 table,}{\b0 \f20
\fs18 and}{\b0 \f20 \fs18 Boolean}{\b0 \f20 \fs18 expression}{\b0 \f20 \fs1
8 for}{\b0 \f20 \fs18 each}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0\i \
f20 \fs19 seven}{\b0\i \f20 \fs19 logic}{\b0\i \f20 \fs19 gates}{\b0 \f20 \f
s18 used}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 digital}{\b0 \f20 \fs18 system
s. }\par
}
\cf0 4-2 THE NAND GATE
fi374 {\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 logic}{\b0 \fs18 diagram}
{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 top}{\b0 \fs18 of}{\b0 \fs18 Fig.}{
\b0 4-1.}{\i \f10 \fs17 An}{\b0 \fs18 AND}{\b0 \fs18 gate}{\b0 \fs18 is}{\b
0 \fs18 connected}{\b0 \fs18 to}{\b0 \fs18 an}{\b0 \fs18 inverter.}{\b0 \fs1
8 Inputs }
\i \fs19 A}{\b0 \fs18 and}{\b0\i \fs19 B}{\b0 \fs18 are}{\b0 \fs18 ANDed}
{\b0 \fs18 to}{\b0 \fs18 form}{\b0 \fs18 the}{\b0 \fs18 Boolean}{\b0 \fs18
expression}{\i \fs18 A}{\b0 \f10 \fs22 .}{\b0\i \fs18 B.}{\b0 \fs18 The}{\i
\fs18 A}{\b0\i \fs19 .B}{\b0 \fs18 is}{\b0 \fs18 then}{\b0 \fs18 inverte
d}{\b0 \fs18 by}{\b0 \fs18 the}{\b0 \fs18 NOT }
\b0 \fs18 gate.}{\b0 \fs18 On}{\b0 \fs18 the}{\b0 \fs18 right}{\b0 \fs18 sid
e}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 inverter,}{\b0 \fs18 the}{\b0 \fs1
8 overbar}{\b0 \fs18 is}{\b0 \fs18 added}{\b0 \fs18 to}{\b0 \fs18 the}{\b0
\fs18 Boolean}{\b0 \fs18 expression.}{\b0 \fs18 The}{\b0 \fs18 Boolean }
\b0 \fs18 expression}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 entire}{\b0 \fs
18 circuit}{\b0 \fs18 is}{\i \fs19 A}{\b0\i \fs19 .B=}{\b0\i \fs19 Y.}{\b0
\fs18 It}{\b0 \fs18 is}{\b0 \fs18 said}{\b0 \fs18 that}{\b0 \fs18 this}{\b
0 \fs18 is}{\b0 \fs18 a}{\b0\i not-AND}{\b0 \fs18 or}{\b0 \fs18 NAND}{\b0
\fs18 circuit. }\par
}
\cf0 Fig. 4-1{\b0
The}{\fs17 NAND}{\b0 gate }\par
}
\cf0 The standard logic symbol for the NAND gate is shown in the bottom diagra
m in Fig. 4-1. Note

the NAND symbol is an AND symbol with a small bubble at the output. The bubble
is sometimes
\par}{\phpg\posx878\pvpg\posy9510\absw9119\absh1718 \sl-237 \f20 \fs18 \cf0 call
ed an{\i \fs19 invert}{\i \fs19 bubble.} The invert bubble provides a simplifi
ed method{\fs18 of} representing the NOT gate
n in the top diagram in Fig.{\fs19 4-1. }
58 The truth table describes the exact operation of a logic gate. The{\i \fs19
truth}{\i \fs19 table} for the NAND gate is
strated in the unshaded columns of Fig.{\fs19 4-2.} The AND-gate truth table
is also given to show how
\par}{\phpg\posx878\pvpg\posy9510\absw9119\absh1718 \sl-238 \f20 \fs18 \cf0 each
output is inverted to give the NAND output. Some students find{\fs18 it} usefu
l to think of the NAND
\par}{\phpg\posx878\pvpg\posy9510\absw9119\absh1718 \sl-239 \f20 \fs18 \cf0 gate
as an AND gate that puts out a{\fs19 0} when it is enabled (when both inputs
are{\fs19 1). }\par
}
\cf0 Fig.{\f10 \fs16 4-2}{\b0 \fs17
The}{\b0 \fs17 AND-}{\b0 \fs17 and}{\
b0 \fs17 NAND-gate}{\b0 \fs17 truth}{\b0 \fs17 tables }
\fi1660 {\b0 \fs19 48 }\par
}
0 CHAP.{\b0 \f10 \fs16 41 }\par
}
{\phpg\posx4255\pvpg\posy524\absw2022\absh201 \f20 \fs17 \cf0 \f20 \fs17 \cf0 OT
HER{\fs17 LOGIC}{\b \fs17 GATES }\par
}
f0 49 \par
}
\cf0 The NAND function has traditionally been the{\b\i \fs19 universal}{\b\i \
fs19 gate} in digital circuits. The NAND gate
9 is} widely used in most digital systems.
5 Consider the NAND gate truth table in{\fs19 Fig.}{\b\i 4-2.} The{\b\i
\fs19 unique}{\b\i \fs19 output} from the NAND gate is a
\par}{\phpg\posx841\pvpg\posy1334\absw9113\absh864 \sl-240 \f20 \fs19 \cf0 LOW w
hen all inputs are{\fs19 HIGH. }\par
}
OLVED PROBLEMS
\fi94 {\b \f20 \fs18 4.1}{\f20 \fs19
Write}{\f20 \fs19 the}{\f20 \fs19 Ho
olean}{\f20 \fs19 expression}{\f20 \fs19 for}{\f20 \fs19 a}{\f20 \fs19 3-inp
ut}{\f20 \fs19 NAND}{\f20 \fs19 gate. }
50 {\fs9 }{\fs23
-. - }
46 {\b\i \f20 \fs17 A}{\fs23 -}{\b\i \f20 \fs17 B}{\fs23 -}{\b\i \f20 \fs17
C}{\b\i \f20 \fs17 =}{\b\i \f20 \fs17 Y}{\f20 \fs17 or}{\b\i \f20 \fs17 AB
C=}{\b\i \f20 \fs17 Y }\par
}
f0 4.2 \par
}
raw the logic symbol for a 3-input NAND gate.
\fs17 Solution: }
66 {\b \fs17 See}{\fs17 Fig.}{\b \fs17 4-3. }\par
}
\f20 \fs15 \cf0 z j - - > Y
\fi517 {\f30 \fs16 C }
\cf0 {\i0 \fs17 Fig.}{\i0 \fs16 4-3}{\i0 \fs17
A}{\b0\i0 \fs17 3-input}{\b0
\i0 \fs17 NAND}{\b0\i0 \fs17 gate }\par
}
cf0 4.3{\b0 \fs19
Draw}{\b0 \fs19 the}{\b0 \fs19 truth}{\b0 \fs19 table}{
\b0 \fs19 for}{\b0 \fs19 a}{\b0 \fs19 3-input}{\b0 \fs19 NAND}{\b0 \fs19 ga
te. }
}
s17 \cf0 C
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }\par
}
nputs
\fi183 {\b\i \fs17 B }
95 0
97 {\fs17 0 }
95 {\fs17 1 }
97 {\fs17 1 }\par
}
s17 \cf0 A
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }\par
}
{\phpg\posx4845\pvpg\posy8745\absw590\absh1508 \f20 \fs17 \cf0 \f20 \fs17 \cf0 O
utput
21 {\b\i \fs18 Y }
46 {\fs17 1 }
43 {\fs17 1 }
43 {\fs17 1 }
43 {\fs17 1 }\par
}
7 1 }
7 1 }\par
}
7 1 }
7 1 }\par
}
cf0 4.4 \par
}
What would the output pulse train shown in{\fs19 Fig.}{\b \fs18 4-4} look lik
e{\fs19 if} input{\b\i \fs19 B} were{\fs19 O? }\par
}
20 \fs17 \cf0 Fig.{\fs16 4-4}{\b0 \fs17
Pulse-train}{\b0 \fs17 problem }
cf0 Solution:
\fi355 {\b0 \fs17 The}{\b0 \fs17 output}{\fs17 of}{\b0 \fs17 the}{\b0 \fs17
NAND}{\b0 \fs17 gate}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.} 44{\b0 \fs17 would}{\b0 \fs17 always}{\b0 \fs16 be}{\b0 \fs16 1. }\par
}
par
}
HER LOGIC GATES \par
}
AP.{\b \f30 \fs18 4 }\par
}
f0 4.5 \par
}
hat would the output pulse train shown in Fig. 4-4 look like if input{\i \fs19
B} were{\fs18 l? }
\fs17 Solution: }
61 {\fs17 The}{\fs17 output}{\fs17 would}{\fs17 be}{\fs17 an}{\fs17 in
verted}{\fs17 copy}{\fs16 of}{\fs17 the}{\fs17 waveform}{\fs17 at}{\fs
17 input}{\b\i \f10 \fs15
A}{\fs17 (Fig.}{\b \f30 \fs18 4-4).}{\fs17 The
}{\fs17 output}{\fs17 pulses }
17 would}{\fs17 be}{\fs17 as}{\fs17 follows: }\par
}
lse{\b\i \fs16 a}{\dn006 \f10 \fs11 =} 0
{\i \fs16 b}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
lse{\i \f10 \fs15 c}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\i \f10 \fs16 d}{\f10 \fs13 =} 0 \par
}
lse e{\dn006 \f10 \fs11 =}{\b \fs16 1 }
{\i \f30 \fs19 f=} 0 \par
}
lse{\fs15 g}{\dn006 \f10 \fs11 =} 0
{\i h}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
cf0 4.6{\b0 \fs18
Draw}{\b0 \fs18 a}{\b0 \fs18 logic}{\b0 \fs18 diagra
m}{\b0 \fs18 of}{\b0 \fs18 how}{\b0 \fs18 you}{\b0 \fs18 could}{\b0 \fs1
8 connect}{\b0 \fs18 a}{\b0 \fs18 2-input}{\b0 \fs18 NAND}{\b0 \fs18 g
ate}{\b0 \fs18 to}{\b0 \fs18 perform}{\b0 \fs18 as}{\b0 \fs18 an }
i499 {\b0 \fs18 inverter.}{\b0 \fs18 Label}{\b0 \fs18 inverter}{\b0 \fs18 in
put}{\b0 \fs18 as}{\i \fs19 A.}{\b0 \fs18 Label}{\b0 \fs18 inverter}{\b0 \f
s18 output}{\b0 \fs18 as}{\b0\i \f30 \fs27 2. }
i867 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 4-5.}{\b0 \fs17 There}{\b0 \
fs17 are}{\b0 \fs17 two}{\b0 \fs17 possibilities. }\par
}
\cf0 Fig. 4-5{\b0
Wiring}{\b0 the}{\b0 \fs17 NAND}{\b0 gate}{\b0 as}{\b0
an}{\b0 inverter }\par
}
\cf0 4-3{\fs19
THE}{\f30 \fs20 NOR} GATE
fi364 {\b0 Consider}{\b0 the}{\b0 logic}{\b0 diagram}{\b0 in}{\b0 Fig.}{\
b0 4-6.}{\b0 An}{\b0 inverter}{\b0 has}{\b0 been}{\b0 connected}{\b0
to}{\b0 the}{\b0 output}{\b0 of}{\b0 an}{\b0 OR }
\b0 gate.}{\b0 The}{\b0 Boolean}{\b0 expression}{\b0 at}{\b0 the}{\b0
input}{\b0 to}{\b0 the}{\b0 inverter}{\b0 is}{\i \fs19 A}{\b0\i \fs19
+B.}{\b0 The}{\b0 inverter}{\b0 then}{\b0 complements }

\b0 the}{\b0 ORed}{\b0 terms,}{\b0 \fs18 which}{\b0 are}{\b0 shown}{\b
0 in}{\b0 the}{\b0 Boolean}{\b0 expression}{\b0 with}{\b0 an}{\b0
overbar.}{\b0 Adding}{\b0 the}{\b0 overbar }
\b0 produces}{\b0 the}{\b0 Boolean}{\b0 expression}{\i A}{\b0 \f10 \fs30 +
}{\b0\i\dn006 \fs19 B}{\b0\dn006 \f10 \fs13 =}{\i \fs19 Y.}{\b0 This}{\b0 is
}{\b0 a}{\b0\i not-OR}{\b0 function.}{\b0 The}{\b0 not-OR}{\b0 function}
{\b0 can}{\b0 be }
\b0 drawn}{\b0 as}{\b0 a}{\b0 single}{\b0 logic}{\b0 symbol}{\b0 called}{\
b0 a}{\b0\i \fs19 NOR}{\b0\i gate.}{\b0 The}{\b0 standard}{\b0 symbol}{\b0
for}{\b0 the}{\b0 \fs19 NOR}{\b0 gate}{\b0 is}{\b0 illustrated }
\b0 in}{\b0 the}{\b0 bottom}{\b0 diagram}{\b0 of}{\b0 Fig.}{\b0 4-6.}{\b0
Note}{\b0 that}{\b0 a}{\b0 small}{\b0 invert}{\b0 bubble}{\b0 has}{\b0
been}{\b0 added}{\b0 to}{\b0 the}{\b0 OR}{\b0 symbol }
\b0 to}{\b0 form}{\b0 the}{\b0 NOR}{\b0 symbol. }\par
}
0 \fs17 \cf0 Fig.{\fs16 4-6}{\b0
The}{\b0 NOR}{\b0 gate }
f0 \fi358 {\b0 \fs18 The}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 in}{\b0
\fs18 Fig.}{\b0 \fs18 4-7}{\b0 \fs18 details}{\b0 \fs18 the}{\b0 \fs18 ope
ration}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 NOR}{\b0 \fs18 gate.}{\b0 \fs
18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 column}
{\b0 \fs18 of }
\b0 \fs18 the}{\b0 \fs18 NOR}{\b0 \fs18 gate}{\b0 \fs18 is}{\b0 \fs18 the}{\
b0 \fs18 complement}{\b0 \fs18 (has}{\b0 \fs18 been}{\b0 \fs18 inverted)}{
\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 shaded}{\b0 \fs19 OR}{\b0 \fs18 colu
mn.}{\b0 \fs18 In}{\b0 \fs18 other}{\b0 \fs18 words,}{\b0 \fs18 the }\par
}
\cf0 Fig.{\fs16 4-7}{\b0
The}{\b0 OR-}{\b0 and}{\b0 NOR-gate}{\b0 truth
}{\b0 tables }\par
}
0 CHAP.{\b0 \f10 \fs16 41 }\par
}
}
\par
}
{\phpg\posx843\pvpg\posy1350\absw9104\absh851 \f20 \fs18 \cf0 \f20 \fs18 \cf0 NO
R gate puts out a{\fs18 0} where the{\fs19 OR} gate would produce a 1. The sm
all invert bubble at the output
9 of} the NOR symbol serves as a reminder of the{\fs18 0} output idea.
0 Consider the NOR gate truth table in Fig.{\b \fs19 4-7.} The{\b\i \fs18 uniq
ue}{\b\i \fs18 output} from the NOR gate is a{\b \fs19 HIGH }
\par}{\phpg\posx843\pvpg\posy1350\absw9104\absh851 \sl-231 \f20 \fs18 \cf0 when
all inputs are LOW. \par
}
cf0 SOLVED PROBLEMS \par
}
f0 4.7 \par
}
rite the Boolean expression for a 3-input{\fs18 NOR} gate.
47 {\b\i \fs17 A}{\b\i \fs17 +}{\b\i \fs17 B}{\b\i \fs17 +}{\b\i \fs17 C}{\b
\i \fs17 =}{\b\i \fs17 Y }\par
}
f0 4.8 \par
}
raw the logic symbol for a 3-input NOR gate.
}
\cf0 Fig.{\fs17 4-8}{\fs17
A}{\b0 \fs17 3-input}{\b0 \fs17 NOR}{\b0 \fs17
gate }\par
}
f0 4.9 \par
}
hat is the truth table for a 3-input{\fs19 NOR} gate?
}
puts \par
}
7 0 }
7 0 }
r
}
7 0 }
7 1 }
r
}
7 1 }
7 0 }
r
}
1{\f20 \fs17
Output}{\b \fs31 I }
\par}{\phpg\posx4733\pvpg\posy9009\absw1141\absh1652 \sl-230 \par\par\f10 \fs30
\cf0 \fi403 {\f20 \fs16 1 }
390 {\f20 \fs17 0 }
386 {\f20 \fs17 0 }
386 {\f20 \fs17 0 }\par
}
puts \par
}
7 1 }
6 1 }\par
}
7 0 }
6 1 }\par
}
7 1 }
6 1 }\par
}
{\f20 \fs17 Output }
cf0 \fi387 {\f20 \fs17 0 }
90 {\f20 \fs17 0 }
90 {\f20 \fs17 0 }
90 {\f20 \fs17 0 }\par
}
cf0 4.10 \par
}
What would the output pulse train{\b \fs19 shown} in Fig.{\b \fs18 4-9} look l
ike if input{\b\i \fs19 B} were{\fs18 l? }\par
}
s15 \cf0 h \par
}

s15 \cf0 g \par
}
s15 \cf0 f \par
}
s15 \cf0 e \par
}
s15 \cf0 d \par
}
s15 \cf0 c \par
}
s15 \cf0 b \par
}
s15 \cf0 a \par
}
{\phpg\posx6331\pvpg\posy12372\absw680\absh303 \f10 \fs25 \cf0 \f10 \fs25 \cf0 $lJ- \par
}
20 \fs16 \cf0 Fig. 4-9{\b0 \fs17
Pulse-train}{\b0 \fs17 problem }
cf0 Solution:
\fi354 {\b0 \fs17 The}{\b0 \fs17 output}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \f
s17 NOR}{\b0 \fs17 gate}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 4-9}{\
b0 \fs17 would}{\b0 \fs17 always}{\b0 \fs17 be}{\b0 \fs17 0. }\par
}
0 52 \par
}
cf0 OTHER LOGIC GATES \par
}
}
f0 4.11 \par
}
hat would the output pulse train shown in Fig.{\b 4-9} look like if input{\i
B} were{\fs18 O? }
\fs17 Solution: }
60 {\b \fs17 The}{\b \fs17 output}{\b \fs17 pulse}{\b \fs17 would}{\b \fs17
be}{\b \fs17 the}{\b \fs17 one}{\b \fs17 shown}{\b \fs17 in}{\b \fs17 Fi
g.}{\b \fs17 4-9}{\b \fs17 but}{\b \fs17 inverted.}{\b \fs17 The}{\b \fs17
pulses}{\b \fs17 would}{\b \fs17 be}{\fs17 as}{\b \fs17 follows: }\par
}
cf0 pulse{\i \f10 \fs15 a}{\b0 \f10 \fs13 =}{\b0 0 }
\par}{\phpg\posx1445\pvpg\posy2188\absw924\absh401 \sl-221 \b \f20 \fs17 \cf0 pu

lse{\i \fs17 b}{\b0 \f10 \fs13 =}{\b0 \fs17 1 }\par
}
cf0 pulse{\i \fs17 c}{\b0 \f10 \fs13 =}{\fs16 1 }
lse{\i \fs17 d}{\b0 \f10 \fs13 =}{\b0 \fs17 0 }\par
}
cf0 pulse{\i \fs17 e}{\b0 \f10 \fs13 =}{\b0 0 }
lse{\i \f30 \fs18 f}{\i \f30 \fs18 =}{\b0 0 }\par
}
cf0 pulse{\i \fs16 g}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 1 }
lse{\b0\i \fs17 h}{\b0 \f10 \fs13 =}{\b0 0 }\par
}
\cf0 4-4{\f20 \fs19
THE}{\f20 \fs19 EXCLUSIVE-OR}{\f20 \fs18 GATE }
fi358 {\b0 \f20 \fs19 The}{\i \f20 \fs19 exclusive-OR}{\i \f20 \fs19 gate}{\b0
\f20 \fs19 is}{\b0 \f20 \fs19 referred}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19
as}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 "any}{\b0 \f20 \fs19 but}{\b0 \f20 \f
s19 not}{\b0 \f20 \fs19 all"}{\b0 \f20 \fs19 gate.}{\b0 \f20 \fs19 The}{\b0
\f20 \fs19 exclusive-OR}{\b0 \f20 \fs19 term}{\b0 \f20 \fs19 is}{\b0 \f20 \fs
19 often }
\b0 \f20 \fs19 shortened}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 read}{\b0 \f20 \
fs19 as}{\i \f20 \fs19 XOR.}{\i \f20 \fs19 A}{\b0 \f20 \fs19 truth}{\b0
\f20 \fs19 table}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 the}{\f20 \fs19 XOR
}{\b0 \f20 \fs19 function}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 shown}{\b0 \f
20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\f20 \fs19 4-10.}{\b0 \f20 \fs19 Caref
ul }
\b0 \f20 \fs19 examination}{\b0 \f20 \fs19 shows}{\b0 \f20 \fs19 that}{\b0 \f2
0 \fs19 this}{\b0 \f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 is}
{\b0 \f20 \fs19 similar}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 the}{\b0 \f20 \fs1
9 OR}{\b0 \f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 except}{\b0
\f20 \fs19 that,}{\b0 \f20 \fs19 when}{\b0 \f20 \fs19 both}{\b0 \f20 \fs19
inputs }
\b0 \f20 \fs19 are}{\f20 \fs18 1,}{\b0 \f20 \fs19 the}{\f20 \fs19 XOR}{\b0 \f
20 \fs19 gate}{\b0 \f20 \fs19 generates}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 0.
}{\b0 \f20 \fs19 The}{\f20 \fs19 XOR}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 is
}{\b0 \f20 \fs19 enabled}{\i \f20 \fs19 only}{\i \f20 \fs19 when}{\i \f20 \f
s19 an}{\i \f20 \fs19 odd}{\i \f20 \fs19 number}{\b0 \f20 \fs18 of}{\b0\i \f
s16 1s}{\i \f20 \fs19 appear}{\i \f20 \fs19 at }
\i \f20 \fs19 the}{\i \f20 \fs19 inputs.}{\b0 \f20 \fs19 Lines}{\b0 \f20 \fs
19 2}{\b0 \f20 \fs19 and}{\f20 \fs18 3}{\b0 \f20 \fs19 of}{\b0 \f20 \fs1
9 the}{\b0 \f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 have}{
\b0 \f20 \fs19 odd}{\b0 \f20 \fs19 numbers}{\b0 \f20 \fs19 of}{\f20 \fs19
Is,}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 therefore}{\b0 \f20 \fs19 the}{\
b0 \f20 \fs19 output}{\b0 \f20 \fs19 is }
\b0 \f20 \fs19 enabled}{\b0 \f20 \fs19 with}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
1.}{\b0 \f20 \fs19 Lines}{\f20 \fs19 1}{\b0 \f20 \fs19 and}{\f20 \fs19 4}{\
b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 truth}{\b0 \f20 \fs19 t
able}{\b0 \f20 \fs19 contain}{\b0 \f20 \fs19 even}{\b0 \f20 \fs19 numbers}{\b
0 \f20 \fs19 (0,2)}{\b0 \f20 \fs18 of}{\f20 \fs19 Is,}{\b0 \f20 \fs19 and}{
\b0 \f20 \fs19 therefore}{\b0 \f20 \fs19 the }
\f20 \fs19 XOR}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 dis
abled}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 a}{\b0 \f20 \fs18 0}{\b0 \f20 \f
s19 appears}{\b0 \f20 \fs19 at}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 outpu
t.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 XOR}{\b0 \f20 \fs19 gate}{\b0 \f20
\fs19 could}{\b0 \f20 \fs19 be}{\b0 \f20 \fs19 referred}{\b0 \f20 \fs19
to}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 an }
\b0 \f20 \fs19 odd-bits}{\b0 \f20 \fs19 check}{\b0 \f20 \fs19 circuit. }\par
}
0 +- \par
}
\cf0 Inputs{\fs17
Output }\par
}
cf0 0
f10 \fs16 0 }
i20 {\f10 \fs16 1 }
f10 \fs15 1 }\par
}
cf0 0
f10 \fs16 1 }
f10 \fs16 0 }
f10 \fs15 1 }\par
}
cf0 0
i22 {\f10 \fs15 1 }
i26 {\f10 \fs15 1 }
fs18 0 }\par
}
\cf0 Fig.{\fs17 4-10}{\fs17
The}{\fs17 exclusive-OR-gatetruth}{\fs17 table
}\par
}
\fs18 \cf0 A{\b0 \fs19 Boolean}{\b0 \fs19 expression}{\b0 \fs19 for}{\b0 \fs
19 the}{\b0 \fs19 XOR}{\b0 \fs19 gate}{\b0 \fs19 can}{\b0 \fs19 be}{\b0 \fs
19 developed}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19 truth}{\b0 \fs19 tab
le}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\fs19 4-10.}{\b0 \fs19 The }
b0 \fs19 expression}{\b0 \fs19 is}{\i \fs19 A}{\b0 \f10 \fs27 -}{\i \f30 \fs2
7 B}{\b0 \f10 \fs29 +}{\b0\i \f30 \fs26 2-}{\b0 \f10 \fs15 =}{\b0\i \fs20 Y.}
{\b0 \fs19 With}{\b0 \fs19 this}{\b0 \fs19 Boolean}{\b0 \fs19 expression,}{\b
0 \fs19 a}{\b0 \fs19 logic}{\b0 \fs19 circuit}{\b0 \fs19 can}{\b0 \fs19 be}
{\b0 \fs19 developed}{\b0 \fs19 by}{\b0 \fs19 using }

b0 \fs19 AND}{\b0 \fs19 gates,}{\b0 \fs19 OR}{\b0 \fs19 gates,}{\b0 \fs19 an
d}{\b0 \fs19 inverters.}{\b0 \fs19 Such}{\b0 \fs19 a}{\b0 \fs19 logic}{\b0 \
fs19 circuit}{\b0 \fs19 is}{\b0 \fs19 drawn}{\b0 \fs19 in}{\b0 \fs19 Fig.}{
\fs19 4-11a.}{\b0 \fs19 This}{\b0 \fs19 logic}{\b0 \fs19 circuit}{\b0 \fs19
will }
b0 \fs19 perform}{\b0 \fs19 the}{\fs19 XOR}{\b0 \fs19 logic}{\b0 \fs19 funct
ion. }\par
}
19 \cf0 B \par
}
fs13 \cf0 (a){\i0 \f20 \fs15 Logic}{\i0 \f20 \fs15 circuit}{\i0 \f20 \fs15 th
at}{\i0 \f20 \fs15 performs}{\i0 \f20 \fs15 the}{\i0 \f20 \fs15 XOR}{\i0 \f2
0 \fs15 function }\par
}
fs15 \cf0 (b){\i0 Standard}{\i0 \fs15 logic}{\i0 \fs15 symbol}{\i0 \fs15 fo
r}{\i0 the}{\i0 \fs16 XOR}{\i0 gate }\par
}
\cf0 Fig.{\fs17 4-11 }\par
}
\cf0 The standard logic symbol for the{\b XOR} gate is shown in Fig.{\b 4-11b
.} Both logic symbol diagrams in
{\b 4-11} would produce the same truth table{\b (XOR).} The Boolean
expression at the right in Fig.
4-11b} is a{\b\i \fs19 simplped}{\b\i XOR}{\b\i \fs19 expression.} The{\f10
\fs15 @} symbol signifies the XOR function in Boolean algebra. It
\par}{\phpg\posx849\pvpg\posy12727\absw9210\absh858 \sl-241 \f20 \fs19 \cf0 is s
aid that inputs{\b\i A} and{\i B} in Fig.{\b 4-llb} are exclusively ORed
together. \par
}
.{\fs17 41 }\par
}
HER{\fs17 LOGIC}{\b \f10 \fs16 GATES }\par
}
f0 53 \par
}
cf0 SOLVED{\fs17 PROBLEMS }\par
}
f0 4.12 \par
}
f0 4.13 \par
}
Write the Boolean expression (simplified form) for a 3-input XOR gate.

\fs17 Solution: }
345 {\b\i \fs17 A}{\b\i \fs17 @}{\b\i \fs17 B}{\b\i \fs17 @}{\b\i \fs17 C}{\
b\i \fs17 =}{\b\i \fs17 Y }
Draw the logic symbol for a 3-input{\fs19 XOR} gate.
\fs17 Solution: }
}
\cf0 Fig.{\f10 \fs16 4-12}{\fs17
A}{\b0 \fs17 3-input}{\b0 \fs17 XOR}{\b0
\fs17 gate }\par
}
f0 4.14 \par
}
hat is the truth table for a 3-input XOR gate? Remember that an odd
number{\fs19 of}{\fs19 1s }
\par}{\phpg\posx1417\pvpg\posy5805\absw8372\absh730 \sl-237 \f20 \fs19 \cf0 gene
rates a 1 output.
}
puts \par
}
{\phpg\posx4831\pvpg\posy7101\absw590\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Ou
tput \par
}
puts \par
}
tput \par
}
{\phpg\posx3627\pvpg\posy7905\absw93\absh70 \f10 \fs5 \cf0 \f10 \fs5 \cf0 ~, \pa
r
}
f0 4.15 \par
}
he{\fs19 XOR} gate might be considered an
}
even-,odd-) number-of-1s detector. \par
}
cf0 4.16 \par
}
\cf0 The{\fs17 XOR} gate generates a{\fs17 1}when an{\fs17 odd} numbe
r of{\fs17 1} bits are present. For this reason it might be
\par}{\phpg\posx1417\pvpg\posy9946\absw8266\absh938 \sl-215 \f20 \fs17 \cf0 cons
idered as an odd-number-of-1s detector.

{\fs19 What}{\fs19 will}{\fs19 the}{\fs19 pulse}{\fs19 train}{\fs19 at}{\fs
19 the}{\fs19 output}{\fs19 of}{\fs19 the}{\fs19 XOR}{\fs19 gate}{\fs19 s
hown}{\fs19 in}{\fs19 Fig.}{\fs19 4-13}{\fs19 look}{\fs19 like? }\par
}
s16 \cf0 g \par
}
s16 \cf0 f \par
}
s16 \cf0 e \par
}
s16 \cf0 d \par
}
s16 \cf0 c \par
}
s16 \cf0 b \par
}
s16 \cf0 a \par
}
20 \fs17 \cf0 Fig.{\f10 \fs16 4-13}{\b0 \fs17
Pulse-train}{\b0 \fs17 probl
em }
cf0 Solution:
\fi351 {\b0 \fs17 The}{\b0 \fs17 output}{\b0 \fs17 pulses}{\b0 \fs17 from}{
\b0 \fs17 the}{\b0 \fs17 XOR}{\b0 \fs17 gate}{\b0 \fs17 shown}{\b0 \fs17
in}{\b0 \fs17 Fig.}{\b0 \fs17 4-13}{\b0 \fs17 will}{\b0 \fs17 be}{\b0 \f
s17 as}{\b0 \fs17 follows: }\par
}
ulse{\b a}{\f10 \fs13 =}{\fs17 0 }
\par}{\phpg\posx1395\pvpg\posy13294\absw921\absh393 \sl-217 \f20 \fs17 \cf0 puls
e{\fs16 b}{\f10 \fs14 =}{\fs16 1 }\par
}
ulse{\b\i \fs16 c}{\f10 \fs13 =}{\fs17 1 }
e{\b\i \f10 \fs16 d}{\f10 \fs13 =} 0 \par
}
ulse e{\f10 \fs14 =}{\fs17 0 }
e{\b\i \f30 \fs19 f}{\b\i \f30 \fs19 =}{\fs17 1 }\par
}
ulse{\fs15 g}{\f10 \fs13 =}{\fs17 1 }\par
}
par
}
}
AP.{\b \f30 \fs18 4 }\par
}
\cf0 4-5{\fs18
THE}{\fs18 EXCLUSIVE-NOR}{\fs18 GATE }
fi360 {\b0 \fs18 The}{\b0 \fs18 output}{\b0 \fs18 of}{\b0 \fs18 an}{\b0 \fs18
XOR}{\b0 \fs18 gate}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 inverted}{\b
0 \fs18 in}{\b0 \fs18 Fig.}{\fs18 4-14.}{\b0 \fs18 The}{\b0 \fs18 output}{\
b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 inverter}{\b0 \fs18 on}{\b0 \fs18 the
}{\b0 \fs18 right }
\b0 \fs18 side}{\b0 \fs18 is}{\b0 \fs18 called}{\b0 \fs18 the}{\b0\i \fs19
exclusive-NOR}{\b0 \fs18 (XNOR)}{\b0 \fs18 function.}{\b0 \fs18 The}{\b0
\fs18 XOR}{\b0 \fs18 gate}{\b0 \fs18 produces}{\b0 \fs18 the}{\b0 \fs18
expression}{\i \fs19 A}{\b0\i \fs19 @B. }
\b0 \fs18 When}{\b0 \fs18 this}{\b0 \fs18 is}{\b0 \fs18 inverted,}{\b0 \fs18
it}{\b0 \fs18 forms}{\b0 \fs18 the}{\b0 \fs18 Boolean}{\b0 \fs18 expressi
on}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 XNOR}{\b0 \fs18 gate,}{\i \fs19
A}{\b0 \f10 \fs15 @}{\b0\i \fs19 B}{\b0\dn006 \f10 \fs13 =}{\b0\i \fs19 Y.
}{\b0 \fs18 The}{\b0 \fs18 standard }
\b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 X
NOR}{\b0 \fs18 gate}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18
the}{\b0 \fs18 bottom}{\b0 \fs18 diagram}{\b0 of}{\b0 \fs18 Fig.}{\b0 \fs18
4-14.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 symbol}{\b
0 \fs18 is }
\b0 \fs18 an}{\b0 \fs18 XOR}{\b0 \fs18 symbol}{\b0 \fs18 with}{\b0 \fs18 an
}{\b0 \fs18 invert}{\b0 \fs18 bubble}{\b0 \fs18 attached}{\b0 \fs18 to}{\b
0 \fs18 the}{\b0 \fs18 output. }\par
}
0 \fs16 \cf0 Fig.{\f10 \fs15 4-14}{\b0 \fs17
The}{\b0 \fs17 XNOR}{\b0 \fs17
gate }
f0 \fi353 {\b0 \fs18 The}{\b0 \fs18 right-hand}{\b0 \fs18 column}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 in}{\b0 \
fs18 Fig.}{\b0 \fs18 4-15}{\b0 \fs18 details}{\b0 \fs18 the}{\b0 \fs18 op
eration}{\fs19 of}{\b0 \fs18 the}{\b0 \fs18 XNOR}{\b0 \fs18 gate. }
\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 all}{\b0 \fs18 outputs}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 XNOR}{\b0 \fs18 gate}{\b0 \fs18 are}{\b0 \f
s18 the}{\b0 \fs18 complements}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 XO
R-gate}{\b0 \fs18 outputs.}{\b0 \fs18 While}{\b0 \fs18 the }
\b0 \fs18 XOR}{\b0 \fs18 gate}{\b0 \fs18 is}{\b0 \fs18 an}{\b0 \fs18 odd-num
ber-of-1s}{\b0 \fs18 detector,}{\b0 \fs18 the}{\b0 \fs18 XNOR}{\b0 \fs18 gat
e}{\b0 \fs18 detects}{\b0\i \fs19 even}{\b0\i \fs19 numbers}{\b0 \fs19 of}{
\b0\i \fs19 Is.}{\b0 \fs18 The}{\b0 \fs18 XNOR }
\b0 \fs18 gate}{\b0 \fs18 will}{\b0 \fs18 produce}{\b0 \fs19 a}{\b0 \fs18
1}{\b0 \fs18 output}{\b0 \fs18 when}{\b0 \fs18 an}{\b0\i \fs19 even}{\b0\i
\fs19 number}{\b0 \fs18 of}{\b0\i \fs19 Is}{\b0 \fs18 appear}{\b0 \fs18
at}{\b0 \fs18 the}{\b0 \fs18 inputs. }\par
}
\cf0 Fig.{\f10 \fs15 4-15}{\b0 \fs17
The}{\b0 \fs17 XOR-}{\b0 \fs17 and}{\
b0 \fs17 XNOR-gate}{\b0 \fs17 truth}{\b0 \fs17 tables }\par
}
SOLVED{\fs16 PROBLEMS }
{\b \f20 \fs18 4.17}{\f20 \fs18
Write}{\f20 \fs18 the}{\f20 \fs18 Boolean
}{\f20 \fs18 expression}{\f20 \fs18 for}{\f20 \fs18 a}{\f20 \fs18 3-input}
{\f20 \fs18 XNOR}{\f20 \fs18 gate. }
\fi611 {\b \f20 Solution: }
958 {\b\i \f20 \fs16 A}{\b\i \f20 \fs16 @}{\b\i \f20 \fs16 B}{\b\i \f20 \fs16
@}{\b\i \f20 \fs16 C}{\b\i \f20 \fs16 =}{\b\i \f20 \fs16 Y }\par
}
cf0 4.18 \par
}
Draw the logic symbol for a 3-input XNOR gate.
}
\cf0 Fig.{\f10 \fs15 4-16} A{\b0 \fs17 3-input}{\b0 \fs17 XNOR}{\b0 \fs17
gate }\par
}
.{\b \fs16 41 }\par
}
}
8 \cf0 55 \par
}
cf0 4.19{\b0
Construct}{\b0 a}{\b0 truth}{\b0 table}{\b0 for}{\b0
a}{\b0 3-input}{\b0 XNOR}{\b0 gate.}{\b0 Remember}{\b0 that}{\b0 an}
{\b0 even}{\b0 number}{\b0 of}{\b0 \fs18 1s }
i598 {\b0 generates}{\b0 \fs19 a}{\b0 1}{\b0 output. }
}
s18 \cf0 C
\fi22 {\b0\i0 \f20 \fs17 0 }
\fi22 {\b0\i0 \f20 \fs17 0 }
\fi22 {\b0\i0 \f20 \fs17 0 }
\fi22 {\b0\i0 \f20 \fs17 0 }\par

}
nputs
\fi178 {\b\i \fs17 B }
93 0
93 {\fs16 0 }
13 {\b \f10 \fs15 1 }
10 {\fs16 1 }\par
}
s16 \cf0 A
\cf0 \fi30 {\b0\i0 \f20 \fs16 0 }
\fi50 {\i0 \fs15 1 }
\fi28 {\b0\i0 \f20 \fs16 0 }
\fi38 {\b0\i0 \f20 \fs16 1 }\par
}
utput
\fi230 {\b\i \fs17 Y }
\fi260 {\b \f10 \fs15 1 }
37 0
37 0
50 {\fs16 1 }\par
}
\fi36 {\fs16 1 }
3 {\fs16 1 }
8 1
3 {\fs16 1 }\par
}
nputs
\fi173 {\b\i \fs17 B }
93 0
93 0
07 {\fs17 1 }
\fs17 \cf0 \f20 \fs17 \cf0 I

\sl-176 \par\f20 \fs17 \cf0
\sl-336 \f20 \fs17 \cf0 \fi1
\sl-260 \f20 \fs17 \cf0 \fi1
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-253 \f20 \fs17 \cf0 \fi2
\f10 \fs16 \cf0 \b\i \f10 \f
\sl-168 \par\b\i \f10 \fs16
\sl-260 \b\i \f10 \fs16 \cf0
\sl-260 \b\i \f10 \fs16 \cf0
\sl-253 \b\i \f10 \fs16 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 o
\sl-176 \par\f20 \fs17 \cf0
\sl-168 \par\f20 \fs17 \cf0
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-253 \f20 \fs17 \cf0 \fi2
\fs17 \cf0 \f20 \fs17 \cf0 C
\sl-170 \par\f20 \fs17 \cf0
\sl-256 \f20 \fs17 \cf0 \fi3
\sl-260 \f20 \fs17 \cf0 \fi2
\sl-255 \f20 \fs17 \cf0 \fi3
\fs17 \cf0 \f20 \fs17 \cf0 I
\sl-176 \par\f20 \fs17 \cf0
\sl-340 \f20 \fs17 \cf0 \fi1
\sl-256 \f20 \fs17 \cf0 \fi1
\sl-260 \f20 \fs17 \cf0 \fi2

03 {\fs16 1 }\par
}
tput \par
}
}
\cf0 Y
\i0 0 }
\par}{\phpg\posx8033\pvpg\posy3141\absw132\absh1191 \sl-256 \i \f20 \fs17 \cf0 \
fi22 {\i0 \fs16 1 }
\i0 \fs16 1 }
\i0 0 }\par
}
s15 \cf0 A
\cf0 \fi27 {\b0\i0 \f20 \fs16 0 }
\fi41 {\b0\i0 \f20 \fs17 1 }
\fi27 {\b0\i0 \f20 \fs17 0 }
\fi40 {\b0\i0 \f20 \fs17 1 }\par
}
f0 4.20 \par
}
hat will the pulse train at the output{\fs18 of} the XNOR gate shown in Fig.
4-17 look like? \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
0 \fs17 \cf0 Fig. 4-17{\b0

Pulse-train}{\b0 problem }
f0 Solution:
fi354 {\b0 The}{\b0 output}{\b0 pulses}{\b0 \fs17 from}{\b0 the}{\fs17
XNOR}{\b0 gate}{\b0 shown}{\b0 \fs17 in}{\b0 Fig.}{\fs16 4-1'7}{\b0 \fs
16 will}{\b0 be}{\b0 as}{\b0 follows: }\par
}
lse{\b\i \fs16 a}{\f10 \fs13 =} 0
{\i \fs16 b}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
lse{\i \f10 \fs14 c}{\f10 \fs13 =} 0
{\b\i \f10 \fs16 d}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
lse{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 0
{\i \f30 \fs19 f=}{\fs16 1 }\par
}
lse{\i \f10 \fs14 g}{\dn006 \f10 \fs11 =} 0 \par
}
\cf0 4-6{\f20 \fs18
CONVERTING}{\f20 \fs18 GATES}{\f20 \fs18 WHEN}{\f20 \
fs18 USING}{\f20 \fs18 INVERTERS }
fi368 {\b0 \f20 \fs18 When}{\b0 \f20 \fs18 using}{\b0 \f20 \fs18 logic}{\b0 \f
20 \fs18 gates,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 need}{\b0 \f20 \fs18 wil
l}{\b0 \f20 \fs18 arise}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 convert}{\b0 \f20
\fs18 to}{\b0 \f20 \fs18 another}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 func
tion.}{\i \fs17 An}{\b0 \f20 \fs18 easy}{\b0 \f20 \fs18 method }
\b0 \f20 \fs18 of}{\b0 \f20 \fs18 converting}{\b0 \f20 \fs18 is}{\b0 \f20 \f
s18 to}{\b0 \f20 \fs18 use}{\b0 \f20 \fs18 inverters}{\b0 \f20 \fs18 plac
ed}{\b0 \f20 \fs18 at}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 outputs}{\b0 \f20
\fs19 or}{\b0 \f20 \fs18 inputs}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 gates.
}{\b0 \f20 \fs18 It}{\b0 \f20 \fs18 has}{\b0 \f20 \fs18 been}{\b0 \f20 \fs1
8 shown}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 an }
\b0 \f20 \fs18 inverter}{\b0 \f20 \fs18 connected}{\b0 \f20 \fs18 at}{\b0 \f
20 \fs18 the}{\b0 \f20 \fs18 output}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 a
n}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 gate}{\b0 \f20 \fs18 produces}{\b0 \
f20 \fs18 the}{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 function.}{\b0 \f20 \fs
18 Also,}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 inverter }
\b0 \f20 \fs18 placed}{\b0 \f20 \fs18 at}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
output}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 OR}{\b0 \f
20 \fs18 gate}{\b0 \f20 \fs18 produces}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
NOR}{\b0 \f20 \fs18 function.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 chart}
{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 4-18}{\b0 \f20 \fs
18 illustrates }
\b0 \f20 \fs18 these}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 other}{\b0 \f20 \fs18
conversions. }
fi376 {\b0 \f20 \fs18 Placing}{\b0 \f20 \fs18 inverters}{\b0 \f20 \fs18 at}{\b
0 \f20 \fs18 all}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 inputs}{\b0 \f20 \fs18
of}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gate}{\b0 \f20 \fs
18 produces}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 results}{\b0 \f20 \fs18 illu
strated}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 4-19.}{\b0 \
f20 \fs18 In}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 first}{\b0 \f20 \fs18 line}{\b0 \f20 \fs18 the}{\b0 \f20 \fs1
8 inputs}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 AND}{\b0
\f20 \fs18 gate}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 being}{\b0 \f20 \fs18
inverted}{\b0 \f20 \fs18 (the}{\b0 \f20 \fs18 plus}{\b0 \f20 \fs18 symbo
l}{\b0 \f20 \fs18 indicates}{\b0 \f20 \fs18 addition}{\b0 \f20 \fs18 in}{\
b0 \f20 \fs18 this }
\b0 \f20 \fs18 figure).}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18 produces}{\b0 \f2
0 \fs18 the}{\b0 \f20 \fs18 NOR}{\b0 \f20 \fs18 function}{\b0 \f20 \fs18 at
}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 output}{\b0 \f20 \fs18 of}{\b0 \f20 \fs1
8 the}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 The}{\b0 \f2
0 \fs18 second}{\b0 \f20 \fs18 line}{\b0 \f20 \fs19 of}{\b0 \f20 \fs18 Fig.
}{\b0 \f20 \fs18 4-19 }
\b0 \f20 \fs18 shows}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 inputs}{\b0 \f20 \f
s18 of}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 OR}{\b0 \f20 \fs18 gate}{\b0 \
f20 \fs18 being}{\b0 \f20 \fs18 inverted.}{\b0 \f20 \fs18 This}{\b0 \f20 \
fs18 produces}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 f
unction.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 first}{\b0 \f20 \fs19 two }
\b0 \f20 \fs18 examples}{\b0 \f20 \fs18 suggest}{\b0 \f20 \fs18 new}{\b0 \f2
0 \fs18 symbols}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
NOR}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 functions.}{\
b0 \f20 \fs18 Figure}{\b0 \f20 \fs18 4-20}{\b0 \f20 \fs18 illustrates}{\b0 \
f20 \fs18 two}{\b0 \f20 \fs18 logic }
\b0 \f20 \fs18 symbols}{\b0 \f20 \fs18 sometimes}{\b0 \f20 \fs18 used}{\b0 \
f20 \fs18 for}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 NOR}{\b0 \f20 \fs18 an
d}{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 functions.}{\b0 \f20 \fs18 Figure}{
\b0 \f20 \fs18 4-20a}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18
alternative}{\b0 \f20 \fs18 logic }
\b0 \f20 \fs18 symbol}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 N
OR}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 Figure}{\b0 \f20 \fs18 4-206}{\b0 \f
20 \fs18 is}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 alternative}{\b0 \f20 \fs18
logic}{\b0 \f20 \fs18 symbol}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 a}{\b0 \f20
\fs18 NAND}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 These}{\b0 \f20 \fs18 sym
bols }
\b0 \f20 \fs18 are}{\b0 \f20 \fs18 encountered}{\b0 \f20 \fs18 in}{\b0 \f20 \f
s18 some}{\b0 \f20 \fs18 manufacturers'}{\b0 \f20 \fs18 literature. }
fi366 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 effect}{\b0 \f20 \fs18 of}{\b0 \f20
\fs18 inverting}{\b0 \f20 \fs18 both}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 in
puts}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 output}{\b0 \f20 \fs18 of}{\b0 \f20
\fs18 a}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gate}{\b0 \f20 \fs18 is}{\b0
\f20 \fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 4-2
1.}{\b0 \f20 \fs18 Again}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 plus}{\b0 \f20 \fs18 symbol}{\b0 \f20 \fs18 stands}{\b0 \f20
\fs18 for}{\b0 \f20 \fs18 addition.}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18
technique}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 probably}{\b0 \f20 \fs18 not
}{\b0 \f20 \fs18 used}{\b0 \f20 \fs18 often}{\b0 \f20 \fs18 because}{\b0 \
f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 large }

\b0 \f20 \fs18 number}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18
needed.}{\b0 \f20 \fs18 Note}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 this}{\b
0 \f20 \fs18 is}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 method}{\b0 \f20 \fs18
of}{\b0 \f20 \fs18 converting}{\b0 \f20 \fs18 from}{\b0 \f20 \fs18 the}{\b0 \
f20 \fs18 AND}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \f20 \fs19 OR}{\b0
\f20 \fs18 to}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 function.}{\b0 \f20 \fs18 This}{\b0 \f20
\fs18 is}{\b0 \f20 \fs18 also}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 method
}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 converting}{\b0 \f20 \fs18 from}{\b0 \
f20 \fs18 the}{\b0 \f20 \fs18 NAND}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 th
e}{\b0 \f20 \fs18 NOR}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \f20 \fs
18 NAND }
\b0 \f20 \fs18 function. }\par
}
\cf0 56 \par
}
HER{\b \fs17 LOGIC} GATES \par
}
f0 [CHAP.{\f10 \fs15 4 }\par
}
{\phpg\posx1849\pvpg\posy1476\absw595\absh327 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Or
iginal
7 gate \par
}
7c>- \par
}
{\phpg\posx3289\pvpg\posy1476\absw899\absh327 \f10 \fs14 \cf0 \f10 \fs14 \cf0 Ad
d{\f20 \fs15 inverter }
6 {\f20 \fs15 to}{\f20 \fs15 output }\par
}
\cf0 New
\par}{\phpg\posx4419\pvpg\posy1476\absw979\absh327 \sl-174 \f20 \fs15 \cf0 logic
function \par
}
d{\f20 \fs15 inverters }
6 {\b \fs11 to}{\f20 \fs15 Inputs }\par
}
{\phpg\posx5859\pvpg\posy2017\absw1287\absh702 \f10 \fs41 \cf0 \f10 \fs41 \cf0 cQ\par}{\phpg\posx5859\pvpg\posy2017\absw1287\absh702 \sl-303 \f10 \fs41 \cf0 {\fs
30 __oo__ }\par
}
iginal
0 gate \par
}
\cf0 New
function \par
}
\par
}
\fs14
NAND }\par
}
\par
}
R \par
}
\par
}
{\phpg\posx3249\pvpg\posy3032\absw860\absh276 \f10 \fs23 \cf0 \f10 \fs23 \cf0 _i
)D_ \par
}
\par
}
{\phpg\posx4761\pvpg\posy3130\absw361\absh164 \f10 \fs14 \cf0 \f10 \fs14 \cf0 AN
D \par
}
+{\fs115 =- }\par
}
\par
}
{\phpg\posx7207\pvpg\posy3969\absw165\absh234 \f10 \fs20 \cf0 \f10 \fs20 \cf0 >
\par
}
\par
}
{\phpg\posx9037\pvpg\posy4026\absw263\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 OR
\par
}
\par
}
\par
}
{\phpg\posx8987\pvpg\posy4886\absw361\absh164 \f10 \fs14 \cf0 \f10 \fs14 \cf0 AN
D \par
}
+){\f20 symbol}{\f20 means}{\f20 adding}{\f20 on}{\f20 this}{\f20 chart }
\fi387 {\b \f20 \fs17 Fig.}{\b \fs15 4-19}{\f20 \fs17
Effect}{\f20 \fs17 of
}{\f20 \fs17 inverting}{\f20 \fs17 inputs}{\f20 \fs17 of}{\f20 \fs17 gates
}\par
}
\cf0 "_a--)-m-= \par
}
15 \cf0 B \par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 NOR}{\b0\i0 \f20 \fs15 gate}{\b0\i0 \f20 \fs15
symbol }\par
}
\f20 \fs15 \cf0 B
\fi583 {\b0\i0 (b)}{\b0\i0 \fs15 NAND}{\b0\i0 gate}{\b0\i0 symbol }
\cf0 {\i0 \fs17 Fig.}{\i0 \f10 \fs15 4-20}{\b0\i0 \fs17
Alternative}{\b0\i0
\fs17 logic}{\b0\i0 \fs17 symbols }\par
}
15 \cf0 Y \par
}
15 \cf0 Y \par
}
\par
}
\par
}
R \par
}
+
s30 -Do- }
s30 -Do- }\par
}
){\f20 \fs15 symbol}{\f20 \fs15 means}{\f20 \fs15 adding}{\f20 \fs15 on}{\f
20 \fs15 this}{\f20 \fs15 chart }
\fi174 {\b \f20 \fs17 Fig.}{\b 4-18}{\f20 \fs17
Effect}{\f20 \fs17 of}{\f20
\fs17 inverting}{\f20 \fs17 outputs}{\f20 \fs16 of}{\f20 \fs17 gates }\par
}
d{\f20 \fs15 inverters }
7 {\f20 \fs15 to}{\f20 \fs15 inputs }\par
}
iginal
5 gate \par
}
d{\f20 \fs15 inverter }

7 {\f20 \fs15 to}{\f20 \fs15 output }\par
}
\cf0 New
function \par
}
{\phpg\posx2715\pvpg\posy12371\absw908\absh605 \f10 \fs30 \cf0 \f10 \fs30 \cf0 P\par}{\phpg\posx2715\pvpg\posy12371\absw908\absh605 \sl-299 \f10 \fs30 \cf0 {\fs
29 -GQ- }\par
}
> \par
}
\par
}
\par
}
{\phpg\posx5877\pvpg\posy12448\absw803\absh272 \f10 \fs23 \cf0 \f10 \fs23 \cf0 I>(.- \par
}
{\fs14
NAND }\par
}
(+){\f20 \fs15 symbol}{\f20 \fs15 means}{\f20 \fs15 adding}{\f20 \fs15 on}
{\f20 \fs15 this}{\f20 \fs15 chart }
\fi659 {\b \f20 \fs17 Fig.}{\b \fs15 4-21}{\f20 \fs17
Effect}{\f20 \fs17 o
f}{\f20 \fs17 inverting}{\f20 \fs17 both}{\f20 \fs17 inputs}{\f20 \fs17 and
}{\f20 \fs17 outputs}{\f20 \fs17 of}{\f20 \fs17 gates }\par
}
.{\fs17 41 }\par
}
cf0 OTHER{\b0 \fs17 LOGIC}{\fs17 GATES }\par
}
\par
}
cf0 SOLVED{\fs17 PROBLEMS }\par
}
f0 4.21 \par
}
Given an{\b \fs19 OR} gate and inverters, draw a logic diagram that wi
ll perform the 2-input NAND
\par}{\phpg\posx1443\pvpg\posy2158\absw8387\absh1000 \sl-249 \f20 \fs19 \cf0 fun
ction.

}
\f10 \fs14 \cf0 {\f20 \fs15 A= }
\cf0 {\i0 \f20 \fs17 Fig.}{\i0 \fs15 4-22}{\b0\i0 \f20 \fs17
2-input}{\b0\i0
\f20 \fs17 NAND}{\b0\i0 \f20 \fs17 function }\par
}
f0 4.22 \par
}
iven an{\fs19 OR} gate and inverters, draw a logic diagram that will
perform the 3-input AND
tion.
}
cf0 c \par
}
\cf0 'ts \par
}
\par
}
\cf0 Fig.{\f10 \fs15 4-23}{\b0 \fs17
3-input}{\b0 \fs17 AND}{\b0 \fs17 fu
nction }\par
}
iven a NAND gate and inverters, draw a logic diagram that will perfor
m the 2-input{\fs19 OR }
tion.
\fs17 Solution: }
}
f0 4.23 \par
}
\cf0 Fig.{\f10 \fs15 4-24}{\b0 \fs17
2-input}{\fs17 OR}{\b0 \fs17 functi
on }\par
}
cf0 4.24 \par
}
Given{\b a} NAND gate and inverters, draw a logic diagram that will perform
the 3-input{\fs19 AND }
ction.

\fs17 Solution: }
}
\cf0 58 \par
}
HER{\b \fs17 LOGICGATES }\par
}
}
\cf0 Fig.{\f10 \fs16 4-25}{\b0 \fs17
3-input}{\b0 \fs17 AND}{\b0 \fs17 fun
ction }\par
}
f0 4.25 \par
}
Given an{\b \fs19 AND} gate and inverters, draw a logic diagram that wil
l perform the 2-input{\b \fs19 NOR }
ction.
364 {\b\i \fs17 See}{\b \fs17 Fig.}{\b \fs17 4-26. }
\cf0 \fi2654 {\b\i \f10 \fs14 A }
4702 {\b\i \fs15 A}{\b\i \fs15 +}{\b\i \fs15 B}{\b\i \fs15 =}{\b\i \fs15
Y}{\b\i \fs15 . }
2664 {\b\i \fs15 B }
\fi2870 {\b \fs16 Fig.}{\b \f10 \fs15 4-26}{\fs17
2-input}{\fs17 NOR}{\fs
17 function }\par
}
\cf0 4-7{\f20 \fs19
NAND}{\f20 \fs19 AS}{\f20 \fs18 A}{\f20 \fs19 UNIVERS
AL}{\f20 \fs19 GATE }
fi368 {\b0 \f20 \fs18 Consider}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 logic}{\b0
\f20 \fs18 circuit}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18
Fig.}{\b0 \f20 \fs18 4-27a.}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18 is}{\b0 \f20
\fs18 referred}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 an}{\
i \f20 \fs18 AND-ORpattern}{\b0 \f20 \fs18 of}{\i \f20 \fs18 gates. }
\b0 \f20 \fs18 The}{\f20 \fs19 AND}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18 feed
}{\b0 \f20 \fs18 into}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 final}{\b0 \f20 \f
s19 OR}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 Boolean}{\b
0 \f20 \fs18 expression}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 this}{\b0 \f20 \
fs18 circuit}{\b0 \f20 \fs19 is}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 at}{\
b0 \f20 \fs18 the }
\b0 \f20 \fs18 right}{\b0 \f20 \fs18 as}{\b0\i \f30 \fs27 2.}{\b0 \fs27
- }
\b0 \f20 \fs18 gates,}{\b0 \f20 \fs18 an}{\b0 \f20 \fs19 OR}{\b0 \f20 \fs18
gate,}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 an}{\b0 \f20 \fs18 inverter).}
{\b0 \f20 \fs18 From}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 manufacturer's}{\b0
\f20 \fs18 catalog,}{\b0 \f20 \fs18 you}{\b0 \f20 \fs18 would}{\b0 \f20 \
fs18 find}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 three }
\b0 \f20 \fs18 different}{\b0 \f20 \fs19 ICs}{\b0 \f20 \fs18 would}{\b0 \f20 \
fs18 be}{\b0 \f20 \fs18 needed}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 implement
}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 circuit}{\b0 \f20 \fs18 shown}{\b0 \f20
\fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 4-27a. }\par
}
s19 \cf0 B{\fs19 +}{\fs19 A}{\fs19 B}{\b0\i0 \f10 \fs14 =}{\fs18 Y.}{\b0\
i0 \fs18 In}{\b0\i0 \fs18 constructing}{\b0\i0 \fs18 the}{\b0\i0 \fs18 cir
cuit,}{\b0\i0 \fs18 you}{\b0\i0 \fs18 need}{\b0\i0 \fs18 three}{\b0\i0 \fs1
8 different}{\b0\i0 \fs18 types}{\b0\i0 \fs18 of}{\b0\i0 \fs18 gates}{\i
0 \fs19 (AND }\par
}
14 \cf0 A \par
}
cf0 A \par
}
f0 T \par
}
14 \cf0 B \par
}
s14 \cf0 + A .{\b0 \fs15 B}{\b0 \fs15 =}{\fs15
Y }\par
}
fs12 \cf0 (a){\i0 \f20 \fs15 An}{\i0 \f20 \fs15 AND-OR}{\i0 \f20 \fs15 logic
}{\b0\i0 \f20 \fs14 circuit }\par
}
\cf0 (h){\b\i0 \fs15 An}{\b\i0 \fs15 equivalent}{\b\i0 \fs15 NAND}{\b\i0 \f
s15 logic}{\b\i0 \fs15 circuit }
\par}{\phpg\posx4023\pvpg\posy13097\absw2851\absh543 \sl-203 \par\i \f20 \fs14 \
cf0 \fi848 {\b\i0 \fs17 Fig.}{\b\i0 \f10 \fs16 4-27 }\par
}
.{\fs17 41 }\par
}
}
\par
}
\cf0 It was mentioned earlier that the NAND gate is considered a universal g
ate. Figure{\fs19 4-276} shows
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-238 \f20 \fs18 \cf0 NAND

gates being used to implement the logic{\i \fs19 A}{\i \fs19 .}{\i \f
s19 B}{\b\i \f10 \fs17 +}{\b\i \f10 \fs17 A}{\b\i \f30 \fs21 *.B }{\dn006 \
f10 \fs13 =}{\b\i \fs19 Y.} This logic is the same as that
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-235 \f20 \fs18 \cf0 perf
ormed by the AND-OR circuit shown in Fig.{\fs19 4-27a.} Remember that the OR-l
ooking gate (gate{\fs19 4) }
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-240 \f20 \fs18 \cf0 with
the invert bubbles at the inputs is a NAND gate. The circuit shown
in Fig.{\fs19 4-27b} is simpler
use all the gates are NAND gates. It is found that only one{\fs19 IC} (a quadru
ple 2-input NAND gate)
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-239 \f20 \fs18 \cf0 is
needed to implement the NAND logic of Fig.{\fs19 4-27b.} Fewer ICs are
needed to implement the
logic circuit than the AND-OR pattern of logic gates.
75 It is customary when converting from AND-OR logic to NAND logic{\fs1
9 to} draw the AND-OR
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-242 \f20 \fs18 \cf0 patt
ern first. This can be done from the Boolean expression. The AND-OR logic dia
gram would be
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-233 \f20 \fs18 \cf0 simi
lar to that in Fig.{\fs19 4-27a.} A NAND gate is then substituted for each inve
rter, AND gate, and OR
. The NAND logic pattern will then be similar to the circuit shown in Fig.{\fs1
9 4-276. }
68 A clue to{\i \fs18 why} the AND-OR logic can be replaced{\fs18 by} NAND
logic is shown in Fig.{\fs19 4-276.} Note
two invert bubbles between the output{\fs18 of} gate 2 and the input{\fs18 of}
gate{\fs19 4.}{\i \fs19 Two}{\fs19 invert}{\fs19 bubbles}{\fs19 cancel }
19 one}{\fs19 another.} That leaves the AND-OR symbols just as in Fig.{\fs19
4-27a.} The{\fs19 double}{\fs19 inversion} also takes
e in Fig.{\fs19 4-27b} between gates{\fs18 3} and 4. This leaves AND gate{\fs
18 3} feeding OR gate{\f10 \fs18 4.} NAND gate{\fs19 1 }
\par}{\phpg\posx839\pvpg\posy1358\absw9148\absh3417 \sl-232 \f20 \fs18 \cf0 acts
as an inverter when its inputs are tied together as shown in Fig.{\fs19 4-27
6. }\par
}
LVED PROBLEMS \par
}
f0 4.26 \par
}
{\phpg\posx1459\pvpg\posy6472\absw8344\absh215 \f20 \fs18 \cf0 \f20 \fs18 \cf0 R
edraw the AND-OR circuit shown in Fig.{\fs19 4-lla} by using five 2input NAND gates. The \par
}
{\phpg\posx1447\pvpg\posy6700\absw4234\absh773 \f20 \fs18 \cf0 \f20 \fs18 \cf0 N
AND logic circuit should perform the logic{\b\i \f10 A }
\fs16 Solution: }

60 {\fs16 See}{\fs16 Fig.}{\b \fs16 4-28. }\par
}
s27 \cf0 B{\b0 \fs28 +A.}{\b0\i0\dn006 \f10 \fs13 =}{\dn006 \f20 \fs19 Y.B }
\par
}
16 \cf0 + A * B = Y \par
}
\cf0 Fig.{\f10 \fs15 4-28}{\b0 \fs17
Solution}{\b0 \fs16 using}{\b0 \fs17
NAND}{\b0 \fs16 logic }\par
}
Draw a logic diagram for the Boolean expression{\b\i \fs19 A}{\f10 \fs27 -}{\
b\i \fs19 B}{\b\i \f10 \fs18 +}{\b\i \f10 \fs18 A}{\f10 \fs23 -}{\i \fs19 B
}{\dn006 \f10 \fs14 =}{\b\i \fs19 Y.} Use inverters, AND gates, \par
}
and OR gates.
360 {\fs16 See}{\fs16 Fig.}{\b \fs16 4-29. }\par
}
}
}
cf0 4.27 \par
}
cf0 4.28 \par
}
Redraw the logic diagram{\f10 \fs19 -}of{\f10 \fs19 -}Prob.{\fs19 4.27} by
using only{\fs18 five} 2-input NAND gates. The circuit
\par}{\phpg\posx1475\pvpg\posy12633\absw8289\absh986 \sl-236 \f20 \fs18 \cf0 sho
uld perform the logic{\b\i A}{\f10 \fs23 -}{\b\i \fs19 B}{\b\i \f10 \fs17 +
}{\b\i \f10 \fs17 A}{\f10 \fs23 -}{\i \fs19 B}{\dn006 \f10 \fs13 =}{\b\i Y
. }
\fs16 Solution: }
354 {\b \fs16 See}{\fs16 Fig.}{\b \fs16 4-30. }\par
}
0 60 \par
}
HER{\b LOGIC}{\b GATES }\par
}
}
\cf0 Fig. 4-29{\b0 \fs17
AND-OR}{\b0 \fs17 logic}{\b0 \fs17 circuit }\par
}
13 \cf0 A \par
}
15 \cf0 B \par
}
14 \cf0 + A . B ={\fs14
Y }\par
}
\cf0 Fig. 4-30{\b0 \fs17
Equivalent}{\b0 \fs17 NAND}{\b0 \fs17 logic}{\b0
\fs17 circuit }\par
}
\cf0 4-8 USING PRACTICAL LOGIC GATES
fi360 {\b0 \fs18 The}{\b0 \fs18 most}{\b0 \fs18 useful}{\b0 \fs18 logic}{\b0
\fs18 gates}{\b0 \fs18 are}{\b0 \fs18 packaged}{\b0 \fs18 as}{\b0 \fs18 i
ntegrated}{\b0 \fs18 circuits.}{\b0 \fs18 Figure}{\i 4-31}{\b0 \fs18 illu
strates}{\b0 \fs18 two}{\b0 \fs18 TTL }
\b0 \fs18 logic}{\b0 \fs18 gates}{\b0 \fs18 that}{\b0 \fs18 can}{\b0 \fs18 b
e}{\b0 \fs18 purchased}{\b0 \fs18 in}{\b0 \fs18 IC}{\b0 \fs18 form.}{\fs18
A}{\b0 \fs18 pin}{\b0 \fs18 diagram}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 7400
}{\b0 IC}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\i
4-31a.}{\b0 \fs18 The }
\i 7400}{\b0 \fs18 is}{\b0 \fs18 described}{\i \fs18 by}{\b0 \fs18 the}{\b0
\fs18 manufacturer}{\b0 \fs18 as}{\b0 \fs18 a}{\i quadrupZe}{\i 2-input}
{\i NAND}{\i gate}{\b0 \fs18 IC.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \f
s18 the}{\i 7400}{\b0 \fs18 IC }
\b0 \fs18 does}{\b0 \fs18 have}{\b0 \fs18 the}{\b0 \fs18 customary}{\b0 \f
s18 power}{\b0 \fs18 connections}{\b0\i \fs18 (Vcc}{\b0 \fs18 and}{\fs18
GND).}{\b0 \fs18 All}{\b0 \fs18 other}{\b0 \fs18 pins}{\b0 \fs18 are}
{\b0 \fs18 the}{\b0 \fs18 inputs}{\b0 \fs18 and }
\b0 \fs18 outputs}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 four}{\b0 \fs18
2-input}{\fs18 NAND}{\b0 \fs18 gates. }\par
}
s18 \cf0 v,
\cf0 {\i0 \f20 \fs14 4B }
\cf0 {\b0\i0 \f10 \fs13 4A }
\cf0 {\i0 \f20 \fs14 4Y }
\cf0 {\f20 \fs14 3B }
\cf0 {\f20 \fs14 3A }
\cf0 {\f20 \fs14 3Y }\par
}
{\phpg\posx4819\pvpg\posy10009\absw79\absh70 \f10 \fs5 \cf0 \f10 \fs5 \cf0 i \pa
r
}
\f20 \fs14 \cf0 1A
\cf0 \fi216 {\b0\i0 \fs14 1B }
\cf0 \fi200 {\i0 \f30 \fs16 1Y }
\cf0 \fi191 {\f10 \fs13 2A }
\cf0 \fi200 2B
\cf0 \fi210 {\b0 2}{\b0 Y }
\cf0 {\i0 \fs15 GND }\par
}
\cf0 IS \par
}
s13 \cf0 2A \par
}
\cf0 1c
f0 {\f20 \fs14 1}{\f20 \fs14 Y }\par
}
{\phpg\posx6041\pvpg\posy10852\absw4389\absh1548 \i \f10 \fs110 \cf0 \i \f10 \fs
110 \cf0 U{\i0 \fs127 @:; }\par
}
a l l \par
}
s17 \cf0 2c{\fs13
6 }
}{\phpg\posx5747\pvpg\posy12019\absw472\absh217 \b\i \f10 \fs17 \cf0 {\dn006 \f2
0 \fs14 2Y }\par
}
ND \par
}
\par
}
fs14 \cf0 (b){\i0 \fs15 Pin}{\i0 \fs15 diagram}{\i0 \fs14 for}{\i0 \fs15 a}{
\b0\i0 \f10 \fs13 7410}{\i0 \fs15 IC }\par
}
\cf0 11{\i \fs18 3c }\par
}
s14 \cf0 2B \par
}
9 \cf0 ( U ) \par
}
\cf0 Pin diagram{\fs15 for}{\fs15 a}{\b0 \f10 \fs13 7400}{\fs15 IC }\par
}
\cf0 Fig. 4-31 \par
}
0 CHAP.{\f30 \fs18 41 }\par
}
HER{\fs17 LOGIC}{\b GATES }\par
}
\par
}
\cf0 Three 3-input NAND gates are housed in the 7410{\fs19 W}{\fs19 L} IC. T
he pin diagram for the 7410 IC is
n in Fig. 4-31b. This device is described by the manufacturer as a triple 3-i
nput{\b\i \fs19 NAND} gate IC.
19 NAND} gates with more than three inputs also are available.
60 The 7400 and 7410 ICs were from the common{\fs19 TTL} logic family. Manufac
turers also produce a
\par}{\phpg\posx857\pvpg\posy1328\absw9133\absh3091 \sl-243 \f20 \fs19 \cf0 vari
ety of NAND, NOR, and{\fs19 XOR} gates in CMOS-type ICs. Typical NAN
D gates might be the
\par}{\phpg\posx857\pvpg\posy1328\absw9133\absh3091 \sl-234 \f20 \fs19 \cf0 CMOS
74COO quad 2-input NAND gate, 74C30 8-input NAND gate, and 4012 dual 4-inpu
t NAND
DIP ICs. Some CMOS NOR gates in{\fs19 DIP}{\fs19 IC} form are the 74C02 quad
2-input NOR gate and the
dual 4-input NOR gate. Several exclusive-OR gates are produced in CMOS;
examples are the
\par}{\phpg\posx857\pvpg\posy1328\absw9133\absh3091 \sl-235 \f20 \fs19 \cf0 74C8
6 quad 2-input{\fs19 XOR} gate and the 4030 quad 2-input{\fs19 XOR} gate. No
te that CMOS ICs come in
\par}{\phpg\posx857\pvpg\posy1328\absw9133\absh3091 \sl-240 \f20 \fs19 \cf0 both
a 74COO series and a 4000 series. It must be remembered that without speci
al interfacing,{\i TTL }
\par}{\phpg\posx857\pvpg\posy1328\absw9133\absh3091 \sl-243 \f20 \fs19 \cf0 and{
\b\i CMOS}{\b\i \fs19 ICs} are not compatible.
{\b \f10 \fs16 SOLVED}{\f10 \fs16 PROBLEMS }
\f10 \fs17 4.29}
Construct the truth table for the circuit shown in Fig. 4
-32. \par
}
\par
}
1 \par
}
\par
}
cf0 150{\f20 \fs15 R }\par
}
\cf0 Fig.{\fs17 4-32}{\b0
Wiring}{\b0 diagram}{\b0 \fs17 of}{\b0 \fs17 a
}{\b0 logic-circuit}{\b0 problem }\par
}
cf0 Solution: \par
}
puts \par
}
tput \par
}
r
}
r
}
7 1 }
7 0 }
7 1 }\par
}
\cf0 4.30{\b0 \fs19
What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 voltag
e}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19 power}{\b0 \fs19 supply}{\b0 \fs19
at}{\b0 \fs19 the}{\b0 \fs19 left}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19
4-32?}{\b0 \fs19 The}{\b0 \fs19 7400}{\b0 \fs19 IC}{\b0 \fs19 is}{\b0 \fs1
9 a}{\b0 \fs19 TTL}{\b0 \fs19 device. }
\fi952 {\fs17 A}{\b0 \fs17 TTL}{\b0 \fs17 device}{\b0 \fs17 uses}{\b0 \fs17
a}{\b0 \fs17 5-V}{\b0 \fs17 dc}{\b0 \fs17 power}{\b0 \fs17 supply. }
cf0 {\fs18 4.31}{\b0 \fs19
If}{\b0 \fs19 both}{\b0 \fs19 switches}{\i \fs
19 (}{\i \fs19 A}{\b0 \fs19 and}{\i \fs19 B}{\i \fs19 )}{\b0 \fs19 shown}
{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 4-32}{\b0 \fs19 are}{\b0 \fs19 in}
{\b0 \fs19 the}{\b0 \fs19 up}{\b0 \fs19 position}{\b0 \fs19 (at}{\b0 \fs1
9 logical}{\b0 \fs18 l),}{\b0 \fs19 the}{\b0 \fs19 output }\par
}
LED will be
}

lit,not lit). \par
}
When both inputs are 1, the output{\fs17 of} the circuit will be{\b
1} and the output LED will be lit. \par
}
par
}
}
AP. 4 \par
}
cf0 4.32{\b0 \f20 \fs19
The}{\b0 \f20 \fs19 7400}{\b0 \f20 \fs19 IC}{\b0 \
f20 \fs19 is}{\b0 \f20 \fs19 described}{\b0 \f20 \fs19 by}{\b0 \f20 \fs19 th
e}{\b0 \f20 \fs19 manufacturer}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 a}{\b0 \f20
\fs19 quadruple }
i606 {\f20 \fs17 Solution: }
i958 {\b0 \f20 \fs17 The}{\b0 \f20 \fs17 7400}{\b0 \f20 \fs17 IC}{\b0 \f20 \fs
17 is}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 quadruple}{\b0 \f20 \fs17 2-input}
{\b0 \f20 \fs17 NAND}{\b0 \f20 \fs17 gate. }\par
}
f0 4.33 \par
}
The circuit shown in Fig.{\b 4-32} could be described as{\fs19 a(n) }
\par}{\phpg\posx1431\pvpg\posy2590\absw5322\absh2116 \sl-246 \f20 \fs19 \cf0 cir
cuit.
\fs17 Solution: }
358 {\fs17 The}{\fs17 circuit}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs17
4-32}{\fs17 uses}{\fs17 NAND}{\fs17 logic. }
The{\b 4012} is a dual 4-input NAND gate IC using the
\fs17 Solution: }
360 {\fs17 The}{\fs17 4000}{\fs17 series}{\fs17 part}{\fs17 numbers}{\fs17
designate}{\fs17 CMOS}{\fs17 digital}{\fs17 ICs. }\par
}
par
}
AND-OR,NAND) logic \par
}
f0 434 \par
}
CMOS,{\fs19 TTL)} technology. \par

}
f0 4.35 \par
}
22 \cf0 SupplementaryProblems
{\f20 \fs17 Write}{\f20 \fs17 the}{\f20 \fs17 Boolean}{\f20 \fs17 express
ion}{\f20 \fs17 for}{\f20 \fs17 a}{\f20 \fs17 4-input}{\f20 \fs17 NAND}{
\f20 \fs17 gate. }
20 \fs17 Ans.}{\f20 \fs17
A}{\f20 \fs17 .}{\f20 \fs17 B}{\f20 \fs17 -}{\f
20 \fs17 C}{\f20 \fs17 .}{\f20 \fs17 D}{\f20 \fs17 =}{\f20 \fs17 Y}{\f20 \f
s17 o}{\f20 \fs17 r}{\f20 \fs17 A}{\f20 \fs17 B}{\f20 \fs17 C}{\f20 \fs17
D}{\f20 \fs17 =}{\f20 \fs17 Y }
\fi27 {\f20 \fs17 Draw}{\f20 \fs17 the}{\f20 \fs17 logic}{\f20 \fs17 symbo
l}{\f20 \fs17 for}{\f20 \fs17 a}{\f20 \fs17 4-input}{\f20 \fs17 NAND}{\f2
0 \fs17 gate.}{\f20 \fs17
Ans.}{\f20 \fs17
See}{\f20 \fs17 Fig.
}{\f20 \fs17 4-33. }\par
}
f0 4.36 \par
}
ig.{\b \f30 \fs17 4-33}{\fs17 A}{\fs17 4-input}{\fs17 NAND}{\fs17 gate }\
par
}
f0 4.37 \par
}
\cf0 Construct the truth table for a 4-input NAND gate.
\par}{\phpg\posx1415\pvpg\posy9173\absw4118\absh390 \sl-220 \f20 \fs17 \cf0 Ans.
\par
}
nputs \par
}
C
23 0
21 {\fs17 0 }
23 {\fs17 0 }
25 {\fs17 0 }
23 {\fs17 1 }
23 {\fs17 1 }
21 {\fs17 1 }
25 {\fs17 1 }\par
}
B
23 0
23 {\fs17 0 }
23 {\fs17 1 }
27 {\fs17 1 }
23 {\fs17 0 }
23 {\fs17 0 }
23 {\fs17 1 }
27 {\fs17 1 }\par
}
D
33 0
29 {\fs17 0 }
33 {\fs17 0 }
33 {\fs17 0 }
33 {\fs17 0 }
33 {\fs17 0 }
29 {\fs17 0 }
33 {\fs17 0 }\par
}
A
23 0
25 {\fs17 1 }
23 {\fs17 0 }
29 {\fs17 1 }
23 {\fs17 0 }
23 {\fs17 1 }
25 {\fs17 0 }
29 {\fs17 1 }\par
}
utput
\fi221 Y \par
}
nputs \par
}
C
35 {\fs17 0 }
37 {\fs17 0 }
35 {\fs17 0 }
37 {\fs17 0 }
31 {\fs17 1 }
35 {\fs17 1 }
33 {\fs17 1 }
37 {\fs17 1 }\par
}
B
39 {\fs17 0 }
42 {\fs17 0 }
39 {\fs17 1 }
44 {\fs17 1 }
35 {\fs17 0 }
39 {\fs17 0 }
35 {\fs17 1 }
42 {\fs17 1 }\par
}
D
42 {\fs17 1 }
42 {\fs17 1 }
42 {\fs17 1 }
42 {\fs17 1 }
38 {\fs17 1 }
42 {\fs17 1 }
42 {\fs17 1 }
42 {\fs17 1 }\par
}
A
42 {\fs17 0 }
48 {\fs17 1 }
42 {\fs17 0 }
50 {\fs17 1 }
38 {\fs17 0 }
42 {\fs17 1 }
37 {\fs17 0 }
48 {\fs17 1 }\par
}
output
223 {\b\i \fs17 Y }
193 {\f10 \fs1 ~~ }
243 {\fs17 1 }
243 {\fs17 1 }
240 {\fs16 1 }
243 {\fs17 1 }
240 {\fs17 1 }
243 {\fs17 1 }
240 {\fs17 1 }
230 0 \par
}
cf0 4.38 \par
}
\cf0 What would the output pulse train shown in Fig. 4-34{\fs17 look}
like if input{\b\i \f30 \fs18 C} were{\fs17 O? }
\i \fs17 Am.}
The output of the NAND gate would be{\fs17 1} at all ti
mes. \par
}
}
}
f0 63 \par
}
4 \cf0 g \par
}
4 \cf0 f \par
}
4 \cf0 e \par
}
14 \cf0 d \par
}
4 \cf0 c \par
}
14 \cf0 b \par
}
14 \cf0 a \par
}
{\phpg\posx7531\pvpg\posy2062\absw110\absh168 \f10 \fs14 \cf0 \f10 \fs14 \cf0 ?
\par
}
\cf0 Fig.{\f10 \fs15 4-34}{\b0 \fs17
}
f0 4.39 \par
}
hat would the output pulse train shown in Fig. 4-34 look like if inp
ut{\b\i \f30 \fs18 C} were{\fs16 l? }\par
}
s16 \cf0 Ans.{\b0\i0 \fs17
pulse}{\b0 \f10 \fs15 n}{\b0\i0 \f10 \fs13 =}{
\b0\i0 \fs17 0 }
\fi534 {\b0\i0 \fs17 pulse}{\b0 \fs16 h}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs16
1 }\par
}
lse{\i \f10 \fs14 c}{\f10 \fs13 =}{\fs16 1 }
{\b\i \fs16 d}{\f10 \fs13 =}{\fs16 0 }\par
}
lse{\b\i \fs16 e}{\f10 \fs13 =}{\fs16 1 }
{\i \f30 \fs20 f}{\dn006 \f10 \fs13 =}{\fs16 0 }\par
}
lse{\i \f10 \fs14 g}{\f10 \fs13 =}{\fs16 1 }\par
}
f0 4.40 \par
}
rite the Boolean expression for a 4-input NOR gate. \par
}
raw the logic symbol for a 4-input NOR gate. \par
}
s17 \cf0 Ans.{\f10 \fs15
A}{\b0\i0 \f10 \fs26 +}{\dn006 B}{\b0\i0 \f10 \fs
26 +}{\dn006 \fs17 C}{\b0\i0 \f10 \fs25 + }\par
}
cf0 D={\b Y }\par
}
f0 4.41 \par
}
s16 \cf0 Ans.{\b0\i0 \fs17
See}{\b0\i0 \fs17 Fig.}{\b0\i0 \fs17 4-35. }\
par
}
\cf0 Fig.{\f10 \fs15 4-35}{\fs16
A}{\b0 \fs17 4-input}{\b0 \fs17 NOR}{\b0
\fs17 gate }\par
}
f0 4.42 \par
}
onstruct the truth table for a 4-input{\fs17 NOR} gate.
i \fs16 Ans. }\par
}
puts \par
}
tput \par
}
puts \par
}
s17 \cf0 C
\cf0 \fi30 {\b0\i0 \fs16 0 }
\fi29 {\b0\i0 \fs16 0 }
\fi32 {\b0\i0 \fs16 0 }
\fi30 {\b0\i0 \fs16 0 }
\fi28 {\b0\i0 \fs16 1 }
\fi25 {\b0\i0 \fs16 1 }
\fi25 {\b0\i0 \fs16 1 }
\fi28 {\b0\i0 \fs16 1 }\par
}
s17 \cf0 R
\cf0 \fi24 {\b0\i0 \fs16 0 }
\fi28 {\b0\i0 \fs16 0 }
\fi28 {\b0\i0 \fs16 1 }
\fi24 {\b0\i0 \fs16 1 }
\fi24 {\b0\i0 \fs16 0 }
\fi24 {\b0\i0 \fs16 0 }
\fi24 {\b0\i0 \fs16 1 }
\fi24 {\b0\i0 \fs16 1 }\par
}
\f20 \fs17 \cf0 \b\i \f20 \f

\sl-168 \par\b\i \f20 \fs17
\sl-254 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 0
16 0 }
16 0 }
16 0 }
16 0 }
16 0 }
16 0 }
16 0 }\par
}
\sl-253 \f20 \fs17 \cf0 {\fs
16 0 }
16 0 }
16 0 }
16 1 }
16 1 }
16 1 }
16 1 }\par
}
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-260 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-255 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-260 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-255 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\fs17 \cf0 \f20 \fs17 \cf0 0

16 0 }
16 1 }
16 1 }
16 0 }
16 0 }
16 1 }
16 1 }\par
}
\sl-260 \f20 \fs17 \cf0 {\fs
16 1 }
16 0 }
16 1 }
16 0 }
16 1 }
16 0 }
16 1 }\par
}
s17 \cf0 D
\cf0 \fi45 {\b0\i0 \fs16 1 }
\fi42 {\b0\i0 \fs16 1 }
\fi45 {\b0\i0 \fs16 1 }
\fi45 {\b0\i0 \fs16 1 }
\fi42 {\b0\i0 \fs16 1 }
\fi38 {\b0\i0 \fs16 1 }
\fi38 {\b0\i0 \fs16 1 }
\fi42 {\b0\i0 \fs16 1 }\par
}
s17 \cf0 A
\cf0 {\b0\i0 \fs16 0 }
\fi26 {\b0\i0 \fs16 1 }
\fi24 {\b0\i0 \fs16 0 }
{\b0\i0 \fs16 1 }
\fi20 {\b0\i0 \fs16 0 }
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs

\sl-259 \f20 \fs17 \cf0 {\fs
\sl-255 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-260 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-255 \f20 \fs17 \cf0 {\fs
\sl-254 \f20 \fs17 \cf0 {\fs
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-168 \par\b\i \f20 \fs17
\sl-254 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-168 \par\b\i \f20 \fs17
\sl-254 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-259 \b\i \f20 \fs17 \cf0
\fi22 {\b0\i0 \fs16 1 }

\fi22 {\b0\i0 \fs16 0 }
\fi20 {\b0\i0 \fs16 1 }\par
}
tput
fi226 {\b\i Y }\par
}
cf0 4.43 \par
}
cf0 4.44 \par
}
What would the output pulse train shown in Fig. 4-36{\b \fs17 look} li
ke i:f input{\b\i \fs16 C} were{\fs16 l? }
\i \fs16 Ans.}
The output of the{\fs17 NOR} gate would always be 0.
What would the output pulse train shown in Fig. 4-36{\b look} like i
f input{\b\i \f30 \fs18 C} were{\fs16 O? }\par
}
pulse}{\b0 \f10 \fs14 a}{\b0\i0 \f10 \fs14 =
}{\b0\i0 \fs16 0 }
0 \fi534 {\b0\i0 \fs17 pulse}{\b0 \fs16 b}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0
\fs16 1 }\par
}
ulse{\i \f10 \fs15 c}{\f10 \fs13 =}{\fs16 1 }
e{\b\i \fs16 d}{\f10 \fs13 =}{\fs16 0 }\par
}
ulse{\b\i \fs16 e}{\f10 \fs13 =}{\fs16 0 }
e{\i \f30 \fs19 f}{\dn006 \f10 \fs13 =} 0 \par
}
ulse{\fs15 g}{\f10 \fs14 =}{\fs16 1 }\par
}
0 64 \par
}
HER{\fs17 LOGIC} GATES \par
}
AP. 4 \par
}
\cf0 0
fi108 {\b\i \f20 \fs14 g }

\par}{\phpg\posx3709\pvpg\posy1418\absw291\absh670 \sl-263 \f10 \fs14 \cf0 oJ1 \
par
}
\cf0 Je \par
}
1 \par
}
\par
}
\par
}
\i \fs14 b }\par
}
\par
}
cf0 5 \par
}
1 0 \par
}
\par
}
r - \par
}
f0 4.45 \par
}
20 \fs16 \cf0 Fig.{\f10 \fs15 4-36}{\b0 \fs17
Pulse-train}{\b0 \fs17 proble
m }
cf0 \fi22 {\b0 \fs17 Write}{\b0 \fs17 the}{\b0 \fs17 Boolean}{\b0 \fs17 ex
pression}{\b0 \fs17 for}{\b0 \fs17 a}{\b0 \fs17 4-input}{\b0 \fs17 XOR}{\
b0 \fs17 gate. }
{\i \fs17 Ans.}{\i \fs17
A}{\i \fs17 @}{\i \fs17 B}{\i \fs17 @}{\i \fs17
C}{\i \fs17 @}{\i \fs17 D}{\i \fs17 =}{\i \fs17 Y }
cf0 \fi26 {\b0 \fs17 Draw}{\b0 \fs17 the}{\b0 \fs17 logic}{\b0 symbol}{\b0
\fs17 for}{\b0 \fs17 a}{\b0 \fs17 4-input}{\b0 \fs17 XOR}{\b0 \fs17 gate
.}{\i \fs17
Am.}{\b0 \fs17
See}{\b0 \fs17 Fig.}{\b0 \fs17 4-37.
}\par
}
f0 4.46 \par
}
\cf0 Fig.{\f10 \fs15 4-37} A{\b0 \fs17 4-input}{\b0 \fs17 XOR}{\b0 \fs17
gate }\par
}
f0 4.47 \par
}
\cf0 Construct the truth table for a 4-input XOR gate.
i Ans. }\par
}
puts \par
}
s17 \cf0 C
\fi20 {\b0\i0 \fs17 0 }
{\b0\i0 0 }
{\b0\i0 0 }
\fi20 {\b0\i0 0 }
{\b0\i0 1 }
{\b0\i0 1 }
{\b0\i0 1 }
\fi20 {\b0\i0 1 }\par
}
s17 \cf0 B
{\b0\i0 \fs17 0 }
{\b0\i0 0 }
{\b0\i0 1 }
{\b0\i0 1 }
{\b0\i0 0 }
{\b0\i0 0 }
{\b0\i0 1 }
{\b0\i0 1 }\par
}
s17 \cf0 D
\fi33 {\b0\i0 \fs17 0 }
\fi33 {\b0\i0 0 }
\fi33 {\b0\i0 0 }
\fi33 {\b0\i0 0 }

\fi33 {\b0\i0 0 }
\fi33 {\b0\i0 0 }
\fi33 {\b0\i0 0 }
\fi33 {\b0\i0 0 }\par
}
s17 \cf0 A
{\b0\i0 \fs17 0 }
{\b0\i0 1 }
{\b0\i0 0 }
{\b0\i0 1 }
{\b0\i0 0 }
{\b0\i0 1 }
{\b0\i0 0 }
{\b0\i0 1 }\par
}
utput
27 {\fs18 Y }
37 0
49 {\fs16 1 }
49 {\fs17 1 }
37 0
49 {\fs16 1 }
37 0
37 0
51 1 \par
}
puts \par
}
s17 \cf0 C
\fi30 {\b0\i0 0 }
\fi34 {\b0\i0 0 }
\fi40 {\b0\i0 0 }
\fi30 {\b0\i0 0 }
\fi34 {\b0\i0 1 }
\fi34 {\b0\i0 1 }
\fi34 {\b0\i0 1 }
\fi34 {\b0\i0 1 }\par
}
s17 \cf0 B
\fi27 {\b0\i0 0 }
\fi31 {\b0\i0 0 }
\fi35 {\b0\i0 1 }
\fi27 {\b0\i0 1 }
\fi31 {\b0\i0 0 }
\fi31 {\b0\i0 0 }
\fi31 {\b0\i0 1 }
\fi29 {\b0\i0 1 }\par
}
s17 \cf0 D
\fi43 {\b0\i0 1 }
\fi47 {\b0\i0 1 }
\fi56 {\b0\i0 1 }
\fi43 {\b0\i0 1 }
\fi47 {\b0\i0 1 }
\fi47 {\b0\i0 1 }
\fi47 {\b0\i0 1 }
\fi50 {\b0\i0 1 }\par
}
s17 \cf0 A
\fi24 {\b0\i0 0 }
\fi28 {\b0\i0 1 }
\fi30 {\b0\i0 0 }
\fi24 {\b0\i0 1 }
\sl-260 \b\i \f20 \fs17 \cf0

\sl-255 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-337 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-337 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-337 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-254 \b\i \f20 \fs17 \cf0
\sl-260 \b\i \f20 \fs17 \cf0
\sl-255 \b\i \f20 \fs17 \cf0
\fi28 {\b0\i0 0 }
\fi28 {\b0\i0 1 }
\fi28 {\b0\i0 0 }
\fi24 {\b0\i0 1 }\par
}
utput
\fi227 {\b\i Y }
52 {\fs16 1 }
36 0
36 0
52 {\fs16 1 }
36 0
48 {\fs16 1 }
52 1
36 0 \par
}
cf0 4.48 \par
}
What would the pulse train at the output{\fs16 of} the XOR gate sho
wn in Fig. 4-38 look like? \par
}
fs17 \cf0 Ans.{\b0\i0
pulse}{\b0\i0 \fs16 a}{\b0\i0 \f10 \fs13 =}{\b0\i0
\fs17 0 }
0 \fi540 {\b0\i0 pulse}{\fs17 b}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 1 }\par
}
ulse{\fs16 c}{\f10 \fs14 =}{\fs16 1 }
e{\b\i \fs17 d}{\f10 \fs14 =}{\fs16 1 }\par
}
ulse e{\dn006 \f10 \fs11 =} 0
e{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =} 0 \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 0
e{\fs17 h}{\dn006 \f10 \fs11 =} 1 \par
}
\par
}

s15 \cf0 h \par
}
15 \cf0 g \par
}
15 \cf0 f \par
}
15 \cf0 e \par
}
s15 \cf0 d \par
}
15 \cf0 c \par
}
s15 \cf0 b \par
}
s15 \cf0 a \par
}
\cf0 Fig.{\f10 \fs15 4-38}{\b0 \fs17
}
. 41 \par
}
}
8 \cf0 65 \par
}
f0 4.49 \par
}
\cf0 Write{\f10 \fs19 -~the Boolean expres}s i on for a 4-input XNOR gate
.
i \fs17 Am.}{\b\i \fs17
A}{\b\i \fs17 @}{\b\i \fs17 B}{\b\i \fs17 @}{\b\i
\fs17 C}{\b\i \fs17 @}{\b\i \fs17 D}{\b\i \fs17 =}{\b\i \fs17 Y }
cf0 \fi30 Draw the logic symbol for a 4-input XNOR gate.{\b\i \fs17
Ans.}
See Fig. 4-39. \par
}
f0 4.50 \par
}
\cf0 Fig.{\f10 \fs15 4-39}{\fs17
A}{\b0 4-input}{\b0 XNOK}{\b0 gate }\par
}
cf0 4.5 1{\b0 \f20 \fs17
Construct}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 tr
uth}{\b0 \f20 \fs17 table}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 a}{\b0 \f20 \
fs17 4-input}{\b0 \f20 \fs17 XNOR}{\b0 \f20 \fs17 gate. }

i576 {\i \f20 \fs17 Am. }
0 \fi2557 {\b0 \f20 \fs17 Inputs}{\b0 \f20 \fs17
output }\par
}
puts \par
}
s17 \cf0 C
\fi30 {\b0\i0 0 }
\fi26 {\b0\i0 \fs17 0 }
\fi26 {\b0\i0 \fs17 0 }
\fi22 {\b0\i0 \fs17 0 }
\fi26 {\b0\i0 \fs17 1 }
\fi24 {\b0\i0 \fs17 1 }
\fi22 {\b0\i0 \fs17 1 }
\fi22 {\b0\i0 \fs17 1 }\par
}
s17 \cf0 B
\fi29 {\b0\i0 0 }
\fi22 {\b0\i0 \fs17 0 }
\fi22 {\b0\i0 \fs17 1 }
{\b0\i0 \fs17 1 }
\fi20 {\b0\i0 \fs17 0 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 1 }\par
}
17 0 }
17 0 }
17 0 }
17 0 }
17 0 }
\sl-260 \f20 \fs17 \cf0 {\fs

\sl-256 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
17 0 }
17 0 }\par
}
17 0 }
17 0 }
17 0 }
17 1 }
17 1 }
17 1 }
17 1 }\par
}
\sl-260 \f20 \fs17 \cf0 {\fs
17 0 }
17 1 }
17 1 }
17 0 }
17 0 }
17 1 }
17 1 }\par
}
\sl-260 \f20 \fs17 \cf0 {\fs
17 1 }
17 0 }
17 1 }
17 0 }
17 1 }
17 0 }
17 1 }\par
}
s17 \cf0 D
\fi42 {\b0\i0 1 }
\sl-260 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-256 \f20 \fs17 \cf0 {\fs

\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\sl-256 \f20 \fs17 \cf0 {\fs
\sl-259 \f20 \fs17 \cf0 {\fs
\sl-253 \f20 \fs17 \cf0 {\fs
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-337 \b\i \f20 \fs17 \cf0
\sl-256 \b\i \f20 \fs17 \cf0
\fi40 {\b0\i0 \fs17 1 }

\fi40 {\b0\i0 \fs17 1 }
\fi36 {\b0\i0 \fs17 1 }
\fi41 {\b0\i0 \fs17 1 }
\fi40 {\b0\i0 \fs17 1 }
\fi36 {\b0\i0 \fs17 1 }
\fi36 {\b0\i0 \fs17 1 }\par
}
s17 \cf0 A
\fi27 {\b0\i0 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }
{\b0\i0 \fs17 0 }
{\b0\i0 \fs17 1 }\par
}
f0 4.52 \par
}
hat would{\fs17 the} pulse train at the output of the XNOR gate shown
in Fig. 4-40 look like? \par
}
s17 \cf0 Ans.{\b0\i0 \fs17
pulse}{\b0\i0 \fs16 a}{\b0\i0 \f10 \fs13 =}{\
b0\i0 \fs17 1 }
\fi538 {\b0\i0 \fs17 pulse}{\b0 \fs17 b}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17
0 }\par
}
lse{\b\i \fs16 c}{\f10 \fs13 =}{\fs16 0 }
{\b\i \fs17 d}{\f10 \fs13 =} 1 \par
}
lse{\fs16 e}{\f10 \fs13 =} 0
{\b\i \f30 \fs19 f}{\b\i \f30 \fs19 =} 1 \par
}
lse{\fs15 g}{\f10 \fs13 =}{\fs17 1 }
{\i h}{\dn006 \f10 \fs11 =} 0 \par

}
{\phpg\posx5863\pvpg\posy9292\absw159\absh272 \f10 \fs23 \cf0 \f10 \fs23 \cf0 \\
\par
}
s13 \cf0 h \par
}
s13 \cf0 g \par
}
13 \cf0 f \par
}
s13 \cf0 e \par
}
s13 \cf0 d \par
}
s13 \cf0 c \par
}
s13 \cf0 b \par
}
s13 \cf0 a \par
}
\cf0 Fig.{\fs17 4-40}{\b0
Pulse-train}{\b0 problem }\par
}
cf0 4.53 \par
}
\cf0 Given an{\fs17 OR} gate and inverters, draw a logic diagram that
will perform the 3-input NAND function.
\i \fs17 Ans.}
See Fig.{\fs17 4-41. }\par
}
\cf0 Fig.{\f10 \fs15 4-41}{\b0
3-input}{\b0 NAND}{\b0 function }\par
}
0 66 \par
}
}
AP. 4 \par
}
f0 4.54 \par
}
\cf0 Given a NOR gate and inverters, draw a logic diagram that will per
form the 3-input AND function.

i Ans.}
See Fig. 4-42. \par
}
\cf0 Fig.{\f10 \fs15 4-42}{\b0 \fs17
3-input}{\b0 \fs17 AND}{\b0 \fs17 fun
ction }\par
}
f0 4.55 \par
}
\cf0 Given a NOR gate and inverters, draw a logic diagram that will per
form the 5-input OR function.
i Ans.}
See Fig. 4-43. \par
}
13 \cf0 A
{\f20 \fs15 B }
{\b0 \f20 \fs23 c }
{\f20 \fs14 D }
{\f20 \fs15 E }\par
}
cf0 '4{\b0 \f10 \fs20 +}{\i\dn006 \f10 \fs13 B }\par
}
\b \f30 \fs15 C}{\b \f30 \fs15 '}{\b \f30 \fs15 + }\par
}
15 \cf0 fl{\b0\i0 \f10 \fs12 f}{\b0 \f20 \fs14
E}{\b0\i0 \f10 \fs10
=}{\
f20 \fs14 Y }\par
}
\cf0 Fig.{\f10 \fs15 4-43}{\b0 \fs17
5-input}{\b0 \fs17 OR}{\b0 \fs17 fun
ction }\par
}
f0 4.56 \par
}
raw a logic diagram for the Boolean expression{\i \f30 \fs23 2.B}{\i }{\f10
\fs23 -}{\b \fs17 C }
s, and an OR gate.{\b\i \fs17
Ans.}
See Fig. 4-44. \par
}
16 \cf0 + A \par
}
17 \cf0 + A{\b0\i0 \f10 \fs19 -}{\b0 \fs17 B}{\b0\i0 \f10 \fs23 -}{\b0\i0 \fs
29 c }\par
}
{\phpg\posx6443\pvpg\posy8022\absw36\absh85 \f10 \fs6 \cf0 \f10 \fs6 \cf0 * \par
}

24 \cf0 B{\b0\i0 \f10 \fs23 -}{\b0\i0 \f20 \fs17 C }\par
}
{\i \f20 \fs17 Y.}{\f20 \fs17 Use}{\f20 \fs17 inverters,}{\f20 \fs17 AND }\
par
}
14 \cf0 A \par
}
s15 \cf0 B \par
}
s15 \cf0 Y \par
}
s16 \cf0 C \par
}
- \par
}
\cf0 c \par
}
\cf0 Fig.{\f10 \fs15 4-44}{\b0 \fs17
An}{\b0 \fs17 AND-OR}{\b0 \fs17 log
ic}{\b0 \fs17 circuit }\par
}
cf0 4.57 \par
}
Redraw the logic diagram for Prob. 4.56 by using three 2-input NAND
gates and{\fs17 four} 3-input NAND
\par}{\phpg\posx1461\pvpg\posy12575\absw8264\absh909 \sl-223 \f20 \fs17 \cf0 gat
es.{\b\i
Ans.}
See{\b Fig.} 4-45.
Write the Boolean expression for the circuit shown in Fig. 4-46. \par
}
fs17 \cf0 Ans.
A{\b0\i0 \f10 \fs27 -}{\b0 \fs17 B}{\b0\i0 \f10 \fs26 +}{\f
30 \fs33 x* }\par
}
{\phpg\posx2987\pvpg\posy13692\absw36\absh85 \f10 \fs6 \cf0 \f10 \fs6 \cf0 * \pa
r
}
s18 \cf0 C{\b0\i0\dn006 \f10 \fs13 =}{\f20 \fs17 Y }\par
}
cf0 4.58 \par
}
0 ('{\f63 \u8364\'3f}\{AP.{\b0 \f10 \fs20 4 }\par
}

0 68 \par
}
}
AP.{\f10 \fs15 4 }\par
}
f0 4.60 \par
}
\fs18 \cf0 If{\b0 \fs17 switches}{\i \fs17 A}{\i \fs17 ,}{\i \fs17 B,}{\b0 \
fs17 and}{\i \f30 \fs18 C}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{
\fs17 4-46}{\b0 \fs17 are}{\b0 \fs17 in}{\b0 \fs17 the}{\i \fs15 up}{\b0 \
fs17 position}{\b0 \fs17 (logical}{\b0 \fs20 11,}{\b0 \fs17 the}{\b0 \fs17
output}{\b0 \fs17 LED}{\b0 \fs17 will}{\b0 \fs17 be }
fi22 {\b0 \fs17 (lit,not}{\b0 \fs17 lit). }
\i \fs17 Ans.}{\b0 \fs17
When}{\b0 \fs17 all}{\b0 \fs17 inputs}{\b0 \fs17
are}{\b0 \fs17 1,}{\b0 \fs17 the}{\b0 \fs17 output}{\b0 \fs17 of}{\b0 \fs1
7 the}{\b0 \fs17 circuit}{\b0 \fs17 will}{\b0 \fs17 be}{\b0 \fs17 1}{\b0
\fs17 according}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 truth}{\b0 \fs17 t
able}{\b0 \fs17 and}{\b0 \fs17 the}{\b0 \fs17 output }
fi24 {\b0 \fs17 LED}{\b0 \fs17 will}{\b0 \fs17 be}{\b0 \fs17 lit. }\par
}
\fs17 \cf0 The{\b0 \fs17 unique}{\b0 \fs17 output}{\b0 \fs17 for}{\b0 \fs17
the }
\i \fs17 Ans.}{\b0 \fs17
NAND }
f0 \fi24 {\b0 \fs17 The}{\b0 \fs17 unique}{\b0 \fs17 output}{\b0 \fs17 for}
{\b0 \fs17 the }
\i \fs17 Ans.}{\b0 \fs17
NOR }\par
}
e \par
}
ogic gate is a{\fs17 LOW} when all inputs are HIGH. \par
}
f0 4.61 \par
}
f0 4.62 \par
}
ogic gate is a HIGH when all inputs are LOW. \par
}
f0 4.63 \par
}
ogic gate generates a HIGH output when an{\b\i \fs17 odd}{\b\i \fs17 num
ber} of inputs are HIGH. \par

}
s17 \cf0 Ans.{\b0\i0 \fs17
exclusive-OR}{\b0\i0 \fs17 or}{\b0\i0 \fs17 XO
R. }\par
}
{\b \fs33 Simplifying}{\b \fs33 Logic}{\b \fs33 Circuits:}{\b \fs33 Mapping }
\par
}
cf0 5-1{\f20 \fs18
INTRODUCTION }
i382 {\b0 \f20 \fs18 Consider}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 Boolean}{
\b0 \f20 \fs18 expression}{\i \f20 \fs19
A}{\b0 \fs27 - }\par
}
37 \cf0 +x. \par
}
\cf0 B{\b \fs18 +}{\b \fs18 A}{\b .}{\b B}{\i0 \f10 \fs14 =}{\b \fs19 Y,}{
\i0 \fs18 a}{\i0 \fs18 logic}{\i0 \fs18 diagram}{\i0 \fs18 for}{\i0 \fs1
8 which}{\i0 \fs18 is}{\i0 \fs18 in }\par
}
ig.{\b\i \fs18 5-la.} Note that{\fs19 six} gates must be used to implement
this logic circuit, which performs the logic
\par}{\phpg\posx863\pvpg\posy3526\absw9153\absh1076 \sl-237 \f20 \fs18 \cf0 deta
iled in the truth table (Fig.{\fs19 5-lc).} From examination of the trut
h table, it is determined that a
i \fs18 single}{\b\i \fs18 2-input}{\b\i \fs18 OR}{\b\i \fs18 gate} will per
form the function. It is found that the{\fs19 OR} gate shown in Fig.{\fs18 516} will
\par}{\phpg\posx863\pvpg\posy3526\absw9153\absh1076 \sl-237 \f20 \fs18 \cf0 be t
he simplest method of performing this logic. The logic circuits in Fig.{\b\i \f
s18 5-la} and{\fs18 b} perform exactly
same logic function. Obviously a designer would choose the simplest,
least expensive circuit, \par
}
{\phpg\posx877\pvpg\posy4722\absw8420\absh219 \f20 \fs18 \cf0 \f20 \fs18 \cf0 sh
own in Fig.{\fs18
5-lb.} It has been shown that the unsimpl
ified Boolean expression{\b\i \fs19
(}{\b\i \fs19 A }\par
}
f0 A.{\b\dn006 \f20 \fs19 B }\par
}
}
\par
}
s19 \cf0 + A{\fs19 B}{\b0\i0 \f10 \fs14 =}{\fs19 Y}{\fs19 )}{\b0\i0 \fs18
could}{\b0\i0 \fs18 be}{\b0\i0 \fs18 simplified}{\b0\i0 \fs18 to}{\f10 \fs17
A}{\b0\i0 \f10 \fs29 +} R{\b0\i0 \f10 \fs14 =}{\b0 \fs19 Y.}{\b0\i0 \fs18
The}{\b0\i0 \fs18 simplification}{\b0\i0 \fs18 was}{\b0\i0 \fs18 done}{\b0\
i0 \fs18 by}{\b0\i0 \fs18 simple}{\b0\i0 \fs18 examina- }\par
}
{\phpg\posx877\pvpg\posy5204\absw8975\absh423 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ti
on of the truth table and recognizing the{\fs19 OR} pattern. Many Bo
olean expressions can be greatly
\par}{\phpg\posx877\pvpg\posy5204\absw8975\absh423 \sl-230 \f20 \fs18 \cf0 simpl
ified. Several systematic methods{\fs19 of} simplification will be examined in
this chapter. \par
}
4 \cf0 A \par
}
f0 1 \par
}
14 \cf0 A \par
}
cf0 \par}{\phpg\posx2629\pvpg\posy6691\absw160\absh611 \sl-149 \f10 \fs19 \cf0 {\b\i
\fs14 A }
\f20 \fs15 B }\par
}
}
cf0 Inputs \par
}
s16 \cf0 B
\cf0 {\i0 \fs17 0 }
{\b0\i0 \f10 \fs16 0 }
\fi38 {\b0\i0 \f10 \fs16 1 }
\fi37 {\b0\i0 \f10 \fs16 1 }\par
}
s16 \cf0 A
\cf0 {\i0 \fs17 0 }
{\b0\i0 \f10 \fs16 1 }
{\b0\i0 \f10 \fs16 0 }
{\b0\i0 \f10 \fs16 1 }\par
}
14 \cf0 AB \par
}
\i \f20 \fs16 AB}{\fs22 + }\par
}

15 \cf0 AB{\b0\i0 \f10 \fs11
=}{\fs15 Y }\par
}
I t \par
}
{\phpg\posx2879\pvpg\posy8368\absw4392\absh1230 \b\i \f20 \fs106 \cf0 \b\i \f20
\fs106 \cf0 "ay \par
}
\cf0 (a){\fs15 Unsimplified}{\fs15 logic}{\fs15 circuit }\par
}
\f20 \fs15 \cf0 B
\cf0 \fi2044 {\fs15 (b)}{\i0 Simplified}{\i0 'logiccircuit }
\cf0 \fi4079 {\i0 \fs16 Fig.}{\i0 \fs16 5-1 }
\cf0 \fi381 {\b0\i0 \fs18 In}{\b0\i0 \fs18 this}{\b0\i0 \fs18 chapter}{\b0\i0
\fs18 simple}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 gates}{\b0\i0 \fs18 will}{\b0
\i0 \fs18 be}{\b0\i0 \fs18 used}{\b0\i0 \fs18 to}{\b0\i0 \fs18 implement}{\b
0\i0 \fs18 combinational}{\b0\i0 \fs18 logic.}{\b0\i0 \fs18 Other}{\b0\i0 \fs
18 techniques }
\fi22 {\b0\i0 \fs18 also}{\b0\i0 \fs18 are}{\b0\i0 \fs18 commonly}{\b0\i0 \fs
18 used}{\b0\i0 \fs18 for}{\b0\i0 \fs18 simplifying}{\b0\i0 \fs18 more}{\b
0\i0 \fs18 complex}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 problems.}{\b0\i0 \fs18
They}{\b0\i0 \fs18 include}{\b0\i0 \fs18 the}{\b0\i0 \fs18 use}{\b0\i0 \fs
18 of}{\fs18 data }
{\fs18 selectors}{\b0\i0 \fs18 (multiplexers),}{\fs18 decoders,}{\fs19 P}{\f
s19 U}{\fs19 S}{\b0\i0 \fs18 (programmable}{\b0\i0 \fs18 logic}{\b0\i0 \fs18
arrays),}{\fs18 ROMs}{\b0\i0 \fs18 (read-only}{\b0\i0 \fs18 memories)}{\b0\
i0 \fs18 and }
{\fs19 PROMS}{\b0\i0 \fs18 (programmable}{\b0\i0 \fs18 read-only}{\b0\i0 \fs
18 memories). }
\cf0 {\i0 \fs18 5-2}{\i0 \fs18
SUM-OF-PRODUCTSBOOLEAN}{\i0 \fs18 EXPRESSIONS
}
\fi371 {\b0\i0 \fs18 It}{\b0\i0 \fs18 is}{\b0\i0 \fs18 customary}{\b0\i0 \fs
18 when}{\b0\i0 \fs18 starting}{\b0\i0 \fs18 a}{\b0\i0 \fs18 logic-desig
n}{\b0\i0 \fs18 problem}{\b0\i0 \fs18 to}{\b0\i0 \fs18 first}{\b0\i0 \fs18
construct}{\b0\i0 \fs18 a}{\b0\i0 \fs18 truth}{\b0\i0 \fs18 table.}{\b0\
i0 \fs18 The}{\b0\i0 \fs18 table }
{\b0\i0 \fs18 details}{\b0\i0 \fs18 the}{\b0\i0 \fs18 exact}{\b0\i0 \fs18 op
eration}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 digital}{\b0\i0 \fs
18 circuit.}{\b0\i0 \fs18 Consider}{\b0\i0 \fs18 the}{\b0\i0 \fs18 truth}{\b
0\i0 \fs18 table}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\fs18 5-2a.}{\b0\i0
\fs18 It}{\b0\i0 \fs18 contains}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 three}{\b0\i0 \fs18 variables}{\b0\i0 \fs18 C,}{\b0 \fs19 B,
}{\b0\i0 \fs18 and}{\f10 \fs18 A.}{\b0\i0 \fs18 Note}{\b0\i0 \fs18 that}{\b
0\i0 \fs18 only}{\b0\i0 \fs18 two}{\b0\i0 \fs18 combinations}{\b0\i0 \fs18
of}{\b0\i0 \fs18 variables}{\b0\i0 \fs18 will}{\b0\i0 \fs18 generate}{\b0\i0
\fs18 a}{\b0\i0 \fs18 1}{\b0\i0 \fs18 output. }
{\b0\i0 \fs18 These}{\b0\i0 \fs18 combinations}{\b0\i0 \fs18 are}{\b0\i0 \fs1

8 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 the}{\b0\i0 \fs18 shaded}{\b0\i0 \fs1
8 second}{\b0\i0 \fs18 and}{\b0\i0 \fs18 eighth}{\b0\i0 \fs18 lines}{\b0\i0
\fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 truth}{\b0\i0 \fs18 table.}{\b0\i0
\fs18 From}{\b0\i0 \fs18 line}{\fs19 2, }
{\b0\i0 \fs18 we}{\b0\i0 \fs18 say}{\b0\i0 \fs18 that}{\b0\i0 \fs18 "a}{\b0\
i0 \fs18 not}{\b0\i0 \fs18 C}{\i0 \fs18 AND}{\b0\i0 \fs18 a}{\b0\i0 \fs18
not}{\b0 \fs19 B}{\b0\i0 \fs18 AND}{\b0\i0 \fs18 an}{\fs19 A}{\b0\i0 \f10
\fs23 -}{\b0\i0 \f10 \fs23 -inpu}{\b0\i0 \fs18 t}{\b0\i0 \fs18 will}{\b0\i0
\fs18 generate}{\b0\i0 \fs18 a}{\b0\i0 \fs18 1}{\b0\i0 \fs18 output."}{\b0\i0
\fs18 This}{\b0\i0 \fs18 is}{\b0\i0 \fs18 shown}{\b0\i0 \fs18 near}{\b0\i0
\fs18 the }
{\b0\i0 \fs18 right}{\b0\i0 \fs18 side}{\b0\i0 \fs18 of}{\b0\i0 \fs18 line
}{\b0\i0 \fs19 2}{\b0\i0 \fs18 as}{\b0\i0 \fs18 the}{\b0\i0 \fs18 Boolean}{
\b0\i0 \fs18 expression}{\b0\i0 \fs18 C}{\b0 \fs18 B}{\fs18 .A.}{\b0\i0 \
fs18 The}{\b0\i0 \fs18 other}{\b0\i0 \fs18 combination}{\b0\i0 \fs18 of}{\b
0\i0 \fs18 variables}{\b0\i0 \fs18 that}{\b0\i0 \fs18 will }\par
}
{\phpg\posx5149\pvpg\posy13485\absw36\absh101 \f10 \fs8 \cf0 \f10 \fs8 \cf0 * \p
ar
}
{\phpg\posx855\pvpg\posy13616\absw9060\absh755 \f20 \fs18 \cf0 \f20 \fs18 \cf0 g
enerate a 1is shown in line{\fs18 8} of the truth table. Line{\fs18 8} reads a
s "a{\fs19 C} AND a{\i \fs19 B} AND an{\b\i \fs19 A} input will
\par}{\phpg\posx855\pvpg\posy13616\absw9060\absh755 \sl-244 \f20 \fs18 \cf0 gene
rate a 1output." The Boolean expression for line{\fs18 8} is shown at the ri
ght as{\b\i \fs18 C}{\i \fs19
B}{\b\i \fs19 .A.} These{\fs18 two }
314 {\b 69 }\par
}
ar
}
\par
}
\cf0 Output
f0 \fi243 {\i \fs17 Y }
f0 \fi230 {\fs17 0 }
fi253 {\f10 \fs15 1 }
fi260 {\f10 \fs15 1 }
fi260 {\fs17 1 }\par
}
s15 \cf0 (c){\i0 \fs15 Truth}{\i0 \fs15 table}{\i0 \fs15 for}{\i0 \fs15 OR}{
\i0 \fs15 function }\par
}
par
}
{\phpg\posx3361\pvpg\posy583\absw3791\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 SI

MPLIFYING LOGIC CIRCUITS: MAPPING \par
}
AP.{\fs17 5 }\par
}
0 \fs17 \cf0 Fig.{\fs16 5-2 }
f0 {\b0 \fs18 possible}{\b0 \fs18 combinations}{\b0 \fs18 are}{\b0 \fs18 then
}{\b0 \fs18 ORed}{\b0 \fs18 together}{\b0 \fs18 to}{\b0 \fs18 form}{\b0 \fs1
8 the}{\b0 \fs18 complete}{\b0 \fs18 Boolean}{\b0 \fs18 expression}{\b0 \fs1
8 for}{\b0 \fs18 the}{\b0 \fs18 truth }
fi7273 {\b0\dn006 \f10 \fs15 -}{\b0 \f10 \fs15
- }
\b0 \fs18 table.}{\b0 \fs18 The}{\b0 \f10 \fs19 -}{\b0 \fs18 complete}{\b0 \f
s18 Boolean}{\b0 \fs18 expression}{\b0 \fs18
is}{\b0 \fs18 shown}{\b0 \
fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs19 5-2b}{\b0 \fs18
as}{\b0\i \fs18
C}{\b0\i \fs19 B}{\i \f10 \fs18 .A}{\b0\i \fs18
C}{\b0\i \fs19 .B}{\i \f
s18 .A}{\b0\i \fs19
Y.}{\b0 \fs18 The }
\b0\i \fs19 C}{\i \fs19 .}{\i \fs19 B}{\i \fs19 .A}{\b0 \f10 \fs28 +}{\b0\i
\fs19 C}{\b0\i \fs19 .B}{\i \fs19 -}{\i \fs19 A}{\b0\dn006 \f10 \fs13 =}{\b
0\i \fs19 Y}{\b0 \fs18
in}{\b0 \fs18 Fig.}{\b0\i \fs19 5-2b}{\b0 \fs18
is}{\b0 \fs18 sometimes}{\b0 \fs18 called}{\b0 \fs18
a}{\b0\i \fs18
sum-of-products}{\b0 \fs18 form}{\b0 \fs18 of}{\b0 \fs18
a}{\b0 \fs18 B
oolean }
\b0 \fs18 expression.}{\b0 \fs18 Engineers}{\b0 \fs18 also}{\b0 \fs18 call}{\
b0 \fs18 this}{\b0 \fs18 form}{\b0 \fs18 of}{\b0 \fs18 expression}{\b0 \fs18
the}{\b0\i \fs18 mintermform.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 t
his}{\b0 \fs18 expression}{\b0 \fs18 can }
\b0 \fs18 be}{\b0 \fs18 translated}{\b0 \fs18 into}{\b0 \fs18 a}{\b0 \fs18 f
amiliar}{\b0 \fs18 AND-OR}{\b0 \fs18 pattern}{\b0 \fs18 of}{\b0 \fs18 logic}
{\b0 \fs18 gates.}{\b0 \fs18 The}{\b0 \fs18 logic}{\b0 \f10 \fs15 - }\par
}
\par
}
}
{\phpg\posx7371\pvpg\posy5875\absw55\absh103 \f10 \fs7 \cf0 \f10 \fs7 \cf0 + \pa
r
}
\par
}
e logic described by the minterm Boolean expression{\i \fs18 C}{\f10 \fs23 }{\i \fs19 B}{\b\i \f10 \fs17 .A}{\f10 \fs27 + }
\par}{\phpg\posx855\pvpg\posy6634\absw5972\absh523 \sl-242 \f20 \fs18 \cf0 truth
table in Fig.{\i \fs19 5-2a. }\par
}
{\phpg\posx6695\pvpg\posy6500\absw2992\absh425 \f10 \fs15 \cf0 \f10 \fs15 \cf0 {\f20 \fs18
diagram}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\i \f20 \fs19 5-2c}{
\f20 \fs18 performs }
\f20 \fs18 C}{\i \f20 \fs19 B}{\b\i \fs17 .A}{\dn006 \fs11 =}{\i \f20 \fs18
Y}{\f20 \fs18 and}{\f20 \fs18 will}{\f20 \fs18 generate}{\f20 \fs18 the
}\par
}
}
\cf0 It is typical procedure in logic-design work to{\i \fs18 first} co
nstruct a truth table.{\i Second,} a minterm
ean expression is then determined from the truth table.{\i Finally,} t
he AND-OR logic circuit is
\par}{\phpg\posx863\pvpg\posy7217\absw9011\absh1703 \sl-238 \f20 \fs18 \cf0 draw
n from the minterm Boolean expression. This procedure is outlined in t
he sample problem in
{\fs19 5-2. }
{\f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }
{\b \f10 \fs17 5.1}
Write a{\i rninterm} Boolean expression for the trut
h table in Fig.{\i \fs19 5-3. }\par
}
\par
}
f0 I \par
}
s16 \cf0 C
\cf0 {\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs16 0 }
{\b0\i0 \f10 \fs16 0 }
\fi20 {\b0\i0 \f10 \fs16 0 }\par
}
puts
}
16 0 }
16 1 }
16 1 }\par
}
s16 \cf0 A
\cf0 {\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs16 1 }
\sl-220 \f10 \fs15 \cf0 {\fs

\sl-222 \f10 \fs15 \cf0 {\fs
\sl-216 \f10 \fs15 \cf0 {\fs
\f20 \fs16 \cf0 \b\i \f20 \f
\sl-248 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf0

{\b0\i0 \f10 \fs16 0 }
{\b0\i0 \f10 \fs16 1 }\par
}
utput
\fi240 {\b\i \fs16 Y }
\fi238 {\f10 \fs16 0 }
40 {\f10 \fs16 0 }
41 {\f10 \fs16 0 }
66 {\f10 \fs16 1 }\par
}
\f20 \fs16 \cf0 C
\cf0 \fi538 {\b0\i0 \f10 \fs16 1 }
\fi540 {\b0\i0 \f10 \fs16 1 }
\fi542 {\b0\i0 \f10 \fs16 1 }
\fi548 {\b0\i0 \f10 \fs16 1 }
\cf0 {\i0 \fs17 Fig.}{\i0 \fs17 5-3 }\par
}
puts
}
ar
}
s16 \cf0 A
\cf0 {\b0\i0 \f10 \fs16 0 }
{\b0\i0 \f10 \fs16 1 }
{\b0\i0 \f10 \fs16 0 }
\fi23 {\b0\i0 \f10 \fs16 1 }\par
}
I{\f20 \fs17
Output }
\fi403 {\b\i \f20 \fs16 Y }
\fi397 {\f10 \fs16 0 }

397 {\f10 \fs16 0 }
422 {\f10 \fs16 1 }
410 {\f10 \fs16 0 }\par
}
\cf0 Solution:
\fi358 {\b0 \fs21 C}{\b0\dn006 \f10 \fs22 .}{\b0\i \fs17 B}{\i \f10 \fs15 -}{\
i \f10 \fs15 A}{\b0 \f10 \fs27 +}{\b0\i \fs26 c}{\b0\i\dn006 \fs17
B.}{\b0
\f10 \fs19 }{\b0\i \f30 \fs25 -A }\par
}
{\i \f20 \fs16 Y }\par
}
r \par
}
\cf0 CBA{\i0 \f10 \fs26 +}{\fs21 CBZ }\par
}
{\i \f20 \fs17 Y }\par
}
cf0 5.2 \par
}
The Boolean expression developed in Prob.{\fs19 5.1} was a \par
}
This type of expression is also called the
360 {\fs17 This}{\fs17
type}{\fs17
of}{\fs17
Boolean}{\fs17
expressi
on}{\fs21 (C.}{\i \fs17 B}{\b\i \fs17 .}{\b\i \fs17 A}{\f10 \fs26 + }
s17 sum-of-products}{\fs17 form. }\par
}
(maxterm, minterm) expression. \par
}
8 \cf0 (product-of-sums, sum-of-products) form.
{\i \fs17 C}{\i \fs17 -}{\i \fs17 B}{\i \f30 \fs25 .A=}{\i\dn006 \fs17 ) }\p
ar
}
\cf0 Y{\i0 \fs17
is}{\i0 \fs17
called}{\i0 \fs17
the}{\i0 \fs17
m
interm}{\i0 \fs17
form}{\i0 \fs17
or}{\i0 \fs17
the }\par
}
.{\f10 51 }\par
}

}
f0 71 \par
}
f0 5.3 \par
}
iagram a logic circuit that will perform the logic in the truth table in Fig.
{\fs19 5-3. }
\fs17 Solution: }
60 {\b\i \fs17 See}{\fs17 Fig.}{\b \f10 \fs16 5-4. }\par
}
s15 \cf0 - - C * B . A + C * B . A =
Y \par
}
\cf0 Fig.{\fs17 5-4}{\b0 \fs17
Logic-diagram}{\b0 \fs17 solution }\par
}
f0 5.4 \par
}
rite a sum-of-products Boolean expression for the truth table in Fig.{\fs19 5
-5. }
}
s25 \cf0 C.B-X+{\f20 \fs23 F}{\f20 \fs23 B}{\f20 \fs23 .}{\f20 \fs23 A }\par
}
16 \cf0 + c . & A \par
}
\b\i \f20 \fs17 Y }\par
}
puts \par
}
\par
}
tput \par
}
\par
}
puts \par
}
\f20 \fs17
Output }\par
}
{\phpg\posx3441\pvpg\posy8140\absw52\absh66 \f10 \fs5 \cf0 \f10 \fs5 \cf0 '~ \pa
r
}
cf0 0 \par
}
cf0 1 \par
}
cf0 0 \par
}
cf0 1 \par
}
cf0 1 \par
}
cf0 0 \par
}
cf0 0 \par
}
cf0 1 \par
}
cf0 1 \par
}
\fs16 \cf0 1
0 {\f20 \fs17 Fig.}{\f20 \fs17 5-5 }\par
}
cf0 1 \par
}
cf0 1 \par
}
7 \cf0 5.5 \par
}
iagram a logic circuit that will perform the logic in the truth table in Fig.
{\fs19 5-5. }
\fs17 Solution: }
60 {\b\i \fs17 See}{\fs17 Fig.}{\b\i \f10 \fs16 5-6. }\par
}
\cf0 c \par
}
s13 \cf0 A \par
}
s13 \cf0 ={\f20 \fs15
Y }\par
}

\cf0 Fig.{\fs16 5-6}{\b0 \fs17
Logic-diagram}{\b0 \fs17 solution }\par
}
0 72 \par
}
}
f0 [CHAP.{\b0\i \fs17 5 }\par
}
\cf0 5-3{\f20 \fs19
PRODUCT-OF-SUMS}{\f20 \fs19 BOOLEAN}{\f20 \fs19 EXPRES
SIONS }
fi370 {\b0 \f20 \fs19 Consider}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 OR}{\b0 \
f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19
Fig.}{\b0\i \f20 \fs19 5-7b.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 Boolean}
{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 this}{\b0 \
f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 can}{\b0 \f20 \fs19
be }
\b0 \f20 \fs19 written}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 two}{\b0 \f20 \fs19
forms,}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 was}{\b0 \f20 \fs19 observed}{\b0
\f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 introductory}{\b0 \f20 \f
s19 section.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 minterm}{\b0 \f20 \fs19 Boo
lean}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 is }
\b0 \f20 \fs19 developed}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 the}{\b0 \f20 \f
s19 output}{\b0 \f20 \fs19 1s}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \
f20 \fs19 truth}{\b0 \f20 \fs19 table.}{\b0 \f20 \fs19 Each}{\b0 \f20 \fs19
1}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 output}{\b0 \f20 \
fs19 column}{\b0 \f20 \fs19 becomes}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 term}{
\b0 \f20 \fs19 to}{\b0 \f20 \fs19 be }
\b0 \f20 \fs19 ORed}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 mi
nterm}{\b0 \f20 \fs19 expression.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 minter
m}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 this}{\b0 \
f20 \fs19 truth}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 giv
en}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0\i \f20 \fs19 5-7c}{\b0 \f20 \
fs19 as }
fi3386 {\i \f20 \fs24 B-A+B.A+B.A=Y }\par
}
0 \fs17 \cf0 Fig.{\f10 \fs16 5-7 }
f0 \fi360 {\b0 \fs19 The}{\b0 \fs19 truth}{\b0 \fs19 table}{\b0 \fs19 in}{\b0
\fs19 Fig.}{\b0\i \fs19 5-7}{\b0 \fs19 can}{\b0 \fs19 also}{\b0 \fs19 be}{
\b0 \fs19 described}{\b0 \fs19 by}{\b0 \fs19 using}{\b0 \fs19 a}{\b0\i \fs19
rnaxterrn}{\i \f30 \fs18 form}{\b0 \fs19 of}{\b0 \fs19 Boolean}{\b0 \fs19
expression. }
\b0 \fs19 This}{\b0 \fs19 type}{\b0 \fs19 of}{\b0 \fs19 expression}{\b0 \fs19
is}{\b0 \fs19 developed}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19 OS}{\b0
\fs19 in}{\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 column}{\b0 \fs19 of}{
\b0 \fs19 the}{\b0 \fs19 truth}{\b0 \fs19 table.}{\b0 \fs19 For}{\b0 \fs19
each}{\b0 \fs19 0}{\b0 \fs19 in }

\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 column,}{\b0 \fs19 an}{\b0 \fs19
ORed}{\b0 \fs19 term}{\b0 \fs19 is}{\b0 \fs19 developed.}{\b0 \fs19 Note}
{\b0 \fs19 that}{\b0 \fs19 the}{\b0\i \fs19 input}{\b0\i \fs19 variables
}{\b0\i \fs19 are}{\b0\i \fs19 inverted}{\b0\i \fs19 and}{\b0\i \fs19 the
n }
\i \fs19 ORed.}{\b0 \fs19 The}{\b0 \fs19 maxterm}{\b0 \fs19 Boolean}{\b0 \
fs19 expression}{\b0 \fs19 for}{\b0 \fs19 this}{\b0 \fs19 truth}{\b0 \fs
19 table}{\b0 \fs19 is}{\b0 \fs19 given}{\b0 \fs19 in}{\b0 \fs19 Fig.}
{\b0\i \fs19 5-7a.}{\b0 \fs19 The}{\b0 \fs19 maxterm }
\b0 \fs19 expression}{\b0 \fs19 for}{\b0 \fs19 the}{\b0 \fs19 OR}{\b0 \fs19
truth}{\b0 \fs19 table}{\b0 \fs19 is}{\b0 \fs19 shown}{\b0 \fs19 as}{\b0\i
\fs19 B}{\i \fs19 +}{\i \fs19 A}{\b0 \f10 \fs14 =}{\i \fs19 Y.}{\b0 \fs19
This}{\b0 \fs19 means}{\b0 \fs19 the}{\b0 \fs19 same}{\b0 \fs19 thing}{\b0
\fs19 as}{\b0 \fs19 the}{\b0 \fs19 familiar }
\b0 \fs19 OR}{\b0 \fs19 expression}{\i \fs19 A}{\b0 \f10 \fs29 +}{\i \fs19 B
}{\b0 \f10 \fs14 =}{\i \fs19 Y.}{\b0 \fs19 For}{\b0 \fs19 the}{\b0 \fs19 t
ruth}{\b0 \fs19 table}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \fs19 5-7,}{\b0 \
fs19 the}{\b0 \fs19 maxterm}{\b0 \fs19 Boolean}{\b0 \fs19 expression}{\b0 \f
s19 turns}{\b0 \fs19 out }
\b0 \fs19 to}{\b0 \fs19 be}{\b0 \fs19 the}{\b0 \fs19 simplest.}{\b0 \fs19
Both}{\b0 \fs19 the}{\b0 \fs19 minterm}{\b0 \fs19 and}{\b0 \fs19 maxterm
}{\b0 \fs19 expressions}{\b0 \fs19 accurately}{\b0 \fs19 describe}{\b0 \fs1
9 the}{\b0 \fs19 logic}{\b0 \fs19 of}{\b0 \fs19 the }
\b0 \fs19 truth}{\b0 \fs19 table}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \fs19
5-7. }
fi372 {\b0 \fs19 Consider}{\b0 \fs19 the}{\b0 \fs19 truth}{\b0 \fs19 table}{\
b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \f10 \fs17 5-8a.}{\b0 \fs19 The}{\b0 \fs1
9 minterm}{\b0 \fs19 expression}{\b0 \fs19 for}{\b0 \fs19 this}{\b0 \fs19 t
ruth}{\b0 \fs19 table}{\b0 \fs19 would}{\b0 \fs19 be}{\b0 \fs19 rather }
\b0 \fs19 long.}{\b0 \fs19 The}{\b0\i \fs19 maxtenn}{\b0 \fs19 Boolean}{\b0
\fs19 expression}{\b0 \fs19 is}{\b0 \fs19 developed}{\b0 \fs19 from}{\b0 \fs
19 the}{\b0 \fs19 variables}{\b0 \fs19 in}{\b0 \fs19 lines}{\b0\i \fs19 5}{
\b0 \fs19 and}{\b0 \fs19 8.}{\b0 \fs19 Each}{\b0 \fs19 of}{\b0 \fs19 these
}\par
}
\cf0 Fig.{\f10 \fs16 5-8}{\b0
Developing} a{\b0 maxterm}{\b0 expression }
\par
}
\cf0 CHAP.{\b0\i0 51 }\par
}
MPLIFYING LOGIC CIRCUITS: h4APPING \par
}
f0 73 \par
}
ines has a{\fs19 0} in the output column. The variables are inverted an
d ORed with parentheses around
\par}{\phpg\posx847\pvpg\posy1362\absw9196\absh1280 \sl-240 \f20 \fs19 \cf0 them
. The terms are then ANDed. The complete maxterm Boolean expression is give
n in Fig. 5-8b.
maxterm expression is also called the{\i product-of-sums}{\i \fs19 fo
rm} of a Boolean expression. The
uct-of-sums term comes from the arrangement of the sum{\f10 \fs16 (}{\f10 \fs
28 +}{\f10 \fs16 )} and product{\f10 \fs16 (}{\f10 \fs17 .)} symbols.
60 A maxterm Boolean expression would be implemented by using an OR-AN
D pattern of logic
s illustrated in Fig. 5-9. Note that the outputs of the two{\fs19 OR} gates ar
e feeding into an AND gate. \par
}
e maxterm expression
\par}{\phpg\posx847\pvpg\posy2790\absw2234\absh433 \sl-242 \f20 \fs19 \cf0 tern
of gates in{\b \fs18 Fig.} 5-9. \par
}
\fs27 \cf0 2)
}{\phpg\posx3107\pvpg\posy2726\absw1898\absh319 \i \f30 \fs27 \cf0 {\f20 \fs37 (
c}{\i0 \f10 \fs27 +}{\i0 \f10 \fs27
+}{\i0 \f10 \fs27
-}{\f20 \fs37 (c}{
\i0 \f10 \fs29 + }\par
}
s19 \cf0 B + A ){\b0\i0\dn006 \f10 \fs13 =}{\b0 \fs19 Y}{\b0\i0 is}{\b0\i0
implemented}{\b0\i0 by}{\b0\i0 using}{\b0\i0 the}{\b0\i0 OR-AND}{\b0\i0
pat- }\par
}
(C{\f10 \fs20 +}{\b\i \f30 \fs17 B}{\f10 \fs19 +}{\i \fs19 A)}{\b\i \fs15
(}{\b\i \fs15 C}{\b\i \fs15 +}{\b\i \fs15 B}{\b\i \fs15 +}{\b\i \fs1
5 A}{\b\i \fs15 )}{\b\i \fs15 =}{\b\i\dn006 \fs14
Y }\par
}
}
\cf0 Fig. 5-9{\b0 \fs17
Maxterm}{\b0 \fs17 expression}{\b0 \fs17 implemente
d}{\b0 \fs17 with}{\b0 \fs17 OR-AND}{\b0 \fs17 circuit }\par
}
LVED PROBLEMS
\b\i \fs17 5.6}{\f20 \fs19
Write}{\f20 \fs19 a}{\b\i \f20 \fs19 muxter
m}{\f20 \fs19 Boolean}{\f20 \fs19 expression}{\f20 \fs19 for}{\f20 \fs19 th
e}{\f20 \fs19 truth}{\f20 \fs19 table}{\f20 \fs19 in}{\f20 \fs19 Fig.}{\f2
0 \fs19 5-10. }\par
}
\cf0 Inputs
{\b\i \f10 \fs15 C}{\b\i \f10 \fs15
B}{\b\i \f10 \fs15
A}{\b\i \f10 \fs1
5
l }\par
}
tput
fi267 {\b\i Y }\par
}
{\phpg\posx6413\pvpg\posy8508\absw1424\absh599 \f10 \fs50 \cf0 \f10 \fs50 \cf0 &
\par
}
nputs
Output \par
}
\cf0 Fig.{\fs17 5-10 }\par
}
\cf0 Solution:
fi352 {\i \f30 \fs18 (C}{\b0 \f10 \fs26 + }\par
}
\cf0 B{\i0 \f10 \fs13 -t-}{\f30 \fs23 2)- }{\i0 \f10 \fs23 (}{\i0 \f10 \fs19
C}{\i0 \f10 \fs27 +}{\b \f30 \fs25 B}{\i0 \f10 \fs26 + }\par
}
s16 \cf0 A){\b0\i0 \fs11 =}{\b0 \f20 \fs17 Y }\par
}
cf0 5.7 \par
}
The Boolean expression developed in Prob. 5.6 is a \par
}
This type{\fs19 of} expression is also called the
}
(maxterm, minterm) expression. \par
}
(product-of-sums, sum-of-products) form. \par
}
7 \cf0 The type of Boolean expression developed in Prob.{\b\i \f10
\fs16
5-6} is called the maxterm form or the
\par}{\phpg\posx1457\pvpg\posy13296\absw8276\absh395 \sl-223 \f20 \fs17 \cf0 pro
duct-of-sums form. \par
}
0 74 \par
}
}
AP.{\b\i \f10 \fs16 5 }\par
}
f0 5.8 \par
}
iagram a logic circuit that will perform the logic in the truth table in Fig.{\
fs19 5-10. }
}
s17 \cf0 ( C + B + + ) = Y \par
}
\cf0 Fig. 5-11{\b0 \fs17
Maxterm}{\b0 \fs17 expression}{\b0 \fs17 implement
ed}{\b0 \fs17 with}{\b0 \fs17 OR-AND}{\b0 \fs17 circuit }\par
}
7 \cf0 5.9 \par
}
he logic diagram{\fs18 of} Prob.{\fs19 5.8}{\fs19 is} called the
s.
}
AND-OR, OR-AND){\fs18 pattern}{\fs18 of}{\fs18 logic }\par
}
he pattern of gates shown{\fs17 in} Fig.{\fs17 5-11} is called the OR-AND
pattern. \par
}
f0 5.10 \par
}
rite the product-of-sums Boolean expression for the truth table in Fig.{\fs19
5-12. }\par
}
cf0 Inputs
\fs17 C}{\fs17
B}{\fs17
A }\par
}
cf0 0
b\i0 \f10 \fs16 0 }
b\i0 \f10 \fs16 0 }
b\i0 \f10 \fs16 0 }\par
}
cf0 0
b\i0 \f10 \fs16 0 }
b\i0 \f10 \fs16 1 }

b\i0 \f10 \fs16 1 }\par
}
cf0 0
b\i0 \f10 \fs16 1 }
b\i0 \f10 \fs16 0 }
b\i0 \f10 \fs16 1 }\par
}
tput
fi263 {\b\i Y }\par
}
I \par
}
\cf0 0 \par
}
\cf0 1
\par}{\phpg\posx5821\pvpg\posy10019\absw134\absh583 \sl-216 \b \f10 \fs16 \cf0 1
\fs16 1 }\par
}
\cf0 0
\fs16 1 }\par
}
\cf0 1
\fs16 1 }\par
}
\cf0 Fig.{\fs16 5-12 }\par
}
\cf0 Solution:
\fi356 {\i (C}{\b0 \f10 \fs24 +}{\i \fs17 B}{\i +}{\i A}{\i )}{\i \fs16
(C }\par
}
r
}
+{\b\i \f30 \fs24 B}{\fs26 +}{\b\i \f30 \fs24 X)}{\fs23 -}{\f20 \fs21 (C}{\fs2
6 +}{\i\dn006 \f20 \fs17 B}{\fs26 +}{\i \fs20 2)}{\dn006 \fs11 =}{\b\i\dn006 \
f20 \fs17 Y }\par

}
cf0 5.11 \par
}
Diagram a logic circuit that will perform the logic in the truth table in{\b \fs
18 Fig.}{\fs19 5-12. }
\fs16 Solution: }
}
f0 75 \par
}
\cf0 Bcx)lcan{\fs18 algebra,} the{\b \fs18 algctva}{\b \fs18 of} logic cir
cuits, has{\fs18 many}{\b \f10 \fs17 laws}{\fs19 or} thcorcmh.{\b\i \fs18
I}{\b\i \fs18 l}{\b\i \fs18 c}{\b\i \fs13 ,\\f~or~citi'st}{\b\i \fs18 lrcwrc
rn.r }
8 arc}{\b \f10 \fs16 vcv} uwful. They{\fs18 allow} for{\b \f10 \fs16 ca\\>} t
ransicr back and forth froni{\b \f10 \fs17 ttic} niintcrm{\b \f10 \fs15 to}
the mastcrni form,{\fs19 of }
\par}{\phpg\posx863\pvpg\posy4774\absw8986\absh646 \sl-240 \f20 \fs18 \cf0 B t x
h n cxprcssion. 'I'hcy{\b also} allow tor cliniination{\fs18 oi} ovcrhars
that{\fs18 ;ire}{\b \fs17 oc'cr}{\b \fs17 sc\\cr;il} wiri;iblcs. \par
}
\cf0 Dc{\b0 \fs18 Morgan's}{\b0 \fs18 thcorcms}{\f10 \fs17 c;in} be{\f10 \
fs16 stated }
f0 \fi2576 {\b0 \f10 \fs10 ___ }\par
}
{\phpg\posx2617\pvpg\posy6052\absw1368\absh209 \f20 \fs18 \cf0 \f20 \fs18 \cf0 f
irst{\b \f10 \fs15 t} hcorcni{\b\i \f10 \fs17 A }\par
}
{\phpg\posx4057\pvpg\posy6159\absw47\absh94 \f10 \fs7 \cf0 \f10 \fs7 \cf0 + \par
}
cf0 ;is{\fs17 tollows: }
i84 {\b0 \f10 \fs21 -}{\b0 \f10 \fs21 - }\par
}
11 \cf0 f t \par
}
19 \cf0 B{\b0\i0 \f10 \fs13 =}{\f30 \fs10 C!}{\b0 \f10 \fs17
U }\par
}
ccond theorem{\fs18 .$I}{\f10 \fs16 .}{\b\i \f30 \fs20 fl}{\f10 \fs15 -}{\f1
0 \fs24
+}{\b\i \f30 \fs26 fi }\par
}
he{\fs19 first} theorem changes thc basic{\fs19 O}{\fs19 K} situation{\b \f10
\fs16 to} an{\b \fs19 Ah'D} situation.{\b \f10 \fs17 A} practical cxamplc
of the first
\par}{\phpg\posx883\pvpg\posy6568\absw9157\absh1336 \sl-239 \f20 \fs18 \cf0 theo
rem is illustrated{\fs19 in} F'ig.{\b \f10 \fs17 5-14a.} Thc N O R{\b \f1
0 \fs16 gatc} on thc{\b \fs19 lcft} is cqual{\fs19 in} function{\b \fs1
7 to} the{\b \fs18 AND}{\b \f10 \fs16 gatc }
18 (with} invcrtcd inputs) on thc right.{\b \fs18 Note} that thc convcr
sion is frorn ttic h i c{\fs19 OK} situatic)ri{\b \fs16 t}{\b \fs16 o
} ttic
\par}{\phpg\posx883\pvpg\posy6568\absw9157\absh1336 \sl-237 \f20 \fs18 \cf0 basi
c{\b \fs18 AND} situation{\fs19 as} shown{\b \fs18 by} thc{\b \f10 \fs15 g
atcs}{\fs19 in} Fig.{\b \f10 5}{\b \f10 -}{\b \f10 1}{\b \f10 4}{\b \f10
~}{\b \f10 )}{\b \f10 .}This conversion is{\b \fs18 uxful}{\dn006 \fs12
iii} gcttinp rid{\fs18 of }
long overbar on the{\b \fs18 NOR}{\fs18 and} can{\fs19 bc} uscd{\fs18 in} c
onverting from{\b a} mintcrni{\b \f10 \fs15 to}{\b\dn006 \f10 \fs11 ;i}niri
stcrni expression.
\fs19 Thc} AND-boking symbol{\fs18 at}{\b \f10 \fs17 the} right{\fs19 in}{\
fs18 I:ig}{\b \f10 \fs17
5-13u} would produce{\b\i\dn006 \fs12
ii}{\b
\fs18 NOR}{\fs18 truth} t;ihlc. \par
}
cf0 Y \par
}
cf0 /I \par
}
14 \cf0 B \par
}
14 \cf0 1'
\fi86 {\fs9 (}{\fs9 U}{\fs9 ) }\par
}
\b\i \fs19 n}{\dn006 \fs11
- }\par
}
\cf0 NOR{\fs13 funcrioom }\par
}
8 \cf0 'I'hc{\fs18 sccond}{\fs18 theorem}{\fs17 changes}{\fs18 thc}{\fs18
basic}{\b \f10 \fs17 AND}{\fs18 situation}{\b \f10 \fs15 t}{\b \f10 \fs15
o}{\fs18 ;in} O K{\fs18 situation.}{\b \f10 \fs17 A}{\fs18 practical}{\fs
18 cxaniple} of
s18 the}{\fs18 second}{\fs18 theorem}{\fs18 is}{\fs18 illustrated} in{\fs18
Fig.}{\b \f30 \fs18 5-14h.}{\fs18 The}{\b \fs18 KAND}{\b \f10 \fs16 gate}{
\fs18 on}{\fs18 the}{\b \fs17 left}{\fs18 is}{\fs18 cqual}{\fs18 in}{\fs1
8 tunction}{\fs18 to}{\fs18 the }
s19 OR}{\fs18 gate}{\fs18 (with}{\fs18 invcrtcd}{\fs18 inputs)}{\b \fs17 o
}{\b \fs17 n}{\fs18 the}{\fs17 right.}{\fs18 A}{\fs18 p}{\fs18 i}{\fs18
n}{\fs18 the}{\fs18 long}{\fs18 ovcrhar}{\fs18 is}{\fs18 climinatcd,}{\fs
18 and}{\fs18 conversions}{\fs18 can }
\f10 \fs17 be}{\fs18 done}{\fs18 froni}{\fs18 mnstcrni}{\b \f10 \fs15 to}{
\fs18 niintcrm}{\fs18 forms}{\fs18 of}{\fs18 I3oolcan}{\fs18 cxprcssions.

}{\fs19 'I'hc}{\fs18 OK-looking}{\fs18 symbol}{\b \f10 \fs15 a}{\b \f10 \fs
15 t}{\fs18 thc}{\fs18 right }
s19 in}{\fs18 {\f63 \u8364\'3f}:ig}{\b \f30 \fs19 5-14h}{\b \fs18 would}{\fs
18 produce}{\b \fs13
;I}{\b \fs18 NAND}{\fs18 truth}{\b \fs18 table. }
354 {\b \fs19 The}{\fs18 synihls}{\b\dn006 \fs12 iit}{\b \fs19 thc}{\fs18
right}{\fs19 in}{\b \fs16 1;ig.}{\b \f10 \fs17 5-14}{\dn006 \f10 \fs10 ;i
re}{\b \f10 \fs15 thc}{\fs18 altcrnatc}{\b \f30 \fs19 symbols}{\b \fs19 used
}{\fs18 for}{\fs18 the}{\f10 \fs17 NOR}{\fs18 and}{\b \fs18 NAND}{\fs18 l
ogic }
s18 functions.}{\fs18 Figure}{\b\i \f10 \fs18 5}{\b\i \f10 \fs18 -}{\b \f10
\fs17 14}{\fs18 illustrates}{\fs18 but}{\fs18 one}{\fs18 usc}{\fs18 of}
Ilc{\fs18 Xlorgan's}{\fs18 thcorcnis. }
367 {\fs18 Four}{\b \fs18 stcps}{\fs18 arc}{\fs18 needed} to{\fs18 transf
orm}{\b \f30 \fs13 3}{\fs18 basic}{\b r1ND}{\fs18 situation}{\fs18 t}{\fs1
8 o}{\fs18 an}{\b \f10 \fs17 OK}{\fs18 situation}{\b \fs19 (or}{\fs18 an
}{\b \f10 \fs18 OR}{\b \fs18 t}{\b \fs18 o}{\fs18 an }
\fs18 AND}{\fs18 situation).}{\b \f10 \fs16 The}{\fs18 four}{\fs18 stcps.}{
\b \fs18 based}{\b \f30 on}{\fs19 I>c}{\fs18 Morgan's}{\fs18 thcorcms.}{\f
s18 arc}{\b \f30 \fs14 ;IS}follows: \par
}
\cf0 1.
20 2. }\par
}
Change{\f10 \fs18 (111}{\b \fs18 OKs}{\b \f10 \fs15 to}{\b \fs18 AKDs} and{
\b \fs19 all}{\b AND5}{\b \f10 \fs15 t}{\b \f10 \fs15 o}{\b \fs18 OKs. }
iplcmcnt cach iiidividwil t,ari;iblc (add ovcrbar to each). \par
}
3.{\fs18
Complement}{\b \fs19 thc}{\fs18 cntirc}{\fs18 function}{\fs18
(add}{\b \f30 ocerbar}{\b \f10 \fs15 to}{\fs18 cntirc}{\fs18 function). }
\f10 \fs16 4.}{\fs18
Eliminate}{\fs18 all}{\fs18 groups}{\fs19 o}{\fs19
f}{\fs18 double}{\fs18 ovcrbars. }\par
}
par
}
}
AP.{\fs17 5 }\par
}
onsider the maxterm expression in Fig.{\i \fs19 5-15a.} By using the above proc
edure, transform this maxterm
\par}{\phpg\posx827\pvpg\posy1356\absw9276\absh1723 \sl-237 \f20 \fs19 \cf0 expr
ession into a minterm expression. The{\i \fs19 first}{\b\i \f30 \fs17 step
} (Fig.{\i \fs19 5}{\i \fs19 1}{\i \fs19 %}{\i \fs19 )} is to change all OR
s to{\b \fs18 ANDs} and
19 ANDs} to{\fs19 ORs.} The{\i \fs19 second}{\i \fs19 step} (Fig.{\i \fs19
5}{\i \fs19 1}{\i \fs19 %}{\i \fs19 )} is to add an overbar to each individu
al variable. The{\i \fs19 third }
\fs19 step} (Fig.{\i \fs19 5-15d)} is to add an overbar to the entire function.
The{\i \fs19 fourth}{\i \fs19 step} is to eliminate all double
\par}{\phpg\posx827\pvpg\posy1356\absw9276\absh1723 \sl-237 \f20 \fs19 \cf0 over
bars and rewrite the final minterm expression. The five groups of double o
verbars which will be
\par}{\phpg\posx827\pvpg\posy1356\absw9276\absh1723 \sl-235 \f20 \fs19 \cf0 elim
inated are shown in the shaded areas in Fig.{\i \fs19 5-15e.} The final minter
m expression appears in Fig.
\fs19 5-15f.} The maxterm expression in Fig.{\i \fs19 5-15a} and the minterm
expression in Fig.{\i \fs19 5-15f} will produce
same truth table. \par
}
\cf0 ( A{\i0 \f10 \fs27 +}{\b \f30 \fs24 B}{\i0 \f10 \fs27 +}{\b\dn006 \fs17
C}{\i0 \f10 \fs23 -) }\par
}
15 \cf0 ( A{\b0\i0 \fs27 +}{\dn006 \f20 \fs17 B }\par
}
\b\i \f20 \fs20 C}{\b\i \f20 \fs20 )}{\b\i \f20 \fs20 =}{\i\dn006 \f20 \fs17
Y }\par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 Maxterm}{\b0\i0 \f20 \fs15 expression }\par
}
par
}
\cf0 A . j j . C + ' j . B . C
fi268 {\b0 \fs15 (d)}{\b0 \fs15 Third}{\b0 \fs15 step }\par
}
15 \cf0 A \par
}
15 \cf0 m \par
}
par
}
fs17 \cf0 A - B . C + A - B * C
\cf0 \fi210 {\b0\i0 \fs15 (b)}{\b0\i0 \fs15 First}{\b0\i0 \fs15 step }
\cf0 {\fs21 J}{\fs21 .}{\fs21 B}{\fs21 .}{\fs21 C}{\fs21 +}{\fs21 A}{\fs2
1 .}{\fs21 B}{\fs21 .}{\fs21 C }
\cf0 \fi220 {\b0\i0 \fs15 (c)}{\b0\i0 \fs15 Second}{\b0\i0 \fs15 step }\par
}
\f20 \fs14 \cf0 (e){\b0\i0 \fs15 Fourth}{\b0\i0 \fs15 step }
\cf0 {\fs19 A}{\fs19 -}{\fs19 B}{\fs19 -}{\fs19 c}{\fs19 +}{\fs19 A}{\fs19
-}{\fs19 B}{\fs19 .}{\fs19 c}{\fs19 =}{\b0 \fs17 Y }
\fi217 {\b0\i0 \fs16 (f)}{\b0\i0 \fs15 Minterm}{\b0\i0 \fs15 expression }\pa
r
}
\cf0 Fig.{\fs17 5-15}{\b0 \fs17
From}{\b0 \fs17 maxterm}{\b0 \fs17 to}{\b0
\fs17 minterm}{\b0 \fs17 expressions}{\b0 \fs17 using}{\b0 \fs17 De}{\b0 \f
s17 Morgan's}{\b0 \fs17 theorems }\par
}
}
f0 5.12 \par
}
onvert the Boolean expression{\f10 \fs20 (}{\b\i \fs18 A}{\f10 \fs29 + }\
par
}
ach step as in Fig.{\i \fs19 5-15. }
}
Maxterm expression
First step
Second step
\cf0 Third step
\par}{\phpg\posx1445\pvpg\posy8427\absw1587\absh1769 \sl-264 \f20 \fs17 \cf0 Fou
rth step
\par}{\phpg\posx1445\pvpg\posy8427\absw1587\absh1769 \sl-256 \f20 \fs17 \cf0 Min
term expression \par
}
17 \cf0 ( A{\b0\i0 \f10 \fs26 + }\par
}
{\i \f20 \fs37 c)}{\fs27 -}{\b\i \f30 \fs37 (x+} +{\i \f20 \fs37 c) }\par
}
19 \cf0 B \par
}
{\b\i \f20 \fs19 Y}{\f20 \fs19 to}{\f20 \fs19 its}{\f20 \fs19 minterm}{\f
20 \fs19 form.}{\f20 \fs19 Show }\par
}
{\i \f20 \fs34 c)}{\i \f30 (A+ }{\b\i\dn006 \f20 \fs17 B} +{\i \f20 \fs33 c) }
\par
}
}
\b\i \f20 \fs17 Y }\par
}
fs15 \cf0 A{\i0 \f20 \fs23 .}{\i0 \f20 \fs23 B}{\i0 \f20 \fs23 .}{\b0 \f20 \f
s22 C+A.B- }
0 {\f30 \fs22 2.E. }
}{\phpg\posx3395\pvpg\posy8694\absw2051\absh1298 \b\i \f10 \fs15 \cf0 \fi0 {\f20
\fs26 F+Z.}{\f20 \fs21 g}{\f20 \fs21 . }
\par}{\phpg\posx3395\pvpg\posy8694\absw2051\absh1298 \sl-258 \par\par\b\i \f10 \
fs15 \cf0 {\b0\i0 \f20 \fs17 eliminate}{\b0\i0 \f20 \fs17 double}{\b0\i0 \f20
\fs17 overbars }\par
}
\cf0 2.{\b \fs18 C}{\b \f20 \fs17 +}{\b \f20 \fs17 A}{\i0 \f10 \fs23 - }
}{\phpg\posx3381\pvpg\posy10102\absw1149\absh299 \i \f30 \fs22 \cf0 \fi0 {\b\dn0
06 \f20 \fs17 B }\par
}
r
}
s19 \cf0 C{\b0\i0\dn006 \f10 \fs11 =}{\f20 \fs17 Y }\par
}
3 \cf0 - \par}{\phpg\posx843\pvpg\posy10660\absw5019\absh441 \sl-276 \f10 \fs23 \cf0 {\b
\f20 \fs19 5.13}{\f20 \fs19
Convert}{\f20 \fs19 the}{\f20 \fs19 Boolean}{\
f20 \fs19 expression}{\i \f20 \fs18 C}{\b\i \f20 \fs19 B}{\b\i \f20 \fs19 .
}{\b\i \f20 \fs19 A}{\fs30 +}{\i \f20 \fs18 C}{\b\i \f20 \fs19 B }\par
}
ar
}
r
}
the procedure.
b \fs17 Solution: }
0 {\fs17 Minterm}{\fs17 expression }
fs17 First}{\fs17 step }
0 {\fs17 Second}{\fs17 step }
0 {\fs17 Third}{\fs17 step }
fs17 Fourth}{\fs17 step }
fs17 Maxterm}{\fs17 expression }\par
}
3 \cf0 c{\i0\dn006 \f10 \fs23 -}{\b \f30 \fs25 B}{\f30 \fs26 .A+}{\i0\dn006 \f
10 \fs23 -}{\f30 \fs26 -A= }

{\i0 \f10 \fs20 (C}{\i0 \f10 \fs26 +}{\b \f30 \fs25 B}{\f30 \fs25 +A)}{\b \f30
\fs18 (C}{\i0 \f10 \fs27 +}{\b\dn006 \fs17 B}{\f30 \fs25 +A) }
{\b \fs22 (}{\b \fs22 c}{\b \fs22 =}{\b \fs22 +}{\b \fs22 B}{\b \fs22 =}{\
b \fs22 +}{\b \fs22 K}{\b \fs22 )}{\b \fs22 .}{\b \fs22 (}{\b \fs22 C}{\b
\fs22 +}{\b \fs22 B}{\b \fs22 +}{\b \fs22 K}{\b \fs22 ) }
{\b \f10 \fs24 (c=+E+A=)}{\i0 \f10 \fs23 -}{\b \fs22 (}{\b \fs22 C}{\b \fs22 +
}{\b \fs22 B}{\b \fs22 +}{\b \fs22 A}{\b \fs22 =}{\b \fs22 ) }
{\i0 \fs17 eliminate}{\i0 \fs17 double}{\i0 \fs17 overbars }\par
}
s18 \cf0 C{\f20 \fs17
B }\par
}
s17 \cf0 Y \par
}
r
}
s19 \cf0 (C{\b0\i0 \f10 \fs26 +}{\dn006 \f20 \fs17 B }\par
}
s15 \cf0 + A ) \par
}
{\phpg\posx4367\pvpg\posy13379\absw870\absh345 \f10 \fs27 \cf0 \f10 \fs27 \cf0 {\f20 \fs30 (c}{\fs27 +}{\b\i \f30 \fs25 B }\par
}
s17 \cf0 + A ){\b0\i0\dn006 \f10 \fs11 =}{\fs17 Y }\par
}
}
fs37 \cf0 .x=
}{\phpg\posx5671\pvpg\posy10714\absw4118\absh364 \b\i \f30 \fs37 \cf0 \fi0 {\f20
\fs19 Y}{\b0\i0 \f20 \fs19 to}{\b0\i0 \f20 \fs19 its}{\b0\i0 \f20 \fs19 maxt
erm}{\b0\i0 \f20 \fs19 form.}{\b0\i0 \f20 \fs19 Show}{\b0\i0 \f20 \fs19 each}
{\b0\i0 \f20 \fs19 step}{\b0\i0 \f20 \fs19 in }\par
}
0 CHAP.{\b\i0 \f10 \fs17 51 }\par
}
}
f0 77 \par
}
onvert the Boolean expression{\b\i A}{\f10 \fs27 -}{\b\i B}{\dn006 \f10 \fs1
3 = }
\fs17 Solution: }
45 {\b\i \fs17 A}{\b\i \fs17 +}{\b\i \fs17 B}{\b\i \fs17 =}{\b\i \fs17 Y }\p
ar
}
onvert the Boolean expression
45 {\b\i \fs17 A}{\b\i \fs17 *}{\b\i \fs17 B}{\b\i \fs17 =}{\b\i \fs17 Y }\p
ar
}
}
}
f0 5.14 \par
}
\cf0 Y{\i0 \fs19 to}{\i0 \fs19 a}{\i0 \fs19 sum-of-products}{\i0 \fs19 form
. }\par
}
f0 5.15 \par
}
cf0 A+{\b \f20 \fs25 E}{\b \f20 \fs25 = }\par
}
s19 \cf0 Y{\b0\i0 \fs19 to}{\b0\i0 \fs19 a}{\b0\i0 \fs19 product-of-sums}{\b0
\i0 \fs19 form. }\par
}
\cf0 5-5{\fs19
USING}{\f30 \fs21 NAND}{\fs19 LOGIC }
fi360 {\b0 \fs19 All}{\b0 \fs19 digital}{\b0 \fs19 systems}{\b0 \fs19 can}{\b
0 \fs19 be}{\b0 \fs19 constructed}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19
fundamental}{\b0 \fs19 AND,}{\b0 \fs19 OR,}{\b0 \fs19 and}{\b0 \fs18 NOT}{
\b0 \fs19 gates.}{\b0 \fs19 Because }
\b0 \fs19 of}{\b0 \fs19 their}{\b0 \fs19 low}{\b0 \fs19 cost}{\b0 \fs19 and}
{\b0 \fs19 availability,}{\b0 \fs19 NAND}{\b0 \fs19 gates}{\b0 \fs19 are}{\b
0 \fs19 widely}{\b0 \fs19 used}{\b0 \fs19 to}{\b0 \fs19 replace}{\b0 \fs19
AND,}{\b0 \fs19 OR,}{\b0 \fs19 and}{\b0 \fs19 NOT}{\b0 \fs19 gates. }
\b0 \fs19 There}{\b0 \fs19 are}{\b0 \fs19 several}{\b0 \fs19 steps}{\b0 \fs19
in}{\b0 \fs19 converting}{\b0 \fs19 from}{\b0 \fs19 AND-OR}{\b0 \fs19 logi
c}{\b0 \fs19 to}{\b0 \fs19 NAND}{\b0 \fs19 logic: }
fi374 {\b0 \fs19 1.}{\b0 \fs19
Draw}{\b0 \fs19 an}{\b0 \fs19 AND-OR}{\b0 \f
s19 logic}{\b0 \fs19 circuit. }
fi362 {\b0 \fs19 2.}{\b0 \fs19
Place}{\b0 \fs19 a}{\b0 \fs19 bubble}{\b0 \
fs19 at}{\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 of}{\b0 \fs19 each}{\
b0 \fs19 AND}{\b0 \fs19 gate. }
fi362 {\b0 3.}{\b0 \fs19

Place}{\b0 \fs19 a}{\b0 \fs19 bubble}{\b0 \fs19
at}{\b0 \fs19 each}{\b0 \fs19 input}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19
OR}{\b0 \fs19 gate. }
fi362 {\b0 \f10 \fs18 4.}{\b0 \fs19
Check}{\b0 \fs19 the}{\b0 \fs19 logic}
{\b0 \fs19 levels}{\b0 \fs19 on}{\b0 \fs19 lines}{\b0 \fs19 coming}{\b0 \fs1
9 from}{\b0 \fs19 the}{\b0 \fs19 inputs}{\b0 \fs19 and}{\b0 \fs19 going}{\b
0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 outputs. }
\b0 \fs19 Consider}{\b0 \fs19 the}{\b0 \fs19 minterm}{\b0 \fs19 Boolean}{\
b0 \fs19 expression}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 5-16a.}{\b0 \fs19
To}{\b0 \fs19 implement}{\b0 \fs19 this}{\b0 \fs19 expression}{\b0 \fs1
9 by}{\b0 \fs19 using }
\b0 \fs19 NAND}{\b0 \fs19 logic,}{\b0 \fs19 the}{\b0 \fs19 steps}{\b0 \fs19
outlined}{\b0 \fs19 above}{\b0 \fs19 will}{\b0 \fs19 be}{\b0 \fs19 follow
ed.}{\b0 \fs19 The}{\i \fs18 first}{\i \fs18 step}{\b0 \fs19 (Fig.}{\b0
5-16b)}{\b0 \fs19 is}{\b0 \fs19 to}{\b0 \fs19 diagram}{\b0 \fs19 an }
\b0 \fs19 AND-OR}{\b0 \fs19 logic}{\b0 \fs19 circuit.}{\b0 \fs19 The}{\i \fs1
8 second}{\i \fs18 step}{\b0 \fs19 is}{\b0 \fs19 to}{\b0 \fs19 place}{\b
0 \fs19 a}{\b0 \fs19 bubble}{\b0 \fs19 (small}{\b0 \fs19 circle)}{\b0 \fs19
at}{\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 of}{\b0 \fs19 each}{\b0 \fs1
9 AND }
\b0 \fs19 gate.}{\b0 \fs19 This}{\b0 \fs19 changes}{\b0 \fs19 the}{\b0 \fs19
AND}{\b0 \fs19 gates}{\b0 \fs19 to}{\b0 \fs19 NAND}{\b0 \fs19 gates.}{\b0 \
fs19 Figure}{\b0 5-16c}{\b0 \fs19 shows}{\b0 \fs19 bubbles}{\b0 \fs19 added
}{\b0 \fs19 to}{\b0 \fs19 gates}{\b0 \fs18 1}{\b0 \fs19 and }
\b0 \fs19 2.}{\b0 \fs19 The}{\i \fs18 third}{\i \fs18 step}{\b0 \fs19 is}{
\b0 \fs19 to}{\b0 \fs19 place}{\b0 \fs19 a}{\b0 \fs19 bubble}{\b0 \fs19 (sm
all}{\b0 \fs19 circle)}{\b0 \fs19 at}{\b0 \fs19 each}{\b0 \fs19 input}{\b0 \
fs19 of}{\b0 \fs19 the}{\b0 \fs19 OR}{\b0 \fs19 gate.}{\b0 \fs19 This}{\b0
\fs19 will}{\b0 \fs19 convert}{\b0 \fs19 the }
\b0 \fs19 OR}{\b0 \fs19 gate}{\b0 \fs19 to}{\b0 \fs19 a}{\b0 \fs19 NAND}{\b0
\fs19 gate.}{\b0 \fs19 Figure}{\b0 5-16c}{\b0 \fs19 shows}{\b0 \fs19 three
}{\b0 \fs19 bubbles}{\b0 \fs19 added}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19
inputs}{\b0 \fs19 of}{\b0 \fs19 gate}{\b0 \fs19 3.}{\b0 \fs19 The}{\i \fs1
8 fourth }
\i \fs18 step}{\b0 \fs19 involves}{\b0 \fs19 examination}{\b0 \fs19 of}{\b0 \
fs19 the}{\b0 \fs19 input}{\b0 \fs19 and}{\b0 \fs19 output}{\b0 \fs19 lines
}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19 AND}{\b0 \fs19 and}{\b0 \fs19 OR
}{\b0 \fs19 symbolsto}{\b0 \fs19 see}{\b0 \fs18 if}{\b0 \fs19 any}{\b0 \fs19
of }
\b0 \fs19 the}{\b0 \fs19 logic}{\b0 \fs19 levels}{\b0 \fs19 have}{\b0 \fs19
been}{\b0 \fs19 changed}{\b0 \fs19 by}{\b0 \fs19 the}{\b0 \fs19 addition}{\b
0 \fs19 of}{\b0 \fs19 bubbles.}{\b0 \fs19 On}{\b0 \fs19 examination}{\b0 \fs
19 of}{\b0 \fs19 the}{\b0 \fs19 circuit}{\b0 \fs19 shown}{\b0 \fs19 in }
\b0 \fs19 Fig.}{\b0 5-16c,}{\b0 \fs19 it}{\b0 \fs19 is}{\b0 \fs19 found}{\b
0 \fs19 that}{\b0 \fs19 the}{\b0 \fs19 added}{\b0 \fs19 bubble}{\b0 \fs1
9 at}{\b0 \fs19 point}{\b0\i \fs19 X}{\b0 \fs19
has}{\b0 \fs19 change
d}{\b0 \fs19 the}{\b0 \fs19 input}{\b0 \fs19 logic}{\b0 \fs19 level}{\b0
\fs19 on}{\b0 \fs19 OR }
\b0 \fs19 symbol}{\b0 \fs19 3.}{\b0 \fs19 The}{\b0 \fs19 AND-OR}{\b0 \fs19 d
iagram}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 5-16b}{\b0 \fs19 shows}{\b0 \fs19

that}{\b0 \fs19 a}{\b0 \fs19 HIGH}{\b0 \fs19 logic}{\b0 \fs19 level}{\b0 \f
s19 is}{\b0 \fs19 connected}{\b0 \fs19 from}{\b0 \fs19 input }
\i \fs19 E}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 OR}{\b0 \fs19 gate.}{\b0
\fs19 The}{\b0 \fs19 HIGH,}{\b0 \fs19 or}{\b0 1,}{\b0 \fs19 activates}{\b
0 \fs19 the}{\b0 \fs19 OR}{\b0 \fs19 gate.}{\b0 \fs19 A}{\b0 \fs19 HIGH}{\b
0 \fs19 must}{\b0 \fs19 also}{\b0 \fs19 arrive}{\b0 \fs19 at}{\b0 \fs19 th
e}{\b0 \fs19 input}{\b0 \fs19 of }
\b0 \fs19 symbol}{\b0 \fs19 3}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 5-16c.}{\b0
\fs19 This}{\b0 \fs19 is}{\b0 \fs19 accomplished}{\b0 \fs19 by}{\b0 \fs19
adding}{\b0 \fs19 the}{\b0 \fs19 shaded}{\b0 \fs19 inverter}{\b0 \fs19 in}
{\b0 \fs19 input}{\b0 \fs19 line}{\i \fs19 E.}{\b0 \fs19 In}{\b0 \fs19 ac
tual }
\b0 \fs19 practice,}{\b0 \fs19 a}{\b0 \fs19 NAND}{\b0 \fs19 gate}{\b0 \fs19
is}{\b0 \fs19 used}{\b0 \fs19 as}{\b0 \fs19 the}{\b0 \fs19 inverter.}{\b0 \f
s19 The}{\b0 \fs19 double}{\b0 \fs19 inversion}{\b0 \fs19 will}{\b0 \fs19 d
eliver}{\b0 \fs19 the}{\b0 \fs19 HIGH}{\b0 \fs19 logic}{\b0 \fs19 level }
\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 OR}{\b0 \fs19 symbol}{\b0 \fs19 to}{\
b0 \fs19 activate}{\b0 \fs19 the}{\b0 \fs19 OR.}{\b0 \fs19 The}{\b0 \fs19 i
nvert}{\b0 \fs19 bubbles}{\b0 \fs19 between}{\b0 \fs19 gates}{\b0 1}{\b0 \
fs19 and}{\b0 3}{\b0 \fs19 cancel}{\b0 \fs19 one}{\b0 \fs19 another. }
\b0 \fs19 Likewise,}{\b0 \fs19 the}{\b0 \fs19 invert}{\b0 \fs19 bubbles}{\b
0 \fs19 between}{\b0 \fs19 gates}{\b0 \fs19 2}{\b0 \fs19 and}{\b0 \fs19
3}{\b0 \fs19 cancel.}{\b0 \fs19 The}{\b0 \fs19 NAND}{\b0 \fs19 logic}{\
b0 \fs19 circuit}{\b0 \fs19 shown}{\b0 \fs19 in}{\b0 \fs19 Fig. }
\b0 5-16c}{\b0 \fs19 will}{\b0 \fs19 produce}{\b0 \fs19 the}{\b0 \fs19 same}
{\b0 \fs19 truth}{\b0 \fs19 table}{\b0 \fs19 as}{\b0 \fs19 that}{\b0 \fs19
for}{\b0 \fs19 the}{\b0 \fs19 AND-OR}{\b0 \fs19 circuit. }\par
}
s14 \cf0 A-\par}{\phpg\posx5981\pvpg\posy10585\absw258\absh510 \sl-186 \par\b\i \f10 \fs14
\cf0 {\f20 \fs15 B-- }\par
}
cf0 1 \par
}
s15 \cf0 Y \par
}
s15 \cf0 C
\cf0 {\fs15 D- }\par
}
\par
}
s15 \cf0 Y \par
}
s16 \cf0 E \par
}
{\phpg\posx6681\pvpg\posy12279\absw254\absh252 \f10 \fs10 \cf0 \f10 \fs10 \cf0 ;

:
17 ...;. }\par
}
...{\fs19 .. }\par
}
' \par
}
s14 \cf0 E \par
}
AND wired
00 as inverter \par
}
fs15 \cf0 (b){\b0\i0 \fs15 Equivalnet}{\b0\i0 \fs15 AND-OR}{\b0\i0 \fs15 log
ic}{\b0\i0 \fs15 circuit }\par
}
fs13 \cf0 ( c ){\b0\i0 \f20 \fs15 Equivalent}{\b0\i0 \f20 \fs15 NAND}{\b0\i0
\f20 \fs15 logic}{\b0\i0 \f20 \fs15 circuit }\par
}
\cf0 Fig.{\fs17 5-16 }\par
}
par
}
}
AP.{\fs17 5 }\par
}
\cf0 Using NAND logic does not always simplify a circuit. The example shown in F
ig.{\fs18 5-16} shows that
\par}{\phpg\posx839\pvpg\posy1364\absw9159\absh855 \sl-239 \f20 \fs18 \cf0 the A
ND-OR circuit would probably be preferred over the NAND circuit because of th
e fewer gates
\par}{\phpg\posx839\pvpg\posy1364\absw9159\absh855 \sl-235 \f20 \fs18 \cf0 used.
Most manufacturers of{\b \fs19 ICs} do produce a good variety of all type
s{\fs18 of} gates. The logic designer
\par}{\phpg\posx839\pvpg\posy1364\absw9159\absh855 \sl-238 \f20 \fs18 \cf0 can u
sually select the logic that produces the simplest circuitry. \par
}
}
cf0 5.16{\b0 \fs18
Diagram}{\b0 \fs18 an}{\b0 \fs18 AND-OR}{\b0 \fs18 lo
gic}{\b0 \fs18 circuit}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 Boolean}{\b0
\fs18 expression}{\i \fs18 A}{\b0 \f10 \fs23 -}{\b0\i \fs19 B}{\b0 \f10 \f
s29 +}{\b0 \fs35 c}{\b0 \f10 \fs28 +}{\b0 \f10 \fs27

- }\par
}
cf0 D{\fs19
E}{\i0\dn006 \f10 \fs13 =}{\b Y. }\par
}
\cf0 Solution:
fi355 {\b0 \fs16 See}{\b0 \fs17 Fig.}{\b0 \fs17 5-17. }\par
}
+%= \par
}
s19 \cf0 A . B + C + D . E ={\fs15 Y }\par
}
\cf0 Fig. 5-17{\b0 \fs17
AND-OR}{\b0 \fs17 logic-circuitsolution }\par
}
f0 5.17 \par
}
iagram a NAND logic circuit from the AND-OR circuit in Prob.{\fs18 5.
16.} The NAND circuit \par
}
hould perform the logic in the expression{\b\i \fs19 A}{\i \fs19
B }
}
}
\f20 \fs33 c}+ \par
}
21 \cf0 D{\b0\i0 \f10 \fs23 -}{\b0 \f20 \fs19 E}{\b0\i0\dn006 \f10 \fs13 =}{
\f20 \fs19 Y. }\par
}
\cf0 Fig. 5-18{\b0 \fs17
NAND}{\b0 \fs17 logic-circuitsolution }\par
}
cf0 5.18 \par
}
Diagram an AND-OR logic circuit for the Boolean expression{\b\i A}{\f10 \fs28
+ }
\fs16 Solution: }
}
\cf0 ( B{\i0 \f10 \fs27 -}{\b \fs19 C>}{\i0 \f10 \fs28 + }\par
}
{\b\i \f20 \fs19 Y. }\par

}
0 CHAP.{\b0 \fs18 51 }\par
}
cf0 SIMPLIFYING LOGIC CIRCUITS: MAPPING \par
}
\par
}
\cf0 Fig.{\fs17 5-19} AND-OR{\b0 \fs17 logic-circuit}{\b0 \fs17 solution }\
par
}
f0 5.19 \par
}
iagram a{\b NAND} logic circuit from the{\b AND-OR} circuit in Prob.{\
fs19 5.18,} The{\b NAND} circuit \par
}
hould perform the logic in the expression{\b\i A}{\f10 \fs28 + }
\fs17 Solution: }
}
s19 \cf0 ( B{\b0\i0 \f10 \fs27 -}{\fs19 C}{\fs19 )}{\b0\i0 \f10 \fs27 + }\par
}
\b\i \f20 \fs19 Y. }\par
}
14 \cf0 D \par
}
\cf0 Fig.{\fs17 5-20}{\fs17
NAND}{\b0 \fs17 logic-circuit}{\b0 \fs17 solu
tion }\par
}
\cf0 5-6{\f20 \fs18
USING}{\f20 \fs18 NOR}{\f20 \fs19 LOGIC }
fi366 {\b0 \f20 \fs19 The}{\f20 \fs19 NAND}{\b0 \f20 \fs19 gate}{\b0 \f20 \f
s19 was}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 ''universal}{\b0 \f20 \fs19 g
ate"}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 substituting
}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 an}{\f20 \fs19 AND-OR}{\b0 \f20 \fs19
logic}{\b0 \f20 \fs19 pattern. }
\b0 \f20 \fs19 When}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 maxterm}{\b0 \f20 \fs19
Boolean}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 forms}{\b0 \f20 \fs19 an}
{\f20 \fs19 OR-AND}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 pattern,}{\b0 \f20 \f
s19 the}{\f20 \fs19 NAND}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 does}{\b0 \f20
\fs19 not}{\b0 \f20 \fs19 work }
\b0 \f20 \fs19 well.}{\b0 \f20 \fs19 The}{\f20 \fs19 NOR}{\b0 \f20 \fs19 gate
}{\b0 \f20 \fs19 becomes}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 ''universal}{\b0
\f20 \fs19 gate"}{\b0 \f20 \fs19 when}{\b0 \f20 \fs19 substituting}{\b0 \f20
\fs19 in}{\f20 \fs19 OR-AND}{\b0 \f20 \fs19 logic}{\b0 \f20 \fs19 patterns.
}{\b0 \f20 \fs19 The }
\f20 \fs19 NOR}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 not}{\
b0 \f20 \fs19 as}{\b0 \f20 \fs19 widely}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19
as}{\b0 \f20 \fs19 the}{\f20 \fs19 NAND}{\b0 \f20 \fs19 gate. }
fi374 {\b0 \f20 \fs19 Consider}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 maxterm}{
\b0 \f20 \fs19 Boolean}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 written}
{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5-21a.}{\b0 \f20 \f
s19 The}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 draw
n}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 an }
\f20 \fs19 OR-AND}{\b0 \f20 \fs19 logic}{\b0 \f20 \fs19 diagram}{\b0 \f20 \fs1
9 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5-21}{\b0\i \f20 \fs18 h.}{\b0 \f20
\fs19 The}{\f20 \fs19 OR-AND}{\b0 \f20 \fs19 pattern}{\b0 \f20 \fs19 is}{\b
0 \f20 \fs19 redrawn}{\b0 \f20 \fs19 with}{\f20 \fs19 NOR}{\b0 \f20 \fs19 ga
tes}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5-21}{\b0 \f20 \f
s17 c. }
\b0 \f20 \fs19 Each}{\f20 \fs19 OR}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 and}{
\f20 \fs19 AND}{\b0 \f20 \fs19 gate}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 repla
ced}{\f20 \fs18 by}{\b0 \f20 \fs19 a}{\f20 \fs19 NOR}{\b0 \f20 \fs19 gate.}{
\b0 \f20 \fs19 Gates}{\b0 \f20 \fs18 1}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 2}
{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5-21c}{\b0 \f20 \fs19
are}{\b0 \f20 \fs19 shown}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 the }\par
}
s14 \cf0 (A{\b0\i0 \fs23 +}{\dn006 \f20 \fs15 B) }
\par}{\phpg\posx861\pvpg\posy10550\absw692\absh1016 \sl-205 \par\par\b\i \f10 \f
s14 \cf0 \fi22 A
\fi22 {\f20 \fs15 B }\par
}
{\phpg\posx5695\pvpg\posy10623\absw2220\absh1989 \b\i \f10 \fs68 \cf0 \b\i \f10
\fs68 \cf0 Az>9
8 \cf0 {\b0\i0 \f20 \fs55 czP }\par
}
s15 \cf0 B \par
}
s17 \cf0 D \par
}
\cf0 (c){\fs15 Equivalent}{\fs15 NOR}{\fs15 logic}{\fs15 circuit }\par
}
r
}
s15 \cf0 (C{\b0\i0 \f10 \fs22 + }
\fi25 {\b0\i0 \f10 \fs20 (4 }\par
}
s15 \cf0 0){\b0\i0 \f10 \fs14 =}{\f20 \fs15 Y }\par
}
s16 \cf0 + D ) ={\f20 \fs15 Y }\par
}
\cf0 c 2 Y \par
}
15 \cf0 D \par
}
fs16 \cf0 (b){\i0 \fs15 Equivalent}{\i0 \fs15 OR-AND}{\i0 \fs15 logic}{\i0 \f
s15 circuit }\par
}
\cf0 Fig.{\fs17 5-21 }\par
}
par
}
MPLIFYINGLOGIC CIRCUITS: MAPPING \par
}
AP.{\i 5 }\par
}
tandard NOR symbols. Gate{\fs19 3} is the alternate NOR symbol. The substitutio
n works because the two
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-237 \f20 \fs19 \cf0 inve
rt bubbles between gates{\fs18 1} and{\fs19 3} cancel each other. Like
wise, the two invert bubbles between
s{\i \fs18 2} and{\fs18 3} cancel. This leaves the two OR symbols{\fs18 (1} a
nd{\i \fs18 2)} driving an AND symbol{\fs18 (3).} This is the
ern used in the original OR-AND logic diagram in Fig.{\i \fs18 5-216. }
62 The procedure for converting from a maxterm Boolean expression to a
NOR logic circuit is
lar to that used in NAND logic. The steps for converting the NOR logic are as f
ollows:
\fi370 {\fs19 1.} Draw an OR-AND logic circuit.
62 {\i \fs18 2.}
Place a bubble at each input to the AND gate.
62 {\fs19 3.}
Place a bubble at the output{\fs18 of} each OR gate.
60 4.
Check the logic levels on lines coming from the inputs and going to the
output.
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-359 \f20 \fs19 \cf0 Cons
ider the maxterm Boolean expression in Fig.{\i \fs18 5-22a.} To implement this
expression by using NOR
c, the four steps outlined above will be followed. The{\i \fs18 first}{\i \fs18
step} (Fig.{\i \fs18 5-226)} is to draw an OR-AND

c circuit. The{\i \fs18 second}{\i \fs18 step} is to place a bubble (small
circle) at each input to the AND gate. This
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-241 \f20 \fs19 \cf0 chan
ges it to a NOR gate. The "AND looking" symbol with the three bubbles at the inp
uts is then a
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-237 \f20 \fs19 \cf0 NOR
gate (Fig.{\i \fs18 5-22c).} The{\i \fs18 third}{\i \fs18 step} is to pl
ace a bubble (small circle) at the output of each OR
. The bubbles are added to gates 1 and{\i \fs18 2} in Fig.{\i \fs18 5-22c.}
The{\i \fs18 fourth}{\i \fs18 step} is to examine the input
output lines for changes in logic levels due to added bubbles. The bubble
added at point{\i Z} in
{\i \fs18 5-22c} is a change from the original OR-AND pattern. The i
nverting effect of bubble{\i \f10 \fs17 2} is
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-236 \f20 \fs19 \cf0 canc
eled by adding the shaded inverter{\fs18 4.} The double inversion (in
verter{\fs18 4} and invert bubble{\i Z}{\i ) }
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-240 \f20 \fs19 \cf0 canc
els in input line{\i E.} In actual practice, inverter{\fs18 4} would probab
ly be a NOR gate. By shorting all
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-237 \f20 \fs19 \cf0 inpu
ts together, a NOR gate becomes an inverter. The NOR and the OR-AND circui
ts pictured in
{\i \fs18 5-22} perform the same logic function.
62 The NOR gate was used as a "universal gate" in the previous example. Using N
OR logic may or
\par}{\phpg\posx857\pvpg\posy1365\absw9215\absh5587 \sl-237 \f20 \fs19 \cf0 may
not simplify the circuit. In this case the OR-AND circuit might be preferred. \p
ar
}
\cf0 Fig.{\fs16 5-22 }\par
}
OLVED PROBLEMS \par
}
cf0 5.20 \par
}
Diagram an OR-AND logic circuit for the Boolean expression{\b\i (}{\b\i A}{\f1
0 \fs30 +}{\i B}{\i ) }
\fs16 Solution: }
361 {\fs16 See}{\b \fs16 Fig.}{\i \fs17 5-23. }\par
}
-{\f10 \fs27
+ }\par
}
\cf0 ( D
E ){\i0\dn006 \f10 \fs13 =} Y. \par
}
.{\f10 \fs17 51 }\par
}
}
\par
}
\cf0 Fig.{\fs17 5-23}{\b0 \fs17
OR-AND}{\b0 \fs17 logic-circuit}{\b0 \fs17
solution }\par
}
f0 5.21 \par
}
iagram a NOR logic circuit from the OR-AND circuit in Prob.{\fs19 5.20.} The NO
R circuit should \par
}
erform the logic in the Boolean expression{\b\i \fs18 (}{\b\i \fs18 A}{\f10 \
fs28 +}{\b\i \fs19 B}{\b\i \fs19 )}{\i \f10 \fs32 c' }
\fs17 Solution: }
}
}
14 \cf0 A
{\f20 \fs15 B }\par
}
s21 \cf0 (D {\b0\i0 \f10 \fs30 +}{\f20 \fs19 E}{\f20 \fs19 )}{\b0\i0\dn006 \f
10 \fs13 =}{\b0 \f20 \fs19 Y. }\par
}
\cf0 Fig.{\f10 \fs15 5-24}{\b0 \fs17
NOR}{\b0 \fs17 logic-circuitproblem }
\par
}
f0 5.22 \par
}
iagram an OR-AND logic circuit for the Boolean expression{\i \f10 \fs23 2.}{\b
\i \fs19 (}{\b\i \fs19 B}{\f10 \fs29 + }
\fs17 Solution: }
}
{\phpg\posx7771\pvpg\posy8649\absw968\absh332 \f10 \fs27 \cf0 \f10 \fs27 \cf0 -)
{\b\i \f20 \fs19 D}{\b\i \f20 \fs19 =}{\dn006 \fs13 Y}{\i\dn006 \f20 \fs19
. }\par
}
f20 \fs15 \cf0 B

{\fs15 C }
\cf0 {\f30 \fs17 D }\par
}
\cf0 A * ( B + C ) * D ={\b \fs15 Y }\par
}
\cf0 Fig.{\f10 \fs15 5-25}{\b0 \fs17
OR-AND}{\b0 \fs17 logic-circuitsoluti
on }\par
}
cf0 5.23 \par
}
Diagram a NOR logic circuit from the OR-AND circuit in Prob.{\fs19 5.22.} The N
OR circuit should \par
}
perform the logic in the Boolean expression
\fs17 Solution: }
}
fs37 \cf0 x-{\b0\i0 \f10 \fs27 + }\par
}
s19 \cf0 ( B \par
}
fs19 \cf0 C ){\b0\i0 \f10 \fs23 -}{\b0 \fs18 D}{\b0\i0\dn006 \f10 \fs13 =}{\b
0 \fs19 Y. }\par
}
0 82 \par
}
cf0 SIMPLIFYING{\fs19 LOGIC}{\fs19 CIRCUITS:}{\fs18 MAPPING }\par
}
8 \cf0 [CHAP.{\f10 \fs17 5 }\par
}
0 \fs17 \cf0 Fig.{\fs18 5-26}{\f30 \fs21 NOR}{\fs18 logiccircuit}{\fs18 solu
tion }
f0 {\f10 \fs18 5-7}{\fs19
KARNAUCHMAPS }
fi371 {\b0 \fs20 Boolean}{\b0 \fs20 algebra}{\b0 \fs20 is}{\b0 \fs20 thc}{\b
0 \fs20 basis}{\b0 \fs20 for}{\b0 \fs20 any}{\b0 \fs20 simplification}{\b0
\fs20 of}{\b0 \fs20 logic}{\b0 \fs20 circuits.}{\b0 \fs20 One}{\b0 \fs20 o
f}{\b0 \fs20 the}{\b0 \fs20 easiest}{\f10 \fs17 ways}{\b0 \fs20 to }
\b0 \fs20 simplify}{\b0 \fs20 logic}{\b0 \fs20 circuits}{\b0 \fs20 is}{\b0 \f
s20 to}{\b0 \fs20 use}{\b0 \fs20 the}{\i \f10 \fs17 Khmuugh}{\i \f10 \fs17
m}{\i \f10 \fs17 p}{\b0 \fs20 method.}{\b0 \fs20 This}{\b0 \fs20 graphic
}{\b0 \fs20 method}{\b0 \fs19 is}{\b0 \fs20 bascd}{\b0 \fs21 on}{\fs21 Bool
can }
\b0 \fs20 theorems.}{\b0 \fs20 It}{\b0 \fs20 is}{\b0 \fs20 only}{\b0 \fs20 o
ne}{\b0 \fs20 of}{\b0 \fs20 several}{\b0 \fs20 methods}{\b0 \fs20 used}{\b0
\fs20 by}{\b0 \fs20 logic}{\b0 \fs20 designers}{\b0 \fs21 to}{\b0 \fs20 sim
plify}{\b0 \fs20 logic}{\b0 \fs20 circuits.}{\b0 \fs20 Karnaugh }
\b0 \fs20 maps}{\b0 \fs20 are}{\b0 \fs20 sometimes}{\b0 \fs20 referred}{\f10
\fs17 to}{\b0 \fs20 as}{\i \f30 \fs23 K}{\i \f10 \fs17 maps. }
fi371 {\b0 \fs20 The}{\i \f10 \fs15 first}{\i \f10 \fs17 step}{\b0 \fs20 i
n}{\b0 \fs20 the}{\b0 \fs20 Karnaugh}{\b0 \fs20 mapping}{\b0 \fs20 proccdu
rc}{\b0 \fs20 is}{\b0 \fs20 to}{\b0 \fs20 develop}{\b0 \fs20 a}{\b0 \fs20
minterm}{\b0 \fs20 Boolean}{\b0 \fs20 expression }
fi22 {\b0 \fs20 from}{\b0 \fs20 a}{\b0 \fs20 truth}{\b0 \fs20 table.}{\b0 \fs
20 Consider}{\b0 \fs20 the}{\b0 \fs20 familiar}{\b0 \fs20 truth}{\b0 \fs20
table}{\b0 \fs20 in}{\b0 \fs20 Fig.}{\i \f10 \fs17 S-27a.}{\b0 \fs20 Each}{
\f10 \fs18 1}{\b0 \fs21 in}{\b0 \fs20 the}{\i \f30 \fs22 Y}{\b0 \fs20 colum
n}{\b0 \fs20 of}{\b0 \fs20 the}{\b0 \fs20 truth }
fi27 {\b0 \fs20 table}{\b0 \fs20 produces}{\b0 \fs20 two}{\b0 \fs20 variab
les}{\b0 \fs20 ANDed}{\b0 \fs20 together.}{\b0 \fs19 These}{\b0 \fs20 AN
Ded}{\b0 \fs20 groups}{\b0 \fs20 are}{\b0 \fs20 thcn}{\b0 \fs20 ORed}{\f
10 \fs17
to}{\b0 \fs20 form}{\b0 \fs20 a }
fi21 {\b0 \fs20 sum-of-products(minterm)}{\b0 \f30 \fs18 type}{\b0 \fs20 of}{\
b0 \fs20 Boolean}{\b0 \fs20 exprcssion}{\b0 \fs20 (Fig.}{\f10 \fs18 5-276).}
{\b0 \fs20 This}{\b0 \fs20 expression}{\b0 \fs19 will}{\b0 \f10 \fs18 be}{\b
0 \fs20 referred}{\f10 \fs17 to }
fi21 {\b0 \fs20 as}{\b0 \fs20 the}{\i \f10 \fs17 unsimpiijied}{\b0 \fs20 Boo
lean}{\b0 \fs20 expression.}{\b0 \fs20 The}{\i \f10 second}{\i \fs20 srep}{\
b0 \fs20 in}{\b0 \fs20 the}{\b0 \fs20 mapping}{\b0 \fs20 procedurc}{\b0 \fs
20 is}{\b0 \fs20 to}{\b0 \fs20 plot}{\f10 \fs18 1s}{\b0 \fs20 in}{\b0 \fs2
0 the }
fi29 {\b0 \fs20 Karnaugh}{\b0 \fs20 map}{\b0 \fs20 in}{\b0 \fs20 Fig.}{\f10 \
fs18 5-27c.}{\b0 \fs20 Each}{\b0 \fs20 ANDed}{\b0 \fs20 set}{\b0 \fs20 of}{
\b0 \fs20 variables}{\b0 \fs20 from}{\b0 \fs20 the}{\b0 \fs20 minterm}{\b0 \
fs20 expression}{\b0 \fs20 is}{\b0 \fs20 placed}{\b0 \fs20 in }\par
}
\cf0 Fig.{\f10 \fs17 5-27}{\fs18 Using}{\f10 \fs15 a}{\fs17 map }\par
}
.{\b \f10 \fs16 51 }\par
}
}
\par
}
he{\b\i \fs19 appropriate} square{\fs19 of}{\b \fs20 thc} map.{\fs20 The}

map{\fs19 is} just a{\b \f10 \fs17 very} special output column{\fs19 of}
the{\fs18 truth} table.
\par}{\phpg\posx837\pvpg\posy1368\absw9536\absh2009 \sl-237 \f20 \fs19 \cf0 The{
\fs18 third} step is{\b \f10 \fs17 to}{\b\i \f10 \fs17 loop} adjacent gr
oups{\fs20 of}{\b \f10 \fs17 two,} four,{\fs20 or} eight{\b \f30 \fs20 Is}
together. Figure{\b\i \f10 \fs19 5-27d} shows{\fs20 two }
\par}{\phpg\posx837\pvpg\posy1368\absw9536\absh2009 \sl-242 \f20 \fs19 \cf0 loop
s drawn on the map. Each loop contains{\b \f10 \fs17
two}{\fs19 Is.}
The{\b\i \fs19 foiuth}{\fs18 step}{\fs19 is}{\b\i \fs20 to} eliminatc
variables.
\par}{\phpg\posx837\pvpg\posy1368\absw9536\absh2009 \sl-260 \f20 \fs19 \cf0 Cons
idcr first the shaded loop{\fs20 in} Fig.{\b\i \f10 \fs19 5-27d.}{\b \fs1
9 Note} that{\fs20 a}{\b\i \f10 \fs19 5} and{\b \f10 \fs16 a}{\b\i \fs2
6 E}{\fs19 (not}{\b\i \f10 \fs18 R}{\b\i \f10 \fs18 )}{\b \f10 \fs17 are
} containcd within
shaded loop.{\b\i \f10 \fs19 Wien}{\b\i \fs19 a}{\b\i \fs19 rariable}{\b\
i \f10 \fs17 and}{\b\i \f10 \fs15 its}{\b\i \fs19 cornplcrncnt}{\b\i \fs19
are}{\b\i \fs19 within}{\b\i \fs19 a}{\b\i \fs19 loop.}{\b\i \fs19 that
}{\b\i \fs19 iaariable}{\b\i \fs19 is}{\b\i \fs19 eliminated. }
\par}{\phpg\posx837\pvpg\posy1368\absw9536\absh2009 \sl-236 \f20 \fs19 \cf0 From
{\fs19 thc} shaded{\fs18 Imp,}{\b thc}{\b\i R} and
terms arc elimina
ted, leaving the{\b\i \f10 \fs17 A} variable (Fig.{\b\i \f10 \fs19 5-27~).}N
ext
ider{\b \f10 \fs17 the} unshadcd{\b \f10 \fs17 loop}{\fs19 in} Fig.{\b\i \f1
0 \fs19 5-276.}{\fs18 It} contains an{\b\i \f10 \fs18 A} and{\b \f10 \fs16
a}{\b \fs19 A(not}{\b\i \f10 \fs18 A).} The{\b\i \f10 \fs18 A} and Atc
rms{\b \f10 \fs17 are }
\par}{\phpg\posx837\pvpg\posy1368\absw9536\absh2009 \sl-249 \f20 \fs19 \cf0 elim
inated, leaving only the{\b\i \f10 \fs17 U} variable (Fig.{\b\i \f10 \fs19 5
-27e).}{\b \fs20 Thc}{\b\i \fs19 fifth}{\b\i \fs19 step}{\fs19 is}{\b \f10
\fs17 to}{\fs20 OR} thc remaining variables.
\f30 \fs20 Thc} final{\b\i \f10 \fs17 simplijied}{\b \fs19 Fkwlean} cxpressio
n{\b \f10 \fs18 is}{\b\i \f10 \fs17 A}{\f10 \fs21 +}{\b\i \f10 \fs18 8}{\dn0
06 \f10 \fs15 =}{\b\i \fs19 Y} (Fig.{\b\i \fs19 5-27e).}The simplified cxpres
sion is that{\fs19 of }\par
}
{\phpg\posx855\pvpg\posy3531\absw1663\absh229 \f20 \fs19 \cf0 \f20 \fs19 \cf0 a{
\fs19 2-input}{\fs20 OR}{\b \f10 \fs16 gatc. }\par
}
\cf0 Pig.{\f10 \fs15 5-28}{\fs17
Using}{\f10 \fs15 a}{\fs17 thrcc-variabl
c}{\fs17 map }\par
}
par
}
}
AP.{\fs17 5 }\par
}
\cf0 In summary, the steps in simplifying a logic expression using a Karnaugh m
ap are as follows:
78 1. Write a minterm Boolean expression from the truth table.
68 {\i \fs18 2.}
Plot a 1 on the map for each ANDed group of variables. (T
he number of 1s in the{\b\i \fs19 Y} column
20 of the truth table will equal the number of{\fs18 Is} on the map.)
68 3.
Draw loops around adjacent groups of two, four, or eight{\fs19
1s} on the map. (The loops may
19 overlap.)
68 {\fs18 4.}
Eliminate the variable(s) that appear(s) with its (their) comp
lement(s) within a loop, and save
20 the variable(s) that is (are) left.
68 {\fs19 5.} Logically{\fs19 OR} the groups that remain to form the simplif
ied minterm expression.
69 Consider the truth table in Fig.{\i \fs18 5-28a.} The{\i \fs18 first}{\i
\fs18 step} in using the Karnaugh map is to write the
\par}{\phpg\posx841\pvpg\posy1359\absw9241\absh3853 \sl-239 \f20 \fs18 \cf0 mint
erm Boolean expression for the truth table. Figure{\i \fs18 5-28b} ill
ustrates the unsimplified minterm
ession for the truth table. The{\i \fs18 second}{\i \fs18 step} is plotti
ng{\fs19 Is} on the map. Five{\fs19 1s} are plotted on the
\par}{\phpg\posx841\pvpg\posy1359\absw9241\absh3853 \sl-245 \f20 \fs18 \cf0 map
in Fig.{\i \fs18 5-28c.} Each 1 corresponds to an ANDed group{\fs18 of} vari
ables (such as{\b\i A}{\f10 \fs27 -}{\i \fs19 B}{\f10 \fs27 -}{\i \fs18 C)
.} The{\i \fs18 third }
\fs18 step} is to loop adjacent groups{\fs18 of}{\fs18 Is} on{\fs18 the} map.
Loops are placed around groups of eight, four, or{\fs18 two }
4 1s. Two loops are drawn on the map in Fig.{\i \fs18 5-28d.} The shaded loop c
ontains two{\fs18 1s.} The larger loop
\par}{\phpg\posx841\pvpg\posy1359\absw9241\absh3853 \sl-235 \f20 \fs18 \cf0 cont
ains four{\fs18 1s.}The{\i \fs18 fourth}{\i \fs18 step} is to eliminate vari
ables.{\fs19 The} shaded loop in Fig.{\i \fs18 5-28d} contains both \par
}
e{\i \fs19 C} and{\fs35 c }\par
}
erms. The{\i \fs19 C} variable can thus be eliminated, leaving the{\i \fs1
9 x}{\i \fs19 .}{\i \fs19 B} term. The large loop \par
}
ntains the{\b\i A} and{\i \f30 \fs29 A} as well as the{\i \fs19 B} an
d \par
}
erms. These can be eliminated, leaving only the \par
}
cf0 C{\i0 \fs18 variable.}{\i0 \fs18 The} fifth step{\i0 \fs18 is}{\i0 \fs
18 to}{\i0 \fs19 OR}{\i0 \fs18 the}{\i0 \fs18 remaining}{\i0 \fs18 terms

.}{\i0 \fs18 The} C{\i0 \fs18 and}{\fs19 A}{\fs19 -}{\fs19 B}{\i0 \fs18
terms}{\i0 \fs18 are}{\i0 \fs18 ORed}{\i0 \fs18 in}{\i0 \fs18 Fig. }
\par}{\phpg\posx843\pvpg\posy6114\absw9046\absh851 \sl-236 \i \f20 \fs18 \cf0 528e.{\i0 \fs18 The}{\i0 \fs18 final}{\i0 \fs18 simplified}{\i0 \fs18 Boolean
}{\i0 \fs18 expression}{\i0 \fs18 is}{\i0 \fs18 then}{\fs19 C}{\i0 \f10 \fs
28 +}{\f30 \fs27 A-}{\dn006 \fs19 B}{\i0 \f10 \fs14 =}{\b \fs19 Y.}{\i0 \fs1
8 This}{\i0 \fs18 is}{\i0 \fs18 much}{\i0 \fs18 easier}{\i0 \fs18 to}{\i0 \f
s18 implement }
i0 \fs18 with}{\i0 \fs18 ICs}{\i0 \fs18 than}{\i0 \fs18 the}{\i0 \fs18 unsim
plified}{\i0 \fs18 version}{\i0 \fs18 of}{\i0 \fs18 Fig.} 5-28b.{\i0 \fs18 T
he}{\i0 \fs18 simplified}{\i0 \fs18 expression}{\i0 \fs18 will}{\i0 \fs18 ge
nerate}{\i0 \fs18 the}{\i0 \fs18 truth }
i0 \fs18 table}{\i0 \fs18 in}{\i0 \fs18 Fig.} 5-28a. \par
}
LVED PROBLEMS
\b \fs17 5.24}{\f20 \fs18
Write}{\f20 \fs18 the}{\f20 \fs18 unsimplified}
{\f20 \fs18 minterm}{\f20 \fs18 Boolean}{\f20 \fs18 expression}{\f20 \fs18
for}{\f20 \fs18 the}{\f20 \fs18 truth}{\f20 \fs18 table}{\f20 \fs18 in}{\f2
0 \fs18 Fig.}{\i \f20 \fs18 5-29. }\par
}
\cf0 Inputs
\b\i \fs16 A}{\b\i \fs16
B}{\b\i \fs16
C }\par
}
r
}
r
}
r
}
utput
\fi239 {\b\i \fs16 Y }
\fi251 {\f10 \fs15 1 }
31 {\f10 \fs16 0 }
51 {\f10 \fs15 1 }
31 {\f10 \fs16 0 }\par
}
puts \par
}
\f20 \fs16 \cf0 A
\cf0 \fi586 {\b0\i0 \f10 \fs15 1 }
\fi584 {\i0 \f10 \fs15 1 }
\fi586 {\b0\i0 \f10 \fs15 1 }
\fi586 {\b0\i0 \f10 \fs15 1 }
\cf0 {\i0 \fs16 Fig.}{\i0 5-29 }\par
}
s16 \cf0 B
\cf0 \fi24 {\b0\i0 \f10 \fs15 0 }
\fi25 {\i0 \f10 \fs15 0 }
\fi24 {\b0\i0 \f10 \fs15 1 }
\fi30 {\b0\i0 \f10 \fs15 1 }\par
}
s16 \cf0 C
\cf0 {\b0\i0 \f10 \fs15 0 }
\fi20 {\i0 \f10 \fs15 1 }
{\b0\i0 \f10 \fs15 0 }
\fi28 {\b0\i0 \f10 \fs15 1 }\par
}
utput
\fi241 {\b\i \fs16 Y }
\fi237 {\f10 \fs16 0 }
55 {\f10 \fs15 1 }
33 {\f10 \fs16 0 }
57 {\f10 \fs15 1 }\par
}
\cf0 Solution:
\fi340 {\b0\i \fs20 A}{\b0\i\dn006 \fs20 .}{\b0\i \fs20 B}{\b0\i \fs20 .}{\b0
\i \fs20 C}{\b0\i \fs20 +}{\b0\i \fs20 A}{\b0\i \fs20 .}{\b0\i \fs20 B}{\b0
\i \fs20 .}{\b0 \fs20 C+}{\i \fs16 A}{\i \f30 \fs19 .B.}{\b0\i \fs25 c }\par
}
s16 \cf0 + A{\fs16 .}{\fs16 B}{\b0\i0 \f10 \fs23 -}{\b0 \fs25 c }\par
}
{\i \f20 \fs17 Y }\par
}
cf0 5.25 \par
}
Draw a 3-variable Karnaugh map. Plot four 1s on the map from the Boo
lean expression
\par}{\phpg\posx1411\pvpg\posy12507\absw8436\absh970 \sl-235 \f20 \fs18 \cf0 dev
eloped in Prob.{\i \fs18 5.24.} Draw the appropriate loops around groups of{\f
s18 Is} on the map.
354 {\b \fs16 See}{\b \fs16 Fig.}{\i \fs17 5-30. }\par
}
.{\f10 \fs17 51 }\par
}
}
\par
}
\par
}
cf0 l.B \par
}
16 \cf0 1 . B \par
}
16 \cf0 A . B \par
}
16 \cf0 A * B \par
}
7 \cf0 5.26 \par
}
0 \fs17 \cf0 Fig.{\fs17 5-30}{\b0 \fs17
Karnaugh}{\b0 \fs17 map}{\b0 \fs17
solution }
f0 {\b0 \fs19 Write}{\b0 \fs19 the}{\b0 \fs19 simplified}{\b0 \fs19 Boolean}{
\b0 \fs19 expression}{\b0 \fs19 based}{\b0 \fs19 on}{\b0 \fs19 the}{\b0 \fs
19 Karnaugh}{\b0 \fs19 map}{\b0 \fs19 from}{\b0 \fs19 Prob.}{\b0 \fs19 5.25
. }\par
}
cf0 Solution: \par
}

\cf0 A-{\b\dn006 \f10 \fs16 +C}{\b \f10 \fs16 }{\b \f10 \fs16
A}{\b \f10
\fs16 *}{\b \f10 \fs16 C}{\i0 \f10 \fs13 =}{\b \f20 \fs17 Y }\par
}
\cf0 5-8{\f20 \fs19
KARNAUGH}{\i \f20 \fs19 MAPS}{\f20 \fs18 WITH}{\f20 \fs
19 FOUR}{\f20 \fs18 VARIABLES }
fi360 {\b0 \f20 \fs19 Consider}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 truth}{\b0
\f20 \fs19 table}{\b0 \f20 \fs19 with}{\b0 \f20 \fs19 four}{\b0 \f20 \fs19 v
ariables}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5-31a.}{\b0
\f20 \fs19 The}{\i \f20 \fs18 first}{\i \f20 \fs18 step}{\b0 \f20 \fs19 in}
{\b0 \f20 \fs19 simplification}{\b0 \f20 \fs19 by}{\b0 \f20 \fs19 using}{\b0
\f20 \fs19 a }
\b0 \f20 \fs19 Karnaugh}{\b0 \f20 \fs19 map}{\b0 \f20 \fs19 is}{\b0 \f20 \fs
19 to}{\b0 \f20 \fs19 write}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 minterm}
{\b0 \f20 \fs19
Boolean}{\b0 \f20 \fs19 expression.}{\b0 \f20 \fs19 The}{
\b0 \f20 \fs19 lengthy}{\b0 \f20 \fs19 unsimplified}{\b0 \f20 \fs19 minter
m }
\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 appears}{\b0 \f20 \fs19 in}{\b0 \f
20 \fs19 Fig.}{\b0 \f20 \fs19 5-31b.}{\i \fs17 An}{\b0 \f20 \fs19 ANDed}{\b0
\f20 \fs19 group}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 four}{\b0 \f20 \fs19 v
ariables}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 written}{\b0 \f20 \fs19 for}{\b0
\f20 \fs19 each}{\b0 \f20 \fs18 1}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{
\i \f20 \fs19 Y }
\b0 \f20 \fs19 column}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19
truth}{\b0 \f20 \fs19 table.}{\b0 \f20 \fs19 The}{\i \f20 \fs18 second}{\i \
f20 \fs18 step}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 plot}
{\b0 \f20 \fs19 1s}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 K
.arnaugh}{\b0 \f20 \fs19 map.}{\b0 \f20 \fs19 Nine}{\b0 \f20 \fs19 1s}{\b0 \
f20 \fs19 are}{\b0 \f20 \fs19 plotted}{\b0 \f20 \fs19 on }
\b0 \f20 \fs19 the}{\b0 \f20 \fs19 map}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig
.}{\b0 \f20 \fs19 5-31c.}{\b0 \f20 \fs19 Each}{\b0 \f20 \fs18 1}{\b0 \f20 \fs
19 on}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 map}{\b0 \f20 \fs19 represents}{\b0
\f20 \fs19 an}{\b0 \f20 \fs19 ANDed}{\b0 \f20 \fs19 group}{\b0 \f20 \fs19 o
f}{\b0 \f20 \fs19 terms}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 the}{\b0 \f20 \f
s19 unsimplified }
\b0 \f20 \fs19 expression.}{\b0 \f20 \fs19 The}{\i \f20 \fs18 third}{\i \f20
\fs18 step}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 loop}{\b0
\f20 \fs19 adjacent}{\b0 \f20 \fs19 groups}{\b0 \f20 \fs18 of}{\b0 \f20 \fs
19 1s.}{\b0 \f20 \fs19 Adjacent}{\b0 \f20 \fs19 groups}{\b0 \f20 \fs19 of}
{\b0 \f20 \fs19 eight,}{\b0 \f20 \fs19 four,}{\b0 \f20 \fs19 or}{\b0 \f20 \f
s19 two}{\b0 \f20 \fs19 1s }
\b0 \f20 \fs19 are}{\b0 \f20 \fs19 looped.}{\b0 \f20 \fs19 Larger}{\b0 \f20 \f
s19 loops}{\b0 \f20 \fs19 provide}{\b0 \f20 \fs19 more}{\b0 \f20 \fs19 simp
lification.}{\b0 \f20 \fs19 Two}{\b0 \f20 \fs19 loops}{\b0 \f20 \fs19 have}{\
b0 \f20 \fs19 been}{\b0 \f20 \fs19 drawn}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19
Fig.}{\b0 \f20 \fs19 5-31c.}{\b0 \f20 \fs19 The }
\b0 \f20 \fs19 larger}{\b0 \f20 \fs19 loop}{\b0 \f20 \fs19 contains}{\b0 \f20
\fs19 eight}{\b0 \f20 \fs19 1s.}{\b0 \f20 \fs19 The}{\i \f20 \fs18 fourt
h}{\i \f20 \fs18 step}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19
eliminate}{\b0 \f20 \fs19 variables.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 l
arge}{\b0 \f20 \fs19 loop}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20
\fs19 5-31c }
\b0 \f20 \fs19 eliminates}{\b0 \f20 \fs19 the}{\i \f20 \fs18 A,}{\b0\i \f20
\fs19 B,}{\b0 \f20 \fs19 and}{\i \f20 \fs19 C}{\b0 \f20 \fs19 variables.}{
\b0 \f20 \fs19 This}{\b0 \f20 \fs19 leaves}{\b0 \f20 \fs19 the}{\b0\i \f20
\fs19 D}{\b0 \f20 \fs19 term.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 small}{
\b0 \f20 \fs19 loop}{\b0 \f20 \fs19 contains}{\b0 \f20 \fs18 two}{\b0 \f20
\fs19 1s}{\b0 \f20 \fs19 and }\par
}
c) Plotting and looping{\b 1s} on map
03 {\b\i \fs18 C}{\b\i \fs18 .}{\b\i \fs18 6}{\b\i \fs17
C}{\b\i \fs17
.}{\b\i \fs17 0}{\b\i \fs15
C}{\b\i \fs15 *}{\b\i \fs15 D}{\b\i \fs15
C}{\b\i \fs15 .}{\b\i \fs15 6 }\par
}
s15 \cf0 D \par
}
7 \cf0 (d){\fs17 Simplified}{\fs17 Boolean}{\fs17 expression: }
{\b Fig.}{\b 5-31}{\fs17
Using}{\b \fs17 a}{\fs17 four-variable}{\fs17 m
ap }\par
}
fs17 \cf0 D{\b0\i0 \f10 \fs24 +}{\b0 \fs20 A}{\b0\i0\dn006 \f10 \fs16 .}{\fs
17 B}{\b0\i0 \f10 \fs23 -}{\i0 \f30 \fs19 C }\par
}
{\b\i \f20 \fs16 Y }\par
}
0 86 \par
}
}
AP.{\i \fs17 5 }\par
}
liminates the{\i D} variable. That leaves the{\i \fs19 A}{\i \fs19 -}
{\i \fs19 B}{\fs19 .}{\fs19 C} term. The fifth step is to logically{\fs
19 OR} the
\par}{\phpg\posx841\pvpg\posy1339\absw9152\absh1711 \sl-237 \f20 \fs18 \cf0 rema
ining terms. Figure 5-31d shows the remaining groups ORed to form the
simplified minterm
ession{\i D}{\f10 \fs28 +}{\i \f30 \fs25 2.}{\f10 \fs23 - }
2 Boolean expressions in Fig. 5-31 are compared.
68 Consider the 3-variable Karnaugh map in Fig. 5-32a. The letters hav
e been omitted from the
\par}{\phpg\posx841\pvpg\posy1339\absw9152\absh1711 \sl-235 \f20 \fs18 \cf0 edge
s of the map to simplify the illustration. How many loops can be drawn on t
his map? There are

\fs19 no} adjacent{\i groups}{\fs18 of}{\i \fs19 Is,} and therefore no loops
are drawn in Fig. 5-32a. No simplification is possible
he example shown in Fig. 5-32a. \par
}
\cf0 B{\i0 \fs19
C}{\i0\dn006 \f10 \fs13 =}{\b Y.}{\i0 \fs18 The}{\i0 \fs1
8 amount}{\i0 \fs18 of}{\i0 \fs18 simplification}{\i0 \fs18 in}{\i0 \fs18
this}{\i0 \fs18 example}{\i0 \fs18 is}{\i0 \fs18 obvious}{\i0 \fs18 whe
n}{\i0 \fs18 the}{\i0 \fs18 two }\par
}
0 \fs16 \cf0 Fig.{\fs16 5-32}{\b0 \fs17
Some}{\b0 \fs17 unusual}{\b0 \fs17
loopingvariations }
f0 \fi367 {\b0 \fs18 The}{\b0 \fs18 3-variable}{\b0 \fs18 Karnaugh}{\b0 \fs18
map}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 5-326}{\b0 \fs18 contains}{\b
0 \fs18 two}{\b0 \fs19 Is.}{\b0 \fs18 Think}{\b0 \fs18 of}{\b0 \fs18 the}{\
b0 \fs18 top}{\b0 \fs18 and}{\b0 \fs18 bottom}{\b0 \fs18 edges}{\b0 \fs18 o
f }
\b0 \fs18 the}{\b0 \fs18 map}{\b0 \fs18 as}{\b0 \fs18 being}{\b0 \fs18 conne
cted}{\b0 \fs18 as}{\b0 \fs18 if}{\b0 \fs18 rolled}{\b0 \fs18 into}{\b0 \fs
18 a}{\b0 \fs18 tube.}{\b0 \fs18 The}{\b0 \fs18 1s}{\b0 \fs18 can}{\b0 \fs1
8 then}{\b0 \fs18 be}{\b0 \fs18 looped}{\b0 \fs18 into}{\b0 \fs18 a}{\b0 \f
s18 group}{\b0 \fs18 of}{\b0 \fs18 two,}{\b0 \fs18 as }
\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 5-326.}{\b0 \fs18 O
ne}{\b0 \fs18 variable}{\b0 \fs18 can}{\b0 \fs18 thus}{\b0 \fs18 be}{\b0 \
fs18 eliminated. }
fi361 {\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 4-variable}{\b0 \fs18 K
arnaugh}{\b0 \fs18 maps}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 5-32c}{\
b0 \fs18 and}{\b0\i \f10 \fs18 d.}{\b0 \fs18 The}{\b0 \fs18 top}{\b0 \fs18
and}{\b0 \fs18 bottom}{\b0 \fs18 edges}{\b0 \fs19 of}{\b0 \fs18 the }
\b0 \fs18 map}{\b0 \fs18 are}{\b0 \fs18 considered}{\b0 \fs18 connected}{\b0
\fs18 for}{\b0 \fs18 looping}{\b0 \fs18 purposes}{\b0 \fs19 in}{\b0 \fs18
Fig.}{\b0 \fs18 5-32c.}{\b0 \fs18 The}{\b0 \fs18 1s}{\b0 \fs18 can}{\b0 \
fs18 then}{\b0 \fs18 be}{\b0 \fs18 looped}{\b0 \fs18 into}{\b0 \fs18 a }
\b0 \fs18 group}{\b0 \fs19 of}{\b0 \fs18 four}{\b0 \fs19 Is,}{\b0 \fs18
and}{\b0 \fs18 two}{\b0 \fs18 terms}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \f
s18 eliminated.}{\b0 \fs18 In}{\b0 \fs18 Fig.}{\b0 \fs18 5-32d}{\b0 \fs1
8 the}{\b0 \fs18 right}{\b0 \fs18 edge}{\b0 \fs18 of}{\b0 \fs18 the}{\
b0 \fs18 map}{\b0 \fs18 is }
\b0 \fs18 considered}{\b0 \fs18 connected}{\b0 \fs18 to}{\b0 \fs18 the}{\b0
\fs18 left}{\b0 \fs18 edge.}{\b0 \fs18 The}{\b0 \fs18 four}{\b0 \fs18 1
s}{\b0 \fs18 are}{\b0 \fs18 looped}{\b0 \fs18 into}{\b0 \fs18 a}{\b0 \fs18
single}{\b0 \fs18 loop.}{\b0 \fs18 Two}{\b0 \fs18 variables}{\b0 \fs18
are }
\b0 \fs18 thus}{\b0 \fs18 eliminated. }
fi359 {\b0 \fs18 Another}{\b0 \fs18 looping}{\b0 \fs18 variation}{\b0 \fs18
is}{\b0 \fs18 illustrated}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 5-3
2e.}{\b0 \fs18 The}{\b0 \fs18 corners}{\b0 \fs19 of}{\b0 \fs18 the}{\b0
\fs18 map}{\b0 \fs18 are}{\b0 \fs18 considered }

\b0 \fs18 connected}{\b0 \fs18 as}{\b0 \fs18 if}{\b0 \fs18 the}{\b0 \fs18 ma
p}{\b0 \fs18 were}{\b0 \fs18 wrapped}{\b0 \fs18 around}{\b0 \fs18 a}{\b0 \f
s18 ball.}{\b0 \fs18 The}{\b0 \fs18 four}{\b0 \fs18 1s}{\b0 \fs18 in}{\b0
\fs18 \{he}{\b0 \fs18 corners}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 map}{
\b0 \fs18 are}{\b0 \fs18 then }
\b0 \fs18 looped}{\b0 \fs18 into}{\b0 \fs18 a}{\b0 \fs18 single}{\b0 \fs18 l
oop.}{\b0 \fs18 The}{\b0 \fs18 single}{\b0 \fs18 loop}{\b0 \fs18 of}{\b0 \fs
18 four}{\b0 \fs18 1s}{\b0 \fs18 thereby}{\b0 \fs18 eliminates}{\b0 \fs18
two}{\b0 \fs18 variables. }\par
}
LVED PROBLEMS
fs17 5.27}{\f20 \fs18
Write}{\f20 \fs18 the}{\f20 \fs18 unsimplified}{\f2
0 \fs18 minterm}{\f20 \fs18 Boolean}{\f20 \fs18 expression}{\f20 \fs18 fo
r}{\f20 \fs18 the}{\f20 \fs18 truth}{\f20 \fs18 table}{\f20 \fs18 in}{\f20
\fs18 Fig.}{\f20 \fs18 5-33. }\par
}
nputs \par
}
fs16 \cf0 B
\cf0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 1 }
0 \fi22 {\b0\i0 \f10 \fs15 1 }\par
}
nputs \par
}
fs16 \cf0 B
\cf0 \fi31 {\b0\i0 \f10 \fs15 0 }
0 \fi35 {\b0\i0 \f10 \fs15 0 }
0 \fi33 {\b0\i0 \f10 \fs15 0 }
0 \fi39 {\b0\i0 \f10 \fs15 0 }
0 \fi37 {\b0\i0 \f10 \fs15 1 }
0 \fi39 {\b0\i0 \f10 \fs15 1 }
0 \fi37 {\b0\i0 \f10 \fs15 1 }

0 \fi39 {\b0\i0 \f10 \fs15 1 }\par
}
fs16 \cf0 C
\cf0 \fi29 {\b0\i0 \f10 \fs15 0 }
0 \fi34 {\b0\i0 \f10 \fs15 0 }
0 \fi31 {\b0\i0 \f10 \fs15 1 }
0 \fi38 {\b0\i0 \f10 \fs15 1 }
0 \fi35 {\b0\i0 \f10 \fs15 0 }
0 \fi37 {\b0\i0 \f10 \fs15 0 }
0 \fi35 {\b0\i0 \f10 \fs15 1 }
0 \fi38 {\b0\i0 \f10 \fs15 1 }\par
}
fs16 \cf0 A
\cf0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 \fi22 {\b0\i0 \f10 \fs15 0 }\par
}
fs16 \cf0 C
\cf0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 1 }
0 \fi23 {\b0\i0 \f10 \fs15 1 }\par
\sl-216 \b\i \f20 \fs16 \cf

\f20 \fs16 \cf0 \b\i \f20 \
\sl-246 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf
\sl-217 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\sl-222 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\f20 \fs16 \cf0 \b\i \f20 \
\sl-246 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf
\sl-217 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\sl-222 \b\i \f20 \fs16 \cf
\sl-210 \b\i \f20 \fs16 \cf
\sl-222 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\f20 \fs16 \cf0 \b\i \f20 \
\sl-246 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf
\sl-217 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
\sl-222 \b\i \f20 \fs16 \cf
\sl-210 \b\i \f20 \fs16 \cf
\sl-222 \b\i \f20 \fs16 \cf
\sl-216 \b\i \f20 \fs16 \cf
}
fs16 \cf0 D
\cf0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 0 }
0 \fi34 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 0 }
0 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \f10 \fs15 0 }
0 \fi24 {\b0\i0 \f10 \fs15 1 }\par
}
utput
\fi246 {\b\i \fs16 Y }\par
}
\f20 \fs16 \cf0 A
\cf0 \fi531 {\b0\i0 \f10 \fs15 1 }
0 \fi534 {\b0\i0 \f10 \fs15 1 }
0 \fi534 {\b0\i0 \f10 \fs15 1 }
0 \fi538 {\b0\i0 \f10 \fs15 1 }
0 \fi538 {\b0\i0 \f10 \fs15 1 }
0 \fi540 {\b0\i0 \f10 \fs15 1 }
0 \fi538 {\b0\i0 \f10 \fs15 1 }
0 \fi538 {\b0\i0 \f10 \fs15 1 }
\cf0 {\i0 \fs16 Fig.}{\i0 \fs17 5-33 }\par
}
fs16 \cf0 D
\cf0 \fi26 {\b0\i0 \f10 \fs15 0 }
0 \fi34 {\b0\i0 \f10 \fs15 1 }
0 \fi28 {\b0\i0 \f10 \fs15 0 }
0 \fi38 {\b0\i0 \f10 \fs15 1 }
0 \fi32 {\b0\i0 \f10 \fs15 0 }
0 \fi34 {\b0\i0 \f10 \fs15 1 }

0 \fi32 {\b0\i0 \f10 \fs15 0 }
0 \fi38 {\b0\i0 \f10 \fs15 1 }\par
}
utput
\fi243 {\b\i \fs16 Y }\par
}
.{\b \f10 \fs16 51 }\par
}
}
\par
}
f0 5.28 \par
}
raw a 4-variable Karnaugh map. Plot six 1s on the map from the Bool
ean expression
\par}{\phpg\posx1449\pvpg\posy2260\absw8473\absh975 \sl-231 \f20 \fs19 \cf0 deve
loped in Prob. 5.27. Draw the appropriate loops around groups of{\fs18 Is} on
the map.
}
\cf0 Fig. 5-34{\b0 \fs17
Karnaugh}{\fs16 map}{\b0 \fs17 solution }\par
}
\cf0 5.29{\b0 \f20 \fs19
Write}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 simpli
fied}{\b0 \f20 \fs19 Boolean}{\b0 \f20 \fs19 expression}{\b0 \f20 \fs19 based
}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 Karnaugh}{\b0 \f20 \
fs19 map}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 Prob.}{\b0 \f20 \fs19 5.28. }
fi604 {\f20 \fs16 Solution: }
fi1598 {\b0 \f10 \fs3 -}{\b0 \f10 \fs3
_}{\b0 \f10 \fs3
. }
fi950 {\b0\i \f20 \fs16 A}{\b0\i \f20 \fs16 .}{\b0\i \f20 \fs16 C}{\b0\i \f20
\fs16 +}{\b0\i \f20 \fs16 A}{\b0\i \f20 \fs16 *}{\b0\i \f20 \fs16 C}{\b0\i \
f20 \fs16 -}{\b0\i \f20 \fs16 D}{\b0\i \f20 \fs16 =}{\b0\i \f20 \fs16 Y }
f0 5.30{\b0 \f20 \fs19
Write}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 unsimplif
ied}{\b0 \f20 \fs19 sum-of-products}{\b0 \f20 \fs19 Boolean}{\b0 \f20 \fs19 e
xpression}{\b0 \f20 \fs19 for}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 truth}{\b0
\f20 \fs19 table}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 5
-35. }\par
}
puts \par
}
s16 \cf0 B
\cf0 {\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 1 }\par
}
s16 \cf0 C
\cf0 {\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 1 }
\fi23 {\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 1 }\par
}
puts
fi43 {\b\i \fs16 B}{\b\i \fs16
C }\par
}
{\phpg\posx6993\pvpg\posy8413\absw995\absh903 \f10 \fs28 \cf0 \f10 \fs28 \cf0 I{
\f20 \fs17
Output }
fs46 I}{\b \fs46
y }\par
}
s16 \cf0 A
\cf0 {\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }

{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }\par
}
s16 \cf0 D
\cf0 {\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 0 }
\fi27 {\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 1 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 1 }\par
}
utput
\fi243 {\b\i Y }
\fi257 {\b \f10 \fs15 1 }
37 {\b \f10 \fs15 0 }
63 {\b \f10 \fs16 1 }
41 {\b \f10 \fs15 0 }
63 {\b \f10 \fs16 1 }
41 {\b \f10 \fs15 0 }
63 {\b \f10 \fs15 1 }
41 {\b \f10 \fs16 0 }\par
}
s16 \cf0 A
\cf0 \fi33 {\i0 \f10 \fs15 1 }
\fi35 {\i0 \f10 \fs15 1 }
\fi35 {\i0 \f10 \fs15 1 }
\fi35 {\i0 \f10 \fs15 1 }
\fi35 {\i0 \f10 \fs15 1 }
\sl-215 \b\i \f20 \fs16 \cf0

\sl-222 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\f20 \fs16 \cf0 \b\i \f20 \f
\sl-248 \par\b\i \f20 \fs16
\sl-222 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\sl-215 \b\i \f20 \fs16 \cf0
\sl-222 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 o
\sl-219 \par\f20 \fs17 \cf0
\sl-248 \par\f20 \fs17 \cf0
\sl-222 \f20 \fs17 \cf0 \fi2
\sl-217 \f20 \fs17 \cf0 \fi2
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-217 \f20 \fs17 \cf0 \fi2
\sl-215 \f20 \fs17 \cf0 \fi2
\sl-222 \f20 \fs17 \cf0 \fi2
\sl-217 \f20 \fs17 \cf0 \fi2
\f20 \fs16 \cf0 \b\i \f20 \f
\sl-247 \par\b\i \f20 \fs16
\sl-217 \b\i \f20 \fs16 \cf0
\sl-222 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0

\fi41 {\i0 \f10 \fs15 1 }
\fi41 {\i0 \f10 \fs15 1 }
\fi42 {\i0 \f10 \fs15 1 }\par
}
16 \cf0 D \par
}
cf0 0 C I O \par
}
\cf0 0
\fs15 1 }\par
}
\cf0 0
\fs15 1 }\par
}
\cf0 1
\fs15 1 }\par
}
cf0 5.31 \par
}
Draw a 4-variable Karnaugh map. Plot{\fs18 five}{\fs18 1s} on the ma
p from the Boolean expression
eloped in Prob.{\i \fs18 5.30.} Draw the appropriate loops around groups of
Is on the map.
374 {\fs16 See}{\fs17 Fig.}{\i \fs16 5-36. }\par
}
par
}
}
}
13 \cf0 A \par
}
3 \cf0 . \par
}
f0 5.32 \par
}
20 \fs16 \cf0 Fig. 5-36{\b0
Karnaugh} map{\b0 \fs16 solution }
cf0 {\b0 \fs18 Write}{\b0 \fs18 the}{\b0 \fs18 simplified}{\b0 \fs18 Boolean}
{\b0 \fs18 expression}{\b0 \fs18 based}{\b0 \fs18 on}{\b0 \fs18 the}{\b0
\fs18 Karnaugh}{\b0 \fs18 map}{\b0 \fs18 from}{\b0 \fs18 Prob.}{\b0\i \fs18
5.31. }
cf0 {\fs16 Solution: }
\fi354 {\i\dn006 \fs17 +}{\i \fs17 A}{\i \fs17 .}{\i \fs17 B}{\i \fs17 .}{\i
\fs17 C}{\i \fs17 .}{\i \fs17 D}{\b0\dn006 \f10 \fs13 =}{\i \fs17 Y Y }\pa
r
}
s17 \cf0 5-9{\i0 \f20 \fs18
USING}{\f20 \fs18 MAPS}{\i0 \f20 \fs18 WITH}{\
i0 \f20 \fs18 MAXTERM}{\i0 \f20 \fs18 EXPRESSIONS }
\fi380 {\b0\i0 \f20 \fs18 A}{\b0\i0 \f20 \fs18 different}{\b0\i0 \f20 \fs18
form}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 Karnaug
h}{\b0\i0 \f20 \fs18 map}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 used}{\b0\
i0 \f20 \fs18 with}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 Boolean}{\b
0\i0 \f20 \fs18 expressions.}{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 steps
}{\b0\i0 \f20 \fs18 for }
\fi25 {\b0\i0 \f20 \fs18 simplifying}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \
fs18 expressions}{\b0\i0 \f20 \fs18 are}{\b0\i0 \f20 \fs18 as}{\b0\i0 \f20 \f
s18 follows: }

\fi395 {\b0 \f20 \fs18 1.}{\b0\i0 \f20 \fs18
Write}{\b0\i0 \f20 \fs18 a}{\
b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 Boolean}{\b0\i0 \f20 \fs18 expr
ession}{\b0\i0 \f20 \fs18 from}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 t
ruth}{\b0\i0 \f20 \fs18 table.}{\b0\i0 \f20 \fs18 (Note}{\b0\i0 \f20 \fs18
the}{\b0\i0 \f20 \fs18 inverted}{\b0\i0 \f20 \fs18 form}{\b0\i0 \f20 \fs18
in}{\b0\i0 \f20 \fs18 Fig. }
\fi734 {\b0 \f20 \fs18 5-37a.) }
\fi387 {\b0 \f20 \fs18 2.}{\b0\i0 \f20 \fs18
Plot}{\b0\i0 \f20 \fs18 a}{\b
0\i0 \f20 \fs18 1}{\b0\i0 \f20 \fs18 on}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20
\fs18 map}{\b0\i0 \f20 \fs18 for}{\b0\i0 \f20 \fs18 each}{\b0\i0 \f20 \fs18
ORed}{\b0\i0 \f20 \fs18 group}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 variab
les.}{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 number}{\b0\i0 \f20 \fs18 of}{
\i0 \f20 \fs18 OS}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 the}{\f20 \fs19 Y
}{\b0\i0 \f20 \fs18 column}{\b0\i0 \f20 \fs18 of }
\fi737 {\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 truth}{\b0\i0 \f20 \fs18 tab
le}{\b0\i0 \f20 \fs18 will}{\b0\i0 \f20 \fs18 equal}{\b0\i0 \f20 \fs18 the}{\
b0\i0 \f20 \fs18 number}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 1s}{\b0\i0
\f20 \fs18 on}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 map. }
\fi385 {\i0 \f20 \fs18 3.}{\b0\i0 \f20 \fs18
Draw}{\b0\i0 \f20 \fs18 loops
}{\b0\i0 \f20 \fs18 around}{\b0\i0 \f20 \fs18 adjacent}{\b0\i0 \f20 \fs18 g
roups}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 two,}{\b0\i0 \f20 \fs18 four,
}{\b0\i0 \f20 \fs18 or}{\b0\i0 \f20 \fs18 eight}{\b0 \f20 \fs18 1s}{\b0\i0 \
f20 \fs18 on}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 map. }
\fi386 {\b0\i0 \f20 \fs18 4.}{\b0\i0 \f20 \fs18
Eliminate}{\b0\i0 \f20 \fs1
8 the}{\b0\i0 \f20 \fs18 variable(s)}{\b0\i0 \f20 \fs18 that}{\b0\i0 \f20 \fs
18 appear(s)}{\b0\i0 \f20 \fs18 with}{\b0\i0 \f20 \fs18 its}{\b0\i0 \f20 \fs1
8 (their)}{\b0\i0 \f20 \fs18 complement(s)}{\b0\i0 \f20 \fs18 within}{\b0\i0
\f20 \fs18 a}{\b0\i0 \f20 \fs18 loop,}{\b0\i0 \f20 \fs18 and}{\b0\i0 \f20 \fs
18 save }
\fi738 {\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 variable(s)}{\b0\i0 \f20 \fs1
8 that}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 (are)}{\b0\i0 \f20 \fs18 lef
t. }
\fi385 {\b0 \f20 \fs19 5.}{\b0\i0 \f20 \fs18
Logically}{\b0\i0 \f20 \fs18
AND}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 groups}{\b0\i0 \f20 \fs18 that}
{\b0\i0 \f20 \fs18 remain}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 form}{\b0
\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 simplified}{\b0\i0 \f20 \fs18 maxterm}{
\b0\i0 \f20 \fs18 expression. }
\fi388 {\b0\i0 \f20 \fs18 Consider}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18
truth}{\b0\i0 \f20 \fs18 table}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 Fig.}
{\b0 \f20 \fs18 5-37a.}{\b0\i0 \f20 \fs18 The}{\b0 \f20 \fs18 first}{\b0 \f20
\fs18 step}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 simplifying}{\b0\i0 \f2
0 \fs18 a}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 expression}{\b0\i0 \f
20 \fs18 by}{\b0\i0 \f20 \fs18 using }
\fi27 {\b0\i0 \f20 \fs18 a}{\b0\i0 \f20 \fs18 Karnaugh}{\b0\i0 \f20 \fs18 m
ap}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 write}{\
b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 expression}{\b0\i0 \f20 \fs18 in}{
\b0\i0 \f20 \fs18 unsimplified}{\b0\i0 \f20 \fs18 form.}{\b0\i0 \f20 \fs18
Figure}{\b0 \f20 \fs18 5-37a}{\b0\i0 \f20 \fs18 illustrates}{\b0\i0 \f20 \f
s18 how}{\b0\i0 \f20 \fs18 a }
\fi27 {\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 wr
itten}{\b0\i0 \f20 \fs18 for}{\b0 \f20 \fs18 each}{\b0\i0 \f20 \fs18 0}{\b
0 \f20 \fs18 in}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 Y}{\b0 \f20 \fs18 column
}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 truth}{\b0
\i0 \f20 \fs18 table.}{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 terms}{\b0\
i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 ORed}{\b0\i0 \f
20 \fs18 group}{\b0\i0 \f20 \fs18 are }
{\b0 \f20 \fs18 inuerted}{\b0\i0 \f20 \fs18 from}{\b0\i0 \f20 \fs18 the}{\b0
\i0 \f20 \fs18 way}{\b0\i0 \f20 \fs18 they}{\b0\i0 \f20 \fs18 appear}{\b0\i0
\f20 \fs18 in}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 truth}{\b0\i0 \f20 \f
s18 table.}{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 ORed}{\b0\i0 \f20 \fs18
groups}{\b0\i0 \f20 \fs18 are}{\b0\i0 \f20 \fs18 then}{\b0\i0 \f20 \fs18 AND
ed}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 form}{\b0\i0 \f20 \fs18 the }
\fi27 {\b0\i0 \f20 \fs18 unsimplified}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20
\fs18 Boolean}{\b0\i0 \f20 \fs18 expression}{\b0\i0 \f20 \fs18 in}{\b0\i0
\f20 \fs18 Fig.}{\b0 \f20 \fs18 5-37b.}{\b0\i0 \f20 \fs18 The}{\b0 \f20 \fs18
second}{\b0 \f20 \fs18 step}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 to}{
\b0\i0 \f20 \fs18 plot}{\b0\i0 \f20 \fs18 Is}{\b0\i0 \f20 \fs18 on}{\b0\i0 \
f20 \fs18 the}{\b0\i0 \f20 \fs18 map}{\b0\i0 \f20 \fs18 for }
\fi27 {\b0\i0 \f20 \fs18 each}{\b0\i0 \f20 \fs18 ORed}{\b0\i0 \f20 \fs18 gro
up.}{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 three}{\b0\i0 \f20 \fs18 maxter
ms}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 unsimplif
ied}{\b0\i0 \f20 \fs18 expression}{\b0\i0 \f20 \fs18 are}{\b0\i0 \f20 \fs18
placed}{\b0\i0 \f20 \fs18 as}{\b0\i0 \f20 \fs18 three}{\b0 \f20 \fs18 1s}{
\b0\i0 \f20 \fs18 on}{\b0\i0 \f20 \fs18 the }
{\b0 \f20 \fs18 reuised}{\b0\i0 \f20 \fs18 Karnaugh}{\b0\i0 \f20 \fs18 map}{
\b0\i0 \f20 \fs18 (Fig.}{\b0 \f20 \fs18 5-37c).}{\b0\i0 \f20 \fs18 The}{\b0 \
f20 \fs18 third}{\b0 \f20 \fs18 step}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs
18 to}{\b0\i0 \f20 \fs18 loop}{\b0\i0 \f20 \fs18 adjacent}{\b0\i0 \f20 \fs18
groups}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 eight,}{\b0\i0 \f20 \fs18
four,}{\b0\i0 \f20 \fs18 or}{\b0\i0 \f20 \fs18 two}{\b0\i0 \f20 \fs18 1s }
\fi27 {\b0\i0 \f20 \fs18 on}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 map.}{\
b0\i0 \f20 \fs18 Two}{\b0\i0 \f20 \fs18 loops}{\b0\i0 \f20 \fs18 have}{\b0\i0
\f20 \fs18 been}{\b0\i0 \f20 \fs18 drawn}{\b0\i0 \f20 \fs18 on}{\b0\i0 \f2
0 \fs18 the}{\b0\i0 \f20 \fs18 map}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs1
8 Fig.}{\b0 \f20 \fs18 5-37c.}{\b0\i0 \f20 \fs18 Each}{\b0\i0 \f20 \fs18 l
oop}{\b0\i0 \f20 \fs18 contains}{\b0\i0 \f20 \fs18 two}{\b0\i0 \f20 \fs18 1
s.}{\b0\i0 \f20 \fs18 The }
{\b0 \f20 \fs18 fourth}{\b0 \f20 \fs18 step}{\b0\i0 \f20 \fs18 is}{\b0\i0 \
f20 \fs18 to}{\b0\i0 \f20 \fs18 eliminate}{\b0\i0 \f20 \fs18 variables.}{\
b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 shaded}{\b0\i0 \f20 \fs18 loop}{\b
0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 5-37c}{\b0\i0 \
f20 \fs18 is}{\b0\i0 \f20 \fs18 shown}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \
fs18 eliminate}{\b0\i0 \f20 \fs18 the}{\f20 \fs18 A }
{\b0\i0 \f20 \fs18 variable.}{\b0\i0 \f20 \fs18 This}{\b0\i0 \f20 \fs18 leave
s}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 maxterm}{\b0 \f20 \fs18 (}{\b0 \
f20 \fs18 B}{\b0\i0 \fs28 +}{\b0 \f20 \fs18 C).}{\b0\i0 \f20 \fs18 The}{\b0\
i0 \f20 \fs18 partially}{\b0\i0 \f20 \fs18 unshaded}{\b0\i0 \f20 \fs18 loop
}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 shown}{\b0\i0 \f20 \fs18 to}{\b0\i0
\f20 \fs18 eliminate}{\b0\i0 \f20 \fs18 the}{\b0 \f20 \fs18 B }
{\b0\i0 \f20 \fs18 variable.}{\b0\i0 \f20 \fs18 This}{\b0\i0 \f20 \fs18 lea
ves}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 maxterm}{\b0 \f30 \fs27 (A+ }

\fi28 {\b0\i0 \f20 \fs18 Figure}{\b0 \f20 \fs18 5-37d}{\b0\i0 \f20 \fs18
s
hows}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 two}{\b0\i0 \f20 \fs18 maxt
erms}{\b0\i0 \f20 \fs18 being}{\b0\i0 \f20 \fs18 ANDed}{\b0\i0 \f20 \fs18
to}{\b0\i0 \f20 \fs18 form}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 simp
lified}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 Boolean }
\fi31 {\b0\i0 \f20 \fs18 expression}{\b0 \f20 \fs18 (}{\b0 \f20 \fs18 B}{\b0
\i0 \fs29 +}{\f20 \fs18 C}{\f20 \fs18 )}{\b0\i0 \fs26 -}{\b0 \f30 \fs25 (2}
{\b0\dn006 \f20 \fs18 C+}{\b0\i0 \fs29 }{\b0 \f20 \fs18
)}{\b0\i0\dn006 \f
s14 =}{\b0 \f20 \fs18 Y.}{\b0\i0 \f20 \fs18 Compare}{\b0\i0 \f20 \fs18 this
}{\b0\i0 \f20 \fs18 simplified}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18
expression}{\b0\i0 \f20 \fs18 with}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \f
s18 simplified }
\fi27 {\b0\i0 \f20 \fs18 minterm}{\b0\i0 \f20 \fs18 expression}{\b0\i0 \f20 \f
s18 from}{\b0\i0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 5-28e.}{\b0\i0 \f20 \fs18 T
hese}{\b0\i0 \f20 \fs18 two}{\b0\i0 \f20 \fs18 expressions}{\b0\i0 \f20 \fs18
were}{\b0\i0 \f20 \fs18 developed}{\b0\i0 \f20 \fs18 from}{\b0\i0 \f20 \fs18
the}{\b0 \f20 \fs18 same}{\b0\i0 \f20 \fs18 truth}{\b0\i0 \f20 \fs18 table.
}
\fi28 {\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 minterm}{\b0\i0 \f20 \fs18 e
xpression}{\b0 \f20 \fs18 (C}{\b0 \f20 \fs18 +}{\b0 \f20 \fs18 z}{\b0 \f20 \f
s18 .}{\b0 \f20 \fs18 B}{\b0\i0\dn006 \fs13 =}{\b0 \f20 \fs18 Y}{\b0 \f20 \f
s18 )}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 slightly}{\b0\i0 \f20 \fs18 ea
sier}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 implement}{\b0\i0 \f20 \fs18 by
}{\b0\i0 \f20 \fs18 using}{\b0\i0 \f20 \fs18 logic}{\b0\i0 \f20 \fs18 gates.
}
\fi388 {\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 maxterm}{\b0\i0 \f20 \fs18 m
apping}{\b0\i0 \f20 \fs18 procedure}{\b0\i0 \f20 \fs18 and}{\b0\i0 \f20 \fs18
Karnaugh}{\b0\i0 \f20 \fs18 map}{\b0\i0 \f20 \fs18 are}{\b0\i0 \f20 \fs18
different}{\b0\i0 \f20 \fs18 from}{\b0\i0 \f20 \fs18 those}{\b0\i0 \f20 \fs18
used}{\b0\i0 \f20 \fs18 for}{\b0\i0 \f20 \fs18 minterm }
\fi31 {\b0\i0 \f20 \fs18 expressions.}{\b0\i0 \f20 \fs18 Both}{\b0\i0 \f20 \fs
18 techniques}{\b0\i0 \f20 \fs18 should}{\b0\i0 \f20 \fs18 be}{\b0\i0 \f20 \f
s18 tried}{\b0\i0 \f20 \fs18 on}{\b0\i0 \f20 \fs18 a}{\b0\i0 \f20 \fs18 tru
th}{\b0\i0 \f20 \fs18 table}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 find}{\
b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 less}{\b0\i0 \f20 \fs18 costly}{\b0\i
0 \f20 \fs18 logic}{\b0\i0 \f20 \fs18 circuit. }
\fi388 {\b0\i0 \f20 \fs18 A}{\b0\i0 \f20 \fs18 4-variable}{\b0\i0 \f20 \fs18
Karnaugh}{\b0\i0 \f20 \fs18 map}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 maxterm
}{\b0 \f20 \fs18 expressions}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 illust
rated}{\b0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 5-38.}{
\b0\i0 \f20 \fs18 Note}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 special }
\fi27 {\b0\i0 \f20 \fs18 pattern}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 le
tters}{\b0\i0 \f20 \fs19 on}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 left}
{\b0\i0 \f20 \fs18 and}{\b0\i0 \f20 \fs18 top}{\b0\i0 \f20 \fs18 edges}{\b0
\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 map.}{\b0 \f20
\fs18 Care}{\b0 \f20 \fs18 must}{\b0 \f20 \fs18 always}{\b0 \f20 \fs18 be}
{\b0 \f20 \fs18 used}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 position}{\b0 \f20 \
fs18 all}{\b0 \f20 \fs18 the }
\fi25 {\b0 \f20 \fs18 terms}{\b0 \f20 \fs18 correctly}{\b0 \f20 \fs18 when}{\
b0 \f20 \fs18 drawing}{\b0 \f20 \fs18 maps. }\par
}

C).{\fs18 The}{\i \fs18 fifth}{\i \fs18 step}{\fs18 is}{\fs18 the}{\fs
18 ANDing}{\fs18 of}{\fs18 the}{\fs18 remaining}{\fs18 terms. }\par
}
. 51 \par
}
}
\par
}
f20 \fs16 \cf0 Fig.{\f30 \fs17 5-38}{\fs16 A}{\b0 \fs16 four-variable}{\b0 \
fs16 maxterm}{\b0 \fs16 Karnaugh}{\fs16 map }
\cf0 {\b0 \f10 \fs16 SOLVED}{\b0 \f10 PROBLEMS }
{\f30 \fs19 5.33}{\b0 \fs19
Write}{\b0 \fs19 the}{\b0 \fs19 unsimplified}
{\b0 \fs19 rnaxterm}{\b0 \fs19 Boolean}{\b0 \fs19 expression}{\b0 \fs19 for
}{\b0 \fs19 the}{\b0 \fs19 truth}{\b0 \fs19 table}{\b0 \fs19 in}{\b0 \fs19
Fig.}{\b0 \fs19 5-39.}{\b0 \fs19 (Be}{\b0 \fs19 sure}{\b0 \fs19 to }
\fi599 {\b0 \fs19 note}{\b0 \fs19 the}{\b0 \fs19 inverted}{\b0 \fs19 form.)
}
\fi956 {\i \f10 \fs15 (}{\i \f10 \fs15 A}{\b0\i \fs17 +}{\b0\i \fs17 B}{\b0
\f10 \fs25 +}{\b0\i \fs21 C}{\b0\i \fs21 )}{\b0\i \fs21 -}{\b0\i \fs21 (}{\
b0\i \fs21 A}{\b0\i \fs21 +}{\b0\i \fs21 B}{\b0 \f10 \fs26 +}{\b0\i \fs21 C}
{\b0\i \fs21 >}{\b0\i \fs21 *}{\b0\i \fs21 (}{\b0\i \fs21 A}{\b0\i \fs21 +}
{\b0\i \fs21 B}{\i \fs21 C}{\b0\i \fs21 +}{\i \fs21 )}{\i \fs21 .}{\i \fs21
(}{\i \fs21 A}{\i \fs21 +}{\i \fs21 B}{\b0 \f10 \fs24 +}{\b0 \fs21 C)}{\b0\
dn006 \f10 \fs13 =}{\i \f30 \fs19 Y }\par
}
0 90 \par
}
}
AP.{\fs17 5 }\par
}
\cf0 Inputs
\b\i \fs16 A}{\b\i \fs16
B}{\b\i \fs16
C }\par
}
5 0 }
5 0 }

5 0 }\par
}
5 0 }
5 1 }
5 1 }\par
}
5 1 }
5 0 }
5 1 }\par
}
I{\f20 \fs17
Output}{\b \fs33 I }
\fi435 {\b \fs15 Y }
\fi450 {\fs15 1 }
423 {\fs15 0 }
450 {\fs15 1 }
445 {\fs15 1 }\par
}
\cf0 Inputs
\b\i \fs16 A}{\b\i \fs16
B}{\b\i \fs16
C }\par
}
\cf0 1
27 1
26 1
26 1
{\b \f20 \fs16 Fig.}{\b \f20 \fs16 5-39 }\par
}
r
}
r
}

{\f20 \fs17
Output }
\fi430 {\b\i \f20 \fs16 Y }
\fi444 {\fs15 1 }
18 {\fs15 0 }
18 {\fs15 0 }
22 {\fs16 0 }\par
}
f0 5.34 \par
}
Draw a 3-variable Karnaugh map for maxterm expressions. Plot four{\fs18
1s} on the map for the
\par}{\phpg\posx1457\pvpg\posy3924\absw8495\absh1187 \sl-237 \f20 \fs19 \cf0 max
term Boolean expression developed in Prob.{\fs19 5.33.} Draw the appro
priate loops around
\par}{\phpg\posx1457\pvpg\posy3924\absw8495\absh1187 \sl-236 \f20 \fs19 \cf0 gro
ups of{\fs18 1s} on the map.
360 {\b \fs16 See}{\b \fs17 Fig.}{\b \f30 \fs18 5-40. }\par
}
14 \cf0 A + B \par
}
14 \cf0 A + B \par
}
17 \cf0 A + B \par
}
14 \cf0 A + B \par
}
f0 5.35 \par
}
20 \fs16 \cf0 Fig. 5-40{\b0 \fs17
Maxterm}{\b0 \fs17 map}{\b0 \fs17 soluti
on }
cf0 {\b0 \fs19 Write}{\b0 \fs19 the}{\b0 \fs19 simplified}{\b0 \fs19 Boolean}
{\b0 \fs19 expression}{\b0 \fs19 based}{\b0 \fs19 on}{\b0 \fs19 the}{\b0 \f
s19 Karnaugh}{\b0 \fs19 map}{\b0 \fs19 from}{\b0 \fs19 Prob.}{\b0 \fs19 5.3
4. }
cf0 Solution:
\fi354 {\b0\i \f30 \fs24 (A+}{\i \f30 \fs24 B) }\par
}
}
cf0 ( B{\i0 \f10 \fs25 +}{\i0 \fs21 C)}{\i0\dn006 \f10 \fs13 =}{\b Y }\par
}
rite the unsimplified product-of-sums Boolean expression for the truth table in
Fig. 5-41.
\fi4556 {\fs17 Inputs}{\fs17
output }\par
}
f0 5.36 \par
}
5 \cf0 1
590 1
590 1
594 1
594 1
594 1
594 1
596 1
{\b \f20 \fs16 Fig.}{\b \f20 \fs16 5-41 }\par
}
s16 \cf0 ( A{\b0\i0 \f10 \fs25 +}{\b0\dn006 \fs17 B }\par
}
0
par
}
0
par
}
0

par
}
\cf0 Solution:
fi352 {\i \f10 \fs15 (}{\i \f10 \fs15 A}{\b0\i \fs17 +}{\b0\i \fs17 B }\par
}
{\i \f20 \fs25 c}{\fs25 +}{\b\i\dn006 \f20 \fs16 D}{\b\i\dn006 \f20 \fs16 )
}\par
}
s16 \cf0 * ( A{\b0 \fs17 +}{\b0 \fs17 B }\par
}
{\i \f20 \fs24 c}{\fs26 +}{\b\i\dn006 \f20 \fs16 m }\par
}
+{\i \f20 \fs17 C}{\i \f20 \fs17 +}{\i \f20 \fs17 D}{\i \f20 \fs17 )}{\i \f2
0 \fs17 .}{\i \f20 \fs17 (}{\i \f20 \fs17 A}{\i \f20 \fs17 +}{\i \f20 \fs17
B}{\fs26 +}{\i \f20 \fs25 c}{\fs25 +}{\b\i \f30 \fs19 D)*(LT+ }{\i\dn006 \f20
\fs17 B}{\fs26 +}{\i\dn006 \f20 \fs17 C }\par
}
\cf0 + D ){\i0\dn006 \f10 \fs11 =}{\fs17 Y }\par
}
.{\f10 \fs17 51 }\par
}
}
\par
}
f0 5.37 \par
}
Draw a 4-variable product-of-sums Karnaugh map. Plot five 1s on the ma
p for the Boolean
ression developed in Prob.{\fs19 5.36.} Draw the appropriate loops arou
nd groups{\fs19 of}{\fs19 Is} on the
.
}
15 \cf0 A + B \par
}

s17 \cf0 A + B
\cf0 A + B
\cf0 A + B \par
}
\cf0 Fig.{\fs17 5-42}{\b0 \fs17
Maxterm}{\b0 \fs17 Karnaugh}{\b0 \fs17 map
}{\b0 \fs17 solution }\par
}
f0 5.38 \par
}
rite the simplified product-of-sums Boolean expression based on the Karn
augh map from
\par}{\phpg\posx1461\pvpg\posy6907\absw8386\absh725 \sl-235 \f20 \fs18 \cf0 Prob
. 5.37.
}
s15 \cf0 ( A{\b0\i0 \fs26 +}{\f20 \fs17 B}{\i0 \f30 t}{\i0 \f20 \fs16 C)}{\
f20 \fs17
(}{\f20 \fs17 B }\par
}
}
\b\i \f30 \fs19 D) }\par
}
\b\i \f20 \fs17 Y }\par
}
\cf0 5-10{\f20 \fs18
DON'T}{\f20 \fs18 CARES}{\f20 \fs18 ON}{\f20 \fs18 KA
RNAUGH}{\i \f20 \fs18 MAPS }
fi373 {\b0 \f20 \fs18 Consider}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 table}{\b0
\f20 \fs18 for}{\b0 \f20 \fs18 BCD}{\b0 \f20 \fs18 (8421)}{\b0 \f20 \fs18 nu
mbers}{\b0 \f20 \fs18 given}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20
\fs18 5-43.}{\b0 \f20 \fs18 Note}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 the}{
\b0 \f20 \fs18 binary}{\b0 \f20 \fs18 numbers}{\b0 \f20 \fs19 0000 }
\b0 \f20 \fs18 to}{\b0 \f20 \fs18 1001}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 th
e}{\b0 \f20 \fs18 table}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 used}{\b0 \f20 \
fs18 to}{\b0 \f20 \fs18 specify}{\b0 \f20 \fs18 decimal}{\b0 \f20 \fs18 nu
mbers}{\b0 \f20 \fs18 from}{\b0 \f20 \fs19 0}{\b0 \f20 \fs18 to}{\b0 \f20 \fs
19 9.}{\b0 \f20 \fs18 For}{\b0 \f20 \fs18 convenience,}{\b0 \f20 \fs18 the}
{\b0 \f20 \fs18 table}{\b0 \f20 \fs18 is }
\b0 \f20 \fs18 completed}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 the}{\b0 \f20 \fs
18 shaded}{\b0 \f20 \fs18 section,}{\b0 \f20 \fs18 which}{\b0 \f20 \fs18 sh
ows}{\b0 \f20 \fs18 other}{\b0 \f20 \fs18 possible}{\b0 \f20 \fs18 combinatio
ns}{\b0 \f20 \fs19 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 variables}{\b0\i \f
20 \fs19 D,}{\i \f20 \fs19 C,}{\i \f20 \fs19 B, }
\b0 \f20 \fs18 and}{\i \f20 \fs18 A.}{\b0 \f20 \fs18 These}{\b0 \f20 \fs19
six}{\b0 \f20 \fs18 combinations}{\b0 \f20 \fs18 (1010,}{\b0 \f20 \fs18 101
1,}{\b0 \f20 \fs18 1100,}{\b0 \f20 \fs18 1101,}{\b0 \f20 \fs18 1110,}{\b0 \f2
0 \fs18 and}{\b0 \f20 \fs18 1111)}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 not}
{\b0 \f20 \fs18 used}{\b0 \f20 \fs18 by}{\b0 \f20 \fs18 the}{\b0 \f20 \fs1
8 BCD }
\b0 \f20 \fs18 code.}{\b0 \f20 \fs18 These}{\b0 \f20 \fs18 combinations}{\b0 \
f20 \fs18 are}{\b0 \f20 \fs18 called}{\b0\i \f20 \fs18 don't}{\b0\i \f20 \fs
19 cares}{\b0 \f20 \fs18 when}{\b0 \f20 \fs18 plotted}{\b0 \f20 \fs18 on}
{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 Karnaugh}{\b0 \f20 \fs18 map.}{\b0 \f20 \
fs18 The}{\b0 \f20 \fs18 don't}{\b0 \f20 \fs18 cares }
\b0 \f20 \fs18 may}{\b0 \f20 \fs18 have}{\b0 \f20 \fs18 some}{\b0 \f20 \fs18
effect}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 simplifying}{\b0 \f20 \fs18 any}{\b
0 \f20 \fs18 logic}{\b0 \f20 \fs18 diagram}{\b0 \f20 \fs18 that}{\b0 \f20 \fs
18 might}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 constructed. }
fi361 {\b0 \f20 \fs18 Suppose}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 problem}{\b0 \
f20 \fs18 specifying}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18
warning}{\b0 \f20 \fs18 light}{\b0 \f20 \fs18 would}{\b0 \f20 \fs18 come}{\b0
\f20 \fs18 ON}{\b0 \f20 \fs18 when}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 BCD}
{\b0 \f20 \fs18 count}{\b0 \f20 \fs18 reached }
fi21 {\b0 \f20 \fs18 1001(decimal}{\b0 \f20 \fs18 9);}{\b0 \f20 \fs18 see}{\b0
\f20 \fs18 the}{\b0 \f20 \fs18 truth}{\b0 \f20 \fs18 table}{\b0 \f20 \fs18
in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 5-44.}{\b0 \f20 \fs18 See}{\b0 \f20 \
fs18 1}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 placed}{\b0 \f20 \fs18 in}{\b0 \f
20 \fs18 the}{\b0 \f20 \fs18 output}{\b0 \f20 \fs18 column}{\i \f20 \fs19 (}
{\i \f20 \fs19 Y}{\i \f20 \fs19 )}{\b0 \f20 \fs19 of}{\b0 \f20 \fs18 the}{\b0
\f20 \fs18 truth }
\b0 \f20 \fs18 table}{\b0 \f20 \fs18 after}{\b0 \f20 \fs18 the}{\b0 \f20 \fs
18 input}{\b0 \f20 \fs18 1001.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 Boolea
n}{\b0 \f20 \fs18 expression}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 this}{\b0
\f20 \fs18 table}{\b0 \f20 \fs18 (above}{\b0 \f20 \fs18 the}{\b0 \f20 \fs
18 shaded}{\b0 \f20 \fs18 section)}{\b0 \f20 \fs18 is }
\par}{\phpg\posx857\pvpg\posy8849\absw9412\absh2898 \b \f10 \fs17 \cf0 \fi315 {\
b0 \fs6 -}{\b0 \fs6
_}{\b0 \fs6
. }
fi1233 {\i \f20 \fs19 Y.}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18 is}{\b0 \f20 \fs
18 shown}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 right}{\b0 \
f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 table.}{\b0 \f20 \fs18 Th
e}{\b0 \f20 \fs18 "not}{\b0 \f20 \fs18 used"}{\b0 \f20 \fs18 combinations}{\
b0 \f20 \fs18 in}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 shaded }
fi2438 {\b0 \fs22 - }
\b0 \f20 \fs18 5-45b.}{\b0 \f20 \fs18 The}{\f20 \fs18 1}{\b0 \f20 \fs18 for
}{\b0 \f20 \fs18 the}{\b0\i \f20 \fs19 D}{\b0 \fs27 -}{\b0 \f20 \fs19 C}{\b
0\i \f20 \fs19 B}{\i \f20 \fs18 .}{\i \f20 \fs18 A}{\b0 \f20 \fs18 term}{\b
0 \f20 \fs18 is}{\b0 \f20 \fs18 plotted}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 map.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs19 six}{\b0\i \f20
\fs18 don't}{\i \f20 \fs18 cares}{\f20 \fs19 (X's}{\b0 \f20 \fs18 from}{\b
0 \f20 \fs18 the}{\b0 \f20 \fs18 truth }\par
}
\cf0 D{\i0 \f10 \fs23 -}{\i0 \fs19 C}{\i0 \f10 \fs27 -} B{\b .}{\b A}{\i0\d
n006 \f10 \fs13 = }\par
}
section{\fs19 of} the truth table {\f10 \fs22 _}might have some effect on th
is problem. A Karnaugh map is drawn in Fig.

2354 {\f10 \fs7 * }
\par}{\phpg\posx859\pvpg\posy11574\absw9363\absh2129 \sl-232 \f20 \fs18 \cf0 tab
le) are plotted as X's on the map. An X on the map means that square can be eit
her a 1 or a{\fs19 0.}{\b A }
\par}{\phpg\posx859\pvpg\posy11574\absw9363\absh2129 \sl-241 \f20 \fs18 \cf0 loo
p is drawn around adjacent 1s. The{\fs19 X's}{\fs19 on} the map can b
e considered Is,{\fs19 so} the single loop is
\par}{\phpg\posx859\pvpg\posy11574\absw9363\absh2129 \sl-239 \f20 \fs18 \cf0 dra
wn around the{\fs18 1} and three{\fs19 X's.} Remember that only groups of tw
o, four, or eight adjacent 1s and
\par}{\phpg\posx859\pvpg\posy11574\absw9363\absh2129 \sl-234 \f20 \fs18 \cf0 X's
are looped together. The loop contains four squares, which will eliminate
two variables. The{\b\i \fs19 B }
{\fs19 C} variables are eliminated, leaving the simplified Boolean expressio
n{\i \fs19 D}{\b\i \fs19 -}{\b\i \fs19 A}{\f10 \fs14 =}{\i \fs19 Y} in Fi
g. 5-45c.
360 As was said earlier, unused combinations from a truth table are c
alled don't cares. They are
wn as X's on a Karnaugh map. Including don't cares{\fs19 (X's)} in l
oops on a map helps to further
\par}{\phpg\posx859\pvpg\posy11574\absw9363\absh2129 \sl-244 \f20 \fs18 \cf0 sim
plify Boolean expressions. \par
}
cf0 SIMPLIFYINGLOGIC CIRCUITS:MAPPING \par
}
f0 [CHAP.{\i \f10 \fs17 5 }\par
}
Big.{\b \fs16 S-45}{\b \f20 \fs17
Using}{\b \fs15 a}{\b \fs16 map }\par
}
\cf0 SOLVED PROBLEMS \par
}
18 \cf0 5.39 \par
}
\cf0 Write the unsimplified minterm Boolean expression{\fs21 for} the{\f30 \fs
23 BCD} truth table in Fig.{\i \f10 \fs19 5-46. }
{\fs18 Solution: }
\fi357 {\i \fs23 D}{\i \fs23 .}{\i \fs23 ~}{\i \fs23 .}{\i \fs23 B}{\i \fs23
.}{\i \fs23 ~}{\i \f10 \fs22 .}{\i \fs23 +}{\i \f10 \fs22 ~}{\i \fs23 D.}{\i
\f10 \fs22 }{\i \f10 \fs22 B}{\i \f10 \fs22 .}{\i \f10 \fs22 A}{\i \f10 \fs
17 y }\par
}
8 \cf0 I \par
}

.{\fs17 51 }\par
}
}
f0 93 \par
}
puts
fi23 {\b\i C}{\b\i
B }\par
}
tput \par
}
{\fs16 pit}{\fs16 t}{\b \fs16 s }
fi20 {\b\i \fs16 C}{\b\i \fs16
B }\par
}
tput \par
}
16 \cf0 D \par
}
16 \cf0 A \par
}
16 \cf0 D \par
}
16 \cf0 A \par
}
r
}
r
}
r
}

r
}
5 0 }
5 0 }
5 0 }
5 0 }\par
}
1
1 \par
}
0
0 \par
}
0
0 \par
}
0
1 \par
}
5 0 }
{\fs15 1 }
{\fs15 1 }\par
}
cf0 Fig.{\f10 \fs15 5-46 }\par
}
f0 5.40 \par
}
Draw a 4-variable minterm Karnaugh map. Plot two{\fs18 1s} and six{\b \fs18 X
's} (for the don't cares) on the
based on the truth table in Fig. 5-46. Draw the appropriate loops around groups
of{\fs18 1s} and
\fs18 X's} on the map.
366 {\i \fs17 See}{\fs17 Fig.}{\fs16 5-47. }\par
}
s17 \cf0 A . B
\cf0 {\fs16 A}{\fs16 .}{\fs16 B }
\cf0 {\fs15 A}{\fs15 .}{\fs15 B }
s17 \cf0 {\f10 \fs13 A}{\f10 \fs13 -}{\f10 \fs13 B }\par
}
ig.{\b \f10 \fs15 5-47}{\fs17
Karnaugh}{\fs16 map}{\fs16 solution }\par
}
f0 5.41 \par
}
rite the simplified Boolean expression based on the Karnaugh map from Prob. 5.
40.
60 {\i \fs17 D}{\i \fs17 =}{\i \fs17 Y }\par
}
\cf0 5-11{\fs18
KARNAUG }\par
}
\cf0 n{\f10 \fs17 WS}{\f20 \fs18
VITH}{\b0 \f20 \fs18 FIVE }\par
}
\cf0 ES \par
}
8 \cf0 A three-dimensional Karnaugh map can be used to solve logic problems w
ith{\fs18 five} variables. The
used to simplify 5-variable minterm Boolean expressions is shown in Fig. 5-48c
. Notice that both
top{\b\i \fs18 (}{\b\i \fs18 E}{\b\i \fs18 )} plane and bottom{\b\i \fs25
(}{\b\i \fs25 E}{\b\i \fs25 )} plane are duplicates of the 4-variable min
term map used in Sec.
. The procedure for simplifying a minterm logic expression using a 5-variable Ka
rnaugh map is like
\par}{\phpg\posx845\pvpg\posy11552\absw9121\absh1913 \sl-232 \f20 \fs18 \cf0 tho

se used previously.
364 Consider the truth table with{\fs18 five} variables in Fig. 5-48a. The{\b\i
\fs17 first}{\b\i \fs17 step}{\fs19 in} simplification is to write
minterm Boolean expression. The lengthy unsimplified miriterm Boolean
expression appears in
\par}{\phpg\posx845\pvpg\posy11552\absw9121\absh1913 \sl-230 \f20 \fs18 \cf0 Fig
. 5-48b.{\b\i \f10 \fs17 An} ANDed group of{\fs18 five} variables is written f
or each{\fs18 1}in the{\b\i \fs18 Y} column of the truth table.
{\b\i \fs17 second}{\b\i \fs17 step} is to plot 1s on the 5-variable map.
Seven 1s are plotted on the map in Fig. 5-48c. \par
}
0 94 \par
}
cf0 SI{\f20 \fs17 MPI-IFYING}{\f20 \fs17 I}{\f20 \fs17 .OGlC}{\f20 \fs17 Cl}{
\f20 \fs17 RCUITS:}{\f20 \fs17 MAPPING }\par
}
f0 [CHAP.{\i \fs16 5 }\par
}
\cf0 Fig.{\f10 5-48}{\f20 \fs17
Karnaugh}{\f20 \fs16 map}{\f20 \fs16 sol
ution--5}{\f20 \fs17
variablc }\par
}
Each{\fs19 1}{\fs20 on} the map represents an ANDed group{\fs19 of} terms
from the unsimplificd mintcrm expression.
{\b\i \fs19 rhird}{\b\i \fs20 sfep}{\fs19 is} to loop adjacent groups{\fs19
of}{\fs19 Is.} Adjacent groups{\b \f10 \fs17 of} eight, four,{\fs19 or}{\
b \f10 \fs17 two}{\b \f10 \fs17 1s}{\fs19 are}{\b lociped. }
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-238 \f20 \fs19 \cf0 Two
{\fs19 loops} have{\fs19 been} drawn{\fs19 in} Fig.{\b \f10 \fs18 5-4
8c.} The largcr loop contains four{\fs19 Is} and forms a cylindcr
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-240 \f20 \fs19 \cf0 bet
ween{\fs19 the} top and bottom planes{\fs20 of}{\fs19 the} map. I'hc
smaller{\fs19 loop} contains{\b \f10 \fs17 two}{\b \f10 \fs17 1s} and
forms the
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-235 \f20 \fs19 \cf0 cyl
inder at the lower{\fs19 left} in Fig.{\b\i \f10 \fs17 5-48c.}{\fs19 Thc} si
nglc{\b \f10 \fs17 1} ncar thc bottom of the map does not have{\b \f10 \fs16
any}{\b \f30 \fs17 Is }
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-244 \f20 \fs19 \cf0 adj
acent{\fs20 to}{\fs19 it}{\fs20 on} cithcr thc{\b\i \fs20 E}{\fs19 or}
planc.{\b \f30 \fs21 Thc}{\b\i \f10 \fs16 fourth}{\fs18 step} is{\fs19
to} climinatc{\f10 \fs25 -}{\f10 \fs25 -vari}ables.{\fs19 Thc} largc loop
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-313 \f20 \fs19 \cf0 (cy
linder) in Fig.{\b \f10 \fs17 5-48c} climinatcs{\fs19 thc}{\b\i B} and E va
riables leaving the term{\f10 \fs25 -}{\f10 \fs31 -}{\f10 \fs25 -}{\f10 \fs27
- }
s19 (cylinder)} contains{\fs19 two}{\b \f30 \fs20 Is} and climinatcs the{\fs19
E} tcrm lcaving the term{\b\i \f10 \fs17 A}{\b\i \fs19
R}{\b\i \fs19 .}
{\b\i \fs19 C}{\f10 \fs31 -}{\b\i \f30 \fs21 D.}{\b \f30 \fs20 The} single{\b
\f10 \fs18 1} ncar
\par}{\phpg\posx857\pvpg\posy11619\absw9368\absh1952 \sl-243 \f20 \fs19 \cf0 thc
bottom is not{\b \fs19 loopcd} and allows no simplification. Thc{\i \f10 \fs
19 fifth}{\b\i \f10 \fs16 srvp}{\fs19 is}{\fs19 to} logically{\fs20 OR} t
hc rcmaining \par
}
fs17 \cf0 A{\i0 \fs18
C}{\b0\i0 \fs25 -D}{\f30 \fs21 .}{\b0\i0 \f20 \fs19 Th
e}{\i0 \f20 \fs19 smallcr}{\b0\i0 \f20 \fs19 loop }\par
}
0 CHAP.{\b0 \f10 \fs17 51 }\par
}
cf0 SIMPLIFYING LOGIC CIRCUITS: MAPPING \par
}
f0 95 \par
}
erms. Figure{\i \f10 \fs18 5-48d} shows the remaining groups ORed, yielding the
simplified minterm expression{\fs19 of }
234 {\f10 \fs7 * }
the two Boolean expressions{\fs19 in} Fig.{\fs19 5-48} are compared.
{\f10 \fs16 SOLVED}{\f10 \fs16 PROBLEMS }
{\b \f10 \fs17 5.42}
Write the unsimplified minterm Boolean expression f
or the truth table in Fig.{\fs19 5-49. }\par
}
17 \cf0 A{\f20 \fs24 E}{\b0\i0 \fs23 -}{\b0\i0 \f20 \fs34 c}{\b0\i0\dn006 \f
s23 -}{\b0 \f20 \fs24 D}{\b0 \f30 \fs28 +A.}{\b0\i0 \f20 \fs34 c}{\b0\i0 \fs2
7 -}{\f30 \fs21 D}{\b0\i0 \fs29 +}{\f20 \fs19 A}{\b0\i0 \fs22 .}{\f20 \fs24 E
}{\b0\i0 \fs27 -}{\b0\i0 \f20 \fs19 C}{\b0\i0 \fs27 -}{\f30 \fs21 D}{\f20 \fs
25 E}{\b0\i0\dn006 \fs13 = }\par
}
s19 \cf0 Y.{\b0\i0 \fs18 The}{\b0\i0 \fs18 amount}{\b0\i0 \fs18 of}{\b0\i0 \f
s18 simplification}{\b0\i0 \fs18 in}{\b0\i0 \fs18 this}{\b0\i0 \fs18 exampl
e}{\b0\i0 \fs18 is}{\b0\i0 \fs18 obvious }\par
}
s15 \cf0 A
\fi24 {\b0\i0 \fs14 0 }
\fi23 {\b0\i0 \fs15 0 }
\fi28 {\b0\i0 \fs15 0 }
\fi24 {\b0\i0 \fs14 0 }
\fi28 {\b0\i0 \fs14 0 }
\fi28 {\b0\i0 \fs14 0 }

\fi28 {\b0\i0 \fs15 0 }
\fi28 {\b0\i0 \fs14 0 }
\fi28 {\b0\i0 \fs15 0 }
\fi28 {\b0\i0 \fs14 0 }
\fi30 {\b0\i0 \fs15 0 }
\fi28 {\b0\i0 \fs15 0 }
\fi28 {\b0\i0 \fs14 0 }
\fi29 {\b0\i0 \fs14 0 }
\fi28 {\b0\i0 \fs14 0 }
\fi30 {\b0\i0 \fs15 0 }\par
}
\cf0 B
\i0 \fs15 0 }
\i0 \fs14 0 }
\i0 \fs15 0 }
\i0 \fs15 0 }
\i0 \fs15 0 }
\i0 \fs15 0 }
\i0 \fs15 0 }
\i0 \fs15 0 }
fi35 {\i0 \f10 \fs13 1 }
fi31 {\b\i0 \fs15 1 }
fi35 {\i0 \f10 \fs14 1 }
fi31 {\b\i0 \fs15 1 }
fi31 {\b\i0 \fs15 1 }
fi31 {\i0 \f10 \fs14 1 }
fi31 {\b\i0 \fs15 1 }
fi31 {\i0 \f10 \fs14 1 }\par
}
nputs
60 {\fs15 C }
72 {\fs15 0 }
72 {\fs15 0 }
73 {\fs14 0 }
72 {\fs15 0 }
88 {\f10 \fs13 1 }
92 {\b 1 }
86 {\f10 \fs14 1 }
88 1
73 {\fs14 0 }
73 {\fs15 0 }
73 {\fs14 0 }
73 {\fs15 0 }
88 {\fs15 1 }
92 {\f10 \fs14 1 }
86 {\b \fs15 1 }
92 {\b \fs15 1 }\par
}
\cf0 D
\i0 \fs15 0 }
\i0 \fs15 0 }
fi35 {\i0 \f10 \fs14 1 }
fi37 {\b\i0 \fs15 1 }
fi23 {\i0 \fs14 0 }
fi23 {\i0 \fs14 0 }
fi35 {\i0 \f10 \fs14 1 }
fi41 {\i0 \f10 \fs14 1 }
\i0 \fs14 0 }
fi23 {\i0 \fs14 0 }
fi35 {\b\i0 \fs15 1 }
fi35 {\i0 \f10 \fs14 1 }
fi23 {\i0 \fs14 0 }
fi23 {\i0 \fs14 0 }
fi35 {\i0 \f10 \fs14 1 }
fi35 {\b\i0 \f10 \fs14 1 }\par
}
s15 \cf0 E
{\b0\i0 \fs15 0 }
\fi36 {\i0 \fs15 1 }
\fi21 {\b0\i0 \fs15 0 }
\fi31 {\i0 \f10 \fs14 1 }
{\b0\i0 \fs15 0 }
\fi36 {\i0 \fs15 1 }
{\b0\i0 \fs15 0 }
\fi35 {\i0 \f10 \fs14 1 }
{\b0\i0 \fs15 0 }
\fi31 {\b0\i0 \f10 \fs14 1 }
\fi21 {\b0\i0 \fs14 0 }
\fi31 {\i0 \f10 \fs14 1 }
\fi21 {\b0\i0 \fs14 0 }
\fi31 {\b0\i0 \f10 \fs13 1 }
\fi21 {\b0\i0 \fs15 0 }
\fi36 {\b0\i0 \fs14 1 }\par
}
utput
02 {\b\i \fs15 Y }
03 {\fs15 0 }
03 {\fs15 0 }
17 {\f10 \fs14 1 }
17 {\b \fs15 1 }
08 {\fs14 0 }
07 {\fs14 0 }
\sl-198 \i \f20 \fs15 \cf0 \

\sl-193 \i \f20 \fs15 \cf0 \
\sl-201 \i \f20 \fs15 \cf0 \
\sl-196 \i \f20 \fs15 \cf0 \
\f20 \fs15 \cf0 \b\i \f20 \f
\sl-275 \b\i \f20 \fs15 \cf0
\sl-200 \b\i \f20 \fs15 \cf0
\sl-202 \b\i \f20 \fs15 \cf0
\sl-195 \b\i \f20 \fs15 \cf0
\sl-197 \b\i \f20 \fs15 \cf0
\sl-198 \b\i \f20 \fs15 \cf0
\sl-199 \b\i \f20 \fs15 \cf0
\sl-196 \b\i \f20 \fs15 \cf0
\sl-200 \b\i \f20 \fs15 \cf0
\sl-196 \b\i \f20 \fs15 \cf0
\sl-200 \b\i \f20 \fs15 \cf0
\sl-197 \b\i \f20 \fs15 \cf0
\sl-198 \b\i \f20 \fs15 \cf0
\sl-193 \b\i \f20 \fs15 \cf0
\sl-201 \b\i \f20 \fs15 \cf0
\sl-196 \b\i \f20 \fs15 \cf0
\fs14 \cf0 \f20 \fs14 \cf0 o
\sl-294 \f20 \fs14 \cf0 \fi2
\sl-275 \f20 \fs14 \cf0 \fi2
\sl-200 \f20 \fs14 \cf0 \fi2
\sl-202 \f20 \fs14 \cf0 \fi2
\sl-195 \f20 \fs14 \cf0 \fi2
\sl-197 \f20 \fs14 \cf0 \fi2
\sl-197 \f20 \fs14 \cf0 \fi2

26 {\f10 \fs14 1 }
26 {\b \fs15 1 }
03 {\fs14 0 }
07 {\fs14 0 }
26 {\b \fs15 1 }
17 {\f10 \fs13 1 }
07 {\fs15 0 }
07 {\fs14 0 }
22 {\b \f10 \fs14 1 }
22 {\b \fs15 1 }\par
}
s15 \cf0 A
\fi41 {\i0 1 }
\fi41 {\i0 1 }
\fi41 {\i0 \fs15 1 }
\fi41 {\i0 1 }
\fi41 {\b0\i0 \f10 \fs14 1 }
\fi50 {\i0 1 }
\fi41 {\b0\i0 \f10 \fs14 1 }
\fi45 {\b0\i0 \f10 \fs14 1 }
\fi41 {\i0 \fs14 1 }
\fi37 {\b0\i0 \f10 \fs14 1 }
\fi41 {\i0 1 }
\fi37 {\i0 1 }
\fi50 {\i0 \f10 \fs14 1 }
\fi41 {\i0 1 }
\fi41 {\b0\i0 \fs14 1 }
\fi41 {\i0 1 }\par
}
\cf0 B
\i0 \fs14 0 }
\par}{\phpg\posx6341\pvpg\posy3576\absw152\absh3089 \sl-200 \i \f20 \fs15

\i0 \fs14 0 }
fi21 {\i0 0 }
fi21 {\i0 \fs14 0 }
fi21 {\i0 \fs14 0 }
fi21 {\i0 0 }
fi21 {\i0 \fs14 0 }
fi21 {\i0 0 }
fi40 {\b\i0 \fs15 1 }
fi40 {\b\i0 \fs15 1 }
fi41 {\b\i0 \f10 \fs14 1 }
fi35 {\i0 \fs14 1 }
fi41 {\i0 \fs15 1 }
fi40 {\i0 \f10 \fs13 1 }
fi41 {\b\i0 \f10 \fs13 1 }
fi40 {\i0 \f10 \fs14 1 }\par
}
{\phpg\posx6779\pvpg\posy3287\absw475\absh3349 \b \f20 \fs14 \cf0 \b \f20
\cf0 Inputs
\par}{\phpg\posx6779\pvpg\posy3287\absw475\absh3349 \sl-294 \b \f20 \fs14
fi156 {\b0 \fs15 C }
fi172 {\b0 \fs15 0 }
fi172 {\b0 \fs14 0 }
fi173 {\b0 \fs14 0 }
fi172 {\b0 \fs15 0 }
fi187 {\b0 \fs14 1 }
fi186 {\b0 \f10 \fs14 1 }
fi187 {\fs15 1 }
fi186 {\b0 \f10 \fs14 1 }
fi172 {\b0 \fs14 0 }
fi173 {\b0 \fs14 0 }
fi173 {\b0 \fs15 0 }
fi172 {\b0 \fs14 0 }
\cf0 {
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs14
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
fi192 {\fs15 1 }
fi196 {\b0 \fs15 1 }
fi192 {\fs15 1 }
fi187 {\b0 \f10 \fs14 1 }\par
}
\cf0 D
fi24 {\i0 \fs14 0 }
fi23 {\i0 \fs14 0 }
fi38 {\b\i0 \fs15 1 }
fi36 {\i0 \fs14 1 }
fi24 {\i0 \fs14 0 }
fi24 {\i0 \fs14 0 }
fi38 {\i0 \f10 \fs14 1 }
fi36 {\b\i0 \fs15 1 }
fi24 {\i0 \fs14 0 }
fi24 {\i0 \fs14 0 }
fi38 {\i0 \f10 \fs14 1 }
fi36 {\i0 \f10 \fs13 1 }
fi24 {\i0 \fs14 0 }
fi28 {\i0 \fs14 0 }
fi38 {\b\i0 \fs15 1 }
fi38 {\i0 \f10 \fs14 1 }\par
}
s15 \cf0 E
{\b0\i0 \fs14 0 }
\fi35 {\i0 \fs15 1 }
{\b0\i0 \fs14 0 }
\fi31 {\b0\i0 \f10 \fs14 1 }
{\b0\i0 \fs14 0 }
\fi35 {\b0\i0 \f10 \fs14 1 }
{\b0\i0 \fs14 0 }
\fi37 {\b0\i0 \f10 \fs14 1 }

{\b0\i0 \fs14 0 }
\fi35 {\b0\i0 \f10 \fs14 1 }
\fi21 {\b0\i0 0 }
\fi27 {\b0\i0 \f10 \fs13 1 }
\fi21 {\b0\i0 \f10 \fs14 0 }
\fi37 {\b0\i0 \f10 \fs14 1 }
\fi21 {\b0\i0 \fs14 0 }
\fi35 {\i0 \f10 \fs14 1 }\par
}
utput
01 {\b\i \fs15 Y }
05 {\fs15 0 }
20 {\b \f10 \fs14 1 }
05 {\fs15 0 }
05 {\fs14 0 }
06 {\fs14 0 }
07 {\fs14 0 }
05 {\fs15 0 }
07 {\fs15 0 }
05 {\fs15 0 }
20 {\f10 \fs14 1 }
07 {\fs14 0 }
05 {\fs15 0 }
07 {\fs15 0 }
07 {\fs14 0 }
07 {\fs15 0 }
07 {\fs14 0 }\par
}
f0 5.43 \par
}
raw a 5-variable Karnaugh map. Plot ten{\fs19 Is} on the map from t
he Boolean expression
loped in Prob.{\fs19 5.42.} Draw the appropriate loops around groups of{\fs1
9 Is} on the map.
64 {\fs17 See}{\b \fs17 Fig.}{\i \fs17 5-50. }\par
}
\cf0 Fig.{\f10 \fs15 5-50 }\par
}
0 96 \par
}
}
}
f0 5.44 \par
}
rite the simplified Boolean expression based on the Karnaugh map from Prob.{\fs
19 5.43. }
}
16 \cf0 A{\b0\i0 \fs23 -}{\b0 \f20 \fs26 c}{\b0\i0 \fs23 - }\par
}
{\phpg\posx2097\pvpg\posy1793\absw399\absh259 \f10 \fs22 \cf0 \f10 \fs22 \cf0 - \par
}
cf0 D{\i0 \f10 \fs23 -}{\b E }\par
}
cf0 +A.{\i0\dn006 \f10 \fs11
=}{\b\dn006 \f20 \fs17 YD }\par
}
f0 5.45 \par
}
{\f20 \fs17 Write}{\f20 \fs17 a}{\f20 \fs17 minterm}{\f20 \fs17 Boolean}{\f
20 \fs17 expression}{\f20 \fs17 for}{\f20 \fs17 the}{\f20 \fs17 truth}{\f
20 \fs17 table}{\f20 \fs17 in}{\f20 \fs17 Fig.}{\f20 \fs17 5-51. }\par
}
s17 \cf0 Ans.{\dn006 \fs17
C}{\b0 \fs17 +}{\b0 \fs17 x}{\b0 \
fs17 .}{\b0 \fs17 B}{\b0\i0 \f10 \fs23 -} c + A .{\fs17 B}{\b0\i0 \f10 \f
s23 -}{\fs17 C- C{\f63 \u49152\'3f} }\par
}
\par
}
}
15 \cf0 + A .{\b0 \f20 \fs17 B}{\f20 \fs17
C}{\b0\i0\dn006 \fs11 = }\par
}
}
cf0 Y \par
}
\cf0 Inputs
\b\i \fs17 A}{\b\i \fs17
B}{\b\i \fs17
C }\par
}
fs15 0 }
fs15 0 }
fs15 0 }\par
}
fs15 0 }
fs15 1 }
fs15 1 }\par
}
fs15 1 }
fs15 0 }
fs15 1 }\par
}
utput
\fi251 {\b\i \fs16 Y }
\fi243 {\f10 \fs16 0 }
65 {\b \f10 \fs15 1 }
67 {\b \f10 \fs15 1 }
45 {\f10 \fs16 0 }\par
}
puts \par
}
s17 \cf0 A

\cf0 \fi31 {\i0 \f10 \fs15 1 }
\fi31 {\i0 \f10 \fs15 1 }
\fi30 {\i0 \f10 \fs15 1 }
\fi35 {\i0 \f10 \fs15 1 }\par
}
s17 \cf0 B
\cf0 \fi28 {\i0 \f10 \fs15 0 }
\fi28 {\i0 \f10 \fs15 0 }
\fi30 {\i0 \f10 \fs15 1 }
\fi40 {\i0 \f10 \fs15 1 }\par
}
s17 \cf0 C
\cf0 \fi25 {\i0 \f10 \fs15 0 }
\fi25 {\i0 \f10 \fs15 1 }
\fi31 {\i0 \f10 \fs15 0 }
\fi45 {\i0 \f10 \fs15 1 }\par
}
utput
\fi243 {\b\i Y }
\fi257 {\b \f10 \fs15 1 }
37 {\f10 \fs15 0 }
39 {\f10 \fs16 0 }
65 {\b \f10 \fs16 1 }\par
}
f0 5.46 \par
}
raw an AND-OR logic diagram that will perform the logic specif
ied by the Boolean expression
loped in Prob. 5.45.{\b\i
Am.}
See Fig. 5-52. \par
}
17 \cf0 Y \par
}
0 \fs9 \cf0 U
\b\i0 \fs17 Fig.}{\b\i0 \fs16 5-52}{\i0 \fs17
AND-OR}{\i0 \fs17 logic}{\i0
\fs17 circuit }\par

}
cf0 5.47 \par
}
7 \cf0 Write the maxterm Boolean expression for the truth table in{\b \f
s16 Fig.} 5-51.
b\i Ans.}{\b\i
(}{\b\i A}{\i +}{\i B}{\f10 \fs27 +}{\b\i\dn006 C}{\b\i
\dn006 )}{\b\i -}{\b\i\dn006 (}{\b\i A}{\b\i \fs22 +}{\b\i \fs22 E}{\b\i \f
s22 +}{\i \fs21 C}{\i \fs21 )}{\i \fs21 -}{\i \fs21 (}{\i \fs21 A}{\i \fs
21 +}{\b\i B}{\f10 \fs25 +}{\i \fs21 c).(A+B+}{\b\i \f30 \fs19 Y }
0 \fi30 Draw an OR-AND logic diagram that{\fs17
will} perform th
e logic specified by the Boolean expression
i32 developed in Prob.{\fs17 5.47.}{\b\i
Ans.}
See Fig.{\fs17
5-53. }\par
}
s17 \cf0 C \par
}
s17 \cf0 ) = \par
}
cf0 5.48 \par
}
.{\f10 \fs16 51 }\par
}
}
\par
}
14 \cf0 A \par
}
\cf0 1 \par
}
\par
}
14 \cf0 A
{\f20 \fs15 B }
cf0 {\b0 \f20 \fs15 C }\par
}
\par
}
f0 5.49 \par
}
20 \fs16 \cf0 Fig.{\f10 \fs15 5-53}{\b0 \fs17
OR-AND}{\b0 \fs17 logic}{\b0
\fs17 circuit }
cf0 {\b0 \fs17 Use}{\b0 \fs17 De}{\b0 \fs17 Morgan's}{\b0 \fs17 theorem}{\b
0 \fs17 to}{\b0 \fs17 convert}{\b0 \fs17 the}{\b0 \fs17 Boolean}{\b0 \fs1
7 expression }
\fi2528 {\i \f10 \fs16 (}{\i \f10 \fs16 A}{\i \fs22 +}{\i \fs22 B}{\i \fs22
+}{\b0\i \f10 \fs22 c}{\b0 \f10 \fs26 +}{\i\dn006 \fs17 D}{\i\dn006 \fs17 )}{
\b0 \f10 \fs23 -}{\i \fs17 (}{\i \fs17 A}{\i \fs22 +}{\i \fs22 B}{\i \fs22
+}{\b0 \f10 \fs20 C-10)}{\b0\dn006 \f10 \fs13 =}{\b0\i \fs17 Y }\par
}
o its minterm form. Show each step as in Fig.{\fs17 5-15. }\par
}
Maxtermexpression }
0 \fi534 {\b0\i0 First}{\b0\i0 step }
\cf0 \fi534 {\b0\i0 Second}{\b0\i0 step }
\cf0 \fi532 {\b0\i0 Third}{\b0\i0 sfep }
0 \fi539 {\b0\i0 Fourth}{\b0\i0 step }\par
}
}
\f10 \fs15 \cf0 ( A{\f20 \fs17 +}{\f20 \fs17 B}{\f20 \fs17 +}{\f20 \fs17 C}{
\f20 \fs17 +}{\f20 \fs17 D}{\f20 \fs17 )}{\f20 \fs17 -}{\f20 \fs17 (}{\f20
\fs17 A}{\f20 \fs17 +}{\f20 \fs17 B}{\f20 \fs17 +}{\f20 \fs17 C}{\f20 \fs17
+}{\f20 \fs17 W}{\f20 \fs17 )}{\f20 \fs17 =}{\f20 \fs17 Y }
0 {\f20 \fs22 A}{\f20 \fs22 .}{\f20 \fs22 B}{\f20 \fs22 -}{\f20 \fs22 c}{\f2
0 \fs22 .}{\f20 \fs22 D}{\f20 \fs22 +}{\f20 \fs22 A}{\f20 \fs22 .}{\f20 \fs
22 B}{\f20 \fs22 .}{\f20 \fs22 C}{\f20 \fs22 .}{\f20 \fs22 D }
0 {\f30 \fs32 x.}{\b0 \fs24 E}{\b0 \fs24 .}{\b0\i0 \f20 \fs30 c. }{\i0\dn006 \f
30 \fs16 jj}{\b0 \f30 \fs25 +A.}{\b0 \fs23 E}{\b0 \fs23 .}{\f20 \fs26 F}{\b0\
dn006 \f20 \fs21 D. }
\cf0 {\b0 \f20 \fs21 A.Z.C.D+A.E.?.D }
0 {\b0\i0 \f20 \fs17 eliminate}{\b0\i0 \f20 \fs17 double}{\b0\i0 \f20 \fs17
overbars }\par
}
{\phpg\posx1937\pvpg\posy7678\absw3287\absh274 \f20 \fs17 \cf0 \f20 \fs17 \cf0 M
interm expression{\i \fs18
A}{\i \fs18 .}{\i \fs18 B}{\f10 \fs23 -}{\fs
21 C}{\fs21 .}{\fs21 0}{\i \f30 \fs25 +A. }\par
}
cf0 B{\f10 \fs16
C}{\fs22 D }\par
}
}

}
\i \f20 \fs17 Y }\par
}
f0 5.50 \par
}
\cf0 Draw a 4-variable minterm Karnaugh map. Plot two{\fs16
1s} on
the map for the terms in the minterm
2 expression developed{\fs17 in} Prob. 5.49. Draw the appropriate loops
around groups of{\fs16 1s} on the map.
i Ans.}
}
\cf0 Fig.{\f10 \fs15 5-54}{\b0 \fs17
Completed}{\b0 \fs17 minterm}{\b0 \fs
17 Karnaugh}{\b0 \fs17 map }\par
}
cf0 5.51 \par
}
\cf0 Write the simplified minterm Boolean expression based on the Karnau
gh map from Prob.{\fs17 5.50. }
\i Ans.}{\i \fs17
X}{\i \fs17 -}{\i \fs17 B}{\i \fs17 .}{\i \fs17 D}{\i
\fs17 =}{\i \fs17 Y }\par
}
Use De Morgan's theorem to convert the Boolean expression{\b\i
A}{\f10 \fs23 -}{\i \fs17 B}{\f10 \fs23 - }
\par}{\phpg\posx1445\pvpg\posy13036\absw5808\absh460 \sl-223 \f20 \fs17 \cf0 max
term form. Show each step as in Fig. 5-15. \par
}
{\phpg\posx6839\pvpg\posy12962\absw478\absh187 \f10 \fs16 \cf0 \f10 \fs16 \cf0 _
- - \par
}
\cf0 C{\b \f30 \fs19 D}{\f20 \fs21 +A-}{\b \f20 \fs17 B}{\i0 \fs23 -}{\b \f3
0 \fs19 C}{\i0 \fs23 -}{\b \f20 \fs17 D=}{\b \f20 \fs17 Y}{\i0 \f20 \fs17
to}{\i0 \f20 \fs17
its }\par
}
}
}
}
cf0 5.52 \par
}
0 98 \par
}
MPLIFYING{\fs17 LOGIC} CIRCUITS: MAPPING \par
}
AP.{\fs17 5 }\par
}
fs15 \cf0 Ans.{\b0\i0 \f20 \fs17
Minterm}{\b0\i0 \f20 \fs17 expression }
0 \fi540 {\b0\i0 \f20 \fs17 First}{\b0\i0 \f20 \fs17 step }
\cf0 \fi540 {\b0\i0 \f20 \fs17 Second}{\b0\i0 \f20 \fs17 step }
\cf0 \fi540 {\b0\i0 \f20 \fs17 Third}{\b0\i0 \f20 \fs17 step }
0 \fi541 {\b0\i0 \f20 \fs17 Fourth}{\b0\i0 \f20 \fs17 step }\par
}
\cf0 (A+{\b \fs24 B}{\i0 \f10 \fs27 +}{\i0 \f20 \fs31 c}{\i0 \f10 \fs27 + }\par
}
\cf0 (A=+{\b \f10 \fs25 B=}{\i0 \f10 \fs27 +}{\i0 \fs36 c= }\par
}
\cf0 0){\i0 \f10 \fs20 (}{\f30 \fs25 A+}{\dn006 \fs17 B}{\i0 \f10 \fs26 +}{\f
s32 c}{\i0 \f10 \fs26 + }\par
}
}
cf0 0) \par
}
{\i \fs24 E}{\i \fs24 )}{\i \fs24 .}{\i \f20 \fs26 (A=+}{\b\i \f30 \fs25 B} +
{\f20 \fs37 c=}+{\i \f20 \fs25 5) }\par
}
s24 \cf0 (A=+{\fs24 E}{\b0\i0 \fs27 +}{\f20 \fs26 F}{\b0\i0 \fs26 +}{\b0 E}
{\b0 )}{\b0\i0 \fs19 .}{\b0 \f30 \fs29 (A=+}{\f30 \fs25 B}{\b0\i0 \fs25 +}{
\b0 \f30 \fs30 F}{\b0\i0 \fs25 +}{\b0 E}{\b0 ) }
{\b0\i0 \f20 \fs17 eliminate}{\b0\i0 \f20 \fs17 double}{\b0\i0 \f20 \fs17 o
verbars }\par
}
axterm expression{\i
(}{\i A}{\i +}{\i B}{\i +}{\i c}{\i +}{\i D}{\i
)}{\i -}{\i (}{\i A}{\i +}{\i B}{\i +}{\i c}{\i +}{\i D}{\i )}{\i =
}{\i Y }\par
}
f0 5.53 \par
}
\cf0 Draw a 4-variable Karnaugh map. Plot two{\fs17 1s} on the map f
or the terms in the maxterm expression
5 developed in Prob.{\fs17 5.52.} Draw the appropriate loops around gro
ups of{\fs16 1s} on the map.

Am.}
}
s15 \cf0 C + D{\f30 \fs17 C}{\f30 \fs17 +}{\f30 \fs17 D}{\b0 \fs26 c+D}{\dn
006 \fs15 c }\par
}
15 \cf0 + D \par
}
15 \cf0 A + B \par
}
15 \cf0 A + B \par
}
17 \cf0 A + B
cf0 {\fs15 A}{\fs15 +}{\fs15 B }\par
}
\cf0 Fig.{\i \fs16 5-55}{\b0 \fs17
Completed}{\b0 \fs17 maxterm}{\b0 \fs17
map }\par
}
f0 5.54 \par
}
\cf0 Write the simplified maxterm Boolean expression based on the Karnaug
h map from Prob.{\fs17 5.53. }
i \f10 \fs15 Ans.}{\b\i \f10 \fs15
A}{\f10 \fs27 +}{\b\i\dn006 \fs17 C}{\f
10 \fs27 +}{\i\dn006 D}{\f10 \fs14 =}{\i Y }\par
}
5 \cf0 5.55 \par
}
\cf0 Draw an AND-OR logic circuit from the Boolean expression{\b\i \f10 \fs1
5 A}{\i
B }
i \f10 \fs15 Ans.}
See Fig.{\b\i \f10 \fs16 5-56. }\par
}
\f20 \fs32 c}{\fs23 - }\par
}
\cf0 D{\i0 \f10 \fs26 +}{\b\i0 \fs22 E}{\i0 \f10 \fs26 +}{\b \fs22 F}{\i0\dn00
6 \f10 \fs11 =}{\dn006 Y. }\par
}
s15 \cf0 B \par
}
\par
}
s15 \cf0 E
\cf0 F \par
}
\cf0 Fig.{\i \f10 \fs15 5-56}{\b0 \fs17
AND-OR}{\b0 \fs17 logic}{\b0 \fs1
7 circuit }\par
}
15 \cf0 5.56 \par
}
Draw a NAND logic circuit for the AND-OR circuit in Prob. 5.55. The
NAND logic circuit should \par
}
perform the logic{\b \fs17 in} the expression{\b\i \f10 \fs15 A}{\i
B
}\par
}
r
}
{\f20 \fs32 c}{\fs23 - }\par
}
s19 \cf0 D{\b0\i0 \f10 \fs25 +}{\f20 \fs22 E}{\b0\i0 \f10 \fs27 + }\par
}
{\i \f20 \fs17 Y. }\par
}
See}{\b0\i0 Fig.}{\b0\i0 5-57. }\par
}
.{\f10 \fs16 51 }\par
}
MPLIFYING LOGIC CIRCUITS: M.APPING \par
}
f0 99 \par
}
15 \cf0 E
cf0 {\f10 \fs14 F }\par
}
f0 I \par
}
\cf0 Fig.{\i \f10 \fs15 5-57}{\b0 \fs17
NAND}{\b0 \fs17 logiccircuit }\par
}
5 \cf0 5.57 \par
}
raw an OR-AND logic circuit for the Boolean expression
i \f10 \fs15 Ans.}

See Fig.{\b \f10 \fs16 5-58. }\par
}
\cf0 A.{\b \fs24 (B}{\i0 \f10 \fs26 +}{\b\dn006 \f20 \fs17 C}{\b\dn006 \f20 \fs
17 ) }\par
}
}
\b\i \f20 \fs17 E}{\dn006 \fs13 =}{\i \f20 \fs17 Y. }\par
}
15 \cf0 B
cf0 {\fs15 C }\par
}
{\phpg\posx6467\pvpg\posy6189\absw2175\absh229 \f10 \fs19 \cf0 \f10 \fs19 \cf0 {\b\i \f20 \fs15
A}{\b\i \f20 \fs15 .}{\b\i \f20 \fs15 (}{\b\i \f20 \fs15
B}{\b\i \f20 \fs15 +}{\b\i \f20 \fs15 C}{\b\i \f20 \fs15 )}{\b\i \f20 \
fs15 *}{\b\i \f20 \fs15 i}{\b\i \f20 \fs15 S}{\b\i \f20 \fs15 *}{\b\i \f
20 \fs15 E}{\b\i \f20 \fs15 =}{\b\i \f20 \fs14 Y }\par
}
s47 \cf0 Dj \par
}
15 \cf0 E \par
}
\cf0 Fig.{\i \f10 \fs15 5-58}{\b0 \fs17
OR-AND}{\b0 \fs17 logic}{\b0 \fs17
circuit }\par
}
f0 5-58 \par
}
raw a NOR logic circuit for the OR-AND circuit in Prob.{\i \fs17 5.57
.} The NOR circuit should perform the \par
}
ogic{\fs17 in} the expression{\i \f30 \fs23 2.( }{\b\i \fs21 E}{\b\i \fs21
+ }\par
}
{\phpg\posx4025\pvpg\posy8468\absw1121\absh274 \f10 \fs23 \cf0 \f10 \fs23 \cf0 ){\b\i\dn006 \f20 \fs16 D}{\i \f20 \fs22 }{\i \f20 \fs17
E}{\dn006 \fs11 =
}{\i \f20 \fs17 Y. }\par
}
}
15 \cf0 Ans. \par
}
ee Fig.{\b\i \f10 \fs16 5-59. }\par
}
14 \cf0 A \par
}
f0 1 \par
}
\par
}
s16 \cf0 D
{\f20 \fs15 E }\par
}
s11 \cf0 0 \par
}
\cf0 Fig.{\i \f10 \fs15 5-59}{\b0 \fs17
NOR}{\b0 \fs17 logiccircuit }\par
}
15 \cf0 5.59 \par
}
NOR logic can{\fs16 be} easily substituted in an \par
}
s15 \cf0 Ans. \par
}
(AND-OR, OR-AND) circuit. \par
}
NOR logic can be substituted for OR-AND circuits. \par
}
cf0 5.60 \par
}
Write the unsimplified sum-of-products Boolean expression for the truth ta
ble in Fig.{\b\i \f10 \fs16 5-60. }\par
}
s15 \cf0 Ans. \par
}
\fs25 \cf0 A.{\b \fs25 B}{\f20 \fs32 c}{\dn006 \f20 \fs22 D}{\i0 \f10 \fs25
+}A.{\b \fs24 B }
{\b \f20 \fs17 A}{\b \f20 \fs17 -}{\b \f20 \fs17 B}{\b \f20 \fs17 -}{\b \f
20 \fs17 C}{\b \f20 \fs17 ~}{\b \f20 \fs17 =}{\b \f20 \fs17 Y }\par
}
{\phpg\posx2421\pvpg\posy13356\absw330\absh95 \f10 \fs7 \cf0 \f10 \fs7 \cf0 *{\f
s6
* }\par
}
{\phpg\posx3531\pvpg\posy13192\absw315\absh274 \f10 \fs23 \cf0 \f10 \fs23 \cf0 {\b\i \f30 \fs18 C }\par
}
r
}
{\i \f30 \fs25 A.}{\fs23 - }\par
}
s17 \cf0 B{\fs16

C }\par
}
{\b\i \fs15 A} - \par
}
r
}
\cf0 c{\i0 \f10 \fs23 - }\par
}
{\b\i \fs15 .A}{\fs23 - }\par
}
s16 \cf0 C{\b0 \fs22 D}{\b0\i0 \f10 \fs25 + }\par
}
r
}
s15 \cf0 A{\f20 \fs17
B}{\b0 \f20 \fs32 c- }\par
}
r
}
r
}
\cf0 D{\i0 \f10 \fs25 + }\par
}
\par
}
}
}
puts \par
}
s17 \cf0 B
\cf0 {\i0 \fs17 0 }
{\i0 \f10 \fs15 0 }
\fi22 {\i0 \f10 \fs15 0 }
{\i0 \f10 \fs16 0 }
{\i0 \f10 \fs16 1 }
\fi28 {\i0 \f10 \fs16 1 }
\fi25 {\i0 \f10 \fs16 1 }
\fi29 {\i0 \f10 \fs16 1 }\par
}
s17 \cf0 C
\cf0 {\i0 \fs17 0 }
\fi22 {\i0 \f10 \fs15 0 }
\fi26 {\i0 \f10 \fs15 1 }
{\i0 \f10 \fs16 1 }
{\i0 \f10 \fs16 0 }
\fi34 {\i0 \f10 \fs16 0 }
\fi24 {\i0 \f10 \fs16 1 }
\fi32 {\i0 \f10 \fs16 1 }\par
}
s17 \cf0 A
\cf0 {\i0 \fs17 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs15 0 }
{\i0 \f10 \fs16 0 }
{\i0 \f10 \fs16 0 }
\fi22 {\i0 \f10 \fs16 0 }
\fi26 {\i0 \f10 \fs16 0 }
\fi26 {\i0 \f10 \fs16 0 }\par
}
s17 \cf0 D
\cf0 {\i0 \fs17 0 }
\fi26 {\i0 \f10 \fs15 1 }
\fi30 {\i0 \f10 \fs15 0 }
\fi44 {\i0 \f10 \fs16 1 }
{\i0 \f10 \fs16 0 }
\fi40 {\i0 \f10 \fs16 1 }
\fi24 {\i0 \f10 \fs16 0 }
\sl-222 \b\i \f20 \fs17 \cf0

\sl-217 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-248 \par\b\i \f20 \fs17
\sl-216 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-220 \b\i \f20 \fs17 \cf0
\sl-215 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-222 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-248 \par\b\i \f20 \fs17
\sl-216 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-220 \b\i \f20 \fs17 \cf0
\sl-215 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-222 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\f20 \fs17 \cf0 \b\i \f20 \f
\sl-248 \par\b\i \f20 \fs17
\sl-216 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-220 \b\i \f20 \fs17 \cf0
\sl-215 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\sl-222 \b\i \f20 \fs17 \cf0
\sl-217 \b\i \f20 \fs17 \cf0
\fi35 {\i0 \f10 \fs16 1 }\par

}
utput
\fi249 {\b Y }
\fi263 {\b \f10 \fs16 1 }
49 {\b \fs17 0 }
73 {\b \f10 \fs16 1 }
51 {\b 0 }
51 {\b \fs17 0 }
59 {\b 0 }
85 {\b \f10 \fs16 1 }
63 {\i \f10 \fs16 0 }\par
}
puts \par
}
s16 \cf0 B
\cf0 \fi26 {\i0 \f10 \fs16 0 }
\fi35 {\i0 \f10 \fs16 0 }
\fi33 {\i0 \f10 \fs15 0 }
\fi37 {\i0 \f10 \fs16 0 }
\fi33 {\i0 \f10 \fs16 1 }
\fi43 {\i0 \f10 \fs16 1 }
\fi47 {\i0 \f10 \fs16 1 }
\fi50 {\i0 \f10 \fs15 1 }\par
}
s16 \cf0 C
\cf0 \fi22 {\i0 \f10 \fs16 0 }
\fi33 {\i0 \f10 \fs16 0 }
\fi29 {\i0 \f10 \fs15 1 }
\fi37 {\i0 \f10 \fs16 1 }
\fi29 {\i0 \f10 \fs16 0 }
\fi41 {\i0 \f10 \fs16 0 }
\fi45 {\i0 \f10 \fs16 1 }

\fi51 {\i0 \f10 \fs15 1 }\par
}
s16 \cf0 A
\cf0 \fi30 {\i0 \f10 \fs16 1 }
\fi37 {\i0 \f10 \fs16 1 }
\fi37 {\i0 \f10 \fs15 1 }
\fi37 {\i0 \f10 \fs16 1 }
\fi37 {\i0 \f10 \fs16 1 }
\fi46 {\i0 \f10 \fs16 1 }
\fi50 {\i0 \f10 \fs16 1 }
\fi50 {\i0 \f10 \fs15 1 }\par
}
s16 \cf0 D
\cf0 {\i0 \f10 \fs16 0 }
\fi30 {\i0 \f10 \fs16 1 }
\fi25 {\i0 \f10 \fs15 0 }
\fi36 {\i0 \f10 \fs16 1 }
\fi25 {\i0 \f10 \fs16 0 }
\fi39 {\i0 \f10 \fs16 1 }
\fi43 {\i0 \f10 \fs16 0 }
\fi52 {\i0 \f10 \fs15 1 }\par
}
utput
\fi246 {\b Y }
\fi260 {\b \f10 \fs15 1 }
46 {\i \fs17 0 }
72 {\b \f10 \fs15 1 }
52 {\i \fs17 0 }
72 {\b \f10 \fs16 1 }
58 {\b 0 }
80 {\b \f10 \fs15 1 }
\sl-215 \b\i \f20 \fs16 \cf0

\f20 \fs16 \cf0 \b\i \f20 \f
\sl-246 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf0
\sl-216 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\sl-222 \b\i \f20 \fs16 \cf0
\sl-215 \b\i \f20 \fs16 \cf0
\f20 \fs16 \cf0 \b\i \f20 \f
\sl-246 \par\b\i \f20 \fs16
\sl-220 \b\i \f20 \fs16 \cf0
\sl-216 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0
\sl-220 \b\i \f20 \fs16 \cf0
\sl-217 \b\i \f20 \fs16 \cf0
\sl-222 \b\i \f20 \fs16 \cf0
\sl-215 \b\i \f20 \fs16 \cf0
\fs17 \cf0 \f20 \fs17 \cf0 o
\sl-239 \par\f20 \fs17 \cf0
\sl-246 \par\f20 \fs17 \cf0
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-216 \f20 \fs17 \cf0 \fi2
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-217 \f20 \fs17 \cf0 \fi2
\sl-222 \f20 \fs17 \cf0 \fi2

60 {\i \f10 \fs16 0 }\par
}
f0 5.61 \par
}
\cf0 Draw a 4-variable rninterm Karnaugh map. Plot seven{\fs16
1s}
on the map from the Boolean expression
6 developed in Prob. 5.60. Draw the appropriate loops around groups of{\b
1s} on the map.
i \fs17 Ans.}
See Fig. 5-61. \par
}
\cf0 Fig.{\f10 \fs15 5-61}{\b0 \fs17
Completed}{\b0 \fs17 minterm}{\b0 \fs1
7 map }\par
}
cf0 5.62 \par
}
\cf0 Write the simplified rninterm Boolean expression based on the Karn
augh map from Prob.{\fs17 5.61. }
\i Ans.}{\b \fs17
C}{\b \fs17 -}{\b \fs17 B}{\b\i \fs17 +}{\b\i \fs17 A}
{\b\i \fs17 -}{\b\i \fs17 B}{\f10 \fs27 +}{\i \fs17 B}{\i \fs17 .}{\i \fs17
D}{\i =Y }\par
}
}
}
cf0 5.63 \par
}
Write the unsimplified product-of-sums Boolean expression for the truth
table in Fig.{\fs17 5-60. }\par
}
fs17 \cf0 Ans.{\fs17
(}{\fs17 A}{\b0\i0 \f10 \fs24 +}{\fs17 B}{\b0\i0 \f
10 \fs27 +}{\fs17 C-+}{\b0 \f10 \fs19 0)}{\b0\i0 \f10 \fs23 -}{\b0 \f10 \fs20
0)}{\f10 \fs15 (}{\f10 \fs15 A}{\b0\i0 \f10 \fs27 +}{\b0\
i0 \f10 \fs24
+}{\b0\i0 \f10 \fs25
+ }\par
}
fs17 \cf0 C{\f30 \fs19 D)}{\f10 \fs15 (}{\f10 \fs15 A}{\b0\i0 \f10 \fs26 +}
{\b0\i0 \f10 \fs24
+}{\b0\i0 \f10 \fs23
+ }
0 \fi42 C{\b0 \fs21 +o)-(A+B+ }\par
}
r
}
s17 \cf0 C{\b0 \fs22
Is)}{\b0\i0 \f10 \fs23 - }\par
}
\cf0 * ( A + B {\i0 \f10 \fs26 +}{\b \fs17 C}{\i0 \f10 \fs25 +}{\f30 \fs25 D
).(A+B}{\b\dn006 \fs17 +}{\i0 \f10 \fs24 c}{\i0 \fs30 +}{\f30 \fs25 D)*(A+E}{\b
\dn006 \fs22 + }\par
}
r
}
fs16 \cf0 ( A{\b0\i0\dn006 \fs25 +}{\f20 \fs17 B}{\b0\i0 \fs23 +}{\b0\i0 \f20
\fs30 c+ }\par
}
\cf0 c+D){\i0 \f10 \fs13 =}{\fs17 Y }\par
}
s15 \cf0 ( A{\b0\i0 \fs25 + }\par
}
{\f20 \fs31 c+}{\b\i \f30 \fs25 D) }\par
}
cf0 5.64 \par
}
\cf0 Draw a 4-variable maxterm Karnaugh map. Plot nine{\b \fs16
1s}{\fs17 on} the map from the Boolean expression
25 developed in Prob.{\i 5.63.} Draw the appropriate loops around groups
of{\b 1s}{\fs17 on} the map.
\i Ans.}
See Fig. 5-62. \par
}
}
cf0 SIMPLIFYINGLOGIC CIRCUITS:MAPPING \par
}
f0 101 \par
}
s15 \cf0 C + n{\i0 \f20 \fs17 C}{\i0 \f20 \fs17 +}{\i0 \f20 \fs17 b}{\i0 \
f20 \fs17 C}{\i0 \f20 \fs17 +}{\i0 \f20 \fs17 b}{\fs14 C}{\fs14 +}{\fs14
D }\par
}
15 \cf0 A + B \par
}
13 \cf0 A + B \par
}
17 \cf0 A + R
cf0 {\f30 \fs18 A}{\f30 \fs18 +}{\f30 \fs18 R }\par
}
\cf0 Fig.{\f10 \fs16 5-62}{\b0 \f20 \fs17
Complctcd}{\b0 \f20 \fs17 maxtcrm}
{\b0 \f20 \fs17 map }\par
}
f0 5.65 \par
}
Writc{\fs17 the} simplifiedmaxterm Boolean cxprcssion based on the Karnaugh
map{\fs18 from} Prob.{\b\i \f10 \fs16 5.64. }
\i \f10 \fs16 Am.}{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 A}{\b\i \f10 \fs16 +
}{\b\i \f10 \fs16 B}{\b\i \f10 \fs16 +}{\b\i \f10 \fs16 C}{\b\i \f10 \fs16 )
}{\b\i \f10 \fs16 *}{\b\i \f10 \fs16 6}{\b\i \f10 \fs16 =}{\b\i \f10 \fs16 Y
}
{\f10 \fs16 The} simplified
(maxtcrm. minterm) form{\f
s18 of} Boolean cxprcssion is the easiest circuit to
20 implcmcnt for the{\fs17 truth} table{\fs18 in} Fig.{\b\i \f10 \fs16 5-6
0. }
\i \f10 \fs16 Am.}{\b \f10 \fs16
The}{\b\i \f10 \fs15 muxrmn} expression{
\b\i \f10 \fs16 (}{\b\i \f10 \fs16 A}{\f10 \fs20 +}{\b\i \fs23 E}{\f10 \fs25
-}{\f10 \fs25 -}{\f10 \fs51 - }
s17 than} the minterm expression{\b \f10 \fs16 C}{\f10 \fs31 -}{\fs22 6}{\f
10 \fs19 +}{\b\i \f10 \fs16 A}{\b\i \fs23 E}{\f10 \fs25 +}{\b\i \f10 \fs16
R}{\b\i \f30 \fs21 D}{\b\i \f30 \fs20 Y. }
Design{\b \f10 \fs16 a} logic circuit that will respond{\fs17 with} a{\b \f1
0 \fs16 1} when evcn numbers (decimals{\b \f10 \fs17 0.}{\b \f10 \fs16 2,4.
6,8)} appear at the
\par}{\phpg\posx1476\pvpg\posy4833\absw8873\absh2932 \sl-215 \f20 \fs17 \cf0 inp
uts. Figurc{\b \f30 \fs18 5-63} is thc{\b \f30 \fs20 DCD}{\b \f10 \fs16 (8
4421)} truth table{\b \f30 you}{\fs17 will} use{\fs18 in} this problem
.{\b\i \f10 \fs15 Write} the unsimplificd
\i \f10 \fs15 mintem} Roolcan expression for the truth table.
6366 ~ h{\fs16
expression}
repre\par}{\phpg\posx1476\pvpg\posy4833\absw8873\absh2932 \sl-221 \f20 \fs17 \cf0 sen
ts the{\b \fs17 Is}{\fs18 in} the{\b\i \f10 \fs16 Y} column{\fs18 of}{\fs1
7 the}{\fs16 truth} tahlc. Sixother groups of don't cares{\b \f10 \fs16 (X
's)} might also{\b \f30 \fs18 be} consid\par}{\phpg\posx1476\pvpg\posy4833\absw8873\absh2932 \sl-220 \f20 \fs17 \cf0 ere
d and{\fs17 will}{\fs17 be} plotted on the map. \par
}
{\b\i \fs16 C).}{\b\i \f30 \fs23 6}{\fs16 =}{\b\i \fs16 Y}{\b \f20 \fs18 ap
pears}{\b \fs16 to}{\b \fs16 bc}{\f20 \fs17 simpler}{\b \fs15 to}{\f20 \fs17
implement}{\f20 \fs17 with}{\f20 \fs17 logic}{\f20 \fs17 gates }\par
}
r
}
r
}

s16 \cf0 A~W.{\f30 \fs25 B}{\f30 \fs25 . }\par
}
s25 \cf0 ( 'I . ~ . ~ ~ + ~ . T . R . ~ + ~ . c . ~ ~ . / ~ + ~.Y{\fs21 .}c . R
{\b0\i0\dn006 \f20 \fs17 c}. ~ ~ + D . ~ . B . X - \par
}
6 \cf0 5.66 \par
}
f0 5.67 \par
}
\cf0 Fig.{\f10 \fs16 5-63}{\b0 \f20 \fs18 Truth}{\b0 \f20 \fs17 table}{\b0 \
f20 \fs17 with}{\b0 \f20 \fs17 don't}{\b0 \f20 \fs17 c}{\b0 \f20 \fs17 a}{\
b0 \f20 \fs17 m }\par
}
cf0 5.68 \par
}
\cf0 Draw a 4-variable mintcrm Karnaugh map. Plot five{\b \f30 \fs18 Is} and
six{\b \f10 \fs17 X's} (for{\fs17 the} don't cares)on the map based
\par}{\phpg\posx1466\pvpg\posy12907\absw8442\absh599 \sl-215 \f20 \fs17 \cf0 on
the truth table{\fs18 in} Fig.{\b \f30 \fs18 5-63.}Draw thc appropriate{
\fs17 loops} around groups of{\b \f10 \fs16 1s} and{\b \f10 \fs17 X's} on
the map.
\f10 \fs16 Am.}
Sce Fig.{\b\i \f30 \fs18 564. }\par
}
0 102 \par
}
}
AP.{\fs17 5 }\par
}
\cf0 Fig.{\f10 \fs15 5-64}{\b0 \fs17
Completed}{\b0 \fs17 minterm}{\b0 \fs1
7 maps}{\b0 \fs17 using}{\b0 \fs17 don't}{\b0 \fs17 cares }\par
}
6 \cf0 5.69 \par
}
\cf0 Write the simplified Boolean expression based on the Karnaugh map f
rom Prob. 5.68.
i \fs17 Ans.}{\b\i \f30 \fs25 L=}{\b\i \fs17 Y }\par
}
f0 5.70 \par
}
5 \cf0 -{\fs17
_}{\fs17
_}{\fs17
_ }

\i \f20 \fs17 Ans.}{\b\i \f20 \fs17
A}{\i \f20 \fs17
D}{\b\i \f20 \fs17
+}{\b\i \f20 \fs17 A}{\fs23 -}{\b\i \f20 \fs17 B}{\b \f20 \fs16
C}{\dn00
6 \fs13 =}{\i \f20 \fs17 Y.}{\f20 \fs17 The}{\f20 \fs17 use}{\b \f20 \fs17
of}{\f20 \fs17 the}{\f20 \fs17 don't}{\f20 \fs17 cares}{\f20 \fs17 grea
tly}{\f20 \fs17 aids}{\f20 \fs17 simplification}{\f20 \fs17 in}{\f20 \fs17
this}{\f20 \fs17 problem}{\f20 \fs17 because }
597 {\f20 \fs17 using}{\f20 \fs17 them}{\f20 \fs17 reduces}{\f20 \fs17 the}
{\f20 \fs17 expression}{\f20 \fs17 to}{\b \fs20 J=}{\i \f20 \fs17 Y. }
\fi31 {\f20 \fs17 In}{\f20 \fs17 this}{\f20 \fs17 chapter,}{\f20 \fs17 in
dividual}{\f20 \fs17 logic}{\f20 \fs17 gates}{\f20 \fs17 were}{\f20 \fs17
used}{\f20 \fs17 to}{\f20 \fs17 simplify}{\f20 \fs17 combinational}{\f20
\fs17 logic}{\f20 \fs17 problems.}{\f20 \fs17 List}{\f20 \fs17 several }
24 {\f20 \fs17 more}{\f20 \fs17 complex}{\b \f20 \fs17 ICs}{\f20 \fs17 used
}{\f20 \fs17 for}{\f20 \fs17 logic}{\f20 \fs17 circuit}{\f20 \fs17 simpli
fication. }
\i \f20 \fs17 Ans.}{\f20 \fs17
Several}{\f20 \fs17
ICs}{\f20 \fs17
us
ed}{\f20 \fs17
to}{\f20 \fs17
simplify}{\f20 \fs17 combinational}{\f20 \
fs17
logic}{\f20 \fs17 problems}{\f20 \fs17
are}{\f20 \fs17
data}{\f2
0 \fs17
selectors}{\f20 \fs17
(multiplexers), }
592 {\f20 \fs17 decoders,}{\f20 \fs17 PLAs,}{\f20 \fs17 ROMs,}{\f20 \fs17 an
d}{\f20 \fs17 PROMS. }
\fi24 {\f20 \fs17 Write}{\f20 \fs17 the}{\f20 \fs17 unsimplified}{\f20 \fs1
7 minterm}{\f20 \fs17 Boolean}{\f20 \fs17 expression}{\f20 \fs17 for}{\f20
\fs17 the}{\f20 \fs17 truth}{\f20 \fs17 table}{\f20 \fs17 in}{\f20 \fs1
7 Fig.}{\f20 \fs17 5-65. }\par
}
}
}
s17 \cf0 Ans.{\b0 \f30 \fs26 A-}{\f30 \fs25 B. }{\dn006 \fs16 C}{\f30 \fs25 -D
}{\b0\dn006 \fs17 E- }\par
}
\cf0 +A.B.{\i0 \f10 \fs23
- }\par
}
16 \cf0 C{\b0 \fs17
D}{\b0 \fs17
E }\par
}
}
\cf0 +A.{\dn006 \f20 \fs17 .}{\b \fs25 -}{\b \fs25 B- }\par
}
cf0 B{\b\i0 \fs16
C }\par
}
cf0 E{\f30 \fs26 +A.}{\i0 \f10 \fs23 - }\par
}
\cf0 B{\b \fs16
C} D E{\i0 \f10 \fs26 + }\par
}
}
}
s15 \cf0 A{\dn006 \f20 \fs17 .}{\f20 \fs17 B}{\f30 \fs20 .C.D}{\f20 \fs22 .}
{\f20 \fs22 E}{\f20 \fs17 +}{\f20 \fs17 A}{\f20 \fs17 .}{\f20 \fs17 B}{\b0
\f20 \fs17 .}{\b0 \f20 \fs17 C}{\b0 \f20 \fs17 -}{\b0 \f20 \fs17 D}{\b0 \f20
\fs17 *}{\b0 \f20 \fs17 E}+ A{\b0 \f20 \fs17 *}{\b0 \f20 \fs17 B}{\i0 \f20
\fs16 .}{\i0 \f20 \fs16 C}{\b0 \f20 \fs17 *}{\b0 \f20 \fs17 D}{\f20 \fs16 -}
{\f20 \fs16 E}{\f20 \fs16 +}{\f20 \fs16 A}{\f20 \fs17 *}{\f20 \fs17 B}{\i0
\f20 \fs16 *}{\i0 \f20 \fs16 C}{\b0 \f20 \fs17 .}{\b0 \f20 \fs17 D}{\b0 \f20 \
fs17 *}{\b0 \f20 \fs17 E }{\b0\i0\dn006 \fs11 =}{\b0 \f20 \fs17 Y }\par
}
rite the simplified Boolean expression based on the Karnaugh map from
Prob. 5.68{\b\i \fs17 without}{\b\i \fs17 using}{\b\i \fs17 the }
i \fs17 don't}{\b\i cares }{\dn006 \f10 \fs15 -}for simplification. \par
}
f0 5.71 \par
}
f0 5.72 \par
}
1 \par
}
s14 \cf0 A
\fi25 {\b0\i0 \f20 \fs15 0 }
\fi25 {\b0\i0 \f20 \fs14 0 }
\fi25 {\b0\i0 \f20 \fs15 0 }
\fi25 {\b0\i0 \f20 \fs15 0 }
\fi30 {\b0\i0 \f20 \fs14 0 }
\fi25 {\b0\i0 \f20 \fs15 0 }
\fi25 {\b0\i0 \f20 \fs15 0 }
\fi28 {\b0\i0 \f20 \fs15 0 }
\fi30 {\b0\i0 \f20 \fs15 0 }
\fi30 {\b0\i0 \f20 \fs15 0 }
\fi34 {\b0\i0 \f20 \fs14 0 }
\fi30 {\b0\i0 \f20 \fs14 0 }
\fi30 {\b0\i0 \f20 \fs15 0 }
\fi30 {\b0\i0 \f20 \fs15 0 }

\fi30 {\b0\i0 \f20 \fs14 0 }
\fi25 {\b0\i0 \f20 \fs15 0 }\par
}
s15 \cf0 B
{\b0\i0 \fs15 0 }
{\b0\i0 \fs15 0 }
{\b0\i0 \fs14 0 }
{\b0\i0 \fs15 0 }
{\b0\i0 \fs15 0 }
{\b0\i0 \fs15 0 }
{\b0\i0 \fs15 0 }
{\b0\i0 \fs15 0 }
\fi31 {\b0\i0 \f10 \fs14 1 }
\fi31 {\i0 \fs15 1 }
\fi27 {\b0\i0 \f10 \fs14 1 }
\fi35 {\i0 \fs15 1 }
\fi35 {\b0\i0 \fs15 1 }
\fi31 {\b0\i0 \f10 \fs14 1 }
\fi27 {\b0\i0 \f10 \fs14 1 }
\fi27 {\b0\i0 \f10 \fs14 1 }\par
}
\cf0 Inputs
fi166 {\b0\i \fs15 C }
fi180 {\b0 \fs14 0 }
fi180 {\b0 \fs14 0 }
fi176 {\b0 \fs15 0 }
fi176 {\b0 \fs14 0 }
fi190 {\fs15 1 }
fi196 {\fs15 1 }
fi190 {\b0 \f10 \fs14 1 }
fi192 {\b0 \fs15 1 }

fi180 {\b0 \fs14 0 }
fi180 {\b0 \fs14 0 }
fi184 {\b0 \fs14 0 }
fi180 {\b0 \fs15 0 }
fi196 {\b0 \fs15 1 }
fi190 {\fs15 1 }
fi190 {\b0 \f10 \fs13 1 }
fi196 {\b0 \fs15 1 }\par
}
s17 \cf0 D
\fi22 {\b0\i0 \f20 \fs15 0 }
\fi22 {\b0\i0 \f20 \fs15 0 }
\fi36 {\i0 \f20 \fs15 1 }
\fi40 {\b0\i0 \f10 \fs14 1 }
\fi22 {\b0\i0 \f20 \fs15 0 }
\fi22 {\b0\i0 \f20 \fs15 0 }
\fi31 {\b0\i0 \f10 \fs14 1 }
\fi39 {\b0\i0 \f20 \fs15 1 }
\fi22 {\b0\i0 \f20 \fs15 0 }
\fi21 {\b0\i0 \f20 \fs14 0 }
\fi36 {\i0 \f20 \fs14 1 }
\fi40 {\i0 \f20 \fs14 1 }
\fi23 {\b0\i0 \f20 \fs14 0 }
\fi22 {\b0\i0 \f20 \fs14 0 }
\fi36 {\i0 \f20 \fs15 1 }
\fi32 {\i0 \f20 \fs15 1 }\par
}
\cf0 E
\i0 \fs14 0 }
fi27 {\i0 \fs15 1 }
\i0 \fs14 0 }

fi25 {\i0 \f10 \fs14 1 }
\i0 \fs14 0 }
fi33 {\b\i0 \fs15 1 }
\i0 \fs14 0 }
fi33 {\i0 \fs14 1 }
\i0 \fs14 0 }
fi27 {\i0 \fs14 1 }
\i0 \fs14 0 }
fi27 {\b\i0 \fs14 1 }
fi20 {\i0 \fs14 0 }
fi27 {\i0 \f10 \fs14 1 }
\i0 \fs14 0 }
fi28 {\b\i0 \fs15 1 }\par
}
\cf0 output
fi202 {\i \fs15 Y }
fi210 {\b0 \fs15 0 }
fi210 {\b0 \fs14 0 }
fi210 {\b0 \fs15 0 }
fi210 {\b0 \fs14 0 }
fi210 {\b0 \fs14 0 }
fi228 {\b0 \fs15 1 }
fi210 {\b0 \fs15 0 }
fi226 {\b0 \f10 \fs14 1 }
fi214 {\b0 \fs15 0 }
fi214 {\b0 \fs15 0 }
fi214 {\b0 \fs14 0 }
fi214 {\b0 \fs15 0 }
fi214 {\b0 \fs15 0 }
fi228 {\b0 \fs15 1 }
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 \
\cf0 \
\cf0 {
\cf0 \
\fs14
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
fi210 {\b0 \fs15 0 }

fi222 {\b0 \f10 \fs13 1 }\par
}
\f10 \fs14 \cf0 A
\fi650 {\i0 \f20 \fs14 1 }
\fi653 {\b0\i0 \f20 \fs14 1 }
\fi650 {\b0\i0 \f20 \fs15 1 }
\fi650 {\b0\i0 \f20 \fs15 1 }
\fi650 {\b0\i0 \f20 \fs15 1 }
\fi653 {\i0 \f20 \fs15 1 }
\fi650 {\i0 \f20 \fs14 1 }
\fi653 {\b0\i0 \f20 \fs14 1 }
\fi650 {\b0\i0 1 }
\fi650 {\i0 \f20 \fs15 1 }
\fi650 {\i0 \f20 \fs15 1 }
\fi656 {\b0\i0 1 }
\fi653 {\i0 \f20 \fs15 1 }
\fi653 {\i0 \f20 \fs14 1 }
\fi650 {\i0 \f20 \fs15 1 }
\fi650 {\i0 \f20 \fs15 1 }
\cf0 {\i0 \f20 \fs16 Fig.}{\fs15 5-65 }\par
}
\cf0 R
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
\i0 \fs14 0 }
fi32 {\i0 \f10 \fs13 1 }

fi27 {\i0 \fs14 1 }
fi32 {\i0 \fs14 1 }
fi36 {\i0 \f10 \fs14 1 }
fi27 {\i0 \fs15 1 }
fi27 {\i0 \fs15 1 }
fi27 {\i0 \f10 \fs14 1 }
fi32 {\i0 \fs15 1 }\par
}
\cf0 Inputs
fi158 {\b0\i \fs15 C }
fi176 {\b0 \fs14 0 }
fi172 {\b0 \fs14 0 }
fi172 {\b0 \fs15 0 }
fi172 {\b0 \fs15 0 }
fi186 {\fs14 1 }
fi192 {\b0 \fs15 1 }
fi192 {\fs14 1 }
fi192 {\b0 \fs15 1 }
fi176 {\b0 \fs15 0 }
fi172 {\b0 \fs14 0 }
fi176 {\b0 \fs14 0 }
fi176 {\b0 \fs14 0 }
fi192 {\fs14 1 }
fi186 {\fs14 1 }
fi194 {\b0 \f10 \fs13 1 }
fi192 {\b0 \f10 \fs14 1 }\par
}
{\phpg\posx7559\pvpg\posy9846\absw146\absh3074 \i \f20 \fs15 \cf0 \i \f20
\cf0 D
fi22 {\i0 \fs14 0 }
fi22 {\i0 \fs14 0 }
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs14
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 \
\cf0 \
\cf0 \
fi36 {\i0 \f10 \fs13 1 }

fi32 {\b\i0 \fs15 1 }
fi22 {\i0 \fs14 0 }
fi22 {\i0 \fs14 0 }
fi36 {\i0 \f10 \fs14 1 }
fi33 {\b\i0 \fs15 1 }
fi22 {\i0 0 }
fi22 {\i0 0 }
fi36 {\i0 \fs14 1 }
fi36 {\b\i0 \fs15 1 }
fi22 {\i0 0 }
fi22 {\i0 0 }
fi36 {\i0 \f10 \fs14 1 }
fi32 {\b\i0 \fs15 1 }\par
}
\cf0 E
\i0 \fs15 0 }
fi27 {\i0 \fs15 1 }
\i0 \fs14 0 }
fi23 {\b\i0 \fs15 1 }
\i0 \fs15 0 }
fi27 {\i0 \fs15 1 }
\i0 \fs15 0 }
fi36 {\i0 \f10 \fs14 1 }
\i0 \fs14 0 }
fi27 {\i0 \f10 \fs14 1 }
\i0 \fs14 0 }
fi23 {\i0 \f10 \fs13 1 }
\i0 \fs14 0 }
fi27 {\i0 \fs15 1 }
\i0 \fs14 0 }
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {
\cf0 \
\cf0 {

fi27 {\i0 \f10 \fs14 1 }\par
}
\cf0 output
fi203 {\i \fs14 Y }
fi207 {\b0 \fs14 0 }
fi203 {\b0 \fs14 0 }
fi207 {\b0 \fs15 0 }
fi207 {\b0 \fs15 0 }
fi207 {\b0 \fs14 0 }
fi207 {\b0 \fs15 0 }
fi207 {\b0 \fs14 0 }
fi206 {\b0 \fs15 0 }
fi207 {\b0 \fs15 0 }
fi207 {\b0 \fs14 0 }
fi217 {\b0 \f10 \fs14 1 }
fi226 {\b0 \f10 \fs14 1 }
fi207 {\b0 \fs14 0 }
fi207 {\b0 \fs15 0 }
fi223 {\fs15 1 }
fi223 {\b0 \f10 \fs14 1 }\par
}
.{\fs17 51 }\par
}
}
\par
}
f0 5.73 \par
}
raw a 5-variable minterm Karnaugh map. Plot eight{\fs17
1s} on t
he map from the Boolean expression
loped in Prob.{\fs17 5.72.} Draw the appropriate loops around groups of{
\fs17 1s}{\fs17 on} the map.

i \fs17 Ans.}
}
cf0 Fig.{\fs17 5-66 }\par
}
f0 5.74 \par
}
rite the simplified minterm Boolean expression based on the Karnaugh map
from Prob.{\fs17 5.73. }
i \f10 \fs15 Ans.}{\b\i \fs17
A}{\b\i \fs17 -}{\b\i \fs17 B}{\b\i \fs17 .
}{\b\i \fs17 D}{\b\i \fs17 +}{\b\i \fs17 x}{\b\i \fs17 *}{\b\i \fs17 C}{\b\
i \fs17 .}{\b\i \fs17 E}{\b\i \fs17 =}{\b\i \fs17 Y }\par
}
{\b \fs33 TTL}{\b \fs33 and}{\b \fs33 CMOS}{\b \fs33 ICs:}{\b \fs33 Characte
ristics }
753 {\b \fs33 and}{\b \fs33 Interfacing }\par
}
\cf0 6-1{\fs19
INTRODUCTION }
fi362 {\b0 \fs19 The}{\b0 \fs19 growing}{\b0 \fs19 popularity}{\b0 of}{\b0 \f
s19 digital}{\b0 \fs19 circuits}{\b0 \fs19 is}{\b0 \fs19 due}{\b0 \fs19 in}
{\b0 \fs19 part}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 availability}{\b0 \f
s18 of}{\b0 \fs19 inexpensive}{\b0 \fs19 integrated }
\b0 \fs19 circuits}{\b0 \fs19 (ICs).}{\b0 \fs19 Manufacturers}{\b0 \fs19 hav
e}{\b0 \fs19 developed}{\b0 \fs19 many}{\i \fs19 families}{\b0 of}{\b0 \f
s19 digital}{\b0 \fs19 ICs-groups}{\b0 \fs19
that}{\b0 \fs19 can}{\b0
\fs19 be}{\b0 \fs19 used }
\b0 \fs19 together}{\b0 \fs19 in}{\b0 \fs19 building}{\b0 \fs19 a}{\b0 \fs19
digital}{\b0 \fs19 system.}{\b0 \fs19 The}{\b0 \fs19 ICs}{\b0 \fs19 in}{\b
0 \fs19 a}{\b0 \fs19 family}{\b0 \fs19 are}{\b0 \fs19 said}{\b0 \fs19 to}{\
b0 \fs19 be}{\b0 \fs19 compatible,}{\b0 \fs19 and}{\b0 \fs19 they}{\b0 \fs1
9 can}{\b0 \fs19 be }
\b0 \fs19 easily}{\b0 \fs19 connected. }
fi367 {\b0 \fs19 Digital}{\fs19 ICs}{\b0 \fs19 can}{\b0 \fs19 be}{\b0 \fs1
9 categorized}{\b0 \fs19 as}{\b0 \fs19 either}{\i \fs19 bipolar}{\b0 \fs
19 or}{\i \fs19 unipolar}{\b0 \f10 \fs22 .}{\b0 \fs19 Bipolar}{\b0 \fs19
digital}{\b0 \fs19 ICs}{\b0 \fs19 are}{\b0 \fs19 fabricated }
\b0 \fs19 from}{\b0 \fs19 parts}{\b0 \fs19 comparable}{\b0 \fs19 to}{\b0 \fs1
9 discrete}{\b0 \fs19 bipolar}{\b0 \fs19 transistors,}{\b0 \fs19 diodes,}{\
b0 \fs19 and}{\b0 \fs19 resistors.}{\b0 \fs19 The}{\b0 \fs19 TTL}{\b0 \fs19
(transistor-tran- }
\b0 \fs19 sistor}{\b0 \fs19 logic)}{\b0 \fs19 family}{\b0 \fs19 is}{\b0 \fs19
the}{\b0 \fs19 most}{\b0 \fs19 popular}{\b0 \fs19 of}{\b0 \fs19 the}{\b
0 \fs19 ICs}{\b0 \fs19 using}{\b0 \fs19 the}{\b0 \fs19 bipolar}{\b0 \fs19

technology.}{\b0 \fs19 Unipolar}{\b0 \fs19 digital}{\b0 \fs19 ICs }
\b0 \fs19 are}{\b0 \fs19 fabricated}{\b0 \fs19 from}{\b0 \fs19 parts}{\b0 \fs
19 comparable}{\b0 \fs19 to}{\b0 \fs19 insulated-gate}{\b0 \fs19 field-eff
ect}{\b0 \fs19 transistors}{\b0 \fs19 (IGFETs).}{\b0 \fs19 The}{\b0 \fs19 C
MOS }
\b0 \fs19 (complementary-metal-oxide}{\b0 \fs19 semiconductor)}{\b0 \fs19 fa
mily}{\b0 \fs19 is}{\b0 \fs19 a}{\b0 \fs19 widely}{\b0 \fs19 used}{\b0 \
fs19 group}{\b0 \fs19 of}{\b0 \fs19 ICs}{\b0 \fs19 based}{\b0 \fs19 on
}{\b0 \fs19 the }
\b0 \fs19 metal-oxide}{\b0 \fs19 semiconductor}{\fs19 (MOS)}{\b0 \fs19 techn
ology. }
fi362 {\b0 \fs19 Integrated}{\b0 \fs19 circuits}{\b0 \fs19 are}{\b0 \fs19 som
etimes}{\b0 \fs19 grouped}{\b0 \fs19 by}{\b0 \fs19 manufacturers}{\b0 \fs19
as}{\b0 \fs19 to}{\b0 \fs19 their}{\b0 \fs19 circuit}{\b0 \fs19 complexity.}
{\b0 \fs19 Circuit }
\b0 \fs19 complexity}{\b0 of}{\b0 \fs19 ICs}{\b0 \fs19 is}{\b0 \fs19 define
d}{\b0 \fs19 as}{\b0 \fs19 follows: }
fi368 {\b0 \fs19 1.}{\i \fs19
SSI}{\i \fs19 (small-scaleintegration}{\b0 \f
10 \fs16 ): }\par
}
umber{\fs19 of} gates:
\par}{\phpg\posx1569\pvpg\posy6919\absw1993\absh435 \sl-240 \f20 \fs19 \cf0 Typi
cal digital devices: \par
}
ess than{\fs19 12 }
s and flip-flops \par
}
\cf0 2.{\i
MSI}{\i \fs19 (medium-scaleintegration): }\par
}
umber{\fs18 of} gates:
}
2{\fs19 to} 99
\par}{\phpg\posx3895\pvpg\posy7690\absw4900\absh646 \sl-240 \f20 \fs19 \cf0 adde
rs, counters, decoders, encoders, multiplexers, and
\par}{\phpg\posx3895\pvpg\posy7690\absw4900\absh646 \sl-235 \f20 \fs19 \cf0 demu
ltiplexers, registers \par
}
\cf0 3.{\i \f20 \fs19
LSI}{\i \f20 \fs19 (large-scale}{\i \f20 \fs19 integr
ation}{\b0 \f20 \fs23 1: }\par
}
umber of gates:
}
00 to 9999
tal clocks, smaller memory chips, calculators \par
}
cf0 4. \par
}
\cf0 VLSI{\i0 \f10 \fs16 (}{\b uery-1arge-kcale}{\b integration}{\i0 \f10 \fs
16 ): }\par
}
umber of gates:
}
0,000{\fs19 to}{\fs19 99,999 }
19 microprocessors,}{\fs19 larger}{\fs19 memory}{\fs19 chips,}{\fs19 advance
d}{\fs19 calculators }\par
}
\cf0 5. \par
}
\cf0 ULSI{\b (ultra-large-scale}{\b integration): }\par
}
Number of gates:
\par}{\phpg\posx1569\pvpg\posy10252\absw1993\absh424 \sl-232 \f20 \fs19 \cf0 Typ
ical digital devices: \par
}
over 100,000
\par}{\phpg\posx3889\pvpg\posy10252\absw2357\absh424 \sl-232 \f20 \fs19 \cf0 adv
anced microprocessors \par
}
9 \cf0 Many digital IC families are available to the digital circuit designer,
and some{\fs18 of} them are listed
\par}{\phpg\posx855\pvpg\posy10836\absw8913\absh2476 \sl-235 \f20 \fs19 \cf0 bel
ow:
\fi389 {\fs18 1.}{\b\i
Bipolar}{\b\i \fs19 families: }
727 RTL
resistor-transistor logic
727 DTL diode-transistor logic
719 {\fs19 TTL}
transistor-transistor logic
1335 (types: standard TTL, low-power TTL, high-speed TTL, Schottky TTL,
1341 advanced low-power Schottky TTL, advanced Schottky TTL)
723 ECL
emitter-coupled logic
1335 (also called CML, current-mode logic)

729 HTL
high-threshold logic \par
}
IL \par
}
(also called HNIL, high-noise-immunity logic)
\par}{\phpg\posx2199\pvpg\posy13584\absw4058\absh787 \sl-237 \f20 \fs19 \cf0 int
egrated-injection logic
\fi2964 104 \par
}
0 CHAP.{\b0 \fs16 61 }\par
}
{\phpg\posx2519\pvpg\posy542\absw5474\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 TT
L{\b \fs17 AND}{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICS}{\b \
fs17 AND}{\b \fs17 INTERFACING }\par
}
{\phpg\posx9413\pvpg\posy521\absw365\absh219 \f20 \fs19 \cf0 \f20 \fs19 \cf0 1{\
i \fs19 05 }\par
}
\cf0 2.{\b\i \fs19
MOS}{\i \fs19 families: }
02 {\b \fs19 PMOS}{\fs19
P-channel}{\fs19 metal-oxide}{\fs19 semiconductor
}
02 {\b \fs19 NMOS}{\fs19
N-channel}{\fs19 metal-oxide}{\fs19 semiconductor
}
98 {\b \fs19 CMOS}{\fs19
complementary}{\fs19 metal-oxide}{\fs19 semicond
uctor }
58 {\fs19 The}{\b TITL}{\fs19 and}{\fs19 CMOS}{\fs19 technologies}{\fs19
are}{\fs19 commonly}{\fs19 used}{\fs19 to}{\fs19 fabricate}{\b \fs19
SSI}{\fs19 and}{\b \fs19 MSI}{\fs19 integrated }
19 circuits.}{\fs19 Those}{\fs19 circuits}{\fs19 include}{\fs19 such}{\fs19
functional}{\fs19 devices}{\fs19 as}{\fs19 logic}{\fs19 gates,}{\fs19 flip
-flops,}{\fs19 encoders}{\fs19 and}{\fs19 decoders, }
19 multiplexers,}{\fs19 latches,}{\fs19 and}{\fs19 registers.}{\fs19 MOS
}{\fs19 devices}{\fs19 (PMOS,}{\b \fs19 NMOS,}{\fs19 and}{\b \fs19 CMO
S)}{\fs19 dominate}{\fs19 in}{\fs19 the }
19 fabrication}{\fs19 of}{\fs19 LSI}{\fs19 and}{\fs19 VLSI}{\fs19 devi
ces.}{\b \fs19 NMOS}{\fs19 is}{\fs19 especially}{\fs19 popular}{\fs19
for}{\fs19 use}{\fs19 in}{\fs19 microprocessors}{\fs19 and }
19 memories.}{\b \fs19 CMOS}{\fs19 is}{\fs19 popular}{\fs19 for}{\fs19 use}
{\fs19 in}{\fs19 very}{\fs19 low}{\fs19 power}{\fs19 applications}{\fs19 s
uch}{\fs19 as}{\fs19 calculators,}{\fs19 wrist}{\fs19 watches, }
19 and}{\fs19 battery-powered}{\fs19 computers. }\par
}

\cf0 6-2{\f20 \fs19 DIGITAL}{\f20 \fs19 IC}{\f20 TERMS }
fi366 {\b0 \f20 \fs19 Several}{\b0 \f20 \fs19 terms}{\b0 \f20 \fs19 that}{\b
0 \f20 \fs19 appear}{\b0 \f20 \fs19 in}{\f20 \fs19 IC}{\b0 \f20 \fs19 ma
nufacturers'}{\b0 \f20 \fs19 literature}{\b0 \f20 \fs19 assist}{\b0 \f20 \fs
19 the}{\b0 \f20 \fs19 technician}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 usi
ng}{\b0 \f20 \fs19 and }
\b0 \f20 \fs19 comparing}{\b0 \f20 \fs19 logic}{\b0 \f20 \fs19 families.}{\b0
\f20 \fs19 Some}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 more
}{\b0 \f20 \fs19 important}{\b0 \f20 \fs19 terms}{\b0 \f20 \fs19 and}{\b0 \f2
0 \fs19 characteristics}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 digital}{\f20 \f
s19 ICs}{\b0 \f20 \fs19 will}{\b0 \f20 \fs19 be }
\b0 \f20 \fs19 outlined. }
fi365 {\b0 \f20 \fs19 How}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
logical}{\b0 \f20 \fs19 0}{\b0 \f20 (LOW)}{\b0 \f20 \fs19 or}{\b0 \f20 \fs1
9 a}{\b0 \f20 \fs19 logical}{\b0 \f20 \fs19 1}{\b0 \f20 \fs19 (HIGH)}{\b0 \f
20 \fs19 defined?}{\b0 \f20 \fs19 Figure}{\b0\i \f20 6-la}{\b0 \f20 \fs19 s
hows}{\b0 \f20 \fs19 an}{\b0 \f20 \fs19 inverter}{\b0 \f20 \fs19 (such}{\b0 \
f20 \fs19 as }
\b0 \f20 \fs19 the}{\b0 \f20 \fs18 7404)}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19
the}{\b0 \f20 TTL}{\b0 \f20 IC}{\b0 \f20 \fs19 family.}{\b0 \f20 \fs19 The}
{\b0 \f20 \fs19 manufacturers}{\b0 \f20 \fs19 specify}{\b0 \f20 \fs19 tha-t,f
or}{\b0 \f20 \fs19 proper}{\b0 \f20 \fs19 operation,}{\b0 \f20 \fs19 a}{\b0\i
\f20 LOW}{\b0\i \f20 input }\par
}
cf0 Input voltage \par
}
\cf0 Output voltage \par
}
\cf0 Typical{\fs15 3.5}{\fs14 V }
f0 \fi576 {\fs15 2.4}{\fs15 V }\par
}
15 \cf0 + 5
cf0 {\i0 \fs14 +4 }
cf0 {\i0 \f20 \fs15 +}{\i0 \f20 \fs15 3 }\par
}
\par
}
cf0 0.4{\f20 \fs15 V }\par
}
\cf0 (a){\fs15 TTL}{\fs14 input}{\fs14 and}{\fs14 output}{\fs14 voltage}{\
fs14 levels }
f0 \fi2240 {\b0\i \f10 \fs14 9.95}{\b0 \fs21 v }\par
}

\cf0 Output voltage \par
}
{\phpg\posx8051\pvpg\posy9692\absw449\absh253 \f20 \fs15 \cf0 \f20 \fs15 \cf0 +I
0{\fs22 v }\par
}
s15 \cf0 +5{\b0\i0 \f20 \fs22 v }\par
}
\cf0 CMOS \par
}
{\phpg\posx3617\pvpg\posy12587\absw3326\absh998 \i \f20 \fs15 \cf0 \fi2541 \i \f
20 \fs15 \cf0 0.05{\i0 \fs21 v }
cf0 \fi215 {\b\i0 \fs15 (6)}{\b\i0 \fs15 CMOS}{\b\i0 \fs14 input}{\b\i0 \fs14
and}{\b\i0 \fs14 output}{\b\i0 \fs14 voltage}{\b\i0 \fs14 levels }
cf0 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 6-1}{\b\i0 \fs17
Defining}{\b\i0 \fs17 l
ogical}{\b\i0 \fs17 HIGH}{\b\i0 \fs17 and}{\b\i0 \fs17 LOW }\par
}
\cf0 GND \par
}
\par
}
L AND{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICS}{\fs17 AND}{\b
\fs17 INTERFACING }\par
}
}
{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \f20 \fs18 \cf0 \f20 \fs18 \cf0 m
ust range from GND to 0.8 V. Likewise, a{\i HIGH}{\i input} must r
ange from 2.0 V to{\fs19 5.0} V. The
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-237 \f20 \fs18 \cf0 unsh
aded section in Fig.{\i 6-l(a)}between{\fs18 0.8} V and 2.0 V on the input sid
e is the forbidden region. An
t voltage{\fs19 of}{\fs19 0.5} V would then be a LOW input, whereas an
input{\fs19 of}{\i 2.6}{\fs18 V} would be a HIGH
t.{\b\i \f10 \fs17 An} input{\fs19 of}{\fs19 1.5}{\fs19 V} would yield un
predictable results and is considered a forbidden input. The
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-236 \f20 \fs18 \cf0 forb
idden region might also be called the uncertain or undefined region.
67 The expected outputs are shown on the right side of the TTL inverter shown in
Fig.{\i 6-la.}A{\i \fs19 LOW }
output} would typically be{\fs19 0.1}{\fs19 V} but could be as high a
s 0.4 V. A{\i HIGH}{\i output} would typically be
19 3.5}{\fs19 V} but could be as low as 2.4 V. The{\i \fs19 HIGH} output dep
ends on the resistance value of the load at
output. The greater the load current, the lower the HIGH output voltage. The un
shaded portion
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-237 \f20 \fs18 \cf0 on t
he output voltage side in Fig.{\i 6-la,} is the forbidden region.
73 Observe the difference in the definition of a HIGH from input to output in
Fig.{\i 6-la.} The input
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-236 \f20 \fs18 \cf0 HIGH
is defined as greater than 2.0 V, whereas the output HIGH{\fs18 is} greater
than 2.4 V. The reason
this difference is to provide for{\i noise} immunity-the
digital c
ircuit's insensitivity to undesired
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-238 \f20 \fs18 \cf0 elec
trical signals. The input LOW is less than{\fs18 0.8} V and the output LOW{\fs
18 is} 0.4{\b V} or less. Again the
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-237 \f20 \fs18 \cf0 marg
in between those figures is to assure rejection of unwanted noise entering the
digital system.
67 The voltage ranges defining HIGH and LOW are different for each logic family.
For comparison,
input and output voltages for a typical CMOS inverter are given in Fig.{\i 6-l
b.} In this example the
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-234 \f20 \fs18 \cf0 manu
facturer specifies that the HIGH{\i output} will be nearly the full supply v
oltage (over +9.95{\fs18 V).} A
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-239 \f20 \fs18 \cf0 LOW{
\i output} will be within{\fs19 0.05}{\fs19 V}{\fs19 of} ground (GN
D) potential. Manufacturers also specify that a
IC will consider{\i any}{\i input}{\i voltage}{\i \fs19 from}{\f10 \fs28
+}{\i \fs18 7}{\i V}{\i to}{\f10 \fs28 +}{\i 10}{\i \fs18 V}{\i as}{\i
a}{\i HIGH.} Figure{\fs19 6-1}{\i \fs18 b} also notes
a CMOS IC will consider any input voltage from GND to{\b \fs19 +}{\b \fs19
3}{\fs18 V} as{\fs19 a} LOW.
70 CMOS ICs have a wide swing of output voltages approaching both rail
s{\fs18 of} the power supply
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-237 \f20 \fs18 \cf0 (GND
and{\fs18
+10} V in this example).{\b \fs19 CMOS}{\b \fs19 ICs} al
so have very good noise immunity. Both these
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-242 \f20 \fs18 \cf0 char
acteristics, along with low power consumption, are listed as{\i advantages
}{\fs19 of}{\b \fs19 CMOS} over{\b \fs19 TTL} ICs.
74 Because of the high operating speeds of many digital circuits, inter
nal switching delays become
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-232 \f20 \fs18 \cf0 impo
rtant. Figure 6-2 is a waveform diagram of the input and output from an inverter
circuit. At point
\f10 \fs16 a} on the diagram, the input is going from LOW to HIGH{\fs18 (0} to{
\fs18 1).} A short time later the output of the
rter goes from HIGH to{\fs19 LOW} (1 to{\fs19 0).} The delay time, shown as{\
i tPLI1, i} s called the{\i propagation }
delay} of the inverter. This propagation delay may be about 20 nanoseconds

(ns) for a standard TTL
rter. At point{\i \fs18 b} in Fig.{\i 6-2,} the input is going from HIGH to L
OW. A short time later, the output
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-244 \f20 \fs18 \cf0 goes
from LOW to HIGH. The propagation delay{\i (}{\i t}{\i p}{\i k}{\i j}
{\i L}is){\i } shown as about 15 ns for this standard
19 'ITL} inverter. Note that the propagation delay may be different for the L-to
-H transition of the input
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-235 \f20 \fs18 \cf0 than
for the H-to-L transition. Some IC families have shorter propagation delays,
which makes them
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-239 \f20 \fs18 \cf0 more
adaptable for high-speed operation. Propagation delays range from an average l
ow{\fs19 of} about{\fs19 1.5 }
\par}{\phpg\posx837\pvpg\posy1350\absw9375\absh7483 \sl-234 \f20 \fs18 \cf0 ns f
or the Advanced Schottky TTL family to a high{\fs19 of} about 125 ns for the
HTL{\fs19 IC} family. \par
}
13 \cf0 a
cf0 \fi30 {\b0\i0 \f20 \fs18 I }
\fi30 {\i0 \fs14 1 }\par
}
\cf0 Time{\f30 \fs15 (ns)- }\par
}
\cf0 output \par
}
15 \cf0 b
cf0 \fi33 {\b0\i0 \fs16 I }
\fi33 {\b0\i0 \f10 \fs17 ! }
\fi33 {\b0\i0 \f10 \fs13 I }
\fi33 {\b0\i0 \f10 \fs14 I }\par
}
cf0 I
\f10 \fs11 0 }\par
}
\fs10 \cf0 ~ P L H
\b0\i \f10 \fs15 z}{\fs15 20}{\fs15 ns }\par
}
\fs10 \cf0 ~ P H L
\i \fs15 z}{\f10 \fs14 15}{\fs15 ns }\par
}

20 \fs16 \cf0 Fig.{\fs16 6-2}{\fs17
Waveforms}{\fs17 showing}{\fs17 prop
agation}{\fs17 delays}{\fs17 for}{\fs17 a}{\fs17 standard}{\fs17 TTL}{\fs1
7 inverter }
cf0 \fi371 {\b0 \fs18 CMOS}{\b0 \fs18 ICs}{\b0 \fs18 are}{\b0 \fs18 noted}{\b
0 \fs18 for}{\b0 \fs18 their}{\b0 \fs18 low}{\b0 \fs18 speed}{\b0 \fs18 (
higher}{\b0 \fs18 propagation}{\b0 \fs18 delays).}{\b0 \fs18 A}{\b0 \fs18 co
mmon}{\b0 \fs18 type}{\b0 \fs18 of}{\b0 \fs18 CMOS }
{\b0 \fs18 IC}{\b0 \fs18 may}{\b0 \fs18 have}{\b0 \fs18 a}{\b0 \fs18 propag
ation}{\b0 \fs18 delay}{\b0 \fs18 of}{\b0 \fs18 from}{\b0 \fs18 25}{\b0 \
fs18 to}{\b0 \fs18 100}{\b0 \fs18 ns,}{\b0 \fs18 depending}{\b0 \fs19 on}{
\b0 \fs18 the}{\b0 \fs18 device.}{\b0 \fs18 However,}{\b0 \fs18 a}{\b0 \f
s18 newer }
{\b0 \fs18 subfamily}{\b0 \fs18 of}{\b0\i \fs18 high-speed}{\i \fs19 CMOS}{
\b0 \fs18 ICs}{\b0 \fs18 has}{\b0 \fs18 reduced}{\b0 \fs18 the}{\b0 \fs18
propagation}{\b0 \fs18 delays.}{\b0 \fs18 For}{\b0 \fs18 instance,}{\b0
\fs18 the}{\b0 \fs18 74HC04 }
{\b0 \fs18 CMOS}{\b0 \fs18 inverter}{\b0 \fs18 has}{\b0 \fs18 a}{\b0 \fs18 p
ropagation}{\b0 \fs18 delay}{\b0 \fs18 of}{\b0 \fs18 only}{\b0 \fs18 8}{\b0
\fs18 ns.}{\b0 \fs18 These}{\b0 \fs18 high-speed}{\b0 \fs18 CMOS}{\b0 \fs1
8 ICs}{\b0 \fs18 make}{\b0 \fs18 this}{\b0 \fs18 family }
{\b0 \fs18 much}{\b0 \fs18 more}{\b0 \fs18 suitable}{\b0 \fs18 for}{\b0 \fs18
higher-speed}{\b0 \fs18 applications. }\par
}
}
L{\fs17 AND}{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICS}{\f10 \f
s16 ANT)}{\b \fs17 INTERFACING }\par
}
\par
}
\cf0 Integrated circuits are grouped into{\i families} because they are comp
atible. Figure{\i 6-3a} shows the
\par}{\phpg\posx843\pvpg\posy1349\absw9265\absh1067 \sl-237 \f20 \fs18 \cf0 left
{\fs19 TTL} inverter driving the right load inverter. In this case{\i conuenti
onal}{\i current} flows from the load
\par}{\phpg\posx843\pvpg\posy1349\absw9265\absh1067 \sl-237 \f20 \fs18 \cf0 devi
ce to the driver gate and to ground as illustrated in Fig.{\i 6-3a.} It is sa
id that the driver inverter is
\fs19 sinking}{\i \fs19 the}{\i current} (sinks current to ground). Th
is sinking current may be{\fs19 as} high as{\i 1.6} mA
\par}{\phpg\posx843\pvpg\posy1349\absw9265\absh1067 \sl-234 \f20 \fs18 \cf0 (mil
liamperes) from a single{\fs19 TTL} load. Note the direction of a sinking curr
ent. \par
}
fs16 \cf0 TTL
fs14 driver }
i36 {\f10 \fs14 +5}{\b0 \fs21 v }\par
}
L
{\fs14 load }
\par}{\phpg\posx6107\pvpg\posy2814\absw440\absh581 \sl-245 \f20 \fs16 \cf0 {\i\d
n006 \fs15 +5}{\fs22 v }\par
}
cf0 HIGH \par
}
cf0 HIGH \par
}
\cf0 ( U ) \par
}
cf0 TTL
fs14 driver }\par
}
\cf0 Sinking drive current{\fs14 to} ground
f0 \fi1813 {\b0 \fs15 'TTL }
fi1827 {\b0 \fs15 load }
fi1807 {\f10 \fs14 +5,}{\b0 \fs21 v }\par
}
\f20 \fs14 \cf0 (h){\i0 \fs14 Source}{\i0 \fs14 drive}{\i0 \fs14 current }
\cf0 \fi4066 {\i0 \fs16 Fig.}{\i0 \fs16 6-3 }
\cf0 \fi364 {\b0\i0 \fs18 When}{\b0\i0 \fs18 the}{\b0\i0 \fs18 output}{\b0\i0
\fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 driver}{\b0\i0 \f
s18 goes}{\b0\i0 \fs19 HIGH,}{\b0\i0 \fs18 the}{\b0\i0 \fs18 situation}{\b0\
i0 \fs19 in}{\b0\i0 \fs18 Fig.}{\fs18 6-3b}{\b0\i0 \fs18 is}{\b0\i0 \fs18 c
reated.}{\b0\i0 \fs18 In}{\b0\i0 \fs18 this}{\b0\i0 \fs18 case }
{\b0 \fs18 conventional}{\fs18 current}{\b0\i0 \fs18 flows}{\b0\i0 \fs18 fr
om}{\b0\i0 \fs18 the}{\b0\i0 \fs18 driver}{\b0\i0 \fs18 to}{\b0\i0 \fs18
the}{\b0\i0 \fs18 load}{\b0\i0 \fs18 device}{\b0\i0 \fs18 as}{\b0\i0 \fs18
illustrated.}{\b0\i0 \fs18 It}{\b0\i0 \fs18 is}{\b0\i0 \fs18 said}{\b0\i0
\fs18 that}{\b0\i0 \fs18 the}{\b0\i0 \fs18 driver }
{\b0\i0 \fs18 inverter}{\b0\i0 \fs18 is}{\b0 \fs19 sourcing}{\b0 \fs18 th
e}{\b0 \fs18 current.}{\b0\i0 \fs18 This}{\b0\i0 \fs18 sourcing}{\b0\i0 \f
s18 current}{\b0\i0 \fs18 is}{\b0\i0 \fs18 quite}{\b0\i0 \fs18 low}{\b0\i0
\fs18 when}{\b0\i0 \fs18 it}{\b0\i0 \fs18 is}{\b0\i0 \fs18 driving}{\b0\
i0 \fs18 a}{\b0\i0 \fs18 single}{\b0\i0 \fs18 load }
{\b0\i0 \fs18 (perhaps}{\b0\i0 \fs18 only}{\b0\i0 \fs18 40}{\f10 \fs15 p}{\
i0 \fs19 A,}{\b0\i0 \fs18 microamperes). }
\fi367 {\b0\i0 \fs18 The}{\b0\i0 \fs18 current}{\b0\i0 \fs18 driving}{\b0\i0

\fs18 capabilities}{\b0\i0 \fs18 of}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 gate
s}{\b0\i0 \fs18 vary}{\b0\i0 \fs18 from}{\b0\i0 \fs18 family}{\b0\i0 \fs18 t
o}{\b0\i0 \fs18 family.}{\b0\i0 \fs18 As}{\b0\i0 \fs18 a}{\b0\i0 \fs18 gener
al}{\b0\i0 \fs18 rule,}{\b0\i0 \fs18 TTL }
{\b0\i0 \fs18 ICs}{\b0\i0 \fs18 can}{\b0\i0 \fs18 sink}{\b0\i0 \fs18 more}{\
b0\i0 \fs18 current}{\b0\i0 \fs18 than}{\b0\i0 \fs18 they}{\b0\i0 \fs18 can
}{\b0\i0 \fs18 source.}{\b0\i0 \fs18 For}{\b0\i0 \fs18 instance,}{\b0\i0 \fs
18 a}{\b0\i0 \fs18 standard}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 gate}{\b0\i0 \f
s18 used}{\b0\i0 \fs18 for}{\b0\i0 \fs18 driving }
{\b0\i0 \fs18 a}{\b0\i0 \fs18 load}{\b0\i0 \fs18 can}{\b0\i0 \fs18 sink}{\b
0\i0 \fs18 up}{\b0\i0 \fs18 to}{\b0 \fs18 16}{\b0\i0 \fs18 mA,}{\b0\i0 \fs1
8 whereas}{\b0\i0 \fs18 a}{\b0\i0 \fs18 low-power}{\b0\i0 \fs18 Schottky}{\
b0\i0 \fs19 TTL}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 can}{\b0\i0 \fs18 sink}{\b
0\i0 \fs18 only}{\b0\i0 \fs18 a}{\b0\i0 \fs18 maximum}{\b0\i0 \fs18 of }
{\b0\i0 \fs18 8}{\b0\i0 \fs18 mA. }
\fi368 {\b0\i0 \fs18 CMOS}{\b0\i0 \fs18 output}{\b0\i0 \fs18 drive}{\b0\i0
\fs18 currents}{\b0\i0 \fs18 are}{\b0\i0 \fs18 nearly}{\b0\i0 \fs18 the}
{\b0\i0 \fs18 same}{\b0\i0 \fs18 when}{\b0\i0 \fs18 sinking}{\b0\i0 \fs18
or}{\b0\i0 \fs18 sourcing}{\b0\i0 \fs18 current.}{\b0\i0 \fs18 A}{\b0\i0
\fs18 typical }
{\b0\i0 \fs18 CMOS}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 might}{\b0\i0 \fs18 have
}{\b0\i0 \fs18 a}{\b0\i0 \fs18 drive}{\b0\i0 \fs18 capability}{\b0\i0 \fs18
of}{\b0\i0 \fs18 about}{\b0\i0 \fs19 0.5}{\b0\i0 \fs18 mA.}{\b0\i0 \fs18 The
}{\b0\i0 \fs18 high-speed}{\b0\i0 \fs18 CMOS}{\b0\i0 \fs18 series}{\b0\i0 \fs
18 of}{\b0\i0 \fs18 ICs}{\b0\i0 \fs18 (such }
{\b0\i0 \fs18 as}{\b0\i0 \fs18 the}{\i0 \fs19 74HC02)}{\b0\i0 \fs18 feature}
{\b0\i0 \fs18 sinking}{\b0\i0 \fs18 or}{\b0\i0 \fs18 sourcing}{\b0\i0 \fs18
drive}{\b0\i0 \fs18 currents}{\b0\i0 \fs18 of}{\b0\i0 \f10 \fs17 4}{\b0\i0 \
fs18 mA. }
\fi380 {\b0\i0 \fs18 It}{\b0\i0 \fs18 is}{\b0\i0 \fs18 common}{\b0\i0 \fs18
in}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 circuits}{\b0\i0 \fs18 to}{\b0\i0 \fs18
have}{\b0\i0 \fs18 one}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 drive}{\b0\i0 \fs18
several}{\b0\i0 \fs18 others.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 limitation}{\
b0\i0 \fs18 of}{\b0 \fs19 how}{\b0 \fs18 many }
{\b0\i0 \fs18 gates}{\b0\i0 \fs18 can}{\b0\i0 \fs18 be}{\b0\i0 \fs18 driven}
{\b0\i0 \fs18 by}{\b0\i0 \fs18 a}{\b0\i0 \fs18 single}{\b0\i0 \fs18 output}{
\b0\i0 \fs18 is}{\b0\i0 \fs18 called}{\b0\i0 \fs18 the}{\b0 \fs18 fan-out}{\
b0\i0 \fs18 of}{\b0\i0 \fs18 a}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 circuit.}
{\b0\i0 \fs18 The}{\b0\i0 \fs18 typical}{\b0\i0 \fs18 fan-out}{\b0\i0 \fs18
for }
{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 circuits}{\b0\i0 \fs18 i
s}{\b0\i0 \fs18 10.}{\b0\i0 \fs18 This}{\b0\i0 \fs18 means}{\b0\i0 \fs18
that}{\b0\i0 \fs18 a}{\b0\i0 \fs18 single}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18
output}{\b0\i0 \fs18 can}{\b0\i0 \fs18 drive}{\b0\i0 \fs18 up}{\b0\i0 \fs1
8 to}{\b0\i0 \fs18 10}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 inputs.}{\b0\i0 \fs1
8 The }
{\b0\i0 \fs18 CMOS}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 family}{\b0\i0 \fs18 ha
s}{\b0\i0 \fs18 a}{\b0\i0 \fs18 fan-out}{\b0\i0 \fs18 of}{\b0\i0 \fs19 50. }
\fi371 {\b0\i0 \fs18 One}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 m

any}{\b0\i0 \fs18 advantages}{\b0\i0 \fs18 of}{\b0\i0 \fs18 ICs}{\b0\i0 \fs
18 over}{\b0\i0 \fs18 other}{\b0\i0 \fs18 circuits}{\b0\i0 \fs18 is}{\b0\i0
\fs18 their}{\b0\i0 \fs18 low}{\b0\i0 \fs18 power}{\b0\i0 \fs18 dissipati
on.}{\b0\i0 \fs18 Some}{\b0\i0 \fs18 IC }
{\b0\i0 \fs18 families,}{\b0\i0 \fs18 however,}{\b0\i0 \fs18 have}{\b0\i0 \
fs18 much}{\b0\i0 \fs18 lower}{\b0\i0 \fs18 power}{\b0\i0 \fs18 dissipat
ion}{\b0\i0 \fs18 than}{\b0\i0 \fs18 others.}{\b0\i0 \fs18 The}{\b0\i0 \fs
18 power}{\b0\i0 \fs18 consumption}{\b0\i0 \fs18 might }
{\b0\i0 \fs18 average}{\b0\i0 \fs18 about}{\b0\i0 \fs18 10}{\b0\i0 \fs18 mi
lliwatts}{\b0\i0 \fs18 (mW)}{\b0\i0 \fs18 per}{\b0\i0 \fs18 gate}{\b0\i0 \fs1
8 in}{\b0\i0 \fs18 the}{\b0\i0 \fs18 standard}{\b0\i0 \fs18 TTI,}{\b0\i0 \fs
18 family,}{\b0\i0 \fs18 whereas}{\b0\i0 \fs18 it}{\b0\i0 \fs18 might}{\b0
\i0 \fs18 be}{\b0\i0 \fs18 as}{\b0\i0 \fs18 low}{\b0\i0 \fs18 as }
\fi21 {\b0 \fs18 1}{\b0\i0 \fs18 mW}{\b0\i0 \fs18 per}{\b0\i0 \fs18 gate}{\b
0\i0 \fs18 in}{\b0\i0 \fs18 the}{\b0\i0 \fs18 low-power}{\b0\i0 \fs19 TTL}{\
b0\i0 \fs18 family.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 CMOS}{\b0\i0 \fs18 famil
y}{\b0\i0 \fs18 is}{\b0\i0 \fs18 noted}{\b0\i0 \fs18 for}{\b0\i0 \fs18 its}
{\b0\i0 \fs18 extremely}{\b0\i0 \fs18 low}{\b0\i0 \fs18 power }
{\b0\i0 \fs18 consumption}{\b0\i0 \fs18 and}{\b0\i0 \fs18 is}{\b0\i0 \fs18 w
idely}{\b0\i0 \fs18 used}{\b0\i0 \fs18 in}{\b0\i0 \fs18 battery-operated}{\b
0\i0 \fs18 portable}{\b0\i0 \fs18 products. }
\cf0 {\i0 \f10 \fs16 SOLVED}{\i0 \f10 \fs16 PROBLEMS }\par
}
cf0 6.1 \par
}
Refer to Fig.{\i 6-la.} A{\b \fs18 2.2-V} input to the{\fs19 TTL} inverter is
a logical
}
\cf0 (0,I){\i0 \fs18 input. }\par
}
\cf0 A 2.2-V input{\fs17 to} a{\b0 TTL} inverter is a logical{\fs16 1}
input, because{\fs15 it} is{\b0 \fs16 in} the HIGH range. \par
}
\par
}
'L AND CMOS ICs: CHARACTERISTICS AND INTERFACING \par
}
AP. 6 \par
}
f0 6.2 \par
}
efer to Fig.{\b \fs18 6-la.}{\b \fs19 A}{\fs19 2.2-V} output from the TTL inv
erter is a logical
}
tput. \par
}
\fs17 \cf0 A{\b0 \fs17 2.2-V}{\b0 \fs17 output}{\b0 \fs17 from}{\b0 \fs17
a}{\b0 \fs17 TTL}{\b0 \fs17 inverter}{\b0 \fs17 is}{\b0 \fs17 defined
}{\b0 \fs17 as}{\b0 \fs17 a}{\b0 \fs17 forbidden}{\b0 \fs17 output}{\b0
\fs17 caused}{\b0 \fs17 by}{\b0 \fs17 a}{\b0 \fs17 faulty}{\b0 \fs17 I
C}{\b0 \fs17 or}{\b0 \fs17 too }
\b0 \fs17 heavy}{\b0 \fs17 a}{\b0 \fs17 load}{\b0 \fs17 at}{\b0 \fs17 the
}{\b0 \fs17 output. }\par
}
f0 6.3 \par
}
hat are{\b\i \fs17 typical}{\fs19 TTL} LOW and HIGH{\b\i \fs17 output} vo
ltages?
\fs17 Solution: }
64 {\fs17 The}{\fs17 typical}{\fs17 LOW}{\fs17 output}{\fs17 voltage}{\f
s17 from}{\fs17 a}{\fs17 TTL}{\fs17 IC}{\fs17 is}{\fs17 0.1}{\fs17 V
.}{\fs17 The}{\fs17 typical}{\fs17 HIGH}{\fs17 output}{\fs17 voltage}{\
fs17 from}{\fs17 a }
\f30 \fs19 TTL}{\fs17 IC}{\b \fs17 is}{\fs17 about}{\fs17 3.5}{\fs17 V,}{\
fs17 but}{\fs17 the}{\fs17 voltage}{\fs17 varies}{\fs17 widely}{\fs17 wi
th}{\fs17 loading. }\par
}
\cf0 A{\b0 \fs19 0.7-V}{\b0 input}{\b0 would}{\b0 be}{\b0 considered}{\b0
a }
}
forbidden, HIGH,{\b LOW)} input{\fs18 to} a{\fs19 TTL} device. \par
}
f0 6.4 \par
}
\cf0 See Fig. 6-la.{\b \f10 \fs17 A}{\b \fs17 0.7-V} input would be conside
red a LOW input to a{\fs17 TTL} IC.
{\fs18 The}{\fs18 time}{\fs18 it}{\fs18 takes}{\fs18 for}{\fs18 the}{\fs18
output}{\fs19 of}{\fs18 a}{\fs18 digital}{\fs18 logic}{\fs18 gate}{\fs18
to}{\fs18 change}{\fs18 states}{\fs18 after}{\fs18 the}{\fs18 input}{\fs18
changes}{\fs18 is }\par
}
{\phpg\posx1467\pvpg\posy5736\absw805\absh514 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ca
lled

}
par
}
f0 6.5 \par
}
\cf0 Propagation delay is the time{\fs17 it} takes for the output to
change after the input has changed logic
\par}{\phpg\posx1465\pvpg\posy6369\absw8262\absh392 \sl-220 \f20 \fs17 \cf0 stat
es. See Fig. 6-2. \par
}
f0 6.6 \par
}
ropagation delays in modern digital ICs are measured in
}
milli, micro, nano) seconds. \par
}
\cf0 Propagation delays in modern digital ICs are measured in nanoseconds.{
\b \fs17 A} nanosecond (ns){\fs17 is}{\fs17 10-9}{\b \fs17 s. }
{\fs18 The}{\fs18 number}{\fs18 of}{\fs18 parallel}{\fs18 loads}{\fs18 that
}{\fs18 can}{\fs18 be}{\fs18 driven}{\fs18 by}{\fs18 a}{\fs18 single}{\fs1
8 digital}{\fs19 IC}{\fs18 output}{\fs18 is}{\fs18 a}{\fs18 characteristic
}\par
}
{\phpg\posx1467\pvpg\posy8674\absw799\absh513 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ca
lled
}
\par
}
f0 6.7 \par
}
an-out{\b is} the number of parallel loads that can be driven by a sing
le digital IC output. \par
}
f0 6.8 \par
}
e
}
\fs19 \cf0 (CMOS,{\b0 TTL)}{\b0 \fs18 digital} IC{\b0 \fs18 family}{\b0 \fs1
8 is}{\b0 \fs18 noted}{\b0 \fs18 for}{\b0 \fs18 its}{\b0 \fs18 very}{\b0 \
fs18 low}{\b0 \fs18 power}{\b0 \fs18 consumption. }

f0 {\b0 \fs17 The}{\b0 \fs17 CMOS}{\b0 \fs17 digital}{\b0 \fs17 IC}{\b0 \fs17
family}{\b0 \fs17 is}{\b0 \fs17 noted}{\b0 \fs17 for}{\b0 \fs17 its}{\b
0 \fs17 very}{\b0 \fs17 low}{\b0 \fs17 power}{\b0 \fs17 consumption. }\par
}
17 \cf0 6.9 \par
}
Refer to Fig.{\b\i \fs18 6-lb.}{\b\i \f10 \fs17 An}{\fs19 8.5-V} input to the
{\b \fs19 CMOS} inverter is a logical
}
0,l){\fs18 input. }\par
}
17 \cf0 8.5-V input to a CMOS inverter is a logical{\fs17 1} input be
cause it is in the HIGH range shown in
\par}{\phpg\posx1461\pvpg\posy11779\absw8250\absh1712 \sl-213 \f20 \fs17 \cf0 Fi
g. 6-lb.
0 {\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\b \fs19 6-lb.}{\fs18 What}{\fs18 are
}{\fs18 the}{\fs18 typical}{\b \fs19 CMOS}{\fs18 LOW}{\fs18 and}{\fs18 HIG
H}{\fs18 output}{\fs18 voltages? }
b \fs17 Solution: }
i360 The typical output CMOS voltages are very near the rails of the power s
upply.{\b \fs17 A} typical LOW might
\par}{\phpg\posx1461\pvpg\posy11779\absw8250\absh1712 \sl-232 \f20 \fs17 \cf0 be
0 V (GND), and a HIGH might be{\f10 \fs25 +} 10 V. \par
}
cf0 6.10 \par
}
}
}
\par
}
cf0 6.11{\b0 \fs19
The }
}
\fs19 \cf0 (CMOS,{\b0 TTL)}{\b0 logic}{\b0 family}{\b0 is}{\b0 noted}{\b0
for}{\b0 its}{\b0 very}{\b0 good}{\b0 noise}{\b0 immunity. }
f0 {\fs17 The}{\fs17 CMOS}{\fs17 family}{\fs17 is}{\fs17 noted}{\b0 \fs17
for}{\fs17 its}{\fs17 good}{\fs17 noise}{\fs17 immunity. }\par

}
cf0 6.12{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 6-4u.}{
\b0 \fs19 The}{\b0 \fs19 NAND}{\b0 \fs19 gate}{\b0 \fs19 is}{\b0 \fs19 said
}{\b0 \fs19 to}{\b0 \fs19 be }
i593 {\b0 \fs19 circuit}{\b0 \fs19 shown. }\par
}
sinking, sourcing) current in the logic \par
}
s13 \cf0 (a){\i0 \f20 \fs15 NAND}{\i0 \f20 \fs15 gate}{\i0 \f20 \fs15 driving
}{\i0 \f20 \fs15 an}{\i0 \f20 \fs15 inverter}{\i0 \f20 \fs15 input }\par
}
6){\b Inverter}{\b driving}{\b an}{\b \fs15 OR}{\b \fs15 input }
\fi813 {\b \fs16 Fig.}{\b \f10 \fs15 6-4 }\par
}
\cf0 Solution:
fi359 {\fs17 The}{\fs17 output}{\b0 \fs17 of}{\fs17 the}{\fs17 NAND}{\fs1
7 gate}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\b0\i \f10 \fs15 6-4a}{\fs17
is}{\fs17 LOW.}{\fs17 The}{\fs17 NAND}{\fs17 gate}{\fs17 is}{\fs17
therefore}{\fs17 said}{\fs16 to}{\fs17 be }
\fs17 sinking}{\fs17 the}{\fs17 drive}{\fs17 current. }\par
}
f0 6.13 \par
}
efer to Fig. 6-4b. The inverter is said to be
uit shown.
}
sinking, sourcing) current in the logic \par
}
\fs17 \cf0 The output of the inverter shown in Fig.{\i \fs16 6-4b} is HIGH. T
he inverter is therefore said to be sourcing
\par}{\phpg\posx1455\pvpg\posy8749\absw8297\absh393 \sl-217 \b \f20 \fs17 \cf0 t
he drive current. \par
}
\cf0 6-3{\fs19
lTL}{\fs19 INTEGRATED}{\fs19 CIRCUITS }
fi358 {\b0 \fs19 The}{\b0 \fs19 famous}{\b0 \fs19 7400}{\b0 \fs19 series}{\b0
\fs19 of}{\b0 \fs19 TTL}{\b0 \fs19 logic}{\b0 \fs19 circuits}{\b0 \fs19 w
as}{\b0 \fs19 introduced}{\b0 \fs19 by}{\b0 \fs19 Texas}{\b0 \fs19 Instrume
nts}{\b0 \fs19 in}{\b0 \fs19 1964.}{\b0 \fs19 The }
\b0 \fs19 TTL}{\b0 \fs19 family}{\b0 \fs19 of}{\b0 \fs19 ICs}{\b0 \fs19 is
}{\b0 \fs19 still}{\b0 \fs19 one}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19
more}{\b0 \fs19 widely}{\b0 \fs19 used}{\b0 \fs19 for}{\b0 \fs19 constru

cting}{\b0 \fs19 logic}{\b0 \fs19 circuits.}{\fs19 T-TL}{\fs19 ICs}{\b0 \f
s19 are }
\b0 \fs19 manufactured}{\b0 \fs19 in}{\b0 \fs19 a}{\b0 \fs19 wide}{\b0 \fs19
variety}{\b0 \fs19 of}{\fs18 SSI}{\b0 \fs19 and}{\fs19 MSI}{\b0 \fs19 int
egrated}{\b0 \fs19 circuits. }
fi366 {\b0 \fs19 Over}{\b0 \fs19 the}{\b0 \fs19 years,}{\b0 \fs19 improvement
s}{\b0 \fs19 in}{\b0 \fs19 TTL}{\b0 \fs19 logic}{\b0 \fs19 circuits}{\b0 \fs
19 have}{\b0 \fs19 been}{\b0 \fs19 made,}{\b0 \fs19 which}{\b0 \fs19 has}{\
b0 \fs19 led}{\b0 \fs19 to}{\i \fs18 subfumilies }
\b0 \fs19 of}{\b0 \fs19 transistor-transistor}{\b0 \fs19
logic}{\fs19 ICs
.}{\b0 \fs19 The}{\b0 \fs19 following}{\fs18 six}{\b0 \fs19 TTL}{\b0 \fs
19 subfamilies}{\b0 \fs19 are}{\b0 \fs19 currently}{\b0 \fs19 available}
{\b0 \fs19 from }
\b0 \fs19 National}{\b0 \fs19 Semiconductor}{\b0 \fs19 Corporation: }\par
}
1.{\fs19
Standard}{\fs19 TTL}{\fs19 logic }\par
}
Typical IC marking:
7404 (function: hex inverter) \par
}
\cf0 2.{\b0 \fs19
Low-power}{\b0 \fs19 TTL}{\b0 \fs19 logic }
\fi2238 {\b0 \fs19 Typical}{\fs19 IC}{\b0 \fs19 marking:}{\b0 \fs19
74L04}
{\b0 \fs19 (hex}{\b0 \fs19 inverter) }
{\b0 \fs19 3.}{\b0 \fs19
Low-power}{\b0 \fs19 Schottky}{\b0 \fs19 TTL}{\b0
\fs19 logic }
\fi2238 {\b0 \fs19 Typical}{\fs19 IC}{\b0 \fs19 marking:}{\b0 \fs19
74LS04
}{\b0 \fs19 (hex}{\b0 \fs19 inverter) }\par
}
4.
Schottky 'ITL logic \par
}
Typical{\b IC} marking:
74S04 (hex inverter) \par
}
\par
}
L{\fs16 AND}{\fs16 CMOS}{\fs16 ICs:}{\fs16 CHARACTERISTICS}{\fs16 AND}{\f
s16 INTERFACING }\par
}
AP.{\b \fs16 6 }\par
}
\fs19 \cf0 5.{\i0 \fs18
Advanced}{\i0 \fs18 low-power}{\i0 \fs18 Schottk
y}{\i0 \fs18 TTL}{\i0 \fs18 logic }
fi2609 {\i0 \fs18 Typical}{\i0 \fs18 IC}{\i0 \fs18 marking:}{\i0 \fs18

74A
LS04}{\i0 \fs18 (hex}{\i0 \fs18 inverter) }
fi364 {\fs18 6.}{\i0 \fs18
Advanced}{\i0 \fs18 Schoitky}{\i0 \fs18 TTL}{\i
0 \fs18 logic }
fi2610 {\i0 \fs18 Typical}{\i0 \fs18 IC}{\i0 \fs18 marking:}{\i0 \fs18
74A
S04}{\i0 \fs18 (hex}{\i0 \fs18 inverter) }
f0 \fi366 {\i0 \fs18 The}{\i0 \fs18 code}{\i0 \fs18 letters}{\i0 \fs18 L,}
{\b\i0 LS,}{\b\i0 \fs18 S,}{\i0 \fs18 ALS,}{\i0 \fs18 and}{\b\i0 \f10 \fs
17 AS}{\i0 \fs18 are}{\i0 \fs18 used}{\i0 \fs18 in}{\i0 \fs18 the}{\fs
18 middle}{\f10 \fs16 of}{\fs18 the}{\fs18 7400}{\fs18 series}{\fs18 n
umber}{\i0 \fs18 to }
\i0 \fs18 designate}{\i0 \fs18 the}{\i0 \fs18 subfamily.}{\i0 \fs18 This}{\i
0 \fs18 can}{\i0 \fs18 be}{\i0 \fs18 observed}{\i0 \fs18 above}{\i0 \fs18
where}{\i0 \fs18 typical}{\i0 \fs18 IC}{\i0 \fs18 markings}{\i0 \fs18 for}
{\i0 \fs18 the}{\i0 \fs18 various}{\i0 \fs18 TTL }
\i0 \fs18 subfamilies}{\i0 \fs18 are}{\i0 \fs18 listed.}{\i0 \fs18 Notice}{\i
0 \fs18 that}{\i0 \fs18 no}{\i0 \fs18 special}{\i0 \fs18 code}{\i0 \fs18 le
tter}{\i0 \fs18 is}{\i0 \fs18 used}{\i0 \fs18 in}{\i0 \fs18 the}{\i0 \fs18
middle}{\i0 \fs18 of}{\i0 \fs18 a}{\i0 \fs18 standard}{\i0 \fs18 TTL}{\i0 \f
s18 logic }
\i0 \fs18 1C.}{\i0 \fs18 The}{\i0 \fs18 subfamilies}{\i0 \fs18 with}{\i0 \
fs18 the}{\i0 \fs18 code}{\i0 \fs18 letter}{\b\i0 \fs18 S}{\i0 \fs18 c
ontain}{\i0 \fs18 a}{\i0 \fs18 Schottky}{\i0 \fs18 barrier}{\i0 \fs18 di
ode}{\i0 \fs18 to}{\i0 \fs18 increase}{\i0 \fs18 switch- }
\i0 \fs18 ing}{\i0 \fs18 speed.}{\i0 \fs18 Several}{\i0 \fs18 companies}{\i
0 \fs18 also}{\i0 \fs18 use}{\i0 \fs18 the}{\i0 \fs18 code}{\i0 \fs18
letter}{\i0 \fs18 F}{\i0 \fs18 (as}{\i0 \fs18 in}{\i0 \fs18 74F04)}{\i0 \f
s18 for}{\i0 \fs18 a}{\fs18 fast}{\i0 \fs18 advanced}{\i0 \fs18 Schottk
y }
\i0 \fs18 TTL}{\i0 \fs18 IC. }
fi371 {\i0 \fs18 It}{\i0 \fs18 should}{\i0 \fs18 be}{\i0 \fs18 noted}{\i0 \fs
18 that}{\i0 \fs18 the}{\i0 \fs18 voltage}{\i0 \fs18 characteristics}{\i0 \
fs18 of}{\i0 \fs18 all}{\i0 \fs18 the}{\i0 \fs18 TTL}{\i0 \fs18 subfamilie
s}{\i0 \fs18 are}{\i0 \fs18 the}{\i0 \fs18 same.}{\i0 \fs18 Their }
\i0 \fs18 power}{\i0 \fs18 and}{\i0 \fs18 speed}{\i0 \fs18 characteristics}{
\i0 \fs18 are}{\i0 \fs18 different,}{\i0 \fs18 and}{\i0 \fs18 under}{\i0 \
fs18 some}{\i0 \fs18 conditions,}{\i0 \fs18 substituting}{\i0 \fs18 one}{\i
0 \fs18 subfamily }
\i0 \fs18 for}{\i0 \fs18 another}{\i0 \fs18 might}{\i0 \fs18 cause}{\i0 \f
s18 trouble.}{\i0 \fs18 For}{\i0 \fs18 instance,}{\i0 \fs18 a}{\i0 \fs18
technician}{\i0 \fs18 would}{\fs18 not}{\i0 \fs18 want}{\i0 \fs18 to}
{\i0 \fs18 replace}{\i0 \fs18 a}{\i0 \fs18 very}{\i0 \fs18 fast }
\i0 \fs18 74AS04}{\i0 \fs18 inverter}{\i0 \fs18 IC}{\i0 \fs18 with}{\i0 \fs1
8 a}{\i0 \fs18 much}{\i0 \fs18 slower}{\i0 \fs18 74L04}{\i0 IC}{\i0 \fs18
from}{\i0 \fs18 the}{\i0 \fs18 low-power}{\i0 \fs18 TTL}{\i0 \fs18 logic}{\i
0 \fs18 subfamily. }
fi366 {\i0 \fs18 The}{\i0 \fs18 internal}{\i0 \fs18 details}{\i0 \fs18 of}{\i
0 \fs18 a}{\i0 \fs18 standard}{\i0 \fs18 TTL}{\i0 \fs18 NAND}{\i0 \fs18 ga

te}{\i0 \fs18 are}{\i0 \fs18 shown}{\i0 \fs18 in}{\i0 \fs18 Fig.}{\i0 \fs18
6-5.}{\i0 \fs18 National}{\i0 \fs18 Semiconduc- }
\i0 \fs18 tor}{\i0 \fs18 Corporation's}{\i0 \fs18 description}{\i0 \fs18 fol
lows.}{\i0 \fs18 TTL}{\i0 \fs18 logic}{\i0 \fs18 was}{\i0 \fs18 the}{\i0 \fs
18 first}{\i0 \fs18 saturating}{\i0 \fs18 logic}{\i0 \fs18 integrated}{\i0 \
fs18 circuit}{\i0 \fs18 family }
\i0 \fs18 introduced;}{\i0 \fs18 it}{\i0 \fs18 set}{\i0 \fs18 the}{\i0 \fs
18 standard}{\i0 \fs18 for}{\i0 \fs18 all}{\i0 \fs18 future}{\i0 \fs18
families.}{\i0 \fs17
It}{\i0 \fs18 offers}{\i0 \fs18 a}{\i0 \fs18 comb
ination}{\i0 \fs18 of}{\i0 \fs18 speed,}{\i0 \fs18 power }
\i0 \fs18 consumption,}{\i0 \fs18 output}{\i0 \fs18 source,}{\i0 \fs18 and
}{\i0 \fs18 sink}{\i0 \fs18 capabilities}{\i0 \fs18 suitable}{\i0 \fs18
for}{\i0 \fs18 most}{\i0 \fs18 applications,}{\i0 \fs18 and}{\i0 \fs18 i
t}{\i0 \fs18 offers}{\i0 \fs18 the }
\i0 \fs18 greatest}{\i0 \fs18 variety}{\i0 \fs18 of}{\i0 \fs18 logic}{\i0
\fs18 functions.}{\i0 \fs18 The}{\i0 \fs18 basic}{\i0 \fs18 gate}{\i0 \f
s18 (see}{\i0 \fs18 Fig.}{\fs18 6-5)}{\i0 \fs18 features}{\i0 \fs18 a}{
\i0 \fs18 multiple-emitter}{\i0 \fs18 input }
\i0 \fs18 configuration}{\i0 \fs18 for}{\i0 \fs18 fast}{\i0 \fs18 switchin
g}{\i0 \fs18 speeds}{\i0 \fs18 and}{\i0 \fs18 active}{\i0 \fs18 pull-up}
{\i0 \fs18 output}{\i0 \fs18 to}{\i0 \fs18 provide}{\i0 \fs18 a}{\i0 \fs
18 low}{\i0 \fs18 driving}{\i0 \fs18 source }
\i0 \fs18 impedance}{\i0 \fs18 which}{\i0 \fs18 also}{\i0 \fs18 improves}{\i0
\fs18 noise}{\i0 \fs18 margin}{\i0 \fs18 and}{\i0 \fs18 device}{\i0 \fs18
speed.}{\i0 \fs18 Typical}{\i0 \fs18 device}{\i0 \fs18 power}{\i0 \fs18 diss
ipation}{\i0 \fs18 is}{\i0 \fs18 10 }
\i0 \fs18 mW}{\i0 \fs18 per}{\i0 \fs18 gate,}{\i0 \fs18 and}{\i0 \fs18 the}{
\i0 \fs18 typical}{\i0 \fs18 propagation}{\i0 \fs18 delay}{\i0 \fs18 is}{\i
0 \fs18 10}{\i0 \fs18 ns}{\i0 \fs18 when}{\i0 \fs18 driving}{\i0 \fs18 a}{
\i0 \fs18 15}{\i0 \fs18 pF}{\i0 \fs18 per}{\i0 \fs18 400}{\i0\dn006 \f10 \f
s11 -}{\i0 \fs18
load. }\par
}
put{\b A }\par
}
cf0 vcc
i121 {\i0 \fs16 I }\par
}
\cf0 1 \par
}
put{\fs16 B }\par
}
{\phpg\posx6547\pvpg\posy9396\absw319\absh168 \f20 \fs14 \cf0 \f20 \fs14 \cf0 tp
ut \par
}
\cf0 Fig.{\i \f10 \fs15 6-5}{\b0
Schematic}{\b0 diagram}{\b0 \fs17 of}{\
b0 a}{\b0 standard}{\b0 \fs16 TTL}{\b0 \fs16 NAND}{\b0 \fs16 gate}{\b0\
i \fs16 (Courtesy}{\b0\i \f10 \fs14 of}{\b0\i \fs16 National}{\b0\i \fs16

Semiconductor}{\b0\i \fs16 Corporation) }\par
}
8 \cf0 Digital logic designers must consider two important factors when selectin
g a logic family. They are
\fs18 speed} and{\b\i \fs17 power}{\i \fs18 consumption.}{\fs18 In} Fig.{\
i \fs18 6-6a} the TTL subfamilies are ranked from best to worst (fastest
\par}{\phpg\posx851\pvpg\posy11787\absw9282\absh1481 \sl-234 \f20 \fs18 \cf0 to
slowest) by speed, or low propagation delay. Note that the advanced S
chottky subfamily is the
\par}{\phpg\posx851\pvpg\posy11787\absw9282\absh1481 \sl-230 \f20 \fs18 \cf0 fas
test.{\fs18 In} Fig.{\i \fs18 6-6b} the TTL subfamilies are ranked by power co
nsumption. Note that the low-power
s18 TTL} is best in power consumption. Both the low-power Schottky and
the advanced low-power
\par}{\phpg\posx851\pvpg\posy11787\absw9282\absh1481 \sl-230 \f20 \fs18 \cf0 Sch
ottky are excellent compromise subfamilies with both low power consumpt
ion and high speed.
\par}{\phpg\posx851\pvpg\posy11787\absw9282\absh1481 \sl-239 \f20 \fs18 \cf0 Cur
rently, both the low-power Schottky and the advanced low-power Schottky are very
popular. \par
}
}
L AND{\b \fs16 CMOS}{\b \fs16 ICs:}{\b \fs16 CHARACTERISTICS}{\fs17 AND}{\b
}
\par
}
\par
}
fs16 \cf0 Speed
0 Fastest \par
}
\par
}
1 \par
}
cf0 S1{\b0\i \f20 \fs17 o}{\f20 \fs16 wes}{\f20 \fs15 t }\par
}
0 \fs16 \cf0 TTL subfamily
cf0 Advanced Schottky
Schottky

Advanced low-power Schottky
Low-power Schottky
Standard{\fs17 TTL }
Low power \par
}
\par
}
\f20 \fs14 \cf0 (a){\i0 \fs15 TTL}{\i0 \fs15 subfamilies}{\i0 \fs15 ranked}{\
i0 \fs14 by}{\i0 \fs15 speed }
\cf0 {\i0 \fs16 Power }\par
}
\cf0 consumption
f0 \fi336 Low \par
}
I \par
}
cf0 High \par
}
\f20 \fs15 \cf0 (h){\i0 \fs15 TTL}{\i0 \fs14 subfamilies}{\i0 ranked}{\i0 \f
s14 by}{\i0 \fs14 power}{\i0 \fs14 consumption }
\cf0 \fi4072 {\i0 \fs16 Fig.}{\i0 \fs16 6-6 }
\cf0 \fi366 {\b0\i0 \fs18 Devices}{\b0\i0 \fs18 in}{\b0\i0 \fs18 the}{\b0 \f
s18 7400}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 series}{\b0\i0 \fs18 are}{\b0\i0
\fs18 referred}{\b0\i0 \fs18 to}{\b0\i0 \fs18 as}{\b0\i0 \fs18 commerci
al}{\b0\i0 \fs18 grade}{\b0\i0 \fs18 ICs;}{\b0\i0 \fs18 they}{\b0\i0 \fs18
operate}{\b0\i0 \fs18 over}{\b0\i0 \fs18 a }
{\b0\i0 \fs18 temperature}{\b0\i0 \fs18 range}{\b0\i0 \fs18 of}{\b0\i0 \fs19
0}{\b0\i0 \fs18 to}{\b0 \fs18 70C.}{\b0\i0 \fs18 The}{\b0 \fs18 5400}{\
b0\i0 \fs18 TTL}{\b0\i0 \fs18 series}{\b0\i0 \fs18 have}{\b0\i0 \fs18 th
e}{\b0\i0 \fs18 same}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 functions,}{\b0\i0 \
fs18 but}{\b0\i0 \fs18 they}{\b0\i0 \fs18 will }
{\b0\i0 \fs18 operate}{\b0\i0 \fs18 over}{\b0\i0 \fs18 a}{\b0\i0 \fs18 great
er}{\b0\i0 \fs18 temperature}{\b0\i0 \fs18 range}{\b0\i0 \f10 \fs16 (}{\b0\i
0 \f10 \fs15 -}{\b0\i0 \fs19 55}{\b0\i0 \fs18 to}{\b0\i0 \fs18 125C).}{\b0\i0
\fs18 The}{\b0 \fs18 5400}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 series}{\b0\i0 \f
s18 is}{\b0\i0 \fs18 sometimes}{\b0\i0 \fs18 called }
{\b0\i0 \fs18 the}{\b0\i0 \fs18 military}{\b0\i0 \fs18 series}{\b0\i0 \fs18
of}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 circuits.}{\b0\i0 \fs1
8 ICs}{\b0\i0 \fs18 in}{\b0\i0 \fs18 the}{\b0 \fs18 5400}{\b0\i0 \fs18 ser
ies}{\b0\i0 \fs18 are}{\b0\i0 \fs18 more}{\b0\i0 \fs18 expensive. }
\fi363 {\b0\i0 \fs18 The}{\b0 \fs18 NAND}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 ou
tput}{\b0\i0 \fs18 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0\i0 \fs18 6
-5}{\b0\i0 \fs18 is}{\b0\i0 \fs18 connected}{\b0\i0 \fs18 between}{\b0\i0 \fs

18 two}{\b0\i0 \fs18 transistors}{\b0 \fs18 (Q3}{\b0\i0 \fs18 and}{\b0 \fs18
Q4).}{\b0\i0 \fs18 This }
{\b0\i0 \fs18 is}{\b0\i0 \fs18 called}{\b0\i0 \fs18 a}{\b0 \fs18 totem}{\b
0 \fs18 pole}{\b0\i0 \fs18 output.}{\b0\i0 \fs18 For}{\b0\i0 \fs18 the}{\b
0\i0 \fs18 output}{\b0\i0 \fs18 to}{\b0\i0 \fs18 sink}{\b0\i0 \fs18 curren
t}{\b0\i0 \fs19 (LOW}{\b0\i0 \fs18 output),}{\b0\i0 \fs18 transistor}{\b0 \
fs18 Q4}{\b0\i0 \fs18 must}{\b0\i0 \fs18 be }
{\b0\i0 \fs18 "turned}{\b0\i0 \fs18 on"}{\b0\i0 \fs18 or}{\b0\i0 \fs18 satur
ated.}{\b0\i0 \fs18 For}{\b0\i0 \fs18 a}{\b0\i0 \fs19 HIGH}{\b0\i0 \fs18 out
put}{\b0\i0 \fs18 as}{\b0\i0 \fs18 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.
}{\b0 \fs18 6-5,}{\b0\i0 \fs18 transistor}{\b0 \fs18 Q3}{\b0\i0 \fs18 must}
{\b0\i0 \fs18 be}{\b0\i0 \fs18 saturated, }
{\b0\i0 \fs18 which}{\b0\i0 \fs18 will}{\b0\i0 \fs18 allow}{\b0\i0 \fs18 the
}{\b0 \fs18 NAND}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 to}{\b0\i0 \fs18 become}{\
b0\i0 \fs18 a}{\b0\i0 \fs18 source}{\b0\i0 \fs18 of}{\b0\i0 \fs18 drive}{\b0
\i0 \fs18 current.}{\b0\i0 \fs18 Most}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 logic}
{\b0\i0 \fs18 gates}{\b0\i0 \fs18 have}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 totem}{\b0\i0 \fs18 pole}{\b0\i0 \fs18 type}{\b0\i0 \fs18 of}{
\b0\i0 \fs18 output. }
\fi372 {\b0\i0 \fs18 Some}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 circuits}{\b0\i0 \f
s18 have}{\b0\i0 \fs18 an}{\b0 \fs18 open-collector}{\b0\i0 \fs18 output}{
\b0\i0 \fs18 in}{\b0\i0 \fs18 which}{\b0\i0 \fs18 transistor}{\b0 \fs18 Q3}
{\b0\i0 \fs18 (see}{\b0\i0 \fs18 Fig.}{\b0 \fs18 6-5)}{\b0\i0 \fs18 is}{\b0\
i0 \fs18 missing. }
{\i0 \fs19 A}{\b0 \fs18 pull-up}{\b0 \fs18 resistor}{\b0\i0 \fs18 is}{\b0\i0
\fs18 used}{\b0\i0 \fs18 with}{\b0\i0 \fs18 open-collector}{\b0\i0 \fs18 ou
tputs.}{\b0\i0 \fs18 Pull-up}{\b0\i0 \fs18 resistors}{\b0\i0 \fs18 are}{\b0\i
0 \fs18 connected}{\b0\i0 \fs18 from}{\b0\i0 \fs18 the}{\b0\i0 \fs18 output
}
{\b0\i0 \fs18 to}{\b0\i0 \fs18 the}{\i0 \fs18 +5-V}{\b0\i0 \fs18 rail}{\b0\
i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 power}{\b0\i0 \fs18 supply}{\b
0\i0 \fs18 outside}{\b0\i0 \fs18 the}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 gate.
}
\fi360 {\i0 \fs19 A}{\b0\i0 \fs18 third}{\b0\i0 \fs18 type}{\b0\i0 \fs18 of
}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 output}{\b0\i0 \fs18 used}{\b0\i0 \fs18 o
n}{\b0\i0 \fs18 some}{\b0\i0 \fs18 devices}{\b0\i0 \fs18 is}{\b0\i0 \fs18
the}{\b0 \fs18 three-state}{\b0 \fs18 output.}{\b0\i0 \fs18 It}{\b0\i0 \fs18
has}{\b0\i0 \fs18 three}{\b0\i0 \fs18 possible }
{\b0\i0 \fs18 outputs}{\b0\i0 \fs19 (HIGH,}{\b0\i0 \fs19 LOW,}{\b0\i0 \fs18
or}{\b0\i0 \fs18 high}{\b0\i0 \fs18 impedance).}{\b0\i0 \fs18 The}{\b0\i0 \fs
18 three-state}{\b0\i0 \fs18 output}{\b0\i0 \fs18 will}{\b0\i0 \fs18 be}{\b0
\i0 \fs18 explored}{\b0\i0 \fs18 in}{\b0\i0 \fs18 connection}{\b0\i0 \fs18 w
ith }
{\b0\i0 \fs18 the}{\b0\i0 \fs18 three-state}{\b0\i0 \fs18 buffer. }
\fi364 {\b0 \fs18 As}{\b0\i0 \fs18 a}{\b0\i0 \fs18 general}{\b0\i0 \fs18 rul
e,}{\b0 \fs18 outputs}{\b0\i0 \fs18 of}{\b0 \fs19 TTL}{\b0 \fs18 devices}{
\b0 \fs18 cannot}{\b0 \fs18 be}{\b0 \fs18 connected}{\b0 \fs18 together.}{\
b0\i0 \fs18 That}{\b0\i0 \fs18 is}{\b0\i0 \fs18 true}{\b0\i0 \fs18 of}{\b0\i
0 \fs18 gates}{\b0\i0 \fs18 with }

{\b0\i0 \fs18 totem}{\b0\i0 \fs18 pole}{\b0\i0 \fs18 outputs.}{\b0\i0 \fs19
TTL}{\b0\i0 \fs18 outputs}{\b0\i0 \fs18 can}{\b0\i0 \fs18 be}{\b0\i0 \f
s18 connected}{\b0\i0 \fs18 together}{\b0\i0 \fs18 with}{\b0\i0 \fs18 no
}{\b0\i0 \fs18 damage}{\b0\i0 \fs18 if}{\b0\i0 \fs18 they}{\b0\i0 \fs18
are}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 open-collector}{\b0\i0 \fs18 or}{\b0\i0 \fs18 three-state}{\b0\
i0 \fs18 type. }
\fi366 {\b0\i0 \fs18 Markings}{\b0\i0 \fs18 on}{\b0\i0 \fs18 TTL}{\b0\i0 \fs1
9 ICs}{\b0\i0 \fs18 vary}{\b0\i0 \fs18 with}{\b0\i0 \fs18 the}{\b0\i0 \fs18
manufacturer.}{\b0\i0 \fs18 Figure}{\b0 \fs18 6-7a}{\b0\i0 \fs18 shows}{\b0\
i0 \fs18 a}{\b0\i0 \fs18 typical}{\b0\i0 \fs18 marking}{\b0\i0 \fs18 on}{\b0
\i0 \fs18 a}{\b0\i0 \fs18 TTL }
{\b0\i0 \fs18 digital}{\b0\i0 \fs18 IC.}{\b0\i0 \fs18 Pin}{\b0\i0 \fs18 1
}{\b0\i0 \fs18 is}{\b0\i0 \fs18 identified}{\b0\i0 \fs18 with}{\b0\i0 \fs18
a}{\b0\i0 \fs18 dot,}{\b0\i0 \fs18 a}{\b0\i0 \fs18 notch,}{\b0\i0 \fs18
or}{\b0\i0 \fs18 a}{\b0\i0 \fs18 colored}{\b0\i0 \fs18 band}{\b0\i0 \fs1
8 across}{\b0\i0 \fs18 the}{\b0\i0 \fs18 end}{\b0\i0 \fs18 of}{\b0\i0 \f
s18 the}{\b0\i0 \fs18 IC.}{\b0\i0 \fs18 The }
{\b0\i0 \fs18 manufacturer's}{\b0\i0 \fs18 logo}{\b0\i0 \fs18 is}{\b0\i0 \f
s18 shown}{\b0\i0 \fs18 at}{\b0\i0 \fs18 the}{\b0\i0 \fs18 upper}{\b0\i0
\fs18 left}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0 \fs18 6-7a.}{\b0\i0
\fs18 In}{\b0\i0 \fs18 this}{\b0\i0 \fs18 example}{\b0\i0 \fs18 the}{\b
0\i0 \fs18 manufacturer}{\b0\i0 \fs18 is }
{\b0\i0 \fs18 National}{\b0\i0 \fs18 Semiconductor}{\b0\i0 \fs18 Corporatio
n.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 part}{\b0\i0 \fs18 number}{\b0\i0 \fs18
is}{\b0 \fs18 DM7408N.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 core}{\b0\i0 \fs
18 number}{\b0\i0 \fs18 (generic }
{\b0\i0 \fs18 number)}{\b0\i0 \fs18 is}{\b0 \fs18 7408,}{\b0\i0 \fs18 which}
{\b0\i0 \fs18 means}{\b0\i0 \fs18 this}{\b0\i0 \fs18 is}{\b0\i0 \fs18 a}{\b0
\i0 \fs18 TTL}{\b0\i0 \fs18 quad}{\b0\i0 \fs18 2-input}{\b0 \fs18 AND}{\b0\i
0 \fs18 gate}{\b0\i0 \fs18 IC. }
\fi360 {\b0\i0 \fs18 The}{\b0\i0 \fs18 part}{\b0\i0 \fs18 number}{\b0 \fs18
(DM7408N)}{\b0\i0 \fs18 is}{\b0\i0 \fs18 further}{\b0\i0 \fs18 decoded}{\b0\i0
\fs18 in}{\b0\i0 \fs18 Fig.}{\b0 \fs18 6-7b.}{\b0\i0 \fs18 The}{\b0\i0 \fs1
8 prefix}{\b0 \fs18 (DM}{\b0\i0 \fs18 in}{\b0\i0 \fs18 this}{\b0\i0 \fs18 e
xample)}{\b0\i0 \fs18 is}{\b0\i0 \fs18 a }
{\b0\i0 \fs18 manufacturer's}{\b0\i0 \fs18 code.}{\b0\i0 \fs18 The}{\b0\i0
\fs18 core}{\b0\i0 \fs18 number}{\b0\i0 \fs18 of}{\b0 \fs18 7408}{\b0\i0
\fs18 is}{\b0\i0 \fs18 divided.}{\b0\i0 \fs18 The}{\b0 \fs18 74}{\b0\i0
\fs18 portion}{\b0\i0 \fs18 means}{\b0\i0 \fs18 that}{\b0\i0 \fs18 this
}{\b0\i0 \fs18 is}{\b0\i0 \fs18 a }
{\b0\i0 \fs18 commercial}{\b0\i0 \fs18 grade}{\b0\i0 \fs19 TTL}{\i0 \fs18 IC
}{\b0\i0 \fs18 from}{\b0\i0 \fs18 the}{\b0\i0 \fs18 7400}{\b0\i0 \fs18 seri
es.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 08}{\b0\i0 \fs18 identifies}{\b0\i0 \fs18
the}{\b0\i0 \fs18 IC}{\b0\i0 \fs18 by}{\b0\i0 \fs18 function}{\b0\i0 \fs
18 (quad}{\b0\i0 \fs18 2-input }
{\b0\i0 \fs18 AND}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 in}{\b0\i0 \fs18 this}{\b
0\i0 \fs18 example).}{\b0\i0 \fs18 The}{\b0 \fs18 N}{\b0\i0 \fs18 suffix}{\
b0\i0 \fs18 is}{\b0\i0 \fs18 the}{\b0\i0 \fs18 manufacturer's}{\b0\i0 \fs18

code}{\b0\i0 \fs18 for}{\b0\i0 \fs18 a}{\b0\i0 \fs18 dual-in-line}{\b0\i0 \fs
18 package}{\b0\i0 \fs18 IC. }\par
}
\fs16 \cf0 TTL subfamily
f0 Low power \par
}
}
\cf0 Advanced low-power Schottky
\par}{\phpg\posx4805\pvpg\posy4779\absw2371\absh972 \sl-215 \b \f20 \fs16 \cf0 L
ow-power Schottky
\par}{\phpg\posx4805\pvpg\posy4779\absw2371\absh972 \sl-215 \b \f20 \fs16 \cf0 A
dvanced Schottky
\par}{\phpg\posx4805\pvpg\posy4779\absw2371\absh972 \sl-218 \b \f20 \fs16 \cf0 S
tandard TTL
chottky \par
}
\par
}
L{\fs17 AND}{\fs17 CMOS}{\fs17 ICs:}{\fs17 CHARACTERISTICS} AND{\fs17 INTER
FACING }\par
}
AP. 6 \par
}
\cf0 (a){\i0 \f20 \fs15 Markings}{\i0 \f20 \fs15 on}{\i0 \f20 \fs15 a}{\i0 \
f20 \fs15 typical}{\i0 \f20 \fs15 TTL}{\b\i0 \f20 \fs15 IC }\par
}
51 \cf0 7 \par
}
T{\f30 \fs101 T }\par
}
cf0 7408 \par
}
\cf0 (b){\i0 \fs15 Decoding}{\i0 \fs15 a}{\i0 \fs15 typical}{\b\i0 \fs15 TT
L}{\b\i0 \fs15 IC}{\i0 \fs15 part}{\i0 \fs15 number }\par
}
cf0 SN74LS04N \par
}
\cf0 Manufacturer's
76 code
15 7400} TTL series

\par}{\phpg\posx2385\pvpg\posy4215\absw1399\absh766 \sl-179 \f20 \fs15 \cf0 (com
mercial grade) \par
}
anufacturer's code for
\par}{\phpg\posx6095\pvpg\posy4229\absw2057\absh769 \sl-177 \f20 \fs15 \cf0 dual
-in-line package
\par}{\phpg\posx6095\pvpg\posy4229\absw2057\absh769 \sl-305 \f20 \fs15 \cf0 Func
tion of{\b \fs15 IC }
\fs15 (NAND} gate in this example) \par
}
\par
}
\par
}
\f20 \fs14 \cf0 (c){\b0\i0 \fs15 Markings}{\b0\i0 on}{\b0\i0 \fs15 another}{
\b0\i0 \fs15 TTL}{\i0 \fs15 IC }
\cf0 \fi4076 {\i0 \fs16 Fig.}{\i0 \fs17 6-7 }
\cf0 \fi364 {\b0\i0 \fs18 Consider}{\b0\i0 \fs18 the}{\b0\i0 \fs18 IC}{\b0\i
0 \fs18 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0\i0 \fs19 6-7c.}{\b
0\i0 \fs18 The}{\b0\i0 \fs18 logo}{\b0\i0 \fs18 represents}{\b0\i0 \fs18 T
exas}{\b0\i0 \fs18 Instruments,}{\b0\i0 \fs18 the}{\b0\i0 \fs18 manufactur
er. }
{\b0\i0 \fs18 The}{\i0 \fs19 SN}{\b0\i0 \fs18 portion}{\b0\i0 \fs18 of}{\b0\
i0 \fs18 the}{\b0\i0 \fs18 part}{\b0\i0 \fs18 number}{\b0\i0 \fs18 is}{\b0\i
0 \fs18 a}{\b0\i0 \fs18 prefix}{\b0\i0 \fs18 used}{\b0\i0 \fs18 by}{\b0\i0 \
fs18 Texas}{\b0\i0 \fs18 Instruments.}{\b0\i0 \fs18 The}{\b0\i0 \fs19 74}{\b
0\i0 \fs18 specifies}{\b0\i0 \fs18 this}{\b0\i0 \fs18 to}{\b0\i0 \fs18 be}{\
b0\i0 \fs18 a }
{\b0\i0 \fs18 commercial}{\b0\i0 \fs18 grade}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18
IC.}{\b0\i0 \fs18 The}{\i0 \fs19 LS}{\b0\i0 \fs18 means}{\b0\i0 \fs18 that}
{\b0\i0 \fs18 this}{\b0\i0 \fs18 is}{\b0\i0 \fs18 a}{\b0\i0 \fs18 low-powe
r}{\b0\i0 \fs18 Schottky}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 digital}{\b0\i0 \fs1
8 IC.}{\b0\i0 \fs18 The}{\b0\i0 \fs19 04 }
{\b0\i0 \fs18 specifies}{\b0\i0 \fs18 the}{\b0\i0 \fs18 function}{\b0\i0 \fs1
8 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 IC}{\b0\i0 \fs18 (hex}{\b0\i0 \fs18 i
nverter}{\b0\i0 \fs18 in}{\b0\i0 \fs18 this}{\b0\i0 \fs18 example).}{\b0\i0
\fs18 The}{\b0\i0 \fs18 trailing}{\b0\i0 \fs19 N}{\b0\i0 \fs18 specifies}{\
b0\i0 \fs18 a}{\b0\i0 \fs18 DIP}{\b0\i0 \fs18 IC. }
\fi364 {\b0\i0 \fs18 Another}{\b0\i0 \fs18 characteristic}{\b0\i0 \fs18 of}{
\b0\i0 \fs19 TTL}{\b0\i0 \fs18 inputs}{\b0\i0 \fs18 should}{\b0\i0 \fs18 b
e}{\b0\i0 \fs18 understood.}{\b0\i0 \fs18 Unconnected}{\b0\i0 \fs18 inputs
}{\b0\i0 \fs18 to}{\b0\i0 \fs18 a}{\b0\i0 \fs18 TTL}{\b0\i0 \fs18 gate }
{\b0\i0 \fs18 are}{\b0\i0 \fs18 said}{\b0\i0 \fs18 to}{\b0\i0 \fs18 be}{\b0
\i0 \fs18 "floating}{\i0 \fs19 HIGH."}{\b0\i0 \fs18 In}{\b0\i0 \fs18 othe
r}{\b0\i0 \fs18 words,}{\b0\i0 \fs18 any}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 in
put}{\b0\i0 \fs18 left}{\b0\i0 \fs18 disconnected}{\b0\i0 \fs18 (floating)
}{\b0\i0 \fs18 will}{\b0\i0 \fs18 be }

{\b0\i0 \fs18 assumed}{\b0\i0 \fs18 to}{\b0\i0 \fs18 be}{\b0\i0 \fs18 at}{\b
0\i0 \fs18 a}{\b0\i0 \fs18 logical}{\b0\i0 \fs19 1. }
\cf0 {\b0\i0 \f10 \fs16 SOLVED}{\b0\i0 \f10 \fs16 PROBLEMS }
{\i0 \fs18 6.14}{\b0\i0 \fs18
List}{\b0\i0 \fs19 six}{\b0\i0 \fs18 TTL}{\
b0\i0 \fs18 subfamilies. }
\fi612 {\i0 \fs17 Solution: }
\fi963 {\b0\i0 \fs17 The}{\i0 \fs17 six}{\b0\i0 \fs18 ITTL}{\b0\i0 \fs17
subfamilies}{\b0\i0 \fs17 currently}{\b0\i0 \fs17
available}{\b0\i0 \fs17
are}{\b0\i0 \fs17 standard}{\b0\i0 \fs17
TTL,}{\b0\i0 \fs17 low-power,}{
\b0\i0 \fs17 low-power}{\b0\i0 \fs17 Schottky, }
\fi610 {\b0\i0 \fs17 Schottky,}{\b0\i0 \fs17 advanced}{\b0\i0 \fs17 low-power
}{\b0\i0 \fs17 Schottky,}{\b0\i0 \fs17 and}{\b0\i0 \fs17 advanced}{\b0\i0 \f
s17 Schottky. }\par
}
\cf0 6.15{\b0 \fs18
The }
}
8 \cf0 (speed, voltage) characteristics of all the{\fs19 TTL} subfamilies are
the same.
{\fs17 The}{\fs17 voltage}{\fs17 characteristics}{\fs16 of}{\fs17 all}{\f
s17 the}{\fs17 ITTL}{\fs17 subfamilies}{\fs17 are}{\fs17 the}{\fs17 sa
me.}{\fs17 They}{\fs17 are}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs16 6la. }\par
}
\cf0 6.16{\b0
The}{\b0 TTL}{\b0 logic}{\b0 family}{\b0 was}{\b0 first}{
\b0 developed}{\b0 in}{\b0 the }
fi950 {\b0 \fs17 The}{\b0 \fs17 first}{\b0 \fs17 TTL}{\b0 \fs17 logic}{\b0 \
fs17 family}{\b0 \fs17 was}{\b0 \fs17 developed}{\b0 \fs17 in}{\fs17 1964
. }\par
}
(1960s, 1970s). \par
}
. 61 \par
}
L AND CMOS ICs: CHARACTERISTICS AND INTERFACING \par
}
\par
}
\cf0 6.17{\b0 \fs18
When}{\b0 \fs18 a}{\b0 \fs18 designer}{\b0 \fs18 s
elects}{\b0 \fs18 a}{\b0 \fs18 logic}{\b0 \fs18 family,}{\b0 \fs18 what}

{\b0 \fs18 two}{\b0 \fs18 very}{\b0 \fs18 important}{\b0 \fs18 character
istics}{\b0 \fs18 must}{\b0 \fs18 be }
fi594 {\b0 \fs18 considered? }
f0 \fi600 {\fs16 Solution: }
fi958 {\b0 \fs17 Designers}{\b0 \fs17 must}{\b0 \fs17 consider}{\b0 \fs17 the
}{\b0 \fs17 speed}{\b0 \fs17 and}{\b0 \fs17 power}{\b0 \fs17 consumption}{\
b0 \fs17 characteristics}{\b0 \fs17 of}{\b0 \fs17 various}{\b0 \fs17 logic}{
\b0 \fs17 families}{\b0 \fs17 in }
fi600 {\b0 \fs17 any}{\b0 \fs17 design. }
f0 6.18{\b0 \fs18
Which}{\f30 \fs20 TTL}{\b0 \fs18 subfamily}{\b0 \fs18 i
s}{\b0 \fs18 the}{\b0 \fs18 fastest? }
fi959 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0\i \f10 \fs15 6-6a
.}{\b0 \fs17 The}{\b0 \fs17 advanced}{\b0 \fs17 Schottky}{\b0 \fs17 TTL}{
\b0 \fs17 family}{\b0 \fs17 provides}{\b0 \fs17 the}{\b0 \fs17 lowest}{\b
0 \fs17 propagation}{\b0 \fs17 delays}{\b0 \fs17 and }
fi597 {\b0 \fs17 therefore}{\b0 \fs17 the}{\b0 \fs17 best}{\b0 \fs17 highspeed}{\b0 \fs17 characteristics. }\par
}
f0 6.19 \par
}
e{\f63 \u8364\'3f}er to Fig.{\fs19 6-5.} This standard{\b \f30 \fs20 TTL} 2-in
put{\b \f30 \fs21 NAND} gate uses
\par}{\phpg\posx1465\pvpg\posy4281\absw5648\absh749 \sl-246 \f20 \fs18 \cf0 pole
) outputs.
}
open-collector, totem \par
}
\cf0 The 2-input TTL NAND gate in Fig. 6-5 uses a totem pole output con
figuration.
{\b \fs18 6.20}{\fs18
Which}{\i \fs18 two}{\b \f30 \fs20 TTL}{\fs18 subf
amilies}{\fs18 consume}{\fs18 the}{\fs18 least}{\fs18 power? }
00 {\b \fs16 Solution: }
58 Refer to Fig.{\i 6-6b.} The low-power and advanced low-power Schottky
'ITL subfamilies are the best
98 for low-power consumption. \par
}
f0 6.21 \par
}
\cf0 TTL{\b0 \f20 \fs18 ICs}{\b0 \f20 \fs18 with}{\b0 \f20 \fs18 totem}{\b
0 \f20 \fs18 pole}{\b0 \f20 \fs18 outputs }
\b0 \f20 \fs18 together. }
f0 {\f20 \fs16 Solution: }\par
}
may, may not) have their outputs connected \par
}
f0 6.22 \par
}
e \par
}
TL totem pole outputs may not have their outputs connected together.
\fi806 {\fs18 (5400,}{\fs18 7400)}{\fs18 series}{\fs18 of}{\b \f30 \fs20 TT
L}{\fs18 logic}{\fs18 devices}{\fs18 will}{\fs18 operate}{\fs18 over}{\fs
18 a}{\fs18 wider}{\fs18 temperature }\par
}
ange, is more expensive, and is referred to as military grade.
56 {\fs17 The}{\fs17 5400}{\fs17 series}{\fs17 of}{\fs17 TTL}{\fs17 logic}{
\fs17 devices}{\fs16 will}{\fs17 operate}{\fs17 over}{\fs17 a}{\fs17 wide
r}{\fs17 temperature}{\fs17 range,}{\fs17 is}{\fs17 more}{\fs17 expensiv
e, }
17 and}{\fs17 is}{\fs17 referred}{\fs17 to}{\fs17 as}{\fs17 military}{\f
s17 grade. }\par
}
\cf0 TTL{\b0 \f20 \fs18 open-collector}{\b0 \f20 \fs18 outputs}{\b0 \f20 \fs18
require}{\b0 \f20 \fs18 a }
\b0 \f20 \fs18 rail}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 po
wer}{\b0 \f20 \fs18 supply. }
\f20 \fs16 Solution: }\par
}
esistor connected from the output to the{\fs19 +5-V }\par
}
f0 6.23 \par
}
cf0 6.24 \par
}
7 \cf0 TTL open-collector outputs require pull-up resistors.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 6-8.}{\fs18 Interpret}{\fs18 the
}{\fs18 markings}{\fs18 on}{\fs18 this}{\fs19 TTL}{\fs18 DIP}{\fs18 IC. }\
par
}
\cf0 Fig.{\fs16 6-8}{\b0 \fs17
TTL}{\b0 \fs17 IC }\par
}
0 114 \par
}
L{\fs17 AND}{\fs17 CMOS}{\fs17 ICs:}{\fs17 CHARACTERISTICS}{\fs17 AND}{\fs1
7 INTERFACING }\par
}
}
\cf0 Solution:
\fi360 {\b0 \fs17 The}{\b0 \fs17 logo}{\b0 \fs17 and}{\b0 \fs17 the}{\b0 \
fs17 DM}{\b0 \fs17 prefix}{\b0 \fs17 indicate}{\b0 \fs17 that}{\b0 \fs17
National}{\b0 \fs17 Semiconductor}{\b0 \fs17 is}{\b0 \fs17 the}{\b0 \fs1
7 manufacturer}{\b0 \fs16 of}{\b0 \fs17 this}{\b0 \fs17 IC. }
{\b0 \fs17 The}{\b0 \fs17 N}{\b0 suffix}{\b0 \fs17 indicates}{\b0 \fs17
that}{\b0 \fs17 this}{\b0 \fs17 is}{\b0 \fs17 a}{\b0 \fs17 dual-in-line}
{\b0 \fs17 package}{\b0 \fs17 IC.}{\b0 \fs17 The}{\b0 \fs17 74ALS76}{\b0 \
fs17 is}{\b0 \fs17 the}{\b0 \fs17 generic}{\b0 \fs17 section}{\b0 \fs17 o
f}{\b0 \fs17 the }
{\b0 \fs17 part}{\b0 \fs17 number.}{\b0 \fs17 The}{\b0 \fs17 74}{\b0 \fs17
means}{\b0 \fs17 this}{\b0 \fs17 is}{\b0 \fs17 a}{\b0 \fs17 commercial
}{\b0 \fs17 grade}{\b0 \fs17 7400}{\b0 \fs17 series}{\b0 \fs17 digital}{\b0
\fs17 TTL}{\b0 \fs17 IC.}{\b0 \fs17 The} 76{\b0 \fs17 specifies}{\b0 \f
s17 the }
{\b0 \fs17 function,}{\b0 \fs17 which}{\b0 \fs17 is}{\b0 \fs17 a}{\b0 \fs1
7 dual}{\b0 \fs17 JK}{\b0 \fs17 flip-flop.}{\b0 \fs17 The}{\b0 \fs17 AL
S}{\b0 \fs17 identifies}{\b0 \fs17 this}{\b0 \fs17 IC}{\b0 \fs17 as}{\b0
\fs17 part}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 advanced}{\b0 \fs17
low-power }
{\b0 \fs17 Schottky?TL}{\b0 \fs17 subfamily. }\par
}
f0 6.25 \par
}
\cf0 An{\b0 \fs18 unconnected}{\b0 \fs18 TTL}{\b0 \fs18 input}{\b0 \fs18 flo
ats}{\b0 \fs18 at}{\b0 \fs18 a }
\fs17 Solution: }
fi365 {\b0 \fs17 HIGH }\par
}
HIGH, LOW) logic level. \par
}
\cf0 6-4{\fs18
CMOS}{\fs18 INTEGRATED}{\fs18 CIRCUITS }

fi372 {\b0 \fs18 The}{\b0 \fs18 first}{\b0\i \fs18 complementary}{\b0\i \fs18
metal-oxide}{\b0\i \fs18 semiconductor}{\b0\i \fs18 (CMOS)}{\b0 \fs18 family
}{\b0 \fs18 of}{\b0 \fs18 ICs}{\b0 \fs18 was}{\b0 \fs18 introduced}{\b0 \fs
18 in}{\b0\i \fs18 1968 }
\b0 \fs18 by}{\b0 \fs18 RCA.}{\b0 \fs18 Since}{\b0 \fs18 then,}{\b0 \fs18
it}{\b0 \fs18 has}{\b0 \fs18 become}{\b0 \fs18 very}{\b0 \fs18 popular.}
{\b0 \fs18 CMOS}{\b0 \fs18 1Cs}{\b0 \fs18 are}{\b0 \fs18 growing}{\b0 \fs1
8 in}{\b0 \fs18 popularity}{\b0 \fs18 because}{\b0 \fs19 of }
\b0 \fs18 their}{\b0 \fs18 extremely}{\b0 \fs18 low}{\b0 \fs18 power}{\b0 \
fs18 consumption,}{\b0 \fs18 high}{\b0 \fs18 noise}{\b0 \fs18 immunity,}
{\b0 \fs18 and}{\b0 \fs18 their}{\b0 \fs18 ability}{\b0 \fs18 to}{\b0 \fs
18 operate}{\b0 \fs18 from}{\b0 \fs18 an }
\b0 \fs18 inexpensive}{\b0 \fs18 nonregulated}{\b0 \fs18 power}{\b0 \fs18
supply.}{\b0 \fs18 Other}{\b0 \fs18 advantages}{\b0 \fs18 of}{\b0 \fs18
CMOS}{\b0 \fs18 ICs}{\b0 \fs18 over}{\b0 \fs18 TTLs}{\b0 \fs18 are}{\b0
\fs18 low}{\b0 \fs18 noise }
\b0 \fs18 generation}{\b0 \fs18 and}{\b0 \fs18 a}{\b0 \fs18 great}{\b0 \fs1
8 variety}{\b0 \fs18 of}{\b0 \fs18 available}{\b0 \fs18 functions.}{\b0 \fs
18 Some}{\b0 \fs18 analog}{\b0 \fs18 functions}{\b0 \fs18 available}{\b0 \fs
18 in}{\b0 \fs18 CMOS}{\b0 \fs18 ICs }
\b0 \fs18 have}{\b0 \fs18 no}{\b0 \fs18 equivalents}{\b0 \fs18 in}{\b0 \fs18
TTLs. }
fi371 {\b0 \fs18 The}{\b0 \fs18 schematic}{\b0 \fs18 diagram}{\b0 \fs19 of}{\
b0 \fs18 a}{\b0 \fs18 CMOS}{\b0 \fs18 inverter}{\b0 \fs18 is}{\b0 \fs18 s
hown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 6-9a.}{\b0 \fs18 It} is{\b0
\fs18 fabricated}{\b0 \fs18 by}{\b0 \fs18 using}{\b0 \fs18 both }
\b0 \fs18 N-channel}{\b0 \fs18 and}{\b0 \fs18 P-channel}{\b0 \fs18 MOSFETS}{
\b0 \fs18 (metal-oxide}{\b0 \fs18 semiconductor}{\b0 \fs18 field-effect}{\b0
\fs18 transistors).}{\b0 \fs18 The}{\b0 \fs18 bottom }
\b0 \fs18 transistor}{\b0 \fs18 (Ql)}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs
18 6-9a}{\fs18 is}{\b0 \fs18 the}{\b0 \fs18 N-channel}{\b0 \fs18 enhancemen
t-mode}{\b0 \fs18 MOSFET.}{\b0 \fs18 The}{\b0 \fs18 top}{\b0 \fs18 transisto
r}{\b0 \fs18 (Q2)}{\b0 \fs18 is }
\b0 \fs18 the}{\b0 \fs18 P-channel}{\b0 \fs18 enhancement-mode}{\b0 \fs18
MOSFET.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 gate}{
\b0 \fs19 (G),}{\b0 \fs18 source}{\fs19 (S),}{\b0 \fs18 and}{\b0 \fs18
drain}{\b0 \fs19 (D) }
\b0 \fs18 connections}{\b0 \fs18 of}{\b0 \fs18 each}{\b0 \fs18 FET}{\b0 \fs1
8 are}{\b0 \fs18 labeled. }\par
}
{\phpg\posx6123\pvpg\posy8520\absw411\absh180 \f20 \fs15 \cf0 \f20 \fs15 \cf0 ln
pu{\fs16 t }\par
}
13 \cf0 Q \par
}
tput \par
}

\cf0 ={\i \f20 \fs18 vss }
\fs14 (b)}{\f20 \fs15 Power}{\f20 \fs15 connections}{\f20 \fs15 on}{\f20 \fs
14 4000 }
76 {\f20 \fs15 series}{\f20 \fs15 CMOS}{\b \f20 \fs15 ICs }\par
}
15 \cf0 GND
s14 (c)} Power{\fs15 connections}{\fs15 on}{\fs14 74COO }
287 {\fs15 and}{\fs14 74HCOO}{\fs15 CMOS}{\b \fs15 ICs }\par
}
put \par
}
tput \par
}
(a){\fs15 Schematic}{\fs15 diagram}{\fs15 of}{\fs15 a}{\fs15 CMOS}{\fs15
inverter }\par
}
\cf0 Fig. 6-9 \par
}
8 \cf0 When the input to the CMOS inverter{\fs19 in} Fig.{\i \fs18 6-9a} goes
LOW (GND), the negative voltage causes
P-channel FET{\f10 \fs18 (Q2)} to conduct. However, the N-channel FET
(Q1) is not conducting. This
\par}{\phpg\posx845\pvpg\posy12476\absw9115\absh1060 \sl-239 \f20 \fs18 \cf0 con
nects the output terminal to the positive{\i (VDD) }
4514 of the power supply through the low-resistance{\b\i \fs19 P }
\par}{\phpg\posx845\pvpg\posy12476\absw9115\absh1060 \sl-230 \f20 \fs18 \cf0 cha
nnel of Q2. The CMOS circuit shown in Fig.{\i \fs18 6-9a} produced a HIGH (posi
tive) output with a LOW
ut. This is the proper action for an inverter. \par
}
.{\fs16 61 }\par
}
L AND CMOS{\fs17 ICs:} CHARACTERISTICS{\fs17 AND} INTERFACING \par
}
\par
}
\cf0 When the input to the CMOS inverter shown in Fig. 6-9a goes{\fs19 HIGH}{\b
\i \fs18 (V,lIl),}the positive voltage
\par}{\phpg\posx835\pvpg\posy1340\absw9239\absh430 \sl-239 \f20 \fs18 \cf0 cause
s the N-channel FET (Q1) to conduct. However, the P-channel FET (Q2) is not cond
ucting. 'This \par

}
nnects the output terminal through the N channel to ground{\fs18 (V&)
}
\par}{\phpg\posx835\pvpg\posy1819\absw6284\absh428 \sl-239 \f20 \fs18 \cf0 examp
le a{\fs19 HIGH} input generates a LOW output. \par
}
f the power supply. In this \par
}
\cf0 The general arrangement of transistors and the operation of the CMOS outpu
t shown in Fig. 6-9a
comparable to the TTL totem pole outputs diagrammed in Fig. 6-5.{\fs19 In} eac
h case only one of the
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-237 \f20 \fs18 \cf0 two
output transistors is conducting at a time. The CMOS arrangement is simple
r and the currents
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-238 \f20 \fs18 \cf0 used
to switch the CMOS are extremely small compared to those of the bipolar TTL cou
nterpart.
60 A logic symbol for the CMOS inverter is shown in Fig. 6-9b. Note especially
the labeling on the
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-237 \f20 \fs18 \cf0 powe
r supply connections. The{\i \fs18 VDU}and{\i \fs18 Vss}{\fs19 (GND)} lab
els are used with the older 4000 series and
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-236 \f20 \fs18 \cf0 many
LSI{\fs19 CMOS} ICs. The newer 74COO and 74HCOO families{\fs19 of} CM
OS digital logic{\fs19 ICs} use the
Vcc} and{\fs19 GND} labels shown in Fig. 6-9c. This labeling is similar to that
of the power connections on
19 TTL} ICS.
65 Manufacturers produce at least three common families of SSI/MSI CMO
S integrated circuits.
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-235 \f20 \fs18 \cf0 They
include the older 4000 series, the 74COO series, and the newer 74HC00 series.
61 The CMOS 4000 series has a wide variety{\fs18 of} circuit functions. The 400
0 series has been improved,
most ICs in this family are now{\i bufSered} and referred to as the 4000B se
ries. Some of the circuit
tions available in the 4000 series are logic gates, flip-flops, regist
ers, latches, adders, buffers,
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-239 \f20 \fs18 \cf0 bila
teral switches, counters, decoders,{\fs18 multiplexers/demultiplexers,}
a
nd multivibrators (astable and
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-238 \f20 \fs18 \cf0 mono
stable).
61 A typical 4000 series IC is sketched in Fig. 6-10a. The manufxturer
is RCA. Pin 1 is located
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-242 \f20 \fs18 \cf0 imme
diately counterclockwise from the notch. The part number (CD4024BE)is decoded in
Fig. 6-10b.
prefix{\fs19 CD} is RCA's code for CMOS digital.{\fs19 The} s u f i{\fs19 E}
is RCA's code for a plastic dual-in-line
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-242 \f20 \fs18 \cf0 pack
age. The generic 4024B is the core number. The 40 identifies this as part o
f the 4000 series of
ICs. The 24 identifies the function of the{\fs19 IC} as a{\fs18 7-s
tage} binary counter. The B stands for
\par}{\phpg\posx833\pvpg\posy2295\absw9311\absh4694 \sl-235 \f20 \fs18 \cf0 seri
es B or buffered CMOS. \par
}
cf0 CD \par
}
cf0 4024B \par
}
cf0 E \par
}
anufacturer's
for CMOS
tal \par
}
\par
}
4 \cf0 1
\f20 \fs14 (a)}{\f20 \fs15 Markings}{\f20 \fs15 on}{\f20 \fs15 a}{\f20 \fs15
typical}{\b \f20 \fs15 CMOS}{\b \f20 \fs14 IC }\par
}
\cf0 Manufacturer's code for
3 plastic{\b \fs15 DIP }
Function of device.
15 7-s}{\fs15 t}age binary counter \par
}
\fs14 \cf0 (h){\i0 \fs15 Decoding}{\i0 \fs15 a}{\i0 \fs15 CMOS}{\b\i0 \fs15
IC}{\i0 \fs15 part}{\i0 \fs15 number }
f0 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 6-10 }\par
}
8 \cf0 The 4000 series of{\fs19 CMOS} ICs features a wide voltage supply range
from{\b \fs18 3} to 15{\b V.} The ICs also
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-234 \f20 \fs18 \cf0 hav
e high noise immunity and very low power consumption{\fs19 (10} nW i
s typical). Many 4000 series

ices can drive two low-power{\fs19 TTLs} or one low-power Schottlcy TTL IC.
357 The 4000 series suffers in the area{\fs18 of} speed. Propagation d
elays may range from{\fs19 20} to 300 ns
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-244 \f20 \fs18 \cf0 dep
ending on the device, temperature, and supply voltage. Static electricity can a
lso be a problem with
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-231 \f20 \fs18 \cf0 CMO
S ICs. Unfortunately, the power consumption{\fs18 of} CMOS devices does increa
se somewhat as the
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-242 \f20 \fs18 \cf0 fre
quency of operation increases.
357 The 74COO series of CMOS digital ICs features functions and pin o
uts compatible with the
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-230 \f20 \fs18 \cf0 ind
ustry standard 7400 TTL series. This helps designers alrea.dy familiar wi
th the 7400 series. The
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-233 \f20 \fs18 \cf0 74C
OO family has the same characteristics as the 4000 series.
357 A typical 74C00 series IC is shown in Fig.{\fs18 6-1}{\b \fs18 1.}
The logo indicates that the manufacturer is
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-237 \f20 \fs18 \cf0 Nat
ional Semiconductor. Pin 1 is located by using a dot, co!or band, or notch. T
he{\b \fs19 IC} has both 4000
\par}{\phpg\posx835\pvpg\posy10597\absw9325\absh2764 \sl-238 \f20 \fs18 \cf0 ser
ies and 74COO series part numbers. The 74COO series part number is MM74C192N. Th
e prefix{\fs19 MM }\par
}
\par
}
FACING }\par
}
AP. 6 \par
}
\cf0 Fig.{\fs17 6-11}{\fs17
A}{\b0 \fs17 typical}{\b0 \fs17 74COO}{\b0 \f
s17 CMOS}{\b0 \fs17 IC }\par
}
s the manufacturer's code for MOS monolithic. The suffix N is National Semico
nductor's code for a
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-237 \f20 \fs19 \cf0 plas
tic DIP IC. 74C192 is the generic part number. The 74C indicates that the IC is
part of the 74COO
es of CMOS ICs. The 192 defines the function of the IC, which is a synchron
ous 4-bit up/down
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-237 \f20 \fs19 \cf0 deca
de counter. This IC can also substitute in the 4000 series family. CD40192BCD is
the 4000 series
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-235 \f20 \fs19 \cf0 part
number.
53 The 74HC00 series of{\i \fs19 high-speed} CMOS digital{\fs19 ICs} is an i
mproved version of the 4000 and 74COO
es. The propagation delays have been improved to attain bipolar (7
4LS) speed. A typical
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-240 \f20 \fs19 \cf0 prop
agation delay of a 74HC00 series gate might be from{\fs19 8} to 12 ns. The n
ormal CMOS advantages
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-237 \f20 \fs19 \cf0 have
been retained but with improved output drive capabilities of up to{\fs18 4} mA
for good fan-out. Some
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-242 \f20 \fs19 \cf0 74HC
00 series ICs have a fan-out of{\fs19 10} LS-TTL loads. The 74HC00 s
eries reproduces the most
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-240 \f20 \fs19 \cf0 popu
lar 7400 and 4000 series functions. A 2- to 6-V power supply operating range was
chosen for the
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-237 \f20 \fs19 \cf0 74CO
O series. A subfamily called the 74HCT00 series is used for interfacing from TTL
to the 74HC00
es.
61 Typical markings on a 74HC00 series high-speed CMOS{\b \fs18 IC} are reprodu
ced in Fig. 6-12. Pin{\fs18 1} is
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-240 \f20 \fs19 \cf0 loca
ted next to the dot. The manufacturer is National Semiconductor Corporation. Tw
o part numbers
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-241 \f20 \fs19 \cf0 appe
ar on the IC; each has the same core number of 74HC32N. The prefix MM is used b
y National
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-237 \f20 \fs19 \cf0 Semi
conductor to mean MOS monolithic, and the prefix MC is used by Motorola. The N
suffix means
\par}{\phpg\posx813\pvpg\posy4217\absw9312\absh4087 \sl-240 \f20 \fs19 \cf0 a D
IP IC. The 74HC means the IC is from the high-speed CMOS family. Th
e 32 describes the
tion of the IC (quad 2-input OR gate). \par
}
\cf0 Fig.{\fs17 6-12}{\b0 \fs17
Typical}{\b0 \fs17 markings}{\b0 \fs17 on
}{\b0 \fs17 a}{\b0 \fs17 74HC00}{\b0 \fs17 series}{\b0 \fs17 high-speed}{\b0
\fs17 CMOS}{\b0 \fs17 IC }\par
}
9 \cf0 The CMOS technology may be most suitable for large-scale and ve
ry-large-scale integrations
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-241 \f20 \fs19 \cf0 ins
tead of SSI/MSI ICs. Because of simple internal circuitry and low po
wer consumption, many
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-240 \f20 \fs19 \cf0 ele
ments can be squeezed onto a very tiny area{\fs19 of} the silicon chip. Some
LSI and VLSI ICs that are
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-237 \f20 \fs19 \cf0 ava
ilable in CMOS are microprocessors, memory devices (RAMS, PROMS), microcontrol
lers, clocks,
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-237 \f20 \fs19 \cf0 mod
ems, filters, coders-decoders, and tone generators for telecommunicat

ions, analog-to-digital
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-241 \f20 \fs19 \cf0 (A/
D) and digital-to-analog (D/A) converters, LCD display decoders/drivers, UART
S for serial data
\par}{\phpg\posx837\pvpg\posy12137\absw9107\absh1509 \sl-237 \f20 \fs19 \cf0 tra
nsmission, and calculator chips. \par
}
. 61 \par
}
{\phpg\posx2505\pvpg\posy552\absw5443\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 "T
L{\fs17 AND}{\fs17 CMOS}{\fs17 ICs:}{\fs17 CHARACTERISTICS}{\fs17 AND}{\f
s17 INTERFACING }\par
}
\par
}
\cf0 Manufacturers suggest that, when CMOS ICs are being worked with,{\i \fs19
damage}{\b\i \f30 \fs19 from}{\i \fs19 static}{\b\i \fs19 discharge }
\fs19 and}{\i \fs19 transient}{\i \fs19 voltages}{\i \fs19 can}{\i \fs19 b
e}{\i \fs19 prevented} by:
75 {\fs18 1.} Storing CMOS ICs in special conductive foam
67 {\fs18 2.}
Using battery-powered soldering irons when working on CMOS chi
ps or grounding the tips of
19 ac-operated irons
67 {\fs19 3.} Turning power off when removing CMOS ICs{\fs19 or} changing con
nections on a breadboard
67 {\fs18 4.}
Ensuring that input signals do not exceed power supply voltage
s
65 {\fs19 5.} Turning input signals off before turning circuit power{\fs19 of
f }
67 {\i \fs19 6.}
Connecting{\i \fs19 all}{\i \fs19 unused}{\i \fs19 inpu
t}{\i \fs19 leads} to either positive or GND of the power supply (only unused
19 CMOS{\i \fs19 outputs} may be left unconnected)
\fs18 6.26}
List three SSI/MSI families of CMOS ICs.
70 {\fs17 Three}{\fs17 popular}{\fs17 SSI/MSI}{\fs17
families}{\fs17 of}
{\fs17 CMOS}{\fs17 ICs}{\fs17 are}{\fs17 the}{\fs17 4000,}{\fs17 74C00,
}{\fs17 and}{\fs17 the}{\fs17 74HC00}{\fs17 series. }\par
}
cf0 6.27{\b0 \fs19
The }

}
\cf0 (CMOS, TTL) family of digital ICs was first introduced in{\b \fs18 1964.
}
{\fs17 The}{\fs17 TTL}{\fs17 family}{\fs17 was}{\fs17 first}{\fs17 introduc
ed}{\fs17 in}{\fs17 1964.}{\fs17 RCA}{\fs17 came}{\fs17 out}{\fs17 with}
{\fs17 CMOS}{\fs17 in}{\fs17 1968. }\par
}
\cf0 6.28{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0\i \fs19 6-9
a.}{\b0 \fs19 If}{\b0 \fs19 the}{\b0 \fs19 input}{\b0 \fs19 is}{\b0 \fs19
at}{\b0 \fs19 GND}{\b0 \fs19 potential,}{\b0 \fs19 which}{\b0 \fs19 MOSFE
T}{\b0 \fs19 transistor}{\b0 \fs19 is}{\b0 \fs19 turned}{\b0 \fs19 on }
fi597 {\b0 \fs19 (conducting)? }
fi957 {\b0 \fs17 If}{\b0 \fs17 the}{\b0 \fs17 inverter}{\b0 \fs17 input}{\
b0 \fs17 (Fig.}{\b0 \fs17 6-9a)}{\b0 \fs17 is}{\b0 \fs17 negative}{\b0 \f
s17 (GND),}{\b0 \fs17 then}{\b0 \fs17 the}{\b0 \fs17 P-channel}{\b0 \fs17
transistor}{\b0 \fs17 (Q2)}{\b0 \fs17 will}{\b0 \fs17 conduct }
fi597 {\b0 \fs17 (be}{\b0 \fs17 turned}{\b0 \fs17 on).}{\b0 \fs17 When}{\b0
\fs17 the}{\b0 \fs17 input}{\b0 \fs17 is}{\b0 \fs17 LOW,}{\b0 \fs17 the
}{\b0 \fs17 output}{\b0 \fs17 from}{\b0 \fs17 the}{\b0 \fs17 inverter}{\b
0 \fs17 will}{\b0 \fs17 be}{\b0 \fs17 HIGH. }
f0 6.29{\b0 \fs19
Decode}{\b0 \fs19 the}{\b0 \fs19 markings}{\b0 \fs19
on}{\b0 \fs19 the}{\b0 \fs19 IC}{\b0 \fs19 depicted}{\b0 \fs19 in}{\b0
\fs19 Fig.}{\b0 \fs19 6-13.}{\b0 \fs19 To}{\b0 \fs19 interpret}{\b0 \fs1
9 all}{\b0 \fs19 the}{\b0 \fs19 markings,}{\b0 \fs19 a }
fi597 {\b0 \fs19 manufacturer's}{\b0 \fs19 logic}{\b0 \fs19 manual}{\b0 \fs19
or}{\b0\i \fs19 IC}{\b0\i \fs19 Master}{\b0 \fs19 would}{\b0 \fs19 proba
bly}{\b0 \fs19 be}{\b0 \fs19 required. }\par
}
\cf0 Fig. 6-13{\b0 \fs17
Dual-in-line}{\b0 \fs17 package}{\b0 \fs17 IC }\p
ar
}
7 \cf0 Solution:
\fi356 {\b0 \fs17 The}{\b0 \fs17 manufacturer}{\b0 \fs17 is}{\b0 \fs17 Nat
ional}{\b0 \fs17 Semiconductor}{\b0 \fs17 (logo);}{\b0 \fs17 the}{\b0 \fs17
core}{\b0 \fs17 number}{\b0 \fs17 is}{\b0 \fs17 4001B.}{\b0 \fs17 CD}{
\b0 \fs17 is}{\b0 \fs17 the}{\b0 \fs17 manufac- }
{\b0 \fs17 turer's}{\b0 \fs17 code}{\b0 \fs17 for}{\b0 \fs17 the}{\b0 \fs
17 CMOS}{\b0 \fs17 4000}{\b0 \fs17 series}{\b0 \fs17 of}{\b0 \fs17 ICs.}{
\b0 \fs17 The}{\b0 \fs17 suffix}{\b0 N}{\b0 \fs17 is}{\b0 \fs17 the}{\b0
\fs17 manufacturer's}{\b0 \fs17 code}{\b0 \fs17 for}{\b0 \fs17 a}{\b0 \fs
17 plastic}{\b0 \fs17 DIP. }
{\b0 \fs17 The}{\b0 \fs17 suffix}{\b0 \fs17 C}{\b0 \fs17 is}{\b0 \fs17 f
or}{\b0 \fs17 a}{\b0 \fs17 temperature}{\b0 \fs17 range}{\b0 \fs17 of}{\
b0 \fs17
-40}{\b0 \fs17
to}{\b0 \fs17 85C.}{\b0 \fs17 The}{\b0 40}{\b0
\fs17 indicates}{\b0 \fs17 the}{\b0 \fs17 4000}{\b0 \fs17 series}{\fs17
of}{\b0 \fs17 CMOS}{\b0 \fs17 ICs. }
{\b0 \fs17 The}{\b0 \fs17 01}{\b0 \fs17 indicates}{\b0 \fs17 the}{\b0 \fs
17 function}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 IC}{\b0 \fs17 (qua
d}{\b0 \fs17 2-input}{\b0 \fs17 NOR}{\b0 \fs17 gate}{\b0 \fs17 in}{\b0 \
fs17 this}{\b0 \fs17 example),}{\b0 \fs17 and}{\fs17 B}{\b0 \fs17 stan
ds}{\b0 \fs17 for}{\b0 \fs17 a }
{\b0 \fs17 buffered}{\b0 \fs17 CMOS}{\b0 \fs17 IC.}{\fs17 A}{\b0 \fs17 man
ufacturer's}{\b0 \fs17 CMOS}{\b0 \fs17 logic}{\b0 \fs17 data}{\b0 \fs17 ma
nual}{\b0 \fs17 or}{\b0 \fs17 general}{\b0 \fs17 manual}{\b0 \fs17 such}{\
b0 \fs17 as}{\b0 \fs17 the}{\i \fs17 IC}{\i \fs17 Master }
{\b0 \fs17 is}{\b0 \fs17 needed}{\b0 \fs17 to}{\b0 \fs17 find}{\b0 \fs17
some}{\b0 \fs17 of}{\b0 \fs17 this}{\b0 \fs17 information. }\par
}
\par
}
6 INTERFACING }\par
}
}
cf0 6.30{\b0 \fs18
List}{\b0 \fs18 several}{\b0 \fs18 advantages}{\b0 \fs1
8 of}{\b0 \fs18 CMOS}{\b0 \fs18 ICs}{\b0 \fs18 over}{\b0 \fs19 TTL}{\b0 \fs
18 devices. }
i958 {\b0 \fs16 The}{\b0 \fs16 advantages}{\b0 \fs16 of}{\b0 \fs16 CMOS}{\b
0 \fs17 ICs}{\b0 \fs16 over}{\b0 \fs17 TTLs}{\b0 \fs16 are}{\b0 \fs16 lower
}{\b0 \fs16 power}{\b0 \fs16 consumption,}{\b0 \fs16 better}{\b0 \fs16 noise
}{\b0 \fs16 immunity,}{\b0 \fs16 lower }
i604 {\b0 \fs16 noise}{\b0 \fs16 generation,}{\b0 \fs16 and}{\b0 \fs16 the}
{\b0 \fs16 ability}{\b0 \fs16 to}{\b0 \fs16 operate}{\b0 \fs16 on}{\b0 \fs
16 an}{\b0 \fs16 inexpensive,}{\b0 \fs16 nonregulated}{\b0 \fs16 power}{\
b0 \fs16 supply. }\par
}
f0 6.3{\fs18 1 }\par
}
ist some disadvantages of CMOS ICs compared with{\fs19 TTLs. }
\fs16 Solution: }
60 {\fs16 The}{\fs16 disadvantages}{\fs16 of}{\fs16 CMOS}{\fs16 ICs}{\fs
16 compared}{\fs16 with}{\fs17 TTLs}{\fs16 are}{\fs16 poorer}{\fs16
speed}{\fs16 characteristics,}{\fs16 unwanted }
16 sensitivity}{\fs16 to}{\fs16 static}{\fs16 discharges}{\fs16 and}{\fs16
transient}{\fs16 voltages,}{\fs16 and}{\fs16 lower}{\fs16 output}{\fs16

current}{\fs16 drive}{\fs16 capabilities. }\par
}
cf0 6.32{\b0 \fs18
Unused}{\b0 \fs18 CMOS}{\b0 \fs18 inputs }
}
may, may not) be left disconnected. \par
}
\cf0 Unused CMOS inputs may not be left disconnected.
{\b \fs18 6.33}{\fs18
When}{\fs18
(CMOS,}{\fs19 TTL)}{\fs18
chips}{\fs18 are}{\fs18 being}{\fs18 worked}{\fs18 on,}{\fs18 battery-ope
rated}{\fs18 soldering}{\fs18 irons}{\fs18 are }
97 {\fs18 recommended}{\fs18 to}{\fs18 protect}{\fs18 the}{\fs18 circuitry.
}
50 When CMOS chips are being worked on, battcry-operated soldering iron
s are used to protect the
91 circuits from possible static discharges or transient voltages. \par
}
cf0 6.34{\b0 \fs18
The }
}
cf0 6.35{\b0 \fs18
The }
}
8 \cf0 (CMOS,{\fs19 TTL)} family has better noise immunity.
{\fs16 The}{\fs16 CMOS}{\fs16 family}{\fs16 has}{\fs16 better}{\fs16 n
oise}{\fs16 immunity}{\fs16 than}{\fs17 TTL}{\fs17 ICs. }
\fi770 {\fs19 (4000,} 74HC00) series{\fs18 of} CMOS ICs has lower propagation
delays. \par
}
\cf0 The 74HC00 series of CMOS{\fs17 ICs} has lower propagation delay
s and can therefore be used at high
\par}{\phpg\posx1461\pvpg\posy8765\absw8244\absh383 \sl-215 \f20 \fs16 \cf0 freq
uencies. \par
}
s17 \cf0 6-5{\i0 \f20 \fs18
INTERFACING}{\i0 \f20 \fs18 TTL}{\i0 \f20 \fs18
AND}{\i0 \f20 \fs18 CMOS}{\i0 \f20 \fs18 ICs }
\fi354 {\b0 \f20 \fs19 Interfacing}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18
the}{\b0\i0 \f20 \fs18 method}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 connec
ting}{\b0\i0 \f20 \fs19 two}{\b0\i0 \f20 \fs18 electronic}{\b0\i0 \f20 \fs18
devices}{\b0\i0 \f20 \fs18 such}{\b0\i0 \f20 \fs18 as}{\b0\i0 \f20 \fs18 logi
c}{\b0\i0 \f20 \fs18 gates.}{\b0\i0 \f20 \fs18 Manufacturers }
{\b0\i0 \f20 \fs18 guarantee}{\b0\i0 \f20 \fs18 that,}{\b0 \f20 \fs19 within}
{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 family}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20
\fs18 logic}{\b0\i0 \f20 \fs18 circuits,}{\b0\i0 \f20 \fs18 one}{\b0\i0 \f20
\fs18 gate}{\b0\i0 \f20 \fs18 will}{\b0\i0 \f20 \fs18 drive}{\b0\i0 \f20 \fs
18 another.}{\i0 \f20 \fs18 As}{\b0\i0 \f20 \fs18 an}{\b0\i0 \f20 \fs18 ex
ample,}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 two }
{\b0\i0 \f20 \fs19 TTL}{\b0\i0 \f20 \fs18 gates}{\b0\i0 \f20 \fs18 shown}{\b
0\i0 \f20 \fs18 in}{\b0\i0 \f20 \fs18 Fig.}{\b0 \f20 \fs19 6-14a}{\b0\i0 \f
20 \fs18 are}{\b0\i0 \f20 \fs18 simply}{\b0\i0 \f20 \fs18 connected}{\b0\i0
\f20 \fs18 together}{\b0\i0 \f20 \fs18 with}{\b0\i0 \f20 \fs18 no}{\b0\i0
\f20 \fs18 extra}{\b0\i0 \f20 \fs18 parts}{\b0\i0 \f20 \fs18 required}{\b
0\i0 \f20 \fs18 and}{\b0\i0 \f20 \fs18 no }
{\b0\i0 \f20 \fs18 problems.}{\i0 \f20 \fs18 A}{\b0\i0 \f20 \fs18 second}{\
b0\i0 \f20 \fs18 example}{\b0\i0 \f20 \fs18 of}{\b0\i0 \f20 \fs18 two}{\b0
\i0 \f20 \fs18 CMOS}{\b0\i0 \f20 \fs18 gates}{\b0\i0 \f20 \fs18 interfaced
}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 illustrated}{\b0\i0 \f20 \fs18 i
n}{\b0\i0 \f20 \fs18 Fig.}{\b0\i0 \f20 \fs18 6-14b.}{\b0\i0 \f20 \fs18 In}
{\b0\i0 \f20 \fs18 both }
{\b0\i0 \f20 \fs18 examples}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 manufac
turer}{\b0\i0 \f20 \fs18 has}{\b0\i0 \f20 \fs18 taken}{\b0\i0 \f20 \fs18 gre
at}{\b0\i0 \f20 \fs18 care}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 make}{\b0
\i0 \f20 \fs18 sure}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 devices}{\b0\i0
\f20 \fs18 would}{\b0\i0 \f20 \fs18 interface}{\b0\i0 \f20 \fs18 easily}{\b
0\i0 \f20 \fs18 and }
{\b0\i0 \f20 \fs18 properly. }\par
}
\cf0 TTL
15 driver }\par
}
TL \par
}
\cf0 CMOS
fi24 {\b0 \fs15 driver }\par
}
\cf0 CMOS
fi79 {\b0 \fs15 load }\par
}
}
\cf0 (a){\b\i0 \f20 \fs14 Interfacing}{\b\i0 \f20 \fs14 two}{\i0 \f20 \fs14
TTL}{\b\i0 \f20 \fs13 gates }\par
}
14 \cf0 74C04

\i \f20 \fs15 (h)}{\b \f20 \fs14 Interfacing}{\b \f20 \fs14 two}{\b \f20 \fs1
4 CMOS}{\b \f20 \fs14 gates }\par
}
\cf0 Fig.{\fs16 6-14 }\par
}
{\phpg\posx3305\pvpg\posy1838\absw909\absh328 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Re
gular TTL
\par}{\phpg\posx3305\pvpg\posy1838\absw909\absh328 \sl-176 \f20 \fs15 \cf0 input
\par
}
cf0 CMoS \par
}
\cf0 CMOS
5 -output }\par
}
{\phpg\posx4883\pvpg\posy2214\absw393\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 GN
D \par
}
\cf0 7 \par
}
a){\fs15 Standard}{\fs15 TTL-to-CMOS}{\fs15 interfacing}{\fs15 using}{\fs
15 pull-up}{\fs15 resistor }\par
}
cf0 +5{\i0 \fs22 v }
\par}{\phpg\posx5335\pvpg\posy3302\absw881\absh643 \sl-225 \par\i \f20 \fs16 \cf
0 \fi260 {\b\i0 \fs15 2.2}{\b\i0 \f30 \fs16 k&2 }\par
}
191 \cf0 f&
\par}{\phpg\posx4805\pvpg\posy2672\absw4062\absh2664 \sl-1507 \f30 \fs191 \cf0 {
\f10 \fs150 . }\par
}
s14 \cf0 (h){\b0\i0 \fs15 Low-power}{\b0\i0 \fs15 Schottky}{\b0\i0 \fs15 TTLto-CMOS}{\b0\i0 \fs15 interfacing}{\b0\i0 \fs15 using}{\b0\i0 \fs15 a}{\b0\i
0 \fs15 pull-up}{\b0\i0 \fs15 resistor }
\fi2579 {\f10 \fs14 +5}{\b0\i0 \fs22 v }\par
}
\par
}
0 f$ \par
}
{\phpg\posx4589\pvpg\posy4382\absw701\absh521 \f20 \fs15 \cf0 \f20 \fs15 \cf0 -I
TL
fi308 GND \par
}
{\phpg\posx5801\pvpg\posy4379\absw504\absh174 \f20 \fs15 \cf0 \f20 \fs15 \cf0 CM

OS \par
}
\b \f30 \fs17 CMOS }\par
}
tput \par
}
\par
}
ow-power TTL
ut \par
}
0 \cf0 t
\f10 \fs12 (c)}{\f20 \fs15 CMOS-to-low-power}{\f20 \fs15 Schottky}{\f20 \fs1
5 TTL}{\f20 \fs15 interfacing }\par
}
{\phpg\posx5095\pvpg\posy9191\absw991\absh172 \f20 \fs15 \cf0 \f20 \fs15 \cf0 sb
uffer>{\fs15 (4049 }\par
}
\par
}
GNDy \par
}
tputTTL \par
}
\cf0 5 \par
}
fs14 \cf0 ( d ){\b0\i0 \f20 \fs15 CMOS-to-standard}{\b0\i0 \f20 \fs15 TTL}{\
b0\i0 \f20 \fs15 interfacing}{\b0\i0 \f20 \fs15 using}{\b0\i0 \f20 \fs15 a}{\
b0\i0 \f20 \fs15 CMOS}{\b0\i0 \f20 \fs15 buffer}{\i0 \f20 \fs15 IC }
\cf0 \fi2214 {\b0 \f20 \fs15 +5}{\b0\i0 \f20 \fs22 v }\par
}
nputLow-power (LS)TTL \par
}
{\phpg\posx3379\pvpg\posy6675\absw866\absh335 \f20 \fs15 \cf0 \f20 \fs15 \cf0 An
y{\fs15 CMOS }
\par
}
{\phpg\posx3371\pvpg\posy9150\absw603\absh208 \f20 \fs15 \cf0 \f20 \fs15 \cf0 ci
nput M \par
}
\par
}
{\phpg\posx4692\pvpg\posy9192\absw73\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 s \
par
}
\cf0 Input
1 anyTI'L
\par}{\phpg\posx2789\pvpg\posy11594\absw777\absh516 \sl-208 \f20 \fs15 \cf0 or{\
b \fs15 NMOS }\par
}
ND \par
}
\cf0 HTC
cf0 \fi346 74HCT34
\fi368 {\b0 \fs15 GND }\par
}
ny CMOS
75 output \par
}
27 \cf0 \par}{\phpg\posx3775\pvpg\posy12765\absw4156\absh572 \sl-314 \f10 \fs27 \cf0 {\b
\i \f20 \fs15 (}{\b\i \f20 \fs15 e}{\b\i \f20 \fs15 )}{\f20 \fs15 TTL-to-CMOS
}{\f20 \fs15 interfacing}{\f20 \fs15 using}{\f20 \fs15 a}{\b \f20 \fs15 74HC
TOO}{\f20 \fs15 series}{\f20 \fs15 IC }\par
}
ig.{\b \f10 \fs15 6-15}{\fs15
Interfacing}{\fs17 TTL}{\fs15 and}{\fs17 C
MOS}{\fs15 when}{\fs15 both}{\fs15 devices}{\fs15 operate}{\fs17 on}{\fs1
7 a}{\fs15 common }
02 {\fs15 Digital}{\fs15 Electronics,}{\b\i \fs17 3d}{\b\i \fs17 ed.,}{\b\
i \fs17 McGruw-Hill,}{\b\i \fs16 New}{\b\i \fs17 York,}{\b\i \fs16 1990) }
\fi4608 {\fs19 119 }\par
}
{\b \f30 \fs18 5-V }\par
}
supply{\fs16 (Roger}{\fs16 L.}{\b\i \fs17 Tokheim, }\par
}
{\phpg\posx5403\pvpg\posy12648\absw272\absh436 \f10 \fs35 \cf0 \f10 \fs35 \cf0 \par}{\phpg\posx5403\pvpg\posy12648\absw272\absh436 \sl-272 \f10 \fs35 \cf0 \fi4
0 {\dn006 \fs27 - }\par
}
0 120 \par
}
L{\fs16 AND}{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICSAND}{\b \
fs17 INTERFACING }\par
}
}
\cf0 What about interfacing families of ICs such as TTL and CMOS? CMO
S and TTL logic levels
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-232 \f20 \fs18 \cf0 (vol
tages) are defined differently. Refer to Fig.{\i \fs19 6-1} for details on
the definition of LOW and HIGH
c levels{\fs19 of} both TTL and CMOS ICs. Because of the differences in voltage
levels, CMOS and TTL
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-239 \f20 \fs18 \cf0 ICs
usually cannot simply be connected directly together as within a family. Current
requirements for
and TTL{\b \fs19 ICs} also are different. Therefore, TTL and CMOS ICs usually
cannot be connected
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-240 \f20 \fs18 \cf0 dire
ctly. Special simple{\i \fs19 interface}{\i \fs19 techniques} will be outlin
ed.
68 Interfacing a CMOS with a TTL IC{\b \fs18 is} quite easy{\fs18 if}
both devices operate on a common{\i \fs19 +5-V }
r supply. Figure{\i \fs19 6-15} shows five examples of TTL-to-CMOS and CMOS-to
-TTL interfacing.
62 Figure{\i \fs19 6-15a} shows the use{\fs18 of} a{\i \fs19 1-kR}{\b\i \f
s17 pull-up}{\i \fs19 resistor} for interfacing standard TTL with CMOS
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-242 \f20 \fs18 \cf0 ICs.
Figure{\i \fs19 6-191} shows the use of a{\b \fs19 2.2-kR} pull-up resistor f
or interfacing low-power{\fs18 TTL} ICs with
ICs.
62 CMOS-to-TTL interfacing is even easier. Figure{\i \fs19 6-15c} shows both CM
OS and low-power TTL ICs
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-239 \f20 \fs18 \cf0 shar
ing the same{\i \fs19 +5-V} power supply.{\b A} direct connection betw
een a CMOS output and{\i \fs19 any}{\i \fs19 one }
\par}{\phpg\posx841\pvpg\posy1353\absw9177\absh3698 \sl-236 \f20 \fs18 \cf0 lowpower TTL input can be made. Note that the CMOS gate can drive only
one low-power{\fs18 TTL }
t. The exception would be 74HC00 series CMOS, which can drive up to 10 low-power
TTL inputs.
\fi4496 {\f10 \fs14 +10}{\fs23 v }\par
}
4t \par
}
cf0 +5{\b0 \f20 \fs21 v }\par
}
{\b \f20 \fs15 kS2 }\par
}

cf0 voltage) \par
}
cf0 Any{\b0 \fs15 TTL- }
\par}{\phpg\posx2397\pvpg\posy6672\absw819\absh340 \sl-180 \b \f20 \fs14 \cf0 in
put \par
}
cf0 2N3904 \par
}
\dn006 \fs34 -.}{\up006 \fs35 .}{\fs50 - }\par
}
s13 \cf0 (a){\i0 \f20 \fs14 TTL-to-CMOS}{\i0 \f20 \fs14 interfacing}{\i0 \f20
\fs14 using}{\i0 \f20 \fs14 a}{\i0 \f20 \fs14 transistor }
\fi1733 {\b0\i0 \fs14 +10}{\b0\i0 \f20 \fs22 v }
\fi532 {\fs14 +5,}{\b0\i0 \f20 \fs22 v }\par
}
cf0 Any{\b0 \fs15 TTL }
fs14 input }\par
}
4 \cf0 4
{\b\i \fs15 (b)}{\b \fs14 TTL-to-CMOS}{\b \fs14 interfacing}{\b \fs14 using}{
\b \fs14 an}{\b \fs14 TTL}{\b \fs14 open-collectorbuffer}{\b \fs14 IC }\par
}
10{\f20 \fs22 v }\par
}
\cf0 +5,{\b0 \f20 \fs22 v }\par
}
f0 . \par
}
TL
\fs14 output }\par
}
{\phpg\posx6919\pvpg\posy12332\absw62\absh105 \f10 \fs9 \cf0 \f10 \fs9 \cf0 I \p
ar
}
0 \fs14 \cf0 (c){\fs14 CMOS-to-TTL}{\fs14 interfacing}{\fs14 using}{\fs14 a
}{\fs14 CMOS}{\fs14 buffer}{\fs14 IC }
f0 {\fs16 Fig.}{\fs17 6-16}{\fs17
Interfacing}{\b0 \fs17 TTL}{\fs17 and}{\
fs17 CMOS}{\fs17 deviceswhen}{\fs17 each}{\fs17 device}{\fs17 uses}{\b0 \f
s16 a}{\fs17 different}{\fs17 power}{\fs17 supply}{\fs17 voltage}{\i \fs16
(Roger}{\b0\i \fs17 L. }
fi810 {\b0\i \fs17 Tokheim,}{\fs17 Digital}{\fs17 Electronics,}{\i \fs17 3d}{
\i \fs17 ed.,}{\i \fs16 McCraw-Hill,}{\b0\i \fs17 New}{\b0\i \fs17 York,}

{\i \fs16 1990) }\par
}
\cf0 CMOS \par
}
}
L{\fs17 AND}{\b \fs17 CMOS}{\b \fs15 ICs:}{\b CHARACTERISTICS}{\fs17 AND}{\b
}
f0 121 \par
}
or more driving power, Fig.{\b \fs18 6-15d} shows the use of a special{\b \fs18
4049} CMOS buffer between the CMOS
TTL units. The CMOS buffer can drive up to two standard TTL inputs.{\b \fs18
A} noninverting buffer
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-237 \f20 \fs19 \cf0 whic
h is similar to the unit shown in Fig.{\b \fs18 6-15d} is the 4050 CMOS IC.
63 The problem of voltage incompatibility from{\fs19 TTL} (or NMOS) to
CMOS can be solved using a
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-241 \f20 \fs19 \cf0 pull
-up resistor as in Fig.{\b \fs18 6-15a.}{\b A} second method of solv
ing this interface problem is shown in
18 Fig.}{\b \fs18 6-15e.} The 74HCT00 series of CMOS ICs is designed as{\fs19
an} interface element between TTL (or
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-235 \f20 \fs19 \cf0 NMOS
) and CMOS.{\b \fs18 A}{\b \fs18 74HCT34} noninverting IC is used as the inte
rface element between{\fs19 TTL} and
ICs in Fig.{\b \fs18 6-15e. }
63 The{\b \fs18 74HCT00} series of CMOS ICs is used for interfacing b
etween{\b \f30 \fs21 LSI} NMOS devices and
. The NMOS output characteristics are almost the same as for low-power Schottk
y{\fs19 TTL} ICs.
67 Interfacing{\fs19 a} CMOS device with a{\fs19 TTL} device requires some
additional components when each
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-234 \f20 \fs19 \cf0 oper
ates on a{\b \fs18 difierent}{\b \fs18 voltagepower}{\b \fs18 supply.} Figu
re{\b \fs18 6-16} shows three examples of TTL-to-CMOS and
-to-TTL interfacing. Figure{\b \fs18 6-16a} shows the TTL inverter driv
ing a general-purpose NPN
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-241 \f20 \fs19 \cf0 tran
sistor. The transistor and associated resistors translate the lower-volt
age{\fs19 ITTL} outputs to the
\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-234 \f20 \fs19 \cf0 high
-voltage inputs needed to operate the CMOS inverter. The CMOS output
has a voltage swing

\par}{\phpg\posx863\pvpg\posy1351\absw9415\absh3846 \sl-234 \f20 \fs19 \cf0 from
GND to{\fs18 +10}{\b \fs18 V. }
69 Figure{\b \fs18 6-16b} shows an{\b \fs18 open-collector} TTL buffer an
d a{\b \fs19 10-kR} pull-up resistor being used to
slate from the lower TTL to the higher CMOS voltages. The{\b \fs18 7406
} and{\b \fs18 7416}{\fs19 ITTL} ICs are two \par
}
cf0 +5{\b0 \f20 \fs22 v }\par
}
cf0 +5{\b0 \f20 \fs23 v }\par
}
cf0 CMOS
put \par
}
\cf0 Light{\b0 \f10 \fs14 =} LOW \par
}
s12 \cf0 (a){\i0 \f20 \fs15 LED}{\i0 \f20 \fs15 lights}{\i0 \f20 \fs15 when}
{\i0 \f20 \fs15 output}{\i0 \f20 \fs14 is}{\i0 \f20 \fs15 HIGH }
\fi215 {\b0\i0 \f20 \fs22 +1ov-+15v }\par
}
cf0 input \par
}
s15 \cf0 (b){\i0 \fs15 LED}{\i0 \fs15 lights}{\i0 \fs15 when}{\i0 \fs15 outp
ut}{\i0 \fs15 is}{\i0 LOW }
\fi1418 {\b0\i0\dn006 \fs15 +I0}{\b0\i0 \fs22 v}{\b0\i0 \f10 \fs23 -}{\b0\i0 \
fs16 +15}{\b0\i0 \fs22 v }\par
}
\cf0 cMosw \par
}
\fs15 \cf0 t=HIGH
0 {\b0 \f10 \fs14 1}{\fs15 kS2 }\par
}
{\phpg\posx5517\pvpg\posy9246\absw978\absh464 \f10 \fs39 \cf0 \f10 \fs39 \cf0 ::
,ss \par
}
cf0 Light{\b0 \f10 \fs14 =}{\f30 \fs17 LOW }\par
}
\cf0 f@1k~2{\i \fs12 vDD}{\b0 \f10 \fs27 \\\\ }
f0 \fi236 {\f30 \fs17 CMOS }
fi1150 output \par
}
\cf0 (c){\fs15 LED}{\fs15 lights}{\fs15 when}{\fs15 output}{\fs15 is}{\fs
15 HIGH }
\fi236 {\f10 \fs14 +5}{\b0 \fs22 v}{\b0 \f10 \fs19 -}{\b0 \fs15 +15}{\b0 \fs2
2 v }\par
}
fs15 \cf0 ( d ){\i0 \fs15 LED}{\i0 \fs15 lights}{\i0 \fs15 when}{\i0 \fs15
output}{\i0 \fs15 is}{\i0 \fs15 LOW }
0 \fi1440 {\f10 \fs15 +5}{\i0 \fs16 v-+15}{\b0\i0 \fs22 v }\par
}
\cf0 Light{\b0 \f10 \fs14 =} LOW \par
}
\cf0 (e){\fs15 CMOS}{\fs15 inverting}{\fs15 buffer-to-LED}{\fs15 interfaci
ng }\par
}
fs15 \cf0 (f){\i0 \f20 \fs15 CMOS}{\i0 \f20 \fs15 noninverting}{\i0 \f20 \fs15
buffer-to-LED}{\i0 \f20 \fs15 interfacing }\par
}
\cf0 Fig.{\fs16 6-17}{\fs15
CMOS-to-LED}{\fs15 interfacing}{\i \fs17 (R
oger}{\b0\i \fs17 L.}{\i \fs17 Tokheim,}{\fs15 Digital}{\fs15 Electronics
,}{\i 3d}{\i \fs17 ed.,}{\i \fs17 McGruw-Hill,}{\i \fs17 New}{\i \fs17
York, }
fi806 {\i \fs16 1990}{\b0 \f10 \fs14 ) }\par
}
\par
}
L AND CMOS ICs: CHARACTERISTICSAND INTERFACING \par
}
AP. 6 \par
}
nverting, open-collector buffers. The{\fs18 7407} and{\fs18 7417} TTL ICs are
similar noninverting, open-collector
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-234 \f20 \fs18 \cf0 buff
ers which can also be used in the circuit{\fs18 in} Fig.{\fs18 6-16b. }
64 Interfacing a higher-voltage CMOS inverter to a lower-voltage TTL in
verter is illustrated in
{\fs18 6-16c.} The{\fs18 4049} buffer is used between the higher-voltage CM
OS inverter and the lower-voltage
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-235 \f20 \fs18 \cf0 TTL
IC. Note that the CMOS buffer is powered by the lower-voltage{\fs18 (+5-V)} po
wer supply shown in
{\fs18 6-16c. }

64 Digital circuits can also drive devices other than logic gates. Int
erfacing CMOS devices with
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-244 \f20 \fs18 \cf0 simp
le LED indicator lamps is easy. Figure{\fs18 6-17} shows six examples
{\fs18 of} CMOS ICs driving LED
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-239 \f20 \fs18 \cf0 indi
cators. Figure{\fs18 6-17a} and b shows the CMOS supply voltage at{\i \
fs19 +5}{\fs18 V.} At this low voltage, no
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-234 \f20 \fs18 \cf0 limi
ting resistors are needed in series with the LEDs. In Fig.{\fs18 6-17a,}
when the output of the CMOS
rter goes HIGH, the LED output indicator lights. The opposite is true in
Fig.{\fs18 6-17b;} when the
output goes LOW, the LED indicator lights.
64 Figure{\fs18 6-17c} and{\i \f10 \fs17 d} shows the CMOS ICs being op
erated on a higher supply voltage{\f10 \fs16 (+}{\fs18 10} to
6 {\fs18 +15} V). Because of the higher voltage, a{\b \fs19 1-kR} limi
ting resistor is placed in series with the LED
ut indicator lights. When the output{\fs18 of} the CMOS inverter shown in Fig
.{\fs18 6-17c} goes HIGH, the
output indicator lights. In Fig.{\fs18 6-17d,} however, the LED indicator is sh
own activated by a LOW
he CMOS output.
64 Figure{\fs18 6-17e} and{\i \f30 \fs21 f} shows CMOS buffers being used
to drive LED indicators. The circuits may
ate on voltages from{\i \fs19 +5} to{\f10 \fs29 +}{\fs19 15}{\fs18 V.} Figu
re{\fs18 6-17e} shows the use{\fs18 of} an inverting CMOS buffer (like
4049 IC), and Fig.{\fs18 6-17.f} uses the noninverting buffer (like th
e{\fs18 4050} IC). In both cases, a 1-kfl
\par}{\phpg\posx831\pvpg\posy1345\absw9141\absh5451 \sl-231 \f20 \fs18 \cf0 limi
ting resistor must be used in series with the LED output indicator.
68 Several simple circuits that interface a TTL with one or two LED i
ndicators are illustrated in
{\fs18 6-18.} TTL inverters are shown driving the LEDs directly in Fig.{\fs18
6-18a,}{\fs18 b,} and{\fs18 c.} The LED shown
\fi6538 {\fs15 +5}{\fs21 v }\par
}
po.
f10 \fs73 &}{\f10 \fs107 . }\par
}
\cf0 (a){\i0 \f20 \fs14 LED}{\i0 \f20 \fs14 lights}{\i0 \f20 \fs14 when}{\i0
\f20 \fs14 output}{\b\i0 \f20 \fs14 HIGH }
f0 \fi1461 {\i0 \f20 \fs15 +5}{\i0 \f20 \fs21 v }\par

}
80 \par
}
OW \par
}
IGH \par
}
L
\par
}
tput \par
}
\cf0 ( h ){\i0 \fs14 LED}{\i0 \fs14 lights}{\i0 \fs14 when}{\i0 \fs14 outpu
t}{\b\i0 \fs14 LOW }\par
}
\cf0 +ilV
{\b0\i \f30 \fs84 9% }\par
}
{\f20 \fs14
Output }\par
}
fs15 \cf0 ( d ){\b0\i0 \fs14 T'TL}{\b0\i0 \fs14 to}{\b0\i0 \fs14 LED}{\b0\i0
\fs14 interfacing}{\b0\i0 \fs14 using}{\b0\i0 \fs14 a}{\b0\i0 \fs14 driver}
{\b0\i0 \fs14 transistor }\par
}
reen \par
}
TL
t \par
}
(c){\fs14 HIGH}{\fs14 and}{\fs14 LOW}{\fs14 LED}{\fs14 indicators }\par
}
\cf0 Fig.{\f10 \fs15 6-18}{\b0 \fs16
TTL-to-LED}{\b0 \fs16 interfacing }\p
ar
}
.{\fs16 61 }\par
}
7 INTERFACING }\par
}

\par
}
\cf0 in Fig.{\fs18 6-18a} lights when the inverter's output is HIGH, but the LE
D shown in Fig. 6-18b lights when
2 the inverter's output is LOW. These ideas are combined to form the circuit sho
wn in{\b Fig.} 6-18c. When
2 the red LED lights, the output{\fs18 of} the inverter is HIGH, but w
hen the output of the inverter goes
0 LOW, the green LED will light.
60 The circuit shown in Fig. 6-18c has an additional feature. If the
output of the inverter were
een HIGH and LOW (in the undefined region), both LEDs would light. This
circuit therefore
\par}{\phpg\posx831\pvpg\posy1349\absw9186\absh3876 \sl-239 \f20 \fs18 \cf0 beco
mes{\fs19 a} simple logic indicator for checking logic levels at the o
utputs of logic circuits. Figure
d shows the use of a driver transistor to turn the LED on and off. When the ou
tput{\fs19 of} the TTL
rter goes LOW, the transistor is turned off and the LED does not light. When the
inverter output
HIGH, the transistor conducts and causes the LED to light. This circuit reduces
the output drive
\par}{\phpg\posx831\pvpg\posy1349\absw9186\absh3876 \sl-237 \f20 \fs18 \cf0 curr
ent from the TTL inverter.
\fi22 {\f10 \fs16 SOLVED}{\f10 \fs16 PROBLEMS }
2 {\b \fs18 6.36}
What is interfacing?
80 {\fs17 Interfacing}{\fs17 is}{\fs17 the}{\fs17 method}{\fs17 used}{\f
s17 to}{\fs17 interconnect}{\fs17 two}{\fs17 separate}{\fs17 electroni
c}{\fs17 devices}{\fs17 in}{\fs17 such}{\fs17 a}{\fs17 way}{\fs17 th
at }
18 {\fs17 their}{\fs17 output}{\fs17 and}{\fs17 input}{\fs17 voltages}{\
fs17 and}{\fs17 currents}{\fs17 are}{\fs17 compatible. }\par
}
f0 6.37 \par
}
how the interfacing of two TTL gates (an OR gate driving an AND gate).
\fs16 Solution: }
60 {\fs17 See}{\fs17 Fig.}{\fs17 6-19.}{\fs17 Note}{\fs17 that,}{\fs17
within}{\fs17 a}{\fs17 family}{\fs17 of}{\fs17
logic}{\fs17 ICs,}{\f
s17 a}{\fs17 direct}{\fs17 connection}{\fs17 can}{\fs17 usually}{\fs17
be}{\b \fs17 made }

17 between}{\fs17 the}{\fs17 output}{\fs17 of}{\fs17 one}{\fs17 gate}{
\fs17 and}{\fs17 the}{\fs17 input}{\fs17 of}{\fs17 the}{\fs17 next.
}\par
}
put \par
}
tput \par
}
\cf0 Fig. 6-19{\b0 \fs17
Solution}{\b0 \fs17 to}{\b0 \fs17 Prob,.}{\fs17 6.
37 }\par
}
\cf0 6.38{\b0 \fs18
Show}{\b0 \fs18 the}{\b0 \fs18 interfacing}{\b0 \fs18
of}{\b0 \fs18 a}{\fs19 CMOS}{\b0 \fs18 NAND}{\b0 \fs18 gate}{\b0 \fs18 dri
ving}{\b0 \fs18 a}{\b0 \fs18 low-power}{\b0 \fs18 Schottky}{\b0 \fs18 TTL}{\
b0 \fs19 OR}{\b0 \fs18 gate.}{\fs19 Use }
fi596 {\b0 \fs18 a}{\b0 \fs19 +5-V}{\b0 \fs18 power}{\b0 \fs18 supply. }
fi955 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 6-20.}{\b0 \fs17 By}{\b0 \fs1
7 using}{\b0 \fs17 Fig.}{\b0 \fs16 6-1%}{\b0 \fs17 as}{\b0 \fs17 a}{\b0 \fs
17 guide,}{\b0 \fs16 it}{\b0 \fs17 was}{\b0 \fs17 determined}{\b0 \fs17 th
at}{\b0 \fs17 the}{\b0 \fs17 output}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17
CMOS}{\b0 \fs17 gate}{\b0 \fs17 can }
fi596 {\b0 \fs17 drive}{\b0 \fs17 one}{\fs17 LS-TTL}{\b0 \fs17 load. }\par
}
nput \par
}
utput \par
}
\cf0 7 \par
}
\cf0 Fig.{\fs16 6-20}{\b0 \fs17
Solution}{\b0 \fs17 to}{\b0 \fs17 Prob.}{
\b0 \fs17 6.38 }\par
}
\par
}
7 INTERFACING }\par
}
AP. 6 \par
}
\cf0 6.39{\b0 \fs18

Show}{\b0 \fs18 the}{\b0 \fs18 interfacing}{\b0 of}{\
b0 \fs18 a}{\b0 \fs18 standard}{\b0 \fs19 TTL}{\b0 \fs19 OR}{\b0 \fs18 gate
}{\b0 \fs18 driving}{\b0 \fs18 a}{\b0 CMOS}{\b0 \fs18 inverter.}{\b0 \fs18
Use}{\b0 \fs18 a}{\b0 \fs19 +5-V}{\b0 \fs18 power }
fi597 {\b0 \fs18 supply. }
fi957 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 6-21.}{\b0 \fs16 By}{\b0 \f
s17 using}{\b0 \fs17 Fig.}{\fs17 6-150}{\b0 \fs17 as}{\b0 \fs17 a}{\b0
\fs17 guide,}{\b0 \fs16 it}{\b0 \fs17 was}{\b0 \fs17 determined}{\b0 \f
s17 that}{\b0 \fs17 a}{\fs17 l-kn}{\b0 \fs17 pull-up}{\b0 \fs17 resisto
r}{\b0 \fs17 was }
fi595 {\b0 \fs17 needed}{\b0 \fs17 to}{\b0 \fs17 help}{\b0 \fs17 pull}{\b0
\fs17 the}{\b0 \fs17 TTL}{\b0 \fs17 output}{\b0 \fs17 to}{\b0 \fs17 a}{\b
0 \fs17 HIGH}{\b0 \fs17 that}{\b0 \fs17 was}{\b0 \fs17 positive}{\b0 \fs17
enough}{\b0 \fs17 to}{\b0 \fs17 have}{\b0 \fs17 the}{\b0 \fs17 CMOS}{\b0
\fs17 input}{\b0 \fs17 accept }
fi596 {\fs16 it}{\b0 \fs17 as}{\b0 \fs17 a}{\b0 \fs17 logical}{\b0 \fs17
1. }
f0 \fi4456 {\f10 \fs14 +5}{\b0 \fs21 v }\par
}
1 \cf0 4
{\b \fs17 Fig.}{\b \fs17 6-21}{\fs17
Solution}{\fs17 to}{\fs17 Prob.}{\fs1
7 6.39 }\par
}
f0 6.40 \par
}
how the interfacing of a standard TTL{\b \f30 \fs20 AND} gate (using{\f
s19 +5-V} supply) driving a{\fs19 CMOS }\par
}
nverter (using a{\f10 \fs29 + }
}
0-V supply). \par
}
\f10 \fs15 \cf0 An{\b0\i0 \f20 \fs17 interface}{\b0\i0 \f20 \fs17 circuit}{\
b0\i0 \f20 \fs17 using}{\b0\i0 \f20 \fs17 a}{\b0\i0 \f20 \fs17 driver}{\b0\i0
\f20 \fs17 transistor}{\b0\i0 \f20 \fs17 is}{\b0\i0 \f20 \fs17 shown}{\b0\i
0 \f20 \fs17 in}{\b0\i0 \f20 \fs17 Fig.}{\b0\i0 \f20 \fs17 6-22.}{\b0\i0 \f20
\fs17 An}{\b0\i0 \f20 \fs17 open-collector}{\b0\i0 \f20 \fs17 TI'L}{\b0\i0
\f20 \fs17 buffer}{\b0\i0 \f20 \fs17 and }
0 {\b0\i0 \f20 \fs17 pull-up}{\b0\i0 \f20 \fs17 resistor}{\b0\i0 \f20 \fs17
could}{\b0\i0 \f20 \fs17 also}{\b0\i0 \f20 \fs17 be}{\b0\i0 \f20 \fs17 used
}{\b0\i0 \f20 \fs17 as}{\b0\i0 \f20 \fs17 in}{\b0\i0 \f20 \fs17 the}{\b0\i
0 \f20 \fs17 circuit}{\b0\i0 \f20 \fs17 shown}{\b0\i0 \f20 \fs17 in}{\b0\i0
\f20 \fs17 Fig.}{\b0\i0 \f20 \fs17 6-16b. }

\cf0 \fi4344 {\b0\i0 \fs14 +10}{\b0\i0 \f20 \fs22 v }
\cf0 \fi2394 {\i0 \fs14 +5}{\b0\i0 \f20 \fs22 v }\par
}
cf0 vcc \par
}
tput \par
}
ND \par
}
35 \cf0 -\par}{\phpg\posx4171\pvpg\posy10744\absw2854\absh711 \sl-191 \par\f10 \fs35 \cf0
{\b \f20 \fs17 Fig.}{\b \f20 \fs16 6-22}{\f20 \fs17
One}{\f20 \fs17 soluti
on}{\f20 \fs17 to}{\f20 \fs17 Prob.}{\f20 \fs17 6.40 }\par
}
\cf0 A \par
}
cf0 6.41 \par
}
Show a{\fs19 TTL}{\b \f30 \fs20 NAND} gate driving an LED output indi
cator{\fs19 so} the LED goes on when the
\par}{\phpg\posx1485\pvpg\posy12387\absw8286\absh1170 \sl-232 \f20 \fs18 \cf0 ou
tput{\fs19 of} the{\fs19 NAND} gate goes{\fs19 HIGH. }
b \fs17 Solution: }
i368 {\fs17 See}{\fs17 Fig.}{\fs17 6-23.}{\fs17 When}{\fs17 the}{\fs17 ou
tput}{\fs16 of}{\fs17 the}{\fs17 NAND}{\fs17 gate}{\fs17 goes}{\fs17 H
IGH,}{\fs17 the}{\fs17 LED}{\fs17 is}{\fs17 forward-biased,}{\fs17 curr
ent }
fs17 flows,}{\fs17 and}{\fs17 the}{\fs17 LED}{\fs17 lights. }\par
}
.{\fs16 61 }\par
}
L{\fs17 AND}{\fs17 CMOS}{\b \fs17 ICs:}{\fs17 CHARACTERISTICSAND}{\fs17 INT
ERFACING }\par
}
\par
}
cf0 output
\par}{\phpg\posx5407\pvpg\posy1394\absw655\absh325 \sl-171 \f20 \fs15 \cf0 indic
ator \par
}
cf0 HIGH \par
}
\par
}
\cf0 Fig.{\f30 \fs17 6-23}{\b0 \fs17 Solution}{\b0 \fs17 to}{\b0 \fs17 Prob
.}{\b0 \fs17 6.41 }\par
}
efer to Fig.{\i \fs19 6-18c.} If the output of the inverter drops ne
ar ground potential, the \par
}
green, red) LED lights to indicate a
}
HIGH,{\fs18 LOW)}{\fs18 logic}{\fs18 level. }\par
}
f0 6.42 \par
}
hen the{\fs16 output} of the inverter shown in{\fs16 Fig.} 6-18c is
near GND or{\fs17 LOW,} the green LED lights. \par
}
f0 6.43 \par
}
how the interfacing for a CMOS NAND gate directly driving an LED{\fs19 so} the
indicator lights \par
}
{\phpg\posx1455\pvpg\posy6094\absw3702\absh849 \f20 \fs18 \cf0 \f20 \fs18 \cf0 w
hen the gate output is{\fs19 HIGH.} Use a{\f10 \fs27 + }
\fs16 Solution: }
68 {\i \fs17 See}{\fs17 Fig.}{\fs17 6-24. }\par
}
0-V power supply. \par
}
0{\f20 \fs22 v }\par
}
tput \par
}
\b \f20 \fs15 kS2 }\par
}
\cf0 Fig.{\f10 \fs15 6-24}{\b0 \fs17
Solution}{\b0 \fs17 to}{\b0 \fs17 Pro
b.}{\fs17 6.43 }\par
}
\cf0 6-6{\fs18
INTERFACING}{\fs18 'ITL} AND{\fs18 CMOS}{\fs19 WITH}{\fs19
SWITCHES }

\fi356 {\fs18 A}{\b0 \fs18 common}{\b0 \fs18 method}{\b0 \fs18 of}{\b0 \fs
18 entering}{\b0 \fs18 information}{\b0 \fs18 into}{\b0 \fs18 a}{\b0 \fs
18 digital}{\b0 \fs18 system}{\b0 \fs18 is}{\b0 \fs18 by}{\b0 \fs18 wa
y}{\b0 \fs18 of}{\b0 \fs18 switches}{\b0 \fs19 (or }
{\b0 \fs18 keyboards).}{\b0 \fs18 This}{\b0 \fs18 section}{\b0 \fs18 details}
{\b0 \fs18 several}{\b0 \fs18 methods}{\b0 \fs19 of}{\b0 \fs18 interfacing}
{\b0 \fs18 a}{\b0 \fs18 switch}{\b0 \fs19 to}{\b0 \fs18 either}{\b0 \fs18 T
TL}{\b0 \fs18 or}{\fs19 CMOS}{\b0 \fs19 ICs. }
\fi360 {\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 simple}{\b0 \fs18 swi
tch}{\b0 \fs18 interface}{\b0 \fs18 circuit}{\b0 \fs18 drawn}{\b0 \fs18 i
n}{\b0 \fs18 Fig.}{\b0\i \fs19 6-25a.}{\b0 \fs18 When}{\b0 \fs18 the}{\b0
\fs18 switch}{\b0 \fs18 is}{\b0 \fs18 open}{\b0 \fs18 (not }
{\b0 \fs18 pressed),}{\b0 \fs18 the}{\b0 \fs18 input}{\b0 \fs18 to}{\b0 \f
s18 the}{\b0 \fs18 TTL}{\b0 \fs18 inverter}{\b0 \fs18 is}{\b0 \fs18 co
nnected}{\b0 \fs18 directly}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 posi
tive}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 power}{\b0 \fs18 supply }
{\b0 \fs18 through}{\b0 \fs18 the}{\fs19 10-kfl}{\b0 \fs18 pull-up}{\b0 \fs
18 resistor;}{\b0 \fs18 the}{\b0 \fs18 switch}{\b0 \fs18 input}{\b0 \fs18 i
s}{\b0 \fs19 HIGH}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs19 6-25a}{\b0 \fs
18 when}{\b0 \fs18 the}{\b0 \fs18 switch}{\b0 \fs18 is}{\b0 \fs18 open. }
{\b0 \fs18 Pressing}{\b0 \fs18 the}{\b0 \fs18 normally}{\b0 \fs18 open}{\b0 \
fs18 switch}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs19 6-251}{\b0 \fs18 gro
unds}{\b0 \fs18 the}{\b0 \fs18 TTL}{\b0 \fs18 input,}{\b0 \fs18 driving}{\b0
\fs18 it}{\b0 \fs18 LOW.}{\b0 \fs18 The}{\b0 \fs18 circuit}{\b0 \fs18 in }
{\b0 \fs18 Fig.}{\b0\i \fs19 6-25a}{\b0 \fs18 might}{\b0 \fs18 be}{\b0 \fs18
called}{\b0 \fs18 an}{\b0\i \fs19 active-LOW}{\b0 \fs18 switch}{\b0 \fs1
8 interface}{\b0 \fs18 because}{\b0 \fs18 the}{\b0 \fs18 TTL}{\b0 \fs18 in
put}{\b0 \fs18 goes}{\b0 \fs18 LOW}{\b0 \fs18 when }
{\b0 \fs18 the}{\b0 \fs18 switch}{\b0 \fs18 is}{\b0 \fs18 activated. }\par
}
0 126 \par
}
L{\fs17 AND}{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICS}{\fs17
AND}{\b \fs17 INTERFACING }\par
}
}
cf0 +5{\i0 \fs21 v }\par
}
cf0 +5{\i0 \fs21 v }\par
}
s12 \cf0 (a){\i0 \f20 \fs15 Simple}{\i0 \f20 \fs15 active-LOW}{\i0 \f20 \fs15
switch}{\i0 \f20 \fs15 interface }
\cf0 \fi1713 {\b0\dn006 \f20 \fs15 +5}{\b0\i0 \f20 \fs22 v }\par

}
s15 \cf0 (b){\i0 \fs15 Simple}{\i0 \fs15 active-HIGH}{\i0 \fs15 switch}{\i0 \
fs15 interface }
\cf0 \fi68 {\i0 \fs16 Fig.}{\i0 \fs16 6-25}{\i0 \fs16
Switch-to-TTL}{\i0 \fs
16 interfaces }\par
}
\cf0 An{\i \fs18 active-HIGH} input switch is diagrammed in Fig.{\i \fs18 6
-25b.} When the switch is activated (pressed),
\i \fs19
+5}{\b \fs19 V} is connected directly to the input of the
TTL inverter. When the switch is released
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-246 \f20 \fs18 \cf0 (ope
ned), the inverter input is pulled LOW by the 330-52 pull-down resistor.
74 Two simple switch-to-CMOS interface circuits are detailed in Fig.{\i \
fs18 6-26.} An active-LOW input
ch is drawn in Fig.{\i \fs18 6-26a.} The{\b \fs19 lOO-kil} pull-up resistor
pulls the voltage to{\i \fs19 +5}{\b V} when the input
ch is open. The CMOS inverter input goes LOW when the normally open
switch is closed in
{\i \fs18 6-26a. }
70 An active-HIGH input switch is shown in Fig.{\i \fs18 6-266.} The
CMOS inverter input is LOW
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-246 \f20 \fs18 \cf0 (con
nected through the pull-down resistor) when the switch is open. When
the switch is closed
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-235 \f20 \fs18 \cf0 (pre
ssed) in Fig.{\i \fs18 6-26b,} the input of the inverter is driven HIGH.
73 Consider the circuit in Fig.{\i \fs18 6-27a.} Each press and release
of the input switch should cause the
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-232 \f20 \fs18 \cf0 coun
ter to increment by{\b \fs18 1.} Unfortunately the counter increases by
1,{\i \fs18 2,}{\fs18 3,} or sometimes more. This
lem is caused by{\i \fs18 switch}{\i \fs18 bounce.} When a mechanical swit
ch closes or opens, the contacts do not
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-230 \f20 \fs18 \cf0 make
or break the circuit cleanly, generating several short voltage spikes
. This means that several
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-244 \f20 \fs18 \cf0 (ins
tead of one) pulses are fed into the clock (CLK) input of{\fs17 the} counter
IC on each switch closure.
68 The counting circuit in Fig.{\i \fs18 6-27a} needs extra circuitry to
eliminate the switch bounce problem.
\fs18 Switching}{\i \fs18 debouncing} circuitry has been added to the count
er circuit in Fig.{\i \fs18 6-27b.} The TTL decade
18 (0} to{\b \fs18 9)} counter IC will now count (increment by only{\f10 \fs1
7 1)} on each HIGH-to-LOW cycle of the input

ch. The cross-wired{\b NAND} gates in the debouncing circuit are sometimes refe
rred to as a{\i \fs18 latch} or
\fs18 RSJEip-Pop.}Flip-flops are covered in greater detail in Chap.{\fs17 9.
}
68 Two other general-purpose switch debouncing circuits are diagrammed in Fig.{\
i \fs18 6-28.} The debounc\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-232 \f20 \fs18 \cf0 ing
circuit in Fig.{\i \fs18 6-28a} will drive any 4000 series, 74C00 series, or 74
HC00 series CMOS or TTL ICs.
\par}{\phpg\posx845\pvpg\posy8575\absw9321\absh4895 \sl-235 \f20 \fs18 \cf0 Anot
her debouncing circuit is drawn in Fig.{\i \fs18 6-28b.} This circuit uses
{\i \fs18 open-collector} 7403 TTL ICs in \par
}
. 61 \par
}
L AND CMOS ICs: CHARACTERISTICSAND INTERFACING \par
}
\par
}
\cf0 (a){\i0 \f20 \fs15 Simple}{\i0 \f20 \fs15 active-LOW}{\i0 \f20 \fs15 sw
itch}{\i0 \f20 \fs15 interface }\par
}
cf0 +5{\i0 \fs22 v }
0 \fi337 {\i0 \fs15 Input }\par
}
cf0 +5{\i0 \fs21 v }\par
}
tput \par
}
0 kfl \par
}
\fs15 \cf0 (b){\i0 Simple}{\i0 active-HIGH}{\i0 switch}{\i0 interface }
cf0 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 6-26}{\i0 \fs17
Switch-to-CMOSinterfaces
}
cf0 \fi378 {\fs16 +5}{\i0 \fs21 v }
\fi1314 {\i0 Decade }\par
}
unter \par
}
tput \par
}
put \par
}
\cf0 (a){\i0 \f20 \fs15 Switch}{\i0 \f20 \fs15 interfacing}{\i0 \f20 \fs15
with}{\i0 \f20 \fs15 decimal}{\i0 \f20 \fs15 counter}{\i0 \f20 \fs15 causes}{
\i0 \f20 \fs15 problems }\par
}
fs15 \cf0 (b){\b0\i0 \fs15 Added}{\b0\i0 \fs15 switch}{\b0\i0 \fs15 debouncin
g}{\b0\i0 \fs15 circuit}{\b0\i0 \fs15 makes}{\b0\i0 \fs15 counter}{\b0\i0 \f
s15 work}{\b0\i0 \fs15 properly }
\cf0 \fi1722 {\i0 \fs16 Fig.}{\i0 \fs16 6-27 }\par
}
0 128 \par
}
6 INTERFACING }\par
}
}
14 \cf0 + 5{\b0\i0 \f20 \fs22 v }\par
}
utput
15 To}{\fs15 4000} series{\fs15 CMOS} or
52 {\fs15 74HC00} series{\fs15 CMOS}{\fs15 or }
52 {\fs15 7400}{\b \f30 \fs17 TTL, }\par
}
s13 \cf0 (a){\b0\i0 \f20 \fs16 Using}{\b0\i0 \f20 \fs15 a}{\b0\i0 \f20 \fs15
74HC00}{\b0\i0 \f20 \fs15 CMOS}{\b0\i0 \f20 \fs14 NAND}{\b0\i0 \f20 \fs16 gat
e }
\cf0 \fi2477 {\b0 \f20 \fs15 +5}{\b0\i0 \f20 \fs22 v }\par
}
}
put \par
}
1 \par
}
13 \cf0 0 \par
}
utput
15 To}{\fs15 4000} series{\fs15 CMOS} or
53 {\fs15 74HC00} series{\fs15 CMOS}{\fs15 or }
58 {\fs15 7400} series{\fs15 TTL }\par
}
0 \fs14 \cf0 (b){\i0 \f20 \fs16 Using}{\i0 \f20 \fs15 a}{\i0 \f20 \fs15 7403}
{\i0 \f20 \fs16 open-collector}{\i0 \f20 \fs15 TTL}{\i0 \f20 \fs16 gate }
f0 \fi2318 {\b\i0 \f20 \fs16 Fig.}{\b\i0 \f20 \fs17 6-28}{\i0 \f20 \fs16
Gen
eral-purpose}{\i0 \f20 \fs16 switch}{\i0 \f20 \fs16 debouncing}{\i0 \f20 \fs
16 circuits }
f0 {\i0 \f20 \fs18 the}{\i0 \f20 \fs18 latch}{\i0 \f20 \fs18 with}{\i0 \f20
\fs18 the}{\i0 \f20 \fs18 required}{\i0 \f20 \fs18
pull-up}{\i0 \f20 \fs1
8 resistors}{\i0 \f20 \fs18 at}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18 outpu
ts}{\i0 \f20 \fs18 of}{\i0 \f20 \fs18
each}{\b\i0 \f20 \fs18 NAND}{\i0 \f
20 \fs18 gate.}{\i0 \f20 \fs18 The}{\i0 \f20 \fs18 switch }
\i0 \f20 \fs18 debouncing}{\i0 \f20 \fs18 circuit}{\i0 \f20 \fs18 in}{\i0 \f
20 \fs18 Fig.}{\f20 \fs18 6-28b}{\i0 \f20 \fs18 will}{\i0 \f20 \fs18 dri
ve}{\i0 \f20 \fs18 4000}{\i0 \f20 \fs18 series,}{\i0 \f20 \fs18 74COO}{\i0
\f20 \fs18 series,}{\i0 \f20 \fs18 or}{\i0 \f20 \fs18 74HC00}{\i0 \f20 \fs
18 series}{\i0 \f20 \fs18 CMOS}{\i0 \f20 \fs18 or }
\i0 \f20 \fs19 TTL}{\b\i0 \f20 \fs18 ICS. }\par
}
\cf0 SOLVED{\b0 PROBLEMS }\par
}
cf0 6.44 \par
}
Refer to Fig.{\i \f10 \fs17 6-25a.} Component{\b\i \fs18 S}{\b\i \fs18 ,} i
s considered an active\par}{\phpg\posx1469\pvpg\posy10553\absw5757\absh732 \sl-227 \f20 \fs18 \cf0 bec
ause closing the switch causes the input{\fs18 of} the inverter to go
}
(HIGH,{\fs18 LOW)}{\fs18 input}{\fs18 switch }
561 (HIGH,{\fs18 LOW). }\par
}
6 \cf0 In Fig.{\i \fs16 6.25a,}{\b \f10 \fs15 S,} is an active-LOW input
switch because closing{\b \f30 \fs18 S,}causes the input of the inverter
to
\par}{\phpg\posx1465\pvpg\posy11423\absw8247\absh390 \sl-213 \f20 \fs16 \cf0 go{
\fs16 LOW. }\par
}
cf0 6.45 \par
}
Refer to Fig.{\i 6-2%.} The{\fs18 33042} resistor{\fs18 is} called a pull\par

}
the input{\fs18 of} the inverter
}
(down, up) resistor as it holds \par
}
(HIGH,{\fs18 LOW)} when the input switch is open (not pressed). \par
}
0 \fs17 \cf0 In{\b0 \fs16 Fig.}{\b0\i \fs16 6-25b}{\b0 \fs16 the}{\b0 \fs1
6 resistor}{\b0 \fs16 is}{\b0 \fs16 called}{\b0 \fs16 a}{\b0 \fs16 pul
l-down}{\b0 \fs16 resistor}{\b0 \fs16 as}{\b0 \fs16 it}{\b0 \fs16 holds}
{\b0 \fs16 the}{\b0 \fs16 input}{\b0 \fs16 of}{\b0 \fs16 the}{\b0 \fs16
inverter}{\b0 \fs16 LOW }
{\b0 \fs16 when}{\b0 \fs16 the}{\b0 \fs16 input}{\b0 \fs16 switch}{\b0 \fs
16 is}{\b0 \fs16 open. }\par
}
.{\b \fs16 61 }\par
}
{\phpg\posx2535\pvpg\posy538\absw5476\absh198 \f20 \fs17 \cf0 \f20 \fs17 \cf0 ?T
L{\fs17 AND}{\fs17 CMOS}{\fs17 ICs:}{\fs17 CHARACTERISTICS}{\fs17 AND}{\fs
17 INTERFACING }\par
}
\par
}
cf0 6.46{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0\i \f10 \fs17
6-27(a).}{\b0 \fs18 The}{\b0 \fs18 counter}{\b0 \fs18 IC}{\b0 \fs18 does}{\b
0 \fs18 not}{\b0 \fs18 accurately}{\b0 \fs18 count}{\b0 \fs18 the}{\b0 \fs18
number}{\b0 \fs19 of}{\b0 \fs18 times}{\b0 \fs18 the}{\b0 \fs18 input }\pa
r
}
witch is pressed because of a problem called switch
}
bounce, hysteresis). \par
}
\cf0 In Fig.{\b\i \fs17 6-27(a),}the counter does not accuratelycount the num
ber of times the input switch is pressed
use of a problem called switch bounce. \par
}
f0 6.47 \par
}

witch debouncing circuits are typically
57 {\fs17 Switch}{\fs17 debouncing}{\fs17 circuits}{\fs17 are}{\fs17 typical
ly}{\fs17 latches. }\par
}
latches, multiplexers). \par
}
f0 6.48 \par
}
efer to Fig.{\b\i \fs19 6-28b.} The{\fs19 7403}{\fs19 TTL}{\b \fs19 NAN
D} gates have
uts which require pull-up resistors at the gate outputs.
}
open-collector, totem pole) \par
}
\cf0 The{\b \fs17 7403}{\fs17 TTL} NAND gates have open-collector outputs
which require pull-up resistors at the gate
uts. \par
}
\cf0 6-7{\fs18
INTEKFACING}{\fs18 TTL/CMOS}{\fs18 WITH}{\fs18 SIMPLE}{\fs
18 OUTPUT}{\fs18 DEVICES }
fi366 {\b0 \fs18 The}{\b0 \fs18 task}{\b0 \fs18 of}{\b0 \fs18 many}{\b0 \fs18
digital}{\b0 \fs18 systems}{\b0 \fs18 is}{\b0 \fs18 to}{\b0 \fs18 control}
{\b0 \fs18 simple}{\b0 \fs18 output}{\b0 \fs18 devices}{\b0 \fs18 that}{\b0
\fs18 may}{\b0 \fs18 have}{\b0 \fs18 very}{\b0 \fs18 different }
\b0 \fs18 voltage}{\b0 \fs18 and}{\b0 \fs18 current}{\b0 \fs18 characteris
tics.}{\b0 \fs18 This}{\b0 \fs18 section}{\b0 \fs18 explores}{\b0 \fs18
simple}{\b0 \fs18 interface}{\b0 \fs18 techniques}{\b0 \fs18 with}{\b0 \fs
18 logic }
\b0 \fs18 elements}{\b0 \fs18 driving}{\b0 \fs18 buzzers,}{\b0 \fs18 relays,}
{\b0 \fs18 electric}{\b0 \fs18 motors,}{\b0 \fs18 and}{\b0 \fs18 solenoids.
}
fi371 {\b0 \fs18 Most}{\b0 \fs18 logic}{\b0 \fs18 families}{\b0 \fs18 do}{\b
0 \fs18 not}{\b0 \fs18 have}{\b0 \fs18 the}{\b0 \fs18 current}{\b0 \fs18 c
apabilities}{\b0 \fs18 to}{\b0 \fs18 drive}{\b0 \fs18 output}{\b0 \fs18 devi
ces}{\b0 \fs18 directly.}{\b0 \fs18 Using}{\b0 \fs18 a }
\b0 \fs18 logic}{\b0 \fs18 element}{\b0 \fs18 to}{\b0 \fs18 turn}{\b0 \fs1
8 on}{\b0 \fs18 a}{\b0 \fs18 transistor}{\b0 \fs18 is}{\b0 \fs18 a}{\b
0 \fs18 common}{\b0 \fs18 interface}{\b0 \fs18 technique.}{\b0 \fs18
Co
nsider}{\b0 \fs18 the}{\b0 \fs18 circuit}{\b0 \fs18 in }
\b0 \fs18 Fig.}{\b0 6-29.}{\b0 \fs18 This}{\b0 \fs18 circuit}{\b0 \fs18 uses
}{\b0 \fs18 the}{\b0 \fs18 NPN}{\b0 \fs18 transistor}{\b0 \fs18 as}{\b0 \fs
18 a}{\b0 \fs18 switch.}{\b0 \fs18 When}{\b0 \fs18 the}{\b0 \fs18 output}{\
b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 inverter}{\b0 \fs18 goes}{\fs19 LOW,
}
\b0 \fs18 the}{\b0 \fs18 voltage}{\b0 \fs18 between}{\b0 \fs18 the}{\b0 \fs1
8 base}{\i \fs19 (}{\i \fs19 B}{\i \fs19 )}{\b0 \fs18 and}{\b0 \fs18 emi
tter}{\i \fs19 (}{\i \fs19 E}{\i \fs19 )}{\b0 \fs18 of}{\b0 \fs18 the}{\b
0 \fs18 bipolar}{\b0 \fs18 transistor}{\b0 \fs19 is}{\b0 \fs18 near}{\b0\i
\fs19 0.}{\b0 \fs18 This}{\b0 \fs18 turns}{\b0 \fs18 the }
\b0 \fs18 transistor}{\b0 \fs19 off}{\b0 \fs18 (very}{\b0 \fs18 high}{\b0 \fs
18 resistance}{\b0 \fs18 between}{\b0\i \fs18 E}{\b0 \fs18 and}{\b0 \fs19
C}{\b0 \fs18 terminals),}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 buzzer}{\
b0 \fs18 does}{\b0 \fs18 not}{\b0 \fs18 sound.}{\b0 \fs18 When }
\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 inve
rter}{\b0 \fs18 goes}{\b0 \fs18 HIGH,}{\b0 \fs18 the}{\b0 \fs18 positive}{\b
0 \fs18 voltage}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 base}{\i \fs19 (}{
\i \fs19 B}{\i \fs19 )}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 transistor}{\
b0 \fs18 turns}{\b0 \fs18 on }
\b0 \fs18 the}{\b0 \fs18 transistor}{\b0 \fs18 (resistance}{\b0 \fs18 betw
een}{\b0\i \fs19 E}{\b0 \fs18 and}{\b0 \fs19 C}{\b0 \fs18 terminals}{\b0
\fs18 becomes}{\b0 \fs18 very}{\b0 \fs18 low),}{\b0 \fs18 allowing}{\b0
\fs18 current}{\b0 \fs18 to}{\b0 \fs18 flow }
\b0 \fs18 through}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 buzzer}{\b0 \fs18
(buzzer}{\b0 \fs18 sounds).}{\b0 \fs18 The}{\b0 \fs18 diode}{\b0 \fs18 pr
otects}{\b0 \fs18 against}{\b0 \fs18 transient}{\b0 \fs18 voltages}{\b0 \fs1
8 (voltage}{\b0 \fs18 spikes }
\b0 \fs18 that}{\b0 \fs18 may}{\b0 \fs18 be}{\b0 \fs18 produced}{\b0 \fs18 w
ithin}{\b0 \fs18 the}{\b0 \fs18 buzzer).}{\b0 \fs18 Notice}{\b0 \fs18 that}{
\b0 \fs18 the}{\b0 \fs18 interface}{\b0 \fs18 circuit}{\b0 \fs18 will}{\b0 \
fs18 work}{\b0 \fs18 with}{\b0 \fs18 either}{\b0 \fs19 TTL}{\b0 \fs18 or }
\b0 \fs18 CMOS}{\b0 \fs18 logic}{\b0 \fs18 elements. }
f0 \fi5364 {\b0\i \fs16 +5}{\b0 \fs21 v }\par
}
f0 RAJ \par
}
\cf0 buzzer{\fs15
Output }\par
}
\cf0 Fig. 6-29{\b0 \fs17
TTL}{\b0 \fs17 or}{\b0 \fs17 CMOS}{\b0 \fs17 int
erfaced}{\b0 \fs17 with}{\b0 \fs17 buzzer}{\b0 \fs17 using}{\b0 \fs17 a}{\b0
\fs17 transistor}{\b0 \fs17 driver }\par
}
\cf0 Input \par
}
\par
}

L AND{\b CMOS}{\b ICs:}{\b CHARACTERISTICS} AND{\b INTERFACING }\par
}
f0 [CHAP. 6 \par
}
\fs19 \cf0 A{\b0 \fs18 relay}{\b0 \fs18 is}{\b0 \fs18 an}{\b0 \fs18 exc
ellent}{\b0 \fs18 means}{\b0 \fs19 of}{\b0 \fs18 isolating}{\b0 \fs18 a}
{\b0 \fs18 logic}{\b0 \fs18 element}{\b0 \fs18 from}{\b0 \fs18 a}{\b0 \fs
18 high-voltage}{\b0 \fs18 or}{\b0 \fs18 high-current }
\b0 \fs18 circuit.}{\b0 \fs18 Figure}{\b0\i \fs19 6-30}{\b0 \fs18 illustrate
s}{\b0 \fs18 how}{\b0 \fs18 a}{\b0 \fs18 logic}{\b0 \fs18 element}{\b0 \fs
18 could}{\b0 \fs18 be}{\b0 \fs18 used}{\b0 \fs18 with}{\b0 \fs18 a}{\
b0 \fs18 relay}{\b0 \fs18 to}{\b0 \fs18 control}{\b0 \fs18 an}{\b0 \fs18
electric }
\b0 \fs18 motor}{\b0 \fs18 or}{\b0 \fs18 solenoid. }
f0 \fi4330 {\b0 \f10 \fs19 +s}{\b0 \fs21 v }\par
}
L
{\fs15 or }\par
}
cf0 2N3904 \par
}
cf0 Input{\b0 \f10 \fs23 - }\par
}
32 \cf0 +
{\b\i \fs13 (a)}{\b \f20 \fs15 Interfacing}{\f20 \fs16 TTL}{\f20 \fs15 or}{\
b \f20 \fs15 CMOS}{\b \f20 \fs15 with}{\b \f20 \fs15 an}{\b \f20 \fs15 elect
ric}{\b \f20 \fs15 motor }
\fi1601 {\fs19 +s}{\f20 \fs21 v }
\cf0 \fi1105 {\fs27 -}{\b\dn006 \f20 \fs19 AI }
\cf0 \fi985 {\b \f20 \fs15 2N3904 }\par
}
cf0 Input{\b0 \f10 \fs19 - }\par
}
}
cf0 Solenoid \par
}
\f20 \fs15 \cf0 (b){\i0 \fs15 Interfacing}{\i0 \fs15 'ITL}{\b0\i0 \fs15 or}{
\i0 \fs15 CMOS}{\i0 \fs15 with}{\i0 \fs15 a}{\i0 \fs15 solenoid }
\cf0 \fi3092 {\i0 \fs16 Fig.}{\i0 \fs16 6-30}{\i0 \fs16
Interfacing}{\i0 \fs
16 using}{\i0 \fs16 a}{\i0 \fs16 relay }

\cf0 \fi368 {\b0\i0 \fs18 Consider}{\b0\i0 \fs18 the}{\b0\i0 \fs18 interface}{
\b0\i0 \fs18 circuit}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0 \fs19 6-30a.}{
\b0\i0 \fs18 The}{\b0\i0 \fs18 same}{\b0\i0 \fs18 NPN}{\b0\i0 \fs18 transist
or}{\b0\i0 \fs18 driver}{\b0\i0 \fs18 employed}{\b0\i0 \fs18 previously }
{\b0\i0 \fs18 is}{\b0\i0 \fs18 used}{\b0\i0 \fs18 to}{\b0\i0 \fs18 snap}{\
b0\i0 \fs18 the}{\b0\i0 \fs18 relay}{\b0\i0 \fs18 contacts}{\b0\i0 \fs18 c
losed}{\b0\i0 \fs18 and}{\b0\i0 \fs18 open.}{\b0\i0 \fs18 When}{\b0\i0 \fs
18 the}{\b0\i0 \fs18 output}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \
fs18 inverter}{\b0\i0 \fs18 is}{\b0\i0 \fs18 LOW,}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 transistor}{\b0\i0 \fs18 is}{\b0\i0 \fs18 turned}{\b0\i0 \fs19
off}{\b0\i0 \fs18 and}{\b0\i0 \fs18 no}{\b0\i0 \fs18 current}{\b0\i0 \fs18
flows}{\b0\i0 \fs18 through}{\b0\i0 \fs18 the}{\b0\i0 \fs18 coil}{\b0\i0 \fs1
8 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 relay.}{\b0\i0 \fs18 The}{\b0\i0 \fs18
spring-loaded}{\b0\i0 \fs18 normally }
{\b0\i0 \fs18 closed}{\b0\i0 \fs18 (NC)}{\b0\i0 \fs18 relay}{\b0\i0 \fs18 co
ntacts}{\b0\i0 \fs18 are}{\b0\i0 \fs18 held}{\b0\i0 \fs18 closed}{\b0\i0 \fs1
8 as}{\b0\i0 \fs18 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 the}{\b0\i0 \fs18 s
chematic}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0 \fs19 6-30a.}{\b0\i0 \fs18
When}{\b0\i0 \fs18 the}{\b0\i0 \fs18 output }
{\b0\i0 \fs19 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 inverter}{\b0\i0 \fs18 goes
}{\b0\i0 \fs19 HIGH,}{\b0\i0 \fs18 the}{\b0\i0 \fs18 transistor}{\b0\i0 \fs18
turns}{\b0\i0 \fs18 on}{\b0\i0 \fs18 (conducts)}{\b0\i0 \fs18 and}{\b0\i0 \
fs18 current}{\b0\i0 \fs18 flows}{\b0\i0 \fs18 through}{\b0\i0 \fs18 the}{\b
0\i0 \fs18 coil}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the }
{\b0\i0 \fs18 relay.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 magnetic}{\b0\i0 \fs18
force}{\b0\i0 \fs18 from}{\b0\i0 \fs18 the}{\b0\i0 \fs18 energized}{\b0\i0 \f
s18 relay}{\b0\i0 \fs18 coil}{\b0\i0 \fs18 attracts}{\b0\i0 \fs18 the}{\b0
\i0 \fs18 armature}{\b0\i0 \fs18 (moving}{\b0\i0 \fs18 part}{\b0\i0 \fs18 o
f}{\b0\i0 \fs18 relay), }
{\b0\i0 \fs18 and}{\b0\i0 \fs18 the}{\b0\i0 \fs18 normally}{\b0\i0 \fs18 op
en}{\b0\i0 \fs18 (NO)}{\b0\i0 \fs18 contacts}{\b0\i0 \fs18 close.}{\b0\i0 \fs
18 The}{\b0\i0 \fs18 NO}{\b0\i0 \fs18 relay}{\b0\i0 \fs18 contacts}{\b0\i0
\fs18 function}{\b0\i0 \fs18 as}{\b0\i0 \fs18 a}{\b0\i0 \fs18 simple}{\b0\
i0 \fs18 mechanical }
{\b0\i0 \fs18 switch}{\b0\i0 \fs18 which}{\b0\i0 \fs18 turns}{\b0\i0 \fs18 o
n}{\b0\i0 \fs18 the}{\b0\i0 \fs18 higher-voltage}{\b0\i0 \fs18 electric}{\b0\
i0 \fs18 motor.}{\b0\i0 \fs18 The}{\b0 \fs19 clamp}{\f30 \fs19 diode}{\b0\i0
\fs18 across}{\b0\i0 \fs18 the}{\b0\i0 \fs18 relay}{\b0\i0 \fs18 coil}{\b0\
i0 \fs18 prevents }
{\b0\i0 \fs18 voltage}{\b0\i0 \fs18 spikes}{\b0\i0 \fs18 which}{\b0\i0 \fs18
might}{\b0\i0 \fs18 be}{\b0\i0 \fs18 induced}{\b0\i0 \fs18 in}{\b0\i0 \fs18
the}{\b0\i0 \fs18 system}{\b0\i0 \fs18 by}{\b0\i0 \fs18 the}{\b0\i0 \fs18 r
elay}{\b0\i0 \fs18 coil.}{\b0\i0 \fs18 Notice}{\b0\i0 \fs18 in}{\b0\i0 \fs18
Fig.}{\b0 \fs19 6-30a}{\b0\i0 \fs18 that}{\b0\i0 \fs18 either }
{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 or}{\i0 \fs19 CMOS}{\b0\i0 \fs18 logic}{\b0\
i0 \fs18 circuits}{\b0\i0 \fs18 may}{\b0\i0 \fs18 be}{\b0\i0 \fs18 interfac
ed}{\b0\i0 \fs18 in}{\b0\i0 \fs18 this}{\b0\i0 \fs18 fashion.}{\b0 \fs19 A
lso}{\b0\i0 \fs18 note}{\b0\i0 \fs18 the}{\b0\i0 \fs18 excellent}{\b0\i0 \fs1
8 isolation}{\b0\i0 \fs18 (no }

{\b0\i0 \fs18 electric}{\b0\i0 \fs18 connection)}{\b0\i0 \fs18 between}{\b0\i
0 \fs18 the}{\b0\i0 \fs18 logic}{\b0\i0 \fs18 elements}{\b0\i0 \fs18 and}{\
b0\i0 \fs18 the}{\b0\i0 \fs18 higher-voltage/current}{\b0\i0 \fs18
motor}{\
b0\i0 \fs18 circuit. }
\fi356 {\i0 \fs18 A}{\b0\i0 \fs18 solenoid}{\b0\i0 \fs18 is}{\b0\i0 \fs18 an
}{\b0\i0 \fs18 electrical}{\b0\i0 \fs18 device}{\b0\i0 \fs18 that}{\b0\i0 \fs
18 can}{\b0\i0 \fs18 produce}{\b0\i0 \fs18 linear}{\b0\i0 \fs18 motion.}{\b0
\i0 \fs18 The}{\b0\i0 \fs18 circuit}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0
\fs19 6-30b}{\b0\i0 \fs18 shows }
{\b0\i0 \fs18 how}{\b0\i0 \fs18 the}{\b0\i0 \fs18 output}{\b0\i0 \fs18 of}{\
b0\i0 \fs18 a}{\b0\i0 \fs19 TTL}{\b0\i0 \fs18 or}{\i0 \fs19 CMOS}{\b0\i0 \fs
18 logic}{\b0\i0 \fs18 gate}{\b0\i0 \fs18 can}{\b0\i0 \fs18 be}{\b0\i0 \fs18
used}{\b0\i0 \fs18 to}{\b0\i0 \fs18 control}{\b0\i0 \fs18 the}{\b0\i0 \fs18
higher}{\b0\i0 \fs18 currents}{\b0\i0 \fs18 and}{\b0\i0 \fs18 voltages }\pa
r
}
.{\b \fs16 61 }\par
}
FACING }\par
}
f0 131 \par
}
n the solenoid circuit. Once again the driver transistor is turned on and off b
y the output of the logic
. The transistor controls the current through the relay coil. The magnetic forc
e from the relay coil
\par}{\phpg\posx859\pvpg\posy1351\absw9043\absh1904 \sl-237 \f20 \fs18 \cf0 snap
s the NO contacts closed when energized. Closing the{\fs19 NO} rela
y contacts completes the
\par}{\phpg\posx859\pvpg\posy1351\absw9043\absh1904 \sl-238 \f20 \fs18 \cf0 high
er-voltage circuit energizing the solenoid coil. The solenoid coil causes the co
re{\fs19 of} the solenoid to
uce a linear motion.
{\b \f10 \fs17 6.49}
Refer to Fig.{\i \fs19 6-29.} The buzzer will sou
nd only when the output of the inverter goes \par
}
HIGH, LOW) and the transistor
}
conducts, does not conduct) current. \par
}
\cf0 The buzzer in Fig. 6-29{\fs16 will} sound when the output{\fs16
of} the inverter goes HIGH and the transistor
\par}{\phpg\posx1457\pvpg\posy4095\absw8353\absh926 \sl-221 \f20 \fs17 \cf0 cond
ucts current.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs19 6-29.}{\fs18 If}{\fs18 the}{\fs18
output}{\fs19 of}{\fs18 the}{\fs18 inverter}{\fs18 goes}{\fs18 LOW,}{\fs1
8 the}{\fs18 transistor}{\fs18
(will,}{\fs18 will}{\fs18 not)
}\par
}
onduct current and the buzzer
}
is{\fs18 silent,}{\fs18 sounds). }\par
}
f0 6.50 \par
}
f0 6.51 \par
}
f0 6.52 \par
}
7 \cf0 If the output of the inverter in Fig. 6-29 goes{\fs17 LOW,} the
transistor will not conduct and the buzzer is
\par}{\phpg\posx1451\pvpg\posy5749\absw8345\absh2207 \sl-216 \f20 \fs17 \cf0 sil
ent.
{\fs18 What}{\fs18 is}{\fs18 the}{\fs18 function}{\fs18 of}{\fs18 the}{\f
s18 relay}{\fs18 in}{\fs18 the}{\fs18 circuits}{\fs18 in}{\fs18 Fig.}{\i \
fs19 6-30? }
358 The
relay
serves to
isolate
the
logic circuitry from
the
higher-voltage and
higher-current
\par}{\phpg\posx1451\pvpg\posy5749\absw8345\absh2207 \sl-220 \f20 \fs17 \cf0 mot
or/solenoid circuits{\fs17 in} Fig.{\fs17 6-30. }
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\i \fs19 6-30a.}{\fs18 The}{\fs18
electric}{\fs18 motor}{\fs18 operates}{\fs18 when}{\fs18 the}{\fs18 o
utput}{\fs18 of}{\fs18 the}{\fs18 logic}{\fs18 element }\par
}
inverter) goes
}
HIGH,{\fs19 LOW). }\par
}
f0 6.53 \par
}
7 \cf0 The motor in Fig. 6-30a operates when the output of the inverte
r goes HIGH.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\i \fs19 6-30b.}{\fs18 What}{\fs18
is}{\fs18 the}{\fs18 purpose}{\fs18 of}{\fs18 the}{\fs18 diode}{\fs18
placed}{\fs18 in}{\fs18 parallel}{\fs18 with}{\fs18 the}{\fs18 relay}
{\fs18 coil? }
\fs16 Solution: }
356 The diode eliminates harmful voltage spikes that may be generated by
the relay coil. It is sometimes
\par}{\phpg\posx1449\pvpg\posy8835\absw8389\absh1461 \sl-215 \f20 \fs17 \cf0 cal
led a clamp diode. \par
}
Refer to Fig.{\i \fs19 6-29.} The transistor acts most like an
\fs16 Solution: }
354 {\fs17 The}{\fs17 transistor}{\fs17 acts}{\fs17 like}{\fs17 a}{\fs17
switch}{\fs17 in}{\fs17 this}{\fs17 circuit. }\par
}
(amplifier, switch) in this circuit. \par
}
cf0 6.54 \par
}
\cf0 6-8{\fs18
D/A}{\fs19 AND} A/D CONVERSION
\fi374 {\b0 Digital}{\b0 systems}{\b0 must}{\b0 often}{\b0 be}{\b0\i \fs19
interfaced}{\b0 with}{\b0 analog}{\b0 equipment.}{\b0 \fs19 To}{\b0 review
,}{\b0 a}{\b0\i \fs19 digital}{\b0\i \fs19 signal}{\b0 is}{\b0 one }
{\b0 that}{\b0 has}{\b0 only}{\b0 two}{\b0 discrete}{\b0 voltage}{\b0
levels.}{\i \f10 \fs17 An}{\b0\i \fs19 analog}{\b0\i \fs19 signal}{\b0 \f
s18 is}{\b0 one}{\b0 that}{\b0 varies}{\b0\i \fs19 continuously}{\b0
from}{\b0 a }
{\b0 minimum}{\b0 to}{\b0 a}{\b0 maximum}{\b0 voltage}{\b0 or}{\b0 cu
rrent.}{\b0 Figure}{\b0\i \fs19 6-31}{\b0 illustrates}{\b0 a}{\b0 typic
al}{\b0 situation}{\b0 in}{\b0 which}{\b0 the }
{\b0 digital}{\b0 processing}{\b0 unit}{\b0 or}{\b0 system}{\b0 has}{\b0
analog}{\b0 inputs}{\b0 and}{\b0 outputs.}{\b0 The}{\b0 input}{\b0 on}{\b
0 the}{\b0 left}{\b0 is}{\b0 a}{\b0 continuous }
{\b0 voltage}{\b0 ranging}{\b0 from}{\b0\i \fs19 0}{\b0 to}{\b0\i \fs19
5}{\b0 V.}{\b0 The}{\b0 special}{\b0 encoder,}{\b0 called}{\b0 an}
{\b0\i \fs19 analog-to-digital}{\b0\i \fs19 converter}{\fs19 (A/D }\par
}
\par
}
L{\fs17 AND}{\fs17 CMOS}{\fs17 ICs:}{\fs17 CHARACTERISTICS}{\fs17 AND}{\fs
17 INTERFACING }\par
}
AP. 6 \par
}
{\f20 \fs39 I }\par
}
\cf0 A/D
\par}{\phpg\posx3945\pvpg\posy1813\absw945\absh348 \sl-179 \f20 \fs15 \cf0 conve
rter{\f10 \fs16
}{\f10 \fs16 /-/ }\par
}
\cf0 D/A
0 \fs14 /}
converter h a l o g
166 output \par
}
alog
\par
}
{\phpg\posx4951\pvpg\posy2319\absw524\absh338 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Di
gital
\par}{\phpg\posx4951\pvpg\posy2319\absw524\absh338 \sl-178 \f20 \fs15 \cf0 syste
m \par
}
cf0 I
9 - }\par
}
\cf0 Fig. 6-31{\b0
Using}{\b0 \fs17 A/D}{\b0 and}{\b0 \fs17 D/A}{\b0 co
nverters}{\b0 in}{\b0 an}{\b0 electronic}{\b0 system }\par
}
onverter), translates the analog input into digital information.{\fs19
On} the output side of the digital
\par}{\phpg\posx861\pvpg\posy4124\absw8956\absh1677 \sl-239 \f20 \fs18 \cf0 syst
em shown in Fig.{\fs18 6-31,} a special decoder translates from digital informa
tion to an analog voltage.
decoder is called a{\i \fs19 digital-to-analog}{\i \fs19 converter} (D/A
converter).
54 The task of a D/A converter is to transform a digital input into an analog
output. Figure{\i \fs18 6-32a }
strates the function of the D/A converter. A binary number is entered a
t the inputs on the left
\fi2304 {\fs15 Binary }
314 {\fs15 inputs }\par
}
\cf0 ( U ) \par
}
\cf0 Block{\b0 diagram }\par
}
nary input \par
}
{\phpg\posx3355\pvpg\posy8863\absw393\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Ro
w \par
}
alog
\par}{\phpg\posx6623\pvpg\posy8650\absw561\absh390 \sl-221 \f20 \fs17 \cf0 outpu
t \par
}
\cf0 1
1 {\fs16 2 }
0 {\fs15 3 }
1 4
1 {\b\i 5 }
1 6
7 {\fs16 7 }
7 {\fs16 8 }
0 {\i \fs16 9 }
par
}
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs15 0 }
0 \fs16 0 }
0 \fs16 0 }
\sl-218 \f20 \fs17 \cf0 0

\sl-215 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 {\f1
0 {\f10 \fs16 1 }
8 {\f10 \fs15 1 }
0 {\f10 \fs15 1 }
0 {\f10 \fs15 1 }
6 {\f10 \fs15 1 }
6 {\f10 \fs15 1 }
8 {\f10 \fs15 1 }
8 {\f10 \fs15 1 }\par
}
\sl-218 \f20 \fs17 \cf0 \fi3
16 0 }
0 \fs15 0 }
0 \fs15 0 }
6 {\f10 \fs15 1 }
7 {\f10 \fs15 1 }
7 {\f10 \fs15 1 }
7 {\f10 \fs15 1 }
0 \fs16 0 }
0 \fs16 0 }
0 \fs16 0 }
0 \fs15 0 }
1 {\f10 \fs15 1 }
5 {\f10 \fs15 1 }
5 {\f10 \fs15 1 }
9 {\f10 \fs15 1 }\par
}
\sl-217 \f20 \fs17 \cf0 {\fs
2 {\f10 \fs15 1 }
3 {\f10 \fs15 1 }
0 \fs16 0 }
\sl-217 \f20 \fs17 \cf0 0

\sl-216 \f20 \fs17 \cf0 \fi2
\sl-221 \f20 \fs17 \cf0 \fi2

\sl-216 \f20 \fs17 \cf0 \fi3
\sl-221 \f20 \fs17 \cf0 \fi3
\sl-216 \f20 \fs17 \cf0 \fi3
\sl-223 \f20 \fs17 \cf0 \fi3
\sl-216 \f20 \fs17 \cf0 \fi3
\sl-219 \f20 \fs17 \cf0 \fi3
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-216 \f20 \fs17 \cf0 {\f1

\sl-215 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-215 \f20 \fs17 \cf0 \fi2
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-220 \f20 \fs17 \cf0 \fi2
\sl-218 \f20 \fs17 \cf0 {\f1
\sl-221 \f20 \fs17 \cf0 {\f1
\sl-216 \f20 \fs17 \cf0 {\f1
\sl-222 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 \fi3
\sl-223 \f20 \fs17 \cf0 \fi3
\sl-216 \f20 \fs17 \cf0 \fi3
\sl-219 \f20 \fs17 \cf0 \fi3
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-215 \f20 \fs17 \cf0 \fi2

\sl-220 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 {\f1
0 \fs16 0 }
0 {\f10 \fs15 1 }
0 {\f10 \fs15 1 }
0 \fs16 0 }
0 \fs16 0 }
0 {\f10 \fs15 1 }
2 {\f10 \fs15 1 }
0 \fs15 0 }
0 \fs16 0 }
6 {\f10 \fs15 1 }
9 {\f10 \fs15 1 }\par
}
3 {\f10 \fs15 1 }
0 \fs15 0 }
0 {\f10 \fs15 1 }
0 \fs15 0 }
2 {\f10 \fs15 1 }
0 \fs16 0 }
2 {\f10 \fs15 1 }
0 \fs16 0 }
2 {\f10 \fs15 1 }
0 \fs15 0 }
5 {\f10 \fs15 1 }
0 \fs15 0 }
8 {\f10 \fs15 1 }
0 \fs15 0 }
3 {\f10 \fs15 1 }\par
}
\cf0 0
6 {\fs15 1 }
\sl-220 \f20 \fs17 \cf0 \fi3

\sl-220 \f20 \fs17 \cf0 \fi3
\sl-218 \f20 \fs17 \cf0 {\f1
\sl-221 \f20 \fs17 \cf0 {\f1
\sl-216 \f20 \fs17 \cf0 \fi3
\sl-222 \f20 \fs17 \cf0 \fi3
\sl-215 \f20 \fs17 \cf0 {\f1
\sl-223 \f20 \fs17 \cf0 {\f1
\sl-216 \f20 \fs17 \cf0 \fi3
\sl-219 \f20 \fs17 \cf0 \fi3
\fs17 \cf0 \f20 \fs17 \cf0 0
\sl-217 \f20 \fs17 \cf0 \fi2
\sl-216 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 \fi3
\sl-220 \f20 \fs17 \cf0 {\f1
\sl-215 \f20 \fs17 \cf0 \fi3
\sl-220 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 \fi3
\sl-218 \f20 \fs17 \cf0 {\f1
\sl-221 \f20 \fs17 \cf0 \fi3
\sl-216 \f20 \fs17 \cf0 {\f1
\sl-222 \f20 \fs17 \cf0 \fi3
\sl-215 \f20 \fs17 \cf0 {\f1
\sl-223 \f20 \fs17 \cf0 \fi3
\sl-216 \f20 \fs17 \cf0 {\f1
\sl-220 \f20 \fs17 \cf0 \fi4
\fs16 \cf0 \fi54 \f10 \fs16
\sl-216 \f10 \fs16 \cf0 \fi7
\sl-218 \f10 \fs16 \cf0 \fi6
2 2
8 {\fs15 3 }
4 {\fs15 4 }
8 {\b\i \fs16 5 }
8 6
6 {\fs15 7 }
8 8
8 {\i 9 }
15 10 }
15 11 }
15 13 }
15 14 }
15 15 }\par
}
5 \cf0 (b) Truth{\fs15 table }
{\b \fs17 Fig.}{\b \fs17 6-32}{\b \fs17
D/A}{\fs17 converter }\par
}
}
L{\b \fs17 AND}{\b \fs17 CMOS}{\b \fs17 ICs:}{\b \fs17 CHARACTERISTICS}{\b
\fs17 AND}{\b \fs17 INTERFACING }\par
}
f0 133 \par
}
ith a corresponding output voltage at the right.{\b \fs19 As} with other tasks
in electronics, it is well to define
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-242 \f20 \fs18 \cf0 exac
tly the inputs and expected outputs from the system. The truth table in Fig.{\i
\fs19 6-32b} details one set
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-239 \f20 \fs18 \cf0 of p
ossible inputs and outputs for the{\b \fs19 D/A} converter.
69 Consider the truth table in Fig.{\i \fs19 6-32b} for the{\b \fs19 D/A} con
verter. If each of the inputs is LOW, the
ut voltage{\i (V,,,)} is{\fs19 0}{\i V} as defined in row{\i \fs19 1} of th
e table. Row{\i \fs19 2} shows just the{\i \fs19 1s} input{\b\i (}{\b\i A}{
\b\i )}being
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-237 \f20 \fs18 \cf0 acti
vated by a HIGH. With the input as LLLH{\i \fs18 (OOOl),} the output
from the{\b \fs19 D/A} converter is{\fs19 1}{\b V. }
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-238 \f20 \fs18 \cf0 Row{
\i \fs19 3} shows only input{\i \fs19 B} activated{\fs19 (0010).} This pro
duces a{\i \fs19 2-V} output. Row{\i \fs19 5} shows only input{\fs19 C }
vated{\i \fs19 (0100).} This yields a{\i \fs19 4-V} output. Row{\fs19 9} sho
ws only input{\i \fs19 D}{\i \fs19 (1000)} activated; this produces
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-242 \f20 \fs18 \cf0 an{\
i \fs19 8-V} output from the{\b \fs19 D/A} converter. Note that the
inputs{\i \fs19 (}{\i \fs19 D}{\i \fs19 ,}{\fs19 C,}{\i \fs19 B,}{\b\i \fs
19 A}{\b\i \fs19 )} are{\i \fs19 weighted}{\fs19 so} that a
at input{\i \fs19 D} generates an{\i \fs19 8-V} output and a HIGH at input
{\b\i \fs19 A} produces only a 1-V output. The
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-236 \f20 \fs18 \cf0 rela
tive weighting of each input is given as{\i \fs19 8} for input{\i \fs19 D,}{\
i \fs19 4} for input{\i \fs19 C,}{\i \fs19 2} for input{\b\i \fs19 B,} and
{\fs19 1}for input
i \fs19 A} in Fig.{\i \fs19 6-32a. }
67 {\b \fs19 A} simple{\b \fs19 D/A} converter consists of{\fs19 two} functio
nal parts. Figure{\i \fs19 6-32a} shows a block diagram of a
\fs19 D/A} converter. The converter is divided into a{\i \fs19 resistor}{\i \f
s19 network} and a{\i \fs19 summing}{\i \fs19 amplijier.} The resistor
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-237 \f20 \fs18 \cf0 netw
ork weights the{\i \fs19 Is,}{\i \fs19 2s,} 4s, and{\i \fs19 8s} inputs pr
operly, and the summing amplifier{\i \fs19 scales} the output
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-237 \f20 \fs18 \cf0 volt
age according to the truth table. An{\i \fs18 op}{\i \fs19 amp,} or{\i \f
s19 operationa1}{\i \fs19 amplifier,} is commonly used as the
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-237 \f20 \fs18 \cf0 summ
ing amplifier.
67 {\b \fs19 A} few of the important specifications of commercial{\b \fs1
9 D/A} converters are resolution, linearity,
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-242 \f20 \fs18 \cf0 sett
ling time, power dissipation, type of input (binary, complemented binary, and si
gn and magnitude),
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-239 \f20 \fs18 \cf0 tech
nology (TTL, CMOS, or ECL), and special features. One manual lists mo
re than a hundred
\par}{\phpg\posx858\pvpg\posy1359\absw9503\absh4958 \sl-237 \f20 \fs18 \cf0 diff
erent{\b \fs19 D/A} converter ICs having resolutions from{\i \fs19 4} to{\i
\fs19 18} bits.
73 Consider the simplified block diagram of a commercial{\b \fs19 A/D} conver
ter reproduced in Fig.{\i \fs19 6-33a. }
is the{\b\i \fs19
ADC0804}{\i \fs19 8-bit}{\i \fs19 microprocessor-com
patible}{\b\i \fs19
A}{\b\i \fs19 /}{\b\i \fs19 D}{\i \fs19 converter.}
The control lines to the \par
}
20 \fs15 \cf0 Top{\b0 \fs15 View }
cf0 \fi1570 {\b0\i \fs15 (b) }
cf0 {\fs16 Fig.}{\fs17 6-33}{\fs17

ADC0804}{\fs17 8-bit}{\fs17 A/D}{\fs16
converter}{\fs17 IC }\par
}
0 134 \par
}
}
f0 [CHAP.{\b0 \fs17 6 }\par
}
DC0804{\b \fs18 A/D}{\fs18 converter}{\fs18 direct}{\fs18 the}{\b \fs18
A/D}{\fs18 converter}{\fs18 to}{\fs18 first}{\b\i \fs17 sample}{\b\i \fs1
7 and}{\b\i \fs17 digitise}{\fs18 the}{\fs18 analog}{\fs18 voltage}{\fs1
8 at }
18 the}{\fs18 input.}{\fs18 Second,}{\fs18 the}{\fs18 control}{\fs18 lines}
{\fs18 direct}{\fs18 the}{\b \fs18 A/D}{\fs18 converter}{\fs18 to}{\fs18
generate}{\fs18 an}{\fs18 8-bit}{\fs18 binary}{\fs18 output.}{\fs18 The }
18 8-bit}{\fs18 output}{\fs18 will}{\fs18 be}{\fs18 directly}{\fs18 proport
ional}{\fs18 to}{\fs18 the}{\fs18 analog}{\fs18 input}{\fs18 voltage.}{\fs
18 If}{\fs18 the}{\fs18 input}{\fs18 voltage}{\fs18 is}{\i \fs19 5}{\b
\fs18 V,}{\fs18 the }
18 binary}{\fs18 output}{\fs18 will}{\fs18 be}{\b \fs18 11111111.}{\fs18
But}{\fs18 if}{\fs18 the}{\fs18 input}{\fs18 voltage}{\fs18 were}{\fs
18 0}{\b \fs18 V,}{\fs18 the}{\fs18 binary}{\fs18 output}{\fs18 woul
d}{\fs18 read }
18 00000000. }
64 {\b \fs18 A}{\fs18 pin}{\fs18 diagram}{\fs18 of}{\fs18 the}{\b \fs18 ADC
0804}{\b \fs18 A/D}{\fs18 converter}{\fs18 IC}{\fs18 is}{\fs18 shown} in{
\fs18 Fig.}{\b \fs18 6-33b.}{\fs18 The}{\b \fs18 ADC0804}{\fs18 IC}{\fs18
is}{\fs18 a }
\fs19 CMOS}{\fs18 8-bit}{\fs18 successive}{\fs18 approximation}{\b \fs18 A/
D}{\fs18
converter}{\fs18 which}{\fs18 is}{\fs18 designed}{\fs18 to}{\
fs18 operate}{\fs18 with}{\fs18 the}{\b \fs18 8080A }
18 microprocessor}{\fs18 without}{\fs18 extra}{\fs18 interfacing.}{\fs18 The
}{\b \fs18 ADC0804}{\b \fs18 IC's}{\fs18 conversion}{\fs18 time}{\fs18 is}{
\fs18 under}{\fs18 100}{\b\i \f10 \fs15 ps,}{\fs18 and}{\fs18 all }
18 inputs}{\fs18 and}{\fs18 outputs}{\fs18 are}{\fs18 TTL}{\fs18 compatible
.}{\fs18 It}{\fs18 operates}{\fs18 on}{\fs18 a} 5-V{\fs18 power}{\fs18
supply,}{\fs18 and}{\fs18 it}{\fs18 can}{\fs18 handle}{\fs18 a}{\fs18 fu
ll }
18 range}{\fs18 0-}{\fs18 to} 5-V{\fs18 analog}{\fs18 input}{\fs18 between}
{\fs18 pins}{\b \fs18 6}{\fs18 and}{\fs18 7.}{\fs18 The}{\b \fs18 ADC0804
}{\b \fs18 IC}{\fs18 has}{\fs18 an}{\fs18 on-chip}{\fs18 clock}{\fs18 gene
rator }
18 which}{\fs18 needs}{\fs18 only}{\fs18 an}{\fs18 external}{\fs18 resisto

r}{\fs18 and}{\fs18 capacitor}{\fs18 (see}{\fs18 Fig.}{\b \fs18 6-34). }
68 {\b \fs18 A}{\fs18 simple}{\fs18 lab}{\fs18 setup}{\fs18 using}{\fs18 th
e}{\b \fs18 ADC0804}{\b \fs18 A/D}{\fs18 converter}{\fs18 is}{\fs18 shown
}{\fs18 in}{\fs18 Fig.}{\b \fs18 6-34.}{\fs18 The}{\fs18 analog}{\fs18 in
put }
18 voltage}{\fs18 is}{\fs18 developed}{\fs18 across}{\fs18 the}{\fs18 wipe
r}{\fs18 and}{\fs18 ground}{\fs18 of}{\fs18 the}{\b \fs18 10-kiZ}{\fs18
potentiometer.}{\fs18 The}{\fs18 resolution}{\fs18 of}{\fs18 the }
\fs18 A/D}{\fs18 converter}{\fs18 is}{\f10 \fs28 &}{\b\i (28}{\f10 \fs15 }{\b \fs18 1)}{\fs18 of}{\fs18 the}{\fs18 full-scale}{\fs18 analog}{\fs18
voltage}{\fs19 (5}{\b \fs18 V}{\fs18 in}{\fs18 this}{\fs18 example).}{\fs18
For}{\fs18 each}{\fs18 increase }
18 of} 0.02{\b V}{\dn006 \f10 \fs14
X}{\i \fs19 5}{\b \fs18 V}{\
dn006 \f10 \fs13 =} 0.02{\b \fs18 V),}{\fs18 the}{\fs18 binary}{\fs18 ou
tput}{\fs18 increments}{\fs18 by}{\fs18 1.}{\fs18 Therefore,}{\fs18 if}
{\fs18 the}{\fs18 analog}{\fs18 input }
18 equals}{\fs18 0.1}{\b V,}{\fs18 the}{\fs18 binary}{\fs18 output}{\fs1
8 will}{\fs18 be}{\fs18 00000101}{\fs18 (0.1}{\fs18 V/0.02}{\b \fs18
V
}{\dn006 \f10 \fs13 =}{\fs19 5,}{\fs18 and}{\fs18 decimal}{\fs19 5}{\dn
006 \f10 \fs13 =}{\fs18 00000101}{\fs18 in }
18 binary). }\par
}
{\phpg\posx1803\pvpg\posy4544\absw597\absh190 \f30 \fs35 \cf0 \f30 \fs35 \cf0 (A
\par
}
16 \cf0 +5{\b0\i0 \f20 \fs22 v }\par
}
16 \cf0 +5{\b0\i0 \f20 \fs21 v }\par
}
\cf0 Binary output
fi148 indicators \par
}
0 I \par
}
\par
}
\cf0 Fig. 6-34{\fs16
Wiring}{\b0 \fs16 a}{\fs16 test}{\fs16 circuit}{\fs16
with}{\fs16 the}{\fs16 ADC0804}{\fs16 8-bit}{\fs16 A/D}{\fs16
converter
}{\fs16 IC }\par
}
input to the{\b \fs18 ADC0804} IC shown in Fig.{\b \fs18 6-34 }\par
}
starts the conversion process. The binary output appears about{\fs18 100}{
\b\i \f10 \fs15 ps} later at the indicators on the
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-242 \f20 \fs18 \cf0 rig

ht. This{\b \fs18 A/D} converter can make more than{\fs18 5000} conv
ersions per second. The outputs are
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-231 \f20 \fs18 \cf0 thr
ee-state buffered,{\fs18 so} they can be connected directly to the dat
a bus{\fs18 of} a microprocessor-based
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-239 \f20 \fs18 \cf0 sys
tem. The{\b \fs18 ADC0804}{\b \fs18 A/D} coriverter has an{\b\i \fs17
interrupt}{\b\i \fs17
output} (INTR, see pin{\b \fs18 5,}{\fs17 Fig.}{\
b \fs18 6-33b)} which
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-230 \f20 \fs18 \cf0 sig
nals the microprocessor system when the current analog-to-digital conversion is
finished. Interrupts
needed in microprocessor systems when interfacing very "slow" asynchronous dev
ices such as an
\fs18 A/D} converter to "very fast" synchronous devices such as a microproces
sor.
367 Important specifications of commercial{\b \fs18 A/D} converters are resol
ution, linearity, conversion time,
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-233 \f20 \fs18 \cf0 pow
er dissipation, type of output (binary, decimal, complemented binary,
sign and magnitude,
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-239 \f20 \fs18 \cf0 par
allel, serial), and special features. One manual lists hundreds of different{\b
\fs18 A/D} converter ICs with
\par}{\phpg\posx839\pvpg\posy10837\absw9304\absh2551 \sl-230 \f20 \fs18 \cf0 res
olutions between{\fs18 8} and 20 bits.{\b \fs18 A/D} converters with deci
mal outputs (like digital voltmeter ICs)
available with resolutions of{\b \f30 \fs19 3;} and{\b \fs18 4;} digits. \p
ar
}
cf0 converter \par
}
15 \cf0 l 9 \par
}
fs11 \cf0 I
f30 \fs15 b }\par
}
{\phpg\posx4375\pvpg\posy8098\absw395\absh287 \b\i \f20 \fs15 \cf0 \fi36 \b\i \f
20 \fs15 \cf0 CLR
{\b0\i0 \f10 \fs14 I }\par
}
15 \cf0 DB,
DB, \par
}
{\phpg\posx5891\pvpg\posy8158\absw158\absh168 \f20 \fs14 \cf0 \f20 \fs14 \cf0 l7
\par
}
The H-to-L transition of the clock pulse at the \par

}
.{\fs17 61 }\par
}
6 INTERFACING }\par
}
\par
}
LVED PROBLEMS \par
}
7 \cf0 6.55 \par
}
{\phpg\posx1463\pvpg\posy1707\absw8238\absh960 \f20 \fs18 \cf0 \f20 \fs18 \cf0 E
xplain the fundamental difference between{\b \fs18 A/D} and{\b D/A} conver
ters.
51 {\fs16 An}{\b \fs16 A/D}{\fs16 converter}{\fs16 changes}{\fs16 an}{\fs1
6 analog}{\fs16 voltage}{\fs16 proportionately}{\fs16 into}{\fs16 a}{\fs16
digital}{\fs16 output}{\fs16 (usuallybinary).}{\fs16 A }
16 D/A}{\fs16
Converter}{\fs16 transforms}{\fs16 a}{\fs16 digital}{\fs16
input}{\fs16 (usually}{\fs16 binary)}{\fs16 proportionately}{\fs16 into}
{\fs16 an}{\fs16 analog}{\fs16 output}{\fs16 voltage. }\par
}
cf0 6.56{\f10 \fs17
A}{\b0 simple} D/A{\b0
converter}{\b0 consists}{
\b0 \fs18 of}{\b0 two}{\b0 functional}{\b0 parts,}{\b0 a }
i604 {\b0 amplifier. }
}
etwork and a \par
}
\cf0 A simple D/A
converter consists of two functional parts,
a resistor network and a summing
\par}{\phpg\posx1459\pvpg\posy4243\absw8260\absh385 \sl-215 \f20 \fs16 \cf0 ampl
ifier. \par
}
f0 6.57 \par
}
efer to Fig. 6-326. List the output voltage{\i (V,,,)} for each inp
ut combination shown in
{\fs18 6-35. }\par
}

nverter \par
}
10 \cf0 vow
{\b0\i0 \f10 \fs15 -? }\par
}
15 \cf0 i \par
}
15 \cf0 k \par
}
15 \cf0 j \par
}
15 \cf0 i \par
}
15 \cf0 h \par
}
15 \cf0 g \par
}
15 \cf0 f \par
}
15 \cf0 e \par
}
15 \cf0 d \par
}
15 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\fs16 6-35}{\b0 \fs16
D/A}{\b0 \fs16 converter}{\b0 \fs16 pulse
-train}{\b0 \fs16 problem }\par
}
\cf0 Solution:
fi352 {\b0 \fs16 The}{\b0 \fs16 analog}{\b0 \fs16 outputs}{\b0\i \fs16 (V,,
,)}{\b0 \fs16 from}{\b0 \fs16 the}{\b0 \fs16 D/A}{\b0 \fs16
converter}{
\b0 \fs17 in}{\b0 \fs16 Fi,g.}{\fs16 6-35}{\b0 \fs16 are}{\b0 \fs16 as}
{\b0 \fs16 follows: }\par
}
ulse{\fs16 a}{\dn006 \f10 \fs11 =}{\b \fs17 2}{\b \fs17 V }\par
}
lse{\i \fs16 b}{\dn006 \f10 \fs11 = }

{\fs10
c'}{\f10 \fs10 = }\par
}
\b \fs16 V }
\par}{\phpg\posx2593\pvpg\posy9755\absw310\absh385 \sl-213 \f20 \fs16 \cf0 {\b 6
}{\fs16 V }\par
}
lse{\i \f10 \fs16 d}{\dn006 \f10 \fs11 = }
{\b\i \fs16 e}{\dn006 \f10 \fs11 = }\par
}
{\b \fs16 V }
6 1}{\b \fs16 V }\par
}
ulse{\i \f10 \fs14 g}{\dn006 \f10 \fs11 =}{\fs16 0} V
e{\b\i \fs17 h}{\dn006 \f10 \fs11 =} 15{\b \fs17 V }
e{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =}{\fs17 5}{\b V }\par
}
lse{\b\i \fs14 j }\par
}
\f20 \fs16 11}{\b \f20 \fs17 V }\par
}
lse{\b\i \fs17 k}{\dn006 \f10 \fs11 = }\par
}
lse{\b\i \f10 \fs15 1}{\dn006 \f10 \fs11 = }\par
}
\b \fs16 V }\par
}
ulse{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =}{\b \fs16 8}{\b \fs17 V }\par
}
\fs17 V }\par
}
cf0 6.58 \par
}
Refer to Fig. 6-32a. The summing amplifier in a{\b \fs18 D/A} conve
rter is commonly a(n)
\par}{\phpg\posx1445\pvpg\posy10773\absw8259\absh1169 \sl-233 \f20 \fs18 \cf0 (m
ultiplexer, op amp).
i360 {\fs16 An}{\fs16 op}{\fs16 amp}{\fs16 (operational}{\fs16 amplifier)
}{\fs16 is}{\fs16 typically}{\fs16 used}{\fs16 as}{\fs16 the}{\fs16 sum
ming}{\fs16 amplifier}{\fs16 in}{\fs16 a}{\fs16 D/A}{\fs16

converter}{\
fs16 as }
fs16 in}{\fs16 Fig.}{\b\i \fs16 6-32a. }\par
}
17 \cf0 6.59 \par
}
The{\b ADC0804}{\b \fs18 IC} is an{\b A/D} converter with a
}
(parallel, serial) output. \par
}
6 \cf0 The ADC0804 IC is an A/D converter with parallel three-state
outputs that may be connected
\par}{\phpg\posx1447\pvpg\posy13279\absw8238\absh388 \sl-219 \f20 \fs16 \cf0 dir
ectly to a microprocessor data bus. \par
}
0 136 \par
}
7 INTERFACING }\par
}
AP.{\b 6 }\par
}
cf0 6.60{\b0 \fs18
The}{\b0 \fs18 ADC0804}{\b0 \fs18 IC}{\b0 \fs18 has}{\
b0 \fs18 a}{\b0 \fs18 resolution}{\b0 of }
}
4,8,12) bits. \par
}
he ADC0804 A/D converter has a resolution of 8 bits, or{\fs16 1} of{\fs
17 255}{\fs17 (28}{\dn006 \f10 \fs11 -}{\fs16 1}{\dn006 \f10 \fs11 =}{\fs1
7 255). }\par
}
cf0 6.61{\b0 \fs18
.}{\b0 \fs19 If}{\b0 \fs18 the}{\b0 \fs18 input}{\b0 \fs18 voltage}{\b0 \
fs18 is}{\b0 \fs18 2}{\fs18 V,}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \f
s18 output}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 A/D}{\b0 \fs18
c
onverter }\par
}
hould be binary
}

par
}
he calculation is as follows:
916 {\fs17 2}{\fs17 v }
779 {\f10 \fs15 --}{\f10 \fs15
-} 100
799 {\fs17 0.02}{\fs25 v }\par
}
ecimal{\fs17 100}{\dn006 \f10 \fs11 =} 01100100 in binary \par
}
he binary output from the A/D converter shown in Fig. 6-34 is{\fs17 0110010
0} when the input voltage is{\fs17 2}{\fs17 V. }\par
}
cf0 6.62{\b0 \f20 \fs18
The}{\b0 \f20 \fs18 ADC0804}{\b0 \f20 \fs18 IC }
}
is, is not) compatible with microprocessor-based systems. \par
}
\cf0 The ADC0804 A/D converter IC is compatible with microprocessor-base
d systems. It has buffered
\par}{\phpg\posx1465\pvpg\posy5661\absw8246\absh389 \sl-218 \f20 \fs17 \cf0 thre
e-state outputs, microprocessor-compatible control inputs, and an interrup
t output. \par
}
cf0 6.63{\b0 \fs18
The}{\b0 \fs18 ADC0804}{\b0 \fs18 A/D}{\b0 \fs18
c
onverter}{\b0 \fs18 has}{\b0 \fs18 a}{\b0 \fs18 conversion}{\b0 \fs18 ti
me}{\b0 \fs18 of}{\b0 \fs18 about}{\b0 \fs18 100 }
i597 {\b0 \fs18 seconds. }
i952 {\b0 \fs17 The}{\b0 \fs17 ADC0804}{\b0 \fs17 IC}{\b0 \fs17 has}{\b0 \fs
17 a}{\b0 \fs17 conversion}{\b0 \fs17 time}{\b0 \fs17 of}{\b0 \fs17 les
s}{\b0 \fs17 than}{\b0 \fs17 100}{\i \f10 \fs14 ps}{\b0 \fs17 (microsecond
s). }\par
}
cf0 6.64{\b0 \fs18
c
onverter}{\b0 \fs18 operates }
i598 {\b0 \fs18 microprocessor. }
}
micro, nano) \par
}
at the same speed as, slower than) a \par

}
\cf0 A/D converters operate slower than microprocessors and therefore
use an interrupt to signal the
em when they are ready to send valid data. \par
}
cf0 6.65 \par
}
{\f20 \fs17 A}{\f20 \fs17 group}{\f20 \fs17 of}{\f20 \fs17 compatible}{\f2
0 \fs17 digital}{\f20 \fs17 ICs}{\f20 \fs17 that}{\f20 \fs17 can}{\f20 \fs
17 be}{\f20 \fs17 connected}{\f20 \fs17 directly}{\f20 \fs17 together}{\f2
0 \fs17 to}{\f20 \fs17 form}{\f20 \fs17 a}{\f20 \fs17 digital}{\f20 \fs17
system}{\f20 \fs17 is}{\f20 \fs17 said }
20 \fs17 to}{\f20 \fs17 form}{\f20 \fs17 a}{\fs19
.}{\b\i \f20 \
fs17
Ans.}{\f20 \fs17
family }\par
}
\cf0 Digital ICs from the
\i Ans.}{\b\i \fs17
(}{\b\i \fs17 a}{\b\i \fs17 )}
TTL \par
}
s16 \cf0 ( a ) \par
}
{\phpg\posx3849\pvpg\posy11471\absw291\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 a
nd \par
}
6) \par
}
families are the most popular. \par
}
b)MOS \par
}
cf0 6.66 \par
}
cf0 6.67
0 6.68
0 6.69 \par
}
An IC containing from{\fs17 12} to 99 equivalent gates{\b \fs16 is} defined
as an
Refer to Fig.{\b \fs16 6-la.} A{\fs17 2.1-V} input to the{\fs17 TTL} in
verter is a logical
Refer to Fig.{\b\i \fs16 6-la.} A{\fs17 2.1-V} output from the{\fs17 TT

'L} inverter is a logical \par
}
(LSI,MSI,SSI).
\fi101 {\fs16 (0,l)} input.
\fi425 output. \par
}
\f20 \fs17 \cf0 Am.{\b0\i0
MSI }
\cf0 Ans.{\b0\i0 \fs16
1 }\par
}
A}{\b0\i0 \fs17 2.1-V}{\b0\i0 output}{\b0\i0 from}
{\b0\i0 the}{\b0\i0 TTL}{\b0\i0 inverter}{\b0\i0 is}{\b0\i0 defined}{\b0\
i0 as}{\b0\i0 a}{\b0\i0 forbidden}{\b0\i0 output}{\b0\i0 caused}{\b0\i0 b
y}{\b0\i0 a}{\b0\i0 defective}{\b0\i0 IC}{\b0\i0 or }
0 \fi532 {\b0\i0 too}{\b0\i0 heavy}{\b0\i0 a}{\b0\i0 load}{\b0\i0 at}{\b
0\i0 the}{\b0\i0 output. }\par
}
0 CHAP.{\f30 \fs17 61 }\par
}
{\phpg\posx2543\pvpg\posy459\absw1989\absh304 \f20 \fs27 \cf0 \f20 \fs27 \cf0 m{
\fs17 AND}{\b \fs18 CMOS}{\b \f30 \fs19 ICS: }\par
}
{\phpg\posx4385\pvpg\posy545\absw3560\absh205 \f20 \fs18 \cf0 \f20 \fs18 \cf0 CH
ARACTERISTICS
AND{\fs18 INERFACING }\par
}
f0 137 \par
}
f0 6.70 \par
}
hat{\fs17 is} the propagation delay of{\b \f10 \fs16 a} digital{\b \f30 \fs2
0 IC? }\par
}
cf0 Am. \par
}
\cf0 Thc time{\fs16 it} takcs for thc output to changc aftcr thc input has ch
angcd logicstatcs.Thc propagation
\par}{\phpg\posx1929\pvpg\posy1570\absw7908\absh404 \sl-225 \f20 \fs17 \cf0 dela
y for modem digital{\b \f10 \fs16 1Cs}{\fs17 may} ranpc from{\fs18 a}{\fs18
b}{\fs18 u}{\fs18 t}{\b \f10 \fs16 1.5} ns to{\fs17 about}{\b \f10 \fs17
125} ns. \par
}
f0 6.71 \par
}
\cf0 What is the fan-out{\fs19 of}{\b \f10 \fs16 a} digital{\fs18 IC? }

\f10 \fs16 Am.}
Thc number of parallcl loads that can{\fs18 be} drivcn
by{\b \f10 \fs15 a} single digital{\b \fs18 IC} output.
{\fs18 The}{\b \f30 \fs20 CMOS} digital{\b \f30 \fs20 IC} family is noted fo
r its{\fs17
(high.}{\fs17 low)} power consumption.
\fi27 Refer{\fs17 to} Fig.{\b \fs17 6}{\b \fs17 l}{\b \fs17 h}{\b \fs17 .}
{\b \f10 \fs15 A}{\b \f30 \fs19 I-V}input{\b \f10 \fs15 to} the{\b \f10 \fs1
6 CMOS} inverter{\fs17 is} considered{\b \f10 \fs15 a} logical
s18 Am.}
OorLOW \par
}
hich{\f10 \fs17 ?TL} subfamilyis{\fs17 best} for{\b \f30 low-power}consumpti
on?{\b \f10 \fs16
Am. }\par
}
ist thrcc{\b \f10 \fs15 typcs}{\b \f30 \fs17 of}{\f30 \fs21 ITL}outputs.
{\b 7TL} logic devices of the
\par}{\phpg\posx1457\pvpg\posy4519\absw2727\absh843 \sl-220 \f20 \fs17 \cf0 grad
c{\b \f30 \fs20 ICs.}{\b \f10 \fs16
Am.}{\b \f10 \fs16
7}{\b \f10 \f
s16 4}{\b \f10 \fs16 0 }\par
}
f0 6.72
6.73 \par
}
\fs16 \cf0 Am.{\b0 \f20 \fs17
low }
f0 {\i (0.1)}{\b0 \f20 \fs17 input. }\par
}
cf0 6.74
0 6.75
0 6.76 \par
}
ow-power{\b \fs18 7TL} (see Fig. 6-66) \par
}
\fs16 \cf0 Am.{\b0 \f20 \fs17
totcm}{\b0 \f20 \fs17 polc.}{\b0 \f20 \fs1
7 opcnallcctor.}{\b0 \f20 \fs17 thrcc-state }
f0 {\fs16 (540,740)}{\f30 \fs18 scrics}{\b0 \f20 \fs17 arc}{\b0 \f20 \fs17 l
csc}{\b0 \f20 \fs17 expensive}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 arc}{\b0 \
f20 \fs17 considered}{\b0 \f20 \fs19 commercial }\par
}
f0 6.77 \par
}
\cf0 Refer to Fig.{\b \fs17 636.}{\b \f30 \fs19 The} manufacturcrof the{\b
\f30 \fs20 IC} shown{\b\i \f10 \fs15 is }

i \f10 \fs16 ART.} National ScmiconductorCorporation{\b\i \f10 \fs16 (sec}{\b
\f30 logo) }\par
}
\par
}
\cf0 Fii{\fs16 6-36}{\b0 \f20 \fs17
Dual-in-lincpackagc}{\f30 \fs20 IC }\par
}
cf0 6.78
0 {\i \fs17 6.79 }
0 {\i \f30 \fs18 6.80 }
0 6.81 \par
}
cfcr to Fig.{\b \fs17 6-36.}{\b \f10 \fs16 A }\par
}
\cf0 (CMOS.{\b0 \f20 \fs19 TTZ)}{\b0 \f20 \fs17 intcgratcd}{\b0 \f20 \fs17 cir
cuit}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 shown. }\par
}
\cf0 Am.{\b0 \f30 \fs21 ITL }\par
}
efer to Fig.{\b \fs17 6-36.}{\b \f10 \fs16 What} is thc function of thc{\b
\f30 \fs20 IC} shown? \par
}
\cf0 The{\b0 \f20 \fs17 lettcn}{\b0 \f20 \fs18 CMOS}{\b0 \f20 \fs17 stand}{\
b0 \f20 \fs17 for }\par
}
\cf0 The
\b0 \f20 \fs17 cquipmcnt. }
f0 {\f30 \fs20 The }\par
}
\par
}
\cf0 Am.{\b0 \f20 \fs17
quad}{\b0 \f20 \fs17 2-input}{\b0 \f20 \fs17 SAND
}\par
}
\cf0 (7400{\f30 \fs21 IC) }\par
}
s16 \cf0 Am.{\b0\i0 \f20 \fs17
complementary}{\b0\i0 \f20 \fs17 mctal&de}{\
b0\i0 \f20 \fs17
semiconductor }\par
}
16 \cf0 6.82 \par
}
\fs20 \cf0 (CMOS.{\b0 \fs20 lTL)}{\b0 \f20 \fs17 families}{\b0 \f20 \fs17 are
}{\b0 \f20 \fs17 generally}{\b0 \f20 \fs17 better}{\b0 \f20 \fs17 suited}{
\b0 \f20 \fs17 for}{\b0 \f20 \fs18 usc}{\b0 \f20 \fs18 in}{\b0 \f20 \fs17
portable}{\b0 \f20 \fs17 hattcry-operated }
\fi183 {\f10 \fs16 Am.}{\fs20 CMOS }
cf0 {\f10 \fs17 (400.7411CO)}{\b0 \f20 \fs17 scrics}{\b0 \f20 \fs17 of}{\fs21
CMOS}{\f20 \fs19 ICs}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17 better}{\b0 \f20 \
fs17 suited}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 high-speed}{\b0 \f20 \fs17
operation. }\par
}
fs16 \cf0 Am.{\i0 \f20 \fs16
74HCOr) }\par
}
\cf0 The
f0 {\fs17 The }\par
}
\cf0 (4000.7400){\b0 \f20 \fs17
scrics}{\b0 \f20 \fs18 of}{\f30 \fs20 ICs}
{\b0 \f20 \fs17 might}{\b0 \f20 \fs19 usc}{\fs16 a}{\f30 \fs18 10-V}{\b0 \f
20 \fs17 dc}{\b0 \f20 \fs17 power}{\b0 \f20 \fs17 supply. }\par
}
cf0 6.83
0 {\i 6.84 }\par
}
\cf0 Am. \par
}
ooo \par
}
\cf0 (CMOS.{\f20 \fs18 7TL)}{\b0 \f20 \fs18 familics}{\b0 \f20 \fs17 are}{\b
0 \f20 \fs17 gcncrally}{\b0 \f20 \fs17 bettcr}{\b0 \f20 \fs17
suited}{\b0
\f20 \fs17
for}{\b0 \f20 \fs17 use}{\b0 \f20 \fs17 when}{\b0 \f20 \fs17
the}{\b0 \f20 \fs17 power}{\b0 \f20 \fs17
source}{\b0 \f20 \fs17 is }\
par
}
unregulated. such{\b \f10 \fs15 as} a battery source. \par
}
\cf0 ICc{\b0 \fs17 of}{\b0 \fs17
thc }
\b0 \fs17 voltagcs. }\par
}
\cf0 A m{\f30 \fs19 CMOS }\par
}
cf0 6 s \par
}
\cf0 Am. \par

}
0 \fs20 \cf0 (CMOS.{\b0 \fs21 ITL)}{\b0 \f20 \fs17 family}{\b0 \f20 \fs17 are}
{\b0 \f20 \fs17 especially}{\b0 \f20 \fs17 scnsitivc }
{\fs20 CMOS }\par
}
\cf0 to{\b0 \f20 \fs17 static}{\b0 \f20 \fs17 dischargcs}{\b0 \f20 \fs17
and}{\b0 \f20 \fs17
transient }\par
}
cf0 6.86 \par
}
If{\fs17 an}{\b \f30 \fs20 IC}{\fs17 has}{\fs17 the}{\fs17 marking}{\b \f1
0 \fs16 74CO8.}{\fs17 it}{\fs17 is}{\b \f10 \fs15 a }\par
}
(CMOS.{\fs19 TTZ)}{\fs17 device. }\par
}
\cf0 Am.{\f30 \fs21 CMOS }\par
}
\par
}
L AND CMOS{\b ICs:} CHARACTERISTICS AND INTERFACING \par
}
}
f0 6.87 \par
}
Refer to Fig.{\b \fs16 6-18c.} When the output of the TTL inverter g
oes to about{\fs17 3}{\fs17 V,} the
lights. That indicates a
(HIGH, LOW) logic level.{\b\i \f
10 \fs15
Ans.}
red, HIGH
Refer to Fig. 6-18d. When the output of the TTL inverter goes LOW, th
e transistor
ducting and the LED
(does not light, lights).{\b\i \f10 \f
s15
Ans.}
is not, does not{\fs16 light }\par
}
{\phpg\posx8771\pvpg\posy1381\absw938\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 (g
reen, red) \par
}
f0 6.88 \par
}
{\phpg\posx8911\pvpg\posy2125\absw795\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 (i
s, is not) \par
}
f0 6.89 \par
}
\cf0 Refer to Fig.{\fs17 6-15d.} The buffer is used for interfacing the
CMOS and standard TTL gate because{\fs16 it} has
705 (fewer, more) output current drive capabilities than the standard CMO
S inverter.
\i \f10 \fs15 Ans.}
more
\fi30 In Fig. 6-16b and{\fs16 c,} special
(buffers, transis
tors) are used between TTL and CMOS gates to aid
30 in interfacing.{\b\i \f10 \fs15
Ans.}
buffers \par
}
efer to Fig. 6-2%. Component{\b \f30 \fs18 S,} is considered an active\par}{\phpg\posx1429\pvpg\posy4573\absw4728\absh392 \sl-215 \f20 \fs17 \cf0 clos
ing the switch causes the input of the inverter to go \par
}
\cf0 (HIGH, LOW) input switch because
\par}{\phpg\posx6467\pvpg\posy4581\absw3229\absh385 \sl-215 \f20 \fs17 \cf0 (HIG
H, LOW).{\b\i \f10 \fs15
Ans.}
HIGH, HIGH \par
}
f0 6.90 \par
}
f0 6.91 \par
}
f0 6.92 \par
}
Refer to Fig.{\i \fs17 6-27b.} The NAND gates forming the switch debou
ncing circuit are wired like a latch or
633 {\f10 \fs19 .}{\b\i \f10 \fs15
Ans.}{\b \fs17
RS} flip-flop
Refer to Fig. 6-28b. The 7403 TTL NAND gates have open-collector out
puts which require
\par}{\phpg\posx1429\pvpg\posy5329\absw8292\absh2201 \sl-221 \f20 \fs17 \cf0 (pu
ll-down, pull-up) resistors at the gate outputs.{\b\i \f10 \fs15
A
ns.}
pull-up
When a mechanical switch closes and opens, the contacts do not make
and break the circuit cleanly,
\par}{\phpg\posx1429\pvpg\posy5329\absw8292\absh2201 \sl-218 \f20 \fs17 \cf0 gen
erating unwanted voltage spikes. This is called switch{\f10 \fs19
.}{\b\i \f10 \fs15
Ans.}
bounce
Refer to Fig. 6-29. When the output of the inverter goes HIGH, the tr
ansistor
(blocks current, \par
}
onducts current) and the buzzer

Refer to Fig. 6-30a. The
\par}{\phpg\posx1429\pvpg\posy7777\absw2619\absh867 \sl-221 \f20 \fs17 \cf0 moto
r circuit.{\b\i \f10 \fs15
Ans.}
relay \par
}
is silent, sounds). \par
}
15 \cf0 Ans. \par
}
onducts current, sounds \par
}
f0 6.93 \par
}
f0 6.94 \par
}
f0 6.95 \par
}
f0 6.96 \par
}
diode, relay) isolates the logic circuitry from the higher-voltage electric \
par
}
f0 6.97 \par
}
efer to Fig. 6-30a. When the output of the inverter goes LOW, the tran
sistor \par
}
onducts current), the \par
}
blocks current, \par
}
NC, NO) contacts of
the
relay close, and
the
electric mo
tor \par
}
does not operate, operates). \par
}
15 \cf0 Ans. \par
}
locks current, NC, does not operate \par
}
cf0 6.98 \par
}
A special decoder that interfaces a digital system and an analog output i

s called a(n)
b\i \f10 \fs15 Ans.}
D/A converter
0 \fi21 A special encoder that interfaces an analog input and a digita
l system is called a(n)
b\i \f10 \fs15 Ans.}
A/D converter \par
}
\par
}
cf0 6.99 \par
}
\par
}
\cf0 6.100{\b0 \fs17
b.}{\b0 \fs17 A}{\fs17 6-V}{\b0 \fs17 output}{\b0 \fs17 from}{\b0 \fs17 t
he}{\b0 \fs17 D/A}{\b0 \fs17
converter}{\b0 \fs17 could}{\b0 \fs17 be}{\
b0 \fs17 generated}{\b0 \fs17 only}{\b0 \fs17 by}{\b0 \fs16 a }
fi599 {\b0 \fs17 input.}{\i \f10 \fs15
Ans.}{\b0 \fs17
0110 }\par
}
\cf0 6.101{\b0 \fs17
The}{\b0 \fs17 abbreviation}{\b0 \fs17 op}{\b0 \fs1
7 amp}{\b0 \fs17 stands}{\b0 \fs17 for }
f0 6.102{\fs17
A}{\b0 \fs17 digital}{\b0 \fs17 voltmeter}{\b0 \fs17 is}{
\b0 \fs17 one}{\b0 \fs17 application}{\b0 \fs17 of}{\b0 \fs17 a(n) }\par
}
\par
}
s15 \cf0 Ans.
\cf0 \fi288 {\b0\i0 \fs19 . }\par
}
operational amplifier
\fi166 {\b\i \f10 \fs15 Ans.}
A/D converter \par
}
inary \par
}
\cf0 6.103{\b0 \fs17
The}{\b0 \fs17 resolution}{\b0 \fs17 of}{\b0 \fs17
an}{\b0 \fs17 A/D}{\b0 \fs17
converter}{\b0 \fs17 can}{\b0 \fs17 be}{
\b0 \fs17 given}{\b0 \fs17 as}{\b0 \fs17 the}{\b0 \fs17 number}{\b0 \fs1
7 of }
fi576 {\i \f10 \fs15 Ans.}{\b0\i \f10 \fs14
(a)}{\b0 \fs17
bits}{\b0\i
(}{\b0\i b}{\b0\i )}{\b0 \fs17
resolution }\par
}
a) \par
}
or as the percent \par
}
\cf0 ( 6 ) \par
}
\par
}
. 61 \par
}
L AND CMOS ICs: CHARACTERISTICS{\b \fs17 AND} INTERFACING \par
}
\par
}
cf0 6.104{\b0 \fs17
co
nverter}{\b0 \fs17 has}{\b0 \fs17 an}{\b0 \fs17 %bit }\par
}
BCD, binary) output. \par
}
cf0 6.105{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 Fig.}{
\b0 \f20 \fs17 6-34.}{\b0 \f20 \fs17 If}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
input}{\b0 \f20 \fs17 voltage}{\f20 \fs17 is}{\b0 \f20 \fs17 3}{\f20 \fs17
V,}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 binary}{\b0 \f20 \fs17 output}{\b0
\f20 \fs17 should}{\b0 \f20 \fs17 be }
i571 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
10010110}{\b0 \f20 \fs17 (3}{\f20
\fs17 V/0.02}{\b0 \f20 \fs17
V}{\b0\dn006 \fs11 =}{\b0 \f20 \fs17 150}{\
b0 \fs13 =}{\b0 \f20 \fs17 10010110}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 bina
ry) }\par
}
binary }
\cf0 \fi323 {\b0\i0 \f10 \fs19 . }\par
}
cf0 6.106{\b0 \fs17
.}{\b0 \fs17 The}{\b0 \fs17 10-kSZ}{\b0 \fs17 resistor}{\b0 \fs17 and}{\b0
\fs17 the}{\b0 \fs17 150-pF}{\b0 \fs17 capacitor}{\b0 \fs17 are}{\b0 \fs
17 associated}{\b0 \fs17 with}{\b0 \fs17 the }
i598 {\b0 \fs17 power}{\b0 \fs17 supply)}{\b0 \fs17 of}{\b0 \fs17 the}{\b0
\fs17 ADC0804}{\b0 \fs17 A/D}{\b0 \fs17
converter}{\b0 \fs17 IC.}{\i \fs
17
Ans.}{\b0 \fs17
clock }\par
}
cf0 6.107{\b0 \fs17
The}{\b0 \fs17 ADC0804}{\fs17 IC}{\b0 \fs17 uses}{\b
0 \fs17 the }
i576 {\i \fs17 Ans.}{\b0 \fs17

successive}{\b0 \fs17 approximation }\par
}
onversion A-to-D conversion technique. \par
}
lock, \par
}
6 \cf0 Chapter{\b\i \f30 \fs59 7 }
\fi2578 {\b \fs34 Code}{\b \fs34 Conversion }
cf0 {\f20 \fs20 Onc}{\f20 \fs20 application}{\f20 \fs20 of}{\f20 \fs20 logi
c}{\f20 \fs20 gates}{\f20 \fs20 in}{\f20 \fs20 digital}{\f20 \fs20 systems}
{\f20 \fs20 is}{\f20 \fs20 as}{\b \fs17 code}{\b\i \f20 \fs19 conr'errers.}{
\f20 \fs20 Common}{\b \fs18 codes}{\f20 \fs20 used}{\f20 \fs20 are }\par
}
\cf0 7-1{\fs20
INTRODUCTION }
f0 {\b0 \fs20 binary,}{\b0 \fs20 BCD}{\f10 \fs18 (8421),}{\b0 \fs20 octal,}{
\b0 \fs20 hcxadccimal,}{\b0 \fs20 and,}{\b0 \fs20 of}{\b0 \fs20 course,}{\b0
\fs20 dccimal.}{\b0 \fs20 Much}{\b0 \fs20 of}{\b0 \fs20 thc}{\b0 \fs20 "m
ystcry"}{\b0 \fs20 surrounding }
\b0 \fs20 computers}{\b0 \fs20 and}{\b0 \fs20 other}{\b0 \fs20 digital}{\b
0 \fs20 systcms}{\b0 \fs20 stems}{\b0 \fs20 from}{\b0 \fs20 the}{\b0 \fs20
unfamiliar}{\b0 \fs20 language}{\b0 \fs20 of}{\b0 \fs20 digital}{\b0 \fs20
circuits.}{\b0 \fs20 Digital }
\b0 \fs20 dcviccs}{\b0 \fs20 can}{\b0 \fs20 process}{\b0 \fs20 only}{\f10 \fs
18 1}{\b0 \fs20 and}{\fs19 0}{\b0 \fs20 bits.}{\b0 \fs20 However.}{\b0 \fs1
8 it}{\b0 \fs18 is}{\b0 \fs20 dificult}{\b0 \fs20 for}{\b0 \fs20 humans}{
\b0 \fs18 to}{\b0 \fs20 understand}{\b0 \fs20 long}{\b0 \fs20 strings}{\b0 \
fs19 of }
fi24 {\f10 \fs17 1s}{\b0 \fs20 and}{\i \f10 \fs18 0s.}{\b0 \fs20 For}{\b0 \fs
20 that}{\b0 \fs20 reason,}{\b0 \fs20 codc}{\b0 \fs20 convcrtcrs}{\b0 \fs20
arc}{\b0 \fs20 ncccssary}{\b0 \fs20 to}{\b0 \fs20 convert}{\b0 \fs20 from}
{\b0 \fs20 thc}{\b0 \fs20 languagc}{\b0 \fs20 of}{\b0 \fs20 pcoplc}{\b0 \fs
20 to }
\b0 \fs20 the}{\b0 \fs20 language}{\b0 \fs20 of}{\b0 \fs18 the}{\b0 \fs20 ma
chine. }
fi366 {\b0 \fs20 Considcr}{\b0 \fs19 the}{\b0 \fs20 simple}{\f30 \fs20 block}
{\b0 \fs20 diagram}{\b0 \fs20 of}{\b0 \fs20 a}{\b0 \fs20 hand-held}{\b0 \fs2
0 calculator}{\b0 \fs20 in}{\b0 \fs20 Fig.}{\f10 \fs18 7-1.}{\b0 \fs20 The}
{\b0 \fs20 input}{\b0 \fs20 dcvicc}{\b0 \fs20 on}{\b0 \fs20 the }
\b0 \fs20 left}{\b0 \fs19 is}{\b0 \fs20 thc}{\b0 \fs20 common}{\b0 \fs20
keyboard.}{\b0 \fs20 Bctwcen}{\b0 \fs20 thc}{\b0 \fs20 kcyboard}{\b0 \fs20
and}{\b0 \fs20 thc}{\b0 \fs20 central}{\b0 \fs20 processing}{\b0 \fs19 u
nit}{\b0 \fs20 (CPU)}{\b0 \fs20 of}{\b0 \fs20 the }
\b0 \fs20 calculator}{\b0 \fs20 is}{\b0 \fs20 an}{\b0 \fs19 encoder.}{\b0 \f
s19 This}{\b0 \fs20 encoder}{\b0 \fs20 transla'tcs}{\b0 \fs20 thc}{\b0 \fs20
dccimal}{\b0 \fs20 number}{\b0 \fs20 pressed}{\b0 \fs20 on}{\b0 \fs20 thc}

{\b0 \fs20 keyboard}{\b0 \fs20 into}{\b0 \fs20 a }
\b0 \fs20 binary}{\b0 \fs20 code}{\b0 \fs20 such}{\f10 \fs17 as}{\b0 \fs19
tlic}{\fs19 RCD}{\f10 \fs17 (R4421)}{\f10 \fs17 a}{\f10 \fs17 t}{\f10 \fs17
e}{\f10 \fs17 .}{\b0 \fs20 The}{\b0 \fs20 CPU}{\b0 \fs20 performs}{\b0 \fs1
8 its}{\b0 \fs20 operation}{\b0 \fs20 in}{\b0 \fs20 binary}{\b0 \fs20 and}
{\b0 \fs20 puts}{\b0 \fs19 out}{\b0 \fs20 a }
\b0 \fs20 binary}{\b0 \fs20 code.}{\f30 \fs22 The}{\b0 \fs20 decoder}{\b0 \fs
20 translatcs}{\b0 \fs20 thc}{\b0 \fs20 binary}{\b0 \fs20 codc}{\b0 \fs20 f
rom}{\b0 \fs19 thc}{\b0 \fs20 CPU}{\b0 \fs20 to}{\b0 \fs20 a}{\b0 \fs20 spc
cial}{\f10 \fs18 calc}{\b0 \fs20 which}{\b0 \fs20 lights}{\b0 \fs20 the }
\b0 \fs20 correct}{\b0 \fs20 segments}{\b0 \fs20 on}{\b0 \fs20 the}{\b0 \f
s20 scvcn-segment}{\b0 \fs20 display.}{\b0 \fs20 Thc}{\b0 \fs20 decodcr}{
\b0 \fs20 thereby}{\b0 \fs20 translatcs}{\b0 \fs20 from}{\b0 \fs20 binar
y}{\b0 \fs20 to }
\b0 \fs20 decimal.}{\b0 \fs20 The}{\b0 \fs20 encoder}{\b0 \fs20 and}{\b0 \fs2
0 dccodcr}{\b0 \fs19 in}{\b0 \fs20 this}{\b0 \fs20 system}{\b0 \fs20 are}{\
b0 \fs20 clectronic}{\b0 \fs20 code}{\b0 \fs20 translators.}{\f30 \fs21 The}
{\b0 \fs20 encoder}{\b0 \fs20 can}{\b0 \fs19 be }
\b0 \fs20 thought}{\b0 \fs20 of}{\f10 \fs17 as}{\b0 \fs20 translating}{\b0 \
fs20 from}{\b0 \fs19 thc}{\b0 \fs20 language}{\b0 \fs19 of}{\b0 \fs20 peop
le}{\f10 \fs17 to}{\b0 \fs19 thc}{\b0 \fs20 languagc}{\b0 \fs18 o}{\b0 \fs18
f}{\b0 \fs20 the}{\b0 \fs20 machine.}{\f30 \fs20 The}{\b0 \fs20 decoder
}
\b0 \fs20 does}{\b0 \fs19 the}{\b0 \fs20 opposite;}{\b0 \fs18 it}{\b0 \fs20
translatcs}{\b0 \fs20 from}{\b0 \fs20 machine}{\b0 \fs20 language}{\b0 \fs20
to}{\b0 \fs20 human}{\b0 \fs20 languapc. }\par
}
cf0 Input \par
}
cf0 Our{\fs14 put }\par
}
cf0 Keyboard \par
}
cf0 Decimal
i23 {\fs13 dicplay }\par
}
\cf0 Fig.{\f10 \fs16 7-1}{\fs19 Basic}{\f30 \fs19 block}{\fs19 diagram}{\fs1
8 of}{\fs19 a}{\fs19 calculator }\par
}
cf0 7-2{\f20 \fs20
ENCODING }
i350 {\b0 \f20 \fs21 The}{\b0 \f20 \fs19 job}{\b0 \f20 \fs20 of}{\b0 \f20 \fs2
0 the}{\b0 \f20 \fs20 cncodcr}{\b0 \f20 \fs20 in}{\b0 \f20 \fs20 thc}{\b0 \
f20 \fs20 calculator}{\b0 \f20 \fs20 is}{\b0 \f20 \fs20 to}{\b0 \f20 \fs20 t
ranslate}{\b0 \f20 \fs20 a}{\b0 \f20 \fs20 decimal}{\b0 \f20 \fs20 input}{\b0
\f20 \fs20 to}{\b0 \f20 \fs20 a}{\b0 \f20 \fs20 BCD}{\fs18 (8421)}{\b0 \f20
\fs20 number. }
fs18 A}{\b0 \f20 \fs20 logic}{\b0 \f20 \fs20 diagram,}{\b0 \f20 \fs20 in}{\b0
\f20 \fs20 simplified}{\b0 \f20 \fs20 form,}{\b0 \f20 \fs20 for}{\b0 \f20 \f
s20 a}{\b0 \f20 \fs20 decimal-to-RCDencodcr}{\b0 \f20 \fs20 is}{\b0 \f20 \fs2
0 shown}{\b0 \f20 \fs19 in}{\b0 \f20 \fs20 Fig}{\b0 \f20 \fs20 7-2.}{\b0 \f
20 \fs20 Thc}{\b0 \f20 \fs20 cncodcr }\par
}
\cf0 Fig.{\fs18 7-2}{\fs19 Logic}{\b0 \fs18 symbol}{\fs19 for}{\f10 \fs15
a}{\fs19 dccimal-to-BCDcncodcr }
\fi1943 {\b0 \fs19 140 }\par
}
0 CHAP.{\b0 \f10 \fs16 71 }\par
}
DE{\b \fs17 CONVERSION }\par
}
\par
}
as ten inputs on the left and four outputs on the right. The encoder may have{\i
\fs19 one}{\i \fs19 active}{\i \fs19 input,} which
urn{\i \fs19 produces}{\i \fs19 a}{\i \fs19 unique}{\i \fs19 output.} Decim
al input 7 is shown being activated in Fig. 7-2. This results in
BCD output{\fs18 of} 0111, as shown on the BCD output indicators at the right.
63 The block diagram for a commercial decimal-to-BCD encoder is shown i
n Fig. 7-3a. The most
\par}{\phpg\posx879\pvpg\posy1334\absw9180\absh2573 \sl-237 \f20 \fs18 \cf0 unus
ual features are the small bubbles at the inputs and outputs. The bubbles at the
inputs mean that
inputs are activated by logical{\b \fs18 OS,} or LOWs. The bubbles at the outpu
ts mean that the outputs are
\par}{\phpg\posx879\pvpg\posy1334\absw9180\absh2573 \sl-238 \f20 \fs18 \cf0 norm
ally HIGHS, or at logical Is, but when activated, they go LOW, or to logical{\
b \fs18 OS.} Four inverters
been added to the circuit to invert the output back to its more usu
al form. Another unusual
\par}{\phpg\posx879\pvpg\posy1334\absw9180\absh2573 \sl-230 \f20 \fs18 \cf0 feat
ure of the encoder is that there is no zero input.{\b \fs19 A} decimal{\fs18 0
} input will mean a 1111 output (at{\i \fs19 D, }
18 C,}{\b\i \fs19 B,} and{\b\i A),}which is true when all inputs (1-9) are n
ot connected to anything. When the inputs are
\par}{\phpg\posx879\pvpg\posy1334\absw9180\absh2573 \sl-232 \f20 \fs18 \cf0 not
connected, they are said to be{\i \fs19 floating.} The 74147 encoder is a
TTL device, which means that
\par}{\phpg\posx879\pvpg\posy1334\absw9180\absh2573 \sl-235 \f20 \fs18 \cf0 unco
nnected inputs will float HIGH. \par
}

cf0 Inputs \par
}
cf0 outputs \par
}
\cf0 BCD output indicators
fi202 {\fs14 8s}{\fs14
4s}{\b0
2s}{\fs14
Is }\par
}
\fs19 \cf0 H H H H H H H H H H H H H
\fi50 {\fs25 x}{\fs25 x}{\fs25 x}{\fs25 x}{\fs25 x}{\fs25 x}{\fs25 x}{\fs2
5 x}{\fs25 L} L H H L
\fi50 X X X X X X X L H L H H H
\fi55 X X X X X X L H H H L L L
\fi55 X X X X X L H H H H L L H
\fi55 X X X X L H H H H H L H L
\fi55 X X X L H H H H H H L H H
\fi55 X X L H H H H H H H H L L
\fi55 X L H H H H H H H H H L H
\fi61 L H H H H H H H H 1H H H{\fs19 L }
cf0 {\f20 \fs15 H}{\b0 \f10 \fs11 =}{\f20 \fs15 HIGH}{\f20 \fs14 logic}{\f2
0 \fs14 lebel,}{\f20 \fs15 L}{\b0 \f10 \fs13 =}{\f20 \fs14 LOW}{\f20 \fs14
logic}{\f20 \fs14 level,}{\f20 \fs15 X}{\b0 \f10 \fs14 =}{\f20 \fs14 irr
elevant }
cf0 \fi1510 {\i \f20 \fs15 (b)}{\f20 \fs14 Truth}{\f20 \fs14 table }\par
}
f0 Decimal
\par}{\phpg\posx893\pvpg\posy6636\absw698\absh326 \sl-174 \b \f20 \fs14 \cf0 \fi
94 input \par
}
\cf0 (a){\fs14 Logic}{\fs15 symbol}{\fs14 with}{\fs14 output}{\fs14 indi
cators }\par
}
\cf0 Fig.{\fs17 7-3}{\fs17
Commercial}{\fs17 TTL}{\fs17 74147}{\fs17 deci
mal-to-BCDpriority}{\fs17 encoder }\par
}
\cf0 The encoder diagrammed in Fig. 7-3 is called a 10-line-to-4-lin
e
priority encoder by the
4 manufacturer. This TTL device is referred to as a 74147 encoder.{\b \fs19 A}
truth table for the 74147 encoder
7 is in Fig. 7-3b. The first line on the truth table is for{\i \fs19 no}{
\i \fs19 inputs.} With all inputs floating HIGH, the
3 outputs are HIGH. This is interpreted as a{\fs18 0000} on the BCD o
utput indicators in Fig.{\i \f10 \fs17 7-3a.} The
8 second line of the truth table in Fig. 7-36 shows decimal input{\fs18 9} bein
g activated by a LOW, or{\fs18 0.} This
2 produces an LHHL at outputs{\i \fs19 D,}{\fs18 C,}{\b\i \fs19 B,}{\b\i \fs1
9 A.} The LHHL{\fs18 is} inverted by the four inverters, and the BCD
1 indicators read 1001, which is the BCD indication for a decimal 9.
73 The second line of the truth table in Fig. 7-3b shows inputs 1 through{\fs18
8} marked with{\fs19 Xs.}{\b\i \f10 \fs16 An}{\b \fs19 X} in
2 the table means{\i \fs19 irrevelant.}{\b\i \f10 \fs17 An} irrelevant i
nput can be either HIGH or LOW. This encoder has a
\fs19 priority}{\i \fs19 feature,} which activates the highest number that has
a LOW input.{\fs18 If} LOWs were simultane\par}{\phpg\posx847\pvpg\posy9419\absw9272\absh4042 \sl-239 \f20 \fs18 \cf0 \fi2
1 ously placed on inputs 9 and{\fs19 5,} the output would be 1001for the decim
al 9. The encoder activates the
1 output of the highest-order input number only.
75 The logic diagram for the 74147 encoder, as furnished by Texas Instruments, I
nc., is shown in Fig.
3 7-4. All{\fs18 30} gates inside the single 74147 TTL{\b \fs19 IC} are shown.
First try activating the decimal{\fs18 9} input
\par}{\phpg\posx847\pvpg\posy9419\absw9272\absh4042 \sl-230 \f20 \fs18 \cf0 (LOW
at input{\fs18 9).} This{\fs18 0} input is inverted by inverter 1, and
a 1 is applied to NOR gates 2 and 3.
1 NOR gates{\b\i \fs19 2} and 3 are thus activated, putting out LOWs. NOR gates
4 and{\fs19 5} are deactivated by the
1 presence of{\b \fs18 OS} at their inputs from the deactivated AND g
ates 7 through 18. These AND gates
\par}{\phpg\posx847\pvpg\posy9419\absw9272\absh4042 \sl-230 \f20 \fs18 \cf0 (7 t
hrough{\fs18 18)} are deactivated by the{\b \fs18 OS} at their bottom inp
uts produced by NOR gate{\b \fs18 6.} The AND
3 gates (7 through{\fs18 18)} make sure that the higher decimal input has pr
iority over small numbers. \par
}
\par
}
DE{\fs17 CONVERSION }\par
}
AP. 7 \par
}

cf0 4 \par
}
0 q:p& \par
}
\cf0 8{\b0 \f10 \fs25 --4tr- }\par
}
\fs16 \cf0 Fig.{\f10 \fs15 7-4}{\b0 \fs16
Logic}{\b0 \fs16 diagram}{\b0 \fs
16 of}{\b0 \fs16 74147}{\b0 \fs16 decimal-to-BCD}{\b0 \fs16 priority}{\b0 \
fs16 encoder}{\b0\i \fs16 (Reprinted}{\i \fs16 by}{\b0\i \fs16 permission}{\
i \f30 \fs16 of}{\b0\i \fs16 Texas}{\b0\i \fs16 Instruments) }
f0 \fi360 {\i \f10 \fs17 An}{\b0 \fs18 encoder}{\b0 \fs18 using}{\b0 \fs18
the}{\b0 \fs18 CMOS}{\b0 \fs18 technology}{\b0 \fs18 also}{\b0 \fs18 is
}{\b0 \fs18 available.}{\b0 \fs18 The}{\b0 \fs18 74HC147}{\b0 \fs18 10-}
{\b0 \fs18 to}{\b0 \fs18 4-Line}{\b0 \fs18 Priority }
\b0 \fs18 Encoder}{\b0 \fs18 is}{\b0 \fs18 one}{\b0 \fs18 of}{\b0 \fs18 ma
ny}{\b0 \fs18 DIP}{\b0 \fs18 ICs}{\b0 \fs18 available}{\b0 \fs18 from}{\b0
\fs18 National}{\b0 \fs18 Semiconductor}{\b0 \fs18 Corporation}{\b0 \fs18
in}{\b0 \fs18 its}{\b0 \fs18 74HC00 }
\b0 \fs18 series. }\par
}
- \par
}
f0 7 \par
}
LVED PROBLEMS \par
}
f0 7.1 \par
}
he 74147 encoder translates from the
\par}{\phpg\posx1459\pvpg\posy9465\absw3457\absh726 \sl-240 \f20 \fs18 \cf0 octa
l) code.
}
{\phpg\posx5023\pvpg\posy9554\absw187\absh113 \f10 \fs9 \cf0 \f10 \fs9 \cf0 ~. \
par
}
decimal, Gray) code into the \par
}
{\phpg\posx9163\pvpg\posy9471\absw646\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (B
CD, \par
}
The 74147 translates from decimals into the BCD code. \par
}
At a given time, an encoder may have
\par}{\phpg\posx1465\pvpg\posy10817\absw3476\absh724 \sl-242 \f20 \fs18 \cf0 uni

que output.
}
(one, many) active input(s) which produceb) a \par
}
cf0 7.2 \par
}
16 \cf0 By definition an encoder will have only one input activated at any gi
ven time.{\b \fs17 If} several inputs appear
be activated{\b by} having{\b \fs17 LOWS,} the highest decimal number{\fs16
will} be encoded{\fs17 on} a unit such as the 74147
\par}{\phpg\posx1467\pvpg\posy11683\absw8300\absh1025 \sl-211 \f20 \fs16 \cf0 en
coder.
0 {\fs18 In}{\fs18 Fig.}{\fs18 7-3a,}{\fs18 if}{\fs18 input}{\fs18 3}{\fs1
8 is}{\fs18 activated}{\fs18 with}{\fs18 a}{\fs18
(HIGH,}{\fs
18 LOW),}{\fs18 the}{\fs18 BCD}{\fs18 output}{\fs18 indicators }\par
}
ill read
}
four bits). \par
}
cf0 7.3 \par
}
A{\fs17 LOW} at input{\b \fs17 3} will produce a 0011 at the output i
ndicators. \par
}
. 71 \par
}
DE{\b \fs17 CONVERSION }\par
}
\par
}
f0 7.4 \par
}
f both inputs{\fs18 4} and{\i \fs19 5} are activated with LOWS, the output i
ndicators shown in Fig.{\fs18 7-3a} will \par
}
ad

}
{\phpg\posx2607\pvpg\posy1599\absw935\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (f
our bits). \par
}
he 74147 encoder gives priority to input{\fs17 5,} producing a 0101 output
on the BCD indicators. \par
}
f0 7.5 \par
}
efer to Fig.{\fs18 7-4.} A logical
}
0,{\fs19 1)}{\fs18 is}{\fs18 needed}{\fs18 to}{\fs18 activate}{\fs18 inpu
t}{\fs18 1. }\par
}
\cf0 A{\b0 logical}{\b0 \fs17 0}{\b0 \fs17 is}{\b0 needed}{\b0 to}{\b0
activate}{\b0 any}{\b0 input}{\b0 on}{\b0 the}{\b0 74147}{\b0 encoder.
}\par
}
f0 7.6 \par
}
ssume that only input{\fs19 1} is activated in the circuit of Fig.{\fs18 7-4.}
Output \par
}
e LOW because AND gate{\fs18 18} is
}
activated, dkabled). \par
}
s19 \cf0 ( A ,{\fs18 B,}{\b0\i0 \fs19 C,}{\b0 D}{\b0 )}{\b0\i0 \fs18 will }\
par
}
utput{\b\i A} will be{\fs17 LOW} because the{\fs17 AND} gate{\fs17 i
s} activated by all 1s at its inputs. \par
}
f0 7.7 \par
}
ist the outputs at the BCD indicators for each of the eight input pu
lses shown in Fig.{\fs18 7-5. }
\par}{\phpg\posx1439\pvpg\posy5598\absw8387\absh929 \sl-233 \f20 \fs18 \cf0 (Rem
ember the priority feature, which activates the highest number that has
a LOW input.)
\fi5740 {\b \fs15 BCD}{\fs14 output}{\fs15 indicators }\par
}
s{\fs13
4s}{\b \f20 \fs14
2s }\par
}
0 P \par
}
cf0 1s \par
}
\cf0 7-3{\fs19
DECODING:}{\fs19 BCD}{\fs18 TO}{\fs19 DECIMAL }
\fi360 {\fs19 A}{\i \fs19 decoder}{\b0 \fs18 may}{\b0 \fs18 be}{\b0 \fs18
thought}{\b0 \fs18 of}{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 opposite}{\b0
\fs18 of}{\b0 \fs18 an}{\b0 \fs18 encoder.}{\b0 \fs18 To}{\b0 \fs18 rever
se}{\b0 \fs18 the}{\b0 \fs18 process}{\b0 \fs18 described}{\b0 \fs18 in }
{\b0 \fs18 Sec.}{\b0 \fs18 7-2}{\b0 \fs18 would}{\b0 \fs18 produce}{\b0 \fs18
a}{\b0 \fs18 decoder}{\b0 \fs18 that}{\b0 \fs18 translated}{\b0 \fs18 from
}{\b0 \fs18 the}{\b0 \fs18 BCD}{\b0 \fs18 code}{\b0 \fs18 to}{\b0 \fs18 dec
imals.}{\fs18 A}{\b0 \fs18 block}{\b0 \fs18 diagram}{\b0 \fs18 of }
{\b0 \fs18 such}{\b0 \fs18 a}{\b0 \fs18 decoder}{\b0 \fs18 is}{\b0 \fs18 in}
{\b0 \fs18 Fig.}{\b0 \fs18 7-6.}{\b0 \fs18 The}{\b0 \fs18 BCD}{\b0 \fs18 (8
421)}{\b0 \fs18 code}{\b0 \fs18 forms}{\b0 \fs18 the}{\b0 \fs18 input}{\b0 \
fs18 on}{\b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \f
s18 decoder.}{\b0 \fs18 The}{\b0 \fs18 10 }
{\b0 \fs18 output}{\b0 \fs18 lines}{\b0 \fs18 are}{\b0 \fs18 shown}{\b0 \fs18
on}{\b0 \fs18 the}{\b0 \fs18 right.}{\b0 \fs18 Only}{\b0 \fs18 one}{\b0 \f
s18 output}{\b0 \fs18 line}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 activat
ed}{\b0 \fs18 at}{\b0 \fs18 any}{\b0 \fs18 one}{\b0 \fs18 time.}{\b0 \fs18
Indicators }
{\b0 \fs18 (LEDs}{\b0 \fs18 or}{\b0 \fs18 lamps)}{\b0 \fs18 have}{\b0 \fs18
been}{\b0 \fs18 attached}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 output}{\b0
\fs18 lines}{\b0 \fs18 to}{\b0 \fs18 help}{\b0 \fs18 show}{\b0 \fs18 which
}{\b0 \fs18 output}{\b0 \fs18 is}{\b0 \fs18 activated.}{\b0 \fs18 Inputs }
{\i \fs19 B}{\b0 \fs18 and}{\b0 \fs18 C}{\i \fs19 (}{\i \fs19 B}{\b0 \f10 \
fs14 =}{\b0 \fs18 2s}{\b0 \fs18 place,}{\b0 \fs18 C}{\b0\dn006 \f10 \fs13 =
}{\b0 \fs18 4s}{\b0 \fs18 place)}{\b0 \fs18 are}{\b0 \fs18 activated}{\b0 \f
s18 in}{\b0 \fs18 Fig.}{\b0 \fs18 7-6.}{\b0 \fs18 This}{\b0 \fs18 causes}{\
b0 \fs18 the}{\b0 \fs18 decimal}{\fs18 6}{\b0 \fs18 output}{\b0 \fs18 to}{\
b0 \fs18 be }
{\b0 \fs18 activated,}{\b0 \fs18 as}{\b0 \fs18 shown}{\b0 \fs18 by}{\b0 \fs18
indicator} 6{\b0 \fs18 being}{\b0 \fs18 lit.}{\b0 \fs18 If}{\b0 \fs18 no}{
\b0 \fs18 inputs}{\b0 \fs18 are}{\b0 \fs18 activated,}{\b0 \fs18 the}{\b0 \f
s18 zero}{\b0 \fs18 output}{\b0 \fs18 indicator}{\b0 \fs18 should }
{\b0 \fs18 light.}{\fs18 A}{\b0 \fs18 BCD}{\b0 \fs18 0011}{\b0 \fs18 input}{
\b0 \fs18 would}{\b0 \fs18 activate}{\b0 \fs18 the}{\b0 \fs18 3}{\b0 \fs18
output}{\b0 \fs18 indicator. }\par
}
\cf0 Fig.{\fs16 7-5}{\b0 \fs16
Encoder}{\b0 \fs16 pulse-train}{\b0 \fs16
problem }\par
}

\cf0 Solution:
fi354 {\b0 The}{\b0 indicators}{\b0 will}{\b0 read}{\b0 the}{\b0 follow
ing}{\b0 BCD}{\b0 (8421)outputs: }\par
}
pulse{\fs16 a}{\f10 \fs13 =}{\fs16 0000 }
\par}{\phpg\posx1439\pvpg\posy10491\absw1172\absh383 \sl-214 \f20 \fs16 \cf0 pul
se{\b\i b}{\f10 \fs13 =} 0111 \par
}
pulse{\i \f10 \fs14 c}{\dn006 \f10 \fs10 =} 0001
se{\b\i \fs17 d}{\dn006 \f10 \fs11 =} 1001 \par
}
pulse{\b\i \fs16 e}{\dn006 \f10 \fs10 =} 0111
se{\i \f10 \fs16 f}{\f10 \fs13 =} 0101 \par
}
pulse{\i \f10 \fs13 g}{\dn006 \f10 \fs10 =} 0011
se{\b\i \fs17 h}{\f10 \fs13 =}{\fs17 0000 }\par
}
\par
}
DE CONVERSION \par
}
AP.{\b\i 7 }\par
}
\cf0 Fig.{\fs17 7-7}{\b0 \fs17
Commercial}{\fs17 7442}{\b0 \fs17 BCD-to-d
ecimal}{\b0 \fs17 decoder/driver }\par
}
.{\fs17 71 }\par
}
DE CONVERSION \par
}
\par
}
\cf0 A commercial BCD-to-decimal decoder is shown in Fig.{\fs18 7-7a.}
This TTL device is given the
er{\fs18 7442} by the manufacturer. The four BCD inputs on the left of the logi
c symbol are labeled{\i \fs19 D, }
19 C,}{\i \fs19 B,} and{\b\i \f10 \fs17 A.} The{\i D} input is the{\fs18
8s} input, and the{\b\i A} input is the{\fs19 Is} input. A logical 1, or HIG
H, will
vate an input. On the right in Fig.{\fs18 7-7a} are 10 outputs from
the decoder. The small bubbles
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-234 \f20 \fs18 \cf0 atta
ched to the logic symbol indicate that the outputs are{\i \fs19 active}{
\i \fs19 LOW} outputs. They normally float
except when activated. For convenience, 10 inverters were added to the
circuit to drive the
mal-indicator lights.{\b\i \f10 \fs17 An} active output{\fs18 will} then be i
nverted to a logical 1 at the output indicators.
54 The truth table for the{\fs18 7442} decoder is in Fig.{\fs18 7-7b.} The fir
st line (representing a decimal{\fs18 0)} shows
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-244 \f20 \fs18 \cf0 all
inputs LOW{\fs21 (U.} With an input of LLLL (OOOO), the decimal{\fs18 0}
output is activated to a{\fs19 LOW}{\fs19 (L) }
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-239 \f20 \fs18 \cf0 stat
e. The bottom inverter complements this output to a HIGH, which lights decimal
output indicator
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-234 \f20 \fs18 \cf0 0.
None of the other indicators are lit. Likewise, the fifth line (representi
ng a decimal{\b \fs19 4)} shows the
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-239 \f20 \fs18 \cf0 BCD
input as LHLL (0100). Output{\fs18 4} is activated to a LOW. The LO
W is inverted in Fig.{\fs18 7-7a, }
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-236 \f20 \fs18 \cf0 ther
eby lighting output decimal indicator{\fs18 4.} This decoder then has
active HIGH inputs and active
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-237 \f20 \fs18 \cf0 LOW
outputs.
62 Consider line{\fs18 11} in Fig.{\fs18 7-7b.} The input is HLHL{\fs1
8 (1010),} and it would normally stand for a
mal{\fs18 10.} Since the BCD code does not contain that number, this is an{\i
\fs19 inualid} input and no output
\par}{\phpg\posx865\pvpg\posy1353\absw9190\absh4916 \sl-236 \f20 \fs18 \cf0 lamp
s will light (no outputs are activated). Note that the last{\fs19 six} lines
of the truth table show invalid
ts with no outputs activated.
60 The logic diagram for the{\fs18 7442} BCD-to-decimal decoder is shown in Fig
.{\fs18 7-8.} The BCD inputs are
he left, and the decimal outputs are on the right. 'The labeling at the inputs{\
fs19 is} somewhat different
that used before.
54 The{\b\i \f10 \fs17
A,} input is the most significant bit (MSB),
or the{\fs18 8s} input. The{\b\i \f10 \fs17 A,} input is the least
ificant bit (LSB), or the{\fs19 Is} input. The outputs are labeled with dec
imal numbers. The decoder's \par
}
{\phpg\posx871\pvpg\posy6660\absw6677\absh397 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ac

tive LOW outputs are shown with bars over the decimal outputs{\f10 \fs22 (9,}{
\fs35 s, }\par
}
nd{\fs18 so} forth). \par
}
\cf0 Fig.{\fs17 7-8}{\b0 \fs17
Logic}{\b0 \fs17 diagram}{\b0 of}{\fs17
7442}{\b0 \fs17 BCD-to-decimal}{\b0 \fs17 decoder }\par
}
\cf0 Assume a BCD input{\fs18 of} LLLL{\fs18 (0000)} on the decoder shown{
\fs19 in} Fig.{\fs18 7-8.} Through careful tracing
the four inputs through inverters{\fs18 12,}{\fs18 14,}{\fs18 16,} an
d{\fs18 18,} four logical{\fs19 Is} are seen{\fs18 to} be applied to
gate 1, which activates the gate and thus puts out a logical 0. All
other NAND gates are \par
}
0 146 \par
}
DE CONVERSION \par
}
AP.{\fs17 7 }\par
}
isabled by{\b \fs19 OS} at some of their inputs. In like manner, each combinati
on of inputs could be verified by
\par}{\phpg\posx863\pvpg\posy1367\absw9112\absh1747 \sl-237 \f20 \fs18 \cf0 anal
ysis of the logic diagram in Fig. 7-8 for the 7442 decoder. All 18 ga
tes shown in Fig. 7-8 are
ained inside the single IC referred to as the 7442 decoder.{\b As} is customary
, the power connections
(Vcc} and GND) to the IC are not shown in the logic diagram.
64 BCD-to-decimal decoders also are available in CMOS form from several manufac
turers. Several
\par}{\phpg\posx863\pvpg\posy1367\absw9112\absh1747 \sl-246 \f20 \fs18 \cf0 repr
esentative CMOS ICs are the 4028, 74C42 and 74HC42 BCD-to-decimal decoders.
}
f0 7.8 \par
}
efer to Fig. 7-7. When inputs{\b\i A}{\b\i ,}{\b\i \fs19 B,} and{\b\i \fs19
C} are activated by
\par}{\phpg\posx1461\pvpg\posy3428\absw5567\absh729 \sl-242 \f20 \fs18 \cf0 (dec
imal number) will be active.

}
\cf0 (OS,{\b0 \fs18 Is),}{\b0 \fs18 output }\par
}
f0 7.9 \par
}
7 \cf0 When inputs{\b\i A}{\b\i ,}{\b\i \fs17 B,} and{\b\i C} are act
ivated by logical{\fs16 Is,} output{\fs17 7} will be active.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 7-7.}{\fs18 If}{\fs18 inputs}{\
fs18 are}{\fs18 at}{\fs18 HHHH}{\fs18 (llll),}{\fs18 which}{\fs18 output}{
\fs18 will}{\fs18 be}{\fs18 activated? }
\fs16 Solution: }
368 Input HHHH (1111) is an invalid BCD input according to the truth t
able, and therefore no outputs
\par}{\phpg\posx1461\pvpg\posy4301\absw8246\absh1421 \sl-215 \f20 \fs17 \cf0 wil
l be activated. \par
}
cf0 7.10{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 7-7.}{\
b0 \fs18 Decimal}{\b0 \fs18 output}{\b0 \fs18 indicator }
i597 {\b0 \fs18 is}{\b0 \fs18 LHLH}{\b0 \fs18 (0101). }
}
decimal number) will be lit when the input \par
}
0101 input activates output{\fs17 5,} and the inverter lights the output
{\i \fs17 5} indicator. \par
}
efer to Fig. 7-8. Gate number
\par}{\phpg\posx1469\pvpg\posy7561\absw2768\absh733 \sl-249 \f20 \fs18 \cf0 (100
0) to this logic circuit.
}
decimal number) is activated when the input is HLLL \par
}
f0 7.11 \par
}
\cf0 NAND gate{\fs17 9} is activated, producing a{\fs17 LOW} output at{\
b \fs21 8} with an HLLL (1000) input.
\b \fs18 7.12}{\fs18
List}{\fs18 the}{\i \fs19 active}{\i \fs19 output}{
\fs18 for}{\fs18 each}{\fs18 of}{\fs18 the}{\fs18 input}{\fs18 pulses}{\f
s18 shown}{\fs18 in}{\fs18 Fig.}{\fs18 7-9. }\par
}
utput \par
}
\cf0 8s \par
}
cf0 I \par
}
11 \cf0 U \par
}
\cf0 I \par
}
\cf0 h \par
}
14 \cf0 g \par
}
\cf0 f{\f20 \fs15
e }\par
}
\cf0 d \par
}
15 \cf0 c \par
}
cf0 h \par
}
\cf0 (7442) \par
}
\cf0 Fig.{\fs16 7-9}{\b0 \fs17
Decoder}{\b0 \fs17 pulse-train}{\b0 \fs17
problem }\par
}
6 \cf0 Solution:
\fi359 {\b0 \fs17 The}{\b0 \fs17 active}{\b0 \fs17 output}{\b0 \fs17 (outp
ut}{\b0\dn006 \f10 \fs11 = }
{\b0 \fs17 pulse}{\b0 \fs16 a}{\b0 \f10 \fs13 =}{\b0 \fs17 8 }
{\b0 \fs17 pulse}{\b0\i b}{\b0 \f10 \fs13 =} 3
{\b0 \fs17 pulse}{\i c}{\b0 \f10 \fs13 =}{\b0 \fs17 (no}{\b0 \fs17 active
}{\b0 \fs17 output) }\par
}
LOW){\fs17 for}{\fs17 each}{\fs17 of}{\fs17 the}{\fs17 inputs}{\fs17 s
hown}{\fs16 in}{\fs17 Fig.}{\fs17 7-9}{\fs17 is}{\fs17 as}{\fs17 follows
: }\par
}
ulse{\i \f10 \fs16 d}{\dn006 \f10 \fs11 =}{\fs16 9 }
e{\fs15 e}{\dn006 \f10 \fs11 =} 7

e{\i \f30 \fs19 f=}{\fs17 0 }\par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 1
e{\i \fs17 h}{\dn006 \f10 \fs11 =}{\b \fs16 6 }
e{\fs15 i}{\dn006 \f10 \fs11 =} 4 \par
}
ulse{\i \f10 \fs15 j }\par
}
={\f20 \fs17 (no}{\f20 \fs17 active}{\f20 \fs17 output) }\par
}
0 CHAP.{\f10 \fs17 71 }\par
}
cf0 CODE{\fs18 CONVERSION }\par
}
f0 147 \par
}
\cf0 74{\fs22 DECODING}{\fs22 RCD-TO-SEVEN-SEGMENTCODE }
fi375 {\f10 \fs18 A}{\b0 \f20 \fs19 common}{\b0 \f20 \fs19 task}{\b0 \f20 \fs1
9 for}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 digital}{\b0 \f20 \fs19 circuit}{\b0
\f20 \fs19 is}{\f10 \fs16 to}{\b0 \f20 \fs19 dccodc}{\b0 \f20 \fs20 from}{
\b0 \f20 \fs19 machine}{\b0 \f20 \fs19 languagc}{\b0 \f20 \fs18 t}{\b0 \f20 \
fs18 o}{\b0 \f20 \fs19 decimal}{\b0 \f20 \fs19 numbers.}{\f10 \fs18 A }
\b0 \f20 \fs19 common}{\b0 \f20 \fs19 output}{\b0 \f20 \fs19 device}{\b0 \f20
\fs19 uscd}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 display}{\b0 \f20 \fs19 deci
mal}{\b0 \f20 \fs19 numbcrs}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 thc}{\i \f10
\fs16 ser-en-sepnenr}{\i \f20 \fs18 dhp/uy.}{\b0 \f20 \fs19 shown}{\b0 \f20
\fs19 in}{\b0 \f20 \fs19 Fig. }
fi20 {\b0 \f20 \fs19 7-IOU.}{\f20 \fs19 The}{\b0 \f20 \fs19 seven}{\b0 \f20 \fs
19 scgmcnts}{\f20 \fs20 arc}{\b0 \f20 \fs19 labclcd}{\b0 \f20 \fs18 with}{\b
0 \f20 \fs19 standard}{\b0 \f20 \fs19 letters}{\b0 \f20 \fs19 from}{\i \f10
\fs17 u}{\b0 \f20 \fs19 through}{\fs18 g.}{\b0 \f20 \fs19 Thc}{\b0 \f20 \f
s19 first}{\b0 \f20 \fs18 10}{\b0 \f20 \fs19 displays. }
fi23 {\b0 \f20 \fs19 representing}{\b0 \f20 \fs19 decimal}{\b0 \f20 \fs19 dig
its}{\f20 \fs18 0}{\b0 \f20 \fs19 through}{\i \f10 \fs17 9.}{\b0 \f20 \fs19
are}{\b0 \f20 \fs19 shown}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 the}{\b0 \f
20 \fs19 left}{\b0 \f20 \fs19 side}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 I:i
g.}{\f20 \fs18 7-10h.}{\b0 \f20 \fs20 For}{\b0 \f20 \fs19 instance.}{\b0 \
f20 \fs18 if }
\b0 \f20 \fs19 segments}{\i \f20 \fs19 h}{\b0 \f20 \fs19 and}{\i \f10 \fs17
c}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 scvcn-segment}{\b0
\f20 \fs19 display}{\b0 \f20 \fs19 light.}{\b0 \f20 \fs20 a}{\b0 \f20 \fs19
dccimal}{\b0 \f20 \fs19 1}{\b0 \f20 \fs19 appcars.}{\b0 \f20 \fs20 If}{\b0
\f20 \fs19 segmcnts}{\i\dn006 \f10 \fs12 U.}{\b0 \f20 \fs19 h.}{\b0 \f20
\fs19 and}{\i \f10 \fs17 c }
\b0 \f20 \fs19 light.}{\b0 \f20 \fs20 a}{\b0 \f20 \fs19 decimal}{\f10 \fs18 7
}{\b0 \f20 \fs19 appears,}{\b0 \f20 \fs19 and}{\i \fs20 so}{\b0 \f20 \fs18 f
orth. }
fi381 {\b0 \f20 \fs19 Seven-segment}{\b0 \f20 \fs19 displays}{\b0 \f20 \fs18
arc'}{\b0 \f20 \fs19 manufacturcd}{\b0 \f10 \fs17 hy}{\b0 \f20 \fs19 usin
g}{\b0 \f20 \fs19 several}{\b0 \f20 \fs19 tcchnologics.}{\b0 \f20 \fs19 Ea
ch}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 thc}{\b0 \f20 \fs19 wvcn }
\b0 \f20 \fs19 scgmcnts}{\f10 \fs17 may}{\fs21 bc}{\b0 \f20 \fs20 a}{\b0 \f
20 \fs19 thin}{\b0 \f20 \fs19 filamcnt}{\b0 \f20 \fs19 which}{\b0 \f20 \fs19
glows.}{\b0 \f20 \fs19 This}{\b0 \f20 \fs18 typc}{\b0 \f20 \fs19 of}{\b0 \f
20 \fs19 display}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 callcd}{\b0 \f20 \fs19
an}{\i \f10 \fs17 incundescenr}{\b0 \f20 \fs19 display, }
fi23 {\b0 \f20 \fs19 and}{\b0 \f20 \fs18 it}{\b0 \f20 \fs19 is}{\b0 \f20 \fs1
9 similar}{\b0 \f20 \fs18 to}{\b0 \f20 \fs20 a}{\b0 \f20 \fs19 rcgular}{\b0
\f20 \fs19 lamp.}{\b0 \f20 \fs19 Another}{\f10 \fs16 typc}{\b0 \f20 \fs19 o
f}{\b0 \f20 \fs19 display}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 thc}{\b0 \f20 \f
s19 gm-dischaqc}{\i \f10 \fs17 tube,}{\b0 \f20 \fs19 which}{\b0 \f20 \fs19
opcratcs}{\f10 \fs16 at }\par
}
13 \cf0 a \par
}
13 \cf0 (a){\i0 \fs14 Segment}{\i0 \fs14 dcnrification }\par
}
\f10 \fs14 \cf0 (h){\i0 \f20 \fs16 Decimal}{\i0 number}{\i0 \f20 \fs15 with}
{\i0 \f20 \fs15 typical}{\i0 \f20 \fs16 display }
\cf0 {\i0 \f20 \fs16 Fig.}{\i0 \fs15 7-10}{\i0 \f20 \fs17
Sewn-scpmcnt}{\i0
\f20 \fs17 display }\par
}
igh voltagcs. This{\fs19 unit} gives{\b \f10 \fs18 off} an orangc glow.{\b \f
10 \fs18 A}{\b\i \f10 \fs16 flrtoreweitr}{\b\i \f10 \fs14 tithe} display gi
vcs{\b \f10 \fs17 off}{\fs20 a} grccnish glow
{\fs18 lit} and{\fs19 operates}{\b \f10 \fs16 at} low voltagcs. Thc newer
{\b\i \f10 \fs17 /iqriid.qsra/}{\b\i \f10 \fs17 di.vphv} (LCD)creates black
numbers
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-239 \f20 \fs19 \cf0 on a
silvcry background. LCD displays{\fs20 arc} extrcmcly popular on hand-hcld cal
culators.{\b \f10 \fs18 The} common
i \f10 \fs17 /i&-etnirring}{\b\i \f10 \fs17
diode} (LED) display{\fs18 giv
cs}{\b \f10 \fs17 off} a charactcristic rcddish glow whcn{\fs19 lit.} LED
displays do
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-240 \f20 \fs19 \cf0 come
{\fs19 in} several{\b colors} othcr than rcd.{\b \fs19 Thc} LED. LCD. and flu
orcsccnt displays{\fs19 arc}{\fs19 currcntly} thc{\b \f10 \fs17 most }
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-239 \f20 \fs19 \cf0 popu
lar. but liquid-crystal displays{\fs19 are} uscd in almost all solar-powcrcd a
nd battcry-opcratcd dcviccs.
80 lkcausc{\fs18 it} is quitc common and{\b \f10 \fs16 easy} to use.

thc LED{\fs18 typc}{\fs20 of} scvcn-scgmcnt display will{\b \f30 \fs21 bc
}
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-240 \f20 \fs19 \cf0 cove
red in grcatcr dctail. Figurc{\fs19 7-1}{\b\i \fs19 la} shows{\fs20 a}{\b \f
s18 5-V}{\b power} supply connected to{\b \f30 \fs14 3} single LED. When
switch{\b \f30 \fs21 (SWI)i}s closed. currcnt will{\b \f30 \fs19 flow}{\fs
20 in} the circuit and{\fs18 light}{\fs19 the} LED. About{\b 20}{\b
\f10 \fs17 mA }
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-239 \f20 \fs19 \cf0 (mil
liamperes){\fs19 of} current would flow{\fs20 in} this circuit, which is thc t
ypical currcnt draw for an LED.{\b \fs19 Thc }
0 {\f10 \fs18 130-0} (ohm) rcsistor{\fs19 is} placed{\fs20 in} thc circuit{\b
\f10 \fs17 to}{\fs19 limit} thc current{\fs19 to}{\b \fs19 20}{\b \f10 \
fs17 mA.} Without the rcsistor, thc
3 LED would bum out. LEDs typically can{\fs19 accept} only about 1.7{\b
\f30 \fs21 V} acros their terminals. Being{\fs20 a }
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-233 \f20 \fs19 \cf0 diod
e, thc LED{\fs19 is} scnsitivc{\fs20 to} polarity.{\fs19 The} cathodc{\b\i \
f30 \fs22 (K)}must{\b \f30 \fs20 bc} toward{\fs19 thc} ncgativc (GND) of rhc
4 {\fs18 power} supply.{\b \fs20 'Ihc} anodc{\b\i \f10 \fs17 (}{\b\i \f10 \fs1
7 A}{\b\i \f10 \fs17 )}must hc toward the.positivc{\fs19 of} thc powcr supply
.
80 {\b \f10 \fs18 A} scvcn-scment LED display is shown{\fs20 in} Fig.{\b \f1
0 \fs18 7-111).} Each scgmcni{\b\i \f10 \fs11
(}{\b\i \f10 \fs11 U} throu
gh{\b \f30 \fs17 g)} contains an
4 LED,{\b \f10 \fs17 as} shown by the scvcn{\fs19 symbols.} 'Ihc display show
n has all thc anodcs ticd topcthcr and coming
the right sitlc{\b \f10 \fs16 as}{\fs18 a} single connection (common anod
e). The inputs{\fs19 on}{\fs19 thc} left{\b \f10 \fs17 go}{\fs20 to} thc
various
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-240 \f20 \fs19 \cf0 scpc
nts{\fs19 of} thc display.
76 {\fs19 To} understand how scgmcnts{\fs19 of} the display{\b \fs19 3rc} act
ivatcd and lightcd. considcr thc circuit{\fs20 in} Fig.
\f10 \fs18 7-1}{\fs19 Ic.} If switch{\fs18 h}{\fs19 is}{\fs20 closed.} curre
nt{\fs19 will}{\b \f10 \fs17 flow} from GKD through the limiting rcsistor{\fs1
9 to} the{\b\i \fs19 h} scgmcnt
3 LED and{\fs19 out} thc common anodc connection{\b \f10 \fs16 to}{\fs19 the
} powcr supply.{\fs19 Only} scgmcnt{\fs18 h}{\fs19 will} light.
79 Supposc you wantcd the dccimal numhcr 7{\fs19 to} light on the display{\fs19
in} Fig. 7-1{\fs19 lc.} Switchcs{\b\i \f10 \fs17 a.}{\b\i \fs20 h.} and
i \f10 \fs15 c} would{\b \f10 \fs18 he} closed, which would{\fs18 light} thc L
ED scgmcnts U,{\b\i \fs19 h,} and{\b\i \f10 \fs16 c.} The decimal 7 would ligh
t{\fs20 on} the
\par}{\phpg\posx802\pvpg\posy7568\absw9154\absh5590 \sl-246 \f20 \fs19 \cf0 disp
lay. Likewise.{\fs19 if} thc decimal{\b\i \f10 \fs18 5} wcrc{\b \f10 \fs17 to
} hc{\fs19 lit.} switches{\b\i \fs13 (I.}{\b\i \f10 \fs16 c.}{\b\i \fs19 d

.}{\b\i \fs20 f}{\b\i \fs20 ,} and{\b \f30 \fs19 R} would{\b he} closed.Tho
se five
cheswould ground{\fs19 thc} corrcct scpmcnts. and{\fs20 a} dccimal{\b\i \f10 \
fs19 5} would appear{\fs19 on} thc display. Notc that
4 {\fs17 it} t:ikcs a{\b \f10 \fs17 GND} voltagc{\b \f10 \fs18 (LOW)}{\b \f10
\fs16 to} activatc thc LED segments{\fs20 on}{\fs19 this} display. \par
}
{\phpg\posx811\pvpg\posy528\absw420\absh210 \f10 \fs18 \cf0 \f10 \fs18 \cf0 1-48
\par
}
f0 [CHhP.{\fs17 7 }\par
}
\cf0 I \par
}
cf0 Fig.{\fs14 7-1}{\f20 \fs16 I }\par
}
'onsidcr{\b
the}{\b \f10 \fs15
co~iii~iori }
}{\phpg\posx1165\pvpg\posy8771\absw8376\absh209 \f20 \fs18 \cf0 \fi0 coniiiicrci
al{\fs18
dccodcr}{\b \f10 \fs15
sliowri}{\fs19 in}{\fs16
1:ig.} 7-{\
fs18 13u.} This{\b \f10 TTI,} dcvicc is{\b \fs18 called }\par
}
47A H~:l)-to-scvcn-scpmcnt dccodcr/drivcr{\b \f10 \fs17
by}{\fs18 the}
ni;iiiuf;ictiircr. The input{\b \fs17
is }\par
}
{\phpg\posx815\pvpg\posy9241\absw5972\absh218 \f20 \fs18 \cf0 \f20 \fs18 \cf0 nu
mber shown{\b \fs19 on} the{\fs18 Icft} (inputs{\b\i \f10 \fs17
A.}{\
b\i \f30 \fs20 H.}{\f10 \fs14 ('.} and{\b \fs17
/I).} Thc{\b \fs18
l3
C'I) }\par
}
cf0 ;I \par
}
cf0 ;i \par
}
{\phpg\posx8697\pvpg\posy9017\absw925\absh205 \f20 \fs18 \cf0 \f20 \fs18 \cf0 4bit{\b \fs17
IX'I) }\par
}
umbcr{\fs17
is} dccodcd{\fs17
t}{\fs17 o}{\fs18 form}{\b \f10 \fs15
a }\par
}
\cf0 seven-scgnicnt{\fs17 code}{\b0 \f20 \fs17 that}{\b0 \f20 \fs17 will}{
\b0 \f20 \fs18 light} the{\b0 \f20 \fs18 ;tppropriatc}{\fs15 scgniciits}{
\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\f20 \fs19 1,t;D}{\b0 \f20 \fs18 dis
play}{\b0 \f20 \fs18 hhown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 1:ig.}{\b0 \f
20 \fs18 7-1}{\b0 \fs17 1}{\i \fs17 h. }
\b0 \f20 \fs18 'Three}{\b0 \f20 \fs18 extra}{\b0 \f20 \fs18 inpiits}{\i\dn00
6 \fs12 iIlS<)}{\b0 \f20 \fs19 arc}{\b0 \f20 \fs18 shoum}{\f20 \fs18 on}{\b
0 \f20 \fs18 the}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 symbol.}{\b0 \f20 \fs
18 The}{\b0 \f20 \fs18 lamp}{\fs14 test}{\b0 \f20 \fs18 input}{\b0 \f20 \f
s18 will}{\b0 \f20 \fs18 turn}{\b0 \f20 \fs17 all}{\f20 \fs18 segments}{\i
\f30 \fs19 0}{\i \f30 \fs19 3 }
\b0 \f20 \fs18 to}{\fs16
sec}{\f20 \fs19 if}{\f20 \fs19 all}{\b0 \f20 \fs
19 o}{\b0 \f20 \fs19 f}{\b0 \f20 \fs18 them}{\b0 \f20 \fs18 operate.}{\b0
\f20 \fs18 F.sscnti;illy,}{\b0 \fs15 thc}{\b0 \f20 \fs18 hlanking}{\b0 \f
20 \fs18 inputs}{\b0 \f20 \fs19 turn}{\b0 \f20 \fs18 all}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 wgmcnts}{\b0 \f20 \fs19 0I:F}{\b0 \f20 \fs18
when }
\b0 \f20 \fs18 activated.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 Iiinlp}{\fs15 t
est}{\b0 \f20 \fs18 iInd}{\b0 \f20 \fs17 hl;inking}{\b0 \f20 \fs18 input5}
{\f20 \fs17 ;ire}{\b0 \f20 \fs18 activ;itctl}{\f30 \fs18 by}{\fs16 l.OW\\.}
{\f20 \fs15 ;is} s h o w n{\b0 \f20 \fs17 by}{\b0 \fs15 tlic}{\fs17 sniall
}{\b0 \f20 \fs19 bubbles}{\fs15 at }
\b0 \f20 \fs18 the}{\b0 \f20 \fs18 inputs.}{\b0 \f20 \fs18 T}{\b0 \f20 \fs18
h}{\b0 \f20 \fs18 c}{\f20 \fs19 BCI)}{\b0 \f20 \fs18 inputs}{\b0 \f20 \fs1
8 arc}{\b0 \f20 \fs18 activated}{\f20 \fs17 by}{\b0 \f20 \fs18 lopicxl}{\
b0 \f20 \fs17 Is.}{\b0 \f20 \fs18 'I'hc}{\b0 \f20 \fs18 7447A}{\b0 \f20 \fs
18 dccodcr}{\fs15 h}{\fs15 a}{\fs15 s}{\f20 \fs18 active}{\b0 \f20 \fs19
LOW}{\f20 \fs17 outputs, }
\f30 \fs13 ;IS}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs17 by}{\b0 \f20 \fs18 the}
{\f20 \fs17 sniall}{\b0 \f20 \fs18 bubbles}{\b0 \f20 \fs17 at}{\b0 \f20 \f
s18 the}{\b0 \f20 \fs18 outputs}{\i \fs11 (}{\i \fs11 (}{\i \fs11 I}{\b0
\f20 \fs18 through}{\f30 \fs17 I:)}{\b0 \f20 \fs19 of}{\b0 \f20 \fs18 the}
{\b0 \f20 \fs18 logic}{\fs16 symbol}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig
.}{\b0\i \f20 \fs18 i-l3(i. }
fi355 {\b0 \f20 \fs18 Thc}{\b0 \f20 \fs18 operation}{\f20 \fs18 o}{\f20 \fs18
f}{\f20 \fs17 the}{\b0 \f20 \fs18 7-447A}{\b0 \f20 \fs18 dccodcr}{\f20 \fs1
6 is}{\b0 \f20 \fs18 dctailcd}{\b0 \f20 \fs18 i}{\b0 \f20 \fs18 n}{\b0 \fs1
5 tlic}{\f20 \fs16 trutli}{\b0 \f20 \fs18 table}{\b0 \f20 \fs18 furnishe
d}{\b0 \f20 \fs17 by}{\f20 \fs18 I'cxiis}{\b0 \f20 \fs18 lnstrunicnts }
\b0 \f20 \fs18 and}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs19 in}{\f20 \fs16 F3g
.}{\b0 \f20 \fs18 7-12h.}{\b0 \f20 \fs18 (:orisider}{\b0 \f20 \fs18 line}{\b
0 \fs17 1}{\f20 \fs19 on}{\fs16 thc}{\b0 \f20 \fs18 truth}{\f20 \fs19 ti
thlc.}{\b0 \f20 \fs19 To}{\b0 \f20 \fs18 light}{\b0 \f20 \fs18 the}{\b0 \f20
\fs18 dccimal}{\i \f20 \fs17 0}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\b0
\f20 \fs18 display.}{\b0 \f20 \fs18 the }
\f20 \fs18 UCL)}{\b0 \f20 \fs18 inputs}{\i \fs17 (D.}{\b0 \f20 \fs17 C'.}{\b0
\i \fs17
U.}{\fs17 and}{\i \fs17 A}{\fs15 1}{\b0 \f20 \fs18 must}{\fs16
be} at{\fs17 LLLL.}{\b0 \f20 \fs18 'l'his}{\fs17 will}{\b0 \f20 \fs18
activate}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 turn}{\f30 \fs20 O}{\f30 \fs20 N
}{\b0 \f20 \fs18 segments}{\i\dn006 \fs11
(1,}{\i \fs17 h.}{\i \fs15 c.}{
\i \f20 \fs17 tl.}{\i \f20 \fs13 P}{\i \f20 \fs13 . }
\f20 \fs18 and}{\b0\i \f30 \fs21 f}{\fs14 t}{\fs14 o}{\f20 \fs16 fomi}{\b0
\fs16 111c}{\b0 \f20 \fs18 dccini;il}{\fs15 (1}{\dn006 \f20 \fs12 0}{\dn0
06 \f20 \fs12 1}{\f20 \fs12 1}{\b0 \fs14 tlic} sc\\'cn-xgniciit{\b0 \f20 \f
s18 diqhy.}{\f20 \fs18 Kotc}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 invalid}{\b
0 \f20 \fs18 13('I)}{\b0 \f20 \fs18
inputs}{\b0 \f20 \fs18 (decimals}{\fs16
10. }
fi34 {\b0 \f20 \fs19 11.}{\b0 \f20 \fs19 12,}{\b0 \fs18 13.}{\b0 \f20 \fs18
14.}{\i\dn006 \fs12 illid}{\b0 \f20 \fs18 15).}{\b0 \f20 \fs18 They}{\b0

\f20 \fs18 arc}{\f20 \fs18 not}{\f20 \fs19 I3C1)}{\b0 \f20 \fs18 numbers
.}{\b0 \f20 \fs18 however.}{\b0 \f20 \fs18 they}{\b0 \f20 \fs17 do}{\b0 \f
20 \fs18 pcncratc}{\dn006 \f20 \fs11
;I}{\b0 \f20 \fs18 unique}{\b0 \f20 \
fs18 output,}{\f30 \fs16 ;is }
\b0 \f20 \fs18 shown}{\b0 \f20 \fs19 in}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
truth}{\f20 \fs18 tahlc}{\b0 \f20 \fs18 in}{\f20 \fs17 Fig.}{\b0 \fs17 7-1
2h.}{\b0 \f20 \fs18 ('onsidcr}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 decimal}{\
f30 \fs18 I0}{\b0 \f20 \fs18 line.}{\b0 \f20 \fs18 With}{\b0 \f20 \fs18 inp
uts}{\f20 \fs18 of}{\f20 \fs19 ItLItL.}{\b0 \f20 \fs18 thc}{\b0 \f20 \fs18 o
utput }\par
}
olumn{\b \f10 \fs15 say\\} that{\b \fs17 outputs}{\b\i \fs17 tl,}{\fs17
v,}{\b \f10 \fs16 and}{\b \f10 \fs13 ,g} arc ;ictiviitctl. Thi5{\fs17 for
ni> }\par
}
ccodcr{\fs18 for} decimals{\b \f10 \fs16
10} through{\fs18 15} ;ire shown{
\b\dn006 \fs12
;is }\par
}
he{\fs18 right}{\fs18 sidc}{\b \fs18 of}{\fs18 Fig.}{\fs18 7-10b.}{\b \f
s18 Note}{\fs18 that }\par
}
{\b \fs12
sni:ill }\par
}
\cf0 c.{\i0 \fs18 'I'hc}{\i0 unique}{\i0 outputs}{\b\i0 \fs18 o}{\b\i0 \
fs18 f}{\i0 this }\par
}
they would iippcar{\b \f10 \fs16 on} the{\b \f10 \fs16 seven-scgnicnt} disp
lay on \par
}
\cf0 ;I{\b0 \f20 \fs18 decimal}{\b0 \fs18 15}{\b0 \f20 \fs18 will}{\b0 \f20
\fs18 rcsult}{\b0 \f20 \fs18 i}{\b0 \f20 \fs18 n }\par
}
\cf0 ;t{\i \f20 \fs12
thiiik }\par
}
isplay{\fs12
(;ill }\par
}
segments{\b \f10 \fs17 OFF). }\par
}
\cf0 A{\b0 \f20 \fs18 practic;il}{\b0 \f20 \fs18 tlccotlcr}{\b0 \fs15 >>\
\tcni}{\f20 is}{\dn006 \f20 \fs12
5liowri }\par
}
in{\fs18 Ia'ig.} 7-13.{\b \f10 \fs17 A}{\b \fs19 t3CD}{\fs18 numhcr}{\f
s18 is}{\f10 \fs16 ciitcrcd }\par
}
\cf0 iit{\b0 \fs18 the}{\b0 \fs18 Icft}{\b0 \fs18 into}{\b0 \fs18 the }\
par
}
\cf0 7U7A{\b0 \f20 \fs18 dccodcr.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 dccodcr
}{\b0 \f20 \fs18 activates}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 proper}{\b0
\f20 \fs18 outputs}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 alto\\vs}{\b0 \f20 \
fs18 the}{\b0 \f20 \fs18 correct}{\b0 \f20 \fs18 dccimiil}{\b0 \f20 \fs18
number}{\b0 \f20 \fs17
t}{\b0 \f20 \fs17 o }
\b0 \f20 \fs18 appcar}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 thc}{\b0 \f20 \fs18
displa).}{\b0 \fs17 Note}{\fs15 that}{\b0 \f20 \fs18 the}{\f20 \fs18 di
splny}{\b0 \f20 \fs16 is}{\fs15 a}{\b0 \f20 \fs18 common-anode}{\b0 \f20 \f
s18 seven-segment} 1.F.I){\b0 \f20 \fs18 display. }\par
}
}
}
\par
}
{\phpg\posx4197\pvpg\posy1591\absw339\absh227 \f10 \fs19 \cf0 \f10 \fs19 \cf0 fb \par
}
mber \par
}
puts \par
}
{\phpg\posx3515\pvpg\posy2672\absw767\absh424 \f20 \fs15 \cf0 \f20 \fs15 \cf0 La
mp-test
3 Blanking \par
}
cf0 ~C
i93 {\f10 \fs14 D }
0 \fi86 {\fs14 LT }
0 \fi86 {\fs14 BI/RBO }\par
}
\i \fs14 d- }
\i \fs13 e- }\par
}
\cf0 output
0 \fs19 >} 7-segment code \par
}

lanking{\fs10
4}{\i \fs14 RBI}
(7447) \par
}
f0 g \par
}
0 ( U ) \par
}
{\phpg\posx5013\pvpg\posy3760\absw945\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Lo
gic symbol \par
}
\cf0 H{\b0 \f10 \fs11 =} HIGH{\b0 \fs15 level,}{\b0 \fs15 L}{\b0 \f10 \fs1
3 =}{\b0 \fs15 LOW}{\b0 \fs15 level,}{\f30 \fs16 X }\par
}
{\f20 \fs15 irrelevant }\par
}
Notes:{\fs15 1.} The blanking input{\i (BI)}must be open or held at a{\b \fs
15 HIGH} logic level when output functions{\b \fs15 0} through{\fs15 15} are
desired.
i735 The ripple-blanking input{\i (RBI)}must be open{\fs14 or}{\b \fs15 H
IGH} if blanking{\b of} a decimal zero is not desired.
i546 {\b\i \fs15 2.} When a LOW logic level is applied directly to the blanking
input{\i (BI),}all segment outputs are{\b \fs15 OFF} regardless{\fs15 of }
i740 the level of any other input.
i548 {\b \fs14 3.} When ripple-blanking input{\i \fs15 (RBI)}and inputs{\b\i
\fs14 A,}{\i \fs15 B,} C, and{\b\i \f10 \fs14 D} are at a LOW level with
the lamp-test input{\b \fs15 HIGH, }
i740 all segment outputs{\b\i \fs15 go}{\fs15 OFF} and the ripple-blanking o
utput{\i \fs15 (RBO)}goes{\fs14 to} a LOW level (response condition).
i546 {\b \f10 \fs14 4.} When the blanking input/ripple-blanking output{\b\i
(BIIRBO)} is open or held{\b \fs15 HIGH} and a LOW is applied to the
i742 lamp-test input, all segment outputs are{\fs14 ON. }
0 \fi2456 {\b\i (b)} Truth table{\i \fs15 (Reprinted}{\i \fs14 by}{\i \fs15
permission}{\i \fs15 of}{\i \fs15 Taus}{\i \fs15 Instruments,}{\i \fs15 I
nc.) }
0 \fi1592 {\b \fs16 Fig.}{\b \fs16 7-12}{\fs17
Commercial}{\fs17 7447}{\fs1
7 BCD-}{\fs17 to-seven-segment}{\fs17 decoder/driver }\par
}
\par
}
DE CONVERSION \par
}

AP.{\fs17 7 }\par
}
14 \cf0 + 5 \par
}
{\phpg\posx4339\pvpg\posy1338\absw128\absh235 \f20 \fs20 \cf0 \f20 \fs20 \cf0 v
\par
}
14 \cf0 + 5{\b0\i0 \f20 \fs20 v }\par
}
\par
}
I
\par}{\phpg\posx4235\pvpg\posy1846\absw60\absh252 \sl-197 \b \f10 \fs5 \cf0 \fi2
3 {\b0 \fs7 < }\par
}
ecimal output \par
}
\par
}
cf0 BCD
b0 input }\par
}
\fs13 \cf0 1s
f0 {\f20 \fs15 2s }
f0 {\fs13 4s }
f0 {\fs13 8s }\par
}
cf0 a
0 {\fs14 b }\par
}
\cf0 U \par
}
coder \par
}
14 \cf0 d \par
}
{\phpg\posx7705\pvpg\posy2648\absw705\absh330 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Co
mmon
6 anode \par
}
17 \cf0 D{\i0 \f10 \fs13

(7447A) }
\fi423 {\b0\i0 \f20 \fs15 GND }
\fi560 {\b0\i0 \f10 \fs19 - }\par
}
20 \cf0 f
\fi27 {\b0\dn006 \f10 \fs12 g}{\b0\i0 \f10 \fs19 - }\par
}
cf0 150{\b0 \f20 \fs15 R }\par
}
0 \fs16 \cf0 Fig.{\f10 \fs16 7-13}{\b0 \fs17
Wiring}{\b0 \fs17 of}{\b0 \fs1
7 decoder}{\b0 \fs17 and}{\b0 \fs17 seven-segment}{\b0 \fs17 LED}{\b0 \fs17
display }
f0 \fi368 {\b0 \fs18 Suppose}{\b0 \fs18 the}{\b0 \fs18 inputs}{\b0 \fs18 to
}{\b0 \fs18 the}{\b0 \fs18 decoder}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \
fs18 Fig.}{\b0 \fs18 7-13}{\b0 \fs18 are}{\b0 \fs18 LLLH}{\b0 \fs19 (000
1).}{\b0 \fs18 This}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 code}{\b0 \fs18
for}{\b0 \fs18 a }
\b0 \fs18 decimal}{\b0 \fs18 1.}{\b0 \fs18 According}{\b0 \fs18 to}{\b0 \fs1
8 the}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 for}{\b0 \fs18 the}{\b0
\fs18 7447A}{\b0 \fs18 decoder,}{\b0 \fs18 this}{\b0 \fs18 combination}{\b
0 \fs18 of}{\b0 \fs18 inputs}{\b0 \fs18 turns}{\b0 \fs18 ON }
\b0 \fs18 segments}{\i \fs19 b}{\b0 \fs18 and}{\b0 \fs17 c.}{\b0 \fs18 A}{
\b0 \fs18 decimal}{\b0 \fs18 1}{\b0 \fs18 is}{\b0 \fs18 formed.}{\b0 \fs18
Note}{\b0 \fs18 that,}{\b0 \fs18 when}{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \
fs18 table}{\b0 \fs18 says}{\b0 \fs18 ON,}{\b0 \fs18 it}{\b0 \fs18 means}{\
b0 \fs18 that}{\b0 \fs18 the }
\b0 \fs18 output}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 7447A}{\b0 \fs18 de
coder}{\b0 \fs18 has}{\b0 \fs18 gone}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18
LOW}{\b0 \fs18 active}{\b0 \fs18 state.}{\b0 \fs18 It}{\b0 \fs18 might}{\b
0 \fs18 also}{\b0 \fs18 be}{\b0 \fs18 said}{\b0 \fs18 that}{\b0 \fs18 the}{
\b0 \fs18 segment }
\b0 \fs18 is}{\b0 \fs18 being}{\b0 \fs18 grounded}{\b0 \fs18 through}{\b0
\fs18 the}{\b0 \fs18 decoder.}{\b0 \fs18 The}{\b0 \fs18 seven}{\b0 \fs19
150-0}{\b0 \fs18 resistors}{\b0 \fs18 limit}{\b0 \fs18 the}{\b0 \fs18
current}{\b0 \fs18 from}{\b0 \fs18 GND }
\b0 \fs18 through}{\b0 \fs18 the}{\b0 \fs18 LED}{\b0 \fs18 segment}{\b0 \fs18
to}{\b0 \fs18 a}{\b0 \fs18 safe}{\b0 \fs18 level.}{\b0 \fs18 Recall}{\b0 \
fs18 that}{\b0 \fs18 the}{\b0 \fs18 7447A}{\b0 \fs18 was}{\b0 \fs18 descri
bed}{\b0 \fs18 as}{\b0 \fs18 a}{\b0 \fs18 decoder/driuer. }
\b0 \fs18 The}{\b0 \fs18 driver}{\b0 \fs18 description}{\b0 \fs18 suggests
}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 current}{\b0 \fs18 from}{\b0
\fs18 the}{\b0 \fs18 display}{\b0 \fs18 LED}{\b0 \fs18 flows}{\b0 \fs18
directly}{\b0 \fs18 through}{\b0 \fs18 the }
\b0 \fs18 7447A}{\b0 \fs18 IC.}{\b0 \fs18 The}{\b0 \fs18 decoder}{\b0 \fs18
is}{\b0 \fs18 directly}{\b0 \fs18 driuing}{\b0 \fs18 the}{\b0 \fs18 display.
}{\b0 \fs18 The}{\b0 \fs18 7447A}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0 \fs18 sai
d}{\b0 \fs18 to}{\b0 \fs18 be}{\b0 \fs18 sinking}{\b0 \fs18 the}{\b0 \fs18
current }
\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 display. }
fi368 {\b0 \fs18 It}{\b0 \fs18 is}{\b0 \fs18 assumed}{\b0 \fs18 in}{\b0 \f
s18 Fig.}{\b0 \fs18 7-13}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 two}{
\b0 \fs18 blanking}{\b0 \fs18 inputs}{\b0 \fs19 (}{\b0 \fs19 R}{\b0 \fs19
B}{\b0 \fs19 Z}{\b0 \fs18 and}{\b0\i \fs19 BI/RBO)}{\b0 \fs18 plus}{\b0 \f
s18 the}{\b0 \fs18 lamp}{\b0 \fs18 test }
\b0 \fs18 input}{\b0 \fs18 are}{\b0 \fs18 allowed}{\b0 \fs18 to}{\b0 \fs18 f
loat}{\b0 \fs18 HIGH.}{\b0 \fs18 They}{\b0 \fs18 are}{\b0 \fs18 therefore}{\
b0 \fs18 not}{\b0 \fs18 active}{\b0 \fs18 and}{\b0 \fs18 not}{\b0 \fs18 s
hown}{\b0 \fs19 on}{\b0 \fs18 the}{\b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \f
s18 in }
\b0 \fs18 Fig.}{\b0 \fs18 7-13. }
fi368 {\b0 \fs18 Many}{\b0 \fs18 CMOS}{\b0 \fs18 display}{\b0 \fs18 decoders}
{\b0 \fs18 are}{\b0 \fs18 available.}{\b0 \fs18 One}{\b0 \fs18 example}{\b0
\fs18 is}{\b0 \fs18 the}{\b0 \fs18 CMOS}{\b0 \fs18 74C48}{\b0 \fs18 BCDto-seven- }
\b0 \fs18 segment}{\b0 \fs18 decoder,}{\b0 \fs18 which}{\b0 \fs18 is}{\b0 \fs
18 similar}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 TTL}{\b0 \fs18 7447A}{\b
0 \fs18 IC.}{\b0 \fs18 The}{\b0 \fs18 74C48}{\b0 \fs18 IC}{\b0 \fs18 does}{
\b0 \fs18 need}{\b0 \fs18 extra}{\b0 \fs18 drive}{\b0 \fs18 circuitry }
\b0 \fs18 for}{\b0 \fs18 most}{\b0 \fs18
LED}{\b0 \fs18 displays.}{\b0 \f
s18 Other}{\b0 \fs18 examples}{\b0 \fs18 of}{\b0 \fs18
CMOS}{\b0 \fs18
decoder}{\b0 \fs18
ICs}{\b0 \fs18 are}{\b0 \fs18 the}{\b0 \fs18 4511}
{\b0 \fs18 and}{\b0 \fs18
74HC4511 }
\b0 \fs18 BCD-to-seven-segment}{\b0 \fs18
latch/decoder/driver.}{\b0 \fs18
The}{\b0 \fs18 CMOS}{\b0 \fs18 4543}{\b0 \fs18 and}{\b0 \fs18 74HC4543}{\
b0 \fs18 BCD-to-seven-seg- }
\b0 \fs18 ment}{\b0 \fs18 latch/decoder/driver}{\b0 \fs18
for}{\b0 \fs18 l
iquid-crystal}{\b0 \fs18 displays}{\b0 \fs18 are}{\b0 \fs18 also}{\b0 \fs18
sold}{\b0 \fs18 in}{\b0 \fs18 convenient}{\b0 \fs18 DIP}{\b0 \fs18 IC}{\b0 \
fs18 form. }\par
}
LVED PROBLEMS \par
}
f0 7.13 \par
}
efer to Fig. 7-lla. Turn just the{\fs19 5-V} battery around and the LED will
\par}{\phpg\posx1459\pvpg\posy9988\absw6147\absh969 \sl-237 \f20 \fs18 \cf0 as b
efore.
51 {\fs17 The}{\fs17 LED}{\fs16 will}{\fs17 not}{\fs17 light}{\fs17 as}{
\fs17 before}{\fs17 because}{\fs16 it}{\fs16 is}{\fs17 sensitive}{\fs17
to}{\fs17 polarity. }\par
}

Refer to Fig. 7-llc. A \par
}
light, not light) \par
}
cf0 7.14 \par
}
(GND,{\fs19 +5-V)} voltage is applied to the cathodes of the LED \par
}
segments through the switches and limiting resistors.
358 {\b \fs17 A}{\fs17 GND}{\fs17 voltage}{\fs17 is}{\fs17 applied}{\fs17
to}{\fs17 the}{\fs17 cathodes}{\fs17 of}{\fs17 the}{\fs17 LED}{\fs17 se
gments}{\fs17 when}{\fs17 a}{\fs17 switch}{\fs17 shown}{\fs17 in}{\fs17 F
ig.}{\fs16 7-llc}{\fs17 is }
s17 closed. }\par
}
cf0 7.15 \par
}
Refer to Fig. 7-11c. When switches{\fs18 6,}{\b\i \fs18 c,}{\fs18 f,} and
{\b\i \fs17
g} are closed, a(n)
\par}{\phpg\posx1441\pvpg\posy13199\absw5940\absh421 \sl-233 \f20 \fs18 \cf0 wil
l be displayed on the seven-segment LED display. \par
}
(decimal number) \par
}
. 71 \par
}
DE CONVERSION \par
}
\par
}
\cf0 Solution:
fi360 {\b0 \fs17 Lighting}{\b0 \fs17 segments}{\b0\i \fs17 b,}{\b0 \fs16 c,
}{\b0\i \f10 \fs16 f,}{\b0 \fs17 and}{\i \fs15 g}{\b0 \fs17
will}{\b0 \f
s17 form}{\b0 \fs17 a}{\b0 \fs17 4}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \
fs17 display. }\par
}
f0 7.16 \par
}
efer to Fig. 7-11c. When switches{\i \fs19 b} and c are closed, a(n)
\par
}
isplayed, and about
}
decimal number) is \par
}
1, 40) mA of current will be drawn by the{\fs19 LEDs. }\par
}
\cf0 Lighting segments{\i \fs17 h} and{\f10 \fs14 c} will form a 1 on
the display, which will cause about 40 mA of current to
drawn by the LEDs. \par
}
f0 7.17 \par
}
efer to Fig. 7-12b.{\fs19 To} display a decimal 2, the{\fs19 BCD} inputs mus
t be \par
}
\cf0 (H, L), which will turn{\fs18 ON} segments
}
list all{\fs18 ON} segments). \par
}
isplaying a decimal{\b\i \fs17 2} requires a BCD input of LLHL, which
turns on segments{\i \f10 \fs14 a,}{\i \fs16 b,}{\b\i d,}{\b\i \fs17 e,
} and{\b\i \fs15 g}{\b\i \fs15 . }\par
}
f0 7.18 \par
}
nvalid{\fs19 BCI)} inputs on the 7447A decoder produce
\par}{\phpg\posx1457\pvpg\posy6142\absw4693\absh718 \sl-233 \f20 \fs18 \cf0 seve
n-segment display.
}
OFF,{\fs18 unique)}{\fs18 readings}{\fs18 on}{\fs18 the }\par
}
\cf0 Invalid BCD inputs (10,11, 12,13,14, and{\fs17 15)}on the 744714 decod
er produce unique readings on the
lay.{\b \fs16 See} Fig. 7-10h. \par
}
f0 7.19 \par
}
ist the decimal indication of the seven-segment display for each input pulse i
n Fig. 7-14. \par
}
- \par
}
13 \cf0 A
cf0 {\f30 \fs17 B }
cf0 {\f30 \fs16 C }\par
}
\fs17 \cf0 c:
0 {\f20 \fs15 Decoder }\par
}
\fs13 \cf0 150{\f30 \fs17 R}{\i \f30 \fs15 a }
f0 \fi833 {\i \f30 \fs15 b }
\b0 \f20 \fs23 4 }
fi833 {\i \f30 \fs15 d }\par
}
\cf0 f
f0 {\b\i0\up006 \fs14 g}{\i0\dn006 \f10 \fs13 y}{\i0 \f10 \fs19 - }\par
}
13 \cf0 + 5{\b0\i0 \f20 \fs20 v }\par
}
\f20 \fs20
v }\par
}
s14 \cf0 d \par
}
s15 \cf0 j \par
}
s15 \cf0 i \par
}
s15 \cf0 h \par
}
s15 \cf0 g \par
}
s15 \cf0 f \par
}
s15 \cf0 e \par
}
s15 \cf0 d \par
}
s15 \cf0 c \par
}
s15 \cf0 b \par
}
s15 \cf0 a \par
}
\f30 \fs17 \cf0 D{\i0 \f20 \fs14
(7447A) }
0 {\i0 \f20 \fs13 1_}{\i0 \f20 \fs15
GND }\par
}
\par
}
\cf0 Fig.{\f10 \fs15 7-14}{\b0 \fs17
Decoder-display}{\b0 \fs17 pulse-trai
n}{\b0 \fs17 problem }\par
}
\cf0 Solution:
\fi350 {\b0 \fs17 The}{\b0 \fs17 decimal}{\b0 \fs17 outputs}{\b0 \fs17 for}
{\b0 \fs17 the}{\b0 \fs17 various}{\b0 \fs17 input}{\b0 \fs17 pulses}{\b0
\fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 7-14}{\b0 \fs17 are}{\b0 \fs17 as}
{\b0 \fs17 follows: }\par
}
ulse{\b\i \f30 \fs12 U}{\dn006 \f10 \fs11
=}{\fs16 9 }
e{\fs16 b}{\dn006 \f10 \fs11 =} 3
e{\f10 \fs14 c}{\dn006 \f10 \fs11 =}{\i \fs17 5 }
e{\i \f10 \fs16 d}{\dn006 \f10 \fs11 =}{\fs16 8 }\par
}
pulse{\b\i \fs16 e}{\dn006 \f10 \fs11 =}{\b 2 }
se{\i \f10 \fs16 f}{\dn006 \f10 \fs11 =} display blank (invalid BCD inpu
t)
se{\fs15 g}{\dn006 \f10 \fs11 =}{\fs16 0 }
se h{\dn006 \f10 \fs10 =} 7 \par
}
ulse{\fs15 i }\par
}
={\b \f30 \fs12 U}{\f20 \fs17 (invalid}{\f20 \fs17 BCD}{\f20 \fs17 input)
}\par
}
ulse{\fs15 j}{\dn006 \f10 \fs11 =}{\b \fs16 6 }\par

}
\par
}
DE CONVERSION \par
}
AP.{\fs17 7 }\par
}
f0 7.20 \par
}
ist the segment of the seven-segment display that will be lit for each of the pu
lses in Fig. 7-14.
60 {\fs16 The}{\fs16 lit}{\fs16 segments}{\fs17 on}{\fs16 the}{\fs16 se
ven-segment}{\fs16 display}{\fs16 in}{\fs16 Fig.}{\fs17 7-14}{\fs16 are}{
\fs16 as}{\fs16 follows: }
16 pulse}{\fs16 a}{\f10 \fs13 =}{\i \f10 \fs14 a,}{\i \fs17 b,}{\fs16 c,}
{\fs17 f,}{\fs15 g}{\fs16
pulse}{\i \f30 \fs19 f=}{\fs16 d
isplay}{\fs16 blank}{\fs16 (invalid}{\fs16 BCD}{\fs16 input) }\par
}
lse{\i \fs17 b }
{\i \f10 \fs14 c }\par
}
{\i \fs15 a,}{\i \f20 \fs17 b,}{\i \f20 \fs18 c,}{\i \fs16 d,}{\f20 \fs15 g
}
10 =}{\i \fs14 a,}{\f20 \fs16 c,}{\i \fs16 d,}{\f20 \fs17 f,}{\f20 \fs15 g
}\par
}
lse{\fs15 g }
{\i \fs16 h }\par
}
{\i \fs14 a,}{\i \f20 \fs17 b,}{\i \f20 \fs17 c,}{\i \fs16 d,}{\f20 \fs16 e
,}{\i \f30 \fs19 f }
\par}{\phpg\posx4414\pvpg\posy2440\absw1163\absh401 \sl-217 \f10 \fs11 \cf0 ={\i
\fs14 a,}{\i \f20 \fs16 b,}{\f20 \fs16 c }\par
}
ulse d{\dn006 \f10 \fs11 =}{\i \f10 \fs14 a,}{\i \fs17 b,}{\fs16 c,}{\i \f
10 \fs16 d,}{\fs16 e,}{\fs17 f,}{\fs15 g }
e{\fs16 e}{\dn006 \f10 \fs10 =}{\i \f10 \fs13 a,}{\i \fs16 b,}{\i \f10 \fs
16 d,}{\i \fs17 e,}{\i \fs15 g }\par
}

lse{\b\i \f30 \fs18 i}{\dn006 \f10 \fs11 = }\par
}
lse{\fs15 j }\par
}
\cf0 b,{\i0 f,}{\i0 \fs15 g}{\i0 \fs16 (invalid}{\i0 \fs16 BCD}{\i0 \fs16
input) }\par
}
\f20 \fs16 c,}{\i \fs15 d,}{\i \f20 \fs16 e,}{\i \f30 \fs19 f,}{\i \f20 \fs15
g }\par
}
\cf0 7-5{\f20 \fs18
LIQUID-CRYSTAL}{\f30 \fs20 DISPLAYS }
fi360 {\b0 \f20 \fs18 Most}{\b0 \f20 \fs18 battery-}{\b0 \f20 \fs18 or}{\b0 \f
20 \fs18 solar-powered}{\b0 \f20 \fs18 electronic}{\b0 \f20 \fs18 equipment}{
\b0 \f20 \fs18 use}{\b0\i \f20 \fs18 liquid-crystal}{\b0\i \f20 \fs18 displa
ys}{\b0 \f20 \fs18 (LCDs).}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 LCD }
\b0 \f20 \fs18 in}{\b0 \f20 \fs18 your}{\b0 \f20 \fs18 calculator,}{\b0 \f20 \
fs18 wristwatch,}{\b0 \f20 \fs18 portable}{\b0 \f20 \fs18 telephone,}{\b0 \f2
0 \fs18 or}{\b0 \f20 \fs18 portable}{\b0 \f20 \fs18 computer}{\b0 \f20 \fs18
are}{\b0 \f20 \fs18 but}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 few}{\b0 \f20 \fs1
8 examples}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 use}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 liquid-crystal}{\b0 \f
20 \fs18 displays.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 main}{\b0 \f20 \fs18
advantages}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 liqui
d-crystal}{\b0 \f20 \fs18 display}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 its}{\
b0 \f20 \fs18 extremely}{\b0 \f20 \fs18 low }
\b0 \f20 \fs18 power}{\b0 \f20 \fs18 consumption}{\b0 \f20 \fs18 and}{\b0 \f20
\fs18 long}{\b0 \f20 \fs18 life.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 main}{
\b0 \f20 \fs18 disadvantage}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20
\fs18 LCD}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 its}{\b0 \f20 \fs18 slow}{\b0 \
f20 \fs18 switching}{\b0 \f20 \fs18 time}{\b0 \f20 \fs18 (on-off }
\b0 \f20 \fs18 and}{\b0 \f20 \fs18 off-on)}{\b0 \f20 \fs18 which}{\b0 \f20 \fs
18 might}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 about}{\b0 \f20 \fs18 40}{\b0 \f
20 \fs18 to}{\b0 \f20 \fs18 100}{\b0 \f20 \fs18 ms.}{\b0 \f20 \fs18 Slow}{\b
0 \f20 \fs18 switching}{\b0 \f20 \fs18 time}{\b0 \f20 \fs18 becomes}{\b0 \f20
\fs18 even}{\b0 \f20 \fs18 more}{\b0 \f20 \fs18 troublesome }
\b0 \f20 \fs18 at}{\b0 \f20 \fs18 low}{\b0 \f20 \fs18 temperatures.}{\f20 \fs
18 A}{\b0 \f20 \fs18 second}{\b0 \f20 \fs18 disadvantage}{\b0 \f20 \fs18 i
s}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 need}{\b0 \f20 \fs18 for}{\b0 \f20 \fs
18 ambient}{\b0 \f20 \fs18 light}{\b0 \f20 \fs18 because}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 LCD}{\b0 \f20 \fs18 reflects }
\b0 \f20 \fs18 (controls)}{\b0 \f20 \fs18 light}{\b0 \f20 \fs18 but}{\b0 \f20
\fs18 does}{\b0 \f20 \fs18 not}{\b0 \f20 \fs18 emit}{\b0 \f20 \fs18 light}
{\b0 \f20 \fs18 like}{\b0 \f20 \fs18 LED,}{\b0 \f20 \fs18 VF,}{\b0 \f20 \fs18
or}{\b0 \f20 \fs18 incandescent}{\b0 \f20 \fs18 displays. }
fi366 {\f20 \fs18 A}{\b0 \f20 \fs18 cutaway}{\b0 \f20 \fs18 view}{\b0 \f20 \fs
18 of}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 typical}{\b0\i \f20 \fs18 field-e
fect}{\b0\i \f20 \fs18 LCD}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 detailed}{\b0
\f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 7-15.}{\b0 \f20 \fs18
When}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 voltage}{\b0 \f20 \fs18 is}{\b0 \f20
\fs18 applied }
\b0 \f20 \fs18 across}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 metalized}{\b0 \f20
\fs18 segments}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 top}{\
b0 \f20 \fs18 glass}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
back}{\b0 \f20 \fs18 plane,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 segment}{\b0
\f20 \fs18 changes}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 black}{\b0 \f20 \fs18
on}{\b0 \f20 \fs19 a }
\b0 \f20 \fs18 silvery}{\b0 \f20 \fs18 background.}{\b0 \f20 \fs18 This}{\b0
\f20 \fs18 is}{\b0 \f20 \fs18 because}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 l
iquid}{\b0 \f20 \fs18 crystal,}{\b0 \f20 \fs18 or}{\b0\i \f20 \fs18 nematic}
{\b0\i \f20 \fs18 fluid,}{\b0 \f20 \fs18 sandwiched}{\b0 \f20 \fs18 between}{
\b0 \f20 \fs18 the}{\b0 \f20 \fs18 front }
\b0 \f20 \fs18 and}{\b0 \f20 \fs18 back}{\b0 \f20 \fs18 pieces}{\b0 \f20 \fs18
of}{\b0 \f20 \fs18 glass}{\b0 \f20 \fs18 transmits}{\b0 \f20 \fs18 light}{\
b0 \f20 \fs18 differently}{\b0 \f20 \fs18 when}{\b0 \f20 \fs18 activated.}{\b
0 \f20 \fs18 The}{\b0 \f20 \fs18 field-effect}{\b0 \f20 \fs18 LCD}{\b0 \f20 \
fs18 uses}{\b0 \f20 \fs18 polarized }
\b0 \f20 \fs18 filters}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18
top}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 bottom}{\b0 \f20 \fs18 of}{\b0 \f20
\fs18 the}{\b0 \f20 \fs18 display}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 in}{
\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 7-15.}{\b0 \f20 \fs18 Each}{\b0 \f20 \fs1
8 segment}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 back}{\b0
\f20 \fs18 plane}{\b0 \f20 \fs18 are }
\b0 \f20 \fs18 internally}{\b0 \f20 \fs18 wired}{\b0 \f20 \fs18 to}{\b0 \f20
\fs18 contacts}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 e
dge}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 LCD}{\b0 \f20 \
fs18 package.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 simplified}{\b0 \f20 \fs
18 diagram}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 7-15
}
\b0 \f20 \fs18 shows}{\b0 \f20 \fs18 only}{\b0 \f20 \fs18 three}{\b0 \f20 \fs1
8 of}{\b0 \f20 \fs18 many}{\b0 \f20 \fs18 edge}{\b0 \f20 \fs18 connectors. }
\par
}
20 \fs16 \cf0 Fig. 7-15{\b0 \fs16
Field-effect}{\b0 \fs16 LCD }
cf0 \fi358 {\b0 \fs18 LCDs}{\b0 \fs18 are}{\b0 \fs18 driven}{\b0 \fs18 by}{\b
0 \fs18 low-frequency}{\b0 \fs18 (30}{\b0 \fs18 to}{\b0 \fs18 200}{\b0 \fs18
Hz)}{\b0 \fs18 square-wave}{\b0 \fs18 signals}{\b0 \fs18 with}{\b0 \fs18 a
}{\b0 \fs19 50%}{\b0 \fs18 duty}{\b0 \fs18 cycle}{\b0 \fs19 (50% }
{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 time}{\b0 \fs18 it's}{\b0 \fs18
HIGH).}{\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 signals}{\b0 \fs18
entering}{\b0 \fs18 the}{\b0 \fs18 LCD}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b
0 \fs18 7-15.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18
signal }
{\b0 \fs18 entering}{\b0 \fs18 the}{\b0 \fs18 back}{\b0 \fs18 plane}{\b0 \
fs18 (b.p.)}{\b0 \fs18 is}{\b0 \fs18 HLH}{\b0 \fs18 (HIGH-LOW-HIGH).}{\b
0 \fs18 The}{\b0 \fs18 square-wave}{\b0 \fs18 signal}{\b0 \fs18 applied}
{\b0 \fs18 to }
{\b0 \fs18 segment}{\i \fs18 e}{\b0 \fs18 is}{\b0 \fs18 LHL}{\b0 \fs18 (
LOW-HIGH-LOW)}{\b0 \fs18 which}{\b0 \fs18 is}{\b0 \fs18 180"}{\b0\i \fs18
out}{\b0 \fs18 of}{\b0\i \fs18 phase}{\b0 \fs18 (inverted)}{\b0 \fs18 w
ith}{\b0 \fs18 the}{\b0 \fs18 back}{\b0 \fs18 plane }
{\b0 \fs18 signal.}{\i \f10 \fs17 An}{\b0 \fs18 out-of-phase}{\b0 \fs18 sign
al}{\b0 \fs18 on}{\b0 \fs18 a}{\b0 \fs18 segment}{\b0 \fs18 will}{\b0 \fs18
activate}{\b0 \fs18 the}{\b0 \fs18 display}{\b0 \fs18 as}{\b0 \fs18 is}{\b
0 \fs18 the}{\b0 \fs18 case}{\b0 \fs18 with}{\b0 \fs18 segment}{\b0\i \fs18
e}{\b0 \fs18 in }\par
}
.{\b \fs17 71 }\par
}
cf0 CODE CONVERSION \par
}
f0 153 \par
}
ig. 7-15. Next consider the signal applied to segment{\b\i \fs18 d} of
the LCD in Fig. 7-15. The signal goes
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-234 \f20 \fs19 \cf0 HLH,
which is a duplicate of the back plane signal, and they are said to be{\b\i \fs
18 in}{\b\i \fs18 phase.} In-phase signals
een the back plane and segment{\i \f10 \fs18 d} produce{\b\i \fs18 no}{\b\
i \fs18 voltage}{\b\i \fs18 difimnce,} and segment{\i \f10 \fs18 d} is not
activated
remains invisible. In summary, in-phase signals do not activate the display whil
e 180"out-of-phase
als activate an LCD segment.
56 {\b \fs18 A} typical LCD is illustrated in Fig. 7-16. This unit comes{\fs18
in.} a 40-pin package ready for mounting
a printed circuit board. Notice that segments that can be activated c
an be manufactured in any
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-241 \f20 \fs19 \cf0 shap
e, including numbers, symbols, and letters. Each segment, decimal point,
word, and symbol is
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-237 \f20 \fs19 \cf0 assi
gned a pin number. Only the back plane or common pin{\fs19 is} noted on the d
rawing. Manufacturer's
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-237 \f20 \fs19 \cf0 data
sheets must be consulted for actual pin numbers. This is a commercial
display that you might
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-240 \f20 \fs19 \cf0 expe
ct on a digital meter. In Fig. 7-16, note the construction of this field-effect
LCD with nematic fluid
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-235 \f20 \fs19 \cf0 sand
wiched between glass plates and polarizers on the top and bottom. Plas
tic headers secure the
\par}{\phpg\posx841\pvpg\posy1330\absw9178\absh2801 \sl-243 \f20 \fs19 \cf0 glas
s plates of the LCD to the pins. \par
}
\cf0 Plastic header \par
}
cf0 Glass \par
}
\cf0 A" \par
}
cf0 Common \par
}
\cf0 (back plane)
f0 {\fs16 Fig.}{\fs17 7-16}{\fs17
Commercial}{\fs17 35}{\fs17 digit}{\fs1
7 LCD }\par
}
\cf0 Care must be taken when using LCDs because they are made of glass and ar
e somewhat fragile.
\fs19 Also,} the driving signals should be generated by CMOS ICs for{\fs18 two}
reasons. CMOS ICs consume very
\par}{\phpg\posx837\pvpg\posy9524\absw9244\absh1921 \sl-235 \f20 \fs19 \cf0 litt
le power like the LCD. The second reason is that signals from{\fs19 CMOS} ICs d
o not have a dc voltage
\par}{\phpg\posx837\pvpg\posy9524\absw9244\absh1921 \sl-237 \f20 \fs19 \cf0 offs
et like that present when using TTL ICs.{\b \fs18 A} dc voltage applied across
the nematic fluid will{\b\i \fs18 destroy }
i \fs18 the}{\b\i \fs18 LCD} after a time.
58 {\b\i \f10 \fs17 An} older type liquid-crystal display that produces frosty-w
hite characters on a dark background is
\b\i \fs18 dynamic-scattering}{\i LCD.} The dynamic-scattering LCD uses
a different nematic fluid and no
\par}{\phpg\posx837\pvpg\posy9524\absw9244\absh1921 \sl-240 \f20 \fs19 \cf0 pola
rizers. These must be viewed in very good light and consume more power than the
more popular
\par}{\phpg\posx837\pvpg\posy9524\absw9244\absh1921 \sl-243 \f20 \fs19 \cf0 fiel
d-effect LCD. \par
}
OLVED PROBLEMS \par
}
cf0 7.21 \par
}
Digits appear
\par}{\phpg\posx1439\pvpg\posy12594\absw1840\absh720 \sl-237 \f20 \fs19 \cf0 liq
uid-crystal display.
}
(black, silver) on a \par
}
(black, silver) background on a field-effect \par
}
\cf0 When using a field-effect LCD, digits will appear black{\b0 \fs17 on}
a silver background. \par
}
\par
}
DE CONVERSION \par
}
f0 [CHAP.{\b0\i \f10 \fs16 7 }\par
}
f0 7.22 \par
}
ist two advantages of LCDs over LED displays.
\fs16 Solution: }
51 {\fs16 Advantages}{\fs16 of}{\fs16 using}{\fs16 an}{\fs17 LCD}{\fs16
are}{\fs16 low-power}{\fs16 consumption}{\fs16 and}{\fs16 long}{\fs16
life. }\par
}
f0 7.23 \par
}
ist{\fs19 two} disadvantages of LCD.
51 {\fs16 An}{\fs17 LCD}{\fs16 has}{\fs16 the}{\fs16 disadvantage}{\fs16
of}{\fs16 slow}{\fs16 switching}{\fs16 times,}{\fs16 especially}{\fs1
6 at}{\fs16 low}{\fs16 temperatures.}{\fs17 A}{\fs16 second }
16 disadvantage}{\fs16 is}{\fs16 that}{\fs16 the}{\fs17 LCD}{\fs16 cann
ot}{\fs16 be}{\fs16 viewed}{\fs16 in}{\fs16 darkness. }\par
}
f0 7.24 \par
}
efer to Fig.{\i \fs19 7-15.} When a voltage is applied across the nematic fluid
in this LCD, the segment \par
}
{\phpg\posx1437\pvpg\posy4463\absw813\absh508 \f20 \fs18 \cf0 \f20 \fs18 \cf0 wi
ll be
}
activated, deactivated). \par
}
\cf0 Voltage applied across the nematic fluid in an{\fs17 LCD} activat
es the segment. An activated segment on
\fs17 LCD} in Fig.{\fs17 7-15} will appear black on a silver backgro
und. \par
}
f0 7.25 \par
}
CDs should be driven by
}
low, high)-frequency square-wave signals. \par
}
CDs{\fs16 should}{\fs16 be}{\fs16 driven}{\fs16 by}{\fs16 low-frequency
} (30{\fs16 to} 200{\b \fs17 Hz)}{\fs16 square-wave}{\fs16 signals}{\fs16
with}{\fs16 a}{\fs17 50%}{\fs16 duty}{\fs16 cycle. }\par
}
cf0 7.26{\b0 \fs18
When}{\b0 \fs18 the}{\b0 \fs18 signals}{\b0 \fs18 appl
ied}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 back}{\b0 \fs18 plane}{\b0 \fs1
8 and}{\b0 \fs18 segment}{\b0 \fs18 of}{\b0 \fs18 an}{\b0 \fs18 LCD}{\b0 \f
s18 are}{\b0 \fs19 180"}{\b0 \fs18 out}{\b0 \fs18 of}{\b0 \fs18 phase,}{\b0
\fs18 the }\par
}
egment will be
}
activated, deactivated). \par
}
ut-of-phase signals activate{\fs17 LCD} segment. \par
}
f0 7.27 \par
}
efer to Fig.{\i \fs19 7-16.} What is sandwiched between the two glass plates
in this LCD?
\fs16 Solution: }
51 {\fs16 Nematic}{\fs16 fluid}{\fs16 (liquid}{\fs16 crystal)}{\fs16 is}{\
fs16 sandwiched}{\fs16 between}{\fs16 the}{\fs16 glass}{\fs16 plates}{\fs1
6 in}{\fs16 the}{\fs17 LCD}{\fs16 pictured}{\fs16 in}{\fs16 Fig.}{\fs17 7
-16. }\par
}
cf0 7.28 \par
}
LCDs can be damaged if driven by

}
(ac, dc) voltages. \par
}
LCDs{\fs16 can}{\fs16 be}{\fs16 damaged}{\fs17 if}{\fs16 driven}{\fs16
by}{\fs16 dc}{\fs16 voltages. }\par
}
\cf0 7-6 DRNING LCDs
\fi363 {\fs18 A}{\b0 \fs18 block}{\b0 \fs18 diagram}{\b0 \fs18 of}{\b0 \fs18
a}{\b0 \fs18 simple}{\b0 \fs18 LCD}{\b0 \fs18 decoder/driver}{\b0 \fs18
circuit}{\b0 \fs18 is}{\b0 \fs18 drawn}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b
0\i \fs19 7-17a.}{\b0 \fs18 The}{\b0 \fs18 input}{\b0 \fs18 is}{\b0 \fs18
in }
{\b0\i \fs19 8421}{\b0 \fs18 BCD}{\b0 \fs18 code.}{\b0 \fs18 The}{\b0 \fs18
decoder}{\b0 \fs18 converts}{\b0 \fs18 the}{\b0 \fs18 incoming}{\b0 \fs18 BC
D}{\b0 \fs18 to}{\b0 \fs18 seven-segment}{\b0 \fs18 code.}{\b0 \fs18 This}{\
b0 \fs18 decoder}{\b0 \fs18 would }
{\b0 \fs18 operate}{\b0 \fs18 much}{\b0 \fs18 like}{\b0 \fs18 the}{\b0\i \
fs19 7447}{\b0 \fs18 TTL}{\b0 \fs18 decoder}{\b0 \fs18 from}{\b0 \fs18 S
ec.}{\b0\i \fs19 7-4}{\b0 \fs18 except}{\b0 \fs18 it}{\b0 \fs18 is}{\b0 \f
s18 a}{\b0 \fs18 CMOS}{\b0 \fs18 unit.}{\b0 \fs18 Next,}{\b0 \fs18 the
}{\b0 \fs18 LCD }
{\b0 \fs18 driver}{\b0 \fs18 unit}{\b0 \fs18 would}{\b0 \fs18 take}{\b0 \fs1
8 the}{\b0 \fs19 100-Hz}{\b0 \fs18 square-wave}{\b0 \fs18 signal}{\b0 \fs1
8 from}{\b0 \fs18 the}{\b0 \fs18 free-running}{\b0 \fs18 clock}{\b0 \fs18
and}{\b0 \fs18 send}{\b0 \fs18 inverted }
{\b0 (180"}{\b0 \fs18 out-of-phase)}{\b0 \fs18 signals}{\b0 \fs18 to}{\b0 \fs
18 only}{\b0 \fs18 the}{\b0 \fs18 LCD}{\b0 \fs18 segments}{\b0 \fs18 that}{
\b0 \fs18 are}{\b0 \fs18 to}{\b0 \fs18 be}{\b0 \fs18 activated.}{\b0 \fs18
The}{\b0 \fs18 LCD}{\b0 \fs18 driver}{\b0 \fs18 would }
{\b0 \fs18 send}{\b0 \fs18 in-phase}{\b0 \fs18 signals}{\b0 \fs18 to}{\b0
\fs18 the}{\b0 \fs18 LCD}{\b0 \fs18 segments}{\b0 \fs18 that}{\b0 \fs18
are}{\b0 \fs18 inactive.}{\b0 \fs18 The}{\b0\i \fs19 free-running}{\b0\i
\fs19 clock}{\b0 \fs18 is}{\b0 \fs18 an}{\b0\i \fs19 astable }
{\b0\i \fs19 multiuibrator}{\b0 \fs18 that}{\b0 \fs18 continuously}{\b0 \fs18
generates}{\b0 \fs18 a}{\b0 \fs18 string}{\b0 \fs18 of}{\b0 \fs18 square-w
ave}{\b0 \fs18 pulses}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18 50%}{\b0 \fs18
duty}{\b0 \fs18 cycle. }\par
}
0 CHAP.{\b0 \f10 \fs16 71 }\par
}
cf0 CODE{\fs15 CONVERSION }\par
}
\par
}
{\phpg\posx3519\pvpg\posy2071\absw213\absh666 \f10 \fs56 \cf0 \f10 \fs56 \cf0 '
\par
}
cf0 BCD \par
}
cf0 Input \par
}
\fs15 \cf0 BCD-to\par}{\phpg\posx3515\pvpg\posy2079\absw1078\absh311 \sl-205 \b \f20 \fs15 \cf0 {
\b0 \f10 \fs20 2} 7-segment \par
}
cf0 decoder \par
}
\cf0 7-segment
fi189 code
fi683 {\b0 \f10 \fs19 \\}
LCD
fi683 {\b0 \f10 \fs21 ,/}
driver \par
}
{\phpg\posx6019\pvpg\posy2971\absw80\absh175 \f10 \fs14 \cf0 \f10 \fs14 \cf0 , \
par
}
}
a \par
}
0 -\par}{\phpg\posx4931\pvpg\posy3847\absw3349\absh4076 \sl-2960 \f10 \fs292 \cf0 {
\fs296 - }\par
}
\cf0 (a){\b\i0 \f20 \fs15 Block}{\b\i0 \f20 \fs15 diagram }\par
}
15 \cf0 a b c d e \par
}
\par}{\phpg\posx5463\pvpg\posy6365\absw513\absh1065 \sl-353 \f20 \fs20 \cf0 U
\par}{\phpg\posx5463\pvpg\posy6365\absw513\absh1065 \sl-358 \f20 \fs20 \cf0 U
0 \fs31 n }\par
}
{\phpg\posx4931\pvpg\posy7442\absw975\absh452 \f20 \fs39 \cf0 \f20 \fs39 \cf0 E+
-- \par
}
\cf0 100{\b \fs16 Hz }

{\b\i \fs15 (b)}{\b \fs15 Wiring}{\b \fs15 diagram }\par
}
cf0 7-segment
i186 code \par
}
{\phpg\posx7609\pvpg\posy2667\absw769\absh244 \f10 \fs17 \cf0 \f10 \fs17 \cf0 ..
.{\fs17 ............... }\par
}
.:...{\fs16 .}{\fs19 -}{\fs17 ..............}{\fs16 . }\par
}
}
\cf0 *I.? \par
}
{\b \f20 \fs15 Common }\par
}
\fs16 .}{\fs18 .... }\par
}
... \par
}
{\phpg\posx7659\pvpg\posy2116\absw799\absh301 \f10 \fs25 \cf0 \f10 \fs25 \cf0 :.
'..{\dn006 \fs16 ........... }\par
}
par
}
par
}
{\phpg\posx7667\pvpg\posy1866\absw942\absh434 \f10 \fs15 \cf0 \f10 \fs15 \cf0 {\
dn006 \fs8 !?::::::::::::.:;;!:: }
:}{\fs8
: }
6 .}{\fs15 :}{\fs8 :: }\par
}
par
}
.:{\fs17 .................. }\par
}
par
}
fs18 . }\par
}
\fs16 .} . \par
}
\cf0 2.{\b0\i0 \f10 \fs8 : }\par

}
fs18 . }\par
}
\fs17 .} ..
{\b \fs10 ..:i }\par
}
{\phpg\posx8163\pvpg\posy1973\absw165\absh235 \f10 \fs15 \cf0 \f10 \fs15 \cf0 ;;
:}{\fs8
: }\par
}
{\phpg\posx3635\pvpg\posy2927\absw158\absh105 \f10 \fs8 \cf0 \f10 \fs8 \cf0 ,- \
par
}
\cf0 Free-running
fi273 clock \par
}
cf0 BCD
\par}{\phpg\posx2519\pvpg\posy6205\absw464\absh602 \sl-184 \b \f20 \fs15 \cf0 In
put
i29 {\b0 \fs15 1}{\b0 \fs15 1 }\par
}
\par
}
\fs15 L}{\b\i \fs15
A }
2 {\b\i \fs15 B }
2 {\b\i \fs15 C }\par
}
cf0 CMOS \par
}
s15 \cf0 D{\i0 \fs15
BCD-to- }
\fi381 {\i0 \fs15 seven- }
\fi313 {\i0 \fs15 segment }
\fi327 {\i0 \fs15 decoder }\par
}
s13 \cf0 a
\cf0 {\f20 \fs15 b }
\cf0 {\f20 \fs15 c }
\cf0 {\f20 \fs15 d }\par

}
\par
}
\par
}
\cf0 Fig. 7-17{\fs15
Decoding/driving}{\b0 \fs17
a}{\fs15 seven-segment}
{\b0 \fs17 LCD }\par
}
0 \fs18 \cf0 A{\b0 more}{\b0 detailed}{\b0 diagram}{\b0 of}{\b0 the}{\b0 L
CD}{\b0 decoder/driver}{\b0
is}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 \fs19 7
-17b.}{\b0 In}{\b0 this}{\b0 example,}{\b0 the }
{\b0 BCD}{\b0 input}{\b0 to}{\b0 the}{\b0 CMOS}{\b0 BCD-to-seven-segment}{
\b0
decoder}{\b0 is}{\b0 \fs18 0111.}{\b0 The}{\b0 decoder}{\b0 transl
ates}{\b0 the}{\b0 BCD }
{\b0 input}{\b0 and}{\b0 activates}{\b0 outputs}{\i a,}{\b0 \fs18 6,}{\b0
and}{\i \fs18 c}{\b0 with}{\b0 \fs19 HIGH,}{\b0 which}{\b0 is}{\b0 the}{\
b0 proper}{\b0 seven-segment}{\b0 code}{\b0 to}{\b0 display }
{\b0 a}{\b0 decimal}{\b0 \fs18 7.}{\b0 \fs18 All}{\b0 other}{\b0 decoder}{\
b0 outputs}{\b0\i \f10 \fs18 (d,}{\b0 \fs18 e,}{\b0\i \f30 \fs21 f,}{\b0 and
}{\i \fs17 g}{\i \fs17 )}{\b0 remain}{\b0 LOW}{\b0 or}{\b0 deactivated.}
{\b0 Notice}{\b0 that}{\b0 the, }
{\b0 LCD}{\b0 driver}{\b0 section}{\b0 contains}{\b0 seven}{\b0 CMOS}{\b0
2-input}{\b0 XOR}{\b0 gates.}{\b0 The}{\b0 100-Hz}{\b0 square-wave}{\b0 s
ignal}{\b0 drives }
{\b0 the}{\b0 top}{\b0 input}{\b0 of}{\b0 each}{\b0 XOR}{\b0 gate.}{
\b0 \fs18 If}{\b0 the}{\b0 bottom}{\b0 input}{\b0 on}{\b0 an}{\b0
XOR}{\b0 gate}{\b0 is}{\b0 LOW,}{\b0 the}{\b0 signal}{\b0 passes }
{\b0 through}{\b0 the}{\b0 gate}{\b0 with}{\b0 no}{\b0 change}{\b0 (in}{\b
0 phase}{\b0 with}{\b0 clock}{\b0 signal).}{\b0 But}{\b0 if}{\b0 the}{\b0
bottom}{\b0 input}{\b0 of}{\b0 an}{\b0 \fs19 XOR}{\b0 gate }
{\b0 is}{\b0 driven}{\b0 \fs18 HIGH,}{\b0 the}{\b0 signal}{\b0 is}{\b0
inverted}{\b0 as}{\b0 it}{\b0 passes}{\b0 through}{\b0 the}{\b0 g
ate}{\b0 \fs18 (180"}{\b0 out}{\b0 \fs18 of}{\b0 phase}{\b0 with}{\b0
clock }
{\b0 signal).}{\b0 Refer}{\b0 back}{\b0 to}{\b0 Fig.}{\b0 4-10}{\b0 to}{
\b0 verify}{\b0 the}{\b0 operation}{\b0 \fs18 of}{\b0 an}{\b0 XOR}{\b0
gate.}{\b0 The}{\b0 out-of-phase}{\b0 signals}{\b0 in }
{\b0 Fig.}{\b0 \fs18 7-176}{\b0 are}{\b0 driving}{\b0 segments}{\i a,}
{\b0 \fs18 6,}{\b0 and}{\i \fs18
c,}{\b0 which}{\b0 are}{\b0 activa
ted}{\b0 and}{\b0 appear}{\b0 dark}{\b0 on}{\b0 a}{\b0 silver }
{\b0 background}{\b0 on}{\b0 the}{\b0 LCD. }\par
}
\par
}
DE CONVERSION \par
}
AP. 7 \par
}
\cf0 The clock signal is generated by an astable multivibrator in Fig. 7-17b. T
he 100-Hz signal is routed
\par}{\phpg\posx813\pvpg\posy1344\absw9154\absh1507 \sl-237 \f20 \fs18 \cf0 to b
oth the common (back plane) of the LCD and each of the XOR gates in the driver
section.
60 {\fs18 Two} commercial CMOS ICs are available that perform the task{
\fs18 of} the LCD decoder/driver.
\par}{\phpg\posx813\pvpg\posy1344\absw9154\absh1507 \sl-237 \f20 \fs18 \cf0 Thes
e are the 4543 and 74HC4543 ICs, described by the manufacturer as a{\i \f
s19 BCD-to-seven-segment }
\fs19 latch/decoder/driver}{\i \fs19 for}{\i \fs19 LCDs. }
60 {\b A} block diagram of an LCD decoder/driver circuit using the 74HC4543 IC
is drawn in Fig. 7-18a.
\par}{\phpg\posx813\pvpg\posy1344\absw9154\absh1507 \sl-235 \f20 \fs18 \cf0 Note
that the 74HC4543 chip contains the BCD-to-seven-segment
decoder and LCD dri
ver sections. \par
}
\cf0 (a){\i0 \f20 \fs15 Block}{\i0 \f20 \fs15 diagram}{\i0 \f20 \fs15 of}{\i0
\f20 \fs15 74HC4543driving}{\i0 \f20 \fs15 LCD }\par
}
D
\par}{\phpg\posx2503\pvpg\posy7001\absw414\absh574 \sl-186 \f20 \fs15 \cf0 Input
0 \par
}
cf0 +5{\i0 \fs22 v }\par
}
par
}
\par
}
\par
}
cf0 LCD
t \par
}
cf0 LV \par
}

{\b\i\dn006 \f10 \fs13 A }
5 2s,g }
5 4s }\par
}
\par
}
17 \cf0 D \par
}
\cf0 CMOS
\par}{\phpg\posx4023\pvpg\posy8339\absw667\absh1044 \sl-302 \f20 \fs15 \cf0 BCDto\par}{\phpg\posx4023\pvpg\posy8339\absw667\absh1044 \sl-216 \f20 \fs15 \cf0 \fi1
18 seven\par}{\phpg\posx4023\pvpg\posy8339\absw667\absh1044 \sl-190 \f20 \fs15 \cf0 \fi5
0 segment
3 decoder \par
}
cf0 b
b \fs15 c }
0 {\f10 \fs14 d }\par
}
cf0 f \par
}
cf0 BI
i92 {\i0 \f10 \fs21 1 }\par
}
\cf0 \par}{\phpg\posx3981\pvpg\posy10157\absw175\absh472 \sl-279 \f10 \fs21 \cf0 {\dn
006 \fs26 -}{\fs31 - }\par
}
D{\i
Ph }
1 {\f10 \fs21 1 }\par
}
lock \par
}
00{\b \fs15 Hz }\par
}
\par
}

{\fs38 m }\par
}
\cf0 d
5 Common }\par
}
\cf0 (b){\i0 \fs15 Wiring}{\i0 \fs15 diagram}{\i0 \fs16 of}{\i0 \fs15 74HC45
43drivingLCD }\par
}
10 \fs13 \cf0 (c){\i0 \f20 \fs15 Format}{\i0 \f20 \fs15 of}{\i0 \f20 \fs15 de
cimal}{\i0 \f20 \fs15 numbers }
cf0 {\i0 \f20 \fs16 Fig.}{\i0 \f20 \fs16 7-18}{\i0 \f20 \fs16
The}{\i0 \f20
\fs16 74HC4543}{\i0 \f20 \fs16 latch/decoder/driver}{\i0 \f20 \fs17
CMOS}
{\i0 \f20 \fs16 IC }\par
}
.{\fs17 71 }\par
}
DE CONVERSION \par
}
\par
}
t also has an added 4-bit latch section to "lock in" the{\fs19 BCD} input at a
given time. Think{\fs19 of} the latch
\par}{\phpg\posx843\pvpg\posy1362\absw9100\absh3279 \sl-235 \f20 \fs18 \cf0 as a
memory unit that holds the four input bits on the input of the decoder sectio
n for a time.
60 {\b A} wiring diagram for the{\fs19 LCD} decoder/driver circuit using the{
\fs19 74HC4543}{\fs19 IC} is detailed in Fig.
19 7-18b.} The{\fs19 BCD} input is{\fs19 1001} (decimal{\fs19 9)} in
this example. The{\fs19
1001} input is decoded into
n-segment code. The{\fs19 100-Hz} clock signal is routed to both the common (
back plane) of the{\fs19 LCD }
the{\i Ph} (phase) input of the{\fs19 74HC4543}{\fs19 IC.} Notice t
hat. the{\fs19 LCD} driver section within the
19 74HC4543}{\fs19 IC} inverts the signals to the segments that are to be activ
ated. In this example segments{\fs19 a, }
19 b,}{\i \fs19 c,}{\i \f10 \fs18 d,}{\fs19 f,} and{\b\i \fs17 g} are acti
vated, displaying the decimal{\fs19 9} on the{\fs19 LCD.} The only in-phase si
gnals passing
\par}{\phpg\posx843\pvpg\posy1362\absw9100\absh3279 \sl-239 \f20 \fs18 \cf0 to t
he{\fs19 LCD} are those of the inactive segments. Only segment{\i \fs19 e}
is inactive in this example.
62 The format{\fs19 of'}the numbers generated by the{\fs19 74HC4543} dec

oder is detailed in Fig.{\fs19 7-18c.} Note
\par}{\phpg\posx843\pvpg\posy1362\absw9100\absh3279 \sl-239 \f20 \fs18 \cf0 espe
cially the numbers{\fs19 6} and{\fs19 9.} These numbers are shaped diffe
rently from those generated by the
19 7447} decoder studied earlier in Sec.{\fs19 7-4.} Compare Fig.{\fs19
7-18c} with Fig.{\fs19 7-10} to verify the different
\par}{\phpg\posx843\pvpg\posy1362\absw9100\absh3279 \sl-234 \f20 \fs18 \cf0 shap
es for the numbers{\fs18 6} and{\fs19 9. }
}
f0 7.29 \par
}
f0 7.30 \par
}
Refer to Fig.{\fs19 7-17a.} What is the job of the decoder block?
355 {\fs17 The}{\fs17 decoder}{\fs17 in}{\fs17 Fig.}{\fs17 7-17a}{\fs17
translates}{\fs17 from}{\fs17 a}{\fs17 BCD}{\fs17 number}{\fs17 to}{\
fs17 seven-segment}{\fs17 code. }
Refer to Fig.{\fs19 7-17a.} What is the job of the{\fs19 LCD} driver block?
353 {\fs17 The}{\fs17 LCD}{\fs17 driver}{\fs17 sends}{\fs17 inverted}{\fs17
signals}{\fs17 to}{\fs17 each}{\fs17 segment}{\fs17 that}{\fs17 is}{\fs1
7 to}{\fs17 be}{\fs17 activated}{\fs17 and}{\fs17 in-phase}{\fs17 signal
s}{\fs17 to }
s17 each}{\fs17 inactive}{\fs17 segment}{\fs17 of}{\fs17 the}{\fs17 li
quid-crystal}{\fs17 display. }\par
}
Refer to Fig.{\fs19 7-17a.} The{\fs19 LCD} driver block consists of
354 {\fs17 The}{\fs17 LCD}{\fs17 driver}{\fs17 consists}{\fs17 of}{\fs17
XOR}{\fs17 gates}{\fs17 (see}{\fs17 Fig.}{\fs17 7-17b). }
Refer to Fig.{\fs19 7-17b.} If the input to the decoder were{\fs19
0001,,,, }
\par}{\phpg\posx1447\pvpg\posy7738\absw5653\absh1791 \sl-237 \f20 \fs18 \cf0 inv
erted outputs and which number does the{\fs19 LCD} display.
}
\cf0 (NAND,{\b0 \fs19 XOR)}{\b0 gates. }\par
}
f0 7.31 \par
}
f0 7.32 \par
}
hich{\fs19 XOR} gates produce \par
}
\cf0 With an input of 0001, only XOR gates{\b\i \fs16 a} and{\i \fs1
6
b} will produce inverted signals at their outputs,
vating segments a and{\i \fs17 b}{\fs17 on} the LCD (decimal 1 will s
how on display). \par
}
\cf0 A{\b0 \f20 \fs18 free-running}{\b0 \f20 \fs18 clock}{\b0 \f20 \fs18 is}
{\b0 \f20 \fs18 also}{\b0 \f20 \fs18 called}{\b0 \f20 \fs18 a(n) }
cf0 {\f20 \fs16 Solution: }\par
}
(astable, monostable) multivibrator. \par
}
cf0 7.33 \par
}
cf0 7.34 \par
}
17 \cf0 The free-running clock may also be called an astable multivibrator.
0 {\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs19 7-19.}{\fs18 What}{\fs18 is}{\f
s18 the}{\fs18 decimal}{\fs18 reading}{\fs18 on}{\fs18 the}{\fs19 LCD}{\fs
18 for}{\fs18 each}{\fs18 input}{\fs18 pulse}{\fs19 (a}{\fs18 through}{\b
\f10 \fs16 e). }
i362 Decimal outputs in Fig. 7-19 are as follows:
\par}{\phpg\posx1441\pvpg\posy11203\absw8328\absh2237 \sl-223 \f20 \fs17 \cf0 pu
lse a{\dn006 \f10 \fs11 =}{\b \fs17 2 }
lse{\i \fs17 b}{\dn006 \f10 \fs11 =} 4
lse{\i \f10 \fs14 c}{\f10 \fs13 =}{\fs16 8 }
lse{\b\i d}{\dn006 \f10 \fs11 =}{\fs17 5 }
lse{\b\i \fs16 e}{\dn006 \f10 \fs11 =}{\fs16 6 }\par
}
\par
}
DE CONVERSION \par
}
AP. 7 \par
}
15 \cf0 LE \par
}
\cf0 Inputs
23 mo}{\dn006 \fs15
0 }
{\i \fs15 7}{\i \fs15
0}{\fs15
0}{\f10 \fs19 o }\par
}
cf0 1 \par
}
\par
}
cf0 Is \par
}
\par
}
15 \cf0 A
cf0 {\fs15 B }\par
}
{\phpg\posx2247\pvpg\posy3225\absw923\absh274 \f20 \fs24 \cf0 \f20 \fs24 \cf0 ll
olllo \par
}
{\f10 \fs31 omo}{\dn006
0 }
\fs15 e}{\i \fs15
d}{\i \fs15
c}{\i \fs15
b}{\i \fs15
a }\par
}
cf0 8s \par
}
17 \cf0 D \par
}
\cf0 BCD-to\par}{\phpg\posx4583\pvpg\posy2560\absw885\absh1349 \sl-200 \f20 \fs15 \cf0 \fi1
88 seven\par}{\phpg\posx4583\pvpg\posy2560\absw885\absh1349 \sl-201 \f20 \fs15 \cf0 \fi1
20 segment
15 latch1
07 decoder1
01 driver
(74HC4543) \par
}

14 \cf0 VCC{\fs15 a }
cf0 \fi344 {\fs15 b }
cf0 \fi338 {\b0 \fs9 C }\par
}
4 \cf0 a \par
}
f0 e \par
}
cf0 f \par
}
\par
}
15 \cf0 BI
\fi67 {\b0\i0 \f10 \fs20 1 }\par
}
cf0 \par}{\phpg\posx4591\pvpg\posy4436\absw171\absh458 \sl-244 \f10 \fs20 \cf0 {\fs2
7 -}{\fs27 - }\par
}
D{\b\i \fs15
Ph }
5 {\f10 \fs20 1 }\par
}
f10 \fs15 \cf0 d
{\b0\i0 \f20 Common }
\fi311 {\i0 \fs14 A }\par
}
\par
}
{\phpg\posx5375\pvpg\posy4318\absw356\absh972 \f10 \fs34 \cf0 \f10 \fs34 \cf0 1t
\par
}
\cf0 Fig. 7-19{\b0 \fs16
Decoder}{\b0 \fs16 pulse-train}{\b0 \fs16 problem
}\par
}
Refer to Fig. 7-19. For input pulse{\i \fs18 e} only, which drive line or line
s to the{\fs19 LCD} have{\i \fs18 in-phase }
\par}{\phpg\posx1455\pvpg\posy6422\absw8440\absh1171 \sl-240 \f20 \fs18 \cf0 sig
nals appearing on them?
360 {\fs16 Decimal}{\b \fs16 6}{\fs16 appears}{\fs16 on}{\fs16 the}{\fs16
LCD}{\fs16 during}{\fs16 pulse}{\b\i \fs16 e}{\fs16 in}{\fs16 Fig.}{\fs1

6 7-19.}{\fs16 Only}{\fs16 segment}{\i \fs15 b}{\fs16 is}{\fs16 inactive
,}{\fs16 and}{\fs16 therefore }
s17 only}{\fs16 drive}{\fs16 line}{\i \fs16 b}{\fs16 has}{\fs16 an}{\f
s16 in-phase}{\fs16 signal.}{\b \fs16 Also}{\fs16 see}{\b \fs15 Fig.}{\fs
16 7-18c}{\fs16 for}{\fs16 the}{\fs16 formation.of}{\fs16 decimal}{\b \
fs16 6. }\par
}
0 Hz
Clock \par
}
f0 7.35 \par
}
\cf0 7.36{\b0 \fs18
9.}{\b0 \fs18 For}{\b0 \fs18 input}{\b0 \fs18 pulse}{\b0\i h}{\b0 \fs18
only,}{\b0 \fs18 which}{\b0 \fs18 drive}{\b0 \fs18 lines}{\b0 \fs18 to}{\
b0 \fs18 the}{\b0 \fs18 LCD}{\b0 \fs18 have}{\b0\i \fs18 out-of-phase }
fi601 {\b0 \fs18 signals}{\b0 \fs18 appearing}{\b0 \fs18 on}{\b0 \fs18 them?
}
fi962 {\b0 \fs16 Decimal}{\f30 \fs17 4}{\b0 \fs16 appears}{\b0 \fs16 on}{\b0
\fs16 the}{\b0 \fs16 LCD}{\b0 \fs16 during}{\b0 \fs16 pulse}{\b0\i \fs1
6 b}{\b0 \fs16 in}{\b0 \fs16 Fig.}{\b0 \fs16 7-19.}{\b0 \fs16 Segments}
{\b0\i \fs17 6,}{\b0 \f10 \fs14 c,}{\b0 \fs16 f,}{\b0 \fs16 and}{\b0 \fs15
g}{\b0 \fs16 are}{\b0 \fs16 activated, }
fi601 {\b0 \fs16 and}{\b0 \fs16 therefore}{\b0 \fs16 drive}{\b0 \fs16 line
s}{\b0\i \fs16 b,}{\fs16 c,}{\b0 \fs17 f,}{\b0 \fs16 and}{\b0 \fs15 g}{\b
0 \fs16 must}{\b0 \fs16 have}{\b0 \fs16 out-of-phase}{\b0 \fs16 signals.
}\par
}
\cf0 7-7{\fs18
VACUUM}{\fs18 FLUORESCENT}{\fs18 DISPLAYS }
\fi368 {\b0 \fs18 The}{\b0\i \fs18 uacuum}{\b0\i \fs18 fluorescent}{\b0\i \fs
19 (VF)}{\b0\i \fs18 display}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 relati
ve}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 earlier}{\b0 \fs18 triode}{\b0 \
fs18 vacuum}{\b0 \fs18 tube.}{\fs18 A}{\b0 \fs18 schematic }
{\b0 \fs18 symbol}{\b0 \fs18 for}{\b0 \fs18 a}{\b0 \fs18 triode}{\b0 \fs18 v
acuum}{\b0 \fs18 tube}{\b0 \fs18 is}{\b0 \fs18 illustrated}{\b0 \fs18 in}{
\b0 \fs18 Fig.}{\b0 7-20.}{\b0 \fs18 The}{\b0 \fs18 parts}{\b0 \fs18 of}{\b
0 \fs18 the}{\b0 \fs18 triode}{\b0 \fs18 tube}{\b0 \fs18 are}{\b0 \fs18 s
hown}{\b0 \fs18 as }
{\b0 \fs18 the}{\b0 \fs18 plate}{\b0\i \fs19 (PI,}{\b0 \fs18 control}{\b0 \fs
18 grid}{\b0 \fs18 (G),}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 cathode}{\
b0\i \fs18 (}{\b0\i \fs18 K}{\b0\i \fs18 )}{\b0\i \fs18 .}{\b0 \fs18 The}{\b
0 \fs18 plate}{\b0 is}{\b0 \fs18 sometimes}{\b0 \fs18 referred}{\b0 \fs18 t
o}{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 anode, }
{\b0 \fs18 while}{\b0 \fs18 the}{\b0 \fs18 cathode}{\b0 \fs18 may}{\b0 \fs18
be}{\b0 \fs18 called}{\b0 \fs18 the}{\b0 \fs18 filament}{\b0 \fs19 or}{\b0

\fs18 heater.}{\b0 \fs18 The}{\b0 \fs18 cathode/filament}{\b0 \fs18 is}{\b0
\fs18 a}{\b0 \fs18 fine}{\b0 \fs18 wire}{\b0 \fs18 that}{\b0 \fs18 when }
{\b0 \fs18 coated}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18 material}{\b0 \fs1
8 such}{\b0 \fs18 as}{\b0 \fs18 barium}{\b0 \fs18 oxide}{\b0 \fs18 will}
{\b0 \fs18 emit}{\b0 \fs18 electrons}{\b0 \fs18 when}{\b0 \fs18 heated.}
{\b0 \fs18 The}{\b0 \fs18 control}{\b0 \fs18 grid}{\b0 \fs18 is}{\b0 a }
{\b0 \fs18 screen}{\b0 \fs18 placed}{\b0 \fs18 between}{\b0 \fs18 the}{\b0 \
fs18 cathode}{\b0 \fs18 and}{\b0 \fs18 plate. }\par
}
\cf0 Fig.{\fs16 7-20}{\b0 \fs16
Schematic}{\b0 \fs16 symbol}{\b0 \fs16 of
}{\b0 \fs16 a}{\b0 \fs16 triode}{\b0 \fs16 vacuum}{\b0 \fs16 tube }\par
}
0 CHAP.{\b0 \fs17 71 }\par
}
cf0 CODE CONVERSION \par
}
\par
}
\cf0 When the cathode/filament is heated, it "boils off" electrons into
the vacuum surrounding the
\par}{\phpg\posx837\pvpg\posy1351\absw9184\absh2990 \sl-237 \f20 \fs18 \cf0 cath
ode. This is sometimes called thermionic emission. If the grid and plate a
re driven positive, the
tively charged electrons will be attracted and flow through the screenlike grid
onto the plate. The
\par}{\phpg\posx837\pvpg\posy1351\absw9184\absh2990 \sl-239 \f20 \fs18 \cf0 trio
de is conducting current from cathode to anode.
64 To stop the triode from conducting, two methods can be employed. First, a neg
ative charge can be
ed on the control grid. This will repel the electrons and stop them from pass
ing through the grid
he plate. Second, the voltage on the plate can be dropped from its normal posi
tive to{\fs18 0} volts. With
\par}{\phpg\posx837\pvpg\posy1351\absw9184\absh2990 \sl-236 \f20 \fs18 \cf0 no
voltage on the plate, it will not attract electrons and the triode tu
be will not conduct. The VF
lay has parts closely resembling those in the triode vacuum tube.
63 Consider the schematic diagram of the vacuum fluorescent display sho
wn in Fig. 7-2lu. This
\par}{\phpg\posx837\pvpg\posy1351\absw9184\absh2990 \sl-229 \f20 \fs18 \cf0 sche
matic represents a single seven-segment digit having seven plates each
coated with a zinc oxide
\par}{\phpg\posx837\pvpg\posy1351\absw9184\absh2990 \sl-246 \f20 \fs18 \cf0 fluo
rescent material. The VF display in Fig. 7-21a also has{\fs18 a} sin
gle grid that controls the entire

lay.{\b \f10 \fs17 A} single cathode/filament{\i \fs18 (}{\i \fs18 K}{\i \fs
18 )} is also shown, while the entire unit is enclosed in glass which
ains a vacuum. \par
}
{\phpg\posx7675\pvpg\posy6295\absw795\absh350 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Fl
uorescent
\par}{\phpg\posx7675\pvpg\posy6295\absw795\absh350 \sl-197 \f20 \fs15 \cf0 mater
ial \par
}
15 \cf0 K \par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 Schematic}{\b0\i0 \f20 \fs15 diagram}{\b0\i0 \
f20 \fs14 of}{\b0\i0 \f20 \fs15 a}{\b0\i0 \f20 \fs15 single}{\b0\i0 \f20 \
fs15 digit }\par
}
12v+12v \par
}
{\phpg\posx5063\pvpg\posy7424\absw316\absh251 \f20 \fs22 \cf0 \f20 \fs22 \cf0 ov
\par
}
\par
}
\par
}
\par
}
\par
}
\fs14 \cf0 (h){\i0 \fs15 Lighting}{\i0 \fs15 two}{\i0 \fs15 segments}{\i0 \fs
15 on}{\i0 \fs15 VF}{\i0 \fs15 display }
f0 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 7-21}{\i0 \fs16
Seven-segment}{\i0 \fs16
vacuum}{\i0 \fs16 fluorescent}{\i0 \fs16 display }\par
}
8 \cf0 Typical operation of a single digit in a VF display is illustrated
in Fig. 7-216. The cathode/fila\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-255 \f20 \fs18 \cf0 men
t is heated using a dc voltage. The control grid has{\f10 \fs28 +}{\fs18
12}{\b \f30 \fs20 C'} applied, which "turns on" the entire
\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-235 \f20 \fs18 \cf0 dis
play. In this example, only segments b and{\b\i c} are to be activa
ted,{\fs18 so} only plates{\i \fs18 Pb} and{\b\i \fs18 Pc} are
\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-263 \f20 \fs18 \cf0 ene
rgized with{\f10 \fs29 +}{\fs18 12}{\fs18 V.} Electrons flow from the catho
de/filament{\i
to}{\i only}{\i \fs18 p1ufe.s}{\i \fs18 Ph} and{\b\i \fs18
Pc}{\fs18 of} the VF
play.{\b \f10 \fs17 As} the electrons strike the plates of the{\i \fs17
b} and{\f10 \fs15 c} segments, they will glow the characteristic

\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-237 \f20 \fs18 \cf0 blu
e-green color. In the example shown in Fig. 7-21b with only segment{\
fs18 6} and{\b\i c} energized, the
ber 1 appears on the seven-segment VF display. Also note in the exampIe in Fi
g. 7-216 that the
\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-229 \f20 \fs18 \cf0 pla
tes{\fs18 of} the deactivated segments{\i \fs18 (P,,}{\b\i Pd,}{\i \fs18 P
e,}{\i P}{\i f}{\i ,} and{\b\i \fs18 Pg)} have{\fs17 0} V applied to them
. In summary, a
\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-255 \f20 \fs18 \cf0 pla
te voltage{\fs18 of}{\f10 \fs28 +}{\fs18 12}{\b V} lights{\fs18 a} segment
, whereas{\fs18 0} V at a plate means the segment will not glow.
353 The physical layout of cathode/filament, grids, and plates in a VF disp
lay is shown in Fig. 7-22.
\par}{\phpg\posx841\pvpg\posy10847\absw9392\absh2552 \sl-234 \f20 \fs18 \cf0 Not
ice in Fig. 7-22a that the plates are shaped to form the individual segments
{\fs18 of} the seven-segment
play. The cathode or heaters are thin wires stretched across the top. The grid i
s a screenlike panel \par
}
\par
}
DE CONVERSION \par
}
AP.{\fs17 7 }\par
}
cf0 K \par
}
cf0 K \par
}
0 \fs15 \cf0 (b){\i0 \fs16 Four-digit}{\i0 \fs16 commercial}{\i0 \fs16 VF}{\i0
\fs16 display }
f0 \fi2951 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 7-22}{\i0 \fs16
Vacuum}{\i0 \fs16
fluorescent}{\i0 \fs16 display }
f0 {\i0 \fs18 that}{\i0 \fs18 is}{\i0 \fs18 positioned}{\i0 \fs18 directly}
{\i0 \fs18 over}{\i0 \fs18 the}{\i0 \fs18 plates.}{\i0 \fs18 The}{\i0 \fs1
8 cathodes}{\i0 \fs18 and}{\i0 \fs18 grid}{\i0 \fs18 are}{\i0 \fs18 physi
cally}{\i0 \fs18 above}{\i0 \fs18 the}{\i0 \fs18 plates}{\i0 \fs18 but }
\i0 \fs18 are}{\i0 \fs18 transparent}{\i0 \fs19 so}{\i0 \fs18 the}{\i0 \fs18
plates}{\i0 \fs18 show}{\i0 \fs18 up}{\i0 \fs18 when}{\i0 \fs18 they}{\i0
\fs18 light. }
fi358 {\b\i0 \fs19 A}{\i0 \fs18 commercial}{\i0 \fs18 vacuum}{\i0 \fs18 fluo
rescent}{\i0 \fs18 display}{\i0 \fs18 is}{\i0 \fs18 shown}{\i0 \fs18 in}{\i
0 \fs18 Fig.}{\i0 \fs18 7-22b.}{\i0 \fs18 It}{\i0 \fs18 contains}{\i0 \fs18
4}{\i0 \fs18 seven-segment}{\i0 \fs18 VF }

\i0 \fs18 displays}{\i0 \fs18 as}{\i0 \fs18 well}{\i0 \fs18 as}{\i0 \fs18
a}{\i0 \fs18 few}{\i0 \fs18 other}{\i0 \fs18 symbols}{\i0 \fs18 that}{
\i0 \fs18 make}{\i0 \fs18 it}{\i0 \fs18 suitable}{\i0 \fs18 for}{\i0 \fs
18 a}{\i0 \fs18 digital}{\i0 \fs18 clock}{\i0 \fs18 readout.}{\i0 \fs18
The }
\i0 \fs18 cathode/filaments}{\i0 \fs18
are}{\i0 \fs18 stretched}{\i0 \fs18
lengthwise}{\i0 \fs18 across}{\i0 \fs18 the}{\i0 \fs18 display}{\i0 \fs1
8 and}{\i0 \fs18 appear}{\i0 \fs18 as}{\i0 \fs18 very}{\i0 \fs18 thin}
{\i0 \fs18 wires}{\i0 \fs18 in}{\i0 \fs18 a }
\i0 \fs18 commercial}{\i0 \fs19 VF}{\i0 \fs18 unit.}{\i0 \fs18 The}{\i0 \f
s18 VF}{\i0 \fs18 unit}{\i0 \fs18 shown}{\i0 \fs18 in}{\i0 \fs18 Fig.}
{\i0 \fs18 7-22b}{\i0 \fs18 has}{\i0 \fs18 five}{\i0 \fs18 control}{\i0
\fs18 grids}{\i0 \fs18 shown}{\i0 \fs18 as}{\i0 \fs18 rectangles }
\i0 \fs18 surrounding}{\i0 \fs18 seven-segment}{\i0 \fs18 and}{\i0 \fs18 co
lon}{\i0 \fs18 displays.}{\i0 \fs18 The}{\i0 \fs18 five}{\i0 \fs18 control
}{\i0 \fs18 grids}{\i0 \fs18 can}{\i0 \fs18 be}{\i0 \fs18 activated}{\i0
\fs18 separately}{\i0 \fs18 to }
\i0 \fs18 "turn}{\i0 \fs18 on"}{\i0 \fs18 an}{\i0 \fs18 individual}{\i0 \f
s18 display.}{\i0 \fs18 The}{\i0 \fs18 control}{\i0 \fs18 grids}{\i0 \fs
18 are}{\i0 \fs18 commonly}{\i0 \fs18 used}{\i0 \fs18 for}{\fs19 rnult
iplexing}{\i0 \fs18 the}{\i0 \fs18 displays }
\i0 \fs18 (turning}{\i0 \fs18 on}{\i0 \fs18 seven-segment}{\i0 \fs18 display
s}{\i0 \fs18 one}{\i0 \fs18 at}{\i0 \fs18 a}{\i0 \fs18 time}{\i0 \fs18 i
n}{\i0 \fs18 rapid}{\i0 \fs18 succession).}{\i0 \fs18 The}{\i0 \fs18 fluor
escent-coated}{\i0 \fs18 plates }
\i0 \fs18 are}{\i0 \fs18 shaped}{\i0 \fs18 like}{\i0 \fs18 the}{\i0 \fs18 nu
mber}{\i0 \fs18 segments,}{\i0 \fs18 triangles,}{\i0 \fs18 or}{\i0 \fs18 co
lons. }
fi364 {\i0 \fs18 Vacuum}{\i0 \fs18 fluorescent}{\i0 \fs18 displays}{\i0 \fs18
are}{\i0 \fs18 commonly}{\i0 \fs18 used}{\i0 \fs18 in}{\i0 \fs18 readouts}
{\i0 \fs18 found}{\i0 \fs18 in}{\i0 \fs18 a}{\i0 \fs18 wide}{\i0 \fs18 var
iety}{\i0 \fs18 of}{\i0 \fs18 electronic }
\i0 \fs18 equipment,}{\i0 \fs18 especially}{\i0 \fs18 those}{\i0 \fs18 found}
{\i0 \fs18 in}{\i0 \fs18 automobiles.}{\b\i0 \fs18 A}{\i0 \fs18 VF}{\i0 \fs
18 display}{\i0 \fs18 has}{\i0 \fs18 extremely}{\i0 \fs18 long}{\i0 \fs18
life,}{\i0 \fs18 fast}{\i0 \fs18 response }
\i0 \fs18 times,}{\i0 \fs18 operates}{\i0 \fs18 at}{\i0 \fs18 relatively}{\i0
\fs18 low}{\i0 \fs18 voltages}{\i0 \fs18 (commonly}{\i0 \fs18 12}{\i0 \fs1
8 V),}{\i0 \fs18 consumes}{\i0 \fs18 little}{\i0 \fs18 power,}{\i0 \fs18 ha
s}{\i0 \fs18 good}{\i0 \fs18 reliability, }
\i0 \fs18 and}{\i0 \fs18 is}{\i0 \fs18 inexpensive.}{\i0 \fs18 Although}{\i0
\fs18 a}{\i0 \fs18 VF}{\i0 \fs18 display}{\i0 \fs18 emits}{\i0 \fs18 a}{\i0
\fs18 blue-green}{\i0 \fs18 color,}{\i0 \fs18 filters}{\i0 \fs18 can}{\i0 \
fs18 be}{\i0 \fs18 used}{\i0 \fs18 to}{\i0 \fs18 display}{\i0 \fs18 other }
\i0 \fs18 colors.}{\i0 \fs18 VF}{\i0 \fs18 displays}{\i0 \fs18 are}{\i0 \fs18
compatible}{\i0 \fs18 with}{\i0 \fs18 the}{\i0 \fs19 CMOS}{\i0 \fs18 fam
ily}{\i0 \fs18 of}{\i0 \fs18 ICs. }

f0 {\i0 \f10 \fs16 SOLVED}{\i0 \f10 \fs16 PROBLEMS }\par
}
cf0 7.37 \par
}
\cf0 A{\b0 \fs18 vacuum}{\b0 \fs18 fluorescent}{\b0 \fs18 display}{\b0 \fs1
8 glows}{\b0 \fs18 with}{\b0 \fs18 a }
cf0 {\fs16 Solution: }\par
}
color when activated. \par
}
6 \cf0 Without{\fs17 a} filter, the{\fs17 VF} display glows with a bluegreen color.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs19 7-216.}{\fs19 If}{\f10 \fs28
+}{\fs18 12}{\fs18 V}{\fs18 was}{\fs18 applied}{\fs18 to}{\fs18 the}{\
fs18 grid}{\fs18 and}{\fs18 all}{\fs18 the}{\fs18 plates}{\fs18 of}{
\fs18 this}{\fs18 VF}{\fs18 display, }
s18 which}{\fs18 segments}{\fs18 would}{\fs18 glow}{\fs18 and}{\fs18 whic
h}{\fs18 number}{\fs18 would}{\fs18 appear? }\par
}
cf0 7.38 \par
}
.{\fs17 71 }\par
}
DE CONVERSION \par
}
\par
}
cf0 Solution:
i351 {\b0 The}{\b0 \f10 \fs25 + }\par
}
2{\fs16 V}{\fs16 at}{\fs16 each}{\fs16 plate}{\fs16 will}{\fs16 activat
e}{\fs16 (light)}{\fs16 all}{\fs16 the}{\fs16 segments}{\fs16 (number}{\
fs17 8}{\fs16 appears),}{\fs16 while}{\fs16 the}{\f10 \fs27 + }\par
}
{\fs17 V }\par
}
n{\fs16 the}{\fs16 grid}{\fs16 turns}{\fs16 on}{\fs16 the}{\fs16 ent
ire}{\fs16 seven-segment}{\fs16 VF}{\fs16 display. }\par
}
f0 7.39 \par
}
Refer to Fig. 7-23. What are the parts labeled{\i \fs19 X}{\i \fs19 ,}{\i \fs
19 Y,} and{\i \f10 \fs17 2} on the VF display?
s16 Part}{\i \fs17 X}{\dn006 \f10 \fs10
=}{\fs16 cathode,}{\fs16 filament
,}{\fs16 or}{\fs16 heater }
s16 Part}{\i \f30 \fs19 Y}{\dn006 \f10 \fs10 =}{\fs16 control}{\fs16 grid }
s16 Part}{\i \fs17 Z}{\f10 \fs11
=}{\fs16 plate}{\fs16 or}{\fs16 anode
}
Refer to Fig. 7-23. Which segments of this VF display will glow and which numbe
r will appear? \par
}
f0 7.40 \par
}
\cf0 Fig.{\fs16 7-23}{\b0 \fs16
VF}{\b0 \fs16 display}{\b0 \fs16 problem }
\par
}
\cf0 Solution:
fi359 {\b0 Segments}{\b0\i \f10 \fs13 a,}{\b0\i \fs16 b,}{\b0\i \f10 \fs16
d,}{\b0\i e,}{\b0 and}{\b0\i \fs15 g}{\b0 are}{\b0 activated}{\b0 \fs1
7 (+12}{\b0 V}{\b0 at}{\b0 these}{\b0 plates)}{\b0 and}{\b0 will}{
\b0 glow.}{\b0 The}{\b0 number}{\b0 \fs17 2}{\b0 will }
\b0 show}{\b0 \fs16 on}{\b0 the}{\b0 seven-segment}{\b0 \fs17 VF}{\b0 d
isplay. }\par
}
cf0 7.41 \par
}
List a few{\fs19 of} the advantages of the VF display.
353 {\fs16 Advantages}{\fs16
of}{\fs17
VF}{\fs16 displays}{\fs16 inclu
de}{\fs16
long}{\fs16 life,}{\fs16 fast}{\fs16 response}{\fs16
time,
}{\fs16 low}{\fs16
power}{\fs16
consumption,}{\fs16
good }
s16 reliability,}{\fs16 compatibility}{\fs16 with}{\fs16 CMOS}{\fs16 ICs
,}{\fs16 and}{\fs16 ability}{\fs16 to}{\fs16 operate}{\fs16 at}{\fs16
relatively}{\fs16 low}{\fs16 voltages. }\par
}
\cf0 7-8
DRIVING{\f30 \fs20 VF}{\fs18 DISPLAYS}{\fs18 WITH} CMOS
\fi362 {\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 decoder/driver}{\b0 \fs
18
and}{\b0 \fs18 VF}{\b0 \fs18 display}{\b0 \fs18 circuit}{\b0 \fs18
drawn}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 7-24.}{\b0 \fs18 In}{\b0
\fs18 this}{\b0 \fs18 example}{\b0 \fs18 the }
{\b0 \fs18 O}{\b0 \fs18 l}{\b0 \fs18 l}{\b0 \fs18 l}{\b0 \fs18 B}{\b0 \fs18
c}{\b0 \fs18 D}{\b0 \fs18 is}{\b0 \fs18 being}{\b0 \fs18 decoded}{\b0 \fs1
8 by}{\b0 \fs18 the}{\b0 \fs19 4511}{\b0 \fs18 latch/decoder/driver}{\b0 \fs
18
IC,}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 VF}{\b0 \fs18 display}{\
b0 \fs18 reads}{\b0 \fs18 decimal}{\b0 \fs19 7. }
{\b0 \fs18 Notice}{\b0 \fs18 that}{\b0 \fs18 only}{\b0 \fs18 outputs}{\b0\i \
f10 \fs15 a,}{\b0\i b,}{\b0 \fs18 and}{\b0 \fs17 c}{\b0 \fs18 are}{\b0 \
fs18 activated}{\b0 \fs19 (HIGH)}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 45
11}{\b0 \fs18 IC.}{\b0 \fs18 These}{\b0 \fs18 three}{\b0 \fs18 HIGHS}{\b0 \f
s18 drive }
{\b0 \fs18 the}{\b0 \fs18 plates}{\b0 \fs18 of}{\b0 \fs18 segments}{\b0\i \f1
0 \fs16 a,}{\b0\i \fs19 b,}{\b0 \fs18 and}{\b0\i \fs18 c}{\b0 of}{\b0 \fs1
8 the}{\b0 VF}{\b0 \fs18 display}{\b0 \fs18 to}{\b0 \f10 \fs29 + }
{\b0 is}{\b0 \fs18 connected}{\b0 \fs18 directly}{\b0 \fs18 to}{\b0 \fs18
positive}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 12-V}{\b0 \fs18 power}{
\b0 \fs18 supply}{\b0 \fs18 which}{\b0 \fs18 activates}{\b0 \fs18 the}{\b
0 \fs18 entire}{\b0 \fs18 seven-segment }
{\b0 \fs18 display.}{\b0 \fs18 The}{\b0 \fs18 cathode}{\b0\i \fs18 (}{\b0\i \
fs18 K}{\b0\i \fs18 )}{\b0 \fs18 is}{\b0 \fs18 connected}{\b0 \fs18 in}{\b0
\fs18 series}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18 limiting}{\b0 \fs18 r
esistor}{\b0\i \fs19 (}{\b0\i \fs19 R}{\b0\i \fs19 I}{\b0\i \fs19 )}{\b0 \f
s18 to}{\b0 \fs18 heat}{\b0 \fs18 the}{\b0 \fs18 filament.}{\b0 \fs18 The }
{\b0 \fs18 resistor}{\b0 \fs18 limits}{\b0 \fs18 the}{\b0 \fs18 current}{\b0
\fs18 through}{\b0 \fs18 the}{\b0 \fs18 filament}{\b0 \fs18 (cathode)}{\b0
\fs18 to}{\b0 \fs18 a}{\b0 \fs18 safe}{\b0 \fs18 level.}{\b0 \fs18 In}{\b0
\fs18 this}{\b0 \fs18 example,}{\b0 \fs18 the}{\b0 \fs18 inactive }
{\b0 \fs18 segments}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 VF}{\b0 \fs18 di
splay}{\b0\i \f10 \fs17 (d,}{\b0 e,}{\b0\i \f30 \fs21 f,}{\b0 \fs18 and}{\b0\
i \fs17 g}{\b0\i \fs17 )}{\b0 \fs18 have}{\b0 \fs18 their}{\b0 \fs18 plate
s}{\b0 \fs18 held}{\b0 \fs18 LOW}{\b0 \fs19 (0}{\b0 \fs18 V),}{\b0 \fs18 a
nd}{\b0 \fs18 they}{\b0 \fs18 do}{\b0 \fs18 not}{\b0 \fs18 light. }\par
}
12 V. The grid of the VF display in Fig.{\fs19 7-24 }\par
}
\par
}
}
AP.{\fs17 7 }\par
}
\cf0 Fig.{\fs16 7-24}{\b0 \fs16
Using}{\b0 \fs16 the}{\b0 \fs16 4511}{\b0
\fs16 IC}{\b0 \fs16 to}{\b0 \fs16 drive}{\b0 \fs16 a}{\b0 \fs17 VF}{\b0 \fs
16 display }\par
}
\cf0 The block diagram for the 4511 BCD-to-seven-segment
latch/decoder/drive
r
IC is the same as

the 74HC4543{\fs18 IC} in Fig. 7-18a. The 4511 latch/decoder/driver
has a
4-bit latch (memory unit).
latch section{\i (LE} input) of the 4511{\fs18 IC} is disabled in Fig. 7-24 b
y holding it LOW. With the latch
\par}{\phpg\posx859\pvpg\posy6180\absw9184\absh1941 \sl-246 \f20 \fs18 \cf0 disa
bled, data from the BCD input passes through to the decoder section{\fs18 of} t
he 4511 IC. Note that a
5 {\f10 \fs28 +} 12-V dc power supply is used for both the vacuum fluoresc
ent display and the 4511{\fs18 CMOS} chip.
4000 CMOS series is ideally suited for driving VF displays because this family o
f ICs can operate
\par}{\phpg\posx859\pvpg\posy6180\absw9184\absh1941 \sl-268 \f20 \fs18 \cf0 on a
wide range{\fs18 of} higher dc voltages up to{\f10 \fs29 +}{\fs18 18} V. T
he decoder section of the 4511 translates from
BCD code to seven-segment code. Figure 7-25b shows how the numbers are
formed using the
decoder. Note especially the formation of the{\fs18 6} and{\fs18 9} i
n Fig. 7-25b. The driver section of the \par
}
\par
}
{\phpg\posx6199\pvpg\posy9252\absw577\absh1958 \f10 \fs15 \cf0 \f10 \fs15 \cf0 {\i \f20 \fs10 V}{\i \f20 \fs10 D}{\i \f20 \fs10 D }
\f30 \fs22 -}{\i \f30 \fs22 f }
\f20 \fs14 14 }
\fs14 -}{\i \fs14 g }
11 - }
0 \fs14 l3}{\i \fs13
a }
0 \fs15 12 }
\f20 \fs14 -}{\i \f20 \fs14 b }
\fs24 L }
0 \fs15 10 }
\fs14 -}{\i \fs14 d }
\par}{\phpg\posx6199\pvpg\posy9252\absw577\absh1958 \sl-225 \f10 \fs15 \cf0 -{\f
20 \fs14 e }\par
}
\par
}
\par
}
ual-in-line package
\fi1376 {\fs15 16 }\par
}
cf0 B
i0 C }\par
}
\cf0 LE
fi97 {\b \f30 \fs16 D }
fi83 {\b \fs14 A }\par
}
5 \cf0 Top{\fs14 view }
{\i \f10 \fs13 (a)}{\fs15 Pin}{\fs14 diagram }\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
20 \fs15 \cf0 (6){\i0 \fs14 Format}{\i0 \fs15 of}{\i0 \fs14 decimal}{\i0 \fs1
4 numbers }
The}{\b\i0 \fs16 451}{\i
0 \fs16 1}{\i0 \fs16 BCD-to-seven-segment}{\i0 \fs16
latch/decoder/driver}{
\i0 \fs16
IC }\par
}
.{\f10 \fs16 71 }\par
}
}
\par
}
511 IC has its outputs connected directly to the plates (anodes) of t
he VF display.{\b \fs19 A} HIGH at
output of the driver activates (lights) the segment on the seven-segment VF disp
lay (assuming the
lay's control grid is activated).{\b \fs19 A} LOW at the output of the driver d
eactivates the segment of the
\par}{\phpg\posx845\pvpg\posy1369\absw9153\absh3487 \sl-238 \f20 \fs18 \cf0 VF d
isplay, and it does not light.
62 {\b A} pin diagram for the 4511 BCD-to-seven-segment
latch/decoder/dr
iver
CMOS IC is repro\par}{\phpg\posx845\pvpg\posy1369\absw9153\absh3487 \sl-242 \f20 \fs18 \cf0 duce
d in Fig. 7-25a. Recall that the power pins are labeled{\i VDD}for p
ositive (pin 16) and{\b\i \f30 \fs21 Vss}for
tive (pin{\b\i \fs19 7).}The{\i \fs19 LE} pin on the 4511 IC is{\fs19 a} lat
ch enable input. Latch enable is an active{\fs19 HIGH }
t and is shown disabled in the circuit in Fig. 7-24.{\fs19 To} disab
le the latch means data will pass
\par}{\phpg\posx845\pvpg\posy1369\absw9153\absh3487 \sl-235 \f20 \fs18 \cf0 thro
ugh the latch from BCD inputs to the decoder. The latch is said to be transpare
nt when disabled.
\par}{\phpg\posx845\pvpg\posy1369\absw9153\absh3487 \sl-237 \f20 \fs18 \cf0 With
the{\b\i \fs19 LE} enabled (HIGH), four memory cells (or latches) hold cur
rent data{\fs19 on} the input to the
decoder. With the latches enabled, changes at the BCD inputs (labeled{\b\i \f10
\fs18 A,}{\b\i \fs19 B,}{\b\i \fs18 C,} and{\b\i \f30 \fs21 D)}to the
\par}{\phpg\posx845\pvpg\posy1369\absw9153\absh3487 \sl-242 \f20 \fs18 \cf0 451{
\fs19 1} IC will be disregarded. The 4511 IC has two active LOW inputs. When the
(light test) input is
vated with{\fs19 a} LOW, all IC outputs go HIGH to test the attached disp
lay. When the
(blanking
t) is activated with a LOW, all outputs go LOW and all segments of the attached
display go blank.
{\b \f10 \fs16 SOLVED}{\f10 \fs16 PROBLEMS }\par
}
f0 7.42 \par
}
efer to Fig. 7-24.{\b \fs19 A }
\par}{\phpg\posx1453\pvpg\posy5365\absw2367\absh726 \sl-233 \f20 \fs18 \cf0 deco
der/driver IC and the

}
5,{\fs18 12)-Vdc}{\fs18 power}{\fs18 supply}{\fs18 is}{\fs18 being}{\fs18
used}{\fs18 because}{\fs18 the}{\b CMOS}{\fs18 4511 }
37 {\fs18 (LCD,}{\fs18 VF)}{\fs18 display}{\fs18 both}{\fs18 operate}{\fs18
at}{\fs18 this}{\fs18 voltage. }\par
}
\cf0 In Fig.{\fs17 7-24,} a{\fs17 12-V} power supply is used because the
CMOS{\fs17 4511}{\fs16 IC} and{\fs17 VF} display both operate at
\par}{\phpg\posx1457\pvpg\posy6233\absw8325\absh904 \sl-215 \f20 \fs17 \cf0 this
voltage.
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 7-24.}{\fs18 In}{\fs18 this}{
\fs18 example,}{\fs18 the}{\fs18 control}{\fs18 grid}{\fs18 on}{\fs18
the}{\fs18 VF}{\fs18 display}{\fs18 is}{\fs18
(activated, }\
par
}
eactivated) by being connected directly to{\f10 \fs30 + }
}
{\fs18 V. }\par
}
f0 7.43 \par
}
n this example, the control grid{\fs18 on} the VF display{\b is} activated by
being connected directly to{\f10 \fs26 + }\par
}
efer to{\b \fs19 Fig.} 7-24. In this example, which plates{\fs18 of} the VF di
splay have{\f10 \fs29 + }\par
}
{\phpg\posx1453\pvpg\posy8661\absw805\absh510 \f20 \fs18 \cf0 \f20 \fs18 \cf0 to
them.
}
cf0 12{\fs17 V. }\par
}
f0 7.44 \par
}
2{\fs19 V} (HIGH) applied \par
}
cf0 7.45 \par
}
cf0 7.46 \par
}
7 \cf0 In{\fs17 this}{\fs17 example,}{\fs17 decimal} 7{\fs17 appears}{\fs17
on}{\fs17 the} VF{\fs17 display,}{\fs17 meaning}{\fs17 that}{\fs17 segment
s}{\fs17 (plates)}{\i \f10 \fs14 a,}{\b\i b,}{\fs17 and}{\b\i \fs16 c}{\f
s17 are }
s17 activated}{\f10 \fs14 (+} 12{\fs16 V}{\fs17 applied}{\fs17 to}{\fs17
them). }
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 7-24.}{\fs18 What}{\fs18 is}{\fs
18 the}{\fs18 purpose}{\fs18 of}{\fs18 resistor}{\i \fs19 R,}{\fs18 in}{\
fs18 this}{\fs18 circuit? }
364 {\fs17 Series}{\fs17 resistor}{\b\i \f30 \fs19 R,}{\fs17 in}{\fs17 Fig.
} 7-24{\fs17 limits}{\fs17 current}{\fs17 through}{\fs17 the}{\fs17 fi
laments}{\fs17 (cathode)}{\fs17 to}{\b \fs16 a}{\fs17 safe}{\fs17 level.
}
8 BCD}{\fs18 input}{\fs18 was}{\fs18 0101,}{\fs18 the}{\fs18 decimal}{\fs1
8 appearing}{\fs18 on}{\fs18 the}{\fs18 VF}{\fs18 display}{\fs18 would }
s18 be}{\f10 \fs16 -. }
\fs16 Solution: }
364 {\b \fs17 If}{\fs17 the}{\fs17 input}{\fs17 was}{\fs16 OlOl,,,}{\fs17
in}{\fs17 Fig.} 7-24,{\fs17 the}{\fs17 decimal}{\fs17 appearin
g}{\fs17 on}{\fs17 the} VF{\fs17 display}{\fs17 would}{\fs17 be} 5.
8 BCD}{\fs18 input}{\fs18 was}{\fs18 1000,}{\fs18 the}{\fs18 decimal}{\fs1
8 appearing}{\fs18 on}{\fs18 the}{\fs18 VF}{\fs18 display}{\fs18 would }\p
ar
}
be{\f10 \fs19 -}and segments (plates)
366 {\fs17 If}{\fs17 the}{\fs17 input}{\fs17 in}{\fs17 Fig.}{\fs17 7-2
4}{\fs17 was}{\fs17 1000,,,, }
s17 (plates)}{\fs17 would}{\fs17 be}{\fs17 activated. }\par
}
8 \cf0 would be activated (HIGH).
{\fs17 the}{\fs17 VF}{\fs17 display}{\fs17 would}{\fs17 show}{\fs17 d
ecimal}{\b \fs16 8}{\fs17 and}{\fs17 all}{\fs17 the}{\fs17 segments }\
par
}
cf0 7.47 \par
}

0 164 \par
}
DE CONVERSION \par
}
AP.{\b 7 }\par
}
f0 7.48 \par
}
efer to Fig. 7-24. If the \par
}
lamp test) input is activated or goes \par
}
HIGH,{\fs18 LOW),}{\fs18 all }\par
}
egments of the seven-segment{\fs19 VF} display would light.
}
{\phpg\posx1799\pvpg\posy2245\absw462\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 If
the \par
}
nput in Fig.{\b 7-24} was activated with a LOW, all segments of the{\
fs17 VF} display would light. \par
}
f0 7.49 \par
}
efer to Fig.{\i \f10 \fs17 7-25a.} When connecting power to this{\fs18 4000}
series CMOS{\b \fs18 IC,} the positive{\fs18 of} the \par
}
ower supply is connected to the \par
}
s18 \cf0 (VDD,{\b0 \fs19 Vss)}{\b0\i0 \fs19 pin. }\par
}
cf0 ( V D U , \par
}
\cf0 Vss){\i0 \fs19 pin,}{\i0 \fs19 while}{\i0 \fs19 the}{\i0 \fs19 negative}
{\i0 \fs19 is}{\i0 \fs19 connected}{\i0 \fs19 to}{\i0 \fs19 the }\par
}
\cf0 Solution:
fi372 {\b0 \fs17 On}{\fs17 4000}{\b0 \fs17 series}{\b0 \fs17 CMOS}{\b0 \fs1
7 ICs}{\b0 \fs17 (see}{\b0 \fs17 the}{\fs17 4511}{\b0 \fs17 in}{\b0 \f
s17 Fig.}{\fs17 7-25a),}{\b0 \fs17 the}{\b0\i VDD}{\b0 \fs17 pin}{\b0 \f
s17 is}{\b0 \fs17 connected}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 po
sitive, }
\b0 \fs17 while}{\b0 \fs17 the}{\b0\i \fs17 Vss}{\b0 \fs17 pin}{\b0 \fs17
is}{\b0 \fs17 connected}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 negative
}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 power}{\b0 \fs17 supply. }\par
}
f0 7.50 \par
}
n a calculator, a(n) \par
}
cf0 ( a ) \par
}
\cf0 SupplementaryProblems
{\f20 \fs17 (decoder,}{\f20 \fs17 encoder)}{\f20 \fs17 would}{\f20 \fs17 tran
slate}{\f20 \fs17 from}{\f20 \fs17 decimal}{\f20 \fs16 to}{\f20 \fs17 binary
while}{\f20 \fs17 a(n) }\par
}
cf0 ( b ) \par
}
\cf0 (decoder, encoder) would translate from binary to the decimal output.
i Ans.}{\i \fs17
(}{\i \fs17 a}{\i \fs17 )}
encoder{\i
(b)} decod
er \par
}
\cf0 It is characteristic that a(n)
i \fs16 Ans.}
encoder \par
}
f0 7.51 \par
}
decoder, encoder) has only one active input at any given time. \par
}
f0 7.52 \par
}
efer to Fig.{\b 7-26.} This encoder has active
\par}{\phpg\posx1431\pvpg\posy7075\absw3464\absh390 \sl-217 \f20 \fs17 \cf0 LOW)
outputs. \par
}
HIGH, LOW) inputs and active \par
}
{\phpg\posx9067\pvpg\posy7077\absw623\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 (H
IGH, \par
}
s17 \cf0 Am.{\b0\i0 \fs17
The}{\i0 \fs17 74148}{\b0\i0 \fs17 encoder}{\b0\
i0 \fs17 has}{\b0\i0 \fs17 active}{\b0\i0 \fs17 LOW}{\b0\i0 \fs17 inputs}{\
b0\i0 \fs17 and}{\b0\i0 \fs17 active}{\b0\i0 \fs17 LOW}{\b0\i0 \fs17 outpu
ts,}{\b0\i0 \fs17 as}{\b0\i0 \fs17 shown}{\b0\i0 \fs17 by}{\b0\i0 \fs17 the}

{\b0\i0 \fs17 small}{\b0\i0 \fs17 bubbles }
{\b0\i0 \fs17 at}{\b0\i0 \fs17 the}{\b0\i0 \fs17 inputs}{\b0\i0 \fs17 and
}{\b0\i0 \fs17 outputs}{\b0\i0 \fs17 of}{\b0\i0 \fs17 the}{\b0\i0 \fs17
logic}{\b0\i0 \fs17 symbol}{\b0\i0 \fs17 in}{\b0\i0 \fs17 Fig.}{\i0 \fs17
7-26. }\par
}
puts \par
}
\cf0 3
f0 {\b0 \fs17 H }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
fi21 {\b0 \fs17 L }
\b0 \fs17 H }
\b0 \fs17 H }
fi22 {\b0 \fs17 H }\par
}
\cf0 4
f0 {\b0 \fs17 H }
fi20 {\b0 \fs17 X }
fi20 {\b0 \fs17 X }
fi24 {\b0 \fs17 X }
fi24 {\b0 \fs17 L }
\b0 \fs17 H }
\b0 \fs17 H }
\b0 \fs17 H }
fi26 {\b0 \fs17 H }\par
}
tputs
fi203 {\b\i \f10 \fs15 A}{\b\i \f10 \fs15 ,}{\b\i \f10 \fs10
A0 }\par
}
1 L
ar
}
\sl-217
\sl-221
\sl-221
\sl-217
\sl-224
\f20
\f20
\f20
\f20
\f20
\fs17
\fs17
\fs17
\fs17
\fs17
\cf0
\cf0
\cf0
\cf0
\cf0
L
L
H
H
\fi2
\sl-219 \f20 \fs17 \cf0 L

\sl-224 \f20 \fs17 \cf0 H
\sl-221 \f20 \fs17 \cf0 H \p
\fs17 \cf0 \f20 \fs17 \cf0 H
\par}{\phpg\posx9298\pvpg\posy9218\absw187\absh1791 \sl-217 \f20 \fs17 \cf0 L

\par}{\phpg\posx9298\pvpg\posy9218\absw187\absh1791 \sl-221 \f20 \fs17 \cf0 H
2 L
2 H \par
}
}
\par
}
cf0 O
0 {\b0 \f20 \fs14 2 }\par
}
{\b \fs15 3 }
41 {\b \fs14 4 }
i \f10 \fs14 -}{\b\i \f10 \fs14 5 }
{\b \fs14 -}{\b \fs14 7 }\par
}
{\phpg\posx1967\pvpg\posy10516\absw359\absh459 \f10 \fs39 \cf0 \f10 \fs39 \cf0 ' \par
}
b \par
}
cf0 1 \par
}
\cf0 Octal
\par}{\phpg\posx1403\pvpg\posy10031\absw481\absh348 \sl-193 \b \f20 \fs15 \cf0 i
nput \par
}
\cf0 encoder{\i \f10 \fs14
A,}{\b0 \f10 \fs26 & }

cf0 \fi1131 {\fs15 2s }
\fi706 {\b0 \fs21 4 }
\fi1147 {\f10 \fs13 1s }
\fi711 {\fs6 *}{\fs6 ,}{\fs6 I }
{\f10 \fs13 (74148) }\par
}
}
\cf0 Fig.{\f10 \fs15 7-26}{\b0 \fs17
The}{\fs17 74148}{\b0 \fs17 octal-to
-binary}{\b0 \fs17 priority}{\b0 \fs17 encoder }\par
}
\cf0 Refer{\fs17
to} Fig.{\b 7-26.} If input{\b
7} were{\b\i \fs16
activated} with a
\i \f10 \fs15 A,=}{\f10 \fs18
,}{\b\i \fs17 A}{\b\i \fs17 ,}{\dn
006 \f10 \fs13 =}{\f10 \fs17
,} and{\b\i \fs16 A}{\b\i \fs16 ,}{
\b\i \fs16 =}
(HIGH, LOW). \par
}
cf0 Priority \par
}
\fs15 \cf0 Binary
\par}{\phpg\posx4263\pvpg\posy10019\absw634\absh332 \sl-175 \b \f20 \fs15 \cf0 o
utputs \par
}
\cf0 0
f0 {\b0 \fs17 H }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
fi36 {\b0 \fs17 L }\par
}
\cf0 1
f0 {\b0 \fs17 H }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 L }
\b0 \fs17 H }\par
}
\cf0 2
f0 {\b0 \fs17 H }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 X }
\b0 \fs17 L }
\b0 \fs17 H }
\b0 \fs17 H }\par
}
\cf0 5
f0 {\b0 \fs17 H }
fi26 {\b0 \fs17 X }
fi26 {\b0 \fs17 X }
fi30 {\b0 \fs17 L }
\b0 \fs17 H }
\b0 \fs17 H }
\b0 \fs17 H }
\b0 \fs17 H }
fi29 {\b0 \fs17 H }\par
}
\cf0 6

f0 {\b0 \fs17 H }
fi31 {\b0 \fs17 X }
fi31 {\b0 \fs17 L }
\b0 \fs17 H }
\b0 \fs17 H }
\b0 \fs17 H }
\b0 \fs17 H }
fi23 {\b0 \fs17 H }
fi33 {\b0 \fs17 H }\par
}
\cf0 7
f0 \fi20 {\b0 \fs17 H }
fi36 {\b0 \fs17 L }
\b0 \fs17 H }
fi20 {\b0 \fs17 H }
fi20 {\b0 \fs17 H }
fi22 {\b0 \fs17 H }
fi22 {\b0 \fs17 H }
fi28 {\b0 \fs17 H }
fi36 {\b0 \fs17 H }\par
}
s15 \cf0 A ,
\cf0 \fi36 {\b0\i0 \f20 \fs17 H }
\fi48 {\b0\i0 \f20 \fs17 L }
\fi42 {\b0\i0 \f20 \fs17 L }
\fi49 {\b0\i0 \f20 \fs17 L }
\fi47 {\b0\i0 \f20 \fs17 L }
\fi39 {\b0\i0 \f20 \fs17 H }
\fi42 {\b0\i0 \f20 \fs17 H }
\fi48 {\b0\i0 \f20 \fs17 H }
\fi48 {\b0\i0 \f20 \fs17 H }\par
}
\cf0 H{\b0\dn006 \f10 \fs11 =}{\f20 \fs15 HIGH.}{\f20 \fs15 L }\par
}
9 \cf0 ( U ) \par
}
\cf0 Logic symbol \par
}
={\b \f20 \fs15 LOW,}{\b \fs14 X}{\fs13 =}{\b \f20 \fs14 irrelevant }
\fi193 {\b\i \fs14 (}{\b\i \fs14 h}{\b\i \fs14 )}{\b \f20 \fs15 Simplified}{
\b \f20 \fs14 truth}{\b \f20 \fs15 table }\par
}
cf0 7.53 \par
}
(HIGH, LOW), the output would be \par
}
If}{\b0\i0 input}{\i0 \fs17 7}{\b0\i0 were}{\b0
\i0 activated}{\b0\i0 with}{\b0\i0 a}{\b0\i0 LOW}{\b0\i0 on}{\b0\i0
the}{\i0 74148}{\b0\i0 encoder,}{\b0\i0 the}{\b0\i0 outputs}{\b0\i0 wou
ld}{\b0\i0 be}{\f10 \fs15 A,}{\b0\i0 \f10 \fs13 =}{\b0\i0 LOW, }
0 {\fs16 A}{\fs16 ,}{\b0\i0 =LOW.}{\b0\i0 and}{\f10 \fs16 A,}{\b0\i0 \f10
\fs13 =}{\b0\i0 LOW. }\par
}
1 \par
}
\cf0 U \par
}
}
DE CONVERSION \par
}
\par
}
f0 7.54 \par
}
efer to Fig.{\b \fs17 7-26.} If all inputs are HIGH, the outputs wil
l be{\b \f10 \fs16 '4,}{\f10 \fs13 = }
78 (HIGH, LOW). \par
}
{\phpg\posx7591\pvpg\posy1324\absw522\absh221 \f10 \fs19 \cf0 \f10 \fs19 \cf0 ,{
\b\i \fs16 A,}{\dn006 \fs13 = }\par
}

\f20 \fs17 and}{\b\i \fs15 A,,}{\dn006 \fs13 = }\par
}
f0 7.55 \par
}
s17 \cf0 Ans.{\b0\i0 \fs17
If}{\b0\i0 \fs17 all}{\b0\i0 \fs17 inputs}{\b
0\i0 \fs17 to}{\b0\i0 \fs17 the}{\i0 74148}{\b0\i0 \fs17 encoder}{\b0\i0 \
fs17 are}{\b0\i0 \fs17 HIGH,}{\b0\i0 \fs17 the}{\b0\i0 \fs17 outputs}{\b0\
i0 \fs17 will}{\b0\i0 \fs17 be}{\b0\i0 \fs17 all}{\b0\i0 \fs17 HIGH. }
\cf0 \fi24 {\b0\i0 \fs17 Refer}{\b0\i0 \fs17
to}{\b0\i0 \fs17
Fig.}{\i0
7-26.}{\b0\i0 \fs17
If}{\b0\i0 \fs17
input}{\i0
3}{\b0\i0 \fs17
is}
{\b0\i0 \fs17
activated,}{\b0\i0 \fs17
the}{\b0\i0 \fs17
outputs}{\b0\i
0
will}{\b0\i0 \fs17
be} A{\b0\i0 \f10 \fs15
-}{\b0 \f10 \fs14
(}{\b0 \f10 \fs14 a}{\b0 \f10 \fs14 )}{\b0\i0 \f10 \fs19
,}{\f10 \fs16 A,
}{\b0\i0\dn006 \f10 \fs13 = }\par
}
{\phpg\posx7055\pvpg\posy2499\absw171\absh123 \f20 \fs11 \cf0 \f20 \fs11 \cf0 2- \par
}
s17 \cf0 A , ={\fs17
(}{\fs17 c}{\fs17 )}{\b0\i0 \fs17
(HIGH,LOW)
. }\par
}
cf0 ( b ){\i0 \f10 \fs17
,}{\i0 \fs17 and }\par
}
f0 7.56 \par
}
s17 \cf0 Ans.{\fs17
(}{\fs17 a}{\fs17 )}{\b0\i0 \fs17
HIGH}{\b0 \fs17
(b)}{\b0\i0 \fs17
LOW}{\b0 \f10 \fs14
(c)}{\b0\i0 \fs17
LOW }
\cf0 \fi35 {\b0\i0 \fs17 List}{\b0\i0 \fs17 the}{\b0\i0 \fs17 binary}{\b0\i0
\fs17 output}{\b0\i0 \fs17 indicator}{\b0\i0 \fs17 reading}{\i0 (3}{\b0\
i0 \fs17 bits)}{\b0\i0 \fs17 for}{\b0\i0 \fs17 each}{\b0\i0 \fs17 of}{\b0\i
0 \fs17 the}{\b0\i0 \fs17 input}{\b0\i0 \fs17 pulses}{\b0\i0 \fs17 shown}
{\b0\i0 in}{\b0\i0 \fs17 Fig.}{\i0 7-27. }\par
}
s17 \cf0 Ans.{\b0\i0 \fs17
pulse}{\fs17 a}{\b0\i0\dn006 \f10 \fs11 =}{\
b0\i0 000 }
\fi535 {\b0\i0 \fs17 pulse}{\fs17 b}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17 010
}\par
}
ulse{\b\i \fs16 c}{\f10 \fs13 =} 100
e{\b\i \fs17 d}{\f10 \fs14 =} 111 \par
}
ulse{\b\i \fs16 e}{\f10 \fs13 =}{\fs17 101 }
e{\i \f30 \fs19 f}{\i \f30 \fs19 =} 010 \par
}
ulse{\fs15 g}{\f10 \fs13 =} 011

e{\b\i h}{\f10 \fs13 =} 001 \par
}
ulse{\b\i \f30 \fs18 i}{\f10 \fs13 =}{\fs17 110 }
e{\i \f10 \fs15 j}{\f10 \fs13 =} 111 \par
}
fs15 \cf0 output
dicators \par
}
cf0 Priority
\par}{\phpg\posx6289\pvpg\posy5321\absw672\absh328 \sl-173 \b \f20 \fs15 \cf0 en
coder \par
}
f0 0 \par
}
p+Jqo \par
}
{\phpg\posx4011\pvpg\posy6318\absw623\absh168 \f10 \fs14 \cf0 \f10 \fs14 \cf0 0]
1--+--0 \par
}
cf0 3 \par
}
4 \cf0 j \par
}
15 \cf0 i \par
}
14 \cf0 h \par
}
4 \cf0 g \par
}
4 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
f0 c \par
}
cf0 b \par
}
cf0 a \par
}
\cf0 Fig.{\f30 \fs18 7-27}{\b0 \fs17 Encoder}{\b0 \fs17 pulse-train}{\b0 \f
s17 problem }\par
}
f0 7.57 \par
}
efer to Fig.{\b \fs17 7-28.} The{\b \fs17 7443} decoder has active
H, LOW) outputs. \par
}
HIGH, LOW) inputs and active \par
}
s17 \cf0 Ans.{\b0\i0 \fs17
The}{\i0 7443}{\b0\i0 \fs17 decoder}{\b0\i0 \fs
17 has}{\b0\i0 \fs17 active}{\b0\i0 \fs17 HIGH}{\b0\i0 \fs17 inputs}{\b0\i0
\fs17 and}{\b0\i0 \fs17 active}{\b0\i0 \fs17 LOW}{\b0\i0 \fs17 outputs,}{\
b0\i0 \fs17 based}{\b0\i0 \fs17 on}{\b0\i0 \fs17 the}{\b0\i0 \fs17 logic}{\
b0\i0 \fs17 symbol}{\b0\i0 \fs17 and }
\fi27 {\b0\i0 \fs17 truth}{\b0\i0 \fs17 table}{\b0\i0 \fs17 in}{\b0\i0 \fs1
7 Fig.}{\i0 7-28. }\par
}
Refer to Fig.{\b \fs17 7-28,} With an input of{\fs17 0110,} the \par
}
activated with a{\i
(}{\i b}{\i )}
(HIGH, LOW). \par
}
s17 \cf0 ( a ) \par
}
(decimal number) output of the{\b \fs17 7443} decoder{\b is }\par
}
cf0 7.58 \par
}
fs15 \cf0 Am.{\f20 \fs17
(}{\f20 \fs17 a}{\f20 \fs17 )}{\i0 \f20 \fs17
3}{\f20 \fs17
(}{\f20 \fs17 h}{\f20 \fs17 )}{\b0\i0 \f20 \fs17
LOW }\
par
}
cf0 7.59 \par
}
cf0 7.60 \par
}
7 \cf0 Refer to Fig.{\b \fs17 7-28.} The invalid input{\fs17
1111} gen
erates all
i28 decoder.
b\i \fs17 Ans.}{\b \fs17
Is }
0 \fi30 Refer to Fig.{\b \fs17 7-28.} The{\b \fs17 7443} IC{\b is} a deco
der that translates from
i24 (decimals, hexadecimals).{\b\i
Ans.}{\b\i \fs17
(}{\b\i \fs17
a}{\b\i \fs17 )}{\b \fs17
XS3}{\i \fs16
(b)} decimals \par
}
fs17 \cf0 (OS,{\i0 Is)}{\b0\i0 \fs17 at}{\b0\i0 \fs17 the}{\b0\i0 \fs17
outputs}{\b0\i0 \fs17 of}{\b0\i0 \fs17 the}{\i0 \fs17 7443 }\par
}
s17 \cf0 ( a ) \par
}
(BCD,{\b \fs17 XS3)} code{\fs16 to }\par
}
s17 \cf0 ( 6 ) \par
}
cf0 7.61 \par
}
Refer to Fig.{\b \fs17 7-28.} When the outputs of the{\b \fs17 7443}
decoder are{\b\i \fs17 deactivated,} they are at logical
s17 (0,}{\b \fs17 1).}{\b\i \fs17
Ans.}{\fs17
1} (HIGH) \par
}
\par
}
DE CONVERSION \par
}
}
3 \par
}
\par
}
13 \cf0 A
{\f20 \fs14 B }
{\b0 \f20 \fs22 c }\par
}
03 \cf0 --ID \par
}
s13 \cf0 (a){\i0 \f20 \fs14 Logic}{\i0 \f20 \fs15 symbol }\par
}
{\phpg\posx3461\pvpg\posy3117\absw359\absh223 \f10 \fs19 \cf0 \f10 \fs19 \cf0 ob
- \par
}
!E \par
}
fs14 \cf0 1{\b0 \fs14 -of-1}{\fs14 0 }
fs15 decimal }
i31 {\fs15 output }\par
}
par
}
0 \fs15 \cf0 (b){\fs15 Truth}{\fs15 table }
f0 {\fs16 Fig.}{\fs16 7-28}{\b0 \fs16
The}{\fs16 7443}{\b0 \fs16 XS3-to-de
cimal}{\b0 \fs16 decoder }\par
}
fs21 \cf0 xs3
fs15 input }\par
}
fs14 \cf0 XS3-to\par}{\phpg\posx2743\pvpg\posy3429\absw671\absh482 \sl-172 \b \f20 \fs14 \cf0 {\
fs15 decimal }
fs15 decoder }\par
}
cf0 (7443) \par
}
f0 7.62 \par
}
ist the{\i \fs17 decimal} output indicator activated for each pulse going
into the{\b 7443} decoder shown in Fig.{\fs17 7-29. }\par
}
s17 \cf0 Ans.{\b0\i0 \fs16
pulse}{\fs16 a}{\b0\i0\dn006 \f10 \fs11 =}{\b
0\i0 6 }
\fi537 {\b0\i0 \fs16 pulse}{\b0 b}{\b0\i0\dn006 \f10 \fs11 =}{\i0 \f30 \fs1
8 4 }
\fi538 {\b0\i0 \fs16 pulse}{\b0\i0 \fs16 c}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs1
6 all}{\b0\i0 \fs16 outputs}{\b0\i0 \fs16 deactivated }
\fi1318 {\b0\i0 \fs16 (invalid}{\b0\i0 \fs16 XS3}{\b0\i0 \fs16 input) }\par
}
lse{\i \f10 \fs16 d}{\f10 \fs13 =}{\fs16 9 }
{\fs16 e}{\dn006 \f10 \fs11 =}{\fs17 0 }
{\i \f30 \fs19 f=}{\fs17 8 }

{\fs15 g}{\dn006 \f10 \fs11 =} 1 \par
}
lse{\i \fs16 h}{\dn006 \f10 \fs10 =} 3
{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =}{\fs17 5 }\par
}
lse{\i \f10 \fs15 j }\par
}
{\f20 \fs16 all}{\f20 \fs16 outputs}{\f20 \fs16 deactivated }
62 {\f20 \fs16 (invalid}{\b \f20 \fs17 XS3}{\f20 \fs16 input) }\par
}
\cf0 Output indicators \par
}
1 \par
}
O \par
}
t l \par
}
\cf0 (7443) \par
}
0
0 \fs14 0}{\b\i \fs10 O }\par
}
15 \cf0 j \par
}
s15 \cf0 i \par
}
s15 \cf0 h \par
}
s15 \cf0 g \par
}
s15 \cf0 f \par
}
s15 \cf0 e \par
}
s15 \cf0 d \par
}
s15 \cf0 c \par
}

s15 \cf0 b \par
}
s15 \cf0 a \par
}
\cf0 Fig. 7-29{\b0 \fs16
Decoder}{\b0 \fs16 pulse-train}{\b0 \fs16 proble
m }\par
}
cf0 7.63 \par
}
cf0 7.64 \par
}
\cf0 Battery and solar-powered equipment most commonly use
\i \fs17 Ans.}
LCD
\fi30 {\fs17 If} an LED emits light,{\fs17 a} liquid-crystal display is
said to
\i \fs17 Ans.}
control \par
}
(LCD, LED) displays. \par
}
(control, generate) light. \par
}
.{\fs17 71 }\par
}
DE CONVERSION \par
}
\par
}
f0 7.65 \par
}
f0 7.66 \par
}
hat is the main disadvantage of liquid-crystal displays?
i \fs17 Am.}
Slow switching speeds or the need for ambient light.
\fi25 Refer to Fig.{\fs17 7-15.} On an LCD, only segments that are
driven by \par
}
quare-wave signals are activated and visible on the display. \par
}

CDs that show \par
}
in-phase, out-of-phase) \par
}
s15 \cf0 Ans.{\b0\i0 \f20 \fs16
out-of-phase }\par
}
f0 7.67 \par
}
black, frosty white) segments on{\b\i \f30 \fs12 ii} silvery background
are referred to as \par
}
ield-effect liquid-crystal displays. \par
}
15 \cf0 Ans.{\b0\i0 \f20 \fs16
black }\par
}
f0 7.68 \par
}
\cf0 Square-wave signals are required when driving
i \f10 \fs15 Ans.}
liquid-crystal \par
}
liquid-crystal, VF) displays. \par
}
f0 7.69
7.70
{\fs18 7.71 }\par
}
he liquid-crystalsandwiched between glass plates{\fs17 on} an LCD{\fs17 is}
called \par
}
\cf0 Refer to Fig. 7-17a. The decoder and LCD driver are
\fi33 Refer to Fig.{\fs17 7-17a.} The LCD driver section consists of seven
i \fs17 Ans.}
XOR \par
}
{\phpg\posx7791\pvpg\posy3949\absw410\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 fl
uid. \par
}
CMOS, TTL) devices. \par
}
s16 \cf0 Am.{\b0\i0 \f20 \fs16
nematic }

\cf0 \fi82 {\f20 \fs16 Ans.}{\b0\i0 \f20 \fs16
CMOS }\par
}
\cf0 (AND,{\fs17 XOR)}{\b0 \fs16 gates. }\par
}
f0 7.72 \par
}
\cf0 Refer to Fig. 7-30. What{\fs17 is} the decimal reading on the LCD
for each input pulse{\fs16 (a} through{\b\i d). }
\i \fs17 Ans.}
pulse{\b\i \fs8
(}{\b\i \fs8 I}{\f10 \fs11 =}{\fs17
0 }
538 pulse{\i \fs16 h}{\dn006 \f10 \fs11 =}{\fs16 9 }
538 pulse{\f30 \fs12 (I}{\dn006 \f10 \fs11 =}{\b \fs16 3 }
538 pulse{\i \f10 \fs16 d}{\dn006 \f10 \fs11 =}{\fs17 6 }
\fi30 Refer to Fig. 7-30. For input pulse{\b \f10 \fs14
c} only, wh
ich drive lines to the LCD have out-of-phase signals
29 appearing{\fs17 on} them?
\i \fs17 Ans.}
Out-of-phase signals are activated on segments{\b\i \f10 \
fs14 a,}{\i \fs16 b,}{\fs16 c,}{\i \f10 d,} and{\b\i \fs15 g}{\b\i \fs1
5 . }\par
}
f0 7.73 \par
}
1 \cf0 U \par
}
cf0 Inputs
i70 {\b0 \fs14 1}{\b0 \fs15
1 }\par
}
{\phpg\posx3657\pvpg\posy9226\absw360\absh107 \f10 \fs9 \cf0 \f10 \fs9 \cf0 --t\par
}
0 \fs15 \cf0 11m\par}{\phpg\posx2541\pvpg\posy9567\absw1376\absh1081 \sl-380 \b \f20 \fs15 \cf0
{\b0 \fs22 -}{\b0 \fs22 -}{\b0 \fs22 i}{\b0 \fs22 l}{\b0 \fs22 o}{\b0 \fs22
o}{\b0 \fs22 o }
cf0 \fi117 {\f10 \fs14 O}{\f10 \fs14 O}{\f10 \fs14 l}{\f10 \fs14 l}{\f10 \
fs14 [}{\f10 \fs14 O}{\f10 \fs14 - }
\fi117 {\i \fs15 d}{\i \fs15
c}{\i \fs15
b}{\i \fs15
a }\par
}
}
cf0 IS.{\i \fs15 A }

0 \fi246 {\i \fs15 B }\par
}
{\phpg\posx4581\pvpg\posy9998\absw18\absh65 \f10 \fs5 \cf0 \f10 \fs5 \cf0 ' \par
}
s15 \cf0 8 s D \par
}
\cf0 f \par
}
s16 \cf0 BI \par
}
\fs15 \cf0 BCD-to\par}{\phpg\posx4995\pvpg\posy9209\absw986\absh2163 \sl-200 \b \f20 \fs15 \cf0 \
fi197 {\fs15 seven- }
fi130 {\fs15 segment }
fi223 {\fs15 latch/ }
fi116 {\fs15 decoder/ }
fi210 {\fs15 driver }
f0 {\fs15 (74HC4543) }
f0 \fi220 {\b0 GND}{\i \fs16
Ph }
\b0\dn006 \f10 \fs27 -}{\b0 \f10 \fs31 - }\par
}
15 \cf0 b \par}{\phpg\posx6075\pvpg\posy9037\absw265\absh482 \sl-176 \par\b\i \f20 \fs15 \
cf0 {\fs10 C }\par
}
\fs15 \cf0 f
\i0 \f10 \fs23 - }\par
}
cf0 - \par
}
\fs14 \cf0 d
\b\i0 \f20 \fs15 Common }\par
}
00{\b \fs16 Hz }\par
}
A \par
}
}
cf0 7.74 \par
}
Refer to Fig.{\b \fs17 7-30.} For input pulse{\i \fs17 b} only, which d
rive lines to the LCD have in-phase signals appearing
\par}{\phpg\posx1435\pvpg\posy13057\absw8274\absh579 \sl-212 \f20 \fs16 \cf0 on
them?
\i Ans.}
Segment{\b\i \fs16 e} is deactivated with an in-phase signa
l (decimal{\fs16 9} appears). \par
}
\par
}
DE CONVERSION \par
}
AP. 7 \par
}
f0 7.75 \par
}
VF display has parts comparable to a \par
}
diode, triode) vacuum tube. \par
}
17 \cf0 Ans.{\b0\i0 \fs17
triode }\par
}
f0 7.76 \par
}
he plates of a{\b \fs17 VF} display are coated with a
glows when bombarded by electrons. \par
}
\cf0 (barium oxide, zinc chloride) fluorescent material
i \fs17 Ans.}
barium oxide \par
}
f0 7.77 \par
}
\cf0 Refer to Fig. 7-31. List the plates (anodes) that are activated on
this seven-segment VF display.
i \fs17 Ans.}
Activated plates{\dn006 \f10 \fs11 =}{\b\i \fs17 Pb,}{\b\i
\f30 \fs19 P,,}{\b\i \f30 \fs19 Pf,}and{\b\i \fs17 Pg }\par
}
\par
}
12v+12v \par
}
\par
}
v{\fs15
+12v+12v }\par
}
\cf0 Fig.{\fs17 7-31}{\b0 \f20 \fs17 VF}{\b0 \f20 \fs17 display}{\b0 \f20 \f
s17 problem }\par
}
f0 7.78
7.79 \par
}
efer to Fig. 7-31. What decimal number would be shown on the seven-segment
VF display?
Refer to Fig. 7-22b. Why are there five separate control grids in this comm
ercial VF display? \par
}
17 \cf0 Ans.{\i0 \f30 \fs17 4 }\par
}
Each}{\b0\i0 \fs17 figure}{\b0\i0 \fs17 has
}{\b0\i0 \fs16 a}{\b0\i0 \fs17 control}{\b0\i0 \fs17 grid}{\b0\i0 \fs16
so}{\b0\i0 \fs17 digits}{\b0\i0 \fs17 (or}{\b0\i0 \fs17 colon)}{\b0\i0 \fs1
7 can}{\b0\i0 \fs17 be}{\b0\i0 \fs17 turned}{\b0\i0 \fs17 on/off}{\b0\i0
\fs17
individually.}{\b0\i0 \fs17 The}{\b0\i0 \fs17 control }
0 \fi22 {\b0\i0 \fs17 grids}{\b0\i0 \fs17 are}{\b0\i0 \fs17 commonly}{\b0\i0 \
fs17 used}{\b0\i0 \fs17 when}{\b0\i0 \fs17 multiplexing}{\b0\i0 \fs17 a}{\
b0\i0 \fs17 display. }
\cf0 \fi34 {\b0\i0 \fs17 Vacuum}{\b0\i0 \fs17 fluorescent}{\b0\i0 \fs17 displ
ays}{\b0\i0 \fs17 are}{\b0\i0 \fs17 widely}{\b0\i0 \fs17 used}{\b0\i0 \fs17
in}{\b0\i0 \fs17
(automobiles,}{\b0\i0 \fs17 solar-powered}{
\b0\i0 \fs17 equipment)}{\b0\i0 \fs17 because }
0 \fi35 {\b0\i0 \fs17 of}{\b0\i0 \fs17 voltage}{\b0\i0 \fs17 compatibility,}{
\b0\i0 \fs17 long}{\b0\i0 \fs17 life,}{\b0\i0 \fs17 low}{\b0\i0 \fs17 cost,
}{\b0\i0 \fs17 and}{\b0\i0 \fs17 good}{\b0\i0 \fs17 reliability.}
A
ns.{\b0\i0 \fs17
automobiles }\par
}
\cf0 Refer{\fs16 to} Fig. 7-23. In the VF display, wires labeled{\b\i \fs17
X} are called the
\i \fs17 Ans.}
cathodes, filaments, or heaters \par
}
\par
}

f0 7.80 \par
}
cf0 7.81 \par
}
cf0 7.82 \par
}
\cf0 Refer to Fig. 7-23. In the VF display, the shaped segments labeled{\i
\f10 \fs16 2} are called the
\i \fs17 Ans.}
plates or anodes \par
}
\par
}
cf0 7.83 \par
}
cf0 7.84 \par
}
7 \cf0 Refer to Fig. 7-32. List the decimal number shown on the VF displa
y during each pulse{\i \f10 \fs14 a} through{\b\i \f10 \fs16 d. }
b\i \fs17 Ans.}
pulse{\b\i \fs16 a}{\f10 \fs13 =} 8
i532 pulse{\i \fs16 b}{\f10 \fs13 =} 9
i534 pulse{\b\i \f10 \fs14 c}{\f10 \fs13 =}{\fs17 5 }
i534 pulse{\b\i \fs16 d}{\f10 \fs13 =} 2
0 \fi28 Refer to Fig. 7-32. During pulse{\i \f10 \fs13 a} only, what i
s the logic level at each output{\i \f10 \fs15 (a} through{\i \f10 \fs1
4
g)} of the
i24 {\b 4511} IC?
b\i \fs17 Ans.}{\fs17
All} outputs{\b\i \f10 \fs14 (}{\b\i \f10 \fs14 a}
through{\i \f10 \fs14 g}{\i \f10 \fs14 )} are HIGH or activated (decimal
{\fs16 8} is displayed). \par
}
.{\fs17 71 }\par
}
DE CONVERSION \par
}
\par
}
f0 7.85 \par
}

20 \fs16 \cf0 Fig.{\fs16 7-32}{\b0 \fs17
Decoder/driver}{\b0 \fs17
pulsetrain}{\b0 \fs17 problem }
cf0 \fi24 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 7-32.}
{\b0 \fs17 During}{\b0 \fs17 pulse}{\b0\i \f10 \fs14 c}{\b0 \fs17 only,}
{\b0 \fs17 what}{\b0 \fs17 is}{\b0 \fs17 the}{\b0 \fs17 logic}{\b0 \fs17
level}{\b0 \fs17 at}{\b0 \fs17 each}{\b0 \fs17 output}{\b0\i \f10 \fs14
(a}{\b0 \fs17 through}{\b0\i g}{\b0\i )}{\b0 \fs17 of}{\b0 \fs17 the
}
\fi21 {\fs17 4511}{\b0 \fs17 IC? }
{\i \fs17 Ans.}{\b0 \fs17
Decimal}{\b0\i \fs17 5}{\b0 \fs17 is}{\b0 \fs17
displayed. }\par
}
lse{\i \f10 \fs14 a}{\dn006 \f10 \fs11 = }
{\i b}{\dn006 \f10 \fs11 = }
{\i \f10 \fs14 c}{\dn006 \f10 \fs11 = }
{\b\i \fs17 d}{\dn006 \f10 \fs11 = }
{\b\i \fs16 e}{\dn006 \f10 \fs11 = }\par
}
IGH output
output
output
output
output \par
}
ulse{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =} HIGH output
e{\fs15 g}{\dn006 \f10 \fs11 =} HIGH output \par
}
{\b \fs33 BinaryArithmetic}{\b \fs33 and}{\b \fs33 Arithmetic}{\b \fs33 Circu
its }\par
}
\cf0 8-1{\fs18
INTRODUCTION }
fi366 {\b0 \fs18 The}{\b0 \fs18 general}{\b0 \fs18 public}{\b0 \fs18 think
s}{\b0 \fs18 of}{\b0 \fs18 digital}{\b0 \fs18 devices}{\b0 \fs18 as}{\b0
\fs18 fast}{\b0 \fs18 and}{\b0 \fs18 accurate}{\b0 \fs18 calculating}{\
b0 \fs18 machines.}{\b0 \fs18 The }
\b0 \fs18 calculator}{\b0 \fs18 and}{\b0 \fs18 digital}{\b0 \fs18 computer}
{\b0 \fs18 are}{\b0 \fs18 probably}{\b0 \fs18 the}{\b0 \fs18 reason}{\b0 \

fs18 for}{\b0 \fs18 that.}{\b0 \fs18 Arithmetic}{\b0 \fs18 circuits}{\b0 \
fs18 are}{\b0 \fs18 common}{\b0 \fs18 in }
\b0 \fs18 many}{\b0 \fs18 digital}{\b0 \fs18 systems.}{\b0 \fs18 It}{\b0 \
fs18 will}{\b0 \fs18 be}{\b0 \fs18 found}{\b0 \fs18 that}{\b0 \fs18 ra
ther}{\b0 \fs18 simple}{\b0 \fs18 combinational}{\b0 \fs18 logic}{\b0 \fs1
8 circuits}{\b0 \fs18 (several}{\b0 \fs18 gates }
\b0 \fs18 connected)}{\b0 \fs18 will}{\b0 \fs18 add,}{\b0 \fs18 subtract,}{\b
0 \fs18 multiply,}{\b0 \fs18 and}{\b0 \fs18 divide.}{\b0 \fs18 This}{\b0 \
fs18 chapter}{\b0 \fs18 will}{\b0 \fs18 cover}{\b0 \fs18 binary}{\b0 \fs18
arithmetic}{\b0 \fs18 and}{\b0 \fs18 the }
\b0 \fs18 way}{\b0 \fs18 it}{\b0 \fs18 is}{\b0 \fs18 performed}{\b0 \fs18 by
}{\b0 \fs18 logic}{\b0 \fs18 circuits. }
f0 8-2{\fs18
BINARY}{\fs18 ADDITION }
fi362 {\b0 \fs18 Adding}{\b0 \fs18 binary}{\b0 \fs18 numbers}{\b0 \fs18 is}{\
b0 \fs18 a}{\b0 \fs18 very}{\b0 \fs18 simple}{\b0 \fs18 task.}{\b0 \fs18 Th
e}{\b0 \fs18 rules}{\b0 \fs18 (addition}{\b0 \fs18 tables)}{\b0 \fs18 for}{\
b0 \fs18 binary}{\b0 \fs18 addition}{\b0 \fs18 using }
\b0 \fs19 two}{\b0 \fs18 bits}{\b0 \fs18 are}{\b0 \fs18 shown}{\b0 \fs18 in}
{\b0 \fs18 Fig.}{\b0 8-1.}{\b0 \fs18 The}{\b0 \fs18 first}{\b0 \fs18 three}{
\b0 \fs18 rules}{\b0 \fs18 are}{\b0 \fs18 obvious.}{\b0 \fs18 Rule}{\b0 \fs1
8 4}{\b0 \fs18 says}{\b0 \fs18 that,}{\b0 \fs18 in}{\b0 \fs18 binary,}{\b0
\fs18 1}{\b0 \f10 \fs27 +}{\b0\dn006 \fs18 1}{\b0\dn006 \f10 \fs13 =}{\b0 1
0 }\par
}
{\phpg\posx837\pvpg\posy5429\absw8578\absh221 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (d
ecimal{\fs19 2).} The{\fs19 1} in the sum must be carried to the next column
as in regular decimal addition. \par
}
7 \cf0 Sum
\par}{\phpg\posx3771\pvpg\posy5923\absw1565\absh784 \sl-220 \f20 \fs17 \cf0 Rule
{\fs17 1}{\fs16
O}{\fs16 +}{\fs16 O}{\fs16 =}{\fs16 O }
2{\b \f10 \fs15
0}{\b \f10 \fs15 +}{\b \f10 \fs15 1}{\b \f10 \fs15 =}{\b
\f10 \fs15 1 }
3{\fs17
1}{\fs17 +}{\fs17 0}{\fs17 =}{\fs16 1 }\par
}
ule{\b \f10 \fs15 4}{\b \f10 \fs16
1}{\f10 \fs26 +}{\dn006 \fs17 1 }\pa
r
}
{\phpg\posx5845\pvpg\posy5923\absw767\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Ca
rry out \par
}
{\f20 \fs17 0}{\f20 \fs17 and}{\f20 \fs17 carry}{\f20 \fs17 1} ={\f20 \fs1
7 10 }\par
}
24 \cf0 +{\f20 \fs15 symbol}{\b \f20 \fs15 means}{\b \f20 \fs15 add }
\fi2748 {\f20 \fs16 Fig.}{\b \fs16 8-1}{\f20 \fs17
Rules}{\f20 \fs17 for
}{\f20 \fs17 binary}{\f20 \fs17 addition }

{\f20 \fs18 Two}{\f20 \fs18 sample}{\f20 \fs18 binary}{\f20 \fs18 addition}{
\f20 \fs18 problems}{\f20 \fs18 are}{\f20 \fs18 shown}{\f20 \fs18 below: }
\fi5124 {\f20 \fs18 carries }
5235 {\f20 \fs19 14}{\f20 \fs19 14}{\f20 \fs18 1.11 }\par
}
{\phpg\posx6575\pvpg\posy8996\absw111\absh116 \f10 \fs9 \cf0 \f10 \fs9 \cf0 II \
par
}
\cf0 1
7 +o }
1 {\fs18 1 }\par
}
8 1 }
8 1 }\par
}
9 0 }
9 0 }\par
}
\cf0 4
9 +}{\fs19 2 }
7 {\b \fs18 6 }\par
}
({\f20 \fs19 I}{\f20 \fs19 ;}{\f20 \fs19 ;}{\f20 \fs19 0}{\f20 \fs19 ;}{\
f20 \fs19 ;}{\f20 \fs19 1 }\par
}
\cf0 ;;{\f20 \fs18 0}{\fs26 ;; }
\par}{\phpg\posx6445\pvpg\posy9223\absw795\absh589 \sl-288 \f10 \fs26 \cf0 {\dn0
06 \f20 \fs18 1}{\fs33 '[}{\dn006 \f20 \fs19 0 }\par
}
; 1
9 0}{\fs19
0 }\par
}
{\phpg\posx6933\pvpg\posy8996\absw117\absh116 \f10 \fs9 \cf0 \f10 \fs9 \cf0 I1 \
par
}
{\phpg\posx7287\pvpg\posy8995\absw98\absh118 \f10 \fs10 \cf0 \f10 \fs10 \cf0 II
\par
}
\par
}
{\phpg\posx1159\pvpg\posy9601\absw563\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (s
um) \par
}
ecimal) \par
}
um) \par
}
\cf0 5
\f20 \fs19 +3 }
71 {\f20 \fs19 8}{\f20 \fs18
(decimal) }\par
}
\cf0 It is now possible to design a gating circuit that will perform a
ddition. Looking at the left{\fs19 two }
\par}{\phpg\posx843\pvpg\posy10188\absw8956\absh643 \sl-238 \f20 \fs18 \cf0 colu
mns of Fig.{\fs19 8-1} reminds one{\fs18 of} a two-variable truth table. The b
inary rules are reproduced in truth
\par}{\phpg\posx843\pvpg\posy10188\absw8956\absh643 \sl-237 \f20 \fs18 \cf0 tabl
e form in Fig. 8-2. The inputs to be added are given the letters{\b\i A} and{
\i \fs19 B.} The sum output{\fs19 is} often \par
}
nputs \par
}
utputs
\fi457 {\fs16 Carry }\par
}
\cf0 0
30 {\f10 \fs16 0 }
50 {\b \f10 \fs16 1 }
50 {\b \f10 \fs15 1 }
{\b\i A }\par
}
7 \cf0 0
128 {\f10 \fs16 1 }
125 {\b \f10 \fs16 0 }
138 {\b \f10 \fs15 1 }
{\b\i +}{\b\i B}{\b\i J }\par
}
0
36 {\b \f10 \fs15 1 }

36 {\b \f10 \fs16 1 }
s17 0 }
\i \fs25 c }\par
}
6 \cf0 0
143 {\fs17 0 }
147 {\fs17 0 }
172 {\b \f10 \fs15 1 }
\cf0 {\b\i \fs11 C}{\b\i \fs11 O }\par
}
Fig.{\b \f10 \fs15 8-2}{\fs17
Half}{\fs17 adder}{\fs17 truth}{\fs16 t
able }
1076 {\fs19 170 }\par
}
.{\b \fs17 81 }\par
}
NARY ARITHMETIC{\fs17 AND} ARITHMETIC CIRCUITS \par
}
\par
}
iven the{\i \fs19 summation}{\i \fs18 symbol}{\fs22 (E).} The carry-out outp
ut column is often just represented with the{\b\i \fs18 CO }
\par}{\phpg\posx869\pvpg\posy1324\absw9140\absh1310 \sl-237 \f20 \fs18 \cf0 symb
ol.
60 The truth table{\fs19 in} Fig. 8-2 is that{\fs18 of} a{\i \fs18 half}{\
i \fs18 adder} circuit.{\b A} block diagram for a half adder might
\par}{\phpg\posx869\pvpg\posy1324\absw9140\absh1310 \sl-237 \f20 \fs18 \cf0 be d
rawn as in Fig.{\i \fs18 8-3a.} Note the two inputs{\b\i \f10 \fs18 A} and
{\i \fs19 B} on the symbol in Fig.{\i \fs18 8-3a.} The outputs are
\par}{\phpg\posx869\pvpg\posy1324\absw9140\absh1310 \sl-236 \f20 \fs18 \cf0 Iabe
Ied{\fs21 C} (sum) and{\b\i \fs18 CO} (carry out). It is common to label
the half adder with{\b \fs19 HA} as shown on the
\par}{\phpg\posx869\pvpg\posy1324\absw9140\absh1310 \sl-237 \f20 \fs18 \cf0 bloc
k symbol. \par
}
0 ^---rr \par
}
8 \cf0 z
\cf0 \fi238 {\b\i \f30 \fs12 CO }

\fi1436 {\i \fs14 (h)}{\f20 \fs15 Logic}{\f20 \fs15 diagram }
{\b \f20 \fs16 Fig.}{\b \f20 \fs16 8-3}{\f20 \fs17
Half}{\f20 \fs16 adder
}\par
}
15 \cf0 B \par
}
a){\b \f30 \fs16 Block} symbol \par
}
\cf0 Looking at the sum{\fs21 (C)} output column of the truth table in Fig
. 8-2, note that it takes an{\fs18 XOR }
tion to produce the{\fs21 C} output. The carry-out column will use an AND func
tion. A complete logic
uit for the half adder with two inputs{\b\i \f10 \fs17 (}{\b\i \f10 \fs17 A} a
nd{\i \fs19 B}{\i \fs19 )} and two outputs{\fs20 (C} and{\b\i \fs18 CO)}is
shown{\fs18 in} Fig.{\i \fs18 8-3b. }
\par}{\phpg\posx853\pvpg\posy5651\absw9132\absh2758 \sl-232 \f20 \fs18 \cf0 Comp
osed only of gates{\fs18 (XOR} and{\b \fs18 AND),} the half adder is classifie
d as a combinational logic circuit.
65 Consider the binary addition problem in Fig.{\i \fs18 8-4a.} The{\fs19 Is}
column is 1{\f10 \fs26 +}{\fs19 I,} and it follows rule{\i \fs18 4} in
{\i \fs18 8-1.} The sum is{\fs19 0} with a carry of 1 to the{\fs18 2s} column
. The 2s column must now be added. In the{\fs19 2s }
mn we have{\fs18 1}{\f10 \fs28 +} 1{\f10 \fs27 +} 1. This is a new situa
tion. It equals binary 11 (decimal{\fs18 3).} The 1 is placed
\par}{\phpg\posx853\pvpg\posy5651\absw9132\absh2758 \sl-244 \f20 \fs18 \cf0 belo
w the{\fs18 2s} column in the sum position.{\b A} 1is carried to the{\i \fs18
4s} column.{\fs18 The} single 1 at the top of the
\fs19 4s} column is added to the{\b \fs18 OS} with a result of 1, which is
written in the{\fs18 sum} position. The result is a
\par}{\phpg\posx853\pvpg\posy5651\absw9132\absh2758 \sl-246 \f20 \fs18 \cf0 sum
of{\fs18 110. }
\fi1702 {\fs17 carry}{\fs17
carry }\par
}
\par
}
s15 \cf0 A + B +{\b0\i0 \f20 \fs16 Carry }\par
}
\fs24 +}{\dn006 \fs16 1}{\fs25 + }\par
}
m \par
}
{\phpg\posx8437\pvpg\posy9179\absw464\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Ca
rry \par
}
{\phpg\posx8527\pvpg\posy9183\absw274\absh188
t \par
}
\par
}
cf0 Rule{\i \f10 \fs16 5 }\par
}
\f20 \fs16 \cf0 \f20 \fs16 \cf0 ou

\f10 \fs50 \cf0 \f10 \fs50 \cf0 I
\b \f20 \fs17 \cf0 \b \f20 \fs17 \
\f20 \fs17 \cf0 \f20 \fs17 \cf0 in

fi26 {\f10 \fs15 1 }\par
}
\par
}
{\fs16
and}{\fs17 carry}{\fs16 1}{\f10 \fs14 =}{\fs16 11 }\par
}
s11 \cf0 (U){\b0\i0 \f20 \fs15 Simple}{\b0\i0 \f20 \fs15 binary}{\b0\i0 \f20 \
fs15 addition}{\b0\i0 \f20 \fs15 problem }\par
}
b){\fs15 Additional}{\fs15 binary}{\fs15 addition}{\fs15 rule }\par
}
20 \fs16 \cf0 Fig. 8-4
cf0 \fi370 {\b0 \fs18 Rule}{\b0\i \fs19 5}{\b0 \fs18 for}{\b0 \fs18 binary}{\
b0 \fs18 addition}{\b0 \fs18 is}{\b0 \fs18 formally}{\b0 \fs18 written}{\b0
\fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 8-4h.}{\b0 \fs18 Note}{\b0 \fs18 the
}{\b0 \fs18 three}{\b0 \fs18 inputs}{\i \f10 \fs18 (}{\i \f10 \fs18 A}{\i \f
10 \fs18 ,}{\b0\i \fs19 B,}{\b0 \fs18 and}{\b0 \fs18 carry }
{\b0 \fs18 in).}{\b0 \fs18 The}{\b0 \fs18 outputs}{\b0 \fs18 are}{\b0 \fs18
the}{\b0 \fs18 usual}{\b0 \fs18 sum}{\b0 \fs18 and}{\b0 \fs18 carry}{\b0 \fs
18 out.}{\b0 \fs18 Rule}{\b0\i \fs19 5}{\b0 \fs18 suggests}{\b0 \fs18 that}
{\b0 \fs18 a}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 will}{\b0\i \fs18
not}{\b0 \fs18 work}{\b0 \fs18 if}{\b0 \fs18 a }
{\b0\i \fs18 carry-in}{\b0 \fs18 situation}{\b0 \fs18 arises.}{\b0 \fs18 Ha
lf}{\b0 \fs18 adders}{\b0 \fs18 will}{\b0 \fs18 add}{\b0 \fs18 only}{\b0 \f
s18 two}{\b0 \fs18 inputs}{\i \f10 \fs17 (}{\i \f10 \fs17 A}{\b0 \fs18 and
}{\i \fs18 B),}{\b0 \fs18 as}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 Is}{
\b0 \fs18 column}{\b0 \fs18 of}{\b0 \fs18 an }
{\b0 \fs18 addition}{\b0 \fs18 problem.}{\b0 \fs18 When}{\b0 \fs18 the}{\b0
\fs19 2s}{\b0 \fs18 column}{\b0 \fs18 or}{\b0 \fs18 the}{\b0\i \fs18 4s}{\
b0 \fs18 column}{\b0 \fs18 is}{\b0 \fs18 added,}{\b0 \fs18 a}{\b0 \fs18 ne
w}{\b0 \fs18 circuit}{\b0 \fs18 is}{\b0 \fs18 needed.}{\b0 \fs18 The}{\b0
\fs18 new }
{\b0 \fs18 circuit}{\b0 \fs18 is}{\b0 \fs18 called}{\b0 \fs18 a}{\i \f30 \fs
19 full}{\b0\i \fs18 adder.}{\fs18 A}{\b0 \fs18 block}{\b0 \fs18 diagram}{\
b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 is}{\
b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \f10 \fs17 8-5a. }
\fi360 {\b0 \fs18 The}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 circuit}{\b
0 \fs18 has}{\b0 \fs18 three}{\b0 \fs18 inputs}{\b0 \fs18 which}{\b0 \fs18

are}{\b0 \fs18 added.}{\b0 \fs18 The}{\b0 \fs18 inputs}{\b0 \fs18 shown}{\b0
\fs18 in}{\b0 \fs18 the}{\b0 \fs18 block}{\b0 \fs18 diagram}{\b0 \fs18 in
}
{\b0 \fs18 Fig.}{\b0\i \fs18 8-5}{\b0 \fs18 are}{\i \fs18 A}{\i \fs18 ,}{\b0
\i \fs19 B,}{\b0 \fs18 and}{\b0\i \fs18 Cin}{\b0 \fs18 (carry}{\b0 \fs18 i
n).}{\b0 \fs18 The}{\b0 \fs18 outputs}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \f
s18 full}{\b0 \fs18 adder}{\b0 \fs18 are}{\b0 \fs18 the}{\b0 \fs18 customar
y}{\b0 \fs21 C}{\b0 \fs18 (sum)}{\b0 \fs18 and }
{\i \fs18 CO}{\b0 \fs18 (carry}{\b0 \fs18 out).}{\b0 \fs18 Note}{\b0 \fs18 th
e}{\b0 \fs18 use}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 letters}{\b0 \fs18
FA}{\b0 \fs18 to}{\b0 \fs18 symbolize}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0
\fs18 in}{\b0 \fs18 the}{\b0 \fs18 block}{\b0 \fs18 diagram.}{\b0 \fs18 To
}{\b0 \fs18 repeat, }
{\b0 \fs18 the}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 is}{\b0 \fs18 use
d}{\b0 \fs18 in}{\b0 \fs18 only}{\b0 \fs18 the}{\b0 \fs18 Is}{\b0 \fs18 pla
ce}{\b0 \fs18 when}{\b0 \fs18 larger}{\b0 \fs18 binary}{\b0 \fs18 numbers}{\
b0 \fs18 are}{\b0 \fs18 added.}{\b0 \fs18 Full}{\b0 \fs18 adders}{\b0 \fs18
are}{\b0 \fs18 used }
{\b0 \fs18 for}{\b0 \fs18 adding}{\b0 \fs18 all}{\b0 \fs18 other}{\b0 \fs18
columns}{\b0 \fs18 (2s,}{\b0\i \fs18 4s,}{\b0 \fs18 8s,}{\b0 \fs18 and}{\b0\
i \fs19 so}{\b0 \fs18 forth). }
\fi356 {\fs19 A}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 circuit}{\b0 \fs1
8 can}{\b0 \fs18 be}{\b0 \fs18 constructed}{\b0 \fs18 from}{\b0 \fs18 half}
{\b0 \fs18 adders}{\b0 \fs18 and}{\b0 \fs18 an}{\b0 \fs19 OR}{\b0 \fs18 g
ate,}{\b0 \fs18 A}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 circuit}{\b0 \
fs18 is }
{\b0 \fs18 diagrammed}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 8-91.}{\b0 \
fs18 The}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 becomes}{\b0 \fs18 a}{
\b0 \fs18 basic}{\b0 \fs18 building}{\b0 \fs18 block}{\b0 \fs18 in}{\b0 \fs1
8 constructing}{\b0 \fs18 other}{\b0 \fs18 adders. }
{\fs18 A}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 for}{\b0 \fs18 the}{\b
0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 is}{\b0 \fs18 detailed}{\b0 \fs18
in}{\b0 \fs18 Fig.}{\b0 \f10 \fs17 8-5c. }\par
}
\par
}
}
AP. 8 \par
}
14 \cf0 A \par
}
cf0 x \par
}
15 \cf0 Cin \par

}
cf0 HA \par
}
\cf0 \par}{\phpg\posx6580\pvpg\posy1917\absw621\absh662 \sl-382 \f10 \fs27 \cf0 - \pa
r
}
15 \cf0 B \par
}
\par
}
11 \cf0 CO \par
}
cf0 x
\f10 \fs27 - }\par
}
16 \cf0 CO \par
}
14 \cf0 A \par
}
14 \cf0 A \par
}
{\phpg\posx924\pvpg\posy2737\absw736\absh447 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Inp
uts{\b\i \f10 \fs14
A }
{\fs15 B }\par
}
tputs \par
}
cf0 HA \par
}
15 \cf0 B \par
}
15 \cf0 B \par
}
15 \cf0 CO \par
}
15 \cf0 CO \par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 Block}{\b0\i0 \f20 \fs15 symbol }\par
}
b){\fs15 Wired}{\fs15 from}{\fs15 half}{\fs15 adders}{\fs15 and}{\fs15

OR}{\fs15 gate }\par
}
\fs12 \cf0 (c){\b0 \f20 \fs15 Truth}{\b0 \f20 \fs15 table }
f0 {\f20 \fs16 Fig.}{\f20 \fs17 8-5}{\b0 \f20 \fs17
Full}{\b0 \f20 \fs17
adder }\par
}
cf0 SOLVED PROBLEMS
0 {\fs17 8.1}{\b0 \f20 \fs19
Solve}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 f
ollowing}{\b0 \f20 \fs19 binary}{\b0 \f20 \fs19 addition}{\b0 \f20 \fs19 prob
lems: }\par
}
19 \cf0 (a) \par
}
cf0 100
\fs28 +}{\dn006 \fs19 11 }\par
}
19 \cf0 ( b ) \par
}
cf0 1010
\fs29 +}110 \par
}
19 \cf0 ( c ) \par
}
cf0 1001
\fs30 +} 101 \par
}
\cf0 Solution:
\fi368 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Figs.}{\b0 \fs17 8-1}{\b0 \
fs17 and}{\b0 \fs17 8-2.}{\b0 \fs17 The}{\b0 \fs17 sums}{\b0 \fs17 in}{\b0
\fs17 the}{\b0 \fs17 problems}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \fs17 f
ollows: }
{\i \f10 \fs15 (a)}{\b0 \fs17
111,}{\i \fs17
(b)}{\b0 \fs17
10000
,}{\i \fs16
(c)}{\b0 \fs17
1110. }\par
}
cf0 8.2 \par
}
Find the binary sums in,the following problems: \par
}
s19 \cf0 (a) \par
}

110
3 {\f10 \fs30 +}{\dn006 11 }\par
}
s19 \cf0 (b) \par
}
\cf0 1011
0 \fs29 +}{\fs18 111 }\par
}
\cf0 (c) \par
}
\cf0 1111
0 \fs29 +}{\fs18 111 }\par
}
\cf0 Solution:
\fi364 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Figs.}{\b0 \fs17 8-1}{\b0 \
fs17 and}{\b0 \fs17 8-2.}{\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 sums}{
\b0 \fs17 in}{\b0 \fs17 the}{\b0 \fs17 problems}{\b0 \fs17 are}{\b0 \fs17
as}{\b0 \fs17 follows: }
{\i \f10 \fs15 (a)}{\b0 \fs17
10001,}{\i \fs17
(b)}{\b0 \fs17
10
010,}{\i \f10 \fs14
(}{\i \f10 \fs14 c}{\i \f10 \fs14 )}{\b0 \fs17
10110. }\par
}
\cf0 CHAP.{\b0\i0 \f10 \fs16 81 }\par
}
}
f0 173 \par
}
f0 8.3 \par
}
half adder circuit has
}
nput(s) and \par
}
tput(s). \par
}
half adder circuit has 2 inputs and 2 outputs. \par
}
\cf0 A{\b0 \fs19 full}{\b0 \fs19 adder}{\b0 \fs19 circuit}{\b0 \fs19 has }
}
nput($ and \par
}
f0 8.4 \par
}
tput(s). \par
}
f0 8.5 \par
}
f0 8.6 \par
}
f0 8.7 \par
}
7 \cf0 A full adder circuit has{\b \fs17 3} inputs and 2 outputs.
{\fs19 Draw}{\fs19 a}{\fs19 block}{\fs19 diagram}{\fs19 of}{\fs19 a}{\fs19
half}{\fs19 adder}{\fs19 and}{\fs19 label}{\fs19 the}{\fs19 inputs}{\fs19
and}{\fs19 outputs. }
Solution: }
361 See Fig.{\i \f10 \fs15 8-3u. }
{\fs19 Draw}{\fs19 a}{\fs19 block}{\fs19 diagram}{\fs19 of}{\fs19 a}{\fs19
full}{\fs19 adder}{\fs19 and}{\fs19 label}{\fs19 the}{\fs19 inputs}{\fs19
and}{\fs19 outputs. }
Solution: }
367 See Fig.{\fs17 8-52. }
{\fs19 A}{\fs19 half}{\fs19 adder}{\fs19 circuit}{\fs19 is}{\fs19 construc
ted}{\fs19 from}{\fs19 what}{\i \fs20 two}{\fs19 logic}{\fs19 gates? }
Soiution: }
361 {\b \f10 \fs15 A} half adder circuit is constructed from a 2-input{\b
\fs17 XOR} gate and a 2-input{\fs17 AND} gate. \par
}
full adder circuit can be constructed{\b \fs18 by} using two
\par}{\phpg\posx1499\pvpg\posy7264\absw4600\absh730 \sl-240 \f20 \fs19 \cf0 (AND
,{\fs19 OR)} gate.
}
\cf0 (FAs,{\b0 \fs19 HAS)}{\b0 \fs19 and}{\b0 \fs19 a}{\b0 \fs19 2-input }\p
ar
}
f0 8.8 \par
}
\cf0 A{\b0 \f20 \fs17 full}{\b0 \f20 \fs17 adder}{\b0 \f20 \fs17 circuit}{\b
0 \f20 \fs17 can}{\b0 \f20 \fs17 be}{\b0 \f20 \fs17 constructed}{\b0 \f20 \
fs17 by}{\b0 \f20 \fs17 using}{\b0 \f20 \fs17 two}{\f20 \fs17 HAS}{\b0 \f2
0 \fs17 and}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 2-input}{\b0 \f20 \fs17 OR}
{\b0 \f20 \fs17 gate. }\par
}
s17 \cf0 An{\b0\i0 \f20 \fs19 HA}{\b0\i0 \f20 \fs19 circuit}{\b0\i0 \f20 \fs
19 is}{\b0\i0 \f20 \fs19 used}{\b0\i0 \f20 \fs19 to}{\b0\i0 \f20 \fs19 a
dd}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 bits}{\b0\i0 \f20 \fs19 in}{\
b0\i0 \f20 \fs19 the }
{\b0\i0 \f20 \fs19 problem. }
\cf0 {\i0 \f20 \fs17 Solution: }
\fi358 {\b0\i0 \f20 \fs17 An}{\b0\i0 \f20 \fs17 HA}{\b0\i0 \f20 \fs17 adds}{
\b0\i0 \f20 \fs17 the}{\i0 \f20 \fs17 1s}{\b0\i0 \f20 \fs17 column}{\b0\i0
\f20 \fs17 in}{\b0\i0 \f20 \fs17 a}{\b0\i0 \f20 \fs17 binary}{\b0\i0 \f20
\fs17 addition}{\b0\i0 \f20 \fs17 problem. }\par
}
Is, 2s) column of{\b a} binary addition \par
}
f0 8.9 \par
}
cf0 8.10 \par
}
Draw the logic diagram of a{\fs19 full} adder using AND,{\fs19 XOK,} and{\fs1
9 OR} gates.
\fs17 Solution: }
356 {\fs17 See}{\b \fs16 Fig.}{\b \fs17 8-6. }\par
}
\cf0 Fig.{\fs16 8-6}{\b0
Logic}{\b0 diagram}{\b0 of}{\b0 a}{\b0 full
}{\b0 adder }\par
}
0 174 \par
}
NARY ARITHMETIC AND ARITHMETIC CIRCUITS \par
}
AP. 8 \par
}
cf0 8.11{\b0
List}{\b0 the}{\fs19 HA}{\b0\i \fs19 sum}{\b0 outputs}{\b
0 for}{\b0 each}{\b0 set}{\b0 \fs18 of}{\b0 input}{\b0 pulses}{\b0 shown
}{\b0 in}{\b0 Fig.}{\b0 \fs19 8-7. }\par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\fs16 8-7}{\b0 \fs17
Half}{\b0 \fs17 adder}{\b0 \fs17 pulse-tr
ain}{\b0 \fs17 problem }\par
}
\cf0 Solution:
fi351 {\b0 \fs17 Based}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 truth}{\b0
\fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 8-2,}{\b0 \fs17 the
}{\b0 sum}{\b0 \fs17 outputs}{\b0 \fs17 from}{\b0 \fs17 the}{\b0 \fs17
half}{\b0 \fs17 adder}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs16 8-7}{\b0 \
fs17 are}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
lse{\b\i \f10 \fs14 a}{\f10 \fs13 =}{\b \fs17 1 }
{\i \fs16 b}{\f10 \fs13 =} 0 \par
}
lse{\i \f10 \fs14 c}{\f10 \fs13 =} 0
{\fs17 d}{\f10 \fs13 =} 0 \par
}
lse{\b\i \fs16 e}{\dn006 \f10 \fs11 =}{\fs16 0 }
{\i \f30 \fs19 f=}{\fs17 1 }\par
}
cf0 8.12{\b0 \f20 \fs18
List}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 half}{\b0
\f20 \fs18 adder}{\i \f20 \fs18 carry-out}{\b0 \f20 \fs18 outputs}{\b0 \f2
0 \fs18 for}{\b0 \f20 \fs18 each}{\b0 \f20 \fs18 set}{\b0 \f20 \fs18 of}{\b0
\f20 \fs18 input}{\b0 \f20 \fs18 pulses}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs
18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs19 8-7. }
i957 {\b0 \f20 \fs17 Based}{\b0 \f20 \fs17 on}{\b0 \f20 \fs17 the}{\b0 \f20
\fs17 truth}{\b0 \f20 \fs17 table}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 Fig
.}{\b0 \f20 \fs17 8-2}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 carry-out}{\b0 \f
20 \fs17 outputs}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
half}{\b0 \f20 \fs17 adder}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 Fig.}{\b0
\f20 \fs16 8-7}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17 as }
i593 {\b0 \f20 \fs17 follows: }\par
}
lse{\b\i \f10 \fs14 a}{\f10 \fs13 =} 0
{\i \fs16 b}{\dn006 \f10 \fs11 =} 0 \par
}
lse{\b\i \fs17 c}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\b\i \fs17 d}{\f10 \fs13 =}{\fs16 0 }\par
}
lse{\i \f10 \fs16 e}{\f10 \fs13 =}{\fs17 1 }
{\i \f30 \fs19 f=} 0 \par
}
cf0 8.13{\b0 \fs18
List}{\b0 \fs18 the}{\b0 \fs18 full}{\b0 \fs18 adder}{
\b0\i \fs19 sum}{\b0 \fs18 outputs}{\b0 \fs19 for}{\b0 \fs18 each}{\b0 \fs1
8 set}{\b0 of}{\b0 \fs18 input}{\b0 \fs18 pulses}{\b0 \fs18 shown}{\b0 \fs
18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-8. }\par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig. 8-8{\b0 \fs17
Full}{\b0 \fs17 adder}{\b0 \fs17 pulse-train}{\b0
\fs17 problem }\par
}
\cf0 Solution:
\fi355 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Figs.}{\b0 \fs17 8-1}{\b0
\fs17 and}{\b0 \fs16 8-4b.}{\b0 \fs17 The}{\b0 \fs17 sum}{\b0 \fs17 output
s}{\b0 \fs17 from}{\b0 \fs17 the}{\b0 \fs17 FA}{\b0 \fs17 shown}{\b0 \fs1
7 in}{\b0 \fs17 Fig.}{\b0 \fs16 8-8}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \f
s17 follows: }\par
}
ulse{\b\i \f10 \fs15 a}{\dn006 \f10 \fs11 =} 0
e{\i b}{\dn006 \f10 \fs11 =} 0 \par
}
ulse{\b\i \fs16 c}{\dn006 \f10 \fs11 =}{\fs17 1 }
e{\fs17 d}{\f10 \fs13 =}{\b \fs17 1 }\par
}
ulse{\b\i \fs16 e}{\f10 \fs13 =}{\fs16 0 }
e{\fs17 f}{\fs17 =}{\fs16 0 }\par
}
ulse{\b\i \fs15 g}{\f10 \fs13 =}{\fs16 1 }
e{\i \fs16 h}{\f10 \fs13 =}{\fs16 1 }\par
}
cf0 8.14 \par
}
List the{\b\i \fs19 FA}{\b\i carry-out} outputs for each set{\fs18 of} input
pulses shown in Fig. 8-8.
\fs17 Solution: }
357 {\fs17 Refer}{\fs17 to}{\fs17 Figs.}{\fs17 8-1}{\fs17 and}{\b \fs17
8-4b.}{\fs17 The}{\b\i \fs17 CO}{\fs17 outputs}{\fs17 from}{\fs17 the}
{\fs17 full}{\fs17 adder}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs16 8
-8}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
ulse{\b\i \f10 \fs14 a}{\f10 \fs13 =}{\b \fs17 1 }
e{\i b}{\f10 \fs13 =}{\fs17 0 }\par
}
ulse{\b\i \fs16 c}{\dn006 \f10 \fs11 =} 0
e{\fs17 d}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}
ulse{\b\i \fs16 e}{\dn006 \f10 \fs11 =}{\fs16 1 }
}
ulse{\i \fs16 g}{\dn006 \f10 \fs11 =}{\fs16 0 }
e{\i h}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
.{\fs16 81 }\par
}
}
\par
}
\cf0 8-3{\fs18
BINARY}{\fs18 SUBTRACTION }
fi367 {\b0 \fs18 Half}{\b0 \fs18 subtractors}{\b0 \fs18 and}{\b0 \fs18 ful
l}{\b0 \fs18 subtractors}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 explaine
d}{\b0 \fs18 in}{\b0 \fs18 this}{\b0 \fs18 section.}{\b0 \fs18 The}{\b0
\fs18 rules}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 binary }
\b0 \fs18 subtraction}{\b0 \fs18 of}{\b0 \fs18 two}{\b0 \fs18 bits}{\b0 \fs
18 are}{\b0 \fs18 given}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-9.}{\b0
\fs18 The}{\b0 \fs18 top}{\b0 \fs18 number}{\b0 \fs18 in}{\b0 \fs18 a}{\
b0 \fs18 subtraction}{\b0 \fs18 problem}{\b0 \fs18 is}{\b0 \fs18 called}{\
b0 \fs18 the }
\b0\i \fs19 rninuend.}{\b0 \fs18 The}{\b0 \fs18 bottom}{\b0 \fs18 number}{\b
0 \fs18 is}{\b0 \fs18 called}{\b0 \fs18 the}{\b0\i \fs19 subtrahend,}{\b0 \f
s18 and}{\b0 \fs18 the}{\b0 \fs18 answer}{\b0 \fs18 is}{\b0 \fs18 called}{\
b0 \fs18 the}{\b0\i \fs19 difference.}{\b0 \fs18 Rule}{\b0 \fs18 1 }
\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-9}{\b0 \fs18 is}{\b0 \fs18 obvious
.}{\b0 \fs18 Rule}{\b0 \fs19 2}{\b0 \fs18 (Fig.}{\b0 \fs18 8-9)}{\b0 \fs18
concerns}{\b0 \fs18 1}{\b0 \fs18 being}{\b0 \fs18 subtracted}{\b0 \fs18 from}
{\b0 \fs18 the}{\b0 \fs18 smaller}{\b0 \fs18 number}{\b0 \fs18 0.}{\b0 \fs18
In}{\b0 \fs18 Fig. }
\b0 \fs18 8-10,}{\b0 \fs18 note}{\b0 \fs18 that,}{\b0 \fs18 in}{\b0 \fs18 th
e}{\b0 \fs18 1s}{\b0 \fs18 column}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 b
inary}{\b0 \fs18 number,}{\b0 \fs18 1}{\b0 \fs18 is}{\b0 \fs18 subtracted}{
\b0 \fs18 from}{\b0 \fs18 0.}{\fs18 A}{\b0 \fs18 1must}{\b0 \fs18 be}{\b0
\fs18 borrowed }
\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs19 2s}{\b0 \fs18 col
umn,}{\b0 \fs18 leaving}{\b0 \fs18 a}{\b0 \fs18 0}{\b0 \fs18 in}{\b0 \fs18
that}{\b0 \fs18 column.}{\b0 \fs18 Now}{\b0 \fs18 the}{\b0 \fs18 subtrahend
}{\b0 \fs19 1}{\b0 \fs18 is}{\b0 \fs18 subtracted}{\b0 \fs18 from}{\b0 \fs1
8 the }
\b0 \fs18 minuend}{\b0 \fs18 10(decimal}{\b0 \fs19 2).}{\b0 \fs18 This}{\b0
\fs18 leaves}{\b0 \fs18 a}{\b0 \fs18 difference}{\b0 \fs18 of}{\b0 \fs18 1}
{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 1s}{\b0 \fs18 column.}{\b0 \fs18 Th
e}{\b0 \fs18 binary}{\b0 \fs18 2s}{\b0 \fs18 column}{\b0 \fs18 uses}{\b0 \fs
18 rule }
fi27 {\b0 \fs19 1}{\b0 \fs18 (0}{\b0 \f10 \fs15 -}{\b0 \fs19 0)}{\b0 \fs18 a
nd}{\b0 \fs18 is}{\b0 \fs18 equal}{\b0 \fs18 to}{\b0 \fs18 0.}{\b0 \fs18
Therefore,}{\b0 \fs18 rule}{\b0 \fs19 2}{\b0 \fs18 is}{\b0 \fs18 0}{\b0 \f
10 \fs15 -}{\b0 \fs18 1}{\b0\dn006 \f10 \fs13 =}{\b0 \fs18 1}{\b0 \fs18 with
}{\b0 \fs19 a}{\b0 \fs18 borrow}{\b0 \fs18 of}{\b0 \fs19 1.}{\b0 \fs18 R
ules}{\b0 \fs19 3}{\b0 \fs18 and}{\fs19 4}{\b0 \fs18 are}{\b0 \fs18 also }

\b0 \fs18 rather}{\b0 \fs18 obvious. }\par
}
{\phpg\posx2411\pvpg\posy4373\absw541\absh786 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Ru
le{\fs17 1 }
\par}{\phpg\posx2411\pvpg\posy4373\absw541\absh786 \sl-220 \f20 \fs17 \cf0 Rule{
\fs17 2 }
3
\par}{\phpg\posx2411\pvpg\posy4373\absw541\absh786 \sl-214 \f20 \fs17 \cf0 Rule{
\b \f10 \fs16 4 }\par
}
{\phpg\posx3103\pvpg\posy4173\absw714\absh967 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Mi
nuend
2 {\fs17 0 }
2 0
4 {\fs17 1 }
4 {\fs17 1 }\par
}
{\phpg\posx4023\pvpg\posy4383\absw140\absh739 \f10 \fs15 \cf0 \f10 \fs15 \cf0 \par}{\phpg\posx4023\pvpg\posy4383\absw140\absh739 \sl-220 \f10 \fs15 \cf0 \par}{\phpg\posx4023\pvpg\posy4383\absw140\absh739 \sl-223 \f10 \fs15 \cf0 {\fs1
9 - }
\par}{\phpg\posx4023\pvpg\posy4383\absw140\absh739 \sl-176 \f10 \fs15 \cf0 - \pa
r
}
{\phpg\posx4353\pvpg\posy4173\absw891\absh967 \f20 \fs17 \cf0 \f20 \fs17 \cf0 Su
btrahend
2 0
4 {\fs17 1 }
6 0
7 {\fs17 1 }\par
}
{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \f10 \fs19 \cf0 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-196 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-243 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-155 \f10 \fs19 \cf0 {\fs1
5 - }
\par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-224 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-196 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-196 \f10 \fs19 \cf0 \par}{\phpg\posx5457\pvpg\posy4293\absw146\absh865 \sl-196 \f10 \fs19 \cf0 - \pa
r
}
fference
4 0
6 {\fs16 1 }
6 {\b \f10 \fs15 1 }

6 0 \par
}
\cf0 Borrow out
and borrow{\fs17 1 }\par
}
\cf0 Fig.{\fs16 8-9}{\b0
Rules}{\b0 For}{\b0 binary}{\b0 subtraction }\
par
}
nuend
\par}{\phpg\posx3787\pvpg\posy6703\absw891\absh624 \sl-224 \f20 \fs17 \cf0 Subtr
ahend
\par}{\phpg\posx3787\pvpg\posy6703\absw891\absh624 \sl-256 \f20 \fs17 \cf0 Diffe
rence \par
}
{\phpg\posx5131\pvpg\posy6415\absw646\absh448 \f20 \fs17 \cf0 \f20 \fs17 \cf0 bo
rrow
{\fs15 /io-'lo }\par
}
{\phpg\posx5075\pvpg\posy6927\absw290\absh423 \f20 \fs17 \cf0 \f20 \fs17 \cf0 -0
0 {\fs17 0 }\par
}
r
}
}
\cf0 2
\fs12 --}{\fs17
1 }\par
}
\par
}
0 \fs17 \cf0 Fig.{\fs16 8-10}{\b0
Binary}{\b0 subtraction}{\b0 problem}{\
b0 showing}{\b0 a}{\b0 borrow }
f0 \fi362 {\b0 \fs18 The}{\b0 \fs18 subtraction}{\b0 \fs18 rules}{\b0 \fs18
given}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-9}{\b0 \fs18 look}{\b0 \fs
18 somewhat}{\b0 \fs18 like}{\b0 \fs18 a}{\b0 \fs18 truth}{\b0 \fs18 tabl
e.}{\b0 \fs18 These}{\b0 \fs18 rules}{\b0 \fs18 have}{\b0 \fs18 been }
\b0 \fs18 reproduced}{\b0 \fs18 in}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0
\fs18 form}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-11.}{\b0 \fs18 Cons
ider}{\b0 \fs18 the}{\b0 \fs18 difference}{\b0\i \fs19 (Di)}{\b0 \fs18 out
put}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \fs18 table. }
\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 this}{\b0 \fs18 output}{\b0 \fs18
represents}{\b0 \fs18 the}{\b0 \fs18 XOR}{\b0 \fs18 function.}{\b0 \fs18 The
}{\b0 \fs18 logic}{\b0 \fs18 function}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs
18 difference}{\b0 \fs18 output}{\b0 \fs18 in}{\b0 \fs18 a }
\b0 \fs18 subtractor}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 same}{\b0 \fs1
8 as}{\b0 \fs18 that}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 sum}{\b0
\fs18 output}{\b0 \fs18 in}{\b0 \fs18 a}{\b0 \fs18 half}{\b0 \fs18 adde
r}{\b0 \fs18 circuit.}{\b0 \fs18 Now}{\b0 \fs18 consider}{\b0 \fs18 the}{\
b0 \fs18 borrow }
\i \fs19 (Bo)}{\b0 \fs18 column}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 truth
}{\b0 \fs18 table.}{\b0 \fs18 The}{\b0 \fs18 logic}{\b0 \fs18 function}{\b0
\fs18 for}{\b0 \fs18 this}{\b0 \fs18 column}{\b0 \fs18 can}{\b0 \fs18 be}{\
b0 \fs18 represented}{\b0 \fs18 by}{\b0 \fs18 the}{\b0 \fs18 Boolean }
\b0 \fs18 expression}{\b0\i \fs19 A}{\b0\i \fs19 .}{\b0\i \fs19 B}{\b0 \f10
\fs14 =}{\i \fs19 Y.}{\b0 \fs18 It}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18
implemented}{\b0 \fs18 by}{\b0 \fs18 using}{\b0 \fs18 an}{\b0 \fs18 inver
ter}{\b0 \fs18 and}{\b0 \fs18 a}{\b0 \fs18 2-input}{\fs18 AND}{\b0 \fs18 g
ate. }\par
}
puts \par
}
Minuend
268 {\b\i \f10 \fs15 A }
\fi280 {\fs17 0 }
282 0
308 {\b \f10 \fs16 1 }
308 {\b \f10 \fs15 1 }\par
}
Subtrahend
401 B
\fi415 0
437 {\b \f10 \fs16 1 }
417 {\b \f30 \fs17 0 }
439 {\b \f10 \fs16 1 }\par
}
\par
}
tputs \par
}
Difference
Borrow \par
}
\fs18 \cf0 0

\fi58 {\f10 \fs15 1 }
\fi64 {\f10 \fs15 1 }
\fi42 {\b0 \f20 \fs17 0 }
cf0 {\i \fs19 Di }\par
}
\cf0 0
66 {\b \f10 \fs15 1 }
47 0
47 0
{\b\i \fs16 Bo }\par
}
s16 \cf0 A - B \par
}
\par
}
0 \fs17 \cf0 Fig.{\fs16 8-11}{\b0
Half}{\b0 subtractor}{\b0 truth}{\b0
table }
f0 \fi351 {\b0 \fs18 The}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 in}{
\b0 \fs18 Fig.}{\b0 \fs18 8-11}{\b0 \fs18 represents}{\b0 \fs18 a}{\b0 \
fs18 logic}{\b0 \fs18 circuit}{\b0 \fs18 called}{\b0 \fs18 a}{\b0\i \fs1
9 half}{\i \fs18 subtractor.}{\b0 \fs18 The}{\b0 \fs18 Boolean }
\b0 \fs18 expression}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 difference}{
\b0 \fs18 output}{\b0 \fs18 is}{\i \fs19 A}{\b0 \f10 \fs15 @}{\i \fs19
B}{\b0 \f10 \fs14 =}{\b0\i \fs19 Di.}{\b0 \fs18 The}{\b0 \fs18 Boolean}{\b
0 \fs18 expression}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 borrow}{\b0\
i \fs19 (Bo) }\par
}
utput is{\b\i \f30 \fs37 x.}{\b\i\dn006 \fs19 B }\par
}
={\b\i \f20 \fs18 Bo.}{\b \f20 \fs18 A}{\f20 \fs18 half}{\f20 \fs18 subtract
or}{\f20 \fs18 would}{\f20 \fs18 be}{\f20 \fs18 wired}{\f20 \fs18 from}{\f20
\fs18 logic}{\f20 \fs18 gates}{\f20 \fs18 as}{\f20 \fs18 shown}{\f20 \fs18
in}{\f20 \fs18 Fig.}{\f20 \fs18 8-12a.}{\f20 \fs18 Input }\par
}
\par
}
pi:\\ \par
}
17 \cf0 A{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 m
inucnd}{\i0 \f20 \fs19 and}{\f20 \fs19 /}{\f20 \fs19 I }\par

}
s the suhtrahcnd. The{\b\i \f10 \fs17
/}{\b\i \f10 \fs17 A} output{\fs1
6
is} the ditlcrci1cc;{\b \fs17
/I0}{\fs16
is} thc horro\\\\.{\f10
\fs16 ..\\ }\par
}
{\phpg\posx875\pvpg\posy3831\absw2699\absh217 \f20 \fs18 \cf0 \f20 \fs18 \cf0 si
mpliticd{\b \fs18 hltxck} di;igr;im for{\b\dn006 \fs11
;I }\par
}
alf suhtr;rctor is{\fs18 in} Fig.{\b \f10 \fs17 S-12h. }\par
}
\cf0 in{\fs18 1:ip. }
8 difkrcncc}{\fs18 in}{\fs18 the}{\fs18 logic}{\fs18 circuits}{\fs17 i
s}{\fs18 that}{\fs18 the}{\fs18 half}{\fs18 suhtractcrr}{\dn006 \fs12
hiis }
f10 \fs18 AND}{\b \f10 \fs16 giltc. }\par
}
ompi~rct{\b \fs18 hc} half whtr;~ctorlogic ~li;~gr;~r~i{\b \f30 S-}{\b\i 12t
r}{\fs13
\\\\it11}{\b \fs14 tlic.}{\b \fs19 hdi}{\b \f10 \fs16 ;idcler}{
\dn006 \fs12
111 }\par
}
ig.{\b \f30 \fs18 S-.%.}{\fs17 'I'hc}{\b \fs16 wily }\par
}
11c{\b \f10 \fs16 aJdc11} invcrtcr{\b \f10 \fs14 at}{\b \fs17 the}{\b \fs18
.,I }\par
}
nput{\b \f10 \fs15 ot} the \par
}
onsider the suhtr;~ctionprohlcm in k'ig.{\b \f30 S-}{\f10 \fs17 13.}{\b Sc
\\er;11}{\b \fs17 horrous} ;1rc-{\fs15 c*.vitlc-nt}{\dn006 \fs11 iii }\par
}
hi\\{\b \fs15 protdciii.}{\b \f10 \fs17 If}{\b \f10 \fs18 \\}{\b \f10 \fs18
i}{\b \f10 \fs18 i }\par
}
htractor circuits{\b
arc} u\\cd{\fs18
for} the{\fs16
six}{\fs17
hinan}{\b \fs17
place\\.}{\fs18 the}{\fs19 txwotv\\} niwt{\f10 \fs17
he} con\\idcrcd.{\f10 \fs17
.A} halt
\par}{\phpg\posx875\pvpg\posy5016\absw9310\absh649 \sl-250 \f20 \fs18 \cf0 suhtr
actor may he uscd tor thc{\b \f30 \fs16 Is}{\b pl;rcc.}{\fs18 F'ull} \\
iihtr;~ctc~rsmust{\fs17 he} i~\\cd{\fs18 in}{\b \f30 \fs18 the}{\b\i \fs16
2s.}{\b \f30 4s.}{\b \f30 \fs17 Ss.}{\b \fs17 I}{\b \fs17 h}{\b \fs17 .
} and{\b\i \fs19 3}{\b\i \fs19 3 }
\par}{\phpg\posx875\pvpg\posy5016\absw9310\absh649 \sl-233 \f20 \fs18 \cf0 colum
ns{\b \fs18 of}{\fs18 this} prohlcm. \par
}
\cf0 A{\f20 \fs19 bltxck}{\b0 \f20 \fs18
diagram}{\b0 \f20 \fs18 of}{\dn0
06 \f20 \fs13
;I }\par
}
ull{\fs18
suhtractor}{\b \f10 \fs18 (1:s)}{\b i.; }\par
}
n{\fs18
1;ig.}{\b \f30 S-}{\b \fs18 l4u.}{\fs18
The}{\fs18
input\\}{\f
s18
;1rc}{\b \f30 \fs19 .4}{\fs18 (minucnd).}{\b\i \fs18 /}{\b\i \fs18
I }\par
}
uhtr:~hcnd).and{\b\i \fs17
Hiri} (horroh input). 'l'hc outputs ;1rc{\b\i
\f10 \fs16 11;} (ditlcrcncc){\b \fs17 ;ind}{\b
/Io}{\dn006 \f10 \fs12 [
} borron output{\dn006 \f10 \fs11 ). }
\fs18 Bo} and{\b\i \f10 \fs17
HUi} lincs arc conncctcd from suhtr;tct
or{\b \f10 \fs15 to} suhtractor{\b \f10 \fs15 to}{\b kccp}{\b track}{\f
s17 o}{\fs17 f} the horrcm\\. \par
}
{\phpg\posx9395\pvpg\posy8208\absw331\absh203 \f20 \fs18 \cf0 \f20 \fs18 \cf0 'l
'hc \par
}
0 \fs11 \cf0 [ c ){\b\i0 \f20 \fs14 I.opc}{\b\i0 \fs13 diagram }
cf0 {\b\i0 \f20 \fs16 Fig.}{\b\i0 \fs15 8-14}{\b\i0 \f20 \fs17
Full}{\b\i0 \
f20 \fs16 subtractor }\par
}
0 CHAP.{\b0 \fs17 81 }\par
}
cf0 BINARY ARITHMETIC{\b0 \fs17 AND} ARITHMETIC CIRCUITS \par
}
\par
}
\cf0 The diagram in Fig.{\b \fs18 8-146} shows how to wire two half subtractor
s{\b \fs19 (HS)} and an{\fs19 OR} gate together
\par}{\phpg\posx855\pvpg\posy1358\absw9124\absh1512 \sl-234 \f20 \fs18 \cf0 to f
orm a full subtractor (FS) circuit. Note that the wiring pattern is similar t
o that used for adders.
\par}{\phpg\posx855\pvpg\posy1358\absw9124\absh1512 \sl-233 \f20 \fs18 \cf0 Fina
lly, Fig.{\f10 \fs17 8-14c} shows how gates could be wired to form a full s
ubtractor circuit. Remember that
\par}{\phpg\posx855\pvpg\posy1358\absw9124\absh1512 \sl-242 \f20 \fs18 \cf0 full
subtractors must be used to subtract all columns except the{\fs19 1s} column
in binary subtraction.
59 The truth table for the full subtractor is in Fig.{\fs19 8-15.} The
inputs are labeled as minuend{\b\i (A), }
\par}{\phpg\posx855\pvpg\posy1358\absw9124\absh1512 \sl-241 \f20 \fs18 \cf0 subt
rahend{\i \fs19 (B),}and borrow in{\i \fs19 (Bin).}The outputs are the custo
mary difference{\i \fs19 (Di)} and borrow out
\fs19 (Bo). }\par
}
0 i \par
}
cf0 Minuend
i229 {\b0 \f10 \fs22 (4 }\par
}
cf0 Line \par
}
\par
}
\fs17 \cf0 Inputs
0 Subtrahend
i335 {\i \fs17 (B) }\par
}
cf0 Borrow in
i206 {\b0\i \fs16 (Bin) }\par
}
\cf0 outputs
f0 \fi404 Borrow out \par
}
\cf0 Difference
f0 \fi340 {\b0 \fs16 0 }
fi360 {\b0 \f10 \fs15 1 }
fi365 {\b0 \f10 \fs15 1 }
fi343 {\b0 \f10 \fs15 0 }
fi366 {\f10 \fs15 1 }
fi340 {\b0 \fs17 0 }
fi343 {\b0 \fs16 0 }
fi368 {\b0 \f10 \fs15 1 }
f0 \fi303 {\i \f30 \fs18 Di }\par
}
s17 \cf0 (Bo)
\cf0 \fi166 {\b0\i0 \f10 \fs15 0 }
\fi188 {\b0\i0 \f10 \fs15 1 }
\fi187 {\b0\i0 \f10 \fs15 1 }
\fi187 {\b0\i0 \f10 \fs15 1 }

\fi166 {\i0 \f30 \fs17 0 }
\fi166 {\b0\i0 \fs16 0 }
\fi167 {\b0\i0 \fs17 0 }
\fi193 {\i0 \f10 \fs15 1 }
\cf0 \fi121 {\b0 \fs17 Bo }\par
}
15 \cf0 A{\b0\i0 \fs11
-}{\b0 \f20 \fs17 B }\par
}
\i \f20 \fs16 Bin }\par
}
\par
}
\cf0 Fig.{\fs16 8-15}{\fs17
Truth}{\fs17 table}{\b0 \fs16 for}{\fs17 th
e}{\fs17 full}{\fs17 subtractor }\par
}
\cf0 The binary subtraction problem{\fs19 in} Fig. 8-16 will aid under
standing of the full subtractor truth
e.{\i \fs18 Follow}{\i \fs19 as}{\i \fs18 this}{\i \fs18 problem}{\i \fs19
is}{\i \fs18 solved,}{\i \fs19 using}{\i \fs18 only}{\i \fs18 the}{\i \fs18
truth}{\i \fs18 tables}{\i \fs19 in}{\i \fs19 Figs.}{\i \fs19 8-11}{\i \fs
19 and}{\i \fs19 8-I5.}{\b \fs19 Look} at the{\fs19 Is }
mn of the problem in Fig.{\fs18 8-16.} The{\fs18 1s} place uses a half subtrac
tor. Find this situation in the truth
e in Fig. 8-11. You find that line{\b\i \fs18 3} of the half subtractor
truth table gives an output{\fs18 of}{\fs19 1} for{\i \fs19 Ri }
\par}{\phpg\posx859\pvpg\posy7582\absw9514\absh1072 \sl-244 \f20 \fs18 \cf0 (dif
ference) and{\i \fs18 0} for borrow out{\i \fs19 (Bo).}This is recorded below
the{\fs19 Is} column in Fig.{\b \fs18 8-16. }\par
}
f10 \fs14 \cf0 A
cf0 {\b0\i0\dn006 \fs11 ---}{\f20 \fs17 }{\f20 \fs17 B }\par
}
17 \cf0 DI \par
}
fs15 \cf0 64s
i202 {\f10 \fs15 1 }
b0 \fs16 -}{\b0 \fs16 0 }
i198 {\f10 \fs15 1 }\par
}

cf0 32s
i91 {\b0 \f10 \fs15 1 }
i71 {\b0 \f10 \fs15 0 }
i71 {\b0 \fs16 0 }\par
}
cf0 16s
i86 {\f10 \fs15 1 }
i83 {\b0 \f10 \fs15 1 }
i86 {\b0 \f10 \fs15 1 }\par
}
cf0 8s
b0 \f10 \fs16 0 }
f10 \fs15 1 }
i26 {\f10 \fs15 1 }\par
}
cf0 4s
i21 {\b0 \f10 \fs16 1 }
b0 \f10 \fs15 1 }
b0 \f10 \fs15 0 }\par
}
cf0 2s
b0 \fs17 0 }
b0 \f10 \fs15 0 }
b0 \f10 \fs15 0 }\par
}
fs10 \cf0 IS
i21 {\f10 \fs16 1 }
b0 \f10 \fs15 0 }
i26 {\f10 \fs15 1 }\par
}
\cf0 117
5 -}{\f20 \fs17
28 }
6 {\f20 \fs17 89 }\par
}
\cf0 Fig. 8-16{\fs17
Solving}{\b0 \fs16 a}{\fs17 binary}{\fs17 subtracti
on}{\fs17 probleni}{\fs17 using}{\fs17 truth}{\fs17 tables }\par
}
8 \cf0 Consider the{\fs18 2s} column in Fig. 8-16. The{\fs18 2s} column uses{\
fs18 a} full subtractor. On the full subtractor
\par}{\phpg\posx859\pvpg\posy12050\absw8953\absh1707 \sl-240 \f20 \fs18 \cf0 tru
th tabIe,{\b \fs19 look} for the situation where{\b\i \f10 \fs18 A}{\dn
006 \f10 \fs13 =}{\fs18 0,}{\i \fs19 B}{\f10 \fs14 =}{\i \fs18 0,} and{
\i \fs19
Bin}{\dn006 \f10 \fs13 =}{\fs18 0.} This is line 1 in Fig.{\
fs19 8-15. }
\par}{\phpg\posx859\pvpg\posy12050\absw8953\absh1707 \sl-231 \f20 \fs18 \cf0 Acc
ording to the truth table, both outputs{\i \fs19 (Di} and{\i \fs19 Bo)} are{\
fs18 0.} This is recorded below the{\fs18 2s} column in
. 8-16.
368 Next consider the 4s column in Fig. 8-16. The inputs to this full subtracto
r will be{\b\i A}{\dn006 \f10 \fs13 =}{\fs19 1,}{\b\i \fs19 B}{\f10 \fs13
=}{\fs18 1, }
{\i \fs19 Bin}{\f10 \fs7
=:}{\fs18 0.} Looking at the input side of the
truth table in Fig.{\fs18 8-15,} it appears that line{\b 7} shows this
\par}{\phpg\posx859\pvpg\posy12050\absw8953\absh1707 \sl-233 \f20 \fs18 \cf0 sit
uation. The outputs{\i \fs19 (Di} and{\i \fs19 Bo)} are both{\fs18 0} accord
ing to the: truth table and are written as such on
.{\fs18 8-16} under the{\fs18 4s} column. \par
}
\par
}
}
AP.{\fs17 8 }\par
}
f0 Bin{\i0\dn006 \f10 \fs13 = }\par
}
\cf0 Look{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 8s}{\b0 \fs18 column}{\b0
\fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-16.}{\b0 \fs18 The}{\b0 \fs18 inp
uts}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 full}{\b0 \fs18 subtractor}{\
b0 \fs18 will}{\b0 \fs18 be}{\i \f10 \fs17 A}{\b0\dn006 \f10 \fs13 = }\pa
r
}
{\phpg\posx8529\pvpg\posy1333\absw585\absh219 \f20 \fs18 \cf0 \f20 \fs18 \cf0 0,
{\i \fs19 B}{\dn006 \f10 \fs13 = }\par
}
and \par
}
.{\fs18 Line}{\fs19 3}{\fs18 of}{\fs18 the}{\fs18 truth}{\fs18 table}{\fs
18 (Fig.}{\fs18 8-15)}{\fs18 shows}{\fs18 this}{\fs18 situation.}{\fs18 T

he}{\fs18 outputs}{\i \fs19 (Di}{\fs18 and}{\i \fs19 Bo)}{\fs18 in}{\fs18
line}{\i 3 }\par
}
{\phpg\posx855\pvpg\posy1814\absw6143\absh479 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ar
e both 1s and are recorded in the{\fs18 8s} column in Fig. 8-16.
7 The 16s column in Fig. 8-16 has inputs of{\b\i A}{\dn006 \f10 \fs13 =} 1,{
\i \fs18 B}{\dn006 \f10 \fs13 =} 1, and{\i \fs19 Bin}{\dn006 \f10 \fs13 =
}\par
}
{\phpg\posx839\pvpg\posy2294\absw4705\absh427 \f20 \fs18 \cf0 \f20 \fs18 \cf0 in
the truth table. Line{\fs18 8} generates an output{\fs18 of}{\i \fs19 Di}{\
dn006 \f10 \fs13 = }
\par}{\phpg\posx839\pvpg\posy2294\absw4705\absh427 \sl-235 \f20 \fs18 \cf0 16s c
olumn in the problem. \par
}
he{\fs18 32s} column has inputs of{\b\i A}{\dn006 \f10 \fs13 =} 1,{\i \fs1
9 B}{\dn006 \f10 \fs13 = }\par
}
.This corresponds with line{\fs18 8 }\par
}
and{\i \fs19 Bo}{\f10 \fs14 =}{\fs18 1.}These 1s are recorded under the \p
ar
}
,{\fs18 and}{\i \fs19 Bin}{\f10 \fs14 =}{\fs18 1.}{\fs18 This}{\fs18 cor
responds}{\fs18 to}{\fs18 line}{\fs19 6}{\fs18 in}{\fs18 the}{\fs18 truth
}\par
}
{\phpg\posx839\pvpg\posy3006\absw4599\absh433 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ta
ble in Fig. 8-15. Line 6 generates outputs of{\i \fs19 Di}{\dn006 \f10 \fs1
3 = }
\par}{\phpg\posx839\pvpg\posy3006\absw4599\absh433 \sl-242 \f20 \fs18 \cf0 colum
n of the problem. \par
}
{\fs18 and}{\i \fs18 Bo}{\dn006 \f10 \fs13 = }\par
}
.{\fs18 These}{\fs18 0s}{\fs18 are}{\fs18 recorded}{\fs18 in}{\fs18 the}
{\fs18 32s }\par
}
inally consider the 64s column in Fig. 8-16. The inputs to the full subtractor
are{\b\i \fs18 A}{\dn006 \f10 \fs13 = }\par
}
{\i \fs18 B}{\dn006 \f10 \fs13 =}{\fs18 0, }\par
}
nd{\i \fs19 Bin}{\f10 \fs14 =}{\fs18 0.} This input combination is shown in
line 5 in the truth table. Line{\fs19 5} generates an output
\par}{\phpg\posx835\pvpg\posy3716\absw8996\absh1750 \sl-244 \f20 \fs18 \cf0 of{\
i \fs19 Di}{\dn006 \f10 \fs13 =} 1 and{\i \fs19 Bo}{\f10 \fs14 =}{\fs18
0.} Figure 8-16 illustrates how binary 11100 is subtracted from binary 1
110101

g truth tables. The borrows are shown below the problem. This procedure{\f
s18 is} quite cumbersome
humans, but electronic circuits can accurately perform this subtraction in mi
croseconds.
\fs18 8.15}
Solve the following binary subtraction problems: \par
}
15 \cf0 (a> \par
}
\cf0 110
\fs11 -}{\fs18 100 }\par
}
cf0 (b) \par
}
\cf0 1111
\fs15 -} 1010 \par
}
18 \cf0 ( c ) \par
}
cf0 10110
\fs15 -}{\fs18 1100 }\par
}
17 \cf0 ( d ) \par
}
001
{\f10 \fs15 -} 110 \par
}
17 \cf0 ( e ) \par
}
cf0 IIOOOI
i116 {\b0 \f10 \fs15 -}{\b0 \f20 \fs18 111 }\par
}
\cf0 Solution:
fi360 {\fs16 By}{\b0 \fs16 a}{\b0 \fs16 procedure}{\b0 \fs16 similar}{\b0
\fs16 to}{\b0 \fs16 that}{\b0 \fs16 illustrated}{\b0 \fs16 in}{\b0 \fs16
Fig.}{\b0 \fs16 8-13,}{\b0 \fs16 the}{\b0 \fs16 differences}{\b0 \fs16 fo
r}{\b0 \fs16 the}{\b0 \fs16 problems}{\b0 \fs16 are}{\b0 \fs16 found}{\b
0 \fs16 to }
\b0 \fs16 be}{\b0 \fs16 as}{\b0 \fs16 follows: }

\b0\i \f10 \fs14 (a)}{\b0
010,}{\b0\i
(}{\b0\i b}{\b0\i )}{\b0 \fs
16
101,}{\b0\i \f10 \fs15
(c)}{\b0 \fs16
1010,}{\i \f10 \fs16
(}{\i \f10 \fs16 d}{\i \f10 \fs16 )}{\b0 \fs16
1011,}{\i
(}{
\i e}{\i )}{\b0 \fs16
101010. }\par
}
cf0 8.16{\b0 \fs18
Draw}{\b0 \fs18 a}{\b0 \fs18 block}{\b0 \fs18 diagram}
{\b0 of}{\b0 \fs18 a}{\b0 \fs18 half}{\b0 \fs18 subtractor}{\b0 \fs18 and}
{\b0 \fs18 label}{\b0 \fs18 inputs}{\b0 \fs18 and}{\b0 \fs18 outputs. }
i958 {\b0 \fs16 See}{\b0 \fs16 Fig.}{\b0 \fs16 8-12b. }\par
}
f0 8.17 \par
}
raw a block diagram of a full subtractor and label inputs and outputs.
55 {\fs16 See}{\fs16 Fig.}{\fs16 8-14a. }\par
}
\cf0 8.18{\b0 \fs18
Draw}{\b0 \fs18 the}{\b0 \fs18 logic}{\b0 \fs18 diagr
am}{\b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 half}{\b0 \fs18 subtractor.}{\b0 \f
s18 Use}{\b0 \fs18 XOR}{\b0 \fs18 and}{\fs18 AND}{\b0 \fs18 gates}{\b0 \fs
18 plus}{\b0 \fs18 an}{\b0 \fs18 inverter.}{\b0 \fs18 Label }
fi599 {\b0 \fs18 inputs}{\b0 \fs18 and}{\b0 \fs18 outputs. }
fi959 {\b0 \fs16 See}{\b0 \fs16 Fig.}{\b0 \fs16 8-12a. }\par
}
\cf0 8.19{\b0 \fs18
When}{\b0 \fs18 half}{\b0 \fs18 adders}{\b0 \fs18
and}{\b0 \fs18 subtractors}{\b0 \fs18 are}{\b0 \fs18 compared,}{\b0 \fs18
it}{\b0 \fs18 is}{\b0 \fs18 found}{\b0 \fs18 that}{\b0 \fs18 the}{\b0
\fs18 half}{\b0 \fs18 subtractor}{\b0 \fs18 logic }\par
}
circuit contains one extra logic element which is an
358 {\b \fs16 A}{\b \fs16 HS}{\fs16 contains}{\fs16 one}{\fs16 inverter}
{\fs16 more}{\fs16 than}{\fs16 an}{\fs17 HA}{\fs16 logic}{\fs16 circu
it. }\par
}
(AND, inverter,{\fs18 OR). }\par
}
cf0 8.20 \par
}
List the difference{\i \fs19 (Di)}outputs from the half subtractor shown in Fi
g. 8-17. \par
}
. 81 \par
}
NARY ARITHMETIC{\fs17 AND} ARITHMETlC CIRCUITS \par
}
\par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
15 \cf0 Bo \par
}
\f10 \fs14 \cf0 A{\b0\i0 \fs11
--}{\f20 \fs15
B }
\cf0 {\i0 \f20 \fs17 Fig.}{\i0 \f20 \fs16 8-17}{\b0\i0 \f20 \fs17
Half}{\b0\
i0 \f20 \fs17 subtractor}{\b0\i0 \f20 \fs17 pulse-train}{\b0\i0 \f20 \fs17
problem }\par
}
\cf0 Solution:
fi354 {\b0 \fs17 Refer}{\b0 \fs17 to}{\fs16 t,,e}{\b0 \fs17 truth}{\b0 \fs1
7 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 8-11.}{\b0 \fs17 The}{\
i \f30 \fs19 Di}{\b0 \fs17 outputs}{\b0 \fs17 from}{\b0 \fs17 the}{\b0 \fs1
7 HS}{\b0 \fs17 (Fig.}{\b0 \fs17 8-17)}{\b0 \fs17 are}{\b0 \fs17 as}{\b0
\fs17 follows: }\par
}
lse a{\f10 \fs13 =} 1
{\i b}{\f10 \fs13 =} 0 \par
}
lse{\fs16 c}{\dn006 \f10 \fs11 =} 0
{\fs16 d}{\f10 \fs13 =}{\fs17 1 }\par
}
lse{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 0
{\fs17 f}{\f10 \fs13 =}{\fs17 1 }\par
}
f0 8.21 \par
}
ist the borrow-out{\b\i (Bo)}outputs from the half subtractor shown in Fig.{\f
s19 8-17. }
54 {\fs17 Refer}{\fs17 to}{\fs17 the}{\fs17 truth}{\fs17 table}{\fs17
in}{\fs17 Fig.}{\fs17 8-11.}{\fs17 The}{\i \fs18 Bo}{\fs17 outputs}{\fs1
7 from}{\fs17 the}{\fs17 HS}{\fs17 (Fig.}{\fs17 8-17)}{\fs17 are}{\fs17
as}{\fs17 follows: }\par
}
lse{\fs15 a}{\f10 \fs13 =}{\fs17 1 }
{\i \fs16 b}{\f10 \fs13 =}{\fs16 0 }\par
}
lse{\fs16 c}{\f10 \fs13 =} 0
{\fs16 d}{\f10 \fs13 =} 0 \par
}
lse{\b\i \fs16 e}{\f10 \fs13 =}{\fs16 0 }
{\i \f30 \fs18 f=}{\fs16 1 }\par
}
f0 8.22 \par
}
ist the difference{\b\i \f30 \fs21 (Di)}outputs from the full subtractor shown
in Fig.{\fs19 8-18. }\par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
5 \cf0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}

15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\fs17 8-18}{\b0 \fs17
Full}{\b0 \fs17 subtractor}{\b0 \fs17 p
ulse-train}{\b0 \fs17 problem }\par
}
\cf0 Solution:
fi351 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 truth}{\b0
\fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 8-15.}{\b0 \fs17 Th
e}{\i \f30 \fs19 Di}{\b0 \fs17 outputs}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \f
s17 FS}{\b0 \fs17 (Fig.}{\b0 \fs17 8-18)}{\b0 \fs17 are}{\b0 \fs17 as}{\b
0 \fs17 follows: }\par
}
ulse{\fs16 a}{\f10 \fs13 =}{\fs16 0 }
e{\b\i \fs16 b}{\dn006 \f10 \fs11 =} 1 \par
}
ulse{\fs16 c}{\dn006 \f10 \fs11 =}{\fs16 1 }
e{\b\i \f10 \fs16 d}{\f10 \fs13 =} 0 \par
}
ulse{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 1
e{\i \f30 \fs20 f=} 0 \par
}
ulse{\fs15 g}{\f10 \fs13 =} 0
e{\b\i h}{\dn006 \f10 \fs11 =} 1 \par
}
\cf0 8.23{\b0 \f20 \fs19
List}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 borrow-o
ut}{\i \f20 \fs19 (Bo)}{\b0 \f20 \fs19 outputs}{\b0 \f20 \fs19 from}{\b0 \f20
\fs19 the}{\b0 \f20 \fs19 full}{\b0 \f20 \fs19 subtractor}{\b0 \f20 \fs19 sh
own}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\b0 \f20 \fs19 8-18. }
fi960 {\b0 \f20 \fs17 Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 the}{\b0 \f20
\fs17 truth}{\b0 \f20 \fs17 table}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 Fi
g.}{\b0 \f20 \fs17 8-15.}{\b0 \f20 \fs17 The}{\i \fs17 Bo}{\b0 \f20 \fs17 o
utputs}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 the}{\f20 \fs17 FS}{\b0 \f20 \f
s17 (Fig.}{\b0 \f20 \fs17 8-18)}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17 as}{\b0
\f20 \fs17 follows: }\par
}
ulse{\i \f10 \fs14 a}{\dn006 \f10 \fs11 =}{\fs16 0 }
e{\i \fs16 b}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
ulse{\f10 \fs14 c}{\dn006 \f10 \fs11 =}{\fs16 0 }

e{\b\i \fs17 d}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}
ulse{\i e}{\dn006 \f10 \fs10 =}{\fs16 1 }
e f ={\fs16 0 }\par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =}{\fs16 1 }
e{\b\i \fs17 h}{\f10 \fs13 =}{\b \fs16 1 }\par
}
cf0 8.24 \par
}
When 2-bit numbers are subtracted, an
687 (FS,{\b \fs19 HS)} is used for the 2s column.
}
(FS,{\b \fs19 HS)} is used for the Is column and an \par
}
In binary subtraction, an{\b HS} is used for the 1s column and an{\b FS
} is used for the{\fs17 2s} column. \par
}
\par
}
}
AP.{\fs17 8 }\par
}
\cf0 8-4{\fs19
PARALLEL}{\fs19 ADDERS}{\fs19 AND}{\fs19 SUBTRACTORS }
fi364 {\b0 \fs18 Binary}{\b0 \fs18 addition}{\b0 \fs18 can}{\b0 \fs18 be}{\b0
\fs18 accomplished}{\b0 \fs18 in}{\b0 \fs18 two}{\b0 \fs18 different}{\b0
\fs18 ways.}{\b0 \fs18 Either}{\i \fs19 parallel}{\b0 \fs18 or}{\i \fs19 s
erial}{\i \fs19 adders}{\b0 \fs18 can}{\b0 \fs18 be }
\b0 \fs18 used.}{\b0 \fs18 A}{\b0 \fs18 serial}{\b0 \fs18 adder}{\b0 \fs18 o
perates}{\b0 \fs18 in}{\b0 \fs18 much}{\b0 \fs18 the}{\b0 \fs18 same}{\b0 \f
s18 way}{\b0 \fs18 as}{\b0 \fs18 addition}{\b0 \fs18 by}{\b0 \fs18 hand.}{\
b0 \fs18 It}{\b0 \fs18 first}{\b0 \fs18 adds}{\b0 \fs18 the}{\b0 \fs19 Is}
{\b0 \fs18 column, }
\b0 \fs18 then}{\b0 \fs18 the}{\b0 \fs19 2s}{\b0 \fs18 column}{\b0 \fs18
plus}{\b0 \fs18 the}{\b0 \fs18 carry,}{\b0 \fs18 then}{\b0 \fs18 the}{\b
0 \fs18 4s}{\b0 \fs18 column}{\b0 \fs18 plus}{\b0 \fs18 the}{\b0 \fs18 c
arry,}{\b0 \fs18 and}{\b0 \fs19 so}{\b0 \fs18 forth.}{\b0 \fs18 Serial}{\
b0 \fs18 addition }
\b0 \fs18 takes}{\b0 \fs18 a}{\b0 \fs18 fair}{\b0 \fs18 amount}{\b0 of}{\b0
\fs18 time}{\b0 \fs18 when}{\b0 \fs18 long}{\b0 \fs18 binary}{\b0 \fs18 n
umbers}{\b0 \fs18 are}{\b0 \fs18 added.}{\b0 \fs18 Parallel}{\b0 \fs18 ad
dition,}{\b0 \fs18 however,}{\b0 \fs18 is}{\b0 \fs18 very }
\b0 \fs18 fast.}{\b0 \fs18 In}{\b0 \fs18 parallel}{\b0 \fs18 addition,}{\b0 \
fs18 all}{\b0 \fs18 the}{\b0 \fs18 binary}{\b0 \fs18 words}{\b0 \fs18 (a}{\
i \fs19 word}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 group}{\b0 \fs18 of}{\b
0 \fs18 bits}{\b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 given}{\b0 \fs18 length,
}{\b0 \fs18 such}{\b0 \fs18 as}{\b0 \fs18 4,}{\b0 \fs19 8, }
\b0 \fs18 or}{\b0 16)}{\b0 \fs18 to}{\b0 \fs18 be}{\b0 \fs18 added}{\b0 \
fs18 are}{\b0 \fs18 applied}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 in
puts}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 sum}{\b0 \fs18 is}{\b0 \fs
18 almost}{\b0 \fs18 immediate.}{\b0 \fs18 Serial}{\b0 \fs18 adders}{\b0
\fs18 are }
\b0 \fs18 simpler}{\b0 \fs18 but}{\b0 \fs18 slower.}{\b0 \fs18 Parallel}{\b0
\fs18 adders}{\b0 \fs18 are}{\b0 \fs18 faster,}{\b0 \fs18 but}{\b0 \fs18
they}{\b0 \fs18 have}{\b0 \fs18 more}{\b0 \fs18 complicated}{\b0 \fs18 logi
c}{\b0 \fs18 circuits. }
fi360 {\fs18 A}{\i \fs19 4-bit}{\i \fs19 parallel}{\i \fs19 adder}{\b0 \fs18
is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 8-19.}{\b0 \fs18
A}{\b0 \fs18 single}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 (HA)}{\b0 \
fs18 and}{\b0 \fs18 three}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 (FA)
}
\b0 \fs18 circuits}{\b0 \fs18 are}{\b0 \fs18 used.}{\b0 \fs18 Note}{\b0 \fs1
8 that}{\b0 \fs18 the}{\b0 \fs18 top}{\b0 \fs18 HA}{\b0 \fs18 adds}{\b0 \f
s18 the}{\b0 1s}{\b0 \fs18 column}{\i \fs18 (}{\i \fs18 A}{\i \fs18 ,}{\b
0 \fs18 and}{\fs19 Bl).}{\b0 \fs18 The}{\b0 \fs19 2s}{\b0 \fs18 column}{\b
0 \fs18 uses}{\b0 \fs18 a}{\b0 \fs18 full }
\b0 \fs18 adder.}{\b0 \fs18 The}{\b0 \fs19 2s}{\b0 \fs18 FA}{\b0 \fs18 adds}
{\b0 \fs18 the}{\i \fs19 A}{\i \fs19 ,}{\b0 \fs18 and}{\i \fs19 B,}{\b0 \
fs18 plus}{\b0 \fs18 the}{\b0 \fs18 carry}{\b0 \fs18 from}{\b0 \fs18 the}{
\b0 1s}{\b0 \fs18 adder.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b
0 \fs18 carry}{\b0 \fs18 line}{\b0 \fs18 runs }
\b0 \fs18 from}{\b0 \fs18 the}{\i \fs19 CO}{\b0 \fs18 of}{\b0 \fs18 the}{\b0
1s}{\b0 \fs18 adder}{\b0 \fs18 to}{\b0 \fs18 the}{\i \fs19 Cin}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs19 2s}{\b0 \fs18 adder.}{\b0 \fs18 The}{\b0 \fs18
4s}{\b0 \fs18 and}{\b0 8s}{\b0 \fs18 adders}{\b0 \fs18 also}{\b0 \fs18 are
}{\b0 \fs18 full}{\b0 \fs18 adders.}{\b0 \fs18 The }
\b0 \fs18 sum}{\b0 \fs21 (C)}{\b0 \fs18 output}{\b0 \fs18 of}{\b0 \fs18 each
}{\b0 \fs18 adder}{\b0 \fs18 is}{\b0 \fs18 connected}{\b0 \fs18 to}{\b0 \fs1
8 a}{\b0 \fs18 sum}{\b0 \fs18 indicator}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \
fs18 lower}{\b0 \fs18 right}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 8-19.}{\b0 \
fs18 The}{\i CO }
\b0 \fs18 of}{\b0 \fs18 the}{\b0 8s}{\b0 \fs18 FA}{\b0 \fs18 is}{\b0 \fs18
an}{\b0 \fs18 overflow}{\b0 \fs18 and}{\b0 \fs18 forms}{\b0 \fs18 the}{\b0 \
fs19 16s}{\b0 \fs18 place}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs19 sum. }\p
ar
}
\cf0 Addition problem

fi198 {\i \f10 \fs14 A4}{\i \f10 \fs14
A3}{\i \f10 \fs14
A2}{\i \f10 \fs14
A, }
\b0 \f10 \fs11 +}{\i \f10 \fs14 B4}{\i \f10 \fs14
B3}{\i \f10 \fs14
B2}{
\i \f10 \fs14
B, }\par
}
14 \cf0 A
cf0 {\f20 \fs15 B }\par
}
14 \cf0 \par}{\phpg\posx5258\pvpg\posy6061\absw649\absh840 \sl-202 \b\i \f10 \fs14 \cf0
\fi21 {\i0 \f20 \fs15 HA }
\fi89 {\i0 \fs14 1s }
cf0 \fi201 {\i0 \f20 \fs15 carry }\par
}
cf0 z
\b\i \f20 \fs11 C}{\b\i \f20 \fs11 O }\par
}
cf0 I: \par
}
15 \cf0 Cin \par
}
f0 r \par
}
\par
}
14 \cf0 A4
{\i0 \f30 \fs17 B4 }\par
}
20 \fs15 \cf0 Sum
{\fs16 Fig.}{\b0 \fs17 8-19}{\b0 \fs17
A}{\b0 \fs16 4-bit}{\b0 \fs16 para
llel}{\b0 \fs16 adder }\par
}
8 \cf0 Suppose the task were to add binary 1111to{\fs19 1111}with the parallel
adder shown in Fig.{\fs19 8-19.}{\b As }
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-240 \f20 \fs18 \cf0 soo
n as these numbers were applied to the eight inputs on the left, the output of
{\fs19 11110} (decimal{\fs19 30) }
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-238 \f20 \fs18 \cf0 wou
ld appear on the output sum indicators. This parallel adder is limited to four i
nput bits. More full
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-233 \f20 \fs18 \cf0 add
ers could be attached to the circuit for the{\fs19 16s} place,{\fs19 32s} pla
ce, and{\fs19 so} forth.
363 As with addition, subtraction can be done serially or by parallel
subtractors. Figure 8-20 is a
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-239 \f20 \fs18 \cf0 dia
gram of a familiar-looking{\b\i \fs19 4-bit}{\b\i \fs19 parallel}{\b\i \fs
19 subtractor.} Its wiring is quite similar to that{\fs19 of} the 4-bit
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-232 \f20 \fs18 \cf0 par
allel adder that was just studied. The two 4-bit numbers are shown in the pr
oblem section at the
\par}{\phpg\posx847\pvpg\posy11791\absw9062\absh1705 \sl-242 \f20 \fs18 \cf0 upp
er left. Note that{\b\i \fs19
B,}{\b\i \fs19 B,}{\b\i \fs19 B,}{\b\i \fs
19 B,} (subtrahend) is subtracted from{\b\i
A,A,A,A,} (minuend). The
\par
}
}
cf0 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS \par
}
f0 181 \par
}
\fs15 \cf0 Subtraction
fi416 problem
fi150 {\i \f10 \fs14 A,}{\i \f10 \fs14
A,}{\i \f10 \fs14
A,}{\i \f10 \fs14
A,} (minuend)
\b0 \f10 \fs19 -}{\i \f10 \fs14 B4}{\i \fs15 B3}{\i \fs15
B2}{\i B,} (su
btrahend)
fi1850 {\b0\dn006 \f10 \fs11 * }\par
}
0 \fs15 \cf0 Difference
f0 \fi2980 {\fs16 Fig.}{\fs16 8-20}{\fs17
A}{\fs17 4-bit}{\fs17 parallel}
{\fs17 subtractor }
f0 {\b0 \fs19 difference}{\b0 \fs19 between}{\b0 \fs19 these}{\b0 \fs19 numbe
rs}{\b0 \fs19 will}{\b0 \fs19 appear}{\b0 \fs19 on}{\b0 \fs19 the}{\b0 \fs19
difference}{\b0 \fs19 output}{\b0 \fs19 indicators}{\b0 \fs19 at}{\b0 \fs19
the}{\b0 \fs19 lower}{\b0 \fs19 right}{\b0 \fs19 in }
\b0 \fs19 Fig.}{\b0 \fs19 8-20. }
fi354 {\b0 \fs19 The}{\b0 \fs19 1s}{\b0 \fs19 column}{\b0 \fs19 in}{\b0 \fs
19 Fig.}{\b0 \fs19 8-20}{\b0 \fs19 uses}{\b0 \fs19 a}{\b0 \fs19 half}{\
b0 \fs19 subtractor}{\fs19 (HS).}{\b0 \fs19 The}{\fs19 2s,}{\b0 \fs19
4s,}{\b0 \fs19 and}{\fs19 8s}{\b0 \fs19 columns}{\b0 \fs19 use}{\b0 \fs1
9 full }
\b0 \fs19 subtractors}{\fs19 (FS).}{\b0 \fs19 Each}{\b0 \fs19 of}{\b0 \fs19

the}{\i \f30 \fs21 Di}{\b0 \fs19 outputs}{\b0 \fs19 of}{\b0 \fs19 the}
{\b0 \fs19 subtractors}{\b0 \fs19 is}{\b0 \fs19 connected}{\b0 \fs19 to}{
\b0 \fs19 an}{\b0 \fs19 output}{\b0 \fs19 indicator}{\b0 \fs19 to }
\b0 \fs19 show}{\b0 \fs19 the}{\b0 \fs19 difference.}{\b0 \fs19 The}{\b0 \fs1
9 borrow}{\b0 \fs19 lines}{\b0 \fs19 connect}{\b0 \fs19 the}{\i \fs18 Bo}{\
b0 \fs19 output}{\b0 \fs18 of}{\b0 \fs19 one}{\b0 \fs19 subtractor}{\b0 \fs1
9 to}{\b0 \fs19 the}{\i \fs19 Bin}{\b0 \fs19 input}{\b0 \fs19 of}{\b0 \fs19
the }
\b0 \fs19 next}{\b0 \fs19 most}{\b0 \fs19 significant}{\b0 \fs19 bit.}{\b0 \
fs19 The}{\b0 \fs19 borrow}{\b0 \fs19 lines}{\b0 \fs19 keep}{\b0 \fs19 tr
ack}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19 many}{\b0 \fs19 borrows}{\b0 \
fs19 in}{\b0 \fs19 binary}{\b0 \fs19 subtraction.}{\b0 \fs19 If }
\b0 \fs19 greater}{\b0 \fs19 than}{\b0 \fs19 4-bit}{\b0 \fs19 numbers}{\b0 \f
s19 were}{\b0 \fs18 to}{\b0 \fs19 be}{\b0 \fs19 subtracted,}{\b0 \fs19 more
}{\b0 \fs19 full}{\b0 \fs19 subtractors}{\b0 \fs19 would}{\b0 \fs19 be}{\b0
\fs19 added}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 circuit. }
\b0 \fs19 FSs}{\b0 \fs19 would}{\b0 \fs19 be}{\b0 \fs19 added}{\b0 \fs19 in}
{\b0 \fs19 the}{\b0 \fs19 pattern}{\b0 \fs19 shown}{\b0 \fs19 in}{\b0 \fs19
Fig.}{\b0 \fs19 8-20.}{\b0 \fs19 This}{\b0 \fs19 parallel}{\b0 \fs19 subtr
actor}{\b0 \fs19 acts}{\b0 \fs19 on}{\b0 \fs19 the}{\b0 \fs19 inputs}{\b0 \f
s19 and }
\b0 \fs19 gives}{\b0 \fs19 the}{\b0 \fs19 difference}{\b0 \fs19 almost}{\b0 \
fs19 immediately. }\par
}
\cf0 Word{\i \f10 \fs14 A }\par
}
\cf0 4-bit \par
}
\cf0 El \par
}
\cf0 parallel{\b0 \f10 \fs14
2, }
fi61 adder \par
}
\cf0 Inputs \par
}
\cf0 Word{\i \fs15 B }\par
}
s14 \cf0 Cout \par
}
\cf0 Carry input{\b0 \f10 \fs23 - }\par
}
\par
}
20 \fs15 \cf0 Typical

\fi4211 Sum
{\fs16 Fig.}{\fs17 8-21}{\fs17
Logic}{\fs17 symbol}{\fs17 for}{\fs17 a}{\
fs17 commercial}{\fs17 7483}{\fs17 4-bit}{\fs17 parallel-adder}{\fs17 IC }\
par
}
\cf0 (7483) \par
}
\par
}
}
}
\cf0 By comparing the 4-bit parallel adder with the subtractor, it can be seen
that the circuits are very
lar (see Figs. 8-19 and 8-20).{\b \f10 \fs17 As} a practical matter, full
adders are purchased in{\fs18 IC} form rather
being wired from logic gates. In fact, several more complicated adders and arit
hmetic logic units
18 (ALUs)} are available in{\fs18 IC} form. Typically, an adder unit is shown
as a block symbol like the one in
8-21. This logic symbol is actually the diagram for a commercial 7483{\b\i \fs1
8 4-bit}{\i full}{\b\i adder}{\fs18 IC.} It could
\par}{\phpg\posx857\pvpg\posy1399\absw9115\absh1708 \sl-237 \f20 \fs18 \cf0 also
be the symbol{\fs19 for} the 4-bit parallel adder shown in Fig. 8-19{\fs18 i
f} the carry input{\i \fs19 (Cin)}were left{\fs19 off }
symbol. The{\b\i \f10 \fs18 A,} and{\i B,} inputs are the{\fs19 LSB}
inputs. The{\b\i \f10 \fs17 A,} and{\b\i R,} connections are the{\fs19
MSB }
ts. It is typical to GND the{\i Cin} (carry input) when not connected to a
preceding parallel adder. \par
}
LVED PROBLEMS \par
}
f0 8.25 \par
}
efer to Fig. 8-19. The top adder (1s HA) will add the
}
LSBs, MSBs). \par

}
he top adder shown in Fig. 8-19 will add the{\fs17 LSBs} (least signi
ficant bits). \par
}
f0 8.26 \par
}
efer to Fig. 8-20. The 8s full subtractor will subtract the
}
LSBs, MSBs). \par
}
he 8s FS shown in Fig. 8-20 will subtract the MSBs (most significant b
its). \par
}
f0 8.27 \par
}
efer to Fig. 8-19. If{\b\i \fs19 A}{\b\i \fs19 ,}{\f10 \fs14 =}{\fs18 1} an
d{\i \fs19 B,}{\dn006 \f10 \fs13 = }\par
}
{\phpg\posx1463\pvpg\posy6911\absw245\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 be
\par
}
{\phpg\posx1757\pvpg\posy6983\absw597\absh126 \f10 \fs10 \cf0 \f10 \fs10 \cf0 __
__ \par
}
HIGH, LOW). \par
}
, then the carry line between the{\fs18 Is} and{\fs19 2s} adders will \par
}
\cf0 Solution:
fi357 {\b0 \fs16 According}{\b0 \fs16 to}{\b0 \fs16 line}{\b0 \fs16 4}{\b0
\fs16 in}{\b0 \fs16 the}{\b0 \fs16 truth}{\b0 \fs16 table}{\b0 \fs16
in}{\b0 \fs16 Fig.}{\b0 \fs16 8-2,}{\b0 \fs16 with}{\i \f10 \fs16 A}{\i \
f10 \fs16 ,}{\b0 \fs16 and}{\b0\i \fs18 B,}{\b0 \fs16 equal}{\b0 \fs16
to}{\b0 \fs16 1,}{\b0 \fs16 the}{\b0 \fs16 carry}{\b0 \fs16 line}{\b0 \fs
16 between }
\b0 \fs16 the}{\b0 \fs16 1s}{\b0 \fs16 and}{\b0 \fs16 2s}{\b0 \fs16 adder
s}{\b0 \fs16 shown}{\b0 \fs16 in}{\b0 \fs16 Fig.}{\b0 \fs16 8-19}{\b0 \f
s16 will}{\b0 \fs16 be}{\b0 \fs17 HIGH,}{\b0 \fs16 indicating}{\b0 \fs16
a}{\b0 \fs16 carry. }\par
}
cf0 8.28{\b0 \fs18
Draw}{\b0 \fs18 a}{\b0 \fs18 diagram}{\b0 \fs18 of}{\b
0 \fs18 a}{\b0 \fs18 6-bit}{\b0 \fs18 parallel}{\b0 \fs18 adder}{\b0 \fs18
using}{\b0 \fs18 one}{\b0 \fs18 HA}{\b0 \fs18 and}{\b0 \fs18 five}{\b0 \fs
18 FAs. }

i961 {\b0 \fs16 See}{\b0 \fs16 Fig.}{\b0 \fs16 8-22. }\par
}
cf0 8.29{\b0 \fs18
When}{\b0 \fs18 the}{\b0 \fs18 6-bit}{\b0 \fs18 unit}
{\b0 \fs18 in}{\b0 \fs18 Prob.}{\b0 \fs18 8.28}{\b0 \fs18 adds}{\b0 \fs18
111111}{\b0 \fs18 and}{\b0 \fs18 111111,}{\b0 \fs18 the}{\b0 \fs18 sum}{\b
0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 binary }\par
}
{\phpg\posx1471\pvpg\posy9975\absw805\absh503 \f20 \fs18 \cf0 \f20 \fs18 \cf0 eq
uals
}
decimal. \par
}
\f20 \fs18 which }\par
}
6 \cf0 When the 6-bit unit in Prob.{\fs17 8.28} adds binary 111111 and
111111, the sum is binary 1111110 by a
cedure similar to that illustrated in Fig.{\fs16 8-4a.} The sum (1111
110) is then converted to its decimal
\par}{\phpg\posx1471\pvpg\posy10603\absw8238\absh581 \sl-219 \f20 \fs16 \cf0 equ
ivalent{\fs17 of} 126{\b \fs16 by} means{\fs16 of} the procedure shown
in Fig. 1-2. \par
}
\cf0 8.30{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 8-19.}
{\b0 \fs18 When}{\b0 \fs18 1100}{\b0 \fs18 and}{\b0 \fs18 0011}{\b0 \fs18
are}{\b0 \fs18 added,}{\b0 \fs18 which}{\b0 \fs18 carry}{\b0 \fs18 lines}{\b
0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 HIGH? }
fi953 {\b0 \fs16 When}{\b0 \fs16 1100}{\b0 \fs16 and}{\b0 \fs16 0011}{\b0 \
fs16 are}{\b0 \fs16 added}{\b0 \fs16 with}{\b0 \fs16 the}{\b0 \fs16 adde
r}{\b0 \fs16 shown}{\b0 \fs16 in}{\b0 \fs16 Fig.}{\b0 \fs16 8-19,}{\b0\i
\fs17 no}{\b0 \fs16 carry}{\b0 \fs16 lines}{\b0 \fs16 are}{\b0 \fs16 HI
GH}{\b0 \fs16 because }
fi596 {\b0 \fs16 no}{\b0 \fs16 carries}{\b0 \fs16 occur}{\b0 \fs16 in}{\b0
\fs16 this}{\b0 \fs16 addition}{\b0 \fs16 problern. }\par
}
cf0 8.31 \par
}
Refer to Fig. 8-19. If all eight inputs to the parallel adder are HIGH, the bina
ry output will be
621 {\f10 \fs18 ,} which equals
in decimal. \par
}

.{\fs17 81 }\par
}
}
f0 183 \par
}
cf0 Inputs \par
}
f0 I \par
}
\par
}
{\phpg\posx5367\pvpg\posy4265\absw122\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 r,
\par
}
par
}
16 \cf0 cin \par
}
\par
}
par
}
0 \fs15 \cf0 Sum
f0 {\fs17 Fig.}{\fs17 8-22}{\fs17
A}{\b0 \fs17 6-bit}{\b0 \fs17 parallel
}{\b0 \fs17 adder }\par
}
\cf0 Solution:
fi360 {\b0 If}{\b0 all}{\b0 inputs}{\b0 to}{\b0 the}{\b0 parallel}{\b0
adder}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-19}{\b0 are}{\b0 \fs17 HI
GH,}{\b0 the}{\b0 binary}{\b0 output}{\b0 \fs17 (sum)}{\b0 will}{\b0
be }\par
}
11,{\f10 \fs27 + }\par
}
111,{\f10 \fs14 =} 11110, (sum) \par
}
he{\fs17 sum} 11110, is equal to a decimal{\fs17 30} according to the
procedure shown in Fig. 1-2. \par
}
efer to{\b Fig.} 8-20. The

}
bottom, top) subtractor is subtracting the least significant bits. \par
}
f0 8.32 \par
}
\cf0 The top subtractor{\fs17 is} subtracting the{\b \fs16 LSBs} in the
problem in Fig. 8-20.
{\b \fs18 8.33}{\fs18
When}{\fs18 0011}{\fs18 is}{\fs18 subtracted}{\fs18
from}{\fs18 1101in}{\fs18 Fig.}{\fs18 8-20,}{\fs18 the}{\fs18 borrow}{\fs
18 line}{\fs18 between}{\fs18 the }\par
}
subtractor and the
}
(2s,{\b 4s,}{\fs19 8s)} subtractor is{\fs19 HIGH. }\par
}
Is,{\fs18 2s,}{\fs19 4s) }\par
}
17 \cf0 When 0011 is subtracted from 1101{\fs17 in} Fig. 8-20, the borrow
line between the 2s and 4s subtractors is
fs17 HIGH.} This is shown by noting the borrow between the 4s and 2
s places in the binary subtraction
\par}{\phpg\posx1457\pvpg\posy12050\absw8276\absh1090 \sl-218 \f20 \fs17 \cf0 pr
oblem
0 \fi4088 {\f10 \fs18 /}{\b \fs17 lfl }
i3640 {\fs17 1}{\fs17
l}{\fs17
o}{\fs17
f}{\fs17
l}{\fs17
1
}\par
}
74 1 \par
}
\cf0 0
ar
}
4 1 \par
}
\par
}
\par
}
0 184 \par
}
cf0 BINARY ARITHMETIC{\fs17 AND} ARITHMETIC CIRCUITS \par
}
f0 [CHAP. 8 \par
}
f0 8.34 \par
}
ist the binary sum at the output indicator for each input pulse to
the 4-bit parallel adder
n in Fig.{\b \fs19 8-23. }\par
}
4 \cf0 o \par
}
14 \cf0 n \par
}
14 \cf0 m \par
}
4 \cf0 l \par
}
14 \cf0 k \par
}
15 \cf0 i \par
}
3 \cf0 j \par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
f0 f \par
}
f0 e \par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
{\phpg\posx7659\pvpg\posy4006\absw40\absh89 \f10 \fs6 \cf0 \f10 \fs6 \cf0 , \par
}
0 E3 \par
}
fs17 \cf0 E4
0 {\i \f10 \fs11 CO }\par
}
f0 1 \par
}
\cf0 output indicators \par
}
\cf0 Fig.{\fs16 8-23}{\fs17
Parallel-adder}{\fs17 pulse-train}{\fs17 probl
em }\par
}
\cf0 Solution:
fi360 {\fs17 Refer}{\fs16 to}{\fs17 the}{\fs17 procedure}{\fs17 in}{\fs17
Fig.}{\fs16 8-4a.}{\fs17 The}{\fs17 binary}{\fs16 sums}{\fs17 for}{\fs17 t
he}{\fs17 pulses}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs17 8-23}{\fs17 are
}{\fs17 as}{\fs17 follows: }\par
}
\cf0 pulse{\b0\i \f10 \fs14 a}{\b0 \f10 \fs13 =}{\b0 \fs16 0101}{\b0 \f10 \f
s25 +}{\b0 \fs16 0101}{\b0 \f10 \fs13 =}{\b0 \fs16 01010 }\par
}
\cf0 pulse{\fs17 b}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 0010}{\b0 \f10 \fs25
+ }
\par}{\phpg\posx1459\pvpg\posy7604\absw1341\absh499 \sl-243 \b \f20 \fs17 \cf0 p
ulse{\b0\i \f10 \fs14 c}{\b0 \f10 \fs13 =} 1000{\b0 \f10 \fs26 + }\par
}
cf0 pulse{\b0\i \f10 \fs16 d}{\b0\dn006 \f10 \fs11 = }
lse{\i \fs16 e}{\b0\dn006 \f10 \fs11 = }\par
}
010{\f10 \fs13 =} 01100
{\f10 \fs13 =} 10100 \par
}
\cf0 0110{\f10 \fs26 +} 0011{\f10 \fs13 =} 01001
{\f10 \fs26 +}{\fs17 0100}{\f10 \fs13 =} 00101 \par
}

\cf0 pulse{\i \f30 \fs17 i}{\b0 \f10 \fs13 =}{\b0 \fs16 0011}{\b0 \f10 \fs24
+}{\b0 \fs16 0010}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 00101 }
pulse{\b0\i \f10 \fs15 j}{\b0 \f10 \fs13 =}{\b0 \fs16 1101}{\b0 \f10 \fs24
+}{\b0 \fs16 1111}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 11100 }
pulse{\fs17 k}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 1110}{\b0 \f10 \fs25 +}{\
b0 \fs16 1001}{\b0\dn006 \f10 \fs11 =}{\b0\dn006 \fs16 10111 }
pulse{\b0 \fs17 1}{\b0 \f10 \fs13 =}{\b0 \fs16 0001}{\b0 \f10 \fs25 +}{\b0 \
fs16 0110}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 00111 }
pulse{\i \f30 rn}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 0010}{\b0 \f10 \fs25 +
}
pulse{\fs16 n}{\b0 \f10 \fs13 =}{\b0 \fs16 1001}{\b0 \f10 \fs26 +}{\b0 \fs1
6 0111}{\b0\dn006 \f10 \fs11 =}{\b0\dn006 \fs16 10000 }
pulse{\fs16 o}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 1111}{\b0 \f10 \fs26 +}{\
b0 \fs16 1111}{\b0\dn006 \f10 \fs11 =}{\b0 \fs16 11110 }\par
}
001{\dn006 \f10 \fs11 =} 01011 \par
}
\cf0 pulse{\i \f30 \fs18 f}{\i \f30 \fs18 =}{\b0 \fs16 0011}{\b0 \f10 \fs25
+ }\par
}
011{\f10 \fs14 =} 01110 \par
}
\cf0 pulse{\b0\i \f10 \fs14 g}{\b0\i \f10 \fs14 =}{\b0 \fs16 1111}{\b0 \f10
\fs26 +}{\b0 \fs16 0111}{\b0 \f10 \fs13 =}{\b0 \fs16 10110 }\par
}
cf0 pulse{\fs18 h}{\b0\dn006 \f10 \fs11 = }\par
}
000{\f10 \fs26 +} 1101{\f10 \fs13 =} 10101 \par
}
\cf0 8-5{\fs18
USING}{\fs18 FULL}{\fs18 ADDERS }
\fi362 {\fs19 A}{\b0 \fs18 4-bit}{\b0 \fs18 parallel}{\b0 \fs18 adder}{\b0
\fs18 using}{\b0 \fs18 three}{\b0 \fs18 full}{\b0 \fs18 adders}{\b0 \fs1
8 and}{\b0 \fs18 one}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 was}{\b
0 \fs18 studied}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-19.}{\b0 \fs18
To }
{\b0 \fs18 standardize}{\b0 \fs18 circuitry}{\b0 \fs18 and}{\b0 \fs18 to}{\b0
\fs18 do}{\b0 \fs18 more}{\b0 \fs18 complicated}{\b0 \fs18 arithmetic,}{\b0
\fs18 a}{\b0 \fs18 somewhat}{\b0 \fs18 different}{\b0 \fs18 4-bit}{\b0 \fs1
8 adder}{\b0 \fs18 is}{\b0 \fs18 used. }
{\b0 \fs18 This}{\b0 \fs18 new}{\b0 \fs18 4-bit}{\b0 \fs18 adder}{\b0 \fs18
is}{\b0 \fs18 diagrammed}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-24.}{
\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 four}{\b0 \fs18 full}{\b0 \fs18
adders}{\b0 \fs18 are}{\b0 \fs18 used}{\b0 \fs18 in}{\b0 \fs18 this}{\b0 \
fs18 revised }
{\b0 \fs18 circuit.}{\b0 \fs19 To}{\b0 \fs18 make}{\b0 \fs18 the}{\fs18 1s}{
\b0 \fs18 FA}{\b0 \fs18 operate}{\b0 \fs18 like}{\b0 \fs18 a}{\b0 \fs18 hal
f}{\b0 \fs18 adder,}{\b0 \fs18 the}{\i \fs18 Cin}{\b0 \fs18 input}{\b0 \fs18
to}{\b0 \fs18 the}{\b0 \fs18 FA}{\b0 \fs18 is}{\b0 \fs18 grounded}{\fs19
(LOW).}{\b0 \fs18 The }
{\b0 \fs18 revised}{\b0 \fs18 circuit}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \f
s18 Fig.}{\b0 \fs18 8-24}{\b0 \fs18 will}{\b0 \fs18 operate}{\b0 \fs18 exac
tly}{\b0 \fs18 like}{\b0 \fs18 the}{\b0 \fs18 older}{\b0 \fs18 version}{\b0
\fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-19. }
\fi365 {\b0 \fs18 The}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 truth}{\b0
\fs18 table}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-25}{\b0 \fs18 has}
{\b0 \fs18 been}{\b0 \fs18 rearranged}{\b0 \fs18 somewhat}{\b0 \fs18 to}{\
b0 \fs18 help}{\b0 \fs18 show}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 f
ull }
{\b0 \fs18 adder}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 converted}{\b0 \fs18
to}{\b0 \fs18 a}{\b0 \fs18 half}{\b0 \fs18 adder}{\b0 \fs18 by}{\b0 \fs18
holding}{\b0 \fs18 the}{\i \fs18 Cin}{\b0 \fs18 input}{\fs19 LOW.}{\b0 \fs1
8 Consider}{\b0 \fs18 the}{\b0 \fs18 upper}{\b0 \fs18 half}{\b0 \fs18 of}{\
b0 \fs18 the }
{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18
in}{\b0 \fs18 Fig.}{\fs18 8-25.}{\b0 \fs18 Note}{\b0 \fs18 that}{\i \fs18
Cin}{\b0\dn006 \f10 \fs13 =}{\b0 \fs18 0}{\b0 \fs18 for}{\b0 \fs18 each}{\b
0 \fs18 line}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 unshaded}{\b0 \fs18 se
ction}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 truth }
{\b0 \fs18 table.}{\b0 \fs18 The}{\i \fs18 B,}{\i \fs18 A}{\i \fs18 ,}{\b0 \
fs21 E,}{\b0 \fs18 and}{\i \fs19 CO}{\b0 \fs18 columns}{\b0 \fs18 now}{\i \
fs18 correspond}{\i \fs18 exactly}{\b0 \fs18 with}{\b0 \fs18 the}{\b0 \fs18
half}{\b0 \fs18 adder}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 in}{\b0
\fs18 Fig.}{\fs19 8-2. }
\fi360 {\b0 \fs18 The}{\b0 \fs18 4-bit}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0
\fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\fs19 8-24}{\b0 \fs18 is}{\b0 \f
s18 a}{\b0 \fs18 block}{\b0 \fs18 diagram}{\b0 \fs18 of}{\b0 \fs18 the}{\fs
19 7483}{\b0 \fs18 full}{\b0 \fs18 adder}{\fs19 IC}{\b0 \fs18 introduced}{\
b0 \fs18 in }
{\b0 \fs18 Fig.}{\fs18 8-21.}{\b0 \fs18 Four-bit}{\b0 \fs18 full}{\b0 \fs18
adder}{\b0 \fs19 ICs}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 connected}{\b0
\fs18 to}{\b0 \fs18 form}{\b0 \fs18 8-,}{\b0 \fs18 12-,}{\b0 \fs18 16-,}{\b
0 \fs18 or}{\b0 \fs18 even}{\b0 \fs18 32-bit}{\b0 \fs18 parallel}{\b0 \fs18
adders. }
{\i \f10 \fs17 An}{\b0 \fs18 8-bit}{\b0 \fs18 parallel}{\b0 \fs18 adder}{\b
0 \fs18 is}{\b0 \fs18 featured}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 826.}{\b0 \fs18 Note}{\b0 \fs18 the}{\b0\i \fs18 Cin}{\b0 \fs18 input}{\b0
\fs18 to}{\b0 \fs18 the}{\b0 \fs18 top}{\b0 \fs18 7483}{\b0 \fs19 IC}{\b
0 \fs18 is}{\b0 \fs18 grounded }
{\fs19 (LOW).}{\fs18 As}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 8-24,}{\b0
\fs18 this}{\fs19 LOW}{\b0 \fs18 at}{\i \fs18 Cin}{\b0 \fs18 converts}{\b0
\fs18 the}{\b0 \fs18 1s}{\b0 \fs18 full}{\b0 \fs18 adder}{\b0 \fs18 to}{\b0
\fs18 a}{\b0 \fs18 half}{\b0 \fs18 adder.}{\b0 \fs18 The}{\i \fs19 CO}{\b0
\fs18 output}{\b0 \fs18 of }\par
}
.{\fs17 81 }\par
}
}
\par
}
\cf0 Binary
\par}{\phpg\posx2772\pvpg\posy1451\absw1261\absh335 \sl-173 \f20 \fs15 \cf0 addi
tion{\fs16 problem }\par
}
{\phpg\posx2838\pvpg\posy2205\absw106\absh82 \f10 \fs6 \cf0 \f10 \fs6 \cf0 + \pa
r
}
11 \cf0 B4{\fs15 B3}{\fs12
B2}{\fs11 Bl }\par
}
1 \cf0 A \par
}
15 \cf0 Cin
cf0 \fi169 {\fs11 3 }\par
}
\par
}
cf0 FA \par
}
cf0 A , \par
}
1 \cf0 4 \par
}
15 \cf0 Cin \par
}
\par
}
5 \cf0 Sum{\b \fs15 output }
{\b \fs16 Fig.}{\b \f10 8-24}{\fs17
Parallel}{\fs17 adder}{\fs16 using}{\
fs17 four}{\fs17 full}{\fs17 adders }\par
}
\cf0 Fig.{\f10 \fs15 8-25}{\b0 \fs17
Full}{\b0 \fs17 adder}{\b0 \fs17 tr
uth}{\b0 \fs17 table }\par
}
\par
}
}
}
\cf0 Binary addition problem
70 {\b\i \fs11 A8'}{\f10 \fs18
"% }
0 \fs15 -+}{\b\i \fs11 B8}{\i \fs12
B7}{\b\i \fs11
B6}{\b\i \fs11
B5
}{\b\i \fs10
B4}{\b\i \fs11
B}{\b\i \fs11 3}{\b\i \fs11
B}{\b\i \fs1
1 2}{\b\i \fs11
B}{\b\i \fs11 l }\par
}
15 \cf0 A2
cf0 {\fs14 A3 }\par
}
}
cf0 =4 \par
}
\par
}
cf0 Sum{\b0 output }\par
}
\cf0 Fig.{\f10 \fs15 8-26}{\b0 \fs16
%bit}{\b0 \fs16 parallel}{\b0 \fs16
adder }\par
}
e top 7483{\fs19 IC} is connected to the{\i \fs18 Cin} input{\fs18 of} the b
ottom unit. This handles carries from the 8s to
16s places. Other carries are handled internally in the 7483 parallel adder{\b
JCs. }
\b \f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }\par
}
cf0 8.35 \par
}
Draw a diagram of an 8-bit parallel adder by using eight FAs.
360 {\b \fs16 See}{\fs16 Fig.}{\fs17 8-27. }\par
}
\cf0 8.36{\b0 \fs18

Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 8-24.}
{\b0 \fs18 The}{\b0 \fs18 1s}{\b0 \fs18 FA}{\b0 \fs18 is}{\b0 \fs18 convert
ed}{\b0 \fs18 to}{\b0 \fs18 function}{\b0 \fs18 as}{\b0 \fs18 a }
}
by grounding the{\i \fs19 Cin} input. \par
}
cf0 8.37 \par
}
7 \cf0 The{\b \fs16 1s}{\fs16 FA}{\fs16 in}{\fs16 Fig.}{\b \fs16 8-24}{\f
s17 is}{\fs16 converted}{\fs16 to} a{\fs16 half}{\fs16 adder}{\fs16 by
}{\fs16 grounding} the{\i Cin}{\fs16 input. }
{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 8-24.}{\fs18 The}{\fs18 conducto
rs}{\fs18 leading}{\fs18 from}{\fs18 the}{\b\i \fs18 CO}{\fs18 of}{\fs18
one}{\fs18 FA}{\fs18 to}{\fs18 the}{\i \fs19 Cin}{\fs18 of}{\fs18 the}{
\fs18 next}{\fs18 FA }
s18 are}{\fs18 known}{\fs18 as}{\fs18
lines. }\par
}
.{\f10 \fs16 81 }\par
}
}
f0 187 \par
}
cf0 1 \par
}
I \par
}
cf0 Cin \par
}
\par
}
f0 1 \par
}
13 \cf0 Cin \par
}
par
}
\par
}
f0 J \par
}
cf0 - I : \par
}
cf0 Cin \par
}
cf0 Cin \par
}
cf0 MSB \par
}
8s \par
}
ig.{\b \f10 \fs16 8-27}{\fs17
8-bit}{\fs17 parallel}{\fs17 adder}{\fs17
circuit }\par
}
\cf0 Solution:
fi359 {\b0 \fs17 Conductors}{\b0 \fs17 leading}{\b0 \fs17 from}{\i \fs17 C
O}{\b0 \fs17 to}{\i \f30 \fs19 Cin}{\b0 \fs17 (Fig.}{\b0 \fs17 8-24)}{\b0 \
fs17 are}{\b0 \fs17 called}{\b0 \fs17 carry}{\b0 \fs17 lines.}{\b0 \fs17
These}{\b0 \fs17 lines}{\b0 \fs17 pass}{\b0 \fs17 carries}{\b0 \fs17 fro
m }
\b0 \fs17 one}{\fs17 FA}{\fs16 to}{\b0 \fs17 the}{\b0 \fs17 next. }\par
}
\cf0 8.38{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 8-24.
}{\b0 \fs19 When}{\b0 \fs19 0001}{\b0 \fs19 and}{\b0 \fs19 0001}{\b0 \fs19
are}{\b0 \fs19 added,}{\b0 \fs19 the}{\b0 \fs19 carry}{\b0 \fs19 line}{\b0 \
fs19 between}{\b0 \fs19 the}{\fs18 1s}{\b0 \fs19 and}{\fs19 2s}{\fs19 FAs}
{\b0 \fs19 is }
\fi1284 {\b0 \fs19 (HIGH,}{\b0 \fs19 LOW). }
cf0 \fi600 {\fs16 Solution: }
\fi958 {\b0 \fs17 Binary}{\b0 \fs17 addition}{\b0 \fs17 problem: }
\fi3960 {\b0 \fs17 0001}{\b0 \f10 \fs25 +}{\b0 \fs17 0001}{\b0\dn006 \f10 \fs1
1 =}{\b0 \fs17 0010 }
\fi592 {\b0 \fs17 When}{\b0 \fs17 0001}{\b0 \fs17 and}{\b0 \fs17 0001}{\b0
\fs17 are}{\b0 \fs17 added}{\b0 \fs17 (Fig.}{\b0 \fs17 8-24),a}{\b0 \fs17
carry}{\b0 \fs17 occurs}{\b0 \fs17 between}{\b0 \fs17 the}{\fs17 1s}{\b0 \
fs17 and}{\b0 \fs17 2s}{\b0 \fs17 place}{\b0 \fs17 and}{\b0 \fs17 that}{
\b0 \fs17 carry}{\b0 \fs17 line }
\fi589 {\b0 \fs17 will}{\b0 \fs17 be}{\b0 \fs17 HIGH. }\par
}
\cf0 8.39{\b0 \fs19
Refer}{\b0 \fs19 to}{\fs18 Fig.}{\b0 \fs19 8-24.}{\b0
\fs19 Which}{\b0 \fs19 carry}{\b0 \fs19 lines}{\b0 \fs19 are}{\fs19 HIGH}{
\b0 \fs19 when}{\b0 \fs19 binary}{\fs19 0111}{\b0 \fs19 and}{\b0 \fs19 0101
}{\b0 \fs19 are}{\b0 \fs19 added? }\par

}
\par
}
}
AP.{\fs17 8 }\par
}
\cf0 Solution:
\fi368 {\b0 See}{\b0 Fig.}{\b0 \fs17 8-28.}{\b0 When}{\b0 0111}{\b0 and}{\b
0 0101}{\b0 are}{\b0 added}{\b0 in}{\b0 the}{\b0 device}{\b0 diagrammed}
{\b0 in}{\b0 Fig.}{\b0 \fs17 8-24,}{\b0 three}{\b0 carry}{\b0 lines }
{\b0 will}{\b0 be}{\b0 HIGH.}{\b0 They}{\b0 are}{\b0 the}{\b0 carry}
{\b0 lines}{\b0 between: }
\fi380 {\b0 \fs16 1.}{\b0 \fs16
1s}{\b0 FA}{\b0 and}{\fs16 2s}{\b0 FA
}
\fi371 {\fs17 2.}{\b0 \fs17
2s}{\b0 FA}{\b0 and}{\b0 \fs17 4s}{\b0 FA
}
\fi373 {\b0 \fs17 3.}{\b0 \fs17
4s}{\b0 FA}{\b0 and}{\b0 \fs17 8s}{\b0
FA }
cf0 \fi3669 {\b0 \fs16 1:}{\b0 \fs16
l}{\b0 \fs16 y}{\b0 \fs16
1: }
\fi3647 {\b0 \fs16 O}{\b0 \fs16 i}{\b0 \fs16 l}{\b0 \fs16
i}{\b0 \fs16
l}{\b0 \fs16
i}{\b0 \fs16 l }
\fi3851 {\fs5 *}{\fs5
,}{\fs5
I }
\fi3498 {\b0 \fs16 +}{\b0 \fs16 o}{\b0 \fs16 i}{\b0 \fs16 1}{\b0 \fs16 ;
}{\b0 \fs16 0}{\b0 \fs16 ;}{\b0 \fs16 1 }
\fi3851 {\f10 \fs5 I}{\f10 \fs5
,}{\f10 \fs5
, }
fi3857 {\f10 \fs4 I}{\f10 \fs4
,}{\f10 \fs4
@ }
\fi3661 {\b0 \f10 \fs15 1}{\b0 \f10 \fs14
L1}{\b0 \f10 \fs13
LO}{\b0 \f10
\fs14
LO }
cf0 \fi2690 Fig.{\fs16 8-28}{\b0
Binary}{\b0 addition}{\b0 problem }\par
}
f0 8.40 \par
}
he block diagram in Fig.
r IC.

}
8-19, 8-24) most accurately describes the 7483 4-bit parallel \par
}
he block diagram in Fig.{\fs17 8-24} describes the{\fs17 7483} adder IC.
\par
}
f0 8.41 \par
}
efer to Fig. 8-26. What is the sum when the binary numbers 10011000 a
nd 10101111 are
d?
\fs17 Solution: }
}
\par
}
10 \fs9 \cf0 1 1 1
\par}{\phpg\posx5021\pvpg\posy8588\absw855\absh716 \sl-173 \b\i \f10 \fs9 \cf0 \
fi82 {\b0\i0 \f20 \fs16 1001}{\b0\i0 \f20 \fs16 loo0 }
\par}{\phpg\posx5021\pvpg\posy8588\absw855\absh716 \sl-216 \b\i \f10 \fs9 \cf0 \
fi82 {\b0\i0 \f20 \fs16 10101111 }
\par}{\phpg\posx5021\pvpg\posy8588\absw855\absh716 \sl-259 \b\i \f10 \fs9 \cf0 {
\b0\i0 \f20 \fs16 10100Olll }\par
}
cf0 Sum \par
}
\cf0 Fig.{\fs16 8-29}{\b0
Binary}{\b0 addition}{\b0 problem }\par
}
\cf0 8-6{\fs19
USING}{\fs19 ADDERS} FOR{\fs19 SUBTRACTION }
\fi368 {\b0 With}{\b0 minor}{\b0 changes,}{\b0 parallel}{\b0 adders}{\b0 ca
n}{\b0 be}{\b0 used}{\b0 to}{\b0 perform}{\b0 binary}{\b0 subtraction.}{\b
0 The}{\b0 4-bit}{\b0 parallel }
{\b0 adder}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-24}{\b0 can}{\b0 be}{
\b0 modified}{\b0 slightly}{\b0 to}{\b0 form}{\b0 a}{\b0 subtractor}
{\b0 circuit.}{\fs18 A}{\i \fs18 4-bit}{\i parallel }
{\i \fs18 subtractor}{\b0 circuit}{\b0 is}{\b0 diagrammed}{\b0 in}{\b0 Fig
.}{\b0 8-30.}{\b0 Note}{\b0 that}{\b0 four}{\b0 full}{\b0 adders} (FAs){\b
0 are}{\b0 used.}{\b0 Note}{\b0 also}{\b0 that }
{\b0 data}{\b0 entering}{\b0 each}{\b0 full}{\b0 adder's}{\b0\i \fs19 B}{\
b0 input}{\b0 is}{\b0 inverted.}{\b0 Finally,}{\b0 note}{\b0 that}{\b0 t
he}{\i \fs18 Cin}{\b0 input}{\b0 to}{\b0 the}{\b0 \fs18 1s}{\b0 FA}{\b0
(top }

{\b0 full}{\b0 adder}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-30)}{\b0 is}{\b0
held}{\b0 HIGH.}{\b0 The}{\b0 4-bit}{\b0 parallel}{\b0 subtractor}{\b0
circuit}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-30 }
{\b0 will}{\b0 subtract}{\b0 the}{\b0 subtrahend}{\b0\i \fs19 (B,}{\b0\i B,
}{\b0\i B,}{\b0\i \fs19 B}{\b0 \f10 \fs16 )}{\b0 from}{\b0 the}{\b0 minuen
d}{\b0 \f10 \fs16 (}{\i \f10 \fs17 A}{\i \fs19 A}{\i A}{\i A}{\b0 \fs22
1. }
\fi370 {\b0 The}{\b0 theory}{\b0 of}{\b0 operation}{\b0 of}{\b0 the}{\
b0 circuit}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-30}{\b0 is}{\b0 base
d}{\b0 on}{\b0 a}{\b0 special}{\b0 mathematical }
{\b0 technique}{\b0 outlined}{\b0 in}{\b0 Fig.}{\b0 \fs18 8-31.}{\b0 The}{\
b0 problem}{\b0 given}{\b0 in}{\b0 Fig.}{\b0 8-31}{\b0 is}{\b0 to}{\b0
subtract}{\b0 binary}{\b0 0111}{\b0 from}{\b0 1110. }
{\b0 The}{\b0 problem}{\b0 is}{\b0 solved}{\b0 across}{\b0 the}{\b0 top}
{\b0 by}{\b0 using}{\b0 traditional}{\b0 decimal}{\b0 and}{\b0 binary}
{\b0 subtraction.}{\b0 The}{\b0 three }
{\b0 steps}{\b0 below}{\b0 detail}{\b0 how}{\b0 the}{\b0 subtraction}{\b0
problem}{\b0 would}{\b0 be}{\b0 solved}{\b0 by}{\b0 using}{\b0 adders}{\b0
and}{\b0 a}{\b0 2s}{\b0 complement }
{\b0 subtrahend. }\par
}
}
cf0 BINARY ARITHMETIC{\b0 \fs17 AND} ARITHMETIC CIRCUITS \par
}
f0 189 \par
}
\cf0 Binary subtraction
fi213 {\i \fs15 A4}{\i \fs15 A3A2}{\i \fs15 A1} Minuend \par
}
\b\i \f20 \fs11 B4 }\par
}
i \par
}
3 \cf0 psJ4SJ(2sJ@J
284 {\b \f20 \fs15 Difference }
\f20 \fs16 Fig.}{\b \f20 \fs16 8-30}{\b \f20 \fs17
4-bit}{\b \f20 \fs17 sub
tractor}{\b \f20 \fs16 using}{\b \f20 \fs17 full}{\b \f20 \fs17 adders }\par
}
\cf0 Follow the steps in Fig.{\b 8-31} when solving the sample problem.

\fi356 Step{\b 1.}{\i
Change}{\i the}{\i subtrahend}{\i to}{\i its}{\i
\fs18 2s}{\i complement}{\b\i \f30 form.}Only the subtrahend must be converte
d
152 to its{\fs18 2s} complement equivalent. First the binary number{\b
0111} is changed to its{\fs19 Is }
148 complement form{\b (lOOO),} and then{\b \fs19 1} is added to form the
{\fs19 2s} complement{\b (1000}{\f10 \fs29 +}{\b 1}{\f10 \fs14 = }
160 {\b 1001). }
60 Step 2.{\i
Add}{\i the}{\i minuend}{\i \fs19 to}{\i the}{\i \fs19 2s
}{\i complement}{\i subtrahend.} The original minuend is added to the
148 {\b \fs19 2s} complement subtrahend to get a temporary result{\fs1
8 (1110}{\f10 \fs28 +}{\b 1001}{\dn006 \f10 \fs13 =}{\b 10111} in this
152 examp{\b \f10 \fs18 1}e).
60 Step{\b 3.}{\i
Discard}{\i the}{\i overjlow.} The{\b \fs19 MSB} is d
iscarded, and the remaining 4 bits are equal to the
146 binary difference. In this example the difference is binary{\b 0111. }
\fi356 The reason why the circuit shown in Fig.{\b 8-30}will work as a subtract
or can now be explained. The
\par}{\phpg\posx859\pvpg\posy9599\absw9439\absh3665 \sl-234 \f20 \fs18 \cf0 four
inverters change the binary subtrahend to its{\fs19 Is} complement form
(each{\b 1} is changed to{\fs19 0} and
{\fs18 0} to{\b 1).} The{\fs18 HIGH} at the{\i Cin} input to the{\fs18
1s} FA is the same as adding{\f10 \fs30 +} 1 to the subtrahend.
minuend and{\fs19 2s} complement subtrahend are added. The{\b\i \fs19 CO} term
inal{\fs18 of} the{\fs18 8s} FA{\fs18 is} the{\i overjlow }
ut. The{\b\i \f30 \fs20 CO} output which discards the overflow is not displayed
. \par
}
\par
}
}
AP.{\fs17 8 }\par
}
{\phpg\posx1737\pvpg\posy1865\absw721\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Pr
oblem: \par
}
cimal
7 {\fs16 14 }
fi152 {\f10 \fs10 __ }

2 {\fs16 -7 }
2 {\b \fs16 7 }\par
}
inary
98 {\fs16 1110}{\fs16
Minuend }\par
}
}
111
Subtrahend \par
}
{\phpg\posx3951\pvpg\posy2027\absw710\absh267 \f10 \fs8 \cf0 \f10 \fs8 \cf0 -__\par}{\phpg\posx3951\pvpg\posy2027\absw710\absh267 \sl-169 \f10 \fs8 \cf0 \fi267
{\f20 \fs16 01}{\b \fs15 1}{\f20 \fs16 1 }\par
}
fference \par
}
- \par
}
cf0 Form \par
}
s16 \cf0 Add{\b0\i0 \fs16 minuend}{\b0\i0 \fs16 to}{\b0\i0 \fs16 2s}{\b0\i0
\fs16 complement}{\b0\i0 \fs16 subtrahend. }\par
}
1 \par
}
110
Minuend \par
}
4 \cf0 +{\f20 \fs16
1001}{\fs15
2s}{\f20 \fs16 complement}{\f20 \fs16 s
ubtrahend }
453 {\f20 \fs16 10111 }
{\b\i \f20 \fs16 Discard}{\f20 \fs16 overflow.}{\f20 \fs16 The}{\f20 \fs16 d
ifference}{\f20 \fs16 is}{\f20 \fs16 0111}{\f20 \fs16 in}{\f20 \fs16 this}{\
f20 \fs16 example. }\par
}
\par
}
\cf0 1110
Minuend
{\f10 \fs13 _____ }\par
}
001{\fs16
2s} complement subtrahend \par
}
{\phpg\posx1759\pvpg\posy2699\absw629\absh237 \f20 \fs16 \cf0 \f20 \fs16 \cf0 St
ep{\i \f30 \fs23 0 }\par
}
\cf0 (a) Traditional decimal and binary subtraction
{\b\i \fs16 Change}{\b\i \fs16 subtrahend}{\fs16 to}{\fs16 2s}{\fs16 comple
ment}{\fs16 form. }\par
}
nary
fi62 {\b \f30 \fs15 0111 }\par
}
\cf0 Is{\b0 \fs14 complement }
f0 \fi333 {\b0 \fs16 1000 }\par
}
cf0 Add{\f10 \fs12 1 }\par
}
s{\fs14 complement }
\fi350 {\fs16 1001 }\par
}
ep{\i \f30 \fs23 0 }\par
}
ep{\i \f30 \fs22 0 }\par
}
8 \cf0 @{\f20 \fs16 0111}{\f20 \fs16
Difference }
406 {\f20 \fs14 Discard}{\fs28 / }
398 {\f20 \fs14 overflow }
\fi1800 {\f20 \fs14 (h)}{\f20 \fs14 Special}{\f20 \fs14 technique}{\f20 \fs14
subtraction}{\f20 \fs14 using}{\f20 \fs14 2s}{\f20 \fs14 complement}{\f20
\fs14 subtrahend}{\f20 \fs14 and}{\f20 \fs14 addition }
\fi4084 {\b \f20 \fs16 Fig.}{\b \f20 \fs16 8-31 }
\fi362 {\f20 \fs18 If}{\f20 \fs18 the}{\f20 \fs18 4-bit}{\f20 \fs18 parallel}
{\f20 \fs18 adder}{\f20 \fs18 and}{\f20 \fs18 subtractor}{\f20 \fs18 circuit
s}{\f20 \fs18 from}{\f20 \fs18 Figs.}{\f20 \fs18 8-24}{\f20 \fs18 and}{\f20
\fs18 8-30}{\f20 \fs18 are}{\f20 \fs18 compared,}{\f20 \fs18 they}{\f20 \fs1
8 are }
0 \fs18 seen}{\f20 \fs18 to}{\f20 \fs18 be}{\f20 \fs18 almost}{\f20 \fs18 id
entical.}{\f20 \fs18 These}{\f20 \fs18 circuits}{\f20 \fs18 can}{\f20 \fs18
be}{\f20 \fs18 combined}{\f20 \fs18 to}{\f20 \fs18 form}{\f20 \fs18 an}{\f20
\fs18 adder/subtractor}{\f20 \fs18 circuit.}{\f20 \fs18 Such }
0 \fs18 a}{\f20 \fs18 circuit}{\f20 \fs18 is}{\f20 \fs18 diagrammed}{\f20 \fs
18 in}{\f20 \fs18 Fig.}{\f20 \fs18 8-32. }

59 {\f20 \fs18 The}{\f20 \fs18 4-bit}{\f20 \fs18 parallel}{\f20 \fs18 adder/
subtractor}{\f20 \fs18 circuit}{\f20 \fs18 shown}{\f20 \fs18 in}{\f20 \fs18
Fig.}{\f20 \fs18 8-32}{\f20 \fs18 has}{\f20 \fs18 an}{\f20 \fs18 additi
onal}{\f20 \fs18 input}{\f20 \fs18 called}{\f20 \fs18 the }
0 \fs18 mode}{\f20 \fs18 control.}{\f20 \fs18 If}{\f20 \fs18 the}{\f20 \fs18
mode}{\f20 \fs18 control}{\f20 \fs18 input}{\f20 \fs18 is}{\f20 \fs18 LOW}{
\f20 \fs18 (logical}{\f20 O),}{\f20 \fs18 the}{\f20 \fs18 four}{\f20 \fs19
XOK}{\f20 \fs18 gates}{\f20 \fs18 have}{\f20 \fs18 no}{\f20 \fs18 effect}{\
f20 \fs18 on}{\f20 \fs18 the }
0 \fs18 data}{\f20 \fs18 at}{\f20 \fs18 the}{\i \f20 \fs19 B}{\f20 \fs18 in
puts}{\f20 \fs18 (data}{\f20 \fs18 passes}{\f20 \fs18 through}{\f20 \fs18 t
he}{\f20 \fs18 XORs}{\f20 \fs18 and}{\f20 \fs18 is}{\f20 \fs18 not}{\f20 \fs
18 inverted).}{\f20 \fs18 The}{\i \f20 \fs18 Cin}{\f20 \fs18 input}{\f20 \fs
18 to}{\f20 \fs18 the}{\f20 \fs18 1s}{\f20 \fs18 FA }
0 \fs18 is}{\f20 \fs18 held}{\f20 \fs18 LOW,}{\f20 \fs18 which}{\f20 \fs18
makes}{\f20 \fs18 the}{\f20 \fs18 FA}{\f20 \fs18 function}{\f20 \fs18 a
s}{\f20 \fs18 a}{\f20 \fs18 half}{\f20 \fs18 adder.}{\b \f20 \fs18 A}{\f2
0 \fs18 4-bit}{\f20 \fs18 sum}{\f20 \fs18 will}{\f20 \fs18 appear}{\f20 \f
s18 at}{\f20 \fs18 the}{\f20 \fs18 output }
0 \fs18 indicators}{\f20 \fs18 at}{\f20 \fs18 the}{\f20 \fs18 lower}{\f20 \fs
18 right. }
61 {\f20 \fs18 When}{\f20 \fs18 the}{\f20 \fs18 mode}{\f20 \fs18 control}{\
f20 \fs18 of}{\f20 \fs18 the}{\f20 \fs18 adder/subtractor}{\f20 \fs18 ci
rcuit}{\f20 \fs18 shown}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20 \fs18 8-32}{
\f20 \fs18 is}{\f20 \fs19 HIGH}{\f20 \fs18 (logical}{\f20 \fs19 I), }
0 \fs18 the}{\f20 \fs18 four}{\f20 \fs19 XOR}{\f20 \fs18 gates}{\f20 \fs18 a
ct}{\f20 \fs18 as}{\f20 \fs18 inverters.}{\f20 \fs18 The}{\f20 \fs18 subtrah
end}{\i \f20 \fs18 (B,B,B,B,)}{\f20 \fs18
is}{\f20 \fs18 inverted.}{\f20 \f
s18 The}{\i \f20 \fs18 Cin}{\f20 \fs18 input}{\f20 \fs18 to}{\f20 \fs18 the
}{\f20 \fs18 1s }
0 \fs18 FA}{\b \f20 \fs18 is}{\f20 \fs19 HIGH}{\f20 \fs18 which}{\f20 \fs18
is}{\f20 \fs18 like}{\f20 \fs18 adding}{\fs29 +}{\f20 \fs18 1}{\f20 \fs18 t
o}{\f20 \fs18 the}{\f20 \fs18 1s}{\f20 \fs18 complement}{\f20 \fs18 subtrah
end.}{\f20 \fs18 The}{\f20 \fs18 difference}{\f20 \fs18 will}{\f20 \fs18 app
ear}{\f20 \fs18 at }
0 \fs18 the}{\f20 \fs18 lower}{\f20 \fs18 right}{\f20 \fs18 in}{\f20 \fs18 F
ig.}{\f20 \fs18 8-32}{\f20 \fs18 in}{\f20 \fs18 binary}{\f20 \fs18 form. }
{\fs16 SOLVED}{\fs16 PROBLEMS }\par
}
cf0 8.42 \par
}
List three modifications that must be made to convert the 4-bit adder shown
in Fig. 8-24 to{\fs18 a }
\par}{\phpg\posx1463\pvpg\posy11353\absw8347\absh1358 \sl-238 \f20 \fs18 \cf0 4bit parallel subtractor.

i367 {\fs16 See}{\fs16 Fig.}{\b \fs16 8-30}{\fs16 for}{\fs16 the}{\fs16
solution.}{\fs16 The}{\fs16 modifications}{\fs16 to}{\fs16 the}{\fs16
adder}{\fs16 shown}{\fs16 in}{\fs16 Fig.}{\b \fs16 8-24}{\fs16 are}{\fs1
6 (1)}{\fs16 adding}{\fs16 four }
fs16 inverters,}{\fs16 (2)}{\fs16 connecting}{\i \fs16 Cin}{\fs16 input}{
\fs16 of}{\fs16 the}{\b \fs16 1s}{\fs16 FA}{\fs16 to}{\fs16 HIGH,}{\fs
16 and}{\fs16 (3)}{\fs16 leaving}{\fs16 the}{\b\i \fs16 CO}{\fs16 output
}{\fs16 from}{\fs16 the}{\fs17 8s}{\b \fs17 FA }
fs16 disconnected. }\par
}
\cf0 8.43{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 8-32.}{\b0 The}{\b0 \fs19 XO
R}{\b0 gates}{\b0 act}{\b0 \fs18 as}{\b0 inverters}{\b0 when}{\b0 the}{\b
0 mode}{\b0 control}{\b0 is }
}
\par
}
The XOR gates in Fig. 8-32 act as inverters when the mode control is HI
GH (subtract mode). \par
}
0 CHAP.{\b0 \fs17 81 }\par
}
cf0 BINARY ARITHMETICAND ARITHMETICCIRCUITS \par
}
\par
}
\cf0 Addition/subtraction
fi304 {\fs11 A4}{\fs12
A3}{\i \fs15 A2}{\fs15 A1 }\par
}
cf0 Cin \par
}
{\phpg\posx6903\pvpg\posy2142\absw193\absh242 \f10 \fs20 \cf0 \f10 \fs20 \cf0 z:
\par
}
par
}
A{\b \f20 \fs11 B} 1l \par
}
\par
}
{\phpg\posx3891\pvpg\posy7524\absw695\absh871 \f10 \fs73 \cf0 \f10 \fs73 \cf0 J
\par
}
cf0 B \par
}
ig.{\b \f30 \fs17 8-32}{\fs16 4-bit}{\fs16 adder/subtractor}{\fs16
circu
it }\par
}
efer to Fig.{\fs19 8-32.} This circuit acts as a 4-bit parallel
\par}{\phpg\posx1461\pvpg\posy9320\absw4762\absh723 \sl-239 \f20 \fs18 \cf0 LOW.
}
hen the mode control input is \par
}
f0 4 \par
}
cf0 w \par
}
\b \f20 \fs15 1deSubtractcontrol }
2 {\b \f20 \fs15 Add}{\fs13 =}{\fs15 0 }\par
}
\fs15 \cf0 Sum or
fs15 difference }\par
}
f0 8.44 \par
}
cf0 8.45 \par
}
cf0 8.46 \par
}
16 \cf0 The circuit shown in{\fs16 Fig.} 8-32 acts as a 4-bit paralle
l adder when the mode control input is{\fs17 LOW. }
0 {\fs18 Use}{\fs19 the}{\fs18 special}{\fs18 technique}{\fs18 shown}{\fs1
8 in}{\fs18 Fig.}{\fs18 8-31}{\fs18 to}{\fs18 subtract}{\fs18 binary}{\fs1
8 0110}{\fs18 from}{\fs18 1111. }
0 {\b Solution: }
i360 See Fig.{\fs17 8-33. }
0 \fi22 {\fs18 Draw}{\fs18 a}{\fs18 diagram}{\fs18 of}{\fs18 a}{\fs18 4-bit
}{\fs18 parallel}{\fs18 subtractor}{\fs18 circuit}{\fs17 by}{\fs18 using}{
\fs18 a}{\fs19 7483}{\fs18 4-bit}{\fs18 parallel}{\fs18 adder}{\fs19 IC}{\
fs18 and }
fs18 four}{\fs18 inverters. }

0 {\b Solution: }
i374 See{\fs16 Fig.} 8-34. \par
}
Refer to Fig. 8-30. When binary 0101 is subtracted from 1100, the difference is
\fs16 Solution: }
350 {\fs16 When}{\fs16 binary}{\fs16 0101}{\fs16 is}{\fs16 subtracted}{\fs
17 from}{\f10 \fs16 1100,}{\fs16 the}{\fs16 difference}{\fs16 is}{\fs16
011}{\b \f10 \fs15 1}{\fs16 (decimal}{\fs16 12}{\f10 \fs15 -}{\fs17 5}{\f
10 \fs13 =}{\i \f10 \fs16 7). }\par
}
\par
}
cf0 8.47 \par
}
0 192 \par
}
}
AP. 8 \par
}
- \par
}
ep{\i \f30 \fs22 0 }\par
}
nary
fi44 {\b \f30 \fs17 0110 }\par
}
{\fs15 s}{\fs15 complement }\par
}
cf0 1001 \par
}
cf0 Form \par
}
\fs14 \cf0 Add{\f10 \fs13 1 }
b0 \f10 \fs8 ___) }\par
}
s{\fs15 complement }
47 {\b \f30 \fs17 1010 }\par
}
0 1 1 \par
}
\fs17 \cf0 1111
0 {\b0 \f10 \fs10 ___-- }
i30 {\b0 \f10 \fs26 +} 1010
i190 {\fs18 11001 }\par
}
cf0 1111 \par
}
nuend \par
}
{\b \f30 \fs17 1010}{\f20 \fs17
2s}{\f20 \fs17 complement}{\f20 \fs17 sub
trahend }
60 {\b \f30 \fs17 100}{\b \f30 \fs17 1 }\par
}
fference \par
}
cf0 Discard
\par}{\phpg\posx4601\pvpg\posy4814\absw660\absh336 \sl-183 \f20 \fs15 \cf0 overf
low \par
}
\cf0 Fig. 8-33{\b0
Special}{\b0 technique}{\b0 for}{\b0 subtraction }
f0 \fi1596 {\i \f10 \fs14 +5}{\b0 \fs23 v }\par
}
cf0 A1 \par
}
s43 \cf0 B l l > o - \par
}
\cf0 A2
f0 {\i \fs15 B2 }
f0 {\fs15 A3- }
f0 {\i \fs15 B3 }
f0 {\fs12 A4 }
f0 {\fs11 8}{\fs11 4 }\par
}

0 ::E \par
}
cf0 = 3 \par
}
\par
}
10 \cf0 C O \par
}
{\phpg\posx3267\pvpg\posy10174\absw6026\absh1399 \f20 \fs15 \cf0 \fi4198 \f20 \f
s15 \cf0 Difference
0 \fi4155 {\b\i \fs11 A}{\b\i \fs11 4}{\b\i \fs11 A}{\b\i \fs11 3}{\b\i \fs11
A}{\b\i \fs11 2}{\b\i \fs11 A}{\b\i \fs11 1 }
i3967 {\f10 \fs11 -}{\b \fs11 B4}{\b\i \fs11 B}{\b\i \fs11 3}{\b\i \fs11
B}{\b\i \fs11 2}{\i \fs10 Bl }
0 \fi693 {\b \fs17 Fig.}{\b \fs17 8-34}{\fs17
4-bit}{\fs17 parallel}{\fs17
subtractor}{\fs17 circuit }
0 {\b \f10 \fs11 i}{\b \f10 \fs11 c}{\b \f10 \fs11 t}{\b \fs14 the}{\b\i \fs
15
R}{\b \fs14
inniitc}{\b \fs14 tn}{\b \fs14 the}{\b \fs14 fniir}{\
b \fs17 FAs}{\b \fs16 when}{\b \fs17 0101}{\b \f30 \fs17 is}{\fs17 subtra
cted}{\fs18 from}{\fs18 1100. }\par
}
cf0 LSB \par
}
puts \par
}
cf0 MSB \par
}
s20 \cf0 4
\cf0 {\fs11 Bl }
\cf0 {\fs15 A2 }
\cf0 {\fs15 B2 }
\cf0 {\f10 \fs13 A3 }
\cf0 {\fs15 B3 }
\cf0 {\i0 \fs11 A4 }
\cf0 {\i0 \f30 \fs11 B4 }\par
}
cf0 4-bit
5 parallel }
{\fs15 adder }\par

}
cf0 (7483) \par
}
cf0 P AP \par
}
\cf0 Refer{\i \f10 \fs10 tn}{\f30 \fs16 Fio}{\f10 \fs18 8-?n}{\f10 T }
cf0 {\fs17 Solution: }\par
}
cf0 8.49 \par
}
17 \cf0 The{\b \fs16 1s} complement of the subtrahend will appear at th
e{\b\i \fs16 B} inputs to the FAs shown in Fig. 8-30.{\b \fs16 If }
\par}{\phpg\posx1445\pvpg\posy12165\absw8252\absh1577 \sl-210 \f20 \fs17 \cf0 th
e subtrahend equals 0101, the{\fs17 Is} complement{\fs17 of} the subtra
hend will be 1010.
0 {\fs18 Refer}{\fs17 to}{\b \fs18 Fig.}{\fs19 8-30.}{\fs18 When}{\fs18 01
01}{\fs18 is}{\fs17 subtracted}{\fs18 from}{\fs18 1100,}{\fs18 which}{\fs1
8 carry}{\fs18 lines}{\fs18 will}{\fs17 be}{\fs18 HIGH? }
b Solution: }
i362 The FAs add 1100 (minuend) to 1011{\fs17 (2s} complement subtrahend),
which means{\fs16 a} carry occurs only
\par}{\phpg\posx1445\pvpg\posy12165\absw8252\absh1577 \sl-215 \f20 \fs17 \cf0 at
{\b\i \fs17 CO}{\fs17 of} the 8s FA.{\fs17 All} the carry lines in Fi
g. 8-30 will be LOW in this operation. \par
}
.{\fs17 81 }\par
}
}
\par
}
\cf0 8-7{\fs18
2s}{\f20 \fs19 COMPLEMENT}{\f20 \fs19 ADDITION}{\f20 \fs18
AND}{\f20 \fs19 SUBTRACTION }
fi374 {\b0 \f20 \fs19 The}{\b0 \f20 \fs19 2s}{\b0 \f20 \fs19 complement}{\b0
\f20 \fs19 method}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 representing}{\b0 \f
20 \fs19 numbers}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 widely}{\b0 \f20 \fs19
used}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 microprocessors.}{\b0 \f20 \fs19
Until }
\b0 \f20 \fs19 now,}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 numbers}{\b0 \f20 \f
s19 added}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19 subtracted}{\b0 \f20 \fs19 w
ere}{\b0 \f20 \fs19 positive}{\b0 \f20 \fs19 numbers.}{\b0 \f20 \fs19 Howe
ver,}{\b0 \f20 \fs19 microprocessors}{\b0 \f20 \fs19 must}{\b0 \f20 \fs19 ad
d }
\b0 \f20 \fs19 and}{\b0 \f20 \fs19 subtract}{\b0 \f20 \fs19 both}{\b0 \f20 \f
s19 positive}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 negative}{\b0 \f20 \fs19
numbers.}{\b0 \f20 \fs19 Using}{\b0 \f20 \fs19 2s}{\b0 \f20 \fs19 complemen
t}{\b0 \f20 \fs19 numbers}{\b0 \f20 \fs19 makes}{\b0 \f20 \fs19 adding}{\b
0 \f20 \fs19 and }
\b0 \f20 \fs19 subtracting}{\b0 \f20 \fs19 signed}{\b0 \f20 \fs19 numbers}{\b0
\f20 \fs19 possible.}{\f20 \fs18 A}{\b0 \f20 \fs19 review}{\b0 \f20 \fs18 o
f}{\b0 \f20 \fs18 2s}{\b0 \f20 \fs19 complement}{\b0 \f20 \fs19 numbers}{\b0
\f20 \fs19 and}{\b0 \f20 \fs19 their}{\b0 \f20 \fs19 use}{\b0 \f20 \fs19 in}
{\b0 \f20 \fs19 represent- }
fi21 {\b0 \f20 \fs19 ing}{\b0 \f20 \fs19 positive}{\b0 \f20 \fs19 and}{\b0 \f2
0 \fs19 negative}{\b0 \f20 \fs19 values}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19
given}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Sec.}{\b0 \f20 \fs18 1-4. }
f0 \fi948 {\b0 \f20 \fs15 Addition}{\b0 \f20 \fs15 or}{\b0 \f20 \fs15 subtract
ion }
fi1490 {\b0 \f20 \fs15 problem }\par
}
s15 \cf0 A8{\fs15 A}{\fs15 ,}{\fs15 A}{\fs15 ,}{\fs15 A5A4}{\fs15 A}
A A \par
}
1 \par
}
s15 \cf0 B5{\fs15 B4} B3 B2 B , \par
}
{\phpg\posx3697\pvpg\posy3515\absw146\absh440 \f10 \fs37 \cf0 \f10 \fs37 \cf0 ]
\par
}
\cf0 2s{\b0 \fs15 complement}{\b0 \fs15 numbers }\par
}
\par
}
15 \cf0 Cin{\b0\i0 \f10 \fs28 L }
\fi367 A \par
}
\par
}
}
{\phpg\posx3999\pvpg\posy9954\absw52\absh65 \f10 \fs5 \cf0 \f10 \fs5 \cf0 I. \pa
r
}
s11 \cf0 B6 \par
}
{\phpg\posx5741\pvpg\posy9658\absw245\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 FA
\par
}
\par}{\phpg\posx4357\pvpg\posy9787\absw76\absh537 \sl-130 \par\par\f10 \fs17 \cf
0 {\b\i \fs9 I }\par
}
O@@L \par
}
\cf0 Sign
fi45 {\b0 bit }\par
}
2s{\f20 \fs15 complement}{\f20 \fs15 sum }
616 {\f20 \fs16 or }
332 {\f20 \fs15 difference }\par
}
\cf0 Mode{\b0 \fs15 control }
fi79 {\b0 \fs15 Subtract}{\b0 \f10 \fs14 =}{\b0 \fs16 I }
fi385 {\fs15 Add}{\b0 \f10 \fs14 =}{\b0 \f10 \fs14 0 }\par
}
Fig.{\b \f30 \fs17 8-35}{\fs16 8-bit}{\fs16 parallel}{\fs16 adder/subtract
or}{\fs16
circuit }\par
}
\par
}
}
AP. 8 \par
}
\fs18 \cf0 A{\b0 circuit}{\b0 for}{\b0 adding}{\b0 and}{\b0 subtracting}{\
b0 signed}{\b0 numbers}{\b0 in}{\b0 \fs19 2s}{\b0 complement}{\b0 notatio
n}{\b0 is}{\b0 diagrammed}{\b0 in }
\b0 Fig.}{\b0 8-35.}{\b0 This}{\b0 is}{\b0 an}{\b0 8-bit}{\b0 paralle
l}{\b0 adder/subtractor}{\b0 that}{\b0 will}{\b0 add}{\b0 or}{\b0 su
btract}{\b0 signed}{\b0 numbers.}{\i \fs19 All }
\b0\i inputs}{\b0\i \fs19 and}{\b0\i outputs}{\i are}{\b0\i \fs19 in}{\b0\i
2s}{\b0\i complement}{\i \f30 \fs18 form. }
fi365 {\b0 Note}{\b0 that}{\b0 the}{\b0 8-bit}{\b0 2s}{\b0 complement}{\b0
adder/subtractor}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-35}{\b0 is}{\b0 an}
{\b0 extension}{\b0 \fs19 of}{\b0 the}{\b0 4-bit }
\b0 adder/subtractor}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-32.}{\b0 \fs19 If
}{\b0 the}{\b0 mode}{\b0 control}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-35}{

\b0 is}{\b0 \fs19 LOW,}{\b0 the}{\b0 circuit}{\b0 adds. }
\b0 However,}{\b0 if}{\b0 the}{\b0 mode}{\b0 control}{\b0 is}{\b0 \fs19 H
IGH,}{\b0 the}{\b0 circuit}{\b0 performs}{\b0 as}{\b0 an}{\b0 8-bit}{\b0
parallel}{\b0 subtractor. }
fi369 {\b0 Four}{\b0 examples}{\b0 of}{\b0 adding}{\b0 \fs19 2s}{\b0 compl
ement}{\b0 numbers}{\b0 are}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 8-36.}{\b
0 Two}{\b0 positive}{\b0 numbers }
\b0 are}{\b0 shown}{\b0 added}{\b0 in}{\b0 Fig.}{\b0 8-36a.}{\b0 2s}{
\b0 complement}{\b0 addition} looks{\b0 exactly}{\b0 like}{\b0 binary
}{\b0 addition}{\b0 when }
\b0 positive}{\b0 numbers}{\b0 are}{\b0 being}{\b0 added.}{\b0 The}{\fs19
MSB}{\b0 is}{\b0 \fs18 0}{\b0 in}{\b0 all}{\b0 three}{\b0 2s}{\b0 comp
lement}{\b0 numbers}{\b0 in}{\b0 \fs18 Fig.}{\b0 8-36a; }
\b0 therefore,}{\b0 all}{\b0 of}{\b0 them}{\b0 are}{\b0 positive.}{\b0 N
ote}{\b0 that}{\b0 the}{\b0 rules}{\b0 \fs18 of}{\b0 binary}{\b0 additi
on}{\b0 are}{\b0 used. }\par
}
cf0 1 1 \par
}
f0 1 \par
}
\cf0 ({\fs21 +}{\f20 \fs17 27) }
5 +(}{\fs27 +}{\f20 \fs17 10) }
7 {\b\i \f30 \fs17 +37io }\par
}
001 1011{\fs17
2s}{\fs16 complement}{\fs16 augend }\par
}
\cf0 +{\f20 \fs16 0000}{\f20 \fs17 1010}{\f20 \fs16
2s}{\f20 \fs16 comp
lement}{\f20 \fs16 addend }
63 {\fs15 0010}{\fs16 0107}{\f20 \fs17
2s}{\f20 \fs16 complement}{\f20 \
fs16 sum }
{\f20 \fs14 (a)}{\f20 \fs15 Adding}{\f20 \fs15 two}{\f20 \fs15 positive}{\f2
0 \fs15 numbers }\par
}
\fs10 \cf0 1 1 1 1 1 1 1 1
fi357 {\f10 \fs15 1}{\b0 \f20 \fs17 1}{\b0 \f20 \fs17 11}{\b0 \f20 \fs17 1}{\f
10 \fs15
1}{\f10 \fs15 1}{\f10 \fs15 1}{\b0 \f20 \fs16
2s}{\b0 \f20 \fs1
6 complement}{\b0 \f20 \fs16 augend }
fi93 {\b0 \f10 \fs25 +}{\b0 \f20 \fs17
1111}{\b0 \f20 \fs17 1101}{\b0 \f20 \
fs16
2scomplementaddend }
\f20 \fs26 ,JB}{\b0 \f20 \fs17 11111100}{\b0 \f20 \fs16
2s}{\b0 \f20 \fs16
complement}{\b0 \f20 \fs16 sum }\par

}
cf0 J \par
}
iscard
\fi442 (h) Adding two negative numbers \par
}
\cf0 (-{\b \fs15
1) }
\fs10 ____ }
{\b \f20 \fs16 +(-3) }
fi264 {\b \f30 \fs10 -}{\b \f30 \fs10 4}{\b \f30 \fs10 1}{\b \f30 \fs10 0 }\par
}
cf0 1 1 \par
}
f0 1 \par
}
\cf0 ({\fs20 +}{\fs15 20) }
\fs10 ______ }
{\fs26 +}{\dn006 \fs15 -(}{\fs15 }{\f20 \fs17
50) }
0 {\b \f30 \fs17 -3010 }\par
}
\cf0 0001{\f10 \fs15 0100}{\fs16
2s}{\fs16 complement}{\fs16 augend }
{\f10 \fs10 _}{\f10 \fs10 _}{\f10 \fs10 _}{\f10 \fs10 _}{\f10 \fs10 _}{\
f10 \fs10 _}{\f10 \fs10 ~}{\f10 \fs10 _ }
3 {\f10 \fs26 +} 1100 1{\fs16 1}10
2s{\fs16 complement}{\fs16 addend }
92 1110{\b \f30 \fs17 0010}{\fs16
2s}{\fs16 complement}{\fs16 sum }\par
}
s12 \cf0 ( c ){\b0\i0 \f20 \fs15 Adding}{\b0\i0 \f20 \fs15 a}{\b0\i0 \f20 \fs
15 smaller}{\b0\i0 \f20 \fs15 positive}{\b0\i0 \f20 \fs15 to}{\b0\i0 \f20 \fs
15 a}{\b0\i0 \f20 \fs15 larger}{\b0\i0 \f20 \fs15 negative}{\b0\i0 \f20 \fs15
number }
s12 \cf0 \fi1493 {\i0 \f30 \fs10 1}{\i0 \f30 \fs10 1}{\i0 \f30 \fs10 1 }\par
}
\cf0 ({\fs22 +}{\b \fs15 40) }
5 +(}{\fs15 -}{\f20 \fs17 13) }\par
}
\cf0 0010 loo0
2s{\fs16 complement}{\fs16 augend }
0 \fs26 +} 11110011
2s{\fs16 complement}{\fs16 addend }
\fi1180 {\fs16 2s}{\fs16 complement}{\fs16 sum }\par
}
i \f10 \fs12 \cf0 d
\par}{\phpg\posx3299\pvpg\posy10480\absw3969\absh1001 \sl-150 \b\i \f10 \fs12 \c
f0 \fi656 {\b0\i0 \f20 \fs15 Discard }
2 \cf0 {\b0\i0 \f20 \fs14 (d)}{\b0\i0 \f20 \fs15 Adding}{\b0\i0 \f20 \fs14 a}
{\b0\i0 \f20 \fs15 larger}{\b0\i0 \f20 \fs15 positive}{\b0\i0 \f20 \fs15 to}{
\b0\i0 \f20 \fs15 a}{\b0\i0 \f20 \fs15 smaller}{\b0\i0 \f20 \fs15 negative}{\
b0\i0 \f20 \fs15 number }
2 \cf0 \fi600 {\i0 \f20 \fs16 Fig.}{\i0 \f20 \fs16 8-36}{\b0\i0 \f20 \fs17
2
s}{\b0\i0 \f20 \fs16 complement}{\b0\i0 \f20 \fs16 addition }\par
}
8 \cf0 The second example{\fs19 of}{\fs19 2s} complement addition is detaile
d in Fig. 8-36b. Two negative numbers
being added. The{\b \fs19 MSB}{\fs18 of} a negative 2s complement n
umber is a{\fs18 1.} In this example the{\fs19 2s }
\par}{\phpg\posx853\pvpg\posy12042\absw9217\absh1506 \sl-230 \f20 \fs18 \cf0 com
plement 11111111is added{\fs18 to} 11111101to get 111111100. The overflow{\fs
19 (MSB)}{\fs18 of} the temporary
\par}{\phpg\posx853\pvpg\posy12042\absw9217\absh1506 \sl-232 \f20 \fs18 \cf0 sum
is discarded, leaving a{\fs19 2s} complement{\fs19
sum} of 1111110
0, Discarding the overflow{\fs18 is} done
\par}{\phpg\posx853\pvpg\posy12042\absw9217\absh1506 \sl-242 \f20 \fs18 \cf0 aut
omatically in a digital system because the register used in this example is on
ly 8 bits wide.
357 {\b A} third example of{\fs19 2s} complement addition is given in Fig. 8-36
c.{\b \fs19 A} positive number{\fs19 is} added to a
\par}{\phpg\posx853\pvpg\posy12042\absw9217\absh1506 \sl-251 \f20 \fs18 \cf0 lar
ger negative number (OOOlOlOO{\f10 \fs27 +} 11001110).The{\fs19 sum} is 1110001
0,or{\fs19 a} -30 in decimal. The fourth \par
}
0 CHAP.{\b0 \fs16 81 }\par
}
cf0 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS \par
}
f0 195 \par
}
xample adds a positive number to a smaller negative number. When{\b \fs19 00101
000} is added to{\b \fs19 11110011, }
result is 1{\b \fs19 0001101}1. The overflow{\fs19 (MSB)}{\fs19 is} discarded
, leaving the sum{\fs19 of} 0001{\b \fs19 101}{\b 1. }
64 Four examples of{\i \fs19 2s} complement subtraction are shown in Fi
g.{\i \fs19 8-37.} Two positive numbers are
\par}{\phpg\posx855\pvpg\posy1351\absw9487\absh1498 \sl-242 \f20 \fs18 \cf0 subt
racted in Fig.{\i \fs19 8-37a.} The{\i \fs19 +41} is converted to its{\fs19

2s} complement form{\fs19 (00101001),} and then it is{\fs19 2s }
lemented again to get a subtrahend{\fs19 of}{\b \fs19 11010111.} The minuen
d and subtrahend are then{\i \fs19 added }
\par}{\phpg\posx855\pvpg\posy1351\absw9487\absh1498 \sl-242 \f20 \fs18 \cf0 to g
et 1{\fs19 00100010.} The overflow{\b \fs19 (MSB)} is discarded, leaving a{\fs
19 2s}{\i \fs19 complement}{\i \fs19 difference}{\b of}{\b \fs19 00100010,}
or
5 {\i \fs19 +34} in decimal. \par
}
\cf0 (+{\b 75) }
\par}{\phpg\posx2067\pvpg\posy3614\absw628\absh355 \sl-188 \f10 \fs15 \cf0 -({\b
\f20 \fs17 +41) }\par
}
\cf0 Form{\fs13 2s} complement \par
}
f0 b \par
}
cf0 ,a \par
}
\fs15 \cf0 Discard
f0 {\i \fs14 (a)} Subtracting two positive numbers
5 \cf0 \fi1919 {\f10 \fs9 1}{\f10 \fs9 1 }\par
}
\cf0 Form{\fs14 2s} complement
f0 \fi460 and add \par
}
\fs17 \cf0 1011o000
Minuend
\b0 \f10 \fs26 +} Oool 1110
Subtrahend
fi252 1100 1110{\fs16
2s} complement difference \par
}
cf0 and add \par
}
\fs17 \cf0 0100 1011
Minuend
\b0 \f10 \fs27 +} 1101 0111
Subtrahend
fi237 00100010{\b0 \fs16
}
{\phpg\posx5603\pvpg\posy4000\absw604\absh85 \f10 \fs6 \cf0 \f10 \fs6 \cf0 _-__.
\par
}
cf0 0010 1001 \par
}
\cf0 ({\dn006 \fs11 -}{\f20 \fs16 80) }
f20 \fs16 -(-30) }\par
}
cf0 11100010 \par
}
s15 \cf0 (b){\i0 \fs15 Subtracting}{\i0 \fs15 two}{\i0 \fs15 negative}{\i0 \f
s15 numbers }
\cf0 \fi2001 {\i0 \f10 \fs9 1 }\par
}
\cf0 Form{\fs13 2s} complement \par
}
f0 b \par
}
cf0 andadd \par
}
\fs17 \cf0 o0o11000
Minuend
f0 {\b0 \f10 \fs15 _______ }\par
}
\par
}
\cf0 o0o10100
Subtrahend
010 1100{\fs16
}
\cf0 ({\fs20 +}{\b \f20 \fs16 24) }
f20 \fs17 -(-20) }
0 {\b \f20 \fs16 +44m }\par
}
cf0 1110 1100 \par
}
{\phpg\posx3649\pvpg\posy7397\absw171\absh156 \f10 \fs13 \cf0 \f10 \fs13 \cf0 ic
) \par
}
\cf0 Subtracting a negative{\fs15 from} a positive number
5 \cf0 \fi1867 {\f10 \fs9 1}{\f10 \fs9 1 }\par
}
\cf0 Form{\i 2s} complement \par
}
\par
}
cf0 and add \par
}
\fs17 \cf0 11000100
Minuend
fi40 {\b0 \f10 \fs26 +}{\fs16
1}{\fs16 1}{\fs16 1}{\fs16 1}{\fs17 O001}
Subtrahend
\i \f10 \fs25 iB} 1011{\b0 \fs22 0101}{\fs16
2s} complement difference \pa
r
}
{\phpg\posx5341\pvpg\posy8448\absw297\absh677 \f10 \fs57 \cf0 \f10 \fs57 \cf0 /
\par
}
6 \cf0 rc
071 {\b \fs15 Discard }
\fi97 {\b \fs15 Subtracting}{\b \fs15 a}{\b \fs15 positive}{\b \fs15 from}{\b
\fs15 a}{\b \fs15 negative}{\b \fs15 number }
{\b Fig.}{\b \fs16 8-37}{\b \fs17
2s}{\b \fs17 complement}{\b \fs17 subtr
action }\par
}
8 \cf0 The second example{\fs19 of}{\fs19 2s} complement subtraction
is detailed in Fig.{\i \fs19 8-37b.} Two negative
bers are subtracted. The minuend{\f10 \fs16 (}{\f10 \fs15 -}{\i \fs19 80)} i
s converted to its{\fs19 2s} complement form{\b \fs19 (10110000).} The
\par}{\phpg\posx843\pvpg\posy10612\absw9698\absh1503 \sl-239 \f20 \fs18 \cf0 sub
trahend{\i \fs19 (-30)} is{\fs19 2s} complemented twice to get first
{\b \fs19 11100010} and finally{\b \fs19 00011110.} The{\fs19 2s }
plement difference is{\b \fs19 11001110}{\f10 \fs16 (}{\f10 \fs15 -}{\b \fs1
9 50)} when the minuend and subtrahend are{\i \fs19 added. }
366 The third example{\fs19 of}{\i \fs19 2s} complement subtraction{\fs18
is} explained in Fig.{\i \fs19 8-37c.}{\b A}{\fs19 -20} is subtracted
\par}{\phpg\posx843\pvpg\posy10612\absw9698\absh1503 \sl-232 \f20 \fs18 \cf0 fro
m a{\i \fs19
+24.} The{\fs19
-20}{\fs18
is} 2s complemented twice
{\fs18 to} get the temporary{\b \fs19
11101100} and the final
\par}{\phpg\posx843\pvpg\posy10612\absw9698\absh1503 \sl-237 \f20 \fs18 \cf0 sub
trahend{\fs19 of}{\b \fs19 00010100.} The subtrahend{\b \f30 \fs20 (OOOlOlOO
)}is then added{\fs18 to} the minuend{\b \fs19 (00011000)} to get \par
}
he{\i \fs19 2s} complement difference of{\b \fs19 00101}{\fs18 100,} or{\f10
\fs28 +}{\i \fs19 44} in decimal. \par
}
The final example{\fs18 of}{\i \fs19 2s} complement subtraction is given{\fs
18 in} Fig.{\i \fs19 8-37d.}{\b \f10 \fs17 A}{\f10 \fs29 + }\par
}
15{\fs18 is}{\fs18 subtracted}{\fs18 from }\par
}

\cf0 -{\f20 \fs19 60.}{\f20 \fs18 The}{\f20 \fs18 minuend}{\fs16 (-}{\f20 \f
s18 60)}{\f20 \fs18 is}{\f20 \fs18 converted}{\f20 \fs18 to}{\f20 \fs18 it
s}{\i \f20 \fs19 2s}{\f20 \fs18 complement}{\f20 \fs18 form}{\f20 \fs18 (1}
{\b \f20 \fs19 1000100).}{\f20 \fs18 The}{\f20 \fs18 subtrahend}{\fs17 (+}{\
f20 \fs19 15) }
0 \fs18 is}{\f20 \fs19 2s}{\f20 \fs18 complemented}{\f20 \fs18 twice}{\f20 \
fs18 to}{\f20 \fs18 get}{\f20 \fs18 the}{\f20 \fs18 temporary}{\b \f20 \fs19
00001111}{\f20 \fs18 and}{\f20 \fs18 the}{\f20 \fs18 final}{\f20 \fs18
subtrahend}{\f20 \fs19 of}{\b \f20 \fs19 11110001.}{\f20 \fs18 The }
0 \fs18 minuend}{\b \f20 \fs18 (1}{\f20 \fs19 1000100)}{\f20 \fs18 and}{\f20
\fs18 subtrahend}{\f20 \fs18 (1}{\f20 \fs18 11}{\f20 \fs18 10001)}{\f20 \fs
18 are}{\f20 \fs18 added}{\f20 \fs18 to}{\f20 \fs18 get}{\f20 \fs18 1}{\f
20 \fs18 10110101.}{\f20 \fs19 The}{\f20 \fs18 overflow}{\b \f20 \fs19 (MSB)
}{\f20 \fs19 is }
0 \fs18 discarded,}{\f20 \fs18 leaving}{\f20 \fs18 a}{\i \f20 \fs19 2s}{\f20
\fs18 complement}{\f20 \fs18 difference}{\f20 \fs19 of}{\f20 \fs19 101}{
\f20 \fs18 10101,}{\f20 \fs18 or}{\fs19 -}{\i \f20 \fs19 75}{\f20 \fs18 in}{
\f20 \fs18 decimal. }\par
}
0 196 \par
}
}
AP.{\fs17 8 }\par
}
\cf0 All the sample problems can be tested by using the 8-bit parallel adder/su
btractor shown in{\fs18 Fig. }
\par}{\phpg\posx875\pvpg\posy1398\absw8898\absh634 \sl-234 \f20 \fs19 \cf0 8-35.
Remember that both the inputs to and outputs from the adder/subtractor circuit
shown in Fig.
must be in 2s complement notation. \par
}
}
f0 8.50 \par
}
hy are{\fs19 2s} complement numbers used in digital systems?
62 {\b \fs17 2s}{\fs17 complement}{\fs17 numbers}{\fs17 are}{\fs17 used}{\fs
17 to}{\fs17 represent}{\fs17 signed}{\fs17 numbers. }\par
}
cf0 8.51{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 8-35.}{
\b0 \fs19 This}{\b0 \fs19 circuit}{\b0 \fs19 can}{\b0 \fs19 add}{\b0 \fs19
or}{\b0 \fs19 subtract }

}
mbers. \par
}
he circuit shown in Fig.{\fs17 8-35} can add or subtract signed numbers in
{\fs17 2s} complement notation. \par
}
s56 \cf0 -IdB2 \par
}
\cf0 A4{\i0 \fs13
(7483) }\par
}
\par
}
13 \cf0 B2 \par
}
10 \cf0 A4 \par
}
{\fs13 complement }
4 {\fs13 inputs }
fi708 {\b\i \fs13 A5 }\par
}
\cf0 G r \par
}
\cf0 (7483) \par
}
\cf0 Fig.{\fs17 8-38}{\b0 \fs17
8-bit}{\b0 \fs17 adder/subtractor}{\b0 \f
s17
circuit }\par
}
\cf0 MSB
20 {\b\i \fs10 B }
13 Mode}{\fs13 control }
3 {\fs13 Subtract}{\f10 \fs13 =}{\fs13 1 }
30 {\fs13 Add}{\f10 \fs13 =} 0 \par
}
10 \cf0 8 \par
}
10 \cf0 p \par
}

10 \cf0 B \par
}
10 \cf0 4 \par
}
\cf0 c o t \par
}
ign
7 bit \par
}
\cf0 2s{\fs13 complement }
s13 sum}{\fs13 or}{\fs12 difference }\par
}
f0 8.52 \par
}
raw a{\b \fs18 diagram}{\b \fs17 of}{\b \fs18 an}{\b \fs17 8-bit}{\b \f
s17 parallcl} addcr/subtrnctor{\b \f10 \fs16
by}{\b \fs18 using}{\b \f10 \
fs16 two}{\b \fs18 7483}{\b \fs18 ICs}{\b \fs18 and}{\b \fs17 cight}{\b
\fs19 XOK }\par
}
\cf0 gatcs.{\f20 \fs18 Usc}{\f20 \fs18 i;igs.}{\f20 \fs17 8-34}{\f20 \fs18
and}{\b0\i \f20 \fs18 8-35}{\f20 \fs18 a\\ }
\f20 \fs17 Solution: }
fi364 {\i \f20 \fs16 Sec}{\b0 \f20 \fs16 Fig.}{\b0 \fs14 X-38. }\par
}
cf0 :I{\fs18 guide. }\par
}
f0 8.53 \par
}
\cf0 Kefcr{\fs16 t}{\fs16 o}{\fs18 Fig.}{\b0\i \fs18 8-35.}{\b0 \fs18 Thc}{
\fs18 numhcrs}{\fs18 input}{\fs17 into}{\fs18 thc}{\fs18 addcr/subtractor
}{\fs18 must}{\fs19 be}{\fs18 in}{\fs16 what}{\fs19 code? }
f0 {\fs17 Solution: }
fi350 {\fs16 The}{\fs16 number\\}{\fs17 inpiit}{\fs15 into}{\fs17 thc}{\fs
17 ddtlcr/\\iibtractor}{\fs17 5hwn}{\fs15 in}{\fs15 big.}{\fs16 8-35}{\
fs17 mu\\[}{\fs17 bc}{\f10 \fs14 in}{\i \fs16 2s}{\fs17 coniplemcnt}{\fs1
7 notation. }\par
}
7 \cf0 8.S \par
}
\cf0 Kcfer{\f10 \fs15 to}{\fs17 Fig.}{\b0\i \fs18 8-35.}{\fs18 What}{\fs18

do}{\fs18 inputs}{\i \f10 \fs16 A,}{\fs18 and}{\fs18 II,}{\fs18 rcpr
cscnt'! }
f0 {\fs17 Solution: }
fi364 {\fs15 Inputs}{\f10 \fs14
A,}{\fs17
m}{\fs17 d}{\i \fs15 !I,}{\dn
006 \f10 \fs10
111}{\f10 \fs15 I-ip.}{\f30 \fs17 S-35}{\fs17 rcpruwnt}{\
b0 \fs16 thu}{\fs15 !.igns}{\fs16 of}{\b0 \fs16 thc}{\fs17 nunibcrr.}{
\fs16 I}{\fs16 f}{\b0 \fs16 the}{\f10 \fs13 sign}{\f10 \fs13 bit}{\dn006
\fs10
IS}{\i \fs15 0,}{\b0 \fs16 the}{\fs17 number}{\f10 \fs15 is }
\fs17 pviitivc:}{\dn006 \f10 \fs10 if}{\fs17 thc}{\f10 \fs14 \\ipii}{\fs16
hit}{\fs17 i}{\fs17 \\}{\fs16
I}{\fs16 .}{\fs15 tlic}{\f10 \fs14 iiu
iiilxr}{\fs10
i5}{\f10 \fs13 iicx;rtivc. }\par
}
7 \cf0 8.55 \par
}
cf0 Add \par
}
\cf0 83{\fs18 and}{\b0 \f10 \fs22 +}{\f10 \fs17 17}{\f30 \fs18 h}{\f30 \fs1
8 y }\par
}
\cf0 using{\i \f20 \fs17 2s}{\f20 \fs17 coniplement}{\b0 \f20 \fs16 riunih
cr5.}{\f30 \fs17 IJsc}{\b0 \f20 \fs17 thc}{\f20 \fs17 prtxcdurc}{\f20 \fs16
shown}{\b0 \f20 \fs18 in}{\f20 \fs18 Fig.}{\i \f20 \fs17 8-36. }\par
}
\cf0 Solution:
fi355 {\b0 \f10 \fs14 Scc}{\f10 \fs13 Fig.}{\b0 \f10 \fs14 X-3q. }\par
}
I \par
}
0 I I \par
}
\cf0 (+U)
\fs13 +(}{\f10 \fs23 +}{\b\dn006 \f10 \fs15 17) }
fi153 {\f10 \fs14 +}{\b\dn006 \f10 \fs9 1}{\b\dn006 \f10 \fs9 0}{\b\dn006 \f10
\fs9 1}{\b\dn006 \f10 \fs9 0 }\par
}
\cf0 0101{\fs15 001}{\b I}{\b\i \f20 \fs16
2s}{\b \f20 \fs17 complement}
{\b \f20 \fs17 augend }
22 +}{\b \fs15 O001}{\fs16 OOOI}{\b\i \f20 \fs17
2s}{\b \f20 \fs17 comp
lement}{\b \f20 \fs17 addend }
30 01{\b \f20 \fs17 10}{\b \f20 \fs17 0100}{\b \f20 \fs17
2s}{\b \f20 \fs17
complement}{\b \f20 \fs17 5uni }\par
}

\cf0 Fig. 8-39 Solution{\fs15 to}{\dn006 \fs11 25 }\par
}
\cf0 complcmcnt{\fs17 addition} problem \par
}
7 \cf0 8.56 \par
}
cf0 Add \par
}
{\b \fs16 110}{\b \f20 \fs18 iind}{\fs15
-}{\fs17 13}{\b \f30 \fs18 by}
{\b \f20 \fs18 wing}{\b \f20 \fs19 25}{\b \f20 \fs18 complcnicnt}{\b \f20
\fs18 nunibcrk.}{\b \f30 \fs17 I:sc}{\b \fs16
thc}{\b \f20 \fs18 prtnxi
urc}{\b \f20 \fs18 illustrated}{\f20 \fs19
in }\par
}
\cf0 I - i g{\fs18 8-30. }
\fs17 Solution: }
fi353 {\f10 \fs14 Sec}{\fs15 Fig.}{\f10 \fs14 WO. }\par
}
cf0 8.57 \par
}
\cf0 Subtract{\i \fs17
+}{\i \fs17 I}{\i \fs17 0}{\fs18 from}{\f30 \fs19
t}{\f30 \fs19 M}{\f30 \fs18 by}{\fs18 using}{\i 2s}{\fs18 coniplcnicnt}
{\fs18 numhcrs.}{\fs19 Uw}{\f10 \fs16
the}{\fs18 procedure}{\fs18 illu
strated}{\fs19 in }
{\fs16 Fig.} 8-37.
cf0 {\fs17 Soh}{\f10 \fs14 t}{\fs17 ion: }
\fi364 {\f10 \fs14 Scc}{\f10 \fs13 Fig.}{\f10 \fs14 S-41. }\par
}
0 I98 \par
}
cf0 HINARY ARITHMETIC{\f10 \fs15 A}{\f10 \fs15 X}{\f10 \fs15 D}{\fs17 ARITt}
{\fs17 IMETIC}{\fs17 CIRCC!ITS }\par
}
\fs16 \cf0 (+U)
b0 \fs14 -(}{\f20 \fs17
+26) }
i245 {\f30 \fs16 +38,0 }\par
}
\cf0 2s{\f20 \fs13 complement }\par
}
{\phpg\posx3673\pvpg\posy1698\absw813\absh316 \f10 \fs27 \cf0 \f10 \fs27 \cf0 '{
\b \f30 \fs19 Oool }\par

}
\cf0 21{\f20 \fs13 complement }
fi240 {\f20 \fs13 andadd }\par
}
\cf0 I
\f10 \fs14 0100oooO}{\fs16
Minuend }\par
}
{\b \f30 \fs17 I10011}{\b \f10 \fs16 10}{\fs16
Subtrahcnd }
30 {\b \f30 \fs18 oOlO~Ol1O}{\b \fs17 2s}{\fs16 complcmcnt}{\fs16 diffcrcncc
}\par
}
\cf0 '{\fs19 ,@ }
4 J }\par
}
6 \cf0 Disc;i;tI
{\b \f10 \fs13 Fig.}{\b \f10 \fs15 841}{\fs16
Solution}{\f10 \fs12 t}{\f10
\fs12 o}{\b\i \fs17 3}{\fs16 complcrncnt}{\fs16 subtraction}{\fs16 proh
lcm }\par
}
f0 8.58 \par
}
ubtract{\f10 \fs15
-}{\fs19 23}{\fs19 froni}{\f10 \fs15
-}{\b \f30 \fs2
0 53}{\b \fs18 by}{\b \fs17 usirig}{\b \f10 \fs18 2s}{\fs17 coniplcnicnt}
{\fs18 nunihcrs.}{\b \f30 \fs17 IJsc}{\fs18 rhc} prcwctlurc{\b illrr\\tr
awd} in
\f10 \fs16 1--1g.}{\f10 \fs17 x-37. }
60 {\b \f10 \fs11 SCC}{\b \fs15 Fig.}{\b \fs16 8-42, }\par
}
cf0 (-53)
b0 \f10 \fs14 (}{\b0\dn006 \f10 \fs14 -}{\fs17 23) }
i95 {\b0 \f10 \fs20 -}{\fs17 3010 }\par
}
\cf0 2scnmplerncnt \par
}
\par
}
cf0 1 1{\fs16 10}{\fs16 1001 }\par
}
\cf0 2s{\fs13 complcmcnt }
fi234 {\fs13 and}{\fs13 add }\par
}
fs9 \cf0 I I{\f20 \fs9
I}{\f20 \fs9 l}{\f20 \fs9 l }
\par}{\phpg\posx6813\pvpg\posy5524\absw944\absh285 \sl-173 \b \f10 \fs9 \cf0 {\f
20 \fs16 I}{\b0 \f20 \fs16 I}{\b0 \f20 \fs16 0}{\b0 \f20 \fs16 0}{\fs15 1}{
\fs15 0}{\fs15 1}{\fs15 1 }\par
}
{\fs15 OOO1}{\b \fs15 011}{\f20 \fs16 I }\par
}
{\phpg\posx7739\pvpg\posy5640\absw875\absh380 \f20 \fs16 \cf0 \f20 \fs16 \cf0 hf
inucnd
\par}{\phpg\posx7739\pvpg\posy5640\absw875\absh380 \sl-222 \f20 \fs16 \cf0 Subtr
ahend \par
}
\cf0 I{\b0 \f10 \fs14 1}{\f10 \fs15 10}{\b0 \f10 \fs15 0010}{\fs16
2s}{\b0
\fs16 complcmcnt}{\b0 \fs16 difference }\par
}
ig.{\b \f10 \fs15 8-42} Solution{\b \f10 \fs14 to}{\b\i \fs17 3} cornpl
cmcnt subtraction prohlcm \par
}
upplementary Problems \par
}
cf0 8.60 \par
}
Givc{\b \f10 \fs15 thc}{\fs16 Icttcr}{\fs16 symbol}{\b \fs16 for}{\b t
he}{\fs16 following}{\fs16 inputs}{\b \f10 \fs13 to}{\fs16 and}{\fs16 o
utput5 }
\f10 \fs14 (a1}{\fs16
top}{\fs16 input.}{\b\i \fs15
(}{\b\i \fs1
5 h}{\b\i \fs15 )}{\fs16
bottom}{\fs16 input.}{\b\i \fs15
(}{\b\
i \fs15 c}{\b\i \fs15 )}{\fs16
sum}{\fs16 output. }\par
}
(}{\fs14 a}{\fs14 )}{\b0\i0 \f20 \fs16
top}{\b0\i0
\f20 \fs16 input}{\fs15 -}{\fs15 A}{\f20 \fs17
(}{\f20 \fs17 h}{
\f20 \fs17 )}{\b0\i0 \f20 \fs16
bottom}{\b0\i0 \f20 \fs16 input}{\b0\i0\dn
006 \fs10
=}{\fs16 H}{\i0 \fs13
(c.) }\par
}
froiri{\b \fs10
;I}{\b \fs10
Ii;ilf}{\b \fs12
;ttltlcr}{\b \f10 \fs16
(IIA): }
137 {\b\i \fs17 (}{\b\i \fs17 d}{\b \f10 \fs15 1}{\fs17
carn}{\fs16 outp
ut. }\par
}
sun1{\b \fs15 outpiit}{\f10 \fs15 -}{\f10 \fs18 L }\par
}
s15 \cf0 ( c f ) \par

}
{\phpg\posx8319\pvpg\posy10553\absw936\absh188 \f20 \fs16 \cf0 \f20 \fs16 \cf0 u
r p{\fs16 output }\par
}
{\b\i \f30 \fs14 ('o }\par
}
cf0 8.61 \par
}
\cf0 Givc{\f20 \fs17 thc}{\b0 \f20 \fs16 lcttcr}{\b0 \f20 \fs16 symbol}{\
b0 \f20 \fs16 for}{\f20 \fs16 the}{\b0 \f20 \fs16 following}{\b0 \f20 \fs1
6 input\\}{\fs13 to}{\b0 \f20 \fs16 and}{\b0 \f20 \fs16 outputs}{\b0 \f2
0 \fs16 from}{\dn006 \f20 \fs10
;i }\par
}
fs14 \cf0 ( a ){\b0\i0 \f20 \fs16
carry}{\b0\i0 \f20 \fs16 input. }
0 {\b0\i0 \f20 \fs16 output. }\par
}
irs. \par
}
fs15 \cf0 ( h ){\i0 \fs14
top}{\b0\i0 \f20 \fs16 data}{\b0\i0 \f20 \fs16 i
nput. }\par
}
\cf0 (c){\f20 \fs16
hottom}{\fs14 data}{\b0 \f20 \fs16 input. }\par
}
\cf0 full{\fs16 atldcr}{\fs16 (FI\\): }
\fi230 {\i \f10 \fs16 (}{\i \f10 \fs16 (}{\i \f10 \fs16 1}{\i \f10 \fs16 )}{\
b0 \fs16
sun1output. }\par
}
s13 \cf0 ( c ){\b0\i0 \fs14
c}{\b0\i0 \fs14 a}{\b0\i0 \fs14 r}{\b0\i0 \fs1
4 n }\par
}
fs14 \cf0 ( a ){\b0\i0 \f20 \fs17
carry}{\b0\i0 \f20 \fs16 input}{\b0\i0\dn
006 \fs11
=}{\f30 \fs17 ('in }\par
}
\cf0 ( h ){\i0 \f20 \fs15
top}{\i0 \f20 \fs16 data}{\i0 \f20 \fs16 input
}\par
}
s15 \cf0 A \par
}
\cf0 (c)
\i \fs17 (}{\i \fs17 (}{\i \fs17 1 }\par
}
6 \cf0 bottom data input

\i \f10 \fs17 )} sum output{\f10 \fs31 -}{\b\i\dn006 \fs19 2: }\par
}
0 i \par
}
s17 \cf0 R \par
}
fs16 \cf0 ( c ){\i0 \fs16
carp}{\i0 \fs16 output }\par
}
{\phpg\posx8147\pvpg\posy11848\absw18\absh92 \f10 \fs7 \cf0 \f10 \fs7 \cf0 ' \pa
r
}
{\phpg\posx8211\pvpg\posy11848\absw26\absh92 \f10 \fs7 \cf0 \f10 \fs7 \cf0 . \pa
r
}
s15 \cf0 C I J \par
}
cf0 8.62 \par
}
\fs15 \cf0 Draw{\b0 \f20 \fs16 a}{\b0 \f20 \fs16 logic}{\b0 \f20 \fs16 dia
gram}{\b0 \f20 \fs16 of}{\b0 \f20 \fs16 an}{\fs15 H}{\fs15 A}{\b0 \f20 \f
s16 circuit}{\b0 \f20 \fs16 using}{\b0 \f20 \fs16 gatch.}{\f20 \fs17 1,;
ihcl}{\b0 \f20 \fs16 thc}{\b0 \f20 \fs16 inputs}{\b0 \f20 \fs16 iind}{\b0 \
f20 \fs16 ouiputs. }
{\i Anc.}{\b0 \f20 \fs17
Scc}{\b0 \f20 \fs16 Fig.}{\i \f20 \fs17 8-Zh.
}\par
}
15 \cf0 8.63 \par
}
\cf0 Draw \par
}
cf0 :i \par
}
logic diagram{\fs16 of} an{\fs17
FA} circuit{\b \fs17 b)} using{\b \
fs17 XOR} and{\b \f30 \fs19 NASD}{\b \f10 \fs14 gatcs} only.{\b \fs16 1
;rhcl}
thc{\b \fs15
input5} iind \par
}
outputs.{\b \f10 \fs15 Usc} Fig.{\fs15 8-6}{\b \f10 \fs14 as}{\b\dn006 \f1
0 \fs10 ;i}guide. \par
}
fs14 \cf0 Am.{\i0 \fs14
Scc}{\b0\i0 \f20 \fs16 Fig.}{\i0 \f30 \fs16 8-43
. }\par
}
.{\fs17 81 }\par
}
}
\par
}
\cf0 Fig.{\fs16 8-43}{\b0
Full}{\b0 adder}{\b0 logic}{\b0 diagram}{\b0
using}{\b0 \fs17 XOR}{\b0 and}{\fs17 NAND}{\b0 gates }\par
}
f0 8.64
8.65 \par
}
n{\fs17 HA}{\fs16 will}{\fs16 add}{\fs16 two}{\fs16 variables,}{\fs16
and}{\fs16 an}{\fs16 FA}{\fs16 will}{\fs16 add }\par
}
nput variables. \par
}
17 \cf0 Ans.{\b0\i0 \fs16
three }\par
}
ist the full adder{\f10 \fs17 C} outputs for each set of input pulses
shown in Fig.{\b \f30 \fs17 8-44. }\par
}
s17 \cf0 Ans.{\b0\i0 \fs16
pulse}{\fs16 a}{\b0\i0 \f10 \fs13 =}{\b0\i0
\fs16 1 }
\fi537 {\b0\i0 \fs16 pulse}{\b0 b}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0 0 }\p
ar
}
lse{\i \f10 \fs14 c}{\f10 \fs13 =}{\fs17 1 }
d{\dn006 \f10 \fs11 =} 1 \par
}
lse{\b\i \fs16 e}{\f10 \fs13 =}{\fs17 0 }
{\i \f30 \fs19 f=} 1 \par
}
lse{\fs15 g}{\f10 \fs13 =} 1
{\i \fs17 h}{\f10 \fs13 =}{\fs16 0 }\par
}
lse{\fs16 i}{\dn006 \f10 \fs11 =}{\fs17 0 }
{\fs15 j}{\dn006 \f10 \fs11 =}{\fs17 0 }\par
}
15 \cf0 j \par
}

15 \cf0 i \par
}
15 \cf0 h \par
}
15 \cf0 g \par
}
15 \cf0 f \par
}
15 \cf0 e \par
}
15 \cf0 d \par
}
15 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\cf0 Fig.{\f10 \fs15 8-44}{\b0 \fs16
Full}{\b0 \fs16 adder}{\b0 \fs16 pu
lse-train}{\b0 \fs16 problem }\par
}
f0 8.66 \par
}
ist the full adder{\b\i CO} outputs for each set{\fs17 of} input pulses
shown in Fig.{\b\i \fs16 8-44. }\par
}
s17 \cf0 Ans.{\b0\i0 \fs16
pulse}{\fs16 a}{\b0\i0 \f10 \fs13 =}{\b0\i0 \
fs17 1 }
\fi531 {\b0\i0 \fs16 pulse}{\b0\i0 \fs16 b}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs1
6 1 }\par
}
lse{\fs16 c}{\f10 \fs13 =}{\fs17 0 }
{\fs16 d}{\f10 \fs13 =}{\fs17 0 }\par
}
lse{\b\i \fs16 e}{\f10 \fs13 =}{\fs16 0 }
{\i \f30 \fs19 f=} 1 \par
}
ulse{\i \f10 \fs14 g}{\dn006 \f10 \fs11 =}{\fs17 0 }
e{\b\i \f30 \fs19 I!}{\dn006 \f10 \fs11 =} 1 \par
}

lse{\b\i \f30 \fs17 i}{\f10 \fs13 =} 1
{\i \f10 \fs15 j}{\f10 \fs13 =}{\fs16 0 }\par
}
cf0 8.67 \par
}
Solve the following binary subtraction problems: \par
}
\cf0 (a) \par
}
\cf0 11011
\par}{\phpg\posx2089\pvpg\posy10411\absw653\absh410 \sl-243 \f20 \fs16 \cf0 -011
10 \par
}
\cf0 (b) \par
}
\cf0 11100
\par}{\phpg\posx3671\pvpg\posy10411\absw655\absh379 \sl-210 \f20 \fs16 \cf0 -011
10 \par
}
c) \par
}
(}{\fs16 a}{\fs16 )}{\b0\i0 \fs16
1101 }\par
}
\cf0 (b){\i0 \fs16
1110 }\par
}
\cf0 (c){\i0 \f20 \fs16
1111 }\par
}
\cf0 11001
0 \fs15 -}01010
\fi78 {\i \f10 \fs16 (}{\i \f10 \fs16 d}{\i \f10 \fs16 )}
0111 \par
}
s15 \cf0 ( d ) \par
}
6 \cf0 10000
366 {\f10 \fs15 -}01001
{\b\i \fs16 (}{\b\i \fs16 e}{\b\i \fs16 )} 0110 \par
}
s16 \cf0 ( e ) \par
}
\cf0 10111
0 \fs15 -} 10001 \par
}
cf0 8.68 \par
}
Give the names of the following inputs to and outputs from a half subtr
actor:
\i \fs17 (}{\b\i \fs17 a}{\b\i \fs17 )}{\b\i \fs17
A}{\b\i \fs17 ,}{\i \f
10 \fs15
(b)}{\i \fs17
B,}{\b\i \fs16
(}{\b\i \fs16 c}{\b\
i \fs16 )}{\b\i \f30 \fs19 Di,}{\b\i \f10 \fs16
(}{\b\i \f10 \fs16 d}{
\b\i \f10 \fs16 )}{\i \fs17
Bo. }\par
}
fs16 \cf0 Am.{\b0 \f10 \fs14
(a)}{\f10 \fs16
A}{\b0\i0 \f10 \fs13 =}{\
b0\i0 minuend}{\b0\i0 input }
0 \fi534 {\i0 \fs17 (6)}{\b0 \fs17
B}{\b0\i0 \f10 \fs13 =}{\b0\i0 subtrahe
nd}{\b0\i0 input }\par
}
c) \par
}
fs19 \cf0 Di{\b0\i0\dn006 \f10 \fs13 =}{\b0\i0 \f20 \fs16 difference}{\b0\i0 \
f20 \fs16 output }\par
}
fs15 \cf0 ( d ){\f20 \fs16
Bo}{\b0\i0 \fs13 =}{\b0\i0 \f20 \fs16 borrow}{\
b0\i0 \f20 \fs16 output }\par
}
cf0 8.69 \par
}
Give the letter symbols for the following inputs to and outputs from
the{\b \fs17 FS: }\par
}
fs17 \cf0 (a){\b0\i0 \fs16
borrow}{\b0\i0 \fs16 input, }
0 {\fs16 (}{\fs16 e}{\fs16 )}{\b0\i0 \fs16
borrow}{\b0\i0 \fs16 output.
}\par
}
\cf0 (b){\i0 \fs16
minuend}{\i0 \fs16 input, }\par
}
(c){\fs16
subtrahend}{\fs16 input, }\par
}
\cf0 (d){\i0 \f20 \fs16
difference}{\i0 \f20 \fs16 output, }\par
}
(}{\fs16 a}{\fs16 )}{\b0\i0 \fs16
borrow}{\b0\i0
\fs16 input}{\b0\i0 \f10 \fs13 =} Bin
0 \fi536 {\fs17 (b)}{\b0\i0 \fs16

minuend}{\b0\i0 \fs16 input}{\fs16 =}{\f
s16 A }\par
}
\cf0 (c) \par
}
subtrahend input{\f10 \fs13 =}{\b\i \fs17 B }\par
}
(e){\fs16
borrow}{\fs16 output}{\f10 \fs13 =}{\b\i \fs16 Bo }\par
}
fs15 \cf0 ( d ){\b0\i0 \f20 \fs16
difference}{\b0\i0 \f20 \fs16 output}{\b0
\i0 \fs13 =}{\f30 \fs20 Di }\par
}
\par
}
}
}
f0 8.70 \par
}
Refer to Fig.{\b \fs17 8-19.} The{\b\i \fs17 A}{\b\i \fs17 ,} and{\b\i \
fs17 B,} inputs are from the
blem.{\b\i \fs17
Ans.}{\fs17
2s }
Refer to Fig.{\b \fs17 8-20.} The{\b\i \f10 \fs16 A,} and{\b\i \fs17 B,
} inputs are from the
blem.{\b\i \fs17
Ans.}{\b \fs17
4s }\par
}
\cf0 (Is,2s,4s, 8s){\b0 \fs17 column}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs
17 addition }\par
}
f0 8.71 \par
}
\cf0 (Is, 2s,4s,8s){\b0 \fs17 column}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17
subtraction }\par
}
f0 8.72 \par
}
efer to Fig.{\b \fs17 8-20.} If all inputs to the{\b 4s} FS are{\b
\fs17 1,} the output from this FS will be Di=
i \fs17 Bo=}{\f10 \fs22
. }\par
}
{\phpg\posx9419\pvpg\posy2903\absw291\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 an
d \par
}
s16 \cf0 Am.{\b0\i0 \f20 \fs17
When}{\b0\i0 \f20 \fs17 all}{\b0\i0 \f20 \f
s17 inputs}{\b0\i0 \f20 \fs17 to}{\b0\i0 \f20 \fs17 the}{\i0 \f20 \fs17 4s}{
\b0\i0 \f20 \fs17 FS}{\b0\i0 \f20 \fs17 shown}{\b0\i0 \f20 \fs17 in}{\b0\i0 \
f20 \fs17 Fig.}{\i0 \f20 \fs17 8-20}{\b0\i0 \f20 \fs17 are}{\b0\i0 \f20 \fs1
7 HIGH,}{\b0\i0 \f20 \fs17 the}{\b0\i0 \f20 \fs17 outputs}{\b0\i0 \f20 \fs17
will}{\b0\i0 \f20 \fs17 be}{\b0\i0 \f20 \fs17 Di}{\b0\i0 \fs14 =}{\i0 \f2
0 \fs16 1}{\b0\i0 \f20 \fs17 and}{\b0 \f20 \fs17 Bo}{\b0\i0 \fs13 =}{\i0 \f
20 \fs17 1. }
\fi22 {\b0\i0 \f20 \fs17 This}{\b0\i0 \f20 \fs17 is}{\b0\i0 \f20 \fs17 based}
{\b0\i0 \f20 \fs17 on}{\b0\i0 \f20 \fs17 line}{\i0 \f20 \fs17 8}{\b0\i0 \f
20 \fs17 of}{\b0\i0 \f20 \fs17 the}{\b0\i0 \f20 \fs17 FS}{\b0\i0 \f20 \fs17
truth}{\b0\i0 \f20 \fs17 table}{\b0\i0 \f20 \fs17 in}{\b0\i0 \f20 \fs17
Fig.}{\b0\i0 \f20 \fs17 8-15. }
s16 \cf0 \fi40 {\b0\i0 \f20 \fs17 Refer}{\b0\i0 \f20 \fs17 to}{\b0\i0 \f20 \fs
17 Fig.}{\i0 \f20 \fs17 8-45.}{\b0\i0 \f20 \fs17 The}{\b0\i0 \f20 \fs17 o
utputs}{\b0\i0 \f20 \fs17 from}{\b0\i0 \f20 \fs17 the}{\i0 \f20 \fs17 1s}{
\b0\i0 \f20 \fs17 HS}{\b0\i0 \f20 \fs17 are}{\b0\i0 \f20 \fs17 Di}{\b0\i0
\fs13 =}{\fs14
(}{\fs14 a}{\fs14 )}{\b0\i0 \f20 \fs17
and}{\f20 \f
s17 Bo}{\b0\i0 \fs13 =}{\f20 \fs16
(}{\f20 \fs16 b}{\f20 \fs16 )}{\b0\
i0 \f20 \fs17
according}{\b0\i0 \f20 \fs17 to}{\b0\i0 \f20 \fs17 line
}\par
}
18 \cf0 ( c ) \par
}
n the truth table in Fig.{\b \fs17 8-11. }
\fi1439 {\b \fs15 Problem }\par
}
cf0 1 \par
}
cf0 0 \par
}
\b \f30 \fs15 0}{\b \f30 \fs15 0 }\par
}
cf0 0
f10 \fs14 1 }\par
}
cf0 1
f10 \fs14 1 }\par
}
f0 8.73 \par
}
I \par
}
15 \cf0 Bin \par
}
15 \cf0 Di \par
}
f0 I \par
}
15 \cf0 Bin \par
}
15 \cf0 Di \par
}
20 \fs15 \cf0 Difference
cf0 {\fs17 Fig.}{\f10 \fs16 8-45}{\b0 \fs17
Parallel-subtractor}{\b0 \fs17
circuit}{\b0 \fs17 problem }\par
}
cf0 8.74 \par
}
Refer to Fig.{\b \fs17 8-45.} The inputs to the{\b \fs17 2s} FS are{
\b\i \f10 \fs16 A}{\f10 \fs13 = }
puts of Di{\f10 \fs13 =}
and{\i \fs17 Bo}{\f10 \fs13 =}
according to line \par
}
The}{\b0\i0 \fs17 inputs}{\b0\i0 to}{\b0\i0
\fs17 the}{\i0 2s}{\i0 \fs17 FS}{\b0\i0 \fs17 (Fig.}{\i0 \fs17 8-45)}
{\b0\i0 \fs17 are}{\f10 \fs15 A}{\b0\i0\dn006 \f10 \fs11 = }
0 {\fs17 Bo}{\b0\i0 \f10 \fs13 =}{\b0\i0 1}{\b0\i0 \fs17 according}{\b0\i0 \f
s17 to}{\b0\i0 \fs17 line}{\i0 \fs16 3}{\b0\i0 \fs17 in}{\b0\i0 \fs17 Fi
g.}{\i0 \fs17 8-15. }\par
}
{\b\i \f20 B}{\fs13 = }\par
}
{\f20 \fs17 and}{\f20 \fs17
Bin}{\dn006 \fs13 = }\par
}
ith \par
}
in the truth table in Fig.{\b \fs17 8-15. }\par
}
0,{\b\i \fs17 B}{\f10 \fs13 =}{\fs16 1,} and Bin{\dn006 \f10 \fs11 = }\
par
}
0 with outputs of Di{\dn006 \f10 \fs11 = }\par
}
\cf0 1{\b0 \fs17 and }\par
}
cf0 8.75 \par
}
Refer to{\b \fs16 Fig.}{\b \fs17 8-45.} The inputs to the{\b \fs17 4s
} FS are{\b\i \f10 \fs16
A}{\f10 \fs13 = }
puts{\fs18 of}{\b\i \f30 \fs19 Di}{\f10 \fs14 =}
and{\b\i
Bo}{\f10 \fs13 =}
}
{\b\i \f20 \fs17 B}{\dn006 \fs13 = }\par
}
8 \cf0 ,{\f20 \fs17 and}{\f20 \fs17
Bin}{\dn006 \fs13 =}{\fs19 -}{\f20 \fs
17 with }
20 \fs17 in}{\f20 \fs17 the}{\f20 \fs17 truth}{\f20 \fs17 table}{\f20 \fs17
in}{\f20 \fs17 Fig.}{\b \f20 \fs17 8-15. }\par
}
The}{\b0\i0 inputs}{\b0\i0 to}{\b0\i0 the}{\i0 \fs1
7 4s}{\i0 \fs17 FS}{\b0\i0 (Fig.}{\i0 \fs17 8-45)}{\b0\i0 are}{\f10 \fs16
A}{\b0\i0 \f10 \fs14 =}{\b0\i0 0,}{\fs17 B}{\b0\i0 \f10 \fs13 =}{\b0\i0 0
,}{\b0\i0 andBin}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17 1}{\b0\i0 with}{\b0\i0
outputs}{\b0\i0 of}{\b0\i0 Di}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs16 1}{\b0\i0
and} Bo{\b0\i0 \f10 \fs13 =}{\i0 \fs16 1 }
0 \fi30 {\b0\i0 according}{\b0\i0 to}{\b0\i0 line}{\b0\i0 \fs17 2}{\b0\i0 i
n}{\b0\i0 Fig.}{\i0 \fs17 8-15. }\par
}
.{\b 81 }\par
}
}
\par
}
f0 8.76 \par
}
efer to Fig. 8-45. The inputs to the{\b \fs17 8s} FS are{\b\i A}{\f
10 \fs13 = }
uts of{\b\i \f30 \fs19 Di}{\dn006 \f10 \fs11 =}
and{\b\i \f3
0 \fs16 Bo=}
}
The}{\b0\i0 inputs}{\b0\i0 to}{\b0\i0 the}{\i0
8s}{\b0\i0 FS}{\b0\i0 in}{\b0\i0 Fig.}{\b0\i0 8-45}{\b0\i0 are} A{\b0
\i0\dn006 \f10 \fs11
= }

{\f30 \fs18 Bo}{\b0\i0 \f10 \fs14 =}{\b0\i0 0}{\b0\i0 according}{\b0\i0 to}
{\b0\i0 line}{\b0\i0 6}{\b0\i0 in}{\b0\i0 Fig.}{\b0\i0 8-15. }\par
}
{\phpg\posx6491\pvpg\posy1375\absw526\absh206 \f10 \fs17 \cf0 \f10 \fs17 \cf0 -,
{\b\i \f20 \fs17 B}{\dn006 \fs11 = }\par
}
\f20 \fs17 and}{\b\i \f20 \fs17
Bin}{\dn006 \fs13 = }\par
}
th \par
}
n the truth table in Fig. 8-15. \par
}
,{\i \fs17 B}{\f10 \fs13 =} 0, and{\b\i Bin}{\dn006 \f10 \fs11 = }\par
}
{\fs17 with}{\fs17 outputs}{\fs17 of}{\b\i \fs17
Di=}{\fs17 0}{\fs17
and }\par
}
f0 8.77
{\f20 \fs17 8.78 }\par
}
efer to Fig. 8-45. The difference showing{\fs17 on} the indicators is{\fs1
7 a} binary \par
}
\cf0 Refer to Fig. 8-45. This unit is a
i Ans.}
4-bit parallel subtractor \par
}
{\phpg\posx4787\pvpg\posy3045\absw285\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 -b
it \par
}
parallel, serial) \par
}
par
}
17 \cf0 Am.{\b0\i0
0110, }\par
}
adder,subtractor). \par
}
f0 8.79 \par
}
\cf0 List the binary differences at the output indicators of the 4-bi
t parallel subtractor circuit shown in
5 Fig. 8-46.

i Ans.}
The differences for the pulses shown in Fig. 8-46 are as follows
: \par
}
ulse{\b\i \fs17 a}{\f10 \fs13 =} 0010
e{\i \fs17 6}{\dn006 \f10 \fs11 =} 1000 \par
}
ulse{\b\i \fs16 c}{\f10 \fs14 =} 0100
e{\b\i \fs17 d}{\f10 \fs13 =} 1001 \par
}
ulse{\b\i \fs17 e}{\f10 \fs13 =} 0011
e{\b\i \f30 \fs18 f}{\f10 \fs14 =} 0011 \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 0001
e{\i h}{\f10 \fs13 =} 0111 \par
}
}
1{\fs17 1 }\par
}
ulse{\i \f10 \fs15 j}{\dn006 \f10 \fs11
=} 1101 \par
}
cf0 Minuend \par
}
\par
}
cf0 Subtrahend \par
}
\par
}
par
}
\par
}
I \par
}
\fs15 \cf0 Difference
\par}{\phpg\posx8405\pvpg\posy8541\absw1354\absh335 \sl-172 \b \f20 \fs15 \cf0 o
utput indicators \par
}
\cf0 Fig.{\f10 \fs16 8-46}{\b0 \fs17

Parallel-subtractor}{\b0 \fs17 pulsetrain}{\b0 \fs17 problem }\par
}
f0 8.80 \par
}
\cf0 Refer to Fig. 8-46. The subtractor probably contains
\i Ans.}{\i \f10 \fs14
(a)}
one{\i \fs17
(}{\i \fs17 6}{\i \fs1
7 )}
three \par
}
s17 \cf0 ( a ) \par
}
cf0 HS(s){\b0 \fs17 and }\par
}
cf0 ( b ){\b\i0 \fs17
FSs. }\par
}
cf0 8.81 \par
}
Refer to Fig. 8-46. The subtractor circuit is classified as a
\par}{\phpg\posx1471\pvpg\posy10755\absw4831\absh380 \sl-207 \f20 \fs17 \cf0 cir
cuit.{\b\i
Ans.}
combinational \par
}
(combinational, sequential) logic \par
}
cf0 8.82 \par
}
\cf0 Refer to Fig.{\b 8-24.} What{\fs17 is} the effect of grounding the{
\b \fs16 1s}{\b full} adder{\b\i Cin} input?
\i Ans.}
Grounding the 1s FA{\i \fs17 Cin} input shown in Fig. 8-24 has
the effect of converting the 1s full adder to a
25 half adder. \par
}
\cf0 The 7483{\fs17 TTL} IC is described as a 4-bit
\i Ans.}
parallel \par
}
(parallel, serial) adder{\b \fs17 DIP} integrated circuit. \par
}
16 \cf0 8.83 \par
}
cf0 8.84 \par
}
\cf0 Refer to Fig. 8-26. What is the{\fs17 sum} when the binary numbers
11101010 and 01001110 are added?

\i Ans.}{\b
sum}{\f10 \fs13 =} 100111000 \par
}
0 202 \par
}
}
}
f0 8.85 \par
}
\cf0 Refer to Fig. 8-26. What is the highest sum that could be generated
by the 8-bit parallel adder?
\i \fs17 Ans.}{\b \fs17
11111111}{\f10 \fs26 +}{\b\dn006 \fs17 11111111}{
\dn006 \f10 \fs11
=}{\b \fs17 111111110,} (255{\f10 \fs26 +} 255{\f10 \fs1
3 =}{\b \fs17 510,,). }
\fi33 Refer to Fig. 8-32. The XOR gates act like{\fs17
(AND} gates, inverters) when the mode control is
30 HIGH.{\b\i
Ans.}
inverters \par
}
\cf0 Refer to Fig. 8-32. This circuit acts as a 4-bit parallel
i \fs16 Ans.}
subtractor \par
}
hen the mode control input is HIGH. \par
}
f0 8.86 \par
}
f0 8.87 \par
}
f0 8.88 \par
}
\cf0 Draw a diagram of an 8-bit parallel adder/subtractor
using eight{\
b \fs17 FAs} and eight{\fs17 XOR} gates.
i Ans.}
See Fig.{\b \fs17 8-47. }\par
}
\cf0 Addition{\b0 or} subtraction
fi483 {\b0 \fs13 problem }
fi239 {\b0 \f10 \fs23 - }\par
}
\cf0 I
' \par
}
\par
}
13 \cf0 Cin \par
}
i \f20 \fs10 B6 }\par
}
}
s12 \cf0 A7 \par
}
s13 \cf0 A \par
}
\cf0 -I:
\f20 \fs13 FA }\par
}
s11 \cf0 B7{\b0\i0 \f10 \fs19 - }\par
}
@@@@@@(hJ@ \par
}
\cf0 Mode control
fi64 Subtract{\b0 \f10 \fs10 =}{\f10 \fs13 1 }
fi332 Add{\b0 \f10 \fs11 =}{\fs13 0 }\par
}
\cf0 Sum{\f30 \fs13 or}{\f20 \fs13 difference }\par
}
\cf0 Fig.{\f10 \fs16 8-47}{\b0 \fs17
8-bit}{\b0 \fs17 parallel}{\b0 \fs17
adder/subtractor}{\b0 \fs17
circuit }\par
}
0 CHAP.{\b0 \f20 \fs17 81 }\par
}
}
f0 203 \par
}

f0 8.89 \par
}
f0 8.90 \par
}
\cf0 Refer to Fig. 8-35. The output from the adder/subtractor is in wh
at code?
i \f10 \fs15 Am.}{\fs17
2s} complement notation
\fi28 Refer to Fig. 8-35. Why does this adder/subtractor circuit speci
fy the use{\fs16 of} 2s complement numbers?
i \fs17 Ans.}{\fs17
2s} complement notation is one method of representi
ng{\b\i \fs17 signed}{\b\i \fs17 numbers} in digital circuits. \par
}
\cf0 Refer to Fig. 8-35. The MSB in the result (sum or difference){\fs1
6 is} the
i \fs17 Ans.}
sign (0{\f10 \fs13 =} positive or{\fs17 1}{\f10 \fs13 =} ne
gative) \par
}
d{\f10 \fs26 + }\par
}
t. \par
}
f0 8.91 \par
}
f0 8.92 \par
}
8 to{\i \fs17 -55} by using{\fs16 2s} complement numbers. Use the pro
cedure shown in Fig. 8-36. \par
}
s17 \cf0 Ans.{\b0\i0 \fs17
See}{\b0\i0 \fs17 Fig.}{\b0\i0 \fs17 8-48. }\
par
}
{\phpg\posx3809\pvpg\posy4151\absw502\absh192 \f10 \fs15 \cf0 \f10 \fs15 \cf0 (+
{\f20 \fs17 18) }\par
}
\fs15 (-}{\f20 \fs17 55) }
8 {\f20 \fs17 -3710 }\par
}
\cf0 0o010010{\fs16
2s} complement augend
0 \fs26 +} 1100 1001{\fs17
2s} complement addend
54 1101 1011{\b \f30 \fs17 2s} Complement{\b sum }\par
}

f0 8.93 \par
}
0 \fs16 \cf0 Fig.{\f10 \fs15 8-48}{\b0 \fs17
Solution}{\b0 \fs17 to}{\b0 \
fs17 2s}{\b0 \fs17 complement}{\b0 \fs17 addition}{\b0 \fs17 problem }
f0 \fi21 {\b0 \fs17 Subtract}{\b0 \f10 \fs15 -}{\b0 \fs17 14}{\b0 \fs17 from
}{\b0 \fs17 +47}{\b0 \fs17 by}{\b0 \fs17 using}{\fs16 2s}{\b0 \fs17 com
plement}{\b0 \fs17 numbers.}{\b0 \fs17 Use}{\b0 \fs17 the}{\b0 \fs17 pro
cedure}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 8-37. }
\i \fs17 Ans.}{\b0 \fs17
See}{\b0 \fs17 Fig.}{\b0 \fs17 8-49. }\par
}
\cf0 ({\fs21 +}{\f20 \fs17 47) }
\fs10 ____ }
{\fs15 -(-}{\f20 \fs17
14) }
2 {\f20 \fs17 +6LO }\par
}
}
110010 \par
}
}
\fs9 \cf0 1{\b\i0 \f20 \fs10
I}{\b\i0 \f20 \fs10 1 }
b\i0 \f30 \fs17 0010}{\i0 \f20 \fs17 1111}{\i0 \f20 \fs17
Minuend }\par
}
{\i \f30 \fs18 oo00}{\f20 \fs17 1110}{\f20 \fs17
Subtrahend }
40 {\f20 \fs17 001}{\b \fs15 1}{\f20 \fs17 1101}{\f20 \fs17
2s}{\f20 \fs17
complement}{\f20 \fs17 difference }\par
}
\cf0 Fig.{\f10 \fs15 8-49}{\b0 \fs17
Solution}{\b0 to}{\f10 \fs16 2s}{\b0
\fs17 complement}{\b0 \fs17 subtraction}{\b0 \fs17 problem }\par
}
{\b \fs32 Flip-Flops}{\b \fs33 and}{\b \fs33 Other}{\b \fs33 Multivibrators }\
par
}
\cf0 9-1{\f20 \fs18
INTRODUCTION }
fi368 {\b0 \f20 \fs18 Logic}{\b0 \f20 \fs18 circuits}{\b0 \f20 \fs18 are}{\b0
\f20 \fs18 classified}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 two}{\b0 \f20 \fs18
broad}{\b0 \f20 \fs18 categories.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 group
s}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 gates}{\b0 \f20 \fs18 described}{\b0 \f
20 \fs18 thus}{\b0 \f20 \fs18 far'have }
\b0 \f20 \fs18 been}{\b0 \f20 \fs18 wired}{\b0 \f20 \fs18 as}{\b0\i \f20 \fs18
combinational}{\b0\i \f20 \fs18 logic}{\b0\i \f20 \fs18 circuits.}{\b0 \f20
\fs18 In}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 chapter}{\b0 \f20 \fs18 a}{\b
0 \f20 \fs18 valuable}{\b0 \f20 \fs18 type}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18
circuit}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 introduced:
}
\b0 \f20 \fs18 the}{\b0\i \f20 \fs18 sequential}{\b0\i \f20 \fs18 logic}{\b0\
i \f20 \fs18 circuit.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 basic}{\b0 \f20 \fs
18 building}{\b0 \f20 \fs18 block}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 combina
tional}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 the}{\b0 \f20
\fs18 logic}{\b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 basic
}
\b0 \f20 \fs18 building}{\b0 \f20 \fs18 block}{\b0 \f20 \fs18 of}{\b0 \f20 \
fs18 the}{\b0 \f20 \fs18 sequential}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18
circuit}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 the}{\b0\i \f20 \fs18 flip-fl
op}{\b0 \f20 \fs18 circuit.}{\b0 \f20 \fs18 Sequential}{\b0 \f20 \fs18 log
ic}{\b0 \f20 \fs18 circuits}{\b0 \f20 \fs18 are }
\b0 \f20 \fs18 extremely}{\b0 \f20 \fs18 valuable}{\b0 \f20 \fs18 because}{\b0
\f20 \fs18 of}{\b0 \f20 \fs18 their}{\b0\i \f20 \fs18 memory}{\b0\i \f20
\fs18 characteristic. }
fi368 {\b0 \f20 \fs18 Several}{\b0 \f20 \fs18 types}{\b0 \f20 \fs18 of}{\b0
\f20 \fs18 flip-flops}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 be}{\b0 \f20 \fs
18 detailed}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 chap
ter.}{\b0 \f20 \fs18 Flip-flops}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 also}{\
b0 \f20 \fs18 called}{\b0 \f20 \fs18 "latches," }
\b0 \f20 \fs18 "bistable}{\b0 \f20 \fs18 multivibrators,"}{\b0 \f20 \fs18 or
}{\b0 \f20 \fs18 "binaries."}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 term}{\b0
\f20 \fs18 "flip-flop"}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 be}{\b0 \f20
\fs18 used}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 book.
}{\b0 \f20 \fs18 Useful }
\b0 \f20 \fs18 flip-flops}{\b0 \f20 \fs18 can}{\b0 \f20 \fs18 be}{\b0 \f20 \fs
18 wired}{\b0 \f20 \fs18 from}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 gates
,}{\b0 \f20 \fs18 such}{\b0 \f20 \fs18 as}{\f20 \fs18 NAND}{\b0 \f20 \fs18
gates,}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 bought}{\b0 \f20 \fs18 in}{\b0
\f20 \fs18 IC}{\b0 \f20 \fs18 form.}{\b0 \f20 \fs18 Flip-flops}{\b0 \f20 \f
s18 are }
\b0 \f20 \fs18 interconnected}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 form}{\b0 \f2
0 \fs18 sequential}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 circuits}{\b0 \f20 \
fs18 for}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 storage,}{\b0 \f20 \fs18 timin
g,}{\b0 \f20 \fs18 counting,}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 sequencing.
}
fi367 {\b0 \f20 \fs18 Besides}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 bistable}{\
b0 \f20 \fs18 multivibrator}{\b0 \f20 \fs18 (flip-flop),}{\b0 \f20 \fs18 tw
o}{\b0 \f20 \fs18 other}{\b0 \f20 \fs18 types}{\b0 \f20 \fs18 of}{\b0 \f20
\fs18 multivibrators}{\f20 \fs18 (MVs)}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18
intro- }
\b0 \f20 \fs18 duced}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18
chapter.}{\b0 \f20 \fs18 The}{\b0\i \f20 \fs18 astable}{\b0\i \f20 \fs18

multivibrator}{\b0 \f20 \fs18
is}{\b0 \f20 \fs18 also}{\b0 \f20 \fs18 c
alled}{\b0 \f20 \fs18 a}{\b0\i \f20 \fs18 free-running}{\b0\i \f20 \fs18 M
V.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 astable}{\b0 \f20 \fs19 MV }
\b0 \f20 \fs18 produces}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 continuous}{\b0 \f
20 \fs18 series}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 square-wave}{\b0 \f20 \
fs18 pulses}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 commo
nly}{\b0 \f20 \fs18 used}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 a}{\b0 \f20 \f
s18 clock}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 digital }
\b0 \f20 \fs18 system.}{\b0 \f20 \fs18 The}{\b0\i \f20 \fs18 monostable}{\b0\i
\f20 \fs18 multiuibrator}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 also}{\b0 \f20
\fs18 called}{\b0 \f20 \fs18 a}{\b0\i \f20 \fs18 one-shot}{\b0\i \f20 \fs18
MV}{\b0 \f20 \fs19 in}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 it}{\b0 \f20
\fs18 produces}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 single}{\b0 \f20 \fs18 pu
lse }
\b0 \f20 \fs18 when}{\b0 \f20 \fs18 triggered}{\b0 \f20 \fs18 by}{\b0 \f20 \fs
18 an}{\b0 \f20 \fs18 external}{\b0 \f20 \fs18 source. }\par
}
7 \cf0 9-2 \par
}
\f30 \fs20 \cf0 RS{\i0 \f20 \fs18 FLIP-FLOP }
{\b0\i0 \f20 \fs18 The}{\b0\i0 \f20 \fs18 most}{\b0\i0 \f20 \fs18 basic}{\b
0\i0 \f20 \fs18 flip-flop}{\b0\i0 \f20 \fs18 is}{\b0\i0 \f20 \fs18 called}{\
b0\i0 \f20 \fs18 the}{\b0 \f20 \fs19 RS}{\b0 \f20 \fs18 flip-flop.}{\i0 \f2
0 \fs18 A}{\b0\i0 \f20 \fs18 block}{\b0\i0 \f20 \fs18 logic}{\b0\i0 \f20 \f
s18 symbol}{\b0\i0 \f20 \fs18 for}{\b0\i0 \f20 \fs18 the}{\b0 \f20 \fs19 R
S}{\b0\i0 \f20 \fs18 flip-flop}{\b0\i0 \f20 \fs18 is }\par
}
hown in Fig.{\i \fs18 9-1.} The logic symbol shows two inputs, labeled{\i \fs18
set}{\b \fs18 (S)} and{\i \fs18 reset}{\i (R),}on the left. The
i \fs19 RS} flip-flop in this symbol has active LOW inputs, shown as sm
all bubbles at the{\b \fs18 S} and{\i \fs19 R} inputs.
0 Unlike logic gates, flip-flops have{\fs18 two} complementary outputs. T
he outputs are typically labeled Q
(say "not Q or Q not"). The{\fs18 Q} output is considered the "normal" o
utput and{\fs18 is} the one most
. The other output{\i \fs29 (12)} is simply the complement of output Q
, and it is referred to as the
lementary output. Under normal conditions these outputs are always complementar
y. Hence, if
\par}{\phpg\posx839\pvpg\posy7617\absw9162\absh1512 \sl-239 \f20 \fs18 \cf0 Q{\f
10 \fs14 =}{\fs19 1,} then{\f10 \fs14
=}{\fs18 0;} or{\fs18 if} Q{\d
n006 \f10 \fs13 =}{\fs18 0,} then{\dn006 \f10 \fs13
=}{\fs19 1. }\par
}
cf0 a \par
}
\cf0 Reset \par

}
s15 \cf0 R \par
}
f{\f20 \fs15 Complementary }\par
}
20 \fs16 \cf0 Fig. 9-1{\b0 \fs16
Logic}{\b0 symbol}{\b0 \fs17 for}{\i \fs1
7 RS}{\fs16 flip-flop }
cf0 \fi354 {\b0 \fs18 The}{\i \fs19 RS}{\b0 \fs18 flip-flop}{\b0 \fs18 can}
{\b0 \fs18 be}{\b0 \fs18 constructed}{\b0 \fs18 from}{\b0 \fs18 logic}{\b
0 \fs18 gates.}{\i \f10 \fs17 An}{\b0\i \fs19 RS}{\b0 \fs18 flip-flop}{\b
0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 wired}{\b0 \fs18 from}{\b0 \fs18 t
wo }
{\fs18 NAND}{\b0 \fs18 gates}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-2a
.}{\b0 \fs18 Note}{\b0 \fs18 the}{\b0 \fs18 characteristic}{\b0 \fs18 feedb
ack}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 of}{\b0 \fs1
8 one}{\fs18 NAND}{\b0 \fs18 gate}{\b0 \fs18 into }
{\b0 \fs18 the}{\b0 \fs18 input}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18
other}{\b0 \fs18 gate.}{\fs18 As}{\b0 \fs18 with}{\b0 \fs18 logic}{\b0 \fs
18 gates,}{\b0 \fs18 a}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 defi
nes}{\b0 \fs18 the}{\b0 \fs18 operation}{\b0 \fs18 of}{\b0 \fs18 the}{\b
0 \fs18 flip-flop. }
{\b0 \fs18 Line}{\b0 \fs19 1}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 truth}{\
b0 \fs18 table}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-2b}{\b0 \fs18 i
s}{\b0 \fs18 called}{\b0 \fs18 the}{\b0\i \fs18 prohibited}{\b0\i \fs18 stat
e}{\b0 \fs18 in}{\b0 \fs18 that}{\b0 \fs18 it}{\b0 \fs18 drives}{\b0 \fs18
both}{\b0 \fs18 outputs}{\b0 \fs18 to}{\b0 \fs18 1,}{\b0 \fs18 or }
{\b0 \fs18 HIGH.}{\b0 \fs18 This}{\b0 \fs18 condition}{\b0 \fs18 is}{\b0 \fs1
8 not}{\b0 \fs18 used}{\b0 \fs18 on}{\b0 \fs18 the}{\i \fs19 RS}{\b0 \fs18
flip-flop.}{\b0 \fs18 Line}{\b0 \fs18 2}{\b0 \fs18 of}{\b0 \fs18 the}{\b0
\fs18 truth}{\b0 \fs18 table}{\b0 \fs18 shows}{\b0 \fs18 the}{\b0\i \fs18 s
et}{\b0 \fs18 condition }
{\b0 \fs19 of}{\b0 \fs18 the}{\b0 \fs18 flip-flop.}{\b0 \fs18 Here}{\b0 \fs18
a}{\b0 \fs18 LOW,}{\b0 \fs18 or}{\b0 \fs18 logical}{\b0 \fs18 0,}{\b0 \fs1
8 activates}{\b0 \fs18 the}{\b0 \fs18 set}{\i \f10 \fs17 (}{\i \f10 \fs17 S
}{\i \f10 \fs17 )}{\b0 \fs18 input.}{\b0 \fs18 That}{\b0 \fs18 sets}{\b0 \fs
18 the}{\b0 \fs18 normal}{\b0\i \fs17 Q}{\b0 \fs18 output}{\b0 \fs18 to }
{\b0 \fs18 HIGH,}{\b0 \fs18 or}{\b0 \fs18 1,}{\b0 \fs18 as}{\b0 \fs18 shown
}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \fs18 table.}{\b0 \fs18
This}{\b0 \fs18 set}{\b0 \fs18 condition}{\b0 \fs18 works}{\b0 \fs18 out}{\
b0 \fs18 if}{\b0 \fs18 the}{\fs18 NAND}{\b0 \fs18 circuit}{\b0 \fs18 shown
}{\b0 \fs18 in }
{\b0 \fs18 Fig.}{\b0\i \fs18 9-2a}{\b0 \fs18 is}{\b0 \fs18 analyzed.}{\fs18
A}{\b0 \fs18 0}{\b0 \fs18 at}{\b0 \fs18 gate}{\b0\i \fs18 1}{\b0 \fs18 gene
rates}{\b0 \fs18 a}{\b0 \fs19 1}{\b0 \fs18 at}{\b0 \fs18 output}{\b0\i \fs17
Q.}{\b0 \fs18 This}{\b0 \fs19 1}{\b0 \fs18 is}{\b0 \fs18 fed}{\b0 \fs18
back}{\b0 \fs18 to}{\b0 \fs18 gate}{\b0 \fs18 2.}{\b0 \fs18 Gate}{\b0 \fs19
2}{\b0 \fs18 now }
{\b0 \fs18 has}{\b0 \fs19 two}{\b0\i \fs18 1s}{\b0 \fs18 applied}{\b0 \fs18
to}{\b0 \fs18 its}{\b0 \fs18 inputs,}{\b0 \fs18 which}{\b0 \fs18 forces}{\b0
\fs18 the}{\b0 \fs18 output}{\b0 \fs18 to}{\b0 \fs18 0.}{\b0 \fs18 Output}
{\b0 \fs18
is}{\b0 \fs18 therefore}{\b0 \fs18 0,}{\b0 \fs18 or}{\b0 \fs1
8 LOW.}{\b0 \fs18 Line}{\b0 \fs19 3 }
{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-2b}{\b0 \fs18 is}{\b0 \fs18 the
}{\b0\i \fs18 reset}{\b0 \fs18 condition.}{\b0 \fs18 The}{\b0 \fs18 LOW,}{\
b0 \fs18 or}{\b0 \fs18 0,}{\b0 \fs18 activates}{\b0 \fs18 the}{\b0 \fs18 re
set}{\b0 \fs18 input.}{\b0 \fs18 This}{\b0 \fs18 clears}{\b0 \fs18 (or}{\b0
\fs18 resets)}{\b0 \fs18 the }
{\b0 \fs18 normal}{\fs18 Q}{\b0 \fs18 output}{\b0 \fs18 to}{\b0 \fs19 0.}{\
b0 \fs18 The}{\b0 \fs18 fourth}{\b0 \fs18 line}{\b0 \fs18 of}{\b0 \fs18 th
e}{\b0 \fs18 table}{\b0 \fs18 shows}{\b0 \fs18 the}{\b0 \fs18 disabled,}{\b0
\fs18 or}{\b0\i \fs18 hold,}{\b0 \fs18 condition}{\b0 \fs18 of}{\b0 \fs18
the}{\b0\i \fs18 RS }
\fi4276 {\b0\i \fs18 204 }\par
}
0 CHAP.{\i0 \fs16 91 }\par
}
{\phpg\posx3257\pvpg\posy549\absw4039\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 FL
IP-FLOPS AND OTHER MULTIVIBRATORS \par
}
\par
}
15 \cf0 S - - o \par
}
22 \cf0 Q \par
}
\cf0 Mode
97 {\fs17 of }
ation
Prohibited
\par}{\phpg\posx5755\pvpg\posy1515\absw791\absh1632 \sl-218 \f20 \fs17 \cf0 Set
\par}{\phpg\posx5755\pvpg\posy1515\absw791\absh1632 \sl-213 \f20 \fs17 \cf0 Rese
t
\par}{\phpg\posx5755\pvpg\posy1515\absw791\absh1632 \sl-218 \f20 \fs17 \cf0 Hold
\par
}
puts \par
}
{\i \fs17 0 }
0 \fs16 0 }

6 1
7 1 \par
}
{\i \fs17 0 }
0 \fs16 1 }
0 0
9 1 \par
}
tputs
fi86 {\fs21 Q}{\fs21
Q }\par
}
\fs17 0 }\par
}
\fs17 1 }\par
}
{\phpg\posx8175\pvpg\posy3105\absw790\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 no
change \par
}
a){\fs15 Wired}{\fs15 using} NAND{\fs15 gates }\par
}
6){\fs15 Truth}{\fs15 table }\par
}
0 \fs17 \cf0 Fig.{\fs17 9-2}{\i
RS}{\b0 \fs17 flip-flop }
f0 {\b0 \fs19 flip-flop.}{\b0 \fs19 The}{\b0 \fs19 outputs}{\b0 \fs19 remain}
{\b0\i \fs19 as}{\b0\i \fs19 they}{\i \fs18 were}{\b0 \fs19 before}{\b0 \fs
19 the}{\b0 \fs19 hold}{\b0 \fs19 condition}{\b0 \fs19 existed.}{\b0 \fs19
There}{\b0 \fs19 is}{\b0 \fs19 no}{\b0 \fs19 change}{\b0 \fs19 in}{\b0 \fs19
the }
\b0 \fs19 outputs}{\b0 \fs19 from}{\b0 \fs19 their}{\b0 \fs19 previous}{\b0 \
fs19 states. }
fi364 {\b0 \fs19 Note}{\b0 \fs19 that,}{\b0 \fs19 when}{\b0 \fs19 the}{\b0 \f
s19 truth}{\b0 \fs19 table}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 9-2b}{\
b0 \fs19 refers}{\b0 \fs19 to}{\b0 \fs19 the}{\i \fs19 ser}{\b0 \fs19 cond
ition,}{\b0 \fs19 it}{\b0 \fs19 means}{\b0 \fs19 setting}{\b0 \fs19 output}{
\b0 \fs18 Q }
\b0 \fs19 to}{\b0 \fs18 1.}{\b0 \fs19 Likewise,}{\b0 \fs19 the}{\i \fs18 res
et}{\b0 \fs19 condition}{\b0 \fs19 means}{\b0 \fs19 resetting}{\b0 \fs19 (c
learing)}{\b0 \fs19 output}{\b0 \fs18 Q}{\b0 \fs19 to}{\b0\i \fs18 0.}{\b0

\fs19 The}{\b0 \fs19 operating}{\b0 \fs19 conditions }
\b0 \fs19 therefore}{\b0 \fs19 refer}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19
normal}{\b0 \fs19 output.}{\b0 \fs19 Note}{\b0 \fs19 that}{\b0 \fs19 the}{
\b0 \fs19 complementary}{\b0 \fs19 output}{\b0\i \f10 \fs26 (0) }
\b0 \fs19 Because}{\b0 \fs19 of}{\b0 \fs19 its}{\b0 \fs19 typical}{\b0 \fs1
9 function}{\b0 \fs19 of}{\b0 \fs19 holding}{\b0 \fs19 data}{\b0 \fs19
temporarily,}{\b0 \fs19 the}{\i \fs19 RS}{\b0 \fs19 flip-flop}{\b0 \fs19
is}{\b0 \fs19 often}{\b0 \fs19 called}{\b0 \fs19 the}{\b0\i \fs19 RS }
\b0\i \fs19 latch.}{\i \fs19 RS}{\b0 \fs19 latches}{\b0 \fs19 can}{\b0 \fs1
9 be}{\b0 \fs19 wired}{\b0 \fs19 from}{\b0 \fs19 gates}{\b0 \fs19 or}{\b0
\fs19 purchased}{\b0 \fs19 in}{\b0 \fs19 IC}{\b0 \fs19 form.}{\b0 \fs19
Think}{\b0 \fs19 of}{\b0 \fs19 the}{\i \fs19 RS}{\b0 \fs19 flip-flop}{\
b0 \fs19 as}{\b0 \fs19 a }
\b0 \fs19 memory}{\b0 \fs19 device}{\b0 \fs19 that}{\b0 \fs19 will}{\b0 \fs19
hold}{\b0 \fs19 a}{\b0 \fs19 single}{\b0 \fs19 bit}{\b0 \fs19 of}{\b0 \fs
19 data. }
}
s exactly the opposite. \par
}
f0 9.1 \par
}
efer to{\fs18 Fig.}{\fs18 9-1.} This{\b\i \fs19 RS} flip-flop has active
}
HIGH, LOW) inputs. \par
}
\cf0 As indicated by the small bubbles at the inputs of the logic symb
ol in Fig. 9-1, the{\b\i \f30 \fs19 RS} flip-flop has
ve LOW inputs. \par
}
f the normal output of the{\i RS} flip-flop is HIGH, then output{\i \fs18 Q}{
\f10 \fs14 = }
\fs18 (0,}{\b \fs18 1). }
}
\cf0 \par}{\phpg\posx7931\pvpg\posy8419\absw1247\absh341 \sl-191 \f10 \fs15 \cf0 {\f2
0 \fs18 (0,l)}{\f20 \fs19 and}{\f20 \fs18 Q}{\fs14 = }\par
}
7 \cf0 9.2 \par
}

\cf0 If{\fs17 the}{\fs17 normal}{\fs17 output}{\fs17 of}{\fs17 the}{\
b\i \f30 \fs19 RS}{\fs17 flip-flop}{\fs17 is}{\fs17 HIGH,}{\fs17 then}{\f
s17 output}{\fs16 Q}{\dn006 \f10 \fs11 =}{\fs17 1}{\fs17 and}{\i \f10 \f
s23 0}{\dn006 \f10 \fs11 =}{\fs17 0. }
{\fs19 Activating}{\fs19 the}{\fs19 reset}{\fs19 input}{\fs19 with}{\fs19 a
}{\fs19
(HIGH,}{\fs19 LOW)}{\fs19 effectively}{\fs19
(clears,}{\fs19 sets)}{\fs19 output }\par
}
Q{\fs19 to}{\fs19 a}{\fs19 logical }
}
\cf0 (0,{\i0 \fs18 1). }\par
}
cf0 9.3 \par
}
Activating the reset input with a LOW clears output Q to 0. \par
}
cf0 9.4 \par
}
List the{\i \fs19 binary} outputs at the normal output{\b \fs18 (Q)}{\fs19 o
f} the{\b\i RS} flip-flop shown in Fig. 9-3. \par
}
+-PI-? \par
}
14 \cf0 j \par
}
14 \cf0 i \par
}
s14 \cf0 h \par
}
s14 \cf0 g \par
}
14 \cf0 f \par
}
s14 \cf0 e \par
}
s14 \cf0 d \par
}
s14 \cf0 c \par
}
s14 \cf0 b \par
}
s14 \cf0 a \par
}
\cf0 Fig.{\fs17 9-3}{\fs17
RS}{\b0 \fs17 flip-flop}{\b0 \fs17 pulse-trai
n}{\b0 \fs17 problem }\par
}
\par
}
}
AP.{\f10 \fs14 9 }\par
}
\cf0 Solution:
fi354 {\b0 \fs16 The}{\b0 \fs16 binary}{\b0 \fs16 outputs}{\b0 \fs16 at}{\b
0 \fs16 output}{\b0\i \f10 \fs15 Q}{\b0 \fs16 shown}{\b0 \fs16 in}{\b0 \f
s16 Fig.}{\b0 \fs16 9-3}{\b0 \fs16 are}{\b0 \fs16 as}{\b0 \fs16 follows:
}\par
}
lse{\i \f10 \fs13 a}{\f10 \fs13 =}{\fs16 1 }
{\i \fs17 b}{\f10 \fs13 =}{\fs16 1 }
{\i \f10 \fs14 c}{\f10 \fs13 =}{\fs17 0 }\par
}
lse{\fs16 d}{\dn006 \f10 \fs11 =} 0
{\i \fs17 e}{\f10 \fs13 =}{\fs17 0 }
}
ulse{\i \fs15 g}{\dn006 \f10 \fs11 =}{\fs16 1 }
e{\i h}{\dn006 \f10 \fs11 =}{\fs17 1 }
e{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =}{\b \f10 \fs15 1} (prohibited st
ate) \par
}
lse{\fs15 j}{\dn006 \f10 \fs11 =} 0 \par
}
7 \cf0 9.5 \par
}
ist the{\i \fs18 binary} outputs at output
\fs17 Solution: }
55 {\fs16 The}{\fs16 binary}{\fs16 outputs}{\fs16 at}{\fs16 output }\par

}
lse{\i \f10 \fs14 a}{\f10 \fs13 =} 0
{\i b}{\f10 \fs13 =}{\fs17 0 }
{\i \f10 \fs14 c}{\f10 \fs13 =}{\fs16 1 }\par
}
lse{\b\i \fs16 d}{\dn006 \f10 \fs11 =}{\fs16 1 }
{\i \fs17 e}{\f10 \fs13 =}{\fs16 1 }
{\fs17 f}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
\cf0 of the{\i \fs18 RS} flip-flop shown in Fig.{\fs18 9-3. }
{\fs16 (Fig.}{\fs16 9-3)}{\fs16 are}{\fs16 as}{\fs16 follows: }\par
}
ulse{\fs15 g}{\dn006 \f10 \fs10 =}{\fs17 0 }
e{\i h}{\dn006 \f10 \fs11 =}{\fs17 0 }
e{\b\i \f30 \fs17 i}{\f10 \fs13 =}{\fs16 1} (prohibited state) \par
}
lse{\fs15 j}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
f0 9.6 \par
}
ist the mode of operation{\fs18 of} the{\i \fs19 RS} flip-flop for each in
put pulse shown in Fig. 9-3.
\fs17 Solution: }
55 {\fs16 The}{\fs16 modes}{\fs16 of}{\fs16 operation}{\fs16 of}{\fs16
the}{\i \fs17 RS}{\fs16 flip-flop}{\fs16 (Fig.}{\fs16 9-3)}{\fs16 are}{\f
s16 as}{\fs16 follows: }\par
}
ulse{\i \f10 \fs15 a}{\f10 \fs13 =} set
e{\i \fs17 b}{\dn006 \f10 \fs11 =} hold
e{\i \f10 \fs14 c}{\dn006 \f10 \fs11 =} reset \par
}
ulse{\fs16 d}{\dn006 \f10 \fs11 =} hold
e{\i \fs17 e}{\f10 \fs13 =} reset
e{\fs17 f}{\dn006 \f10 \fs11 =} hold \par
}
ulse{\i \fs15 g}{\f10 \fs13 =} set

e{\i \fs17 h}{\dn006 \f10 \fs11 =} hold
e{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =} prohibited \par
}
ulse{\fs15 j}{\dn006 \f10 \fs11 =} reset \par
}
\cf0 9-3{\fs18
CLOCKED}{\i \fs18 RS}{\fs18 FLIP-FLOP }
fi376 {\b0 \fs18 The}{\b0 \fs18 basic}{\b0\i \fs18 RS}{\b0 \fs18 latch}{\b0
\fs18 is}{\b0 \fs18 an}{\b0\i \fs18 asynchronous}{\b0 \fs18 device.}{\b0
\fs18 It}{\b0 \fs18 does}{\b0\i \fs18 not}{\b0 \fs18 operate}{\b0 \fs18 i
n}{\b0 \fs18 step}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18 clock}{\b0 \fs18
or}{\b0 \fs18 timing }
\b0 \fs18 device.}{\b0 \fs18 When}{\b0 \fs18 an}{\b0 \fs18 input}{\b0 \fs18
(such}{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 set}{\b0 \fs18 input)}{\b0 \fs
18 is}{\b0 \fs18 activated,}{\b0 \fs18 the}{\b0 \fs18 normal}{\b0 \fs18 out
put}{\b0 \fs18 is}{\b0 \fs18 immediately}{\b0 \fs18 activated }
\b0 \fs18 just}{\b0 \fs18 as}{\b0 \fs18 in}{\b0 \fs18 combinational}{\b0 \fs
18 logic}{\b0 \fs18 circuits.}{\b0 \fs18 Gating}{\b0 \fs18 circuits}{\b0 \f
s18 and}{\b0\i \fs18 RS}{\b0 \fs18 latches}{\b0 \fs18 operate}{\b0 \fs18
asynchronously. }
fi376 {\b0 \fs18 The}{\b0 \fs18 clocked}{\b0\i \fs18 RSflip-flop}{\b0 \fs18
adds}{\b0 \fs18 a}{\b0 \fs18 valuable}{\b0\i \fs18 synchronous}{\b0 \fs18
feature}{\b0 \fs18 to}{\b0 \fs18 the}{\b0\i \fs18 RS}{\b0 \fs18 latch.
}{\b0 \fs18 The}{\b0 \fs18 clocked}{\b0\i \fs18 RS }
\b0 \fs18 flip-flop}{\b0\i \fs18 operates}{\b0\i \fs18 in}{\b0\i \fs18 step}{
\b0\i \fs18 with}{\b0\i \fs18 the}{\b0\i \fs18 clock}{\b0 \fs18 or}{\b0 \fs
18 timing}{\b0 \fs18 device.}{\b0 \fs18 In}{\b0 \fs18 other}{\b0 \fs18 wor
ds,}{\b0 it}{\b0 \fs18 operates}{\b0 \fs18 synchronously.}{\fs18 A }
\b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 c
locked}{\b0\i \fs18 RS}{\b0 \fs18 flip-flop}{\b0 \fs18 is}{\b0 \fs18 shown
}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-4.}{\b0 \fs18 It}{\b0 \fs18 h
as}{\b0 \fs18 the}{\b0 \fs18 set}{\i \fs18 (}{\i \fs18 S}{\i \fs18 )}{\b0 \
fs18 and}{\b0 \fs18 reset}{\b0\i \fs19 (}{\b0\i \fs19 R}{\b0\i \fs19 )}{\b0
\fs18 inputs }
fi20 {\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 added}{\b0 \fs18 clock}{\b0 \fs
18 (CLK)}{\b0 \fs18 input.}{\b0 \fs18 The}{\b0 \fs18 clocked}{\b0\i \fs18
RS}{\b0 \fs18 flip-flop}{\b0 \fs18 has}{\b0 \fs18 the}{\b0 \fs18 customary}
{\b0 \fs18 normal}{\b0 \fs18 output}{\b0\i \fs18 (}{\b0\i \fs18 Q}{\b0\i \fs
18 )}{\b0 \fs18 and }
\b0 \fs18 complementary}{\b0 \fs18 output}{\b0 \fs17 (Q). }\par
}
nputs \par
}
\cf0 Set
fs14 Clock- }
Reset-R \par
}
\fs15 \cf0 FF{\b0\i \fs19
Q }
fs15 CLK }
i598 {\b0\i \f10 \fs20 0- }\par
}
utputs \par
}
20 \fs17 \cf0 Fig.{\fs16 9-4}{\b0 \fs16
Logic}{\b0 \fs16 symbol}{\b0 \fs16
for}{\b0 \fs16 clocked}{\b0\i RS}{\b0 \fs16 flip-flop }
cf0 \fi364 {\b0 \fs18 The}{\b0 \fs18 clocked}{\i \fs18 RS}{\b0 \fs18 flipflop}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 implemented}{\b0 \fs18 with
}{\b0 \fs18 NAND}{\b0 \fs18 gates.}{\b0 \fs18 Figure}{\b0\i \fs18 9-5a}{
\b0 \fs18 illustrates}{\b0 \fs18 two }
{\fs18 NAND}{\b0 \fs18 gates}{\b0 \fs18 being}{\b0 \fs18 added}{\b0 \fs18 to
}{\b0 \fs18 the}{\b0\i \fs18 RS}{\b0 \fs18 latch}{\b0 \fs18 (flip-flop)}{\
b0 \fs18 to}{\b0 \fs18 form}{\b0 \fs18 the}{\b0 \fs18 clocked}{\b0\i \fs18
RS}{\b0 \fs18 flip-flop.}{\b0 \fs18 NAND}{\b0 \fs18 gates}{\b0 \fs18 3 }
{\b0 \fs18 and}{\fs18 4}{\b0 \fs18 add}{\b0 \fs18 the}{\b0 \fs18 clocked
}{\b0 \fs18 feature}{\b0 \fs18 to}{\b0 \fs18 the}{\i \fs18 RS}{\b0 \fs18
latch.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 just}{\b0 \fs18 gates}
{\b0 \fs18 1}{\b0 \fs18 and}{\b0 \fs18 2}{\b0 \fs18 form}{\b0 \fs18 the}{
\b0\i \fs18 RS}{\b0 \fs18 latch,}{\b0 \fs18 or }
{\b0 \fs18 flip-flop.}{\b0 \fs18 Note}{\b0 \fs18 also}{\b0 \fs18 that,}{\b0
\fs18 because}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 inverting}{\b0 \fs1
8 effect}{\b0 \fs18 of}{\b0 \fs18 gates}{\b0 \fs18 3}{\b0 \fs18 and}{\b0
\fs18 4,}{\b0 \fs18 the}{\b0 \fs18 set}{\fs19 (S)}{\b0 \fs18 and}{\b0
\fs18 reset}{\b0\i \fs18 (}{\b0\i \fs18 R}{\b0\i \fs18 ) }
{\b0 \fs18 inputs}{\b0 \fs18 are}{\b0 \fs18 now}{\b0 \fs18 active}{\b0 \fs18
HIGH}{\b0 \fs18 inputs.}{\b0 \fs18 The}{\b0 \fs18 clock}{\b0 \fs18 (CLK)}{\
b0 \fs18 input}{\b0 \fs18 triggers}{\b0 \fs18 the}{\b0 \fs18 flip-flop}{\b0
\fs18 (enables}{\b0 \fs18 the}{\b0 \fs18 flip-flop) }
{\b0 \fs18 when}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs1
8 goes}{\b0 \fs18 HIGH.}{\b0 \fs18 The}{\b0 \fs18 clocked}{\b0\i \fs18
RS}{\b0 \fs18 flip-flop}{\b0 \fs18 is}{\b0 \fs18 said}{\b0 \fs18 to}{\b
0 \fs18 be}{\b0 \fs18 a}{\b0\i \fs18 level-triggered}{\b0 \fs18 device.
}
{\b0 \fs18 Anytime}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs1
8 is}{\b0 \fs18 HIGH,}{\b0 \fs18 the}{\b0 \fs18 information}{\b0 \fs18 at}{
\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 inputs}{\b0\i \fs18 (}{\b0\i \fs18
R}{\b0 \fs18 and}{\fs18 S)}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 trans
ferred}{\b0 \fs18 to }
{\b0 \fs18 the}{\b0 \fs18 outputs.}{\b0 \fs18 It}{\b0 \fs18 should}{\b0 \fs1
8 be}{\b0 \fs18 emphasized}{\b0 \fs18 that}{\b0 \fs18 the}{\fs18 S}{\b0
\fs18 and}{\b0\i \fs18 R}{\b0 \fs18 inputs}{\b0 \fs18 are}{\b0 \fs18 act
ive}{\b0 \fs18 during}{\b0 \fs18 the}{\b0 \fs18 entire}{\b0 \fs18 time}{\b0
\fs18 the }

{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 level}{\b0 \fs18 is}{\b0 \fs18
HIGH.}{\b0 \fs18 The}{\b0 \fs18 HIGH}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18
clock}{\b0 \fs18 pulse}{\b0 \fs18 may}{\b0 \fs18 be}{\b0 \fs18 thought}{\b
0 \fs18 of}{\b0 \fs18 as}{\b0 \fs18 an}{\b0 \fs18 enabling}{\b0 \fs18 puls
e. }\par
}
cf0 FLI{\f10 \fs16 P-}{\fs17 FLOPS}{\f30 \fs19 AN}{\f10 \fs17 D} OTI{\f10 \fs1
7 1}{\f10 \fs17 ER}{\fs18 MULTI}{\f30 \fs19 V}{\f10 \fs16 1}{\f30 \fs20 BRAT0}
{\f30 \fs20 RS }\par
}
f0 207 \par
}
\cf0 Fig. 9-5{\f10 \fs16
Clwkcd}{\i \f10 RS}{\fs16 flip-flop }\par
}
\cf0 The truth table{\fs20 in} Fig.{\fs19 9-56} details the opcration{\fs
19 of} thc clockcd{\b\i \fs19 RS} flip-flop. Thc hold modc{\fs19 of }
ation is described{\fs20 in} linc{\b \f10 \fs17 1}{\fs19 of} thc truth ta
blc. When{\fs19 a} clock pulsc arrives at the{\fs19 CLK} input{\fs19 (with }
i \fs19 0s} at thc{\b \f30 \fs21 S} and{\fs20 R} inputs), thc outputs{\b\i \
f10 \fs18 (10}{\b\i \fs15 rroi}{\b\i \fs18 c.lrurip.} The outputs stay the s
ame{\fs19 as} they wcrc bcforc
clock pulse. This modc might also bc dcscribcd as the{\b\i \fs19 disahktcl} co
ndition{\fs19 of} the flip-flop. Line{\fs20 2} is
rcsct mode.{\fs19 The} normal output{\b\i (Q)}{\fs19 will}{\b \f30 \fs20
bc} clcarcd{\fs19 or} reset{\fs19 to}{\b \fs19 0} when a HIGH activate
s thc{\b\i \fs20 R }
t and a{\b \fs19 clock} pulse arrives at the{\fs19 CLK} input. It{\fs19
will}{\b \f30 \fs21 tw:} notcd that just placing{\b\i \f10 \fs17 R}{\f10
\fs14 =}{\b\dn006 \f10 \fs17 1} and{\b\i \f10 \fs18 S}{\f10 \fs15 =}{\f
s19 0 }
\fs20 docs}{\fs19 not} immcdiatcly rcxt the flip-flop. The flip-flop waits
until the clock pulsc{\b \f10 \fs16 goes}{\fs19 from} LOW{\fs19 to }
\f30 \fs22 HIGH,}and then thc flip-flop resets. This{\fs19 unit} operates synch
ronously,{\fs19 or}{\fs19 in} stcp with the clock. Line{\fs20 3 }
19 of} the truth tablc describes the set condition{\fs19 of} the flip
-flop.{\b \f10 \fs17 A}{\fs19 HIGH} activatcs the{\b \f10 \fs16
S} inpu
t (with
20 R}{\f10 \fs14 =}{\fs19 0} and a{\fs20 HIGH} clock pulsc), sctting thc{
\fs19 Q} output{\fs19 to}{\b \f10 \fs18 1.} Line{\b \f10 \fs17 4}{\fs19
of} thc{\fs18 truth} tahlc is{\b \fs18 a} prohibited
\par}{\phpg\posx875\pvpg\posy4663\absw9328\absh5603 \sl-237 \f20 \fs19 \cf0 comb
ination (all inputs{\b \f10 \fs17 1)} and is{\fs19 not} used because{\fs18
it} drives both outputs HIGH.
84 {\b\i \fs19 Warefornu,}{\fs20 or}{\b\i \f10 \fs17 riming}{\b\i diagranrs,

}{\fs20 arc} widely used and are quite{\fs20 useful}{\fs19 for} working{\
fs19 with} flip-flops
scqucntial logic circuits. Figure{\fs18 9-6}{\b \f10 \fs18 is}{\b\dn006 \f10 \
fs12 il} timing diagram{\fs19 for} the clocked{\fs19 RS} flip-flop.{\b \fs20
The} top three
19 lincs} rcprcscnt thc binary signals at thc clock, set, and rcsct inputs. On
ly{\fs19 a} single output{\f10 \fs17 ((2)}{\fs19 is} shown
\par}{\phpg\posx875\pvpg\posy4663\absw9328\absh5603 \sl-237 \f20 \fs19 \cf0 acro
ss the bottom. Beginning at the Icft. clock pulsc{\fs18 1} arrives but has{\f
s20 no} effect{\fs20 on}{\b\i \f30 \fs22 Q} because inputs{\b \f30 \fs21 S
}
\b\i R} arc{\fs19 in} the hold mode. Output{\b\i \f30 \fs21 Q} therefore st
ays at{\b \fs19 0.} At{\fs18 point}{\b\i \f10 \fs15 a}{\fs19 on} the timing
diagram, the{\fs19 set }
t{\fs19 is} activated{\fs17 to}{\b \f10 \fs16 a} HIGH. After{\b a} ti
mc at point{\fs19 6.} output{\b\i Q} is{\fs18 sct}{\fs19 to}{\b \f10 \
fs17 1.} Notc that thc flip-flop
\par}{\phpg\posx875\pvpg\posy4663\absw9328\absh5603 \sl-234 \f20 \fs19 \cf0 wait
ed until clock pulsc 2 started{\fs17 t}{\fs17 o}{\b \f10 \fs16 go} from{\b
\f30 \fs21 LOW}{\fs19 to} HIGH{\b \fs19 before} output{\b \fs19 Q}{\b \f
10 \fs16 was} sct. Pulsc{\fs19 3} scnscs
inputs{\b\i \fs20 (}{\b\i \fs20 R} and{\b \f10 \fs18 S)}{\fs19 in} the hold
modc, and thcrcforc the output does{\fs20 not} change.{\b \f10 \fs17 At}{\fs1
8 point}{\b\i \fs19 c} the rcsct
t{\fs19 is} activatcd with a {\f63 \u8364\'3f}iIGIi.{\b \f10 \fs18 A} short tim
e latcr at{\fs19 point} d, output{\fs19 Q} is cleared.{\fs20 or} reset{\fs1
9 to}{\fs19 0.} Again
19 this} happens{\fs20 on} the LOW-to-HIGH transition{\fs19 of} the cl
ock pulsc. Point{\b\i \fs19 c} senses the sct input
0 activated, which sets output{\b\i \fs19 Q} to{\fs18 1} at point{\fs20 f}
on thc timing diagram. Input{\b \f30 \fs21 S}{\b \f10 \fs18 is} deactivated
and{\fs20 R}{\fs19 is }
vated before pulse{\fs19 6,} which causes output{\f10 \fs18 @}{\fs18 t}
{\fs18 o}{\b \f10 \fs16 go}{\fs18 t}{\fs18 o}{\b \fs19 I,OW,} or{\b \f1
0 \fs15 t}{\b \f10 \fs15 o} the reset condition. Pulse{\b \f10 \fs18 7
}
s that output{\b\i \fs19 Q} follows inputs{\b \f30 \fs21 S} and{\b\i \f30 \
fs22 R} the entire timc thc clock is HIGH.{\b \f10 \fs18 At} point{\b\i
\f10 \fs15
g}{\fs20 on} thc
1 timing diagram in{\fs19 Fig.}{\fs18 9-6,} thc sct input{\b \f30 \fs21 (
S)}goes{\b \f30 \fs21 HIGH} and the{\b\i \f30 \fs22 Q} output follows by go
ing{\fs19 HIGH. }
8 Input{\b\i \f10 \fs18 S} then{\b \f30 \fs18 g}{\b \f30 \fs18 w}{\b \f30 \
fs18 s}{\fs19 LOW.} Next the rcsct input{\b\i \fs20 (}{\b\i \fs20 R}{\b
\i \fs20 )} is activated by{\b \f10 \fs16 a}{\fs19 HIGH} at{\fs18 point
} h. That{\fs19 causes }\par
}

\cf0 Fig.{\i \f10 \fs16 9-6}{\fs17
Wavcform} diagram{\fs17 for}{\fs17 c
locked}{\fs17 RS}{\fs16 flip-flop }\par
}
\par
}
IP-FLOPS{\b \fs17 AND} OTHER MULTIVIBRATORS \par
}
}
utput{\b\i \fs18 Q} to reset, or go LOW. Input{\i \fs19 R} then returns t
o LOW, and finally clock pulse{\fs19 7} ends with a
-to-LOW transition. During clock pulse{\fs19 7,} the output was{\i \f10 \fs16
set} to HIGH and then{\i \fs19 reset} to{\fs19 LOW. }
\par}{\phpg\posx843\pvpg\posy1364\absw9054\absh1289 \sl-238 \f20 \fs18 \cf0 Note
that between pulses{\i \fs19 5} and{\fs19 6} it appears that both in
puts{\b\i \fs19 S} and{\i \fs19 R} are at 1. The condition of
ts{\b\i \fs19 R} and{\b \f30 \fs21 S} both being HIGH would normally be cons
idered the prohibited state for the flip-flop.
\par}{\phpg\posx843\pvpg\posy1364\absw9054\absh1289 \sl-232 \f20 \fs18 \cf0 In t
his case it is acceptable for both{\b\i \fs19 R} and{\b\i \fs19 S} to be
HIGH because the clock pulse{\fs19 is} LOW and the
\par}{\phpg\posx843\pvpg\posy1364\absw9054\absh1289 \sl-245 \f20 \fs18 \cf0 flip
-flop is not activated. \par
}
}
f0 9.7 \par
}
efer to Fig.{\fs19 9-4.} The reset and set inputs on the clocked{\i \fs1
9 RS} flip-flop are said to be active
84 (HIGH, LOW) inputs.
\fs17 Solution: }
52 {\fs17 The}{\b\i \f30 \fs19 R}{\fs17 and}{\fs17 S}{\fs17 inputs}{\fs17
are}{\fs17 active}{\fs17 HIGH}{\fs17 inputs}{\fs17 on}{\fs17 the}{\fs
17 clocked}{\i \fs17 RS}{\fs17 flip-flop}{\fs17 shown}{\fs17 in}{\fs17
Fig.}{\fs16 9-4. }\par
}
f0 9.8 \par
}
\cf0 A{\b0 flip-flop}{\b0 that}{\b0 operates}{\b0 in}{\b0 step}{\b0 w
ith}{\b0 the}{\b0 clock}{\b0 \fs19 is}{\b0 said}{\b0 to}{\b0 operate
}
\b0 synchronously). }
\fs17 Solution: }
fi360 {\fs17 A}{\b0 \fs17 flip-flop}{\b0 \fs17 that}{\b0 \fs17 operates}{\b0
\fs17 in}{\b0 \fs17 step}{\b0 \fs17 with}{\b0 \fs17 the}{\b0 \fs17 clo
ck}{\b0 \fs17 operates}{\b0 \fs17 synchronously. }\par
}
asynchronously, \par
}
f0 9.9 \par
}
he{\b\i \fs19 RS} latch operates
}
asynchronously, synchronously). \par
}
he{\b\i \fs17 RS} latch operates asynchronously. \par
}
cf0 9.10{\b0
The}{\b0 clocked}{\i \fs19 RS}{\b0 flip-flop}{\b0 operate
s }
}
asynchronously, synchronously). \par
}
he clocked{\b\i RS} flip-flop operates synchronously. \par
}
cf0 9.11{\b0
Draw}{\b0 the}{\b0 logic}{\b0 symbol}{\b0 of}{\b0 a}{\b0
clocked}{\b0\i \fs19 RS}{\b0 flip-flop}{\b0 by}{\b0 using} NAND{\b0 gates
. }
i958 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0\i \f10 \fs15 9-5a. }\par
}
\cf0 9.12{\b0
List}{\b0 the}{\b0\i \fs19 binary}{\b0 output}{\b0 at
}
\fi592 {\b0 clock}{\b0 pulses. }
\fi952 {\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 outputs}{\b0 \fs17 at }
\fi598 {\b0 \fs17 follows: }\par
}
ulse{\fs17 1}{\f10 \fs13 =}{\fs17 1 }

e{\fs17 2}{\dn006 \f10 \fs11 =} 0 \par
}
ulse 3{\dn006 \f10 \fs11 =} 0
e{\b \f30 \fs18 4}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
for the clocked{\i \fs19 RS} flip-flop shown in Fig.{\fs18 9-6} during
the input \par
}
in this flip-flop are the opposite{\fs16 of} those at the{\i \fs16 Q
} output. They are as \par
}
ulse{\fs17 5}{\dn006 \f10 \fs11 =} 0
e{\b \fs16 6}{\f10 \fs13 =}{\fs17 1 }\par
}
pulse{\fs17 7}{\f10 \fs13 =}{\b \fs17 1,} then{\fs16 0,} and then{\fs16
1 }\par
}
\cf0 9.13{\b0
List}{\b0 the}{\b0\i \fs19 binary}{\b0 output}{\b0 at}{\i
\fs19 Q}{\b0 for}{\b0 the}{\b0 flip-flop}{\b0 \fs19 of}{\b0 Fig.}{\b0 \
fs19 9-7}{\b0 during}{\b0 the}{\b0 eight}{\b0 clock}{\b0 pulses. }\par
}
. 91 \par
}
}
f0 209 \par
}
\cf0 Fig. 9-7{\b0 \fs17
Clocked}{\i \fs17 RS}{\b0 \fs17 flip-flop}{\b0 \f
s17 pulse-train}{\b0 \fs17 problem }\par
}
\cf0 Solution:
fi350 {\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 outputs}{\b0 \fs17 at}{\b
0 Q}{\b0 \fs17 for}{\b0 \fs17 the}{\b0 \fs17 clocked}{\i \fs17 RS}{\b0
\fs17 flip-flop}{\b0 \fs17 of}{\b0 \fs17 Fig.}{\b0 \fs17 9-7}{\b0 \fs17 a
re}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
lse{\b a}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\i \fs16 b}{\dn006 \f10 \fs11 =}{\fs16 1 }\par
}
lse{\f10 \fs15 c}{\dn006 \f10 \fs11 =}{\fs17 1 }

{\b\i \fs17 d}{\f10 \fs13 =} 0 \par
}
ulse{\fs16 e}{\dn006 \f10 \fs11 =}{\fs16 0 }
e{\i f}{\dn006 \f10 \fs11
=}{\fs17 1} (prohibited condition) \par
}
lse{\i \fs15 g}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\b\i h}{\f10 \fs13 =}{\fs17 1 }\par
}
cf0 9.14{\b0
List}{\b0 the}{\b0 mode}{\b0 of}{\b0 operation}{\b0 of}{\b
0 the}{\b0 flip-flop}{\b0 of}{\b0 Fig.}{\b0 \fs19 9-7}{\b0 during}{\b0 th
e}{\b0 eight}{\b0 clock}{\b0 pulses}{\b0 (use}{\b0 terms: }
i600 {\b0 hold,}{\b0 reset,}{\b0 set,}{\b0 prohibited). }
i952 {\b0 \fs17 The}{\b0 \fs17 operational}{\b0 \fs17 modes}{\b0 \fs17 for}
{\b0 \fs17 the}{\b0 \fs17 clocked}{\i \fs17 RS}{\b0 \fs17 flip-flop}{\b0
\fs17 of}{\b0 \fs17 Fig.}{\b0 \fs17 9-7}{\b0 \fs17 are}{\b0 \fs17 as}{\b
0 \fs17 follows: }\par
}
ulse{\fs16 a}{\f10 \fs13 =} set
e{\i \fs16 b}{\dn006 \f10 \fs11 =} hold \par
}
ulse{\i \f10 \fs14 c}{\dn006 \f10 \fs11 =} set
e{\b\i \fs17 d}{\f10 \fs13 =} reset \par
}
ulse{\fs16 e}{\f10 \fs13 =} hold
e{\i \fs17 f}{\dn006 \f10 \fs11
=} prohibited \par
}
ulse{\fs15 g}{\f10 \fs13 =} set
e{\b\i h}{\f10 \fs13 =} hold \par
}
f0 9.15 \par
}
efer to Fig.{\fs19 9-6.} The clocked{\i \fs19 RS} flip-flop is level-trigge
red, which means the unit is enabled \par
}
uring the entire
}
HIGH,{\fs18 LOW)}{\fs18 portion}{\fs18 of}{\fs18 the}{\fs18 clock}{\fs18 p

ulse. }\par
}
\cf0 The flip-flop{\fs16 of} Fig.{\fs17 9-6} is level-triggered, which mea
ns it{\b \fs17 is} enabled during the entire HIGH portion
16 of} the clock pulse. \par
}
\cf0 9-4{\i \f30 \fs20 D}{\f20 \fs19 FLIP-FLOP }
fi355 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 logic}{\b0 \f20 \fs18 symbol}{\b0 \f
20 \fs18 for}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 common}{\b0 \f20 \fs18 type
}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 flip-flop}{\b0 \f20 \fs18 is}{\b0 \f20
\fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs19 9-8.}{\b
0 \f20 \fs18 The}{\b0\i \f20 \fs18 Dflip-flop}{\b0 \f20 \fs18 has}{\b0 \f20
\fs18 only}{\b0 \f20 \fs18 a }
\b0 \f20 \fs18 single}{\b0\i \f20 \fs19 data}{\b0 \f20 \fs18 input}{\b0\i \f
20 \fs19 (}{\b0\i \f20 \fs19 D}{\b0\i \f20 \fs19 )}{\b0 \f20 \fs18 and}{\b0
\f20 \fs18 a}{\b0 \f20 \fs18 clock}{\b0 \f20 \fs18 input}{\b0 \f20 \fs19 (C
LK).}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 customary}{\b0 \f20 \fs19 Q}{\b0 \f
20 \fs18 and}{\b0 \f20 \fs18
outputs}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18
shown}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 right}{\b0 \f20 \fs18 side}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 symbol.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs19 D}{\b0
\f20 \fs18 flip-flop}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 often}{\b0 \f20 \f
s18 called}{\b0 \f20 \fs18 a}{\b0\i \f20 \fs19 delay}{\i \f20 flip-flop.
}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18 name}{\b0 \f20 \fs18 accurately }
\b0 \f20 \fs18 describes}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 unit's}{\b0 \f20
\fs18 operation.}{\b0 \f20 \fs18 Whatever}{\b0 \f20 \fs18 the}{\b0 \f20 \fs1
8 input}{\b0 \f20 \fs18 at}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 data}{\b0\i \
f20 \fs19 (}{\b0\i \f20 \fs19 D}{\b0\i \f20 \fs19 )}{\b0 \f20 \fs18 point,}{\
b0 \f20 \fs18 it}{\b0 \f20 \fs18 is}{\b0\i \f20 \fs19 deluyed}{\b0 \f20 \fs18
from}{\b0 \f20 \fs18 getting}{\b0 \f20 \fs18 to }
\b0 \f20 \fs18 the}{\b0 \f20 \fs18 normal}{\b0 \f20 \fs18 output}{\i \f20 \fs
18 (}{\i \f20 \fs18 Q}{\i \f20 \fs18 )}{\b0\i \f20 \fs19 by}{\b0\i \f20 \fs1
9 one}{\b0\i \f20 \fs19 clock}{\b0\i \f20 \fs19 pulse.}{\b0 \f20 \fs18 Dat
a}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 transferred}{\b0 \f20 \fs18 to}{\b0 \f
20 \fs18 the}{\b0 \f20 \fs18 output}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 th
e}{\b0 \f20 \fs18 LOW-to-HIGH }
\b0 \f20 \fs18 transition}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \f
s18 clock}{\b0 \f20 \fs18 pulse. }\par
}
cf0 a \par
}
\cf0 Inputs \par
}
lock \par
}
utputs \par
}
20 \fs16 \cf0 Fig.{\fs17 9-8}{\b0 \fs17
Logic}{\b0 \fs17 symbol}{\b0 \fs17
for}{\i \f30 \fs19 D}{\b0 \fs17 flip-flop }
cf0 \fi350 {\b0 \fs18 The}{\b0 \fs18 clocked}{\b0\i \fs19 RS}{\b0 \fs18 fli
p-flop}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 converted}{\b0 \fs18 to}{\b0
\fs18 a}{\i \fs19 D}{\b0 \fs18 flip-flop}{\fs18 by}{\b0 \fs18 adding}{\b0
\fs18 an}{\b0 \fs18 inverter.}{\b0 \fs18 That}{\b0 \fs18 conversion }
{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 di
agram}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-9u.}{\b0 \fs18 Note}{\b
0 \fs18 that}{\b0 \fs18 the}{\b0\i \fs19 R}{\b0 \fs18 input}{\b0 \fs18
to}{\b0 \fs18 the}{\b0 \fs18 clocked}{\b0\i \fs19 RS}{\b0 \fs18 flip-fl
op}{\b0 \fs18 has}{\b0 \fs18 been }
{\b0 \fs18 inverted. }\par
}
1 \cf0 Data'al \par
}
IP-FLOPS{\b AND} OTHER MULTIVIBRATORS \par
}
cf0 Clock \par
}
cf0 CLK{\b0 \fs14 FF }\par
}
fr \par
}
cf0 Preset
i62 {\b0 \fs15 (set) }\par
}
{\phpg\posx6215\pvpg\posy2210\absw401\absh164 \f20 \fs14 \cf0 \f20 \fs14 \cf0 Cl
ock \par
}
14 \cf0 (7474){\f10 \fs13 Q }
\fi1273 {\b \fs14 Clear }
1247 (reset)
{\i \fs14 (h)}{\b \fs14 Logic} symbol for 7474{\b\i \f30 \fs16 D}{\b \fs14
flip-flop}{\b \fs14 with}{\b \fs14 asynchronous}{\b \fs14 inputs }
{\b \fs16 Fig.}{\b \fs16 9-9 }\par
}
s14 \cf0 (a){\f30 \fs16 D}{\i0 flip-flop}{\i0 wired}{\b0\i0 \fs14 from}{\i
0 clocked} RS{\i0 flip-flop }\par
}
\fs18 \cf0 A{\b0 commercial}{\b0\i \fs19 D}{\b0 flip-flop}{\b0 is}{\b0

shown}{\b0 in}{\b0 Fig.}{\b0 \fs18 9-9b.}{\b0 The}{\b0\i \fs19 D}{\b0
flip-flop}{\b0 in}{\b0 Fig.}{\b0 \fs18 9-9b}{\b0 is}{\b0 a}{\b0 TTL
}{\b0 device }
\b0 described}{\b0 by}{\b0 the}{\b0 manufacturers}{\b0 as}{\b0 a}{\b0
7474}{\b0 IC.}{\b0 The}{\b0 logic}{\b0 symbol}{\b0 for}{\b0 the}{\b0
7474}{\b0\i \fs19 D}{\b0 flip-flop}{\b0 shows}{\b0 the }
\b0 regular}{\b0\i D}{\b0 and}{\b0 CLK}{\b0 inputs.}{\b0 Those}{\b0 in
puts}{\b0 are}{\b0 called}{\b0 the}{\b0\i synchronous}{\b0 inputs,}{\b0
for}{\b0 they}{\b0 operate}{\b0 in}{\b0 step }
\b0 with}{\b0 the}{\b0 clock.}{\b0 The}{\b0 extra}{\b0 two}{\b0 inputs}{\b
0 are}{\b0 the}{\b0\i asynchronous}{\b0 inputs,}{\b0 and}{\b0 they}{\b0
operate}{\b0 just}{\b0 as}{\b0 in}{\b0 the}{\b0\i \fs19 RS }
\b0 flip-flop}{\b0 discussed}{\b0 previously.}{\b0 The}{\b0 asynchronous}{\b
0 inputs}{\b0 are}{\b0 labeled}{\b0 preset}{\b0\i \fs19 (}{\b0\i \fs19 P}{
\b0\i \fs19 E}{\b0\i \fs19 )}{\b0 and}{\b0 clear}{\b0 (CLR).}{\b0 The }
\b0 preset}{\b0\i \fs18 (PR)}{\b0 input}{\b0 can}{\b0 be}{\b0 activated
}{\b0 by}{\b0 a}{\b0 LOW,}{\b0 \fs18 as}{\b0 shown}{\b0 by}{\b0 th
e}{\b0 small}{\b0 bubble}{\b0 on}{\b0 the}{\b0 logic}{\b0 symbol. }
\b0 When}{\b0 the}{\b0 preset}{\b0\i \fs18 (PR)}{\b0 is}{\b0 activated,
}{\b0 \fs17 it}{\b0\i sets}{\b0 the}{\b0 flip-flop.}{\b0 \fs18 In}{\b0
other}{\b0 words,}{\b0 \fs17 it}{\b0 places}{\b0 a}{\b0 \fs18 1}{\b0
at}{\b0 the}{\b0 normal }
\b0 output}{\b0\i \fs18 (Q,.}{\b0 It}{\b0 presets}{\b0\i \fs18 Q}{\b0 t
o}{\b0 \fs18 1.}{\b0 The}{\b0 clear}{\b0 (CLR)}{\b0 input}{\b0 can}{\b0
be}{\b0 activated}{\b0 by}{\b0 a}{\b0 LOW,}{\b0 as}{\b0 shown}{\b0
by}{\b0 the }
\b0 small}{\b0 bubble}{\b0 on}{\b0 the}{\b0 logic}{\b0 symbol.}{\b0 When
}{\b0 the}{\b0 clear}{\b0 (CLR)}{\b0 input}{\b0 to}{\b0 the}{\b0\i \fs1
9 D}{\b0 flip-flop}{\b0 is}{\b0 activated,}{\b0 the}{\b0\i \fs18 Q }
\b0 output}{\b0 is}{\b0 reset,}{\b0 or}{\b0 cleared}{\b0 to}{\b0 \fs18
0.}{\b0 The}{\b0\i asynchronous}{\b0\i inputs}{\b0\i \fs18 orwride}{\b0\
i the}{\b0\i synchronous}{\b0\i \fs18 inputs}{\b0 on}{\b0 this}{\b0\i \f
s19 D }
\b0 flip-flop. }
fi370 {\f10 \fs17 A}{\b0 truth}{\b0 table}{\b0 for}{\b0 the}{\b0 7474}{\b0\
i \fs19 D}{\b0 flip-flop}{\b0 is}{\b0 \fs18 in}{\fs17 Fig.}{\b0 \fs18 910.}{\b0 The}{\b0 modes}{\b0 of}{\b0 operation}{\b0 are}{\b0 given}{\b0 o
n}{\b0 the}{\b0 left }
\b0 and}{\b0 the}{\b0 truth}{\b0 table}{\b0 on}{\b0 the}{\b0 right.}{\b0
The}{\b0 first}{\b0 three}{\b0 lines}{\b0 are}{\b0 for}{\b0 asynchronous}
{\b0 operation}{\b0 (preset}{\b0 and}{\b0 clear }
\b0 inputs).}{\b0 Line}{\b0 1}{\b0 shows}{\b0 the}{\b0 preset}{\b0\i \fs18
(PR)}{\b0 input}{\b0 activated}{\b0 with}{\b0 a}{\b0 LOW.}{\b0 That}{\b0
sets}{\b0 the}{\b0 \fs18 Q}{\b0 output}{\b0 to}{\b0 \fs18 1.}{\b0 Note }
\b0 the}{\b0 X's}{\b0 under}{\b0 the}{\b0 synchronous}{\b0 inputs}{\b0
(CLK}{\b0 and}{\b0\i D).}{\b0 The}{\b0 X's}{\b0 mean}{\b0 that}{\b0

these}{\b0 inputs}{\b0 are}{\b0 irrelevant }
\b0 because}{\b0 the}{\b0 asynchronous}{\b0 inputs}{\b0 override}{\b0 them
.}{\b0 Line}{\b0 \fs19 2}{\b0 shows}{\b0 the}{\b0 clear}{\b0 \fs18 (CLR)}
{\b0 input}{\b0 activated}{\b0 with}{\b0 a }
\b0 \fs18 LOW.}{\b0 This}{\b0 results}{\b0 in}{\b0 output}{\b0 Q}{\b0 bein
g}{\b0 reset,}{\b0 or}{\b0 cleared}{\b0 to}{\b0 \fs18 0.}{\b0 Line}{\fs18
3}{\b0 shows}{\b0 the}{\b0 prohibited}{\b0 asynchronous }
\b0 input}{\b0 (both}{\b0\i \fs19
PR}{\b0 and}{\b0 CLR}{\b0 at}{\b0 \
fs18 0).}{\b0 The}{\b0 synchronous}{\b0 inputs}{\b0\i (}{\b0\i D}{\b0
and}{\b0 CLK)}{\b0 will}{\b0 operate}{\b0 when}{\b0 both }
\b0 asynchronous}{\b0 inputs}{\b0 are}{\b0 disabled}{\b0\i \fs18 (PR}{\b0
\f10 \fs14 =}{\b0 \fs18 1,}{\b0 CLR}{\b0\dn006 \f10 \fs13 =}{\b0 1).}{\b0
Line}{\b0 4}{\b0 shows}{\b0 \fs18 a}{\b0 \fs18 1}{\b0 at}{\b0 the}{\b
0 data}{\b0\i \fs19 (}{\b0\i \fs19 D}{\b0\i \fs19 )}{\b0 input}{\b0 and}
{\b0 a }
\b0 rising}{\b0 clock}{\b0 pulse}{\b0 (shown}{\b0 with}{\b0 the}{\b0 upwar
d}{\b0 arrow).}{\b0 The}{\b0 1}{\b0 \fs17 at}{\b0 input}{\b0\i D}{\b0
is}{\b0 transferred}{\b0 \fs18 to}{\b0 output}{\b0\i \fs18 Q}{\b0 on}{\b0
the }
\b0 clock}{\b0 pulse.}{\b0 Line}{\b0\i \fs18 5}{\b0 shows}{\b0 a}{\b0
\fs18 0}{\b0 at}{\b0 the}{\b0 data}{\b0\i \fs19 (}{\b0\i \fs19 D}{\b0
\i \fs19 )}{\b0 input}{\b0 being}{\b0 transferred}{\b0
to}{\b0 output
}{\b0\i \fs17
Q}{\b0 on}{\b0 the }
\b0 LOW-to-HIGH}{\b0 clock}{\b0 transition. }\par
}
\par
}
AP.{\fs16 9 }\par
}
20 \fs16 \cf0 Mode
\fi680 {\b0 \fs17 of }
\fi382 operation
\cf0 Asynchronous set
Asynchronous reset
Prohibited
Set
Reset \par
}
20 \fs16 \cf0 Inputs
cf0 Asynchronous \par
}
fs16 \cf0 P R
\cf0 \fi78 {\b0\i0 \fs17 0 }
0 \fi100 {\b0\i0 \f10 \fs15 1 }
0 \fi80 {\b0\i0 0 }
0 \fi102 {\i0 \f10 \fs15 1 }
0 \fi102 {\b0\i0 \f10 \fs15 1 }\par
}
CLR
\fi170 {\fs16 1 }
147 {\fs16 0 }
147 {\fs16 0 }
171 {\b \f10 \fs15 1 }
171 {\f10 \fs15 1 }\par
}
\cf0 outputs \par
}
\cf0 Synchronous \par
}
CLK
\fi113 {\b \f30 \fs19 X }
113 {\b \f30 \fs19 X }
113 {\b \f30 \fs19 X }
146 {\f10 \fs20 T }
146 {\f10 \fs20 1 }\par
}
fs16 \cf0 D
\cf0 {\i0 \fs17 X }
0 {\b0\i0 \fs24 x }
0 {\i0 \fs17 X }
0 \fi44 {\i0 \f10 \fs15 1 }
0 {\b0\i0 \fs16 0 }\par
}
fs16 \cf0 Q
\cf0 \fi53 {\b0\i0 \f10 \fs15 1 }
0 {\b0\i0 \fs24 o }
0 \fi57 {\i0 \f10 \fs15 1 }
0 \fi57 {\b0\i0 \f10 \fs15 1 }
0 \fi33 {\b0\i0 \fs16 0 }\par
}
fs16 \cf0 Q
\cf0 \fi38 {\b0\i0 \f10 \fs15 0 }
0 \fi50 {\i0 \f10 \fs15 1 }
0 \fi46 {\b0\i0 \f10 \fs15 1 }
0 \fi42 {\b0\i0 \f10 \fs15 0 }
0 \fi52 {\i0 \f10 \fs15 1 }\par
}
\cf0 Fig.{\fs16 9-10} Truth table{\fs16 for}{\fs16 7474}{\b0\i D}{\fs16
flip-flop }\par
}
0 CHAP.{\b0 \fs16 91 }\par
}
cf0 FLIP-FLOPSAND{\b0 \fs17 OTHER}{\b0 \fs16 MULTIVIBRATORS }\par
}
f0 21{\b0 \fs18 1 }\par
}
\cf0 Only the bottom two lines of the truth table in Fig. 9-10 are needed{
\fs18 if} the{\i \fs19 D} flip-flop does not
the asynchronous inputs.{\i \fs19 D} flip-flops are widely used in data sto
rage. Because{\fs19 of} this use, it is
\par}{\phpg\posx853\pvpg\posy1362\absw9236\absh3775 \sl-239 \f20 \fs18 \cf0 some
times also called a{\i data}{\b\i \f30 \fs17 flip-flop. }
66 Look at the{\i \fs19 D} flip-flop symbols shown in Figs. 9-8 and 9-96. Not
e that the clock (CLK) input in
{\fs18 9-9b} has a small{\f10 \fs21 >} inside the symbol, meaning t
hat this is an{\i edge-triggered} device. This
-triggered flip-fop transfers data from input{\i \fs19 D} to output{\i \fs18
Q} on the LOW-to-HIGH transition of
clock pulse. In edge triggering, it{\fs18 is} the{\i change}{\fs18 of}{\i
the}{\i \fs19 clock} from LOW to HIGH (or H to L) that

sfers data. Once the clock pulse is HIGH on the edge-triggered flip-flop, a chan
ge in input{\i \fs19 D} will
no effect on the outputs.
67 Figures 9-8 and 9-9a show a{\i \fs19 D} flip-flop that{\fs18 is}{\i leue
l-triggered} (as opposed to edge-triggered). The
\par}{\phpg\posx853\pvpg\posy1362\absw9236\absh3775 \sl-232 \f20 \fs18 \cf0 abse
nce{\fs18 of} the small{\f10 \fs21 >} inside the symbol at the clock input
indicates a level-triggered device. On{\fs18 a }
\par}{\phpg\posx853\pvpg\posy1362\absw9236\absh3775 \sl-247 \f20 \fs18 \cf0 leve
l-triggered flip-flop, a certain voltage level will cause the data at in
put{\i \fs19 D} to be transferred to
ut Q. The problem with the level-triggered device is that the output will
follow the input if the
t changes while the clock pulse is HIGH. Level triggering, or clocking, can be
a problem if input
changes while{\fs18 the} clock is HIGH.
}
f0 9.16 \par
}
hat two other names are given to the{\i \fs19 D} flip-flop?
60 {\fs16 The}{\i \fs17 D}{\fs16 flip-flop}{\fs16 is}{\fs17 also}{\fs16
called}{\fs16 the}{\i \fs17 delay}{\fs16 and}{\fs16 the}{\i \fs17 data
}{\fs16 flip-flop. }\par
}
f0 9.17 \par
}
Draw a logic diagram of a clocked{\b\i \fs19 RS} flip-flop and inverter wired
as a{\i \fs19 D} flip-flop.
\fs16 Solution: }
356 {\fs16 See}{\fs16 Fig.}{\fs16 9-9a. }
Draw the logic symbol for a{\fs19 D} flip-flop. Label inputs as{\i \fs19 D,
} CLK,{\b\i \fs19 PR,} and CLR. Label outputs
\par}{\phpg\posx1459\pvpg\posy6968\absw8393\absh2119 \sl-239 \f20 \fs18 \cf0 as
Q and{\fs23 Q. }
\fs16 Solution: }
356 {\fs16 See}{\b \fs16 Fig.}{\fs16 9-9b. }\par
}
he data bit at the{\i D} input of the 7474{\i \fs19 D} flip-flop is transfe
rred to output \par
}
e
\b \fs16 Solution: }\par
}
H-to-L, L-to-H) transition{\fs18 of} the clock pulse. \par
}
cf0 (Q, \par
}
{\phpg\posx9181\pvpg\posy9549\absw456\absh477 \f20 \fs42 \cf0 \f20 \fs42 \cf0 e)
\par
}
{\phpg\posx9477\pvpg\posy9779\absw245\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 on
\par
}
f0 9.18 \par
}
f0 9.19 \par
}
6 \cf0 The data at the{\i \fs17 D} input of a{\i \fs17 D} flip-flop{\
b is} transferred to output Q on the L-to-H transition{\fs16 of} the
\par}{\phpg\posx1455\pvpg\posy10622\absw8238\absh395 \sl-224 \f20 \fs16 \cf0 clo
ck pulse. \par
}
cf0 9.20 \par
}
Refer to Fig. 9-10. An{\fs19 X} in the truth table stands for an
}
(extra, irrelevant) input. \par
}
0 \fs17 \cf0 An X{\b0 in}{\b0 \fs16 the}{\b0 \fs16 truth}{\b0 \fs16 tab
le}{\b0 \fs16 stands}{\b0 \fs16 for}{\b0 \fs16 an}{\b0 \fs16 irrelevant}
{\b0 \fs16 input.}{\fs17 An}{\fs17 X}{\b0 \fs16 input}{\b0 \fs16 can}{\
b0 \fs16 be}{\b0 \fs16 either}{\b0 \fs16 0}{\b0 \fs16 or}{\b0 \fs17 1}{\
b0 \fs16 and}{\b0 \fs16 has}{\b0 \fs16 no }
{\b0 \fs16 effect}{\b0 \fs16 on}{\b0 \fs16 the}{\b0 \fs16 output. }\par
}
cf0 9.21 \par
}
List the binary outputs at the complementary output
\par}{\phpg\posx1459\pvpg\posy12983\absw4655\absh425 \sl-237 \f20 \fs18 \cf0 eac
h of the clock pulses. \par
}
e) \par
}
of the{\i \fs19 D} flip-flop{\fs19 of} Fig. 9-11 after \par
}
\par
}
}
AP.{\fs17 9 }\par
}
cf0 0 \par
}
cf0 1 \par
}
cf0 1 \par
}
\par
}
cf0 1 \par
}
cf0 1 \par
}
\par
}
}
\par
}
cf0 0 \par
}
\par
}
\par
}
cf0 0 \par
}
cf0 0 \par
}
cf0 0 \par
}

\par
}
{\phpg\posx7087\pvpg\posy2333\absw105\absh154 \f10 \fs13 \cf0 \f10 \fs13 \cf0 I\par
}
15 \cf0 h
cf0 {\b0 \f10 \fs14 0 }\par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
15 \cf0 e
cf0 {\i0 \f10 \fs14 1 }\par
}
14 \cf0 d \par
}
15 \cf0 b \par
}
\fs16 \cf0 CLK
f0 \fi568 {\fs14 (7474)Q }
fi606 {\f30 \fs17 CkR }
\b0 \f30 \fs31 1 }\par
}
\par
}
cf0 1 \par
}
\par
}
par
}
cf0 1 \par
}
f0 - \par
}
\cf0 Fig.{\f10 \fs15 9-11}{\i \f30 \fs19 D}{\b0 \fs17 flip-flop}{\b0 \fs17
pulse-train}{\b0 \fs17 problem }\par
}
\cf0 Solution:
\fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 9-10.}{\b0 \fs17
The}{\b0 \fs17 binary}{\b0 \fs17 outputs}{\b0 \fs17 at }
\b0 \fs17 follows: }\par
}
lse{\i \f10 \fs14 a}{\f10 \fs13 =} 0
{\fs16 b}{\dn006 \f10 \fs11 =}{\fs17 1 }\par
}
lse{\i \f10 \fs14 c}{\f10 \fs14 =} 0
{\b\i \f10 \fs16 d}{\f10 \fs13 =}{\fs16 1 }\par
}
lse{\fs16 e}{\dn006 \f10 \fs11 =} 0
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 0
e{\fs17 h}{\dn006 \f10 \fs11 =}{\fs16 1} (prohibited state) \par
}
f the{\b\i \f30 \fs19 D} flip-flop (Fig. 9-11) are as \par
}
\cf0 9.22{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 9-11.}{\b0 Which}{\b0 input}
{\b0 has}{\b0 control}{\b0 \fs18 of}{\b0 the}{\b0 flip-flop}{\b0 during}{\
b0 pulse}{\b0 \fs17 a? }
fi956 {\b0 \fs17 The}{\b0 \fs17 preset}{\i \f30 \fs19 (PI?)i}{\b0 \fs17 nput}{
\b0 \fs17 is}{\b0 \fs17 activated}{\b0 \fs17 during}{\b0 \fs17 pulse}{\b0\i
\f10 \fs14 a}{\b0 \fs17 and}{\b0 \fs17 overrides}{\b0 \fs17 all}{\b0 \fs
17 other}{\b0 \fs17 inputs.}{\b0 \fs17 It}{\b0 \fs17 sets}{\b0 \fs17 the}
{\b0 \fs16 Q}{\b0 \fs17 output }
fi598 {\b0 \fs17 to}{\b0 \fs16 1. }
f0 9.23{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 9-11.}{\b0 Just}{\b0 before
}{\b0 pulse}{\b0 \fs19 6,}{\b0 output}{\b0 Q}{\b0 is}{\b0
(HIGH,}{\b0 LOW);}{\b0 during}{\b0 pulse}{\b0 \fs18 6, }\par
}
utput Q is
H, LOW).
}
HIGH, LOW); on the H-to-L clock-pulse transition, output{\b\i \fs18 Q}{\fs19
is }\par
}
\cf0 Just before pulse{\fs16 b,} output{\fs16 Q} is HIGH; during pulse{\f
s16 b,} output{\i \fs16 Q} is LOW; on the H-to-L clock-pulse
sition, output{\b\i \f30 \fs19 Q} is LOW. \par
}
\cf0 9-5{\i
JK} FLIP-FLOP
fi360 {\b0 The}{\b0 logic}{\b0 symbol}{\b0 for}{\b0 a}{\i \fs19 JK}{\b0
flip-flop}{\b0 is}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 9-12.}{\b0 This}{\b
0 device}{\b0 might}{\b0 be}{\b0 considered}{\b0 the }
\b0 universal}{\b0 flip-flop;}{\b0 other}{\b0 types}{\b0 can}{\b0 be}{\b0
made}{\b0 from}{\b0 it.}{\b0 The}{\b0 logic}{\b0 symbol}{\b0 shown}{\b
0 in}{\b0 Fig.}{\b0 9-12}{\b0 has}{\b0 three }
\b0 synchronous}{\b0 inputs}{\i (}{\i J}{\i ,}{\b0\i \fs19 K}{\b0\i \fs19
,}{\b0 and}{\b0 CLK).}{\b0 The}{\i \fs19 J}{\b0 and}{\b0\i \fs19 K
}{\b0
inputs}{\b0 are}{\b0 data}{\b0 inputs,}{\b0 and}{\b0 the}{\b0
clock}{\b0 input }
\b0 transfers}{\b0 data}{\b0 from}{\b0 the}{\b0 inputs}{\b0 to}{\b0
the}{\b0 outputs.}{\b0 The}{\b0 logic}{\b0 symbol}{\b0 shown}{\b0 \fs1
8 in}{\b0 Fig.}{\b0 9-12}{\b0 also}{\b0 has}{\b0 the }
\b0 customary}{\b0 normal}{\b0 output}{\b0\i \fs18 (}{\b0\i \fs18 Q}{\b0\i \
fs18 )}{\b0 and}{\b0 complementary}{\b0 output}{\i \f30 \fs33 (D). }\par
}
\cf0 Inputs \par
}
\cf0 Clock
f0 \fi268 {\i \fs14 K }\par
}
utputs \par
}
20 \fs16 \cf0 Fig.{\f10 \fs15 9-12}{\b0 \fs17
Logic}{\b0 \fs17 symbol}{\b0
\fs17 for}{\b0 \fs17 JK}{\b0 \fs17 flip-flop }
cf0 \fi354 {\fs18 A}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 for}{\b0 \fs
18 the}{\i \fs19 JK}{\b0 \fs18 flip-flop}{\b0 \fs18 is}{\b0 \fs18 in}{\b0
\fs18 Fig.}{\b0 \fs18 9-13.}{\b0 \fs18 The}{\b0 \fs18 modes}{\b0 \fs18 of}{
\b0 \fs18 operation}{\b0 \fs18 are}{\b0 \fs18 given}{\b0 \fs18 on}{\b0 \fs18
the}{\b0 \fs18 left}{\b0 \fs18 and }
{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 is}{\b0 \fs18 on
}{\b0 \fs18 the}{\b0 \fs18 right.}{\b0 \fs18 Line}{\b0 \fs18 1}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs18 shows}{\b0
\fs18 the}{\b0 \fs18 hold,}{\b0 \fs18 or}{\b0 \fs18 disabled,}{\b0 \fs18 c
ondition.}{\b0 \fs18 Note }
{\b0 \fs18 that}{\b0 \fs18 both}{\b0 \fs18 data}{\b0 \fs18 inputs}{\i \fs19
(}{\i \fs19 J}{\b0 \fs18 and}{\b0\i \fs19 K}{\b0\i \fs19 )}{\b0 \fs18 ar
e}{\b0 \fs18 LOW.}{\b0 \fs18 The}{\b0 \fs18 reset,}{\b0 \fs18 or}{\b0 \fs18
clear,}{\b0 \fs18 condition}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 flip-f

lop}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in }\par
}
0 CHAP.{\b0 \fs17 91 }\par
}
cf0 FLIP-FLOPS AND OTHER MULTIVIBRATORS \par
}
\par
}
cf0 Inputs \par
}
cf0 Outputs \par
}
\cf0 operation
f0 \fi119 Hold
fi119 Reset
fi119 Set
fi112 Toggle \par
}
5 n }
\fs16 n }
\fs16 n }\par
}
{\phpg\posx5163\pvpg\posy2810\absw55\absh184 \f20 \fs16 \cf0 \f20 \fs16 \cf0 l \
par
}
cf0 0
b0 \f30 \fs25 o }
0 \fi30 {\fs16 1 }\par
}
cf0 0
i24 {\fs16 1 }
b0 \fs16 O }
i28 {\fs16 1 }\par
}
cf0 no change \par
}
cf0 0
i27 {\i0 \f10 \fs15 1 }\par
}
fs16 \cf0 1
b0\i \f20 \fs17 0 }\par
}
cf0 opposite
i151 state \par
}
\cf0 Fig.{\fs16 9-13}{\fs17
Truth}{\fs17 table}{\fs17 for}{\fs17 pulse-t
riggered}{\i \fs17 JK}{\fs17 flip-flop }\par
}
ne 2 of the truth table. When{\i \fs19 J}{\dn006 \f10 \fs13 = }\par
}
\fs18 and}{\i \fs19 K}{\dn006 \f10 \fs13 = }\par
}
and a clock pulse arrives at the CLK input, the \par
}
{\phpg\posx861\pvpg\posy4518\absw7479\absh305 \f20 \fs18 \cf0 \f20 \fs18 \cf0 fl
ip-flop is reset{\i \fs18 (Q}{\dn006 \f10 \fs13 =}{\fs18 0).} Line{\fs18 3}
shows the set condition of the{\i \fs19 JK} flip-flop. When{\i \fs19 J}{\dn0
06 \f10 \fs13 = }\par
}
{\i K}{\dn006 \f10 \fs13 = }\par
}
cf0 0,{\i0 \fs18 and}{\i0 \fs18 a }\par
}
lock pulse is present, output Q is set to 1. Line 4 illustrates a very useful co
ndition of the{\i \fs19 JK} flip-flop
is called the{\i toggle} position. When both inputs{\i J} and{\i \fs
19 K} are HIGH, the output will go to the
\par}{\phpg\posx861\pvpg\posy4752\absw9461\absh2775 \sl-231 \f20 \fs18 \cf0 oppo
site state when a pulse arrives at the CLK input. With repeated clock pulses, th
e{\i \fs18 Q} output might
\par}{\phpg\posx861\pvpg\posy4752\absw9461\absh2775 \sl-235 \f20 \fs18 \cf0 go
LOW, HIGH, LOW, HIGH, LOW, and{\fs18 so} forth. This LOW-HIGH-LOW-HIGH
idea is called
toggling.} The term "toggling" comes from the ON-OFF nature of a toggle switch
.
62 Note in the truth table in Fig.{\fs18 9-13} that an entire clock pul
se is shown under the clock (CLK)
t heading. Many{\i \fs18 JK} flip-flops are{\i pulse-triggered.} It{\i take
s}{\i the}{\i entirepulse}{\i to}{\i transfer}{\i data} from the

t to the outputs of the flip-flop. With the clock input in the truth table, it
is evident that the{\i \fs19 JK }
-flop is a synchronous flip-flop.
56 The{\i \fs19 JK} is considered the universal flip-flop. Figure{\i
9-14a} shows how a{\i \fs19 JK} flip-flop and an
rter would be wired to form a{\i D} flip-flop. Note the single{\i \fs19 D
} input at the far left and the clock
t. This wired{\fs19 D} flip-flop would trigger on the HIGH-to-LOW trans
ition of the clock pulse, as
n by the bubble at the CLK input. \par
}
f20 \fs14 \cf0 D
{\i0 \fs14 Clock }\par
}
14 \cf0 G \par
}
cf0 FF{\b0\i \fs11
Q' }\par
}
f0 J \par
}
cf0 a>{\f20 \fs15 CLK }\par
}
\cf0 HIGH
f20 \fs14 Clock }\par
}
{\phpg\posx2189\pvpg\posy9110\absw274\absh164 \f10 \fs14 \cf0 \f10 \fs14 \cf0 +K \par
}
{\phpg\posx3319\pvpg\posy9020\absw386\absh270 \f20 \fs23 \cf0 \f20 \fs23 \cf0 Q\par
}
{\phpg\posx5183\pvpg\posy9104\absw222\absh164 \f10 \fs14 \cf0 \f10 \fs14 \cf0 -K \par
}
\fs15 \cf0 FF{\i \fs15
Q-- }
fs15 CLK }
i476 {\i \f10 \fs21 d }\par
}
cf0 Clock \par
}
s15 \cf0 (a){\i0 \fs14 Wiring}{\i0 the}{\fs15 J}{\fs15 K}{\i0 \fs14 flip-f
lop}{\i0 as}{\i0 \fs15 a }
\fi261 {\i0 \fs15 D}{\i0 \fs14 flip-flop }\par
}
s15 \cf0 (b){\i0 \fs14 Wiring}{\b0\i0 \fs14 the}{\fs15 J}{\fs15 K}{\i0 \fs14
flip-flop}{\i0 \fs15 as}{\i0 \fs15 a }
\fi273 {\fs15 T}{\i0 \fs14 flip-flop }
}
s15 \cf0 (c){\i0 \fs14 Logic}{\i0 symbol}{\i0 for}{\i0 \fs15 a }
\fi274 {\i0 \fs14 Tflip-flop }\par
}
0 \fs19 \cf0 A{\b0 \fs18 useful}{\b0\i \fs18 toggle}{\b0\i \fs18 flip-flop}{
\b0 \fs18 (T-type}{\b0 \fs18 flip-flop)}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0
\fs18 wired}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-14b.}{\fs18 A}{\b
0\i JK}{\b0 \fs18 flip-flop}{\b0 \fs18 is}{\b0 \fs18 shown }
{\b0 \fs18 being}{\b0 \fs18 used}{\b0 \fs18 in}{\b0 \fs18 its}{\b0 \fs18 tog
gle}{\b0 \fs18 mode.}{\b0 \fs18 Note}{\b0 \fs18 that}{\b0 \fs18 the}{\b0\i \
fs18 J}{\b0 \fs18 and}{\b0\i K}{\b0 \fs18 inputs}{\b0 \fs18 are}{\b0 \fs
18 simply}{\b0 \fs18 tied}{\b0 \fs18 to}{\b0 \fs18 a}{\b0 \fs18 HIGH,}{\b0
\fs18 and}{\b0 \fs18 the}{\b0 \fs18 clock }
{\b0 \fs18 is}{\b0 \fs18 fed}{\b0 \fs18 into}{\b0 \fs18 the}{\b0 \fs18 CL
K}{\b0 \fs18 input.}{\fs18 As}{\b0 \fs18 the}{\b0 \fs18 repeated}{\b0 \f
s18 clock}{\b0 \fs18 pulses}{\b0 \fs18 feed}{\b0 \fs18 into}{\b0 \fs18
the}{\b0 \fs18 CLK}{\b0 \fs18 input,}{\b0 \fs18 the}{\b0 \fs18 outputs}{
\b0 \fs18 will }
{\b0 \fs18 simply}{\b0 \fs18 toggle. }
\fi362 {\b0 \fs18 The}{\b0 \fs18 toggle}{\b0 \fs18 operation}{\b0 \fs18 is}{
\b0 \fs18 widely}{\b0 \fs18 used}{\b0 \fs18 in}{\b0 \fs18 sequential}{\b0 \
fs18 logic}{\b0 \fs18 circuits.}{\b0 \fs18 Because}{\b0 \fs18 of}{\b0 \fs18
its}{\b0 \fs18 wide}{\b0 \fs18 use,}{\b0 \fs18 a}{\b0 \fs18 special }
{\b0 \fs18 symbol}{\b0 \fs18 is}{\b0 \fs18 sometimes}{\b0 \fs18 used}{\b0 \fs
18 for}{\b0 \fs18 the}{\b0 \fs18 toggle}{\b0 \fs18 (T-type)}{\b0 \fs18 flip
-flop.}{\b0 \fs18 Figure}{\b0 \fs18 9-14c}{\b0 \fs18 shows}{\b0 \fs18 the}{\
b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \fs18 for}{\b0 \fs18 the }\par
}
oggle flip-flop. The single input (labeled{\i \fs19 T}{\i \fs19 )} is the clo
ck input. The Customary{\fs18 Q} and
n on the right of the symbol. The{\i \fs19 T} flip-flop has only the toggle m
ode{\fs18 of} operation. \par
}
outputs are \par
}
\cf0 One commercial{\i \fs19 JK} flip-flop is detailed in Fig.{\i 9-15.} T
his is described by the manufacturer as a

i \fs18 7476}{\i \fs18 TTL}{\i dual}{\b\i \fs17 JKflip-flop.}{\b A} pin diag
ram of the 7476 IC is reproduced in Fig.{\i 9-15a.} Note that the IC
ains{\fs18 two} separate{\i \fs19 JK} flip-flops. Each flip-flop has asy
nchronous preset{\i \fs18 (PR)} and clear (CLR)
ts. The synchronous inputs are shown as{\i J}{\i ,}{\i \fs19 K}{\i \fs19 ,
} and CLK (.clock).The customary normal{\i \fs18 (Q)}and \par
}
0 214 \par
}
cf0 FLIP-FLOPSAND OTHER MULTIVIBRATORS \par
}
f0 [CHAP. 9 \par
}
s17 \cf0 1K IQ{\fs20 1Q}{\fs16 GND}{\fs17 2K} 2Q{\fs19 2Q}{\fs16 2J }\pa
r
}
s17 \cf0 ICK 1PR{\fs15 1 }
\fi750 {\i0 \f20 \fs15 CLR }\par
}
17 \cf0 1J \par
}
s14 \cf0 Vcc{\i0 \fs15 2CLK2PR }\par
}
f30 \fs16 \cf0 2
{\i0 \f20 \fs15 CLR }\par
}
s14 \cf0 (a){\i0 \fs14 Pin}{\i0 \fs15 diagram}{\fs13
(Reprinted}{\fs13 by
}{\fs13 permission}{\f30 \fs13 of}{\f30 \fs14 Texas}{\fs13 Instruments,}{\f
s13
Inc.) }\par
}
0 \fs17 \cf0 Mode
\fi705 of
\fi405 operation
cf0 Asynchronous set
Asynchronous clear
Prohibited
cf0 Hold
Reset
Set
Toggle \par
}
cf0 outputs \par
}
s22 \cf0 Q
\cf0 \fi36 {\i0 \f10 \fs16 1 }
{\i0 \f30 \fs17 0 }
\fi36 {\i0 \f10 \fs16 1 }\par
}
s22 \cf0 Q
\cf0 {\i0 \f30 \fs18 0 }
\fi29 {\i0 \f10 \fs16 1 }
\fi29 {\i0 \f10 \fs16 1 }\par
}
s17 \cf0 P R
\cf0 \fi70 {\i0 \f30 \fs17 0 }
\fi93 {\i0 \f10 \fs16 1 }
\fi70 {\i0 \f30 \fs17 0 }
\cf0 \fi92 {\i0 \f10 \fs15 1 }
\fi92 {\i0 \f10 \fs15 1 }
\fi92 {\i0 \f10 \fs16 1 }
\fi92 {\i0 \f10 \fs16 1 }\par
}
\cf0 CLR
f0 \fi213 {\f10 \fs16 1 }
fi187 {\f30 \fs18 0 }
fi187 {\f30 \fs17 0 }
f0 \fi207 {\f10 \fs16 1 }
fi207 {\f10 \fs16 1 }
fi207 {\f10 \fs16 1 }

fi207 {\f10 \fs15 1 }\par
}
\cf0 CLK
fi122 {\f30 \fs26 x }
fi125 {\f30 \fs26 x }
fi122 {\f30 \fs26 x }
f0 {\b0 \fs17 n }
\b0 n }
\b0 \fs17 n }
\b0 \fs16 n }\par
}
17 \cf0 J
{\i0 \f30 \fs26 x }
{\i0 \f30 \fs26 x }
{\i0 \f30 \fs26 x }\par
}
7 o }
6 1 }\par
}
\cf0 K
\f30 \fs26 x }
\f30 \fs26 x }
\f30 \fs26 x }
f0 {\b0 \fs17 0 }
\b0 \fs17 1 }
\b0 \fs17 0 }
fi23 {\b0 \fs16 1 }\par
}
cf0 no change \par
}
cf0 0
i26 {\fs17 1 }\par
}
fs17 \cf0 1
fs17 0 }\par
}
cf0 opposite
i147 state \par
}
\cf0 X{\b0 \fs14 =}{\f20 irrelevant}{\b0 \f30 \fs17 n}{\b0 \fs14 =}{\f20 po
sitive}{\f20 \fs15 clock}{\f20 pulse }
f0 \fi1997 {\i \f20 \fs14 (h)}{\f20 Mode-select}{\f20 truth}{\f20 table }
f0 \fi1586 {\f20 \fs16 Fig.}{\f20 \fs16 9-15}{\f20 \fs17
The}{\f20 \fs17 7
476}{\i \f20 \fs17 JK}{\f20 \fs17 flip-flop}{\f20 \fs17 IC }\par
}
mplementary{\i \f10 \fs26 (0) }\par
}
utputs are available. Pins 5 and{\fs19
13} are the{\fs19
+5-V}{\i \
fs22 (V,,)} and{\fs18 GND} power \par
}
onnections on this IC.
60 {\b A} truth table for the 7476{\b\i JK} flip-flop is shown in Fig
. 9-15b. The top three lines detail the
ation{\fs18 of} the asynchronous inputs preset{\i \fs18 (PR)}and clear (CLR).
Line{\fs19 3} of the truth table shows the
\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-236 \f20 \fs18 \cf0 proh
ibited state of the asynchronous inputs. Lines 4 through 7 detail the
conditions of the syn\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-230 \f20 \fs18 \cf0 chro
nous inputs for the hold, reset, set, and toggle modes of the 7476{\i \fs18 JK}
flip-flop. The manufacturer
\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-239 \f20 \fs18 \cf0 desc
ribes the 7476 as a{\i \fs19 master-slave}{\b\i \fs17 JKflzp-flop} using positi
ve-pulse triggering. The data at the outputs
\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-236 \f20 \fs18 \cf0 chan
ges on the{\fs19 H-to-L} transition of the clock pulse, as symbolized by the s
mall bubble and{\f10 \fs21 >} symbol
he CLK input{\fs18 on} the flip-flop logic diagram in Fig.{\fs18 9-1%. }
62 Most commercial{\b\i \fs19 JK} flip-flops have asynchronous input features
(such as{\i \fs18 PR} and CLR). Most{\i \fs19 JK }
-flops are pulse-triggered devices like the 7476{\fs19 IC,} but they
can also be purchased as edge\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-237 \f20 \fs18 \cf0 trig
gered units.
67 Flip-flops are the fundamental building blocks of sequential logic circuits.
Therefore,{\fs18 IC} manufac-
\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-234 \f20 \fs18 \cf0 ture

rs produce a variety of flip-flops using both the ?TL and CMOS techn
ologies. Typical TTL
-flops are the 7476{\b\i \fs18 JK} flip-flop with preset and clear, 7474 dual
positive-edge-triggered{\i D} flip-flop
preset and clear, and the 7475 4-bit bistable latch. Typical CMOS flip-flops in
clude the 4724 8-bit
\par}{\phpg\posx855\pvpg\posy9915\absw9147\absh3400 \sl-242 \f20 \fs18 \cf0 addr
essable latch, 40175 quad{\i \fs19 D} flip-flop, and the 74C76{\i \fs19 JK}
flip-flop with preset and clear. \par
}
. 91 \par
}
}
f0 215 \par
}
}
f0 9.24 \par
}
raw the logic symbol for a{\b\i JK} flip-flop with pulse triggering. Label i
nputs as J,{\i \fs19 K}{\i \fs19 ,} and CLK.
\par}{\phpg\posx1465\pvpg\posy1733\absw8400\absh992 \sl-276 \f20 \fs19 \cf0 Labe
l outputs as{\i \fs19 Q} and{\i \fs30 D. }
}
\cf0 9.25{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 four}{\b0 \fs19 synchr
onous}{\b0 \fs19 modes}{\b0 \fs19 of}{\b0 \fs19 operation}{\b0 \fs19 of}{\b
0 \fs19 the}{\b0\i \fs19 JK}{\b0 \fs19 flip-flop. }
fi950 {\b0 \fs17 The}{\b0 \fs17 synchronous}{\b0 \fs17 modes}{\b0 \fs17 of}{
\b0 \fs17 operation}{\b0 \fs17 for}{\b0 \fs17 the}{\b0\i \fs17 JK}{\b0 \
fs17 flip-flop}{\b0 \fs17 are}{\b0 \fs17 hold,}{\b0 \fs17 reset,}{\b0 \fs
17 set,}{\b0 \fs17 and}{\b0 \fs17 toggle. }
f0 9.26{\b0 \fs19
When}{\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs18 of}{\b
0 \fs19 a}{\b0 \fs19 flip-flop}{\b0 \fs19 goes}{\b0 \fs19 LOW,}{\b0 \fs19 H
IGH,}{\b0 \fs19 LOW,}{\b0 \fs19 .HIGH}{\b0 \fs19 on}{\b0 \fs19 repeated}{\b0
\fs19 clock}{\b0 \fs19 pulses,}{\b0 \fs19 it}{\b0 \fs19 is }
fi616 {\b0 \fs19 in}{\b0 \fs19 what}{\b0 \fs19 mode}{\b0 \fs19 of}{\b0 \fs19
operation? }

fi978 {\b0 \fs17 If}{\b0 \fs17 a}{\b0 \fs17 flip-flop's}{\b0 \fs17 output}{
\b0 \fs17 alternates}{\b0 \fs17 states}{\b0 \fs17 (LOW,}{\b0 \fs17 HIGH,
}{\fs17 LOW)}{\b0 \fs17 on}{\b0 \fs17 repeated}{\b0 \fs17 clock}{\b0 \fs
17 pulses,}{\b0 \fs17 it}{\b0 \fs17 is}{\b0 \fs17 in}{\b0 \fs17 the }
fi616 {\b0 \fs17 toggle}{\b0 \fs17 mode. }\par
}
f0 9.27 \par
}
ist the{\i binary} output at output{\fs18 Q}{\fs19 of} the{\i \fs19 JK} fli
p-flop{\fs19 of} Fig. 9-16 after each{\fs19 of} the eight clock
es. \par
}
\cf0 Fig. 9-16{\b0\i \fs17
JK}{\b0 \fs17 flip-flop}{\b0 \fs17 pulse-train}
{\b0 \fs17 problem }\par
}
\cf0 Solution:
\fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 9-13.}{\b0 \fs17
Based}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 truth}{\b0 \fs17 table,}{\
b0 \fs17 the}{\b0 \fs17 binary}{\b0 \fs17 output}{\b0 \fs17 (at}{\b0 \f1
0 \fs15 (2)}{\b0 \fs17 (Fig.}{\b0 \fs17 9-16) }
\b0 \fs17 after}{\b0 \fs17 each}{\b0 \fs17 clock}{\b0 \fs17 pulse}{\b0 \fs
17 is}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
lse{\fs16 a}{\f10 \fs13 =} 1
{\i \fs16 b}{\f10 \fs13 =} 1 \par
}
lse{\fs16 c}{\f10 \fs13 =} 1
{\i \f10 \fs16 d}{\f10 \fs13 =}{\fs16 0 }\par
}
lse{\fs16 e}{\f10 \fs13 =} 0
{\i \f10 \fs16 f}{\i \f10 \fs16 =} 1 \par
}
lse{\b\i \fs15 g}{\dn006 \f10 \fs11 =} 0
{\b\i h}{\f10 \fs13 =} 1 \par
}
\cf0 9.28{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 mode}{\b0 \fs19 of}{\
b0 \fs19 operation}{\b0 \fs19 of}{\b0 \fs19 the}{\b0\i \fs19 JK}{\b0 \fs
19 flip-flop}{\b0 \fs19 during}{\b0 \fs19 each}{\b0 \fs19 of}{\b0 \fs19 t
he}{\b0 \fs19 eight}{\b0 \fs19 clock}{\b0 \fs19 pulses}{\b0 \fs19 shown}{\b0
\fs18 in }

\fi604 {\fs18 Fig.}{\b0 \fs18 9-16. }
\fi962 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 mode-selec
t}{\b0 \fs17 truth}{\b0 \fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \
fs17 9-13.}{\b0 \fs17 Based}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 ta
ble,}{\b0 \fs17 the}{\b0 \fs17 mode}{\b0 \fs17 of}{\b0 \fs17 the}{\b0\i
\fs17 JK}{\b0 \fs17 flip-flop }
\fi602 {\b0 \fs17 during}{\b0 \fs17 each}{\b0 \fs17 clock}{\b0 \fs17 pulse}
{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 9-16}{\b0 \fs17
is}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
pulse{\fs16 a}{\f10 \fs13 =} set
\fs16 pulse}{\i \fs16 b}{\f10 \fs13 =} hold \par
}
pulse{\fs16 c}{\f10 \fs14 =} hold
se{\i \f10 \fs16 d}{\f10 \fs13 =} reset \par
}
pulse{\fs16 e}{\f10 \fs13 =} hold
se{\fs17 f}{\fs17 =} toggle \par
}
pulse{\b\i \fs15 g}{\dn006 \f10 \fs11
=} toggle
se{\b\i h}{\f10 \fs13 =} toggle \par
}
\cf0 9.29{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 asynchronous}{\b0 \fs19
inputs}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 7476}{\b0\i \fs19 JK}{\b0 \
fs19 flip-flop. }
fi952 {\b0 \fs17 The}{\b0 \fs17 asynchronous}{\b0 \fs17 inputs}{\b0 \fs17 to
}{\b0 \fs17 the}{\fs17 7476}{\b0\i \fs17 JK}{\b0 \fs17 flip-flop}{\b0 \f
s17 are}{\b0 \fs17 preset}{\i \f30 \fs19 (PR)}{\b0 \fs17 and}{\b0 \fs17 cl
ear}{\b0 \fs17 (CLR). }\par
}
\par
}
}
AP. 9 \par
}
cf0 9.30{\b0 \fs19
The}{\b0 \fs19 asynchronous}{\b0 \fs19 inputs}{\b0 \f
s19 to}{\b0 \fs19 the}{\b0 \fs19 7476}{\b0\i JK}{\b0 \fs19 flip-flop}{\b

0 \fs19 have}{\b0 \fs19 active }
i962 {\b0 \fs17 The}{\b0 \fs17 asynchronous}{\b0 \fs17 inputs}{\b0 \fs17 to}
{\b0 \fs17 the}{\b0 \fs17 7476}{\b0\i \fs17 JK}{\b0 \fs17 flip-flop}{\b0
\fs17 have}{\b0 \fs17 active}{\b0 \fs17 LOW}{\b0 \fs17 inputs. }\par
}
cf0 9.31{\b0 \fs19
Both}{\b0 \fs19 asynchronous}{\b0 \fs19 inputs}{\b0 \fs
19 to}{\b0 \fs19 the}{\b0 \fs19 7476}{\b0 \fs19 IC}{\b0 \fs19 must}{\b0 \fs
19 be }\par
}
{\phpg\posx1457\pvpg\posy2704\absw801\absh517 \f20 \fs19 \cf0 \f20 \fs19 \cf0 mu
st be
}
HIGH, LOW) inputs. \par
}
HIGH, LOW); the{\b\i \fs18 J} and{\i \fs19 K} inputs \par
}
HIGH, LOW); and a clock pulse must be present for the flip-flop to toggle. \p
ar
}
\cf0 Both asynchronous inputs to the 7476 IC must be HIGH; the{\b\i \fs17
J} and{\i K} inputs must be HIGH, and a
98 clock pulse must be present for the flip-flop to toggle.
{\b \fs19 9.32}{\fs19
List}{\fs19 the}{\fs19 mode}{\fs19 of}{\fs19 opera
tion}{\fs19 of}{\fs19 the}{\fs19 7476}{\i \fs19 JK}{\fs19 flip-flop}{\fs19
during}{\fs19 each}{\fs19 of}{\fs19 the}{\fs19 seven}{\fs19 clock}{\fs19
pulses}{\fs19 shown }
99 {\fs19 in}{\fs19 Fig.}{\fs19 9-17. }\par
}
\cf0 Ql-? \par
}
\par
}
\par
}
cf0 1 \par
}
cf0 1 \par
}
cf0 1 \par
}

cf0 1 \par
}
cf0 1 \par
}
cf0 Fig.{\fs17 9-17 }\par
}
\fs16 \cf0 Solution:
fi962 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 mode-select
}{\b0 \fs17 truth}{\b0 \fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \f
s17 9-15b.}{\b0 \fs17 Based}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 tabl
e,}{\b0 \fs17 the}{\b0 \fs17 mode}{\b0 \fs17 of}{\b0 \fs17 the}{\b0\i \f
s17 JK}{\b0 \fs17 flip-flop }
fi598 {\b0 \fs17 during}{\b0 \fs17 each}{\b0 \fs17 clock}{\b0 \fs17 pulse}{
\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 9-17}{\b0 \fs17
is}{\b0 \fs17 as}{\b0 \fs17 follows: }
fi594 {\b0 \fs17 pulse}{\b0\i \f10 \fs14 a}{\b0 \f10 \fs13 =}{\b0 \fs17 asyn
chronous}{\b0 \fs17 set }
fi594 {\b0 \fs17 pulse}{\b0\i \f10 \fs16 b}{\b0\dn006 \f10 \fs11 =}{\b0 \fs1
7 toggle }
fi594 {\b0 \fs17 pulse}{\i \fs17 c}{\b0 \f10 \fs13 =}{\b0 \fs17 toggle }
fi598 {\b0 \fs17 pulse}{\b0 \fs16 d}{\b0 \f10 \fs14 =}{\b0 \fs17 asynchronou
s}{\b0 \fs17 clear}{\b0 \fs17 (reset) }
fi593 {\b0 \fs17 pulse}{\i \fs17 e}{\b0 \f10 \fs13 =}{\b0 \fs17 set }
fi597 {\b0 \fs17 pulse}{\i \f30 \fs18 f}{\i \f30 \fs18 =}{\b0 \fs17 hold }
fi593 {\b0 \fs17 pulse}{\b0 \fs15 g}{\b0 \f10 \fs14 =}{\b0 \fs17 reset }
f0 {\fs19 9.33}{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19
9-17.}{\b0 \fs19 List}{\b0 \fs19 the}{\b0\i \fs19 binary}{\b0 \fs19 output}{
\b0 \fs19 at}{\b0\i \fs18 Q}{\b0 \fs19 of}{\b0 \fs19 the}{\i \fs19 JK}{\b0
\fs19 flip-flop}{\b0 \fs19 after}{\b0 \fs19 each}{\b0 \fs19 of}{\b0 \fs19
the}{\b0 \fs19 seven}{\b0 \fs19 clock }
fi597 {\b0 \fs19 pulses. }
fi604 Solution:
\fs17 table}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 9-1%.}{\b0 \fs17 Based}
{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 table,}{\b0 \fs17 the}{\b0 \fs17
binary}{\b0 \fs17 output}{\b0 \fs17 (at}{\i \fs17 Q}{\i \fs17 )}{\b0 \
fs17 after}{\b0 \fs17 each}{\b0 \fs17 clock }
fi598 {\b0 \fs17 pulse}{\b0 \fs17 is}{\b0 \fs17 as}{\b0 \fs17 follows: }
fi598 {\b0 \fs17 pulse}{\b0\i \f10 \fs14 a}{\b0 \f10 \fs13 =}{\b0 \fs16 1 }
fi598 {\b0 \fs17 pulse}{\b0\i \f10 \fs16 b}{\b0 \f10 \fs13 =}{\b0 \fs17 0 }

fi598 {\b0 \fs17 pulse}{\i c}{\b0 \f10 \fs13 =}{\b0 \fs17 1 }
fi598 {\b0 \fs17 pulse}{\b0 \fs16 d}{\b0 \f10 \fs13 =}{\b0 0 }
fi594 {\b0 \fs17 pulse}{\i e}{\b0 \f10 \fs13 =}{\b0 \fs17 1 }
fi598 {\b0 \fs17 pulse}{\i \f30 \fs18 f}{\i \f30 \fs18 =}{\fs17 1 }
fi598 {\b0 \fs17 pulse}{\b0 \fs15 g}{\b0 \f10 \fs13 =}{\b0 \fs17 0 }\par
}
.{\fs16 91 }\par
}
}
\par
}
\cf0 9-6{\fs18
TRIGGERING}{\fs18 OF}{\fs18 FLIP-FLOPS }
fi368 {\b0 \fs18 Most}{\b0 \fs18 complicated}{\b0 \fs18 digital}{\b0 \fs18
equipment}{\b0 \fs18 operates}{\b0 \fs18 as}{\b0 \fs18 a}{\b0 \fs18 synch
ronous}{\b0 \fs18 sequential}{\b0 \fs18 system.}{\b0 \fs18 This}{\b0 \fs18
suggests }
\b0 \fs18 that}{\b0 \fs18 a}{\b0 \fs18 master}{\b0 \fs18 clock}{\b0 \fs18 si
gnal}{\b0 \fs18 is}{\b0 \fs18 sent}{\b0 \fs18 to}{\b0 \fs18 all}{\b0 \fs18
parts}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 system}{\b0 \fs18 to}{\b0 \fs1
8 coordinate}{\b0 \fs18 system}{\b0 \fs18 operation.}{\b0 \fs18 A}{\b0 \fs1
8 typical }
\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 train}{\b0 \fs18 is}{\b0 \fs18
shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-18.}{\b0 \fs18 Remember}
{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 horizontal}{\b0 \fs18 distance
}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 waveform}{\b0 \fs18 is }
\b0\i \fs19 time}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs18 vertical}{\b0 \fs
18 distance}{\b0 \fs18 is}{\b0\i \fs19 voltage.}{\b0 \fs18 The}{\b0 \fs18
clock}{\b0 \fs18 pulses}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 the}{\b0
\fs18 figure}{\b0 \fs18 are}{\b0 \fs18 for}{\b0 \fs18 a}{\b0 \fs19 TTL}{\
b0 \fs18 device }
\b0 \fs18 because}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs19 +5-V}{\b0 \fs18
and}{\b0 \fs18 GND}{\b0 \fs18 voltages.}{\b0 \fs18 Other}{\b0 \fs18 digit
al}{\b0 \fs18 circuits}{\b0 \fs18 use}{\b0 \fs18 clocks,}{\b0 \fs18 but}{\b
0 \fs18 the}{\b0 \fs18 voltages}{\b0 \fs18 might}{\b0 \fs18 be }
\b0 \fs18 different. }\par
}
cf0 Positive
\par}{\phpg\posx2579\pvpg\posy3551\absw616\absh320 \sl-175 \f20 \fs14 \cf0 (lead
ing) \par
}
cf0 Negative
(trailing)
\b\i \f10 \fs20 J }\par
}
f0 a \par
}
cf0 3
b0 \f10 \fs13 4 }\par
}
\cf0 Fig. 9-18{\fs17
Clock}{\b0 \fs17 pulses }\par
}
\cf0 Start at the{\fs18 left}{\fs18 of} the waveform in Fig. 9-18. The voltag
e is at first LOW, or at GND. That is also
ed a logical{\fs19 0.} Pulse{\i \fs19 a} shows the{\i \fs19 leading}{\i \fs1
9 edge} (also called the{\i \fs19 positive}{\i \fs19 edge)} of the waveform g
oing
GND voltage to{\i \fs19 +5}{\b V.} This edge of the waveform may
also be called the LOW-to-HIGH
\par}{\phpg\posx855\pvpg\posy5419\absw9501\absh2369 \sl-239 \f20 \fs18 \cf0 (L-t
o-H) edge{\fs19 of} the waveform. On the right side of pulse{\i \fs19 a,} the
waveform drops from{\i \fs19 +5}{\b \fs19 V} to GND
\par}{\phpg\posx855\pvpg\posy5419\absw9501\absh2369 \sl-238 \f20 \fs18 \cf0 volt
age. This edge is called the HIGH-to-LOW (H-to-L) edge of the clock pulse. It
is also called the
\fs19 negatiue-going} edge or the{\i \fs19 trailing} edge of the clock puls
e.
76 Some flip-flops transfer data from input to output on the positive
(leading) edge{\fs19 of} the clock
e. These flip-flops are referred to as{\i \fs19 positive-edge-triggered}
{\i \fs19 flip-flops.} An example of such a
-flop is shown in Fig. 9-19. The clock input is shown by the middle waveform. Th
e top waveform
1 shows the Q output when the positive-edge-triggered flip-flop is in its to
ggle mode. Note that each
1 leading edge (positive-going edge) of the clock toggles the flip-flop. \par
}
\cf0 Positive\par}{\phpg\posx1823\pvpg\posy8513\absw955\absh488 \sl-186 \f20 \fs14 \cf0 edgetriggered
6 {\fs15 FF }\par
}
\cf0 N{\f20 \fs14 ega}{\b\dn006 \f10 \fs11 t}{\f20 \fs14 i}{\f20 \fs14 \\}{\f2
0 \fs14 e- }
0 \fs14 edge-triggered }
95 {\f20 \fs14 FF }\par
}
\cf0 Fig.{\fs16 9-19}{\b0 \fs17
Triggering}{\b0 \fs16 of}{\b0 \fs17 pos
itive-}{\b0 \fs17 and}{\b0 \fs17 negative-edge}{\b0 \fs17 flip-flops }\par
}
8 \cf0 Other flip-flops are classed as{\i \fs19 negatiue-edge-triggeredflip-fl
ops.} The operation of a negative-edge\par}{\phpg\posx855\pvpg\posy11396\absw9431\absh2149 \sl-239 \f20 \fs18 \cf0 \fi
23 triggered flip-flop is shown by the bottom two waveforms in Fig. 9-19.
The middle waveform is the
23 clock input. The bottom waveform is the Q output when the flip-flop is in it
s toggle mode. Note that
27 this flip-flop toggles to its opposite state only on the trailing edge (neg
ative-going edge) of the clock
27 pulse. It is important to note the difference in timing of the po
sitive- and negative-edge-triggered
27 flip-flops shown in Fig. 9-19. The timing difference is of great importance
in some applications.
391 Many{\i \fs19 JK} flip-flops are{\i \fs19 pulse-triggered} units. The
se pulse-triggered devices are{\i \fs19 master-slave}{\i \fs19 JK }
\fs19 flip-flops.}{\b A} master-slave{\i \fs19 JK} flip-flop{\fs18 is} actu
ally several gates and flip-flops wired together to use the
31 entire clock pulse to transfer data from input to output. In Fig. 9-1
8, pulse{\fs18 c} will be used to help
31 explain how pulse triggering works with a master-slave{\i \fs19 JK}
flip-flop. The following events happen, \par
}
\par
}
cf0 FLIP-FLOPS{\fs20 AND} OTHER MULTIVIBRATORS \par
}
cf0 [CHAP.{\fs18 9 }\par
}
uring the{\fs18 pulsc-triggering} scqucncc, at thc numbcrcd points{\fs20 in}
Fig.{\b \f10 \fs17 9-18: }
\fi384 1. Thc input and output of thc flip-flop arc isolated.
64 {\b \f10 \fs19 2.}
Data{\fs19 is} entered from{\fs19 the}{\b\i \fs19 J
} and{\b\i \f30 \fs22 K}{\fs18 inputs,} but{\fs18 it}{\fs19 is}{\fs19 n
ot} transfcrrcd{\fs19 to} thc output.

64 {\fs20 3.} The{\b\i \f30 \fs22 J} and{\b\i \f30 \fs22 K} inputs are dis
abled.
60 {\b \f10 \fs18 4.}
Previously entcrcd data from{\b\i \fs20 J} and{\b\i
\f30 \fs23 K} is transfcrrcd{\fs20 to} thc{\fs19 output. }
20 Notc} that thc data actually appcars at thc outputs at point{\b \f10 \fs18
4} (trailing cdgc){\fs20 of} thc wavcform in Fig.
\f10 \fs18 9-18.} Thc logic symbol for a pulsc-triggcred flipflop has{\b \f10 \f
s18 a} small bubble attached{\fs19 to} !he clock (CLK)
t{\fs20 (scc} Fig.{\b \f10 \fs17 Y-15a)}{\fs19 to}{\fs19 show} that{\fs19 t
he} actual transfcr{\fs20 of} data to the output takes place{\fs20 on} the H-t
o-L
sition{\fs19 of}{\fs19 the} clock pulsc.
64 Thc wavcforms in Fig.{\fs19 9-20}{\fs19 will} aid undcrstanding{\fs20
of} the opcration of the mastcr-slave{\b\i \f30 \fs22 JK }
-flop and pulse triggcring.Start at thc{\fs19 left}{\fs20 of} thc wavcform dia
gram.{\fs19 The} top thrcc waveforms are
synchronous inputs{\b\i \fs19 J}{\b\i \fs19 ,}{\b\i \f30 \fs21 K.} and C1.K.{
\b \fs20 The} top linc describes{\fs19 the} modc of opcration during{\fs20 th
c} clock
4 {\fs19 pulse.} Thc bottom linc is the rcsultant output{\fs20 of} the{\b\i
\f30 \fs22 JK} flip-flop at output{\fs19 Q. }\par
}
0 \fs16 \cf0 Fig.{\i \f10 \fs16 9-20}{\fs17
Waveform}{\fs17 diagram}{\fs17
for}{\fs17 a}{\fs17 mastcr-slavc}{\fs17 JK} flipflop
f0 \fi377 {\f30 \fs21 Look}{\b0 \fs20 at}{\b0 \fs20 clock}{\b0 \fs20 (CLK)pul
sc}{\f10 \fs17 1}{\b0 \fs20 shown}{\b0 \fs19 in}{\b0 \fs20 Fig.}{\i \f10 \
fs17 9-20.}{\b0 \fs19 Both}{\i \fs19 J}{\b0 \fs20 and}{\i \f30 \fs22 K}{\
b0 \fs20 inputs}{\b0 \fs20 arc}{\b0 \fs20 LOW.}{\b0 \fs20 This}{\b0 \fs19
is}{\b0 \fs20 the}{\b0 \fs20 hold }
\b0 \fs20 condition.}{\b0 \fs20 and}{\i \f10 \fs15 so}{\b0 \fs20 thc}{\i \f1
0 \fs17 Q}{\b0 \fs20 output}{\b0 \fs20 stays}{\b0 \fs20 at}{\b0 \fs18 0.}{
\b0 \fs20 as}{\b0 \fs19 it}{\f10 \fs17 was}{\b0 \fs20 beforc}{\b0 \fs20 pul
se}{\f10 \fs18 1.}{\f30 \fs21 Look}{\b0 \fs20 at}{\b0 \fs20 clock}{\b0 \fs20
(CLK)pulse}{\f10 \fs19 2.}{\b0 \fs20 Inputs }
\i \fs19 J}{\b0 \fs20 and}{\i \f10 \fs18 K}{\b0 \fs20 arc}{\b0 \fs20 in}{
\b0 \fs20 thc}{\b0 \fs19 set}{\b0 \fs20 mode}{\i \fs20 (}{\i \fs20 I}{\b0 \
f10 \fs17 =}{\f10 \fs18 1.}{\i \f30 \fs22 K}{\b0 \f10 \fs16 =}{\fs19 0).}{
\b0 \fs19 On}{\b0 \fs20 the}{\b0 \fs20 trailing}{\b0 \fs20 edge}{\b0 \fs20 o
f}{\b0 \fs20 pulsc}{\b0 \fs19 2.}{\b0 \fs20 output}{\b0 \fs19 Q}{\f10 \fs17
gcxs}{\b0 \fs19 to}{\b0 \fs20 a}{\b0 \fs20 logical }
fi37 {\f10 \fs18 I.}{\b0 \fs20 or}{\b0 \fs20 HIGH.}{\b0 \fs20 Pulsc}{\b0 \f
s20 3}{\b0 \fs20 sccs}{\b0 \fs20 the}{\b0 \fs20 inputs}{\b0 \fs20 in}{\b0
\fs20 the}{\b0 \fs20 rcsct}{\b0 \fs20 modc}{\i \fs20 (}{\i \fs20 I}{\b0
\f10 \fs14 =}{\fs19 0.}{\i \f30 \fs22 K}{\b0 \f10 \fs14 =}{\b0 \fs19 1).}{\
b0 \fs20 On}{\b0 \fs20 thc}{\b0 \fs20 trailing}{\b0 \fs20 cdgc}{\b0 \fs20

of}{\b0 \fs20 clock }
\b0 \fs20 pulse}{\b0 \fs21 3.}{\b0 \fs20 output}{\i \f30 \fs23 Q}{\b0 \fs20
is}{\b0 \fs20 rcsct.}{\b0 \fs20 or}{\b0 \fs20 cleared}{\b0 \fs19 to}{\b0 \
fs19 0.}{\b0 \fs20 Pulsc}{\f10 \fs18 4}{\f10 \fs18 sccs}{\b0 \fs20 thc}{\b0
\fs20 inputs}{\b0 \fs20 in}{\b0 \fs20 the}{\b0 \fs20 toggle}{\b0 \fs20 m
odc}{\i \fs19 (}{\i \fs19 J}{\b0 \f10 \fs56 -}{\f10 \fs18 1,}{\i \f30 \fs22
K}{\b0 \f10 \fs17 =}{\f10 \fs18 1). }
\b0 \fs20 On}{\b0 \fs19 thc}{\b0 \fs20 trailing}{\b0 \fs20 edge}{\b0 \fs19 o
f}{\b0 \fs20 clock}{\b0 \fs20 pulse}{\f10 \fs17 4.}{\b0 \fs20 output}{\i \f3
0 \fs22 Q}{\b0 \fs20 toggles}{\b0 \fs19 to}{\b0 \fs20 a}{\b0 \fs20 logical}
{\f10 \fs18 1.}{\b0 \fs20 or}{\b0 \fs20 HIGH.}{\b0 \fs20 Pulse}{\i \f10 \fs1
9 5}{\b0 \fs20 sees}{\b0 \fs20 the}{\b0 \fs20 inputs }
\b0 \fs20 in}{\b0 \fs20 thc}{\b0 \fs20 toggle}{\b0 \fs19 mcdc}{\b0 \fs20 a
gain.}{\f10 \fs18 On}{\b0 \fs20 the}{\b0 \fs20 trailing}{\b0 \fs20 edge}{\b0
\fs20 of}{\b0 \fs20 pulx}{\i \f10 \fs19 5.}{\b0 \fs20 output}{\b0 \fs19
Q}{\b0 \fs20 togglcs}{\b0 \fs20 to}{\f10 \fs18 a}{\b0 \fs20 logical}{\b0 \
fs19 0}{\b0 \fs20 or}{\f10 \fs19 LOW. }
fi377 {\b0 \fs20 Pulsc}{\b0 \fs19 6}{\b0 \fs20 (Fig.}{\b0 \fs19 9-20)}{\b0 \f
s19 will}{\b0 \fs19 show}{\b0 \fs20 an}{\b0 \fs20 unusual}{\b0 \fs20 charact
cristic}{\b0 \fs20 of}{\b0 \fs20 thc}{\b0 \fs20 mastcr-slavc}{\b0 \fs20 JK}{
\b0 \fs20 Hip-flop.}{\b0 \fs20 Notc}{\b0 \fs20 that, }
\b0 \fs20 on}{\b0 \fs20 the}{\b0 \fs20 leading}{\b0 \fs20 edgc}{\b0 \fs20 o
f}{\b0 \fs20 clock}{\b0 \fs20 pulse}{\b0 \fs19 6.}{\b0 \fs20 input}{\i \f30
\fs21 K}{\b0 \f10 \fs14 =}{\dn006 \f10 \fs18 1}{\b0 \fs20 and}{\i \fs19
I}{\b0 \f10 \fs16 =}{\b0 \fs19 0.}{\b0 \fs20 When}{\b0 \fs20 clock}{\b0 \fs
20 pulsc}{\b0 \fs18 6}{\b0 \fs19 is}{\b0 \fs20 HIGH,}{\b0 \fs20 input}{\i \
f30 \fs22 K }
\f10 \fs17 goes}{\b0 \fs20 from}{\f10 \fs18 1}{\b0 \fs20 to}{\b0 \fs19 0}{\b
0 \fs20 while}{\i \fs19 J}{\f10 \fs17 gcxs}{\b0 \fs20 from}{\f30 \fs19 Q}{
\b0 \fs20 to}{\b0 \fs19 I}{\b0 \fs17 to}{\b0 \fs17 0.}{\f30 \fs20 On}{\b0
\fs20 the}{\b0 \fs20 trailing}{\f10 \fs17 edge}{\b0 \fs19 of}{\b0 \fs20 clo
ck}{\b0 \fs18 pulse}{\fs18 6.}{\b0 \fs20 both}{\b0 \fs20 inputs}{\i \fs19 (
}{\i \fs19 J}{\b0 \fs20 and }
\i \f30 \fs22 K}{\i \f30 \fs22 )}{\b0 \fs20 arc}{\b0 \fs20 LOW.}{\b0 \fs20
Howcvcr.}{\b0 \fs20 as}{\b0 \fs20 strangc}{\f10
as}{\b0 \fs19 it}{\b0
\fs20 may}{\b0 \fs20 sccm.}{\b0 \fs19 thc}{\b0 \fs20 flip-flop}{\b0 \fs1
9 still}{\i \fs19 toggles}{\b0 \fs19 to}{\b0 \fs20 a}{\b0 \fs20 HIGH.}
{\b0 \fs20 The }
\b0 \fs20 master-slave}{\i \f30 \fs22 JK}{\b0 \fs20 flip-flop}{\i \f10 \fs17
remetnbers}{\i \f10 \fs17 any}{\i \f10 \fs17 or}{\i \f10 \fs19 all}{\i \f
10 \fs18 HIGH}{\i \f10 inpiits}{\i \f10 \fs18 while}{\i \f10 the}{\i \f10
\fs18 clock}{\i \f10 \fs17 pulse}{\b0 \f10 \fs17 is}{\i \f10 \fs18 HIGH.}
{\b0 \fs20 During }
\b0 \fs20 pulse}{\b0 \fs19 6,}{\b0 \fs20 both}{\b0 \fs20 input}{\i \f10 \fs1
8 1}{\b0 \fs20 and}{\i \f30 \fs22 K}{\b0 \fs20
were}{\b0 \fs20 HIGH}{\b
0 \fs20 for}{\b0 \fs20 a}{\b0 \fs20 short}{\b0 \fs20 time}{\b0 \fs20 w
hen}{\b0 \fs20 the}{\b0 \fs20 clock}{\b0 \fs20 input}{\b0 \fs18 was}{\b0
\fs20 HIGH.}{\f30 \fs21 The }
\b0 \fs20 flip-flop}{\b0 \fs20 thercforc}{\b0 \fs20 rcgardcd}{\b0 \fs19 this}
{\b0 \fs20 as}{\b0 \fs20 thc}{\b0 \fs20 togglc}{\b0 \fs20 condition. }

fi384 {\b0 \fs20 Next}{\b0 \fs20
refer}{\b0 \fs19 to}{\b0 \fs20 clock}{\b
0 \fs20 pulse}{\f10 \fs18 7}{\b0 \fs20 (Fig.}{\b0 \fs19 9-20).}{\b0 \fs2
0 Pulsc}{\f10 \fs19 7}{\b0 \fs20 sccs}{\b0 \fs20 inputs}{\b0 \f10 \fs35
.'}{\b0 \fs20 and}{\i \f30 \fs22 K}{\b0 \fs20
in}{\b0 \fs20 the}{\b0 \f
s20 hold}{\b0 \fs20 mode }
\i \fs20 (}{\i \fs20 I}{\b0 \f10 \fs16 =}{\fs19 0,}{\i \f30 \fs23 K}{\b0 \f10
\fs14 =}{\fs19 0).}{\b0 \fs20 Output}{\b0 \fs19 Q}{\b0 \fs20 remains}{\b
0 \fs20 in}{\b0 \fs19 its}{\b0 \fs20 prcscnt}{\b0 \fs20 state}{\b0 \fs20 (s
tays}{\b0 \fs20 at}{\f10 \fs17 1).}{\b0 \fs20 Pulsc}{\f10 \fs18 8}{\f10 \f
s18 sccs}{\b0 \fs20 input}{\i \f10 \fs19 K}{\b0 \fs20 at}{\f10 \fs18 1}{
\b0 \fs20 for}{\b0 \fs20 a}{\b0 \fs20 short }
fi23 {\b0 \fs20 timc}{\b0 \fs20 and}{\b0 \fs20 input}{\i \f30 \fs22 J}{\b0
\fs20 at}{\f10 \fs18 U.}{\b0 \fs20 Thc}{\b0 \fs20 flip-flop}{\b0 \fs20 i
ntcrprcts}{\b0 \fs20 this}{\b0 \fs20 as}{\b0 \fs20 thc}{\b0 \fs20 rcsct}
{\b0 \fs20 modc.}{\b0 \fs20 Output}{\i \f30 \fs23 Q}{\b0 \fs20 therefore}
{\b0 \fs20 re%& }
\b0 \fs20 output}{\b0 \f10 \fs18 @}{\b0 \fs20 to}{\b0 \fs19 0}{\b0 \fs20 on
}{\b0 \fs20 thc}{\b0 \fs20 trailing}{\b0 \fs20 edge}{\b0 \fs20 of}{\b0 \fs20
clock}{\b0 \fs20 pulse}{\f10 \fs19 8. }
fi387 {\b0 \fs20 Rcfcr}{\b0 \fs20 to}{\b0 \fs20 clock}{\b0 \fs20 pulse}{\b0 \
fs18 9}{\b0 \fs20 (Fig.}{\fs19 9-20).}{\f30 \fs21 The}{\b0 \fs20 mastcr-sla
ve}{\i \f30 \fs22 JK}{\b0 \fs20 flip-flop}{\i \f30 \fs20 secs}{\b0 \fs20 bo
th}{\i \f10 \fs17
1}{\b0 \fs20 and}{\i \f30 \fs22 K}{\b0 \fs20 inputs}{\b
0 \fs20 at}{\b0 \fs20 a }
fi27 {\f10 \fs17 I}{\f10 \fs17 D}{\f10 \fs17 W}{\f30 \fs19 on}{\b0 \fs20 the
}{\b0 \fs20 positive}{\f10 \fs17 edge}{\b0 \fs19 o}{\b0 \fs19 f}{\b0 \fs20
clock}{\b0 \fs20 pulse}{\b0 \fs18 9.}{\b0 \fs20 When}{\b0 \fs19 thc}{\b0 \fs
20 pulse}{\b0 \fs19 is}{\b0 \fs20 HIGH.}{\b0 \fs20 input}{\i \f10 \fs18 K}
{\f10 \fs17 goes}{\b0 \fs20 HIGH}{\b0 \fs20 for}{\b0 \fs20 a}{\b0 \fs20 sh
ort }
fi24 {\b0 \fs20 limc}{\b0 \fs20 and}{\b0 \fs20 thcn}{\b0 \fs18 input}{\i \fs2
0 I}{\f10 \fs17 gocs}{\fs20 HIGH}{\b0 \fs20 for}{\b0 \fs20 a}{\b0 \fs20
short}{\b0 \fs20 timc.}{\b0 \fs20 Inputs}{\i \f30 \fs22 J}{\b0 \fs20 and}{\
i \f30 \fs23 K}{\b0 \fs20 arc}{\i \f10 \fs17 nor}{\b0 \fs20 HIGH}{\b0 \fs2
0 at}{\b0 \fs20 the}{\b0 \fs20 same}{\b0 \fs20 timc, }\par
}
. 91 \par
}
}
\par
}
owever. On the trailing edge of clock pulse{\fs19 9,} both inputs{\b\
i \fs19 (}{\b\i \fs19 J} and{\b\i \fs19 K}{\b\i \fs19 )} are{\fs19 LOW
.} The flip-flop
rprets this as the toggle mode. Output{\i \fs18 Q} changes states and goes fr
om a{\fs19 0} to a 1.
62 It should be noted that not all{\i \fs19 JK} flip-flops are of the mas
ter-slave type. Some{\i \fs19 JK} flip-flops are
-triggered. Manufacturers' data manuals will specify if the flip-flop{\b
\fs19 is} edge-triggered or pulse\par}{\phpg\posx859\pvpg\posy1386\absw9142\absh1072 \sl-239 \f20 \fs18 \cf0 trig
gered. \par
}
}
f0 9.34 \par
}
lip-flops are classified as either edge-triggered or
}
{\phpg\posx6585\pvpg\posy3515\absw1393\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 triggered units. \par
}
lip-flops are classified as either edge-triggered or pulse-triggered units.
\par
}
cf0 9.35{\f10 \fs17
A}{\b0 \fs18 positive-edge-triggered}{\b0 \fs18 flip-f
lop}{\b0 \fs18 transfers}{\b0 \fs18 data}{\b0 \fs18 from}{\b0 \fs18 input}{
\b0 \fs18 to}{\b0 \fs18 output}{\b0 \fs18 on}{\b0 \fs18 the }
i591 {\b0 \fs18 trailing)}{\b0 \fs18 edge}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \
fs18 clock}{\b0 \fs18 pulse. }
}
{\phpg\posx8947\pvpg\posy4871\absw783\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (l
eading, \par
}
\fs17 \cf0 A{\b0 \fs17 positive-edge-triggered}{\b0 \fs17 flip-flop}{\b0 \f
s17 transfers}{\b0 \fs17 data}{\b0 \fs17 from}{\b0 \fs17 input}{\b0 \fs1
7 to}{\b0 \fs17 output}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 leading
}{\b0 \fs17 edge}{\b0 \fs17 of}{\b0 \fs17 the }
\b0 \fs17 clock}{\b0 \fs17 pulse. }\par
}
f0 9.36 \par
}
\cf0 A{\b0 \f20 \fs18
negative-edge-triggered}{\b0 \f20 \fs18 flip-flop}{\
b0 \f20 \fs18 transfers}{\b0 \f20 \fs18
data}{\b0 \f20 \fs18
from}{\b0 \
f20 \fs18
input}{\b0 \f20 \fs18
to}{\b0 \f20 \fs18 output}{\b0 \f20 \fs1
8 on}{\b0 \f20 \fs18
the }
{\b0 \f20 \fs18 (H-to-L,}{\b0 \f20 \fs18 L-to-H)}{\b0 \f20 \fs18 transition}{\
b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 clock}{\b0 \f20 \fs18
pulse. }
{\f20 \fs17 Solution: }
\fi358 {\f20 \fs17 A}{\b0 \f20 \fs17 negative-edge-triggered}{\b0 \f20 \fs17 f
lip-flop}{\b0 \f20 \fs17 transfers}{\b0 \f20 \fs17 data}{\b0 \f20 \fs17 from
}{\b0 \f20 \fs17 input}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 output}{\b0 \f20 \
fs17 on}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 ,H-to-Ltransition}{\b0 \f20 \fs1
7 of}{\b0 \f20 \fs17 the }
{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 pulse. }\par
}
f0 9.37 \par
}
he master-slave{\i \fs19 JK} flip-flop is an example of a
}
positive-edge-, pulse-) triggered unit. \par
}
he master-slave{\b\i \fs17 JK} flip-flop is an example of a pulse-triggere
d unit. \par
}
f0 9.38 \par
}
efer to Fig.{\fs19 9-20.} List the{\i \fs19 binary} output (at{\i \f10 \fs26
0) }
}
he \par
}
\cf0 after{\i0 \fs18 each}{\i0 \fs18 of}{\i0 \fs18 the}{\i0 \fs18 nine}{\i0
\fs18 clock}{\i0 \fs18 pulses. }\par
}
output is always the complement of the{\fs16 Q} output{\fs17 on} a flip-f
lop.Therefore the binary outputs \par
}
at{\i \f10 \fs24 0) }\par
}
in{\fs17 Fig.}{\fs16 9-20}{\fs17 after}{\fs17 each}{\fs17 clock}{\fs17
pulse}{\fs17 are}{\fs17 as}{\fs17 follows: }\par
}
ulse{\fs16 1}{\dn006 \f10 \fs11 =}{\fs17 1 }
e{\b \fs17 2}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}

ulse{\b 3}{\dn006 \f10 \fs11 =} 1
e{\b \f30 \fs18 4}{\dn006 \f10 \fs11 =} 0 \par
}
ulse{\fs17 5}{\dn006 \f10 \fs11 =}{\fs16 1 }
e{\b\i \fs16 6}{\f10 \fs13 =}{\fs16 0 }\par
}
ulse{\fs17 7}{\dn006 \f10 \fs11 =}{\fs16 0 }
e 8{\dn006 \f10 \fs11 =} 1 \par
}
ulse{\b 9}{\f10 \fs13 =}{\fs17 0 }\par
}
\cf0 9.39{\b0 \fs18
List}{\b0 \fs18 the}{\b0\i \fs19 binary}{\b0 \fs18 o
utput}{\b0 \fs18 (at}{\b0\i \fs18 Q}{\b0\i \fs18 )}{\b0 of}{\b0 \fs18 the}{\
b0 \fs18 master-slave}{\b0\i \fs19 JK}{\b0 \fs18 flip-flop}{\b0 \fs18 of}{\
b0 \fs18 Fig.}{\fs18 9-21}{\b0\i \fs19 after}{\b0 \fs18 each}{\fs19 of}{\b0
\fs18 the}{\b0 \fs18 eight }
\fi591 {\b0 \fs18 clock}{\b0 \fs18 pulses. }
\fi964 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 truth}{\b0
\fs17
table}{\b0 \fs17
in}{\b0 \fs17
Fig.}{\b0 \fs17 9-13.}{\b0 \fs1
7 According}{\b0 \fs17 to}{\b0 \fs17 this}{\b0 \fs17 table,}{\b0 \fs17
the}{\b0 \fs17 binary}{\b0 \fs17 output}{\b0 \fs17 (at}{\i \f30 \fs19 Q
)}{\b0 \fs17 of}{\b0 \fs17
the }
\fi600 {\b0 \fs17 master-slave}{\i \fs17 JK}{\b0 \fs17 flip-flop}{\b0 \fs17
(Fig.}{\b0 \fs17 9-21)}{\b0 \fs17 after}{\b0 \fs17 each}{\b0 \fs17 clock}{
\b0 \fs17 pulse}{\b0 \fs17 is}{\b0 \fs17 as}{\b0 \fs17 follows: }\par
}
ulse{\b\i \fs16 a}{\dn006 \f10 \fs11 =}{\fs17 1 }
e{\i \fs16 h}{\f10 \fs13 =} 0 \par
}
ulse{\b \f10 \fs14 c}{\f10 \fs13 =}{\fs16 1 }
e{\b\i \fs17 d}{\f10 \fs14 =}{\fs16 0 }\par
}
ulse{\fs16 e}{\dn006 \f10 \fs11 =} 0
}
ulse{\fs15 g}{\f10 \fs13 =}{\fs16 0 }
e{\b\i h}{\f10 \fs13 =} 1 \par
}
\par
}
IP-FLOPS{\fs17 AND}{\fs17 OTHER}{\fs17 MULTIVIBRATORS }\par
}
AP.{\fs16 9 }\par
}
f0 9.40 \par
}
ist the mode of operation for the master-slave{\b\i \fs19 JK} flip-flop of
Fig.{\i \fs18 9-21} for each clock pulse. \par
}
\cf0 Fig.{\f10 \fs15 9-21}{\i \fs17
JK}{\b0
flip-flop}{\b0 pulse-train}{
\b0 problem }\par
}
\cf0 Solution:
fi359 {\b0 Refer}{\b0 to}{\b0 the}{\b0 mode-select}{\b0 truth}{\b0 tab
le}{\b0 in}{\b0 Fig.}{\b0 \fs16 9-13.}{\b0 According}{\b0 to}{\b0 the}{
\b0 table,}{\b0 the}{\b0 modes}{\b0 \fs16 of}{\b0 operation}{\b0 for
}
\b0 the}{\b0 master-slave}{\b0\i \fs17 JK}{\b0 flip-flop}{\b0 (Fig.}{\b0
9-21)}{\b0 for}{\b0 each}{\b0 clock}{\b0 pulse}{\b0 are}{\b0 as}{\b0
follows: }\par
}
ulse{\i \f10 \fs14 a}{\f10 \fs13 =} set
e{\i \fs16 b}{\f10 \fs11 =} reset \par
}
ulse{\f10 \fs13 c}{\f10 \fs11 =} toggle
e{\b\i \f10 \fs16 d}{\f10 \fs11 =} toggle \par
}
lse{\b\i \fs16 e }\par
}
\f20 \fs16 hold }\par
}
ulse{\i \f10 \fs14 g}{\f10 \fs13 =} reset
e{\i \fs16 h}{\f10 \fs11 =} toggle \par
}
ulse{\i \f30 \fs19 f=} toggle \par
}
f0 9.41 \par
}

Refer to Fig.{\i \fs18 9-21.} Assume the{\i \fs19 JK} flip-flop is a neg
ative-edge-triggered unit. List the{\i \fs18 binary }
put (at{\i \fs18 Q}{\i \fs18 )} of the edge-triggered flip-flop after each of
the eight clock pulses.
374 {\fs16 Refer}{\fs16 to}{\fs16 the}{\fs16 truth}{\fs16 table}{\fs16 i
n}{\fs16 Fig.}{\fs17 9-13,}{\fs16 but}{\fs16 remember}{\fs16 that}{\fs16
this}{\fs16 is}{\fs16 a}{\fs16 negative-edge-triggered}{\i \fs17 JK}{\f
s16 flip-flop }
s16 (it}{\fs16 triggers}{\fs16 on}{\fs16 the}{\fs16 H-to-L}{\fs16 trans
ition}{\fs16 of}{\fs16 the}{\fs16 clock}{\fs16 pulse).}{\fs16 The}{\fs1
6 binary}{\fs16 output}{\fs16 (at}{\i \fs17 Q}{\i \fs17 )}{\fs16 for}{
\fs16 the}{\fs16 negative-cdgc- }
s16 triggered}{\i \fs17 JK}{\fs16 flip-flop}{\fs16 after}{\fs16 each}{\fs
16 clock}{\fs16 pulse}{\fs16 is}{\fs16 as}{\fs16 follows: }\par
}
lse{\i \f10 \fs13 a}{\f10 \fs11 =} 1
{\i \fs16 b}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}
lse{\f10 \fs14 c}{\dn006 \f10 \fs10 =}{\fs17 1 }
{\b\i \f10 d}{\f10 \fs11 =}{\fs17 0 }\par
}
lse{\i e}{\f10 \fs11 =}{\fs16 0 }
{\i \f30 \fs19 f}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}
lse{\i \f10 \fs14 g}{\dn006 \f10 \fs10 =}{\fs16 0 }
{\i \fs16 h}{\dn006 \f10 \fs11 =} 1 \par
}
\cf0 9-7{\fs18
ASTABLE}{\fs18 MULTMBRATORS-CLOCKS }
f0 {\fs18 Introduction }
fi373 {\b0 \fs18 A}{\b0 \fs18 multivibrator}{\b0 \fs19 (MV)}{\b0 \fs18 is}
{\b0 \fs18 a}{\b0 \fs18 pulse}{\b0 \fs18 generator}{\b0 \fs18 circuit}{\
b0 \fs18 which}{\b0 \fs18 produces}{\b0 \fs18 a}{\b0 \fs18 rectangular-w
ave}{\b0 \fs18 output. }
fi25 {\b0 \fs18 Multivibrators}{\b0 \fs18 are}{\b0 \fs18 classified}{\b0 \fs18
as}{\b0\i \fs18 astable,}{\b0\i \fs18 bistable,}{\b0 \fs18 or}{\b0\i \fs18
monostable. }
fi373 {\f10 \fs17 An}{\b0 \fs18 astable}{\fs19 MV}{\b0 \fs18 is}{\b0 \fs18 a
lso}{\b0 \fs18 called}{\b0 \fs18 a}{\b0\i \fs18 free-running}{\b0\i \fs18 m
ultiribrator.}{\b0 \fs18 The}{\b0 \fs18 astable}{\b0 \fs19 MV}{\b0 \fs18 gen
erates}{\b0 \fs18 a}{\b0 \fs18 continuous }

fi20 {\b0 \fs18 flow}{\b0 \fs18 of}{\b0 \fs18 pulses}{\b0 \fs18 as}{\b0 \fs18
depicted}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-22a. }
fi380 {\b0 \fs18 A}{\b0 \fs18 bistable}{\b0 \fs18 multivibrator}{\b0 \fs18
is}{\b0 \fs18 also}{\b0 \fs18 called}{\b0 \fs18 a}{\b0\i \fs17 flip-pop.}{
\b0 \fs18 The}{\b0 \fs18 bistable}{\b0 \fs18 MV}{\b0 \fs18 is}{\b0 \fs18 a
lways}{\b0 \fs19 in}{\b0 \fs18 one}{\b0 \fs18 of}{\b0 \fs18 two}{\b0 \fs18
stable }
fi22 {\b0 \fs18 states}{\b0 \fs18 (set}{\b0 \fs18 or}{\b0 \fs18 reset).}{\b0
\fs18 The}{\b0 \fs18 basic}{\b0 \fs18 idea}{\b0 \fs18 of}{\b0 \fs18 a}{
\b0 \fs18 bistable}{\b0 \fs19 MV}{\b0 \fs18 is}{\b0 \fs18 diagrammed}{\b0
\fs19 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-22b,}{\b0 \fs18 where}{\b0 \fs18
the}{\b0 \fs18 input }
\b0 \fs18 pulse}{\b0 \fs18 triggers}{\b0 \fs18 a}{\b0 \fs18 change}{\b0 \fs18
in}{\b0 \fs18 output}{\b0 \fs18 from}{\b0 \fs18 LOW}{\b0 \fs18 to}{\b0 \fs
19 HIGH. }
fi371 A{\b0 \fs18 monostable}{\fs19 MV}{\b0 \fs18 is}{\b0 \fs18 also}{\b
0 \fs18 called}{\b0 \fs18 a}{\b0\i \fs18 one-shot}{\b0\i \fs18 multivibr
ator.}{\b0 \fs18 When}{\b0 \fs18 the}{\b0 \fs18 one-shot}{\b0 \fs18 is}{
\b0 \fs18 triggered,}{\b0 \fs18 as }
\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-22c,}{\b0 \fs18
the}{\b0 \fs19 MV}{\b0 \fs18 generates}{\b0 \fs18 a}{\b0 \fs18 single}{\b0
\fs18 short}{\b0 \fs18 pulse. }
f0 \fi25 {\fs18 Astable}{\fs18 Multivibrator }
fi387 {\b0 \fs18 The}{\b0 \fs18 versatile}{\b0\i \fs19 555}{\b0 \fs18 Time
r}{\b0 \fs19 IC}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 used}{\b0 \fs18
to}{\b0 \fs18 implement}{\b0 \fs18 an}{\b0 \fs18 astable,}{\b0 \fs18 b
istable,}{\b0 \fs18 or}{\b0 \fs18 monostable }
fi36 {\b0 \fs18 multivibrator.}{\b0 \fs18 The}{\b0\i \fs19 555}{\b0 \fs18 tim
er}{\b0 \fs19 is}{\b0 \fs18 shown}{\b0 \fs18 wired}{\b0 \fs18 as}{\b0 \fs18
a}{\b0 \fs18 free-running}{\b0 \fs18 (astable)}{\b0 \fs18 multivibrator}{\b
0 \fs18 in}{\b0 \fs18 Fig.}{\b0\i \fs18 9-23a.}{\b0 If }\par
}
.{\fs16 91 }\par
}
}
\fs19 1 }\par
}
\fs16 \cf0 Fig.{\fs16 9-22 }
f0 {\b0 \fs18 (kilohms)}{\b0 \fs18 and}{\b0\i \fs18 C}{\b0\dn006 \f10 \fs11
= }\par
}
{\phpg\posx905\pvpg\posy6047\absw3476\absh303 \f20 \fs18 \cf0 \f20 \fs18 \cf0 bo
th resistors{\b\i \fs19 (}{\b\i \fs19 R}{\b\i \fs19 A} and{\i \fs19 R}{\i
\fs19 H}{\i \fs19 )}{\fs18

4.7}{\b \fs26 ka }\par
}
\cf0 =
\fs18 level}{\f20 \fs18 pulses}{\f20 \fs18 at}{\f20 \fs18 a}{\f20 \fs18 fr
equency}{\f20 \fs18 of}{\f20 \fs18 1}{\b \f20 \fs18 Hz. }\par
}
80{\b pF,} the output will{\fs18 be} a string of{\fs19 TTL }\par
}
\cf0 The output frequency of the{\fs18 MV} shown in{\fs18 Fig.}{\i \fs18 9-2
3a} can be increased by{\i \fs18 decreasing} the value{\fs18 of }
resistors and/or capacitor. For example, if the resistors{\b\i \fs19 (R
A} and{\i \fs19 RB) }{\dn006 \f10 \fs11 =} 330{\f30 \fs20 fl} and{\b C}{\d
n006 \f10 \fs11 =}{\fs18 0.1}{\b pF, }
\par}{\phpg\posx909\pvpg\posy6602\absw9376\absh1167 \sl-240 \f20 \fs18 \cf0 then
the output frequency will rise to about 10 kHz.
\fi1948 {\b \f30 \fs12 t5}{\fs22 v }\par
}
I \par
}
\par
}
0 - \par
}
cf0 TTL
t \par
}
\cf0 0
.
. \par
}
\fs15 \cf0 RA{\i0 \f10 \fs13 =} RB{\i0 \f10 \fs13 =} 4.7{\b\i0 \fs15 k!L?
}
f0 {\f10 \fs14 C}{\i0 \f10 \fs11
=}{\i0 \fs15 100pF }
\par}{\phpg\posx5271\pvpg\posy9193\absw1450\absh919 \sl-276 \i \f20 \fs15 \cf0 R
A =RB=33052
fi35 {\f10 \fs14 C}{\i0 \f10 \fs14
=0.1}{\i0 \fs15 pF }\par
}
\par
}
\cf0 (a){\f20 \fs14 555}{\i0 \f20 \fs14 timer}{\i0 \f20 \fs14 IC}{\i0 \f20
\fs14 wired}{\i0 \f20 \fs14 as}{\i0 \f20 \fs14 an}{\i0 \f20 \fs14 astable}{
\i0 \f20 \fs14 MV }
cf0 \fi1981 {\i0 \f20 \fs15 Top}{\i0 \f20 \fs14 View }\par
}

utput
\fi130 Reset \par
}
iTl \par
}
\par
}
4 \cf0 (c){\i \fs14 555}{\fs14 timer}{\fs14 pin}{\fs14 diagram }
{\b \fs16 Fig.}{\b \fs16 9-23 }\par
}
cf0 Rb
0 \fi48 {\fs22 c }\par
}
\cf0 7
fi93 {\fs15 6 }
\fs15 -}{\fs15 2 }\par
}
s{\b \f30 \fs16 14 }
\fi70 {\i \fs16 555 }
3 {\fs14 timer }
27 {\fs15 IC }\par
}
11 \cf0 R A \par
}
}
cf0 3 \par
}
utput{\i \f30 \fs13 x}{\f10 \fs14 1}{\fs15 Hz }\par
}
utput{\i \f30 \fs13 x}{\fs15 10}{\b \fs15 kHz }\par
}
i y h a r g e
Threshold
Control Voltage \par
}
\cf0 ( h ){\fs14 555}{\i0 \fs14 timer}{\i0 \fs14 DIP}{\i0 \fs14 IC }\par

}
\par
}
}
AP. 9 \par
}
\cf0 The{\i \fs19 555} timer is commonly sold in an 8-pin DIP IC li
ke that pictured in Fig.{\i \fs19 9-23b.} The pin
tions for the{\i \fs19 555} timer IC are shown in Fig.{\i \fs19 9-23c. }
56 Another astable multivibrator circuit is shown in Fig.{\i \fs19 9-24.} This
free-running MV uses{\fs19 two} CMOS
rters from the{\i \fs19 4069} hex inverter IC. Note the use of a 10-V d
c power source, which is common
\par}{\phpg\posx843\pvpg\posy1373\absw9222\absh1285 \sl-242 \f20 \fs18 \cf0 (but
not standard) in CMOS circuits. The frequency of the output is about
{\fs19 10} kHz. The output
uency can be varied by changing the value(s) of the resistors and capacitor in
the circuit. \par
}
\cf0 Another astable multivibrator circuit using CMOS inverters is diag
rammed in Fig.{\i \fs19 9-25.} This
\par}{\phpg\posx843\pvpg\posy6413\absw9163\absh1060 \sl-235 \f20 \fs18 \cf0 free
-running MV contains a crystal-controlled oscillator{\i \fs19 (4049a} and{\i \
fs19 4049b)} with inverters{\i \fs19 (4049c} and
\fs19 4049d)} used to square up the waveform. The output frequency is controlled
by the natural frequency
he crystal, which is 100 kHz in this circuit. The frequency is very stable. The
square-wave output is
\par}{\phpg\posx843\pvpg\posy6413\absw9163\absh1060 \sl-238 \f20 \fs18 \cf0 at C
MOS voltage levels (about{\fs18 10}{\b V} p-p). \par
}
0 \par
}
0{\f20 \fs21 v }\par
}
00-kHz{\fs16 10-v}{\b \fs14 p-p}{\fs15 output }\par
}
J l J l J l - 0 . . \par
}
I 1 \par
}
\par
}
\par
}
\cf0 Fig.{\fs16 9-25}{\b0 \fs17
Crystal-controlled}{\b0 \fs17 astable}{\
b0 \fs17 MV }\par
}
8 \cf0 Astable multivibrators are often called{\i \fs19 clocks} when the
y are used in digital systems. A system
ck is used in all synchronous digital and microprocessor-based systems. Some imp
ortant character\par}{\phpg\posx833\pvpg\posy11159\absw9610\absh2288 \sl-230 \f20 \fs18 \cf0 ist
ics of a clock in a digital system are{\i \fs19 frequency,}{\i \fs19 clock}{\
i \fs19 cycle}{\i \fs19 time,}{\i \fs19 frequency}{\i \fs19 stability,}{\i
\fs19 voltage}{\i \fs19 stability, }
{\i \fs19 shape} of the waveform. The clock cycle time is calculated by using
the formula
\fi4586 1
4169 {\b\i \fs19 T}{\b\i \fs19 =}{\dn006 \f10 \fs15 - }
4563 {\fs24 f }
\par}{\phpg\posx833\pvpg\posy11159\absw9610\absh2288 \sl-354 \f20 \fs18 \cf0 whe
re{\i \fs19 T}{\i \fs19 =} time,{\fs18 s }
570 {\i \f30 \fs22 f=} frequency,{\b \fs19 Hz }
\par}{\phpg\posx833\pvpg\posy11159\absw9610\absh2288 \sl-237 \f20 \fs18 \cf0 Clo
cks require square-wave pulses with fast rise times and fast fall times. \par
}
0 CHAP.{\b0 \fs16 91 }\par
}
}
\par
}
LVED PROBLEMS \par
}
f0 9.42 \par
}
ist three classes{\fs18 of} multivibrators.
55 {\fs16 Multivibrators}{\fs16 are}{\fs16 classified}{\fs16 as}{\fs16 ast
able,}{\fs16 bistablc,}{\fs16 or}{\fs16 monostable. }\par

}
cf0 9.43{\b0 \fs18
Another}{\b0 \fs18 name}{\b0 \fs18 for}{\b0 \fs18 an}
{\b0 \fs18 astable}{\b0 \fs18 multivibrator}{\b0 \fs18 is }
}
par
}
n astable MV is also called a frec-running multivibrator. \par
}
f0 9.44 \par
}
nother name for a bistable multivibrator is
\fs16 Solution: }
58 {\b \fs16 A}{\fs16 bistablc}{\fs16 MV}{\fs16 is}{\fs16 also}{\fs16 c
alled}{\fs16 a}{\b \fs15 flip-flop. }\par
}
par
}
cf0 9.45{\b0 \fs18
Another}{\b0 \fs18 name}{\b0 \fs18 for}{\b0 \fs18 a}{\
b0 \fs18 monostable}{\b0 \fs18 multivibrator}{\b0 \fs18 is }
i949 {\fs16 A}{\b0 \fs16 monostable}{\b0 \fs16 MV}{\b0 \fs16 is}{\b0 \fs16
also}{\b0 \fs16 called}{\b0 \fs16 a}{\b0 \fs16 one-shot}{\b0 \fs16 mul
tivibrator. }\par
}
par
}
f0 9.46 \par
}
ncreasing the value of both resistors and the capacitor{\fs18 in} the MV ci
rcuit shown in Fig.{\i 9-23a }\par
}
ll
}
\cf0 (decrease, increase) the output frequency.
{\fs16 Increasing}{\fs17 the}{\fs16 value}{\fs16 of}{\fs16 the}{\fs16 r
esistors}{\fs16 and}{\fs16 capacitor}{\fs17 in}{\fs16 the}{\fs16 free-r
unning}{\fs17 MV}{\fs16 of}{\fs16 Fig.}{\i \fs16 9-23a}{\fs16 will}{\fs1
6 decrease }\par
}
he output frequency. \par
}
f0 9.47 \par
}
in number
}
s next{\fs18 to} the dot on the 8-pin DIP IC shown in{\fs17 Fig.} 9-236. \
par
}
in 1 is located next to the dot on{\fs16 top} of the &pin DIP{\f10 \
fs15 1C}{\fs16 of} Fig.{\i \fs16 9-23h. }\par
}
f0 9.48 \par
}
he clock pulses from the MV shown in Fig. 9-23a
}
are, are not) compatible with{\fs19 TTL. }\par
}
6 \cf0 The clock pulses from the{\i \fs17 555} timcr shown in Fig.{\i 9
-23a} are at TTL voltage levels.{\fs16 (LOW}{\dn006 \f10 \fs10 = }
\par}{\phpg\posx1431\pvpg\posy10529\absw7572\absh381 \sl-213 \f20 \fs16 \cf0 HIG
H{\f10 \fs11 =} about{\f10 \fs15
+4.S} V.) \par
}
{\fs16 V}{\fs16 and }\par
}
\cf0 9.49{\b0 \fs18
The}{\b0 \fs18 4069}{\b0 \fs18 inverters}{\b0 \fs18
used}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 MV}{\b0 \fs18 shown}{\b0 \fs19
in}{\b0 \fs18 Fig.}{\b0 \fs18 9-24}{\b0 \fs18 are }
fi945 {\b0 \fs16 The}{\b0 \fs16 4069}{\b0 \fs16 is}{\b0 \fs16 a}{\b0 \fs16
CMOS}{\b0 \fs16 hex}{\b0 \fs16 inverter}{\b0 \fs16 IC. }\par
}
(CMOS,{\fs19 TTL)}{\fs18 ICs. }\par
}
cf0 9.50 \par
}
The astable MV shown in Fig.
}
(9-24, 9-25) would have the greatest frequency stability. \par
}
6 \cf0 The free-running MV shown{\fs16
in} Fig.{\fs16 9-25} would
have great frequency stability. The oscillator's
\par}{\phpg\posx1465\pvpg\posy13267\absw8236\absh389 \sl-224 \f20 \fs16 \cf0 fre
quency is crystal-controlled. \par
}
0 224 \par
}
IP-FLOPS{\b AND}{\fs17 OTHER}{\b MULTIVIBRATORS }\par
}
}
cf0 9.51{\b0
The}{\b0 output}{\b0 from}{\b0 the}{\b0 crystal-controlled}
{\b0 free-running}{\b0 MV}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 9-25}{\b0 is}
{\b0 compatible}{\b0 with }\par
}
}
\cf0 (CMOS,{\fs19 TTL)}{\fs18 circuit. }
{\fs17 The}{\b \fs17 10-V}{\fs17 output}{\fs17 from}{\fs17 the}{\b \fs17
MV}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs17 9-25}{\fs17 means}{\fs16
it}{\fs17 is}{\fs17 compatible}{\fs17 with}{\fs17 a}{\b \fs17 CMOS}{\
fs17 circuit.}{\fs17 TTL }\par
}
oltage levels{\fs17 must} range from{\fs16 0} to{\i \fs17 +5.5}{\b
V}
only. \par
}
cf0 9.52{\b0 \fs18
The}{\b0 \fs18 clock}{\b0 \fs18 cycle}{\b0 \fs18 time}
{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 MV}{\b0 \fs18 shown}{\b0 \fs18 in}
{\b0 \fs18 Fig.}{\b0 \fs18 9-25}{\b0 \fs18 is }
}
\cf0 The formula{\fs16 is}{\i \fs17 T}{\f10 \fs11 =}{\fs16 l/f,} so{\i
\fs17 T}{\dn006 \f10 \fs11 =}{\fs17 1/100,000}{\dn006 \f10 \fs11
= }
{\b \fs16 is}{\fs17 0.00001}{\b \f10 \fs15 s,}{\fs16 or}{\fs16 10}{\b \f3
0 \fs15 ,us. }\par
}
cf0 S. \par
}
.00001.{\fs17 The}{\fs17 clock}{\fs17 cycle}{\fs17 time}{\fs17 for}{\fs17

the}{\fs17 MV}{\fs17 shown}{\fs17 in}{\fs17 Fig. }\par
}
\cf0 9-8{\fs19
MONOSTABLE}{\fs19 MULTIVIBRATORS }
fi365 {\b0 \fs18 The}{\b0\i \fs18 one-shot}{\b0 \fs18 or}{\b0\i \fs18 mono
stable}{\b0\i \fs18 multir?ibrator}{\b0 \fs18 generates}{\b0 \fs18 an}{\b0
\fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 of}{\b0 \fs18 fixed}{\b0 \fs18 d
uration}{\b0 \fs18 each}{\b0 \fs18 time }
\b0 \fs18 its}{\b0 \fs18 input}{\b0 \fs18 is}{\b0 \fs18 triggered.}{\b0 \fs1
8 The}{\b0 \fs18 basic}{\b0 \fs18 idea}{\b0 \fs18 of}{\b0 \fs18 the}{\b
0 \fs18 monostable}{\b0 \fs18 MV}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs1
8 graphically}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-22c.}{\b0 \fs18 T
he }
\b0 \fs18 input}{\b0 \fs18 trigger}{\b0 \fs18 may}{\b0 \fs18 be}{\b0 \fs18 a
n}{\b0 \fs18 entire}{\b0 \fs18 pulse,}{\b0 \fs18 an}{\b0 \fs18 L-to-H}{\b0 \
fs18 transition}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 clock,}{\b0 \fs18
or}{\b0 \fs18 an}{\b0 \fs18 H-to-L}{\b0 \fs18 transition}{\b0 \fs18 of}{\b0
\fs18 the }
\b0 \fs18 trigger}{\b0 \fs18 pulse}{\b0 \fs18 depending}{\b0 \fs18 on}{\b0
\fs18 the}{\b0 \fs18 one-shot.}{\b0 \fs18 The}{\b0 \fs18 output}{\b0 \f
s18 pulse}{\b0 \fs18 may}{\b0 \fs18 be}{\b0 \fs18 either}{\b0 \fs18 a}
{\b0 \fs18 positive}{\b0 \fs18 or}{\b0 \fs18 a}{\b0 \fs18 negative }
\b0 \fs18 pulse.}{\b0 \fs18 The}{\b0 \fs18 designer}{\b0 \fs18 can}{\b0 \fs18
adjust}{\b0 \fs18 the}{\b0 \fs18 time}{\b0 \fs18 duration}{\b0 \fs18 of}{\
b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 by}{\b0 \fs18 us
ing}{\b0 \fs18 different}{\b0 \fs18 resistor-capaci- }
\b0 \fs18 tor}{\b0 \fs18 combinations. }
fi365 {\b0 \fs18 The}{\b0 \fs18 adaptable}{\b0 \fs18 555}{\b0 \fs18 timer}{\b
0 \fs19 IC}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 wired}{\b0 \fs18 as}{\
b0 \fs18 a}{\b0 \fs18 one-shot}{\b0 \fs18 MV}{\b0 \fs18 in}{\b0 \fs18 Fig.
}{\b0 \fs18 9-26.} A{\b0 \fs18 short}{\b0 \fs18 negative}{\b0 \fs18 input }
\b0 \fs18 pulse}{\b0 \fs18 causes}{\b0 \fs18 the}{\b0 \fs18 longer}{\b0 \fs18
positive}{\b0 \fs18 output}{\b0 \fs18 pulse.}{\b0 \fs18 The}{\b0 \fs18 tim
e}{\b0 \fs18 duration}{\b0\i \fs17 t}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs
18 output}{\b0 \fs18 pulse}{\b0 \fs18 is}{\b0 \fs18 calculated}{\b0 \fs18 b
y }
\b0 \fs18 using}{\b0 \fs18 the}{\b0 \fs18 formula }
fi3946 {\b0\i \fs18 t}{\b0\dn006 \f10 \fs13 =}{\b0 \fs18 l.lR,C }
\b0 \fs18 where}{\i \fs19 RA}{\b0 \fs18 is}{\b0 \fs18 equal}{\b0 \fs18 to}
{\b0 \fs18 the}{\b0 \fs18 value}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18
resistor}{\b0 \fs19 in}{\b0 \fs18 ohms,}{\b0\i \fs19 C}{\b0 \fs18 is}{\b
0 \fs18 equal}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 value}{\b0 \fs18 o
f}{\b0 \fs18 the}{\b0 \fs18 capacitor}{\b0 \fs18 in }
\b0 \fs18 farads,}{\b0 \fs18 and}{\b0\i \fs18 t}{\b0 \fs18 is}{\b0 \fs18 e
qual}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 time}{\b0 \fs18 duration}{\b0 \
fs18 of}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 in}
{\b0 \fs18 seconds.}{\b0 \fs18 By}{\b0 \fs18 calculating}{\b0 \fs18 the}{\b
0 \fs18 output }
\b0 \fs18 pulse}{\b0 \fs18 time}{\b0 \fs18 duration}{\b0\i \fs18
t}{\b0 \fs
18 for}{\b0 \fs18 the}{\b0 \fs18 one-shot}{\b0 \fs18 shown}{\b0 \fs18 in}
{\b0 \fs18 Fig.}{\b0 \fs18 9-26,}{\b0 \fs18 we}{\b0 \fs18 have }
f0 \fi3030 {\b0\i \fs18 t}{\b0\dn006 \f10 \fs13 =}{\b0 \fs18 1.1}{\b0\i \fs23
x}{\b0 \fs18 10,000}{\b0 \f10 \fs20 x}{\b0 \fs18 0.0001}{\b0\dn006 \f10 \fs
13 =}{\b0 \fs18 1.1}{\b0 \fs19 s }
\b0 \fs18 The}{\b0 \fs18 calculated}{\b0 \fs18 time}{\b0 \fs18 duration}{\b
0\i \fs18
t}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 p
ulse}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 one-shot}{\b0 \fs18 MV}{\b0 \
fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-26}{\b0 \fs19 is}{\b
0 \fs18 1.1}{\b0 \f10 \fs17 s. }
fi368 {\b0 \fs18 The}{\b0 \fs18 one-shot}{\b0 \fs19 MV}{\b0 \fs18 shown}{\
b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-26}{\b0 \fs18 is}{\b0\i \fs18
nonretriggerable.}{\b0 \fs18 This}{\b0 \fs18 means}{\b0 \fs18 that}{\b0 \f
s18 when}{\b0 \fs18 the}{\b0 \fs18 one-shot's }
\b0 \fs18 output}{\b0 \fs18 is}{\b0 \fs19 HIGH,}{\b0 \fs18 it}{\b0 \fs18 wil
l}{\b0 \fs18 disregard}{\b0 \fs18 any}{\b0 \fs18 input}{\b0 \fs18 pulse.}{
\b0 \fs18 Retriggerable}{\b0 \fs18 monostable}{\b0 \fs18 MVs}{\b0 \fs18 al
so}{\b0 \fs18 are}{\b0 \fs18 available. }
f0 \fi3260 {\b0 \f10 \fs14 +5}{\b0 \fs22 v }\par
}
49 \cf0 +l
0 \fi520 {\f30 \fs67 ii }
f20 \fs14 loo}{\f20 \fs13 lJF}{\fs30 T" }\par
}
\cf0 Fig. 9-26{\b0\i \fs17
555}{\b0 \fs17 timer}{\b0 \fs17 IC}{\b0 \fs1
7 wired}{\b0 \fs17 as}{\b0 \fs16 a}{\b0 \fs17 monostable}{\fs17 MV }\pa
r
}
utput \par
}
n \par
}
\cf0 Input
24 U }\par
}
\cf0 timer
14 Trigger }\par
}
.{\fs16 91 }\par
}
IP-FLOPS{\b \fs17 AND}{\fs17 OTHER}{\fs17 MULTIVIBRATORS }\par
}
\par
}
\cf0 In Fig. 9-27 the TTL 74121 one-shot{\fs19 IC} is shown being used to gen
erate{\i \fs19 single}{\fs19 TTL} level pulses
a mechanical switch is pressed. Many digital trainers used in technic
al education and design
\par}{\phpg\posx851\pvpg\posy1386\absw9175\absh651 \sl-239 \f20 \fs18 \cf0 work
use circuits of this type to generate single clock pulses. Both positive and
negative clock pulses \par
}
{\phpg\posx863\pvpg\posy2111\absw4856\absh686 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ar
e available from the normal (Q) and complementary
fi4380 {\b\i \f10 \fs14 +5}{\fs21 v }\par
}
\par
}
{\phpg\posx5695\pvpg\posy1888\absw616\absh469 \f20 \fs41 \cf0 \f20 \fs41 \cf0 (e
) \par
}
utputs{\fs18 of} the 74121 one-shot{\fs19 IC. }\par
}
0{\b \f20 \fs15 kS2: }\par
}
4 \par
}
0 = \par
}
-{\fs11
- }\par
}
{\phpg\posx4195\pvpg\posy5094\absw567\absh168 \f10 \fs14 \cf0 \f10 \fs14 \cf0 0.
01{\b \f20 \fs13 pF }\par
}
cf0 Q \par
}
D \par
}
0 \fs16 \cf0 Fig.{\fs16 9-27}{\b0 \fs16
74121}{\b0 \fs17 IC}{\b0 \fs16 w
ired}{\b0 to}{\b0 \fs16 generate}{\b0 \fs16 single}{\fs16 clock}{\b0 \fs1
6 pulses }
f0 \fi361 {\b0 \fs18 The}{\b0 \fs18 duration}{\b0 \fs18 of}{\b0 \fs18 the}
{\b0 \fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs
18 adjusted}{\b0 \fs18 by}{\b0 \fs18 varying}{\b0 \fs18 the}{\b0 \fs18
values}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 resistor}{\b0\i \fs19 R}

{\b0 \fs18 and }
\b0 \fs18 capacitor}{\b0 \fs19 C.}{\b0 \fs19 To}{\b0 \fs18 calculate}{\b0 \fs
18 the}{\b0 \fs18 time}{\b0 \fs18 duration}{\b0 \fs18 of}{\b0 \fs18 the}{
\b0 \fs18 output}{\b0 \fs18 pulse,}{\b0 \fs18 use}{\b0 \fs18 the}{\b0 \fs18
formula }
fi4009 {\b0\i \fs18 t}{\b0\dn006 \f10 \fs11 =}{\b0 \fs18 0.7RC }
\b0 \fs18 where}{\b0\i \fs19 R}{\b0 \fs18 equals}{\b0 \fs18 the}{\b0 \fs18
value}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 resistor}{\b0 \fs18 in}{\b0
\fs18 ohms,}{\b0\i \fs19 C}{\b0 \fs18 equals}{\b0 \fs18 the}{\b0 \fs18 valu
e}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 capacitor}{\b0 \fs18 in}{\b0 \fs18
farads,}{\b0 \fs18 and}{\b0\i \fs18 t }
\b0 \fs19 is}{\b0 \fs18 the}{\b0 \fs18 duration}{\b0 \fs18 of}{\b0 \fs18 t
he}{\b0 \fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 in}{\b0 \fs18 seconds.}{\b
0 \fs18 By}{\b0 \fs18 calculating}{\b0 \fs18 the}{\b0 \fs18 duration}{\b0
\fs19 of}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 pulse}{\b0 \fs18 in}{
\b0 \fs18 the }
\b0 \fs18 one-shot}{\b0 \fs18 circuit}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs
18 9-27,}{\b0 \fs18 we}{\b0 \fs18 have }
fi2777 {\b0\i \fs18 t}{\b0\dn006 \f10 \fs13 =}{\b0 \fs18 0.7}{\b0 \f10 \fs14
X}{\b0 \fs19 15,000}{\b0 \f10 \fs14 X}{\b0 \fs19 0.000001}{\b0\dn006 \f10 \f
s13 =}{\b0 \fs19 0.0105}{\fs19 s }
\b0 \fs18 The}{\b0 \fs18 calculated}{\b0 \fs18 time}{\b0 \fs18 duration}{\b
0\i \fs18 t}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 pu
lse}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 one-shot}{\b0 \fs18 shown}{\b
0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-27}{\b0 \fs18 is}{\b0 \fs19 0.0105}
{\b0 \fs19 s, }
\b0 \fs18 or}{\b0 \fs18 about}{\b0 \fs18 10}{\b0 \fs18 ms. }
fi367 {\fs18 A}{\b0 \fs18 pin}{\b0 \fs18 diagram}{\b0 \fs18 and}{\b0 \fs18
truth}{\b0 \fs18 table}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 74121}{\b0
\fs18 one-shot}{\b0 \fs18 IC}{\b0 \fs18 are}{\b0 \fs18 reproduced}{\b0 \fs1
8 in}{\b0 \fs18 Fig.}{\b0 \fs18 9-28.}{\b0 \fs18 Note}{\b0 \fs18 that }
\b0 \fs18 the}{\b0 \fs18 74121}{\b0 \fs18 one-shot}{\b0 \fs18 has}{\b0 \fs1
8 three}{\b0 \fs18 separate}{\b0 \fs18 trigger}{\b0 \fs18 inputs}{\b0 \fs2
4 (XI,}{\b0\i \fs24 X2,}{\b0 \fs18 and}{\b0\i \fs18 B).}{\b0 \fs18 Typically
,}{\b0 \fs18 only}{\b0 \fs18 a}{\b0 \fs18 single}{\b0 \fs18 input }\par
}
put
\fs13 -L }\par
}
Ll+l
\fi968 {\f20 \fs15 outputs }
{\fs14 1 }\par
}
par
}
'2p \par
}
e-shot \par
}
{\phpg\posx3131\pvpg\posy5625\absw288\absh172 \f20 \fs15 \cf0 \f20 \fs15 \cf0 sw
l \par
}
03 {\b \f10 \fs39 i }\par
}
15 \cf0 H{\f10 \fs13 =}{\fs15 HIGH} voltage level
i651 L{\f10 \fs13 =} LOW voltage level
i648 {\fs15 X}{\f10 \fs13 =} don't care
i652 {\fs18 t}{\dn006 \f10 \fs13 =} LOW-to-HIGH transition
i656 {\f10 \fs15 .1}{\f10 \fs11 =} HIGH-to-LOW transition
0 \fi400 {\i \fs14 (h)} Truth table{\b\i \fs14 (Courtesy}{\fs13 of'}{\b\i \fs
14 Signetics}{\b\i \fs14 Corporation) }
0 {\b \fs16 Fig.}{\b \fs16 9-28 }\par
}
\par
}
}
AP.{\fs17 9 }\par
}
{\phpg\posx843\pvpg\posy1351\absw6192\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 wo
uld be used at a time. In the application shown in Fig. 9-27, input \par
}
d trigger input \par
}
\f30 \fs36 \cf0 x,
\cf0 {\b0\i0 \f20 \fs18 reacts}{\b0\i0 \f20 \fs18 to}{\b0\i0 \f20 \fs18 a}{\b0
\i0 \f20 \fs18 HIGH-to-LOW}{\b0\i0 \f20 \fs18 transition}{\b0\i0 \f20 \fs18
of}{\b0\i0 \f20 \fs18 the}{\b0\i0 \f20 \fs18 trigger}{\b0\i0 \f20 \fs18 puls
e. }\par
}
pin{\b \fs19 3)} serves as the trigger \par
}

put. This matches the situation in line 6{\fs19 of} the truth table (Fig. 9-286
). Inputs \par
}
nd{\i \fs19 B} are{\fs19 HIGH, }\par
}
\cf0 Monostable multivibrators are useful, for timing applications when
precision{\fs19
is} not critical.
\par}{\phpg\posx855\pvpg\posy2058\absw8951\absh430 \sl-242 \f20 \fs18 \cf0 One-s
hots are also used to introduce delays in digital systems. \par
}
LVED PROBLEMS \par
}
cf0 9.53{\b0
A }\par
}
cf0 Solution: \par
}
8 \cf0 multivibrator is{\fs18 also} referred to{\fs18 as} a one-shot.
\fi365 {\b \f10 \fs15 A}{\fs16 monostable}{\fs16 MV}{\fs16 is}{\fs16 al
so}{\fs16 called}{\fs16 a}{\fs16 one-shot. }
The one-shot circuit shown in Fig.{\fs18 9-26} generates{\fs17 a }
\par}{\phpg\posx1439\pvpg\posy3539\absw5055\absh1833 \sl-233 \f20 \fs18 \cf0 whe
n triggered by a negative input pulse.
}
f0 9.54 \par
}
negative, positive) output pulse \par
}
\cf0 The one-shot shown{\fs17 in} Fig.{\fs16 9-26} generates a positivc
output pulse when triggered{\fs16 by} a negative input
e. \par
}
7 \cf0 9.55 \par
}
hat is the calculated time duration{\i \fs17 t}{\fs18 of} the output pulse
from the one-shot shown in Fig. 9-26
\par}{\phpg\posx1447\pvpg\posy6465\absw8408\absh438 \sl-242 \f20 \fs18 \cf0 if{\
b\i \fs19 RA}{\dn006 \f10 \fs13 =}{\fs18 9.1}{\b \fs19 kSZ} and{\fs19 C}
{\dn006 \f10 \fs13 =} 10{\b \fs18 pF? }\par
}
\cf0 Solution:
fi352 {\b0 The}{\b0 formula}{\b0 is}{\i \fs16 t}{\b0\dn006 \f10 \fs11 =
}\par
}
.1{\b\i \fs17 RAC;}then \par
}
cf0 t{\i0\dn006 \f10 \fs10 =}{\b\i0 \fs16 1 }\par
}
{\f20 \fs16 1}{\fs17 x}{\f20 \fs16 9}{\f20 \fs16 100}{\fs18 x}{\b\i \f20 \
fs16 0.0000}{\f20 \fs16 1 }\par
}
he calculated time duration of the output{\fs16 pulsc} from thc one-s
hot would{\fs16 be}{\fs16 0.1}{\b \f30 \fs15 s. }\par
}
7 \cf0 9.56 \par
}
\par
}
H-to-L, L-to-H) transition{\fs18 of} the trigger pulse shown in Fig.
9-27 causes the \par
}
ne-shot to generate an output pulse.
\fs16 Solution: }
66 {\fs16 In}{\fs16 Fig.}{\fs16 9-27,}{\fs16 it}{\fs16
is}{\fs16 the}
{\fs16
HIGH-to-L,OW}{\fs16
transition}{\fs16 of}{\fs16 the}{\fs16 tr
igger}{\fs16 pulse}{\fs16
that}{\fs16
causes}{\fs16 the}{\fs16 one-s
hot}{\fs16 to }
16 generate}{\fs16 an}{\fs16 output}{\fs16 pulse. }\par
}
In Fig.{\fs19 9-27,} what will be the time duration{\fs18 of} the output puls
e{\fs18 if}{\i R}{\dn006 \f10 \fs11 = }
i360 {\fs16 The}{\fs16 formula}{\fs16 is }
i3747 {\b\i \fs15 t}{\dn006 \f10 \fs11
=}{\fs16 0.7RC }
b \f10 \fs10 SO }
i3150 {\i \fs15 t}{\dn006 \f10 \fs11 =}{\fs16 0.7}{\f10 \fs18 x}{\fs16 30,0
00}{\f10 \fs17 x}{\b \f10 \fs15 0.0001 }
fs16 The}{\fs16 time}{\fs16 duration}{\fs16 of}{\fs16 the}{\fs16 outpu
t}{\fs16 pulse}{\fs16 from}{\fs16 the}{\fs16 74121}{\fs17 IC}{\fs16 w
ill}{\fs16 be}{\fs16 2.1}{\b \f30 \fs16 s. }\par
}
30{\b \fs19 kR} and{\i \fs18 C}{\dn006 \f10 \fs13 = }\par
}

00 pF? \par
}
17 \cf0 9.57 \par
}
17 \cf0 9.58 \par
}
Pressing the switch SW1 shown in Fig. 9-27 activates the trigger input and ge
nerates a
\par}{\phpg\posx1451\pvpg\posy12381\absw8246\absh1181 \sl-233 \f20 \fs18 \cf0 (n
egative, positive) pulse from the complementary <Q)output.
i367 {\fs16 Pressing}{\fs16 SWl}{\fs16
in}{\fs16
Fig.}{\fs16 9-27}{\fs
16 triggers}{\fs16
the}{\fs16
74121}{\fs16 one-shot}{\fs16
and}{\fs
16
generates}{\fs15 a}{\fs16 negative}{\fs16
pulsc}{\fs16
from}{\fs
16
the }
fs16 complementary}{\i \f10 \fs24 (0) }\par
}
output.{\b \f10 \fs15 Also} see truth table in Fig. 9-28h. \par
}
. 93 \par
}
}
9 \cf0 227 \par
}
{\f20 \fs16 If}{\f20 \fs16 it}{\f20 \fs16 is}{\f20 \fs16 said}{\f20 \fs16
that}{\f20 \fs16 "the}{\f20 \fs16 flip-flop}{\f20 \fs16 is}{\f20 \fs16 set
,"}{\f20 \fs16 then}{\f20 \fs16 output}{\b\i \f30 \fs19 Q}{\f20 \fs16 is}
{\dn006 \fs9
.}{\f20 \fs16 (HIGH,}{\f20 \fs17 LOW). }
\par
}
{\phpg\posx1487\pvpg\posy2657\absw386\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 A(
n) \par
}
f0 9.59
9.60 \par
}
s17 \cf0 Ans.{\i0 \fs17
HIGH }\par
}
clocked{\fs17 RS,}{\i \fs17 RS)} flip-flop is an example of a synchronous
ly operated device. \par

}
clocked}{\b0 RS }
\cf0 \fi22 {\b0\i0 \fs16 A(n)}{\b0
(}{\b0 D}{\b0 ,}{\b0 R
S)}{\b0\i0 \fs16 flip-flop}{\b0\i0 \fs16 does}{\b0 nor}{\b0\i0 \fs16 have}
{\b0\i0 \fs16 a}{\b0\i0 \fs16 clock}{\b0\i0 \fs16 input. }
\cf0 \fi22 {\b0\i0 \fs16 Combinational}{\b0\i0 \fs16 logic}{\b0\i0 \fs16 cir
cuits}{\b0\i0 \fs16 and}{\b0\i0 \fs16 the}{\b0\i0 \fs17 RS}{\b0\i0 \fs16
latch}{\b0\i0 \fs16 operate }
0 {\b0 \fs17 Ans.}{\b0\i0 \fs16
asynchronously }\par
}
he normal output of a flip-flop is the \par
}
f0 9.61
9.62 \par
}
\f20 \fs17 \cf0 Ans.{\b0
RS }
\cf0 {\b0\i0 \f10 \fs13 .}{\b0\i0 \fs16 (asynchronously,synchronously). }\par
}
f0 9.63
9.64 \par
}
\cf0 \par}{\phpg\posx5273\pvpg\posy4668\absw1201\absh290 \sl-196 \f10 \fs11 \cf0 {\b\
i \f30 \fs19 (Q,Q)}{\f20 \fs16 output. }\par
}
17 \cf0 Ans.{\b0\i0
Q }\par
}
ist the{\i \fs17 binary} output (at{\b\i \f30 \fs19 Q)}of the{\i \fs17
RS} latch shown{\fs17 in} Fig. 9-29 for each of the eight pulses. \par
}
s17 \cf0 Ans.{\b0\i0 \fs16
pulse}{\b0\i0 \fs16 a}{\b0\i0 \f10 \fs13 =}{\
b0\i0 0 }
\fi531 {\b0\i0 \fs16 pulse}{\b0 \fs16 b}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0
\fs17 0 }\par
}
lse{\i \fs17 c}{\dn006 \f10 \fs11 =} 1
{\b\i \f10 \fs16 d}{\dn006 \f10 \fs11 =}{\fs16 0 }\par
}
ulse{\i \fs17 e}{\dn006 \f10 \fs11 =}{\b \fs17 1 }
e{\i f}{\i =} 1 (prohibited) \par

}
lse{\fs15 g}{\f10 \fs13 =}{\b 1 }
{\i \fs17 h}{\f10 \fs13 =}{\b \fs16 1 }\par
}
15 \cf0 h \par
}
fs14 \cf0 0
0 {\i \f20 \fs15 g }\par
}
cf0 0
0 {\i \f20 \fs15 f }\par
}
fs14 \cf0 0
0 {\i \f20 \fs15 e }\par
}
fs14 \cf0 1
0 {\i \f20 \fs15 d }\par
}
cf0 0
0 {\i \f20 \fs15 c }\par
}
cf0 1
0 {\i \f20 \fs15 b }\par
}
cf0 1
\b\i \f20 \fs15 a }\par
}
\cf0 Fig.{\fs16 9-29}{\b0\i \fs17
RS}{\b0 \fs16 flip-flop}{\b0 \fs16 puls
e-train}{\b0 \fs16 problem }\par
}
f0 9.65 \par
}
ist the mode of operation of the{\b\i \fs17 RS} flip-flop shown{\fs17
in} Fig. 9-29 for each of the eight pulses. \par
}
s16 \cf0 Am.{\b0\i0 \f20 \fs16
pulse}{\f20 \fs16 a}{\b0\i0\dn006 \fs11
=}{\b0\i0 \f20 \fs16 reset }
\fi531 {\b0\i0 \f20 \fs16 pulse}{\b0 \f20 \fs17 b}{\b0\i0\dn006 \fs11 =}{\b
0\i0 \f20 \fs16 hold }\par
}
ulse{\i \f10 \fs14 c}{\f10 \fs13 =} set
e{\i \f10 \fs16 d}{\f10 \fs13 =} reset \par
}
cf0 a \par
}
ulse{\i \f10 \fs14 c}{\dn006 \f10 \fs11 =}{\fs17 0 }
e{\b\i \f10 \fs15 d}{\dn006 \f10 \fs11 =}{\b \fs16 1 }\par
}
ulse{\fs16 e}{\f10 \fs13 =} set
e{\i \fs17 f}{\i \fs17 =} prohibited condition \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} set
e{\i \fs16 h}{\f10 \fs13 =} hold \par
}
f0 9.66 \par
}
ist the binary output at
es. \par
}
pulse}{\fs16 a}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17
0 }
0 \fi540 {\i0 \fs16 pulse}{\fs16 b}{\b0\i0 \f10 \fs11 =}{\b0\i0 \fs16 0 }\p
ar
}
or the clocked{\i \fs17 RS} flip-flop shown{\fs17 in} Fig. 9-7 for e
ach of the eight clock \par
}
ulse{\fs16 e}{\dn006 \f10 \fs11 =}{\b 1 }
e{\i \f10 \fs16 .f=}{\b 1 }\par
}
ulse{\fs15 g}{\f10 \fs13 =}{\fs17 0 }
e{\b\i \fs17 h}{\f10 \fs13 =}{\fs17 0 }\par
}
cf0 9.67 \par
}
Refer to Fig. 9-30. The clocked{\fs17 RS} flip-flop is triggered by t
he
ck pulse.{\b\i \fs17
Ans.}
leading \par
}
(leading, trailing) edge{\fs17 of} the \par
}
\cf0 0 \par
}
\cf0 0 \par
}
\cf0 0 \par
}
\cf0 0 \par
}
\cf0 Fig.{\fs16 9-30}{\b0 \fs16
Clocked}{\i \fs17 RS}{\b0 \fs16 flip-fl
op}{\b0 \fs16 pulse-train}{\b0 \fs16 problem }\par
}
\par
}
}
AP. 9 \par
}
f0 9.68 \par
}
ist the{\i \fs17 binary} output (at{\i Q}{\i )} of the clocked{\i \fs1
7
RS} flip-flop shown in Fig. 9-30 for each of the six clock
es. \par
}
\cf0 Ans.{\i0 \fs16
pulse}{\fs17 a}{\i0\dn006 \f10 \fs11 =}{\i0 \fs16
1 }
fi531 {\i0 \fs16 pulse} b{\i0\dn006 \f10 \fs11 =}{\i0 \fs16 0 }\par
}
lse{\i c}{\f10 \fs11 =}{\fs17 0 }
d{\f10 \fs13 =} 1 \par
}
ulse{\i e}{\f10 \fs11 =} 1 (prohibited condition)
e{\i \f10 \fs16 ,f}{\fs17
1 }\par
}
\par
}
f0 9.69 \par
}
ist the mode{\fs16 of} operation for the clocked{\i \fs17 RS} flip-flop s
hown in Fig. 9-30 as each pulse triggers the unit. \par
}
\cf0 Ans.{\i0 \fs16
pulse}{\fs17 a}{\i0 \f10 \fs11 =}{\i0 \fs16 set }
fi536 {\i0 \fs16 pulse}{\fs16 h}{\i0 \f10 \fs11 =}{\i0 \fs16 reset }\par
}
lse{\i \fs17 c }\par
}
ulse d{\f10 \fs13 =} set
e{\i \fs17 e}{\f10 \fs13 =} prohibited condition \par
}
{\f20 \fs16 hold}{\i \f20 \fs16 (}{\i \f20 \fs16 S}{\f20 \fs16 and}{\i \f2
0 \fs17 R}{\f20 \fs16 are}{\f20 \fs16 both}{\f20 \fs17 0}{\f20 \fs16
pulse}{\i \fs16 f}{\dn006 =}{\f20 \fs16 set}{\i \f20 \fs17 (}{\i \f20 \
fs17 S}{\dn006 = }\par
}
n leading edge) \par
}
{\phpg\posx6431\pvpg\posy3089\absw339\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 I,
{\i R }\par
}
\b\i \f20 \fs17 0}{\f20 \fs16 on}{\f20 \fs16 the }\par
}
eading edge) \par
}
f0 9.70 \par
}
ist the{\i \fs17 binary} output (at{\i Q}{\i )} for the{\i \fs17 0}
flip-flop shown{\fs16 in} Fig.{\f10 \fs15 9-1}{\b \f10 \fs15 1} after eac
h{\f10 \fs15 of} the eight clock pulses. \par
}
\cf0 Ans.{\i0 \fs16
pulse}{\i0 \fs16 a}{\i0 \f10 \fs13 =}{\i0 \fs16 1 }
fi535 {\i0 \fs16 pulse} b{\i0 \f10 \fs13 =}{\i0 \fs17 0 }\par
}
lse{\fs17 c}{\dn006 \f10 \fs11 =}{\fs17 1 }
{\i \f10 d}{\f10 \fs13 =}{\fs16 0 }\par
}
lse e{\f10 \fs11 =}{\fs17 1 }

{\fs17 f}{\f10 \fs13 =}{\b\i \fs17 0 }\par
}
ulsc{\fs15 g}{\f10 \fs11 =} 1
c{\i \f10 \fs15 h}{\dn006 \f10 \fs10 =} 1 (prohibited condition) \par
}
f0 9.71 \par
}
f0 9.72 \par
}
\cf0 Refer to Fig. 9-11. Which input has control of the flip-flop durin
g pulse{\fs17 e? }
\i \fs17 Ans.}
The preset{\i \fs17 (}{\i \fs17 P}{\i \fs17 S}{\i \fs17
)} input is activated during pulse e and overrides all other inputs.
It sets the{\i
Q }
25 output to{\fs17 1. }
\fi28 Refer to Fig. 9-11. Which input has control{\fs17 of} the flip-f
lop during pulse{\i \f10 \fs16 f}{\i \f10 \fs16 ? }
\fs17 Ans.}
The clear (CLR) input is activated during pulsc{\fs17 f
} and overrides all other inputs. It resets thc{\i \fs16 Q }
25 output{\fs16 to}{\i \fs17 0. }
\fi34 {\b \fs17 A} delay flip-flop is also called a{\i \fs16
(}{\i \fs16 D}{\i \fs16 ,} T)-type flip-flop.{\b\i \f10 \fs15
Am.
}{\i \fs17
D }
\fi35 {\fs17 On} a{\b\i \f30 \fs19 D} flip-flop, the data bit at input{\
b\i \f30 \fs19 D} is delayed{\fs16
(0,}{\fs16 I}{\fs16
,} 2,{\fs16 3,}{\f10 \fs15 4)} clock pulse(s) from getting to \par
}
utput{\i \fs17
(Q, }\par
}
{\phpg\posx3065\pvpg\posy6722\absw548\absh432 \f20 \fs38 \cf0 \f20 \fs38 \cf0 e)
. \par
}
cf0 Ans.{\i0 \fs17
I}{\i0 \fs17 ;}{\f10 \fs16 Q }\par
}
\cf0 A{\b0 \fs16 T-type}{\b0 \fs16 flip-flop}{\b0 \fs16 is}{\b0 \fs16 als
o}{\b0 \fs16 called}{\b0 \fs16 a }\par
}
toggle. truth-table) flip-flop. \par
}
s15 \cf0 Am.{\b0\i0 \f20 \fs16
toggle }
\cf0 \fi187 {\f20 \fs16 Ans.}{\b0\i0 \f20 \fs16
See}{\b0\i0 \f20 \fs16 Fig
.}{\b0\i0 \f20 \fs16 9-14h. }\par

}
f0 9.73
9.74 \par
}
f0 9.75
9.76
9.77 \par
}
raw a logic diagram showing how to wire a{\i \fs17 JK} flip-flop as a{
\i \fs17 T} flip-flop. \par
}
f0 9.78 \par
}
\cf0 Draw a logic diagram showing how to wire a{\i \fs17 JK} flip-flop
and an inverter as a{\i \fs17 D} flip-flop.
\fs17 Ans.}
See Fig.{\i \fs17 9-14a. }
\fi44 List the{\i \fs17 binary} output (at{\fs17 Q)} fo the{\i \fs17 J
K} flip-flop shown{\fs17 in} Fig.{\fs15 9-16} after each{\fs16 of} th
e eight clock pulses. \par
}
\cf0 Ans.{\i0 \fs16
pulse}{\fs18 a}{\i0 \f10 \fs13 =}{\i0 \fs16 0 }
fi536 {\i0 \fs16 pulse}{\fs17 b}{\i0 \f10 \fs13 =}{\i0 \fs16 0 }\par
}
lse{\i c}{\f10 \fs11 =}{\fs17 0 }
d{\f10 \fs11 =}{\fs17 1 }\par
}
lsc{\b\i \fs17 r}{\dn006 \f10 \fs11 =}{\b 1 }
\par}{\phpg\posx4451\pvpg\posy9027\absw874\absh390 \sl-222 \f20 \fs16 \cf0 pulsc
{\fs17 f}{\dn006 \f10 \fs10 =}{\fs16 0 }\par
}
lse{\i \f10 \fs13 g}{\f10 \fs11 =}{\fs17 1 }
{\b\i \fs17 h}{\f10 \fs13 =}{\fs16 0 }\par
}
f0 9.79 \par
}
efer to Fig. 9-16. The
on this unit. \par
}
asynchronous, synchronous) inputs to the{\i \fs17 JK} flip-flop are show

n being \par
}
cf0 9.80 \par
}
7 \cf0 Am.{\i0 \fs16
The}{\b \fs16 J}{\b \fs16 ,}{\b \fs16 K}{\b \fs16
,}{\i0 \fs16 and}{\i0 \fs16 CLK}{\i0 \fs16 inputs}{\i0 \fs16 are}{\i0 \
fs16 synchronous}{\i0 \fs16 inputs. }
\par}{\phpg\posx1423\pvpg\posy10095\absw8268\absh1723 \sl-212 \par\i \f20 \fs17
\cf0 \fi31 {\i0 \fs16 Refer}{\i0 \fs16 to}{\i0 \fs16 Fig.}{\i0 \fs16 9-17.}
{\i0 \fs16 Which}{\i0 \fs16 input}{\i0 \fs16 has}{\i0 \fs16 control}{\i0
\fs16 of}{\i0 \fs16 the}{\fs17 JK}{\i0 \fs16 flip-flop}{\i0 \fs16 durin
g}{\i0 \fs16 pulse}{\b \f30 \fs13 U? }
{\b \f10 \fs15 Ans.}
PR{\i0 \fs16 (Preset}{\i0 \fs16 input}{\i0 \fs16
activated}{\i0 \fs16 with}{\i0 \fs16 LOW}{\i0 \fs16 sets}{\i0 \fs16 outp
ut}{\i0 \fs16 Q}{\i0 \fs16 to}{\b\i0 \fs16 1.) }
\par}{\phpg\posx1423\pvpg\posy10095\absw8268\absh1723 \sl-204 \par\i \f20 \fs17
\cf0 \fi44 {\i0 \fs16 Refer}{\i0 \fs16 to}{\i0 \fs16 Fig.}{\i0 \fs16 9-17.}
{\i0 \fs16 Which}{\i0 \fs16 input}{\i0 \fs16 has}{\i0 \fs16 control}{\i0
\fs16 of}{\i0 \fs16 the}{\fs17 JK}{\i0 \fs16
flip-flop}{\i0 \fs16 duri
ng}{\i0 \fs16 pulse}{\fs16 d? }
Ans.{\i0 \fs16
CLR}{\i0 \fs16 (Clear}{\i0 \fs16 input}{\i0 \fs16 acti
vated}{\i0 \fs16 with}{\i0 \fs16 LOW}{\i0 \fs16 resets}{\i0 \fs16 output}
{\fs16 Q}{\i0 \fs16 to}{\i0 \fs16 0.) }
\fi40 {\i0 \fs16 Refer}{\i0 \fs16 to}{\i0 \fs16 Fig.}{\i0 \fs16 9-17.}{\i0
\fs16 List}{\i0 \fs16 the} binary{\i0 \fs16 output}{\i0 \fs16 at}{\f10
\fs24 0}{\i0 \fs16 (complementary}{\i0 \fs16 output)}{\i0 \fs16 of}{\i0 \fs
16 the}{\fs16 JK}{\i0 \fs16 flip-flop}{\fs16 afrer}{\i0 \fs16 each}{\b\
i0 \fs16 of }\par
}
6 \cf0 the seven clock pulses.
i \fs17 Ans.}
pulse{\fs15 a}{\dn006 \f10 \fs11 =}{\fs16 0 }
i537 pulse{\i \fs16 b}{\dn006 \f10 \fs11 =}{\b 1 }
i534 pulse{\i \fs17 c}{\dn006 \f10 \fs11 =}{\fs17 0 }
i534 pulse d{\f10 \fs11 =}{\fs17 1 }
i534 pulse{\fs15 e}{\f10 \fs13 =}{\fs16 0 }
i534 pulse{\i \f30 \fs19 f=}{\fs16 0 }\par
}
ulse{\fs15 g }\par
}
{\phpg\posx2593\pvpg\posy13609\absw133\absh77 \f10 \fs5 \cf0 \f10 \fs5 \cf0 ;= \
par
}
\par
}
cf0 9.81 \par

}
cf0 9.82 \par
}
.{\i \f10 \fs15 91 }\par
}
IP-FLOPS{\b AND} OTHER MULTIVIBRATORS \par
}
\par
}
f0 9.83 \par
}
\cf0 A{\b0 \f20 \fs16 negative-edge-triggered}{\b0 \f20 \fs16 flip-flop}{\b0
\f20 \fs16 transfers}{\b0 \f20 \fs16 data}{\b0 \f20 \fs16 from}{\b0 \f20 \fs
16 input}{\b0 \f20 \fs16 to}{\b0 \f20 \fs16 outputs}{\b0 \f20 \fs16 on}{\b0
\f20 \fs16 the }
\b0 \f20 \fs16 edge}{\b0 \f20 \fs16 of}{\b0 \f20 \fs16 the}{\b0 \f20 \fs16
clock}{\b0 \f20 \fs16 pulse.}{\i \fs14
Ans.}{\b0 \f20 \fs16
trai
ling }
f0 A{\b0 \f20 \fs16 positive-edge-triggered}{\b0 \f20 \fs16 flip-flop}{\b0 \
f20 \fs16 transfers}{\b0 \f20 \fs16 data}{\b0 \f20 \fs16 from}{\b0 \f20 \fs
16 input}{\b0 \f20 \fs16 to}{\b0 \f20 \fs16 outputs}{\b0 \f20 \fs16 on}{\b
0 \f20 \fs16 the }
\b0 \f20 \fs16 transition}{\b0 \f20 \fs16 of}{\b0 \f20 \fs16 the}{\b0 \f20 \
fs16 clock}{\b0 \f20 \fs16 pulse.}{\i \f20 \fs16
Ans.}{\b0 \f20 \fs1
6
L-to-H }\par
}
leading, trailing) \par
}
f0 9.84 \par
}
H-to-L, L-to-H) \par
}
f0 9.85 \par
}
efer to Fig. 9-21. List the{\i binary} output (at{\fs16 Q)} of the ma
ster-slave{\i \fs17 JK} flip-flop{\b\i \fs16 after} each of the eight
\par}{\phpg\posx1449\pvpg\posy2685\absw8219\absh385 \sl-215 \f20 \fs16 \cf0 cloc
k pulses. \par
}
s17 \cf0 Ans.{\b0\i0 \fs16
pulse}{\b0\i0 \fs16 a}{\b0\i0\dn006 \f10 \fs11
=}{\b0\i0 \fs16 0 }
\fi526 {\b0\i0 \fs16 pulse}{\b0 \fs16 b}{\b0\i0\dn006 \f10 \fs11 =}{\b0\i0

\fs16 1 }\par
}
lse{\b \f10 \fs13 c}{\dn006 \f10 \fs11 =}{\fs16 0 }
{\i \f10 \fs15 d}{\dn006 \f10 \fs11 =}{\b \f10 \fs15 1 }\par
}
lse{\fs16 e}{\dn006 \f10 \fs11 =} 1
{\i \f10 \fs15 f}{\i \f10 \fs15 =}{\fs17 0 }\par
}
lse{\fs14 g}{\dn006 \f10 \fs11 =}{\f10 \fs15 'I }
{\i \fs17 h}{\dn006 \f10 \fs11 =}{\fs17 0 }\par
}
f0 9.86 \par
}
efer to Fig. 9-21. List the mode of operation of the{\i \fs17 negatic
e-ed~e-tri~~ered} flip-flop for each of the
}{\phpg\posx1443\pvpg\posy3773\absw8222\absh388 \f20 \fs16 \cf0 \fi7 {\i \fs17 J
K }
k pulses. \par
}
s15 \cf0 Am.{\b0\i0 \f20 \fs16
pulse}{\b0 \fs14 a}{\b0\i0\dn006 \fs11 =
}{\b0\i0 \f20 \fs16 set }
\fi531 {\b0\i0 \f20 \fs16 pulse}{\b0 \f20 \fs16 b}{\b0\i0\dn006 \fs11 =}{\b
0\i0 \f20 \fs16 reset }\par
}
ulse{\f10 \fs14 c}{\dn006 \f10 \fs11 =} toggle
e{\i \f10 \fs15 d}{\dn006 \f10 \fs11 =} toggle \par
}
6 \cf0 pulse{\i \fs17 e}{\dn006 \f10 \fs11 =} hold
132 pulse{\i \f30 \fs19 f}{\dn006 \f10 \fs11 =} hold{\b\i \fs17 (}{\b\i \fs1
7 J} and{\b\i \fs17 K}{\dn006 \f10 \fs11
=}{\fs16 0 }
1304 during H-to-L
1302 pulse)
mu1tivibrator.{\b\i \f10 \fs15
Ans.}
bistable \par
}
ulse{\fs15 g}{\f10 \fs13 =} reset
e{\i \fs16 h}{\dn006 \f10 \fs11 =} toggle \par
}
cf0 9.87

0 9.88
0 9.89
0 9.90
0 9.91 \par
}
\cf0 A{\b0 \f20 \fs16 flip-flop}{\b0 \f20 \fs16 is}{\b0 \f20 \fs17 also}{\b
0 \f20 \fs16 referred}{\b0 \f20 \fs16 to}{\b0 \f20 \fs16 as}{\b0 \f20 \fs16
a(n) }\par
}
\cf0 A{\b0 \f20 \fs16 free-running}{\b0 \f20 \fs16 clock}{\b0 \f20 \fs16 is
}{\b0 \f20 \fs16 also}{\b0 \f20 \fs16 referred}{\b0 \f20 \fs16 to}{\b0 \f20
\fs16 as}{\b0 \f20 \fs16 a(n) }\par
}
ne-shots are also called{\f10 \fs19
. }\par
}
ultivibrator. \par
}
15 \cf0 Ans. \par
}
{\phpg\posx7851\pvpg\posy5745\absw535\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 as
table \par
}
s16 \cf0 Ans.{\b0\i0 \fs16
monostable}{\b0\i0 \fs16 multivibrators }\par
}
he main advantage of a crystal-controlled clock is its \par
}
{\phpg\posx6453\pvpg\posy6617\absw645\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 st
ability. \par
}
15 \cf0 Ans. \par
}
{\phpg\posx8011\pvpg\posy6617\absw767\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 fr
equency \par
}
\cf0 If{\fs16 a}{\fs16 free-running}{\fs16 MV}{\fs16 has}{\fs16 a}{\fs
16 clock}{\fs16 cycle}{\fs16 time} of{\fs16 0.000001}{\fs16 s,}{\fs16
the}{\fs16 frequency}{\fs17 of}{\fs16 the}{\fs16 clock}{\fs16 is }
\fs16 Rns.}{\fs16
1}{\fs16 MHz }
\fi21 {\fs16 The}{\fs16 output}{\fs16 of}{\fs16 the}{\fs16 astable}{\fs1
6 MV}{\fs16 shown}{\fs16 in}{\fs16 Fig.}{\fs16 9-25}{\fs16
(is,}{\fs16 is}{\fs16 not)}{\fs16 TTL-compatible. }
i \fs16 Ans.}{\fs16
is}{\fs16 not}{\fs16 (voltage} is{\fs16 too}{\fs16
high.) }\par
}

par
}
f0 9.92 \par
}
apter{\fs52 10 }\par
}
0 \fs33 \cf0 Counters
f0 {\f20 \fs18 10-1}{\f20 \fs19
INTRODUCTION }
fi365 {\b0 \f20 \fs19 Counters}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 important}{
\b0 \f20 \fs19 digital}{\b0 \f20 \fs19 electronic}{\b0 \f20 \fs19 circuits.}{
\b0 \f20 \fs19 They}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 sequential}{\b0 \f20
\fs19 logic}{\b0 \f20 \fs19 circuits}{\b0 \f20 \fs19 because}{\b0\i \f20 \fs1
8 timing }
\b0 \f20 \fs19 is}{\b0 \f20 \fs19 obviously}{\b0 \f20 \fs19 important}{\b0 \f
20 \fs19 and}{\b0 \f20 \fs19 because}{\b0 \f20 \fs19 they}{\b0 \f20 \fs19
need}{\b0 \f20 \fs19 a}{\b0\i \f20 \fs18 memory}{\b0 \f20 \fs19 characte
ristic.}{\b0\i \f20 \fs18 Digital}{\b0\i \f20 \fs18 counters}{\b0 \f20 \fs19
have}{\b0 \f20 \fs19 the }
\b0 \f20 \fs19 following}{\b0 \f20 \fs19 important}{\b0 \f20 \fs19 characteris
tics: }
fi377 {\b0 \f20 \fs18 1.}{\b0 \f20 \fs19
Maximum}{\b0 \f20 \fs19 number}{\b0
\f20 \fs19 of}{\b0 \f20 \fs19 counts}{\b0 \f20 \fs19 (modulus}{\b0 \f20 \fs
19 of}{\b0 \f20 \fs19 counter) }
fi364 {\f20 \fs19 2.}{\b0 \f20 \fs19
Up}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19
down}{\b0 \f20 \fs19 count }
fi364 {\b0 \f20 \fs18 3.}{\b0 \f20 \fs19
Asynchronous}{\b0 \f20 \fs19 or}{\
b0 \f20 \fs19 synchronous}{\b0 \f20 \fs19 operation }
fi365 {\b0 \fs18 4.}{\b0 \f20 \fs19
Free-running}{\b0 \f20 \fs19 or}{\b0 \f
20 \fs19 self-stopping }
\f20 \fs19 As}{\b0 \f20 \fs19 with}{\b0 \f20 \fs19 other}{\b0 \f20 \fs19 seq
uential}{\b0 \f20 \fs19 circuits,}{\b0 \f20 \fs19 flip-flops}{\b0 \f20 \fs19
are}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 construct}{\b0 \
f20 \fs19 counters. }
fi371 {\b0 \f20 \fs19 Counters}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 extremely}{
\b0 \f20 \fs19 useful}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 digital}{\b0 \f20 \
fs19 systems.}{\b0 \f20 \fs19 Counters}{\b0 \f20 \fs19 can}{\b0 \f20 \fs19 b
e}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 count}{\b0 \f20 \f
s19 events}{\b0 \f20 \fs19 such}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 a }
\b0 \f20 \fs19 number}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 clock}{\b0 \f20 \fs1
9 pulses}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 given}{\b0 \f2
0 \fs19 time}{\b0 \f20 \fs19 (measuring}{\b0 \f20 \fs19 frequency).}{\b0 \f20
\fs19 They}{\b0 \f20 \fs19 can}{\b0 \f20 \fs19 be}{\b0 \f20 \fs19 used}{\
b0 \f20 \fs19 to}{\b0 \f20 \fs19 divide}{\b0 \f20 \fs19 frequency }

\b0 \f20 \fs19 and}{\b0 \f20 \fs19 store}{\b0 \f20 \fs19 data}{\b0 \f20 \fs19
as}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 digital}{\b0 \f20 \f
s19 clock,}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 they}{\b0 \f20 \fs19 can}{\b
0 \f20 \fs19 also}{\b0 \f20 \fs19 be}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19
in}{\b0 \f20 \fs19 sequential}{\b0 \f20 \fs19 addressing}{\b0 \f20 \fs19 and
}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 some }
\b0 \f20 \fs19 arithmetic}{\b0 \f20 \fs19 circuits. }
f0 {\f20 \fs18 10-2}{\f20 \fs19
RIPPLE}{\f20 \fs19 COUNTERS }
fi371 {\b0 \f20 \fs19 Digital}{\b0 \f20 \fs19 counters}{\b0 \f20 \fs19 will}
{\b0 \f20 \fs19 count}{\b0 \f20 \fs19 only}{\b0 \f20 \fs19 in}{\b0 \f20 \f
s19 binary}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 binary}
{\b0 \f20 \fs19 codes.}{\b0 \f20 \fs19 Figure}{\b0 \f20 \fs19 10-1}{\b0 \f
20 \fs19 shows}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 counting }
\b0 \f20 \fs19 sequence}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 binary}{\b0 \f20 \f
s19 from}{\b0 \f20 \fs19 0000}{\b0 \f20 \fs19 to}{\b0 \f20 \fs18 1111}{\b0
\f20 \fs19 (0}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 15}{\b0 \f20 \fs19 in}{\b0
\f20 \fs19 decimal).}{\f20 \fs19 A}{\b0 \f20 \fs19 digital}{\b0 \f20 \fs19
counter}{\b0 \f20 \fs19 that}{\b0 \f20 \fs19 would}{\b0 \f20 \fs19 count}{
\b0 \f20 \fs19 from }
\b0 \f20 \fs19 binary}{\b0 \f20 \fs19 0000}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19
1111}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 shown}{\b0 \f20 \fs19 in}{\b0 \f2
0 \fs19 the}{\b0 \f20 \fs19 table}{\b0 \f20 \fs19 might}{\b0 \f20 \fs19
be}{\b0 \f20 \fs19 called}{\b0 \f20 \fs19 a}{\b0\i \f20 \fs18 modulo-16}{\
b0\i \f20 \fs18 counter.}{\b0 \f20 \fs19 The}{\b0\i \f20 \fs18 modulus}{\b0
\f20 \fs18 of}{\b0 \f20 \fs19 a }
\b0 \f20 \fs19 counter}{\b0 \f20 \fs19
is}{\b0 \f20 \fs19 the}{\b0 \f20 \fs
19 number}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 counts}{\b0 \f20 \fs19 the}
{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 goes}{\b0 \f20 \fs19 through.}{\b0
\f20 \fs19 The}{\b0 \f20 \fs19 term}{\b0 \f20 \fs19 "modulo"}{\b0 \f20 \f
s19
is}{\b0 \f20 \fs19 sometimes }
\b0 \f20 \fs19 shortened}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 "mod."}{\b0 \f20
\fs19 This}{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 might}{\b0 \f20 \fs19 thu
s}{\b0 \f20 \fs19 be}{\b0 \f20 \fs19 called}{\b0 \f20 \fs19 a}{\b0\i \f20 \f
s18 mod-I6}{\b0\i \f20 \fs18 counter. }\par
}
ecimal
5 count
\fi310 {\b \f10 \fs16 0 }
36 {\b \f10 \fs15 1 }
18 {\b \f10 \fs16 2 }
24 {\b \f10 \fs16 3 }
18 {\b \f10 \fs15 4 }
24 {\b \f10 \fs16 5 }
24 {\b \f10 \fs16 6 }\par

}
par
}
inary count
33 {\b \f10 \fs16 8s}{\b \f10 \fs16 4s}{\b \f10 \fs16 2s}{\b \f10 \fs15 1s }
20 {\fs17 D}{\fs17 C}{\fs17 B}{\fs17 A }\par
}
\cf0 0
\fs15 0 }
\fs16 0 }
\fs16 0 }
\fs15 0 }
\fs15 0 }
\fs15 0 }\par
}
\cf0 0
\fs15 0 }
\fs16 0 }
\fs16 0 }
\fs15 1 }
\fs15 1 }
\fs15 1 }\par
}
\cf0 0
\fs15 0 }
fi28 {\fs15 1 }
fi28 {\fs15 1 }
\fs15 0 }
\fs15 0 }
\fs15 1 }\par
}
\cf0 0
\fs15 1 }
\fs15 0 }
fi27 {\fs15 1 }
\fs15 0 }
\fs15 1 }
\fs15 0 }\par
}
ecimal
6 count
\fi316 {\b \f10 \fs16 8 }
13 {\b \f10 \fs16 9 }
44 {\b \f10 \fs15 10 }
43 {\b \f10 \fs15 11 }
43 {\b \f10 \fs16 12 }
47 {\b \f10 \fs16 13 }
43 {\b \f10 \fs15 14 }\par
}
inary count
28 {\b \f10 \fs15 8s}{\b \f10 \fs14 4s}{\b \f10 \fs16 2s}{\b \f10 \fs15 1s }
\fi120 D C B A \par
}
\cf0 1
\fs15 1 }
\fs15 1 }
\fs15 1 }
\fs15 1 }
\fs15 1 }
\fs15 1 }\par
}
\cf0 0
\fs15 0 }
\fs15 0 }
\fs15 0 }
\fs15 1 }
\fs15 1 }
\fs15 1 }\par
}
\cf0 0
\fs15 0 }
\fs15 1 }
\fs15 1 }
\fs15 0 }
\fs15 0 }
\fs15 1 }\par
}
\cf0 0
\fs15 1 }
\fs15 0 }
\fs15 1 }
\fs15 0 }
\fs15 1 }
\fs15 0 }\par
}
16 \cf0 Fig.{\b \f10 \fs15 10-1}{\fs17 Counting}{\fs17 sequence}{\fs16 for
}{\fs17 a}{\fs17 4-bit}{\fs17 counter }
\fi356 {\fs19 A}{\fs19 logic}{\fs19 diagram}{\fs18 of}{\fs19 a}{\fs19 mod16}{\fs19 counter}{\fs19 using}{\b\i \fs19 JK}{\fs19 flip-flops}{\fs19 is}
{\fs19 shown}{\fs19 in}{\fs19 Fig.}{\fs18 10-2.}{\fs19 First}{\fs19 note}{\
fs19 that}{\fs19 the}{\i \fs18 J }
s19 and}{\b\i \fs19 K}{\fs19 data}{\fs19 inputs}{\fs19 of}{\fs19 the}{\fs
19 flip-flops}{\fs19 are}{\fs19 tied}{\fs19 to}{\fs19 logical}{\fs18 1.}{\
fs19 This}{\fs19 means}{\fs19 that}{\fs19 each}{\fs19 flip-flop}{\fs19 is
}{\fs19 in}{\fs19 its}{\fs19 toggle }
s19 mode.}{\fs19 Each}{\fs19 clock}{\fs19 pulse}{\fs19 will}{\fs19 then}{\
fs19 cause}{\fs19 the}{\fs19 flip-flop}{\fs19 to}{\fs19 toggle}{\fs19 to}{
\fs19 its}{\fs19 opposite}{\fs19 state.}{\fs19 Note}{\fs19 also}{\fs19 th
at}{\fs19 the }
\i \fs18 Q}{\fs19 output}{\b \fs18 of}{\fs18 FF1}{\fs19 (flip-flop}{\fs18 1
)}{\fs19 is}{\fs19 connected}{\fs19 directly}{\fs19 to}{\fs19 the}{\fs19 c
lock}{\b \fs18 (CLK)}{\fs19 input}{\fs19 to}{\fs19 the}{\fs19 next}{\fs19
unit}{\fs18 (FF2),}{\fs19 and }

s19 so}{\fs19 forth.}{\fs19 Output}{\fs19 indicators}{\fs19 (lamps}{\fs19 o
r}{\fs18 LEDs),}{\fs19 shown}{\fs19 at}{\fs19 the}{\fs19 upper}{\fs19 righ
t,}{\fs19 monitor}{\fs19 the}{\fs19 binary}{\fs19 output}{\fs18 of }
s19 the}{\fs19 counter.}{\fs19 Indicator}{\b\i \f10 \fs17 A}{\fs19 is}{\fs1
9 the}{\b \fs18 LSB}{\fs19 (least}{\fs19 significant}{\fs19 bit),}{\b\i \f3
0 \fs21 D}{\fs18 is}{\fs19 the}{\b \fs18 MSB. }
4272 {\fs19 230 }\par
}
}
{\phpg\posx9017\pvpg\posy1641\absw86\absh108 \f10 \fs8 \cf0 \f10 \fs8 \cf0 7 \pa
r
}
par
}
\par}{\phpg\posx9424\pvpg\posy1641\absw86\absh292 \sl-224 \f10 \fs8 \cf0 \fi39 {
\fs5 I }\par
}
par
}
}
{\phpg\posx4791\pvpg\posy1610\absw36\absh132 \f10 \fs11 \cf0 \f10 \fs11 \cf0 f \
par
}
1 }\par
}
t \par
}
\par
}
cf0 COUNTERS \par
}
f0 [CHAP.{\b0 \fs17 10 }\par
}
\cf0 Look at the dashed line after pulse{\fs18 4} to the HIGH waveform at{\i
Q} of FF3. Note that quite a lot of
\fs19 time} passes before FF3 finally toggles to its HIGH state. That is beca
use FF1 toggles, which in turn
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-252 \f20 \fs18 \cf0 togg
les FF2, which in turn toggles FF3. All that takes time. This type of
counter{\fs18 is} called a{\i \fs19 ripple }
\fs19 counter.} The triggering from flip-flop to flip-flop in effect ripples thr
ough the counter. The counter is
19 also} referred to as an{\i \fs19 asynchronous}{\i \fs19 counter} becaus
e not all flip-flops toggle exactly in step with the
k pulse.
60 Look at the remainder of the waveform shown in Fig. 10-3 to make
sure you understand its
ation. Note particularly that, on pulse 16, the H-to-L transition toggles FF
1. The output of FF1
from HIGH to{\fs19 LOW.} FF2 is toggled by FF1. The output of FF2 goes from HI
GH to LOW. FF3
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-236 \f20 \fs18 \cf0 is t
oggled by FF2, and{\fs19 so} forth. Note that all the flip-flops toggle in turn
and{\fs17 go} from their HIGH to
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-237 \f20 \fs18 \cf0 thei
r{\fs19 LOW} states. The binary count is then back to{\fs18 0000.} The counte
r does not stop at its maximum
t; it continues counting as long as the clock pulses are fed into the CLK input{
\fs18 of} FF1.
70 Count carefully the- number of HIGH pulses under the first 16 clock pu
lses (in the FF1 output
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-237 \f20 \fs18 \cf0 line
, Fig. 10-3).You will find eight pulses. Sixteen pulses go into FF1, and only ei
ght pulses come out.
flip-flop is therefore a{\i \fs19 frequency}{\i \fs19 divider.} 16 di
vided by{\fs18 8} equals 2. FF1 may thus also be
idered a{\i \fs19 divide-by-2}{\i \fs19 counter. }
68 Count the{\fs19 HIGH} output pulses at FF2. For 16 clock pulses, only four
pulses appear at the output
19 of}{\b \fs19 FF2} (16 divided by{\fs18 4} equals{\fs18 4).} Output{\i \
fs18 Q} of FF2 may be considered a{\i \fs19 divide-by-4}{\i \fs19 count
er.} It is
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-234 \f20 \fs18 \cf0 foun
d that the output of FF3 is a divide-by-8 counter. The output of FF4 is a divide
-by-16counter. On
\par}{\phpg\posx831\pvpg\posy1348\absw9248\absh5645 \sl-241 \f20 \fs18 \cf0 some
devices, such as digital clocks, dividing frequency is a very important job for
counters.
74 The waveform confirms that a counter is a sequential logic device. The memory
characteristic also
2 is important; for the flip-flop must "remember" how many clock pulses have arr
ived at the{\fs19 CLK} input.
ripple counter is the simplest type{\fs18 of} counter. Its shortcoming
is the{\i \fs19 time}{\i \fs19 Zag} as one flip-flop

2 triggers the next, and{\fs19 so} forth.
{\b \f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }\par
}
cf0 10.1{\fs18 A}{\b0 \fs18 ripple}{\b0 \fs18 counter}{\b0 \fs18 is}{\b0 \
fs18 a(n) }
}
asynchronous, synchronous) device. \par
}
\cf0 The ripple counter is an asynchronous device because not all flip-flops
trigger exactly in step with the
k pulse. \par
}
cf0 10.2{\fs19 A}{\b0 \fs18 counter}{\b0 \fs18 that}{\b0 \fs18 counts}{\b0
\fs18 from}{\b0 0}{\b0 \fs18 to}{\b0 \fs19 7}{\b0 \fs18 is}{\b0 \fs18 cal
led}{\b0 \fs18 a}{\b0 \fs18 mod- }
i848 {\fs17 A}{\b0 \fs17 counter}{\b0 \fs17 that}{\b0 \fs17 counts}{\b0 \fs
17 from}{\b0 \fs17 0}{\b0 \fs17 to}{\b0 \fs17 7}{\fs17 is}{\b0 \fs17 ca
lled}{\b0 \fs17 a}{\b0 \fs17 mod-8}{\b0 \fs17 counter. }\par
}
unter. \par
}
\cf0 10.3{\b0 \fs18 Draw}{\b0 \fs18 a}{\b0 \fs18 logic}{\b0 \fs18 diagram}{
\b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 mod-8}{\b0 \fs18 ripple}{\b0 \fs18 cou
nter}{\b0 \fs18 using}{\b0 \fs18 three}{\i \fs19 JK}{\b0 \fs18 flip-flops.
}
fi856 {\b0 \fs17 See}{\fs17 Fig.}{\fs16 10-4. }\par
}
1 \par
}
- \par
}
s14 \cf0 J \par
}
s19 \cf0 Q , \par
}
4 1 \par
}

- \par
}
14 \cf0 J \par
}
s19 \cf0 Q - \par
}
41 \par
}
\cf0 1- \par
}
cf0 J \par
}
lock
6 {\fs14 input }\par
}
\fs15 \cf0 FF{\f30 \fs15 1 }
\f30 \fs16 CLK }\par
}
s14 \cf0 1 - K \par
}
\cf0 c \par
}
>
\fi133 {\b \f20 \fs14 1}{\b \f20 \fs14 -}{\b \f20 \fs14 K }\par
}
\fs15 \cf0 FF2
\f30 \fs16 CLK }\par
}
\cf0 FF3 \par
}
utput \par
}
{\phpg\posx2711\pvpg\posy12910\absw620\absh113 \f10 \fs9 \cf0 \f10 \fs9 \cf0 ----O> \par
}
\f30 \fs12 \cf0 01{\i0 \fs16 CLK }
\cf0 {\f20 \fs15 I}{\f20 \fs15 -}{\f20 \fs15 K }\par
}
\cf0 Fig.{\fs17 10-4} A{\b0 \fs17 3-bit}{\b0 \fs17 ripple}{\b0 \fs17 coun
ter }\par
}
.{\fs17 101 }\par
}
UNTERS \par
}
\par
}
cf0 10.4{\b0 \f20 \fs19
List}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 sequence}{
\b0 \f20 \fs19 of}{\b0 \f20 \fs19 binary}{\b0 \f20 \fs19 counts}{\b0 \f20 \fs
19 that}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 in}{\b0
\f20 \fs19 Prob.}{\b0 \f20 \fs19 10-3would}{\b0 \f20 \fs19 go}{\b0 \f20 \fs1
9 through. }
i849 {\b0 \f20 \fs17 The}{\b0 \f20 \fs17 mod-8}{\b0 \f20 \fs17 counter}{\b0
\f20 \fs17 would}{\b0 \f20 \fs17 count}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17
binary}{\b0 \f20 \fs17 as}{\b0 \f20 \fs17 follows:}{\b0 \f20 \fs17 000,00
1,010,011,100,101,110,111,}{\b0 \f20 \fs17
and}{\b0 \f20 \fs17 then }
i490 {\b0 \f20 \fs17 back}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 000,}{\b0 \f20 \
fs17 and}{\b0 \f20 \fs17 so}{\b0 \f20 \fs17 forth. }\par
}
cf0 10.5{\b0 \f20 \fs19
It}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 customary}{\b
0 \f20 \fs19 to}{\b0 \f20 \fs19 designate}{\b0 \f20 \fs19 FF1}{\b0 \f20 \fs19
in}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 as}{\b0 \f20 \
fs19 the }
i850 {\b0 \f20 \fs17 Customarily,}{\b0 \f20 \fs17 FF1}{\b0 \f20 \fs17 is}{\b0
\f20 \fs17 the}{\b0 \f20 \fs17 LSB}{\b0 \f20 \fs17 counter. }\par
}
\cf0 (LSB,{\fs19 MSB)}{\b0 counter. }\par
}
cf0 10.6{\b0 \fs19
Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 10-5.}{\
b0 \fs19 What}{\fs19 is}{\b0 \fs19 the}{\b0 \fs19 binary}{\b0 \fs19 count}
{\b0 \fs19 after}{\b0 \fs19 pulse}{\b0 \fs19 2? }\par
}
\cf0 Fig. 10-5{\b0 \fs17
Timing}{\b0 \fs17 diagram}{\b0 \fs17 for}{\b0 \fs1
7 a}{\b0 \fs17 mod-8}{\b0 \fs17 ripple}{\b0 \fs17 counter }\par
}
\cf0 Solution:
fi354 {\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 count}{\b0 \fs17 after}{\
b0 \fs17 pulse}{\b0 \fs17 2}{\b0 \fs17 is}{\b0 \fs17 010. }\par
}
cf0 10.7{\b0 \fs19

}{\b0 \fs19 The}{\b0 \fs19 output}{\b0 \fs19 of}{\b0 \fs19 FF1}{\b0 \fs19
will}{\b0 \fs19 go}{\b0 \fs19 HIGH}{\b0 \fs19 again}{\b0 \fs19 on}{\b
0 \fs19 the}{\b0 \fs19 trailing}{\b0 \fs19 edge}{\b0 \fs19 of}{\b0 \fs19
clock }
i489 {\b0 \fs19 pulse}{\b0 \f10 \fs19 --. }
i850 {\b0 \fs17 FF1}{\b0 \fs17 will}{\b0 \fs16 go}{\b0 \fs17 HIGH}{\b0 \fs17
again}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 trailing}{\b0 \fs17 edge}
{\b0 \fs17 of}{\b0 \fs17 clock}{\b0 \fs17 pulse}{\b0 \fs17 5. }\par
}
\cf0 10.8{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 10-5.
will}{\b0 \fs19 go}{\b0 \fs19 HIGH}{\b0 \fs19 again}{\b0 \fs19 on}{\b0 \fs
19 the }
\fi487 {\b0 \fs19 edge}{\b0 \fs19 of}{\fs19 clock}{\b0 \fs19 pulse} 6.
\fi851 {\b0 \fs17 FF2}{\b0 \fs17 will}{\b0 \fs17 go}{\b0 \fs17 HIGH}{\b0 \fs
17 again}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 trailing}{\b0 \fs17 edg
e}{\b0 \fs17 of}{\b0 \fs17 clock}{\b0 \fs17 pulse}{\fs16 6, }\par
}
(leading, tra \par
}
will}{\b0 \fs19 go}{\b0 \fs19 LOW}{\b0 \fs19 again}{\b0 \fs19 on}{\b0 \fs19
the}{\b0 \fs19 H-to-L}{\b0 \fs19 edge}{\b0 \fs19 of}{\b0 \fs19 clock}{\b0
\fs19 pulse }
\fi850 {\b0 \fs17 FF3}{\b0 \fs17 will}{\b0 \fs17 go}{\b0 \fs17 LOW}{\b0 \fs1
7 again}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 H-to-L}{\b0 \fs17 edge}{
\b0 \fs17 of}{\b0 \fs17 clock}{\b0 \fs17 pulse}{\b0 \fs17 8. }\par
}
\cf0 10.10{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 10-5.}{
\b0 \fs19 The}{\b0 \fs19 binary}{\b0 \fs19 count}{\b0 \fs19 after}{\b0 \fs19
clock}{\b0 \fs19 pulse}{\b0 \fs19 8}{\b0 \fs19 will}{\b0 \fs19 be }
fi947 {\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 count}{\b0 \fs17 after}{\b
0 \fs17 clock}{\b0 \fs17 pulse}{\fs17 8}{\b0 \fs17 will}{\b0 \fs17 be}{\
b0 \fs17 000. }\par
}
\par
}

\par
}
UNTERS \par
}
f0 [CHAP.{\b0 1}{\b0 0 }\par
}
\fs19 \cf0 10-3{\fs20 PARALLEL}{\fs20 COUNTERS }
fi378 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 asynchronous}{\b0 \f20 \fs18 ripple
}{\b0 \f20 \fs18 counter}{\b0 \f20 \fs18 has}{\b0 \f20 \fs18 the}{\b0 \f20 \
fs18 limitation}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 tim
e}{\b0 \f20 \fs18 lag}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 triggering}{\b0 \f2
0 \fs18 all}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 flip-flops. }
\b0 \f20 To}{\b0 \f20 \fs18 cure}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 problem
,}{\b0\i \f20 \fs18 parallel}{\b0\i \f20 \fs18 counters}{\b0 \f20 \fs18 can
}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 used.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs1
8 logic}{\b0 \f20 \fs18 diagram}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 a}{\b0
\f20 \fs18 3-bit}{\b0 \f20 \fs18 parallel}{\b0 \f20 \fs18 counter}{\b0 \f20
\fs18 is }
\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0\i \f20 \fs
18 10-6a.}{\b0 \f20 \fs18 Note}{\b0 \f20 \fs18 that}{\b0 \f20 \fs18 all}{
\b0 \f20 \fs18 CLK}{\b0 \f20 \fs18 inputs}{\b0 \f20 \fs18 are}{\b0 \f20 \fs1
8 tied}{\b0 \f20 \fs18 directly}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b
0 \f20 \fs18 input}{\b0 \f20 \fs18 clock.}{\b0 \f20 \fs18 They}{\b0 \f20 \f
s18 are}{\b0 \f20 \fs18 wired}{\b0 \f20 \fs18 in }
\b0\i \f20 \fs18 parallel.}{\b0 \f20 \fs18 Note}{\b0 \f20 \fs18 also}{\b0 \f2
0 \fs18 that}{\b0\i \f20 \fs18 JK}{\b0 \f20 \fs18 flip-flops}{\b0 \f20 \fs1
8 are}{\b0 \f20 \fs18 used.}{\b0 \f20 \fs18 FFl}{\b0 \f20 \fs18 is}{\b0 \
f20 \fs18 the}{\b0 \f10 \fs16
1s}{\b0 \f20 \fs18 place}{\b0 \f20 \fs18 co
unter}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 always}{\b0 \f
20 \fs18 in}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 toggle }
\b0 \f20 \fs18 mode.}{\b0 \f20 \fs18 FF2}{\b0 \f20 \fs18 has}{\b0 \f20 \fs18
its}{\b0\i \f20 J}{\b0 \f20 \fs18 and}{\b0\i \f20 \fs18 K}{\b0 \f20 \fs18
inputs}{\b0 \f20 \fs18 tied}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \
f20 \fs18 output}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 FF1}{\b0 \f20 \fs18 an
d}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 hold}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 toggle}{\b0 \
f20 \fs18 mode. }
\b0 \f20 \fs18 The}{\b0 \f20 \fs18 outputs}{\b0 \f20 \fs18 of}{\b0 \f20 \fs1
8 FF1}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 FF2}{\b0 \f20 \fs18 are}{\b0 \
f20 \fs18 fed}{\b0 \f20 \fs18 into}{\b0 \f20 \fs18 an}{\f20 \fs18 AND}{\
b0 \f20 \fs18 gate.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs1
8 gate}{\b0 \f20 \fs18 controls}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 mode
}{\b0 \f20 \fs18 of }
\b0 \f20 \fs18 operation}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 FF3.}{\b0 \f20 \fs
18 When}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 AND}{\b0 \f20 \fs18 gate}{\b0 \f
20 \fs18 is}{\b0 \f20 \fs18 activated}{\b0 \f20 \fs18 by}{\fs18 Is}{\b0 \f20
\fs18 at}{\i \f10 \fs17 A}{\b0 \f20 \fs18 and}{\b0\i \f20 B,}{\b0 \f20 \
fs18 FF3}{\b0 \f20 \fs18 will}{\b0 \f20 \fs18 be}{\b0 \f20 \fs18 in}{\b0 \
f20 \fs18 its}{\b0 \f20 \fs18 toggle}{\b0 \f20 \fs18 mode. }

\b0 \f20 \fs18 With}{\b0 \f20 \fs18 the}{\f20 \fs18 AND}{\b0 \f20 \fs18 gate}
{\b0 \f20 \fs18 deactivated,}{\b0 \f20 \fs18 FF3}{\b0 \f20 \fs18 will}{\b0 \f
20 \fs18 be}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 its}{\b0 \f20 \fs18 hold}{\b0
\f20 \fs18 mode.}{\b0 \f20 \fs18 FF2}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 the
}{\b0 \f20 \fs18 2s}{\b0 \f20 \fs18 place}{\b0 \f20 \fs18 counter}{\b0 \f20 \
fs18 and}{\b0 \f20 \fs18 FF3}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 4s}{\b0 \f20 \fs18 place}{\b0 \f20 \fs18 counter. }\par
}
ock
input \par
}
\par
}
a){\fs14 Logic}{\fs14 diagram }\par
}
ci{\b \f30 \fs17 m}{\f10 \fs14 a}{\f10 \fs15 1 }
5 {\fs16 count }\par
}
\cf0 Binary
43 {\fs16 count }
0 \fs16 --- }
2 {\b \fs16 4s}{\b 2s}{\b \fs16 Is }
\fi102 {\b\i \f10 \fs15 C}{\b\i \f10 \fs15
B}{\b\i \f10 \fs15
A }\par
}
15 0 }
15 0 }
2 1
3 {\b \fs14 1 }
3 1
2 {\b 1 }\par
}
\sl-216 \f10 \fs15 \cf0 0

\sl-221 \f10 \fs15 \cf0 {\fs
\sl-218 \f10 \fs15 \cf0 {\fs
\sl-220 \f10 \fs15 \cf0 \fi4
\sl-211 \f10 \fs15 \cf0 \fi4
\sl-219 \f10 \fs15 \cf0 \fi4
\sl-220 \f10 \fs15 \cf0 \fi5
\fs15 \cf0 \f10 \fs15 \cf0 0

1 1
15 1 }
2 0
4 {\b \fs14 0 }
4 1
0 {\b 1 }\par
}
\sl-220 \f10 \fs15 \cf0 \fi3
15 1 }
3 0
4 {\b \fs14 1 }
5 0
9 {\b 1 }\par
}
\sl-216 \f10 \fs15 \cf0 1

\sl-221 \f10 \fs15 \cf0 0
\sl-218 \f10 \fs15 \cf0 {\fs
\sl-211 \f10 \fs15 \cf0 \fi3

\sl-219 \f10 \fs15 \cf0 \fi3
\sl-220 \f10 \fs15 \cf0 \fi5
\fs15 \cf0 \f10 \fs15 \cf0 0
\sl-220 \f10 \fs15 \cf0 \fi2

\sl-211 \f10 \fs15 \cf0 \fi2
\sl-219 \f10 \fs15 \cf0 \fi2
\sl-220 \f10 \fs15 \cf0 \fi4
\fs15 \cf0 \f10 \fs15 \cf0 0

3 {\fs15 1 }
15 2 }
2 {\fs15 3 }
3 {\i \f20 \fs16 5 }
2 {\b\i \f20 \fs16 6 }
0 {\f20 \fs16 7 }\par
}
10 \fs14 \cf0 (b){\i0 \f20 \fs14 Counting}{\i0 \f20 \fs14 sequence }
cf0 \fi3092 {\b\i0 \f20 \fs16 Fig.}{\b\i0 \fs14 10-6}{\b\i0 \f20 \fs16
A}{\
i0 \f20 \fs16 3-bit}{\i0 \f20 \fs16 parallel}{\i0 \f20 \fs16 counter }
cf0 \fi356 {\i0 \f20 \fs18 The}{\i0 \f20 \fs18 counting}{\i0 \f20 \fs18 sequen
ce}{\i0 \f20 \fs18 for}{\i0 \f20 \fs18 this}{\i0 \f20 \fs18 3-bit}{\i0 \f2
0 \fs18 parallel}{\i0 \f20 \fs18 counter}{\i0 \f20 \fs18 is}{\i0 \f20 \fs1
8 shown}{\i0 \f20 \fs18 in}{\i0 \f20 \fs18 Fig.}{\i0 \f20 \fs18 10-66.}{\
i0 \f20 \fs18 Note}{\i0 \f20 \fs18 that}{\i0 \f20 \fs18 this}{\i0 \f20 \fs1
8 is}{\i0 \f20 \fs18 a }
{\i0 \f20 \fs18 modulo-8}{\i0 \f20 \fs18 (mod-8)}{\i0 \f20 \fs18 counter.}{\i0
\f20 \fs18 The}{\i0 \f20 \fs18 counter}{\i0 \f20 \fs18 will}{\i0 \f20 \fs18
start}{\i0 \f20 \fs18 counting}{\i0 \f20 \fs18 at}{\i0 \f20 \fs18 binary}{\f
20 \fs18 000}{\i0 \f20 \fs18 and}{\i0 \f20 \fs18 count}{\i0 \f20 \fs18 up}
{\i0 \f20 \fs18 to}{\i0 \f20 \fs18 11}{\i0 \f20 \fs18 1.}{\i0 \f20 \fs18 It}
{\i0 \f20 \fs18 will }
{\i0 \f20 \fs18 then}{\i0 \f20 \fs18 recycle}{\i0 \f20 \fs18 back}{\i0 \f20 \f
s18 to}{\f20 \fs18 000}{\i0 \f20 \fs18 to}{\i0 \f20 \fs18 start}{\i0 \f20 \
fs18 the}{\i0 \f20 \fs18 count}{\i0 \f20 \fs18 again. }
\fi360 {\i0 \f20 \fs18 The}{\i0 \f20 \fs18 waveform}{\i0 \f20 \fs18 (timing}{
\i0 \f20 \fs18 diagram)}{\i0 \f20 \fs18 for}{\i0 \f20 \fs18 the}{\i0 \f20 \fs
18 parallel}{\i0 \f20 \fs18 mod-8}{\i0 \f20 \fs18 counter}{\i0 \f20 \fs18 i
s}{\i0 \f20 \fs18 drawn}{\i0 \f20 \fs18 in}{\i0 \f20 \fs18 Fig.}{\i0 \f20 \f
s18 10-7.}{\i0 \f20 \fs18 The}{\i0 \f20 \fs18 top}{\i0 \f20 \fs18 line }
{\i0 \f20 \fs18 represents}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18 clock}{\i0 \f20
\fs18 (CLK)}{\i0 \f20 \fs18 inputs}{\i0 \f20 \fs18 to}{\i0 \f20 \fs18 all}{
\i0 \f20 \fs18 three}{\i0 \f20 \fs18 flip-flops.}{\i0 \f20 \fs18 The}{\i0 \f2
0 \fs18 outputs}{\i0 \f20 \fs18 (at}{\f20 \fs17 Q}{\f20 \fs17 )}{\i0 \f20 \
fs18 of}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18 flip-flops}{\i0 \f20 \fs18 are}{\
i0 \f20 \fs18 shown }
{\i0 \f20 \fs18 in}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18 middle}{\i0 \f20 \fs18
three}{\i0 \f20 \fs18 lines.}{\i0 \f20 \fs18 The}{\i0 \f20 \fs18 bottom}{\i
0 \f20 \fs18 line}{\i0 \f20 \fs18 gives}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18
indicated}{\i0 \f20 \fs18 binary}{\i0 \f20 \fs18 count. }
\fi360 {\i0 \f20 \fs18 Consider}{\i0 \f20 \fs18 pulse}{\i0 \f20 \fs18 1,}{\i0
\f20 \fs18 Fig.}{\f20 \fs18 10-7.}{\i0 \f20 \fs18 Pulse}{\i0 \f20 \fs18 1}
{\i0 \f20 \fs18 arrives}{\i0 \f20 \fs18 at}{\i0 \f20 \fs18 each}{\i0 \f20 \fs
18 of}{\i0 \f20 \fs18 the}{\i0 \f20 \fs18 three}{\i0 \f20 \fs18 flip-flops.}
{\i0 \f20 \fs18 FF1}{\i0 \f20 \fs18 toggles}{\i0 \f20 \fs18 from}{\i0 \f20 \
fs18 LOW }\par
}
o{\fs19 HIGH.}{\fs19 FF2}{\fs18 and}{\fs18 FF3}{\fs18 do}{\fs18 not}{\fs18
toggle}{\fs18 because}{\fs18 they}{\fs18 are}{\fs18 in}{\fs18 the}{\fs1
8 hold}{\fs18 mode}{\i \fs18 (}{\i \fs18 J}{\fs18 and}{\i \fs19 K}{\dn
006 \f10 \fs13 = }
18 count}{\fs18 is}{\fs18 now}{\i \fs18 001. }\par
}
0).{\fs18 The}{\fs18 binary }\par
}
.{\fs16 103 }\par
}
UNTERS \par
}
\par
}
\cf0 Fig. 10-7{\b0
Timing}{\b0 diagram}{\b0 for}{\b0 a}{\b0 3-bit}{\b0 p
arallel}{\b0 counter }\par
}
\cf0 Look at pulse 2, Fig. 10-7. Pulse 2 arrives at all the flip-flops,{\fs19
FF1} and FF2 toggle because they are
the toggle mode{\b\i \f30 \fs20 (J} and{\i K}{\dn006 \f10 \fs11
=} 1).
FF1 goes from HIGH to LOW while FF2 goes from LOW to
.{\fs19 FF3} is still in the hold mode, and{\fs18 so} it does not toggle.
The count is now{\fs19 010. }
60 Pulse{\fs19 3} arrives at all the flip-flops at the same time. Only
FF1 toggles. FF2 and FF3 are in the
\par}{\phpg\posx903\pvpg\posy4894\absw9304\absh3932 \sl-242 \f20 \fs18 \cf0 hold
mode because{\fs18 J} and{\i K}{\dn006 \f10 \fs13 =}{\fs19 0.} The binar
y count is now 011.
60 Consider pulse 4, Fig. 10-7. Note that the AND gate is activated just befor
e the clock pulse goes
HIGH to LOW. The AND gate will put FF3 in the toggle mode{\i (}{\i J} and{\
i K}{\dn006 \f10 \fs11
=} 1). On the H-to-L
sition{\fs19 of} clock pulse 4,{\i \fs18 all} flip-flops toggle.{\fs19
FF1} and FF2 go from HIGH to LOW.{\fs19 FF3} toggles
LOW to HIGH. The binary count is now{\fs18 100.} Note the dashed line b
elow the trailing edge{\fs19 of }
k pulse{\fs19 4.} Hardly any time lag is evident from{\fs19 FF1} to{\fs19 FF3
} because all the flip-flops are clocked at
\par}{\phpg\posx903\pvpg\posy4894\absw9304\absh3932 \sl-239 \f20 \fs18 \cf0 exac
tly the same time. That is the advantage of the parallel-type counter.
Parallel counters are also
ed{\i \fs19 synchronous}{\i \fs19 counters} because all flip-flops trigg
er exactly in time with the clock. Parallel
ters are more complicated (see the added lines and the AND gate), but they a
re used when the
\par}{\phpg\posx903\pvpg\posy4894\absw9304\absh3932 \sl-237 \f20 \fs18 \cf0 time
lag problem with a ripple counter would cause problems.
64 Look over the rest of the waveform in Fig. 10-7. Understand that each flipflop is clocked on each
k pulse. FF1 always toggles. FF2 and FF3 may be in either the toggle or the hol
d mode.
}
cf0 10.11{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 10-7.}{\
b0 \fs18 When}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 5
}{\b0 \fs18 is}{\b0 \fs18 HIGH,}{\b0 \fs18 FF1}{\b0 \fs18 is}{\b0 \fs18 in}
{\b0 \fs18 its}{\b0 \fs18 toggle}{\b0 \fs18 mode,}{\b0 \fs18 FF2}{\b0 \fs18
in}{\b0 \fs18 its }\par
}
hold, toggle) mode, and FF3 in its
}
hold, toggle) mode. \par
}
{\phpg\posx9655\pvpg\posy9490\absw40\absh113 \f10 \fs9 \cf0 \f10 \fs9 \cf0 . \pa

r
}
6 \cf0 When pulse{\fs17 5} is{\fs17 HIGH,} FF1 is in its toggle mode,
FF2 in its hold mode, and FF3 in its hold mode.
{\b \fs18 10.12}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-7.}{\fs18 O
n}{\fs18 the}{\fs18 trailing}{\fs18 edge}{\fs18 of}{\fs18 clock}{\fs18 pu
lse}{\fs19 6,}{\fs18 which}{\fs18 flip-flop(s)}{\fs18 toggle? }
\fi594 {\b Solution: }
950 On the trailing edge of clock pulse 6 (Fig. 10-7), both{\fs17 FF1}
and FF2 toggle.
{\b \fs18 10.13}{\fs18
Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-7.}{\fs18 W
hen}{\fs18 clock}{\fs18 pulse}{\fs18 8}{\fs18 is}{\fs18 HIGH,}{\fs18 whic
h}{\fs18 flip-flops}{\fs18 are}{\fs18 in}{\fs18 the}{\fs18 toggle}{\fs18 m
ode? }
950 When clock pulse{\fs17 8} (Fig. 10-7) is{\fs17 HIGH,} all three fl
ip-flops are in the toggle mode.
{\b \fs18 10.14}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-7.}{\fs18 W
hat}{\fs18 is}{\fs18 the}{\fs18 binary}{\fs18 count}{\fs18 after}{\fs18 cl
ock}{\fs18 pulse}{\fs19 8? }
954 The binary count after clock pulse{\fs17 8} (Fig. 10-7) is{\fs17 0
00. }\par
}
\par
}
UNTERS \par
}
AP.{\fs16 10 }\par
}
cf0 10.15{\b0 \fs18 All}{\b0 \fs18 flip-flops}{\b0 \fs18 in}{\b0 \fs18 th
e}{\b0 \fs18 counter}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0
10-7}{\b0 \fs18 operate}{\b0 \fs18 in}{\b0 \fs18 step}{\b0 \fs18 with}{\
b0 \fs18 the}{\b0 \fs18 clock.}{\b0 \fs18 The}{\b0 \fs18 counter}{\b0 \fs1
8 is }\par
}
herefore referred to as a(n)
}
asynchronous, synchronous) counter. \par
}
\cf0 The counter shown in{\fs16 Fig.}{\fs16 10-7} is referred to as
a synchronous counter.
{\b \fs18 10-4}{\b \fs18
OTHER}{\b \fs18 COUNTERS }
60 {\fs18 Suppose}{\fs18 a}{\fs18 modulo-6}{\fs18 ripple}{\fs18 counter}
{\fs18 were}{\fs18 needed.}{\fs18 What}{\fs18 would}{\fs17
it}{\fs18
look}{\fs18 like?}{\fs18 The}{\fs18 first}{\fs18 step}{\fs18 in }
18 constructing}{\fs18 a}{\fs18 mod-6}{\fs18 ripple}{\fs18 counter}{\fs18
is}{\fs18 to}{\fs18 list}{\fs18 the}{\fs18 counting}{\fs18 sequence}{\fs18
shown}{\fs18 in}{\fs18 Fig.}{\i \fs18 10-8a.}{\fs18 The}{\fs18 counting }
18 sequence}{\fs18 for}{\fs18 the}{\fs18 mod-6}{\fs18 counter}{\fs18 is
}{\fs18 from}{\fs18 000}{\fs18 to}{\fs18 101.}{\fs18 Note}{\fs18 that}{
\fs18 a}{\fs18 3-bit}{\fs18 counter}{\fs18 is}{\fs18 needed}{\fs18 w
ith}{\fs18 a}{\fs18 4s }
18 counter}{\i \fs18 (C),}{\fs18 a}{\fs18 2s}{\fs18 counter}{\i \fs18 (
B),}{\fs18 and}{\fs18 a}{\fs18 1s}{\fs18 counter}{\b\i \fs18 (A).}{\fs1
8 As}{\fs18 shown}{\fs18 in}{\fs18 Fig.}{\i \fs18 10-8a,}{\fs18 the}{
\fs18 3-bit}{\fs18 counter }
18 normally}{\fs18 counts}{\fs18 from}{\fs18 000}{\fs18 to}{\fs18 111.}{\
fs18 The}{\fs18 last}{\fs18 two}{\fs18 counts}{\fs18 on}{\fs18 the}{\fs18
chart}{\fs18 (110}{\fs18 and}{\fs18 111)}{\fs18 must}{\fs18 be}{\fs18 om
itted. }\par
}
ecycle{\fs16 (reset) }\par
}
\cf0 1
fs14 Clock}{\f10 \fs15 - }
4 input }
6 {\f10 \fs13 1 }\par
}
tput \par
}
{\phpg\posx5171\pvpg\posy6454\absw359\absh168 \f20 \fs14 \cf0 \f20 \fs14 \cf0 CL
R \par
}
set \par
}
s14 \cf0 (a){\b0\i0 \fs14 Counting}{\b0\i0 \fs14 sequence }\par
}
5 \cf0 (6){\fs14 Logic-symbol}{\fs14 diagram }
{\b \fs16 Fig.}{\b \fs16 10-8}{\fs16
Mod-6}{\fs16 ripple}{\fs16 counter
}\par
}

\cf0 The trick to this mod-6 design problem is to{\fs18 look} at the binary co
unt{\i immediatdy}{\i after}{\i the}{\i highest }
count}{\i \fs18 of}{\i thc}{\i \fs18 counter.}{\fs18 In} this case, it is{\f
s18 110.} Feed the 110 into a logic circuit that will produce a{\i clear,} or
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-237 \f20 \fs18 \cf0 rese
t, pulse. The clear pulse goes back to an asynchronous clear input{\f
s18 on} each{\i \fs18 JK} flip-flop, thus
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-238 \f20 \fs18 \cf0 clea
ring, or resetting, the counter to 000.
65 The logic circuit needed to clear or reset the{\i \fs18 JK} flip-flops
back to 0 is shown in Fig. 10-8b. The
put NAND gate will do the job when the outputs of FF2 and{\fs18 FF3} are fed
into it. Note from the
ting table in Fig.{\fs18 10-8a} that the first time both{\i \fs18 C}
and{\i \fs18 B} are{\fs18 1} is{\i immediately}{\i \fs18 after} the
highest
t. Thus{\fs18 when} the counter tries to go to{\fs18 110,} it will immediatel
y be cleared or reset to 000.
72 The mod-6 counter shown in Fig. 10-8b is a ripple counter that is just reset
or cleared two counts
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-238 \f20 \fs18 \cf0 befo
re its normal maximum count of 11{\fs18 1.} The NAND gate does the{\fs17 job}
of resetting the{\i \fs18 JK} flip-flops
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-238 \f20 \fs18 \cf0 to 0
by activating the CLR inputs.
64 Waveforms for the mod-6 ripple counter are diagrammed in Fig.{\fs17 10-9
.} The clock{\fs18 (CLK)} input to
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-244 \f20 \fs18 \cf0 FF1
is shown across the top. The middle three lines show the state of the{\i \fs17
Q} outputs. The bottom line
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-231 \f20 \fs18 \cf0 give
s the binary count.
64 The mod-6 counter represented in the diagram in Fig. 10-9 operates as a
normal ripple counter
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-237 \f20 \fs18 \cf0 unti
l pulse 6. The binary count before pulse 6 is 101, the maximum count for this
unit. On the H-to-L
sition of clock pulse 6,{\fs18 FF1} toggles from HIGH to{\fs18 LOW.} F
Fl's H-to-L transition triggers FF2,
h toggles from LOW to HIGH. At point{\i a,} Fig. 10-9, both outputs of FF2 and
{\fs18 FF3} are at 1.These
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-242 \f20 \fs18 \cf0 two{
\fs18 Is} are applied to the NAND gate (see Fig. 10-8b). The NAND gate i
s activated, producing a{\fs18 0. }
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-237 \f20 \fs18 \cf0 The{
\fs18 0} activates the asynchronous CLR input to ail the flip-flops, resetting
them all to 0. The resetting,
\par}{\phpg\posx865\pvpg\posy9033\absw9241\absh4504 \sl-237 \f20 \fs18 \cf0 or c
learing to{\fs18 000,} is shown at point{\i b,} Fig.{\fs18 10-9.} The small
pulse at point{\i \f10 \fs16 a,} Fig. 10-9,{\fs18 is} so short that \par
}
0 CHAP.{\b0 \fs17 101 }\par
}
UNTERS \par
}
\par
}
\cf0 Fig.{\fs16 10-9}{\b0 Timing}{\b0 diagram}{\b0 for}{\b0 \fs16 a}{\b0
mod-6}{\b0 ripple}{\b0 counter }\par
}
t does not even light the output indicators. The counter is free to count upwar
d normally again from
ry{\fs19 000. }
68 Look at the trailing edge of pulse 6 (Fig.{\fs18 10-9)} again. Again note th
e lag between the time pulse 6
from{\fs18 HIGH} to{\fs18 LOW} and the time{\fs18 FF2} and{\fs19 FF3} final
ly are reset to{\fs19 0} at point{\i b.} Engineers refer
his lag time as the propagation time, and it is based on the propagation del
ay of the flip-flop and \par
}
{\phpg\posx877\pvpg\posy5885\absw7809\absh424 \f20 \fs18 \cf0 \f20 \fs18 \cf0 ga
te being used. The propagation delay for a typical{\fs18 TTL} flip-fl
op is very short-from
\par}{\phpg\posx877\pvpg\posy5885\absw7809\absh424 \sl-237 \f20 \fs18 \cf0 (nano
seconds). Some logic families have much longer propagation delays. \par
}
\fs18 to}{\fs19 30}{\fs18 ns }\par
}
\fs18 \cf0 A{\b0 \fs18 decade}{\b0 \fs18 counter}{\b0 \fs18
is}{\b0 \fs18
probably}{\b0 \fs18 the}{\b0 \fs18 most}{\b0 \fs18 widely}{\b0 \fs18
used}{\b0 \fs18 counter.}{\b0 \fs18 It}{\b0 \fs18 could}{\b0 \fs18 also}
{\b0 \fs18 be}{\b0 \fs18 described}{\b0 \fs18 as}{\b0 \fs18 a }
b0 \fs18 rnodulo-10}{\b0 \fs18 counter.}{\b0 \fs18 Figure}{\b0 \fs18 10-10a
}{\b0 \fs19 is}{\b0 \fs18 a}{\b0 \fs18 diagram}{\b0 \fs18 of}{\b0 \fs18 a}
{\b0 \fs18 mod-10}{\b0 \fs18 ripple}{\b0 \fs18 counter.}{\b0 \fs18 Four}{\b
0\i \fs19 JK}{\b0 \fs18 flip-flops}{\b0 \fs18 plus}{\b0 \fs18 a }
b0 \fs18 NAND}{\b0 \fs18 gate}{\b0 \fs18 are}{\b0 \fs18 used}{\b0 \fs18 to
}{\b0 \fs18 wire}{\b0 \fs18 the}{\b0 \fs18 decade}{\b0 \fs18 counter.}{\b0
\fs18 The}{\b0 \fs18 unit}{\b0 \fs18 counts}{\b0 \fs18 just}{\b0 \fs18 li
ke}{\b0 \fs18 the}{\b0 \fs18 mod-16}{\b0 \fs18 counter}{\b0 \fs18 up}{\b0 \f
s18 to }\par
}
8 \cf0 ohob \par

}
15 \cf0 D \par
}
15 \cf0 C
}{\phpg\posx8188\pvpg\posy8366\absw490\absh475 \b\i \f20 \fs15 \cf0 {\b0\i0 \fs1
4 Binary}B
cf0 {\b0\i0 \fs14 output }\par
}
set \par
}
1, \par
}
22 \cf0 Q-' \par
}
4 \cf0 1 \par
}
4 \cf0 J \par
}
cf0 Q-' \par
}
4 \cf0 1 \par
}
4 \cf0 J \par
}
{\phpg\posx4463\pvpg\posy8673\absw291\absh206 \f10 \fs17 \cf0 \f10 \fs17 \cf0 QI \par
}
15 \cf0 1 \par
}
cf0 Clock
i21 {\b0 \fs14 input }\par
}
{\phpg\posx2175\pvpg\posy9076\absw281\absh248 \f10 \fs21 \cf0 \f10 \fs21 \cf0 ->
\par
}
\fs15 \cf0 FF{\b0 \fs15 1 }
b0 \fs15 CLK }\par
}
15 \cf0 1 K \par
}
R \par
}
cf0 Y \par
}
\par
}
fs15 \cf0 FF2
b0 \fs15 CLK }\par
}
15 \cf0 1 K \par
}
R \par
}
\par
}
20 \fs15 \cf0 J
cf0 {\b0\i0 \f10 \fs21 >}{\b0\i0 \fs15 CLK }\par
}
cf0 FF3 \par
}
cf0 Q+' \par
}
4 \cf0 1 \par
}
4 \cf0 J \par
}
\par
}
\fs15 \cf0 FF4
b0 \fs15 CLK }\par
}
15 \cf0 1 K \par
}
R \par
}
\par
}
15 \cf0 1 K \par
}
R \par
}
\par
}
\cf0 (a){\i0 \f20 \fs14 Logic}{\i0 \f20 \fs14 diagram}{\i0 \f20 \fs14 for}
{\i0 \f20 \fs14 ripple-type}{\i0 \f20 \fs14 decade}{\i0 \f20 \fs14 counter }\
par
}
0 I \par
}
utputs \par
}
nputs \par
}
\par
}
4 \cf0 Decade
957 counter
\i \fs15 (b)} Simplified logic symbol for decade counter
\fi1087 {\b \fs16 Fig.}{\b \fs16 10-10 }\par
}
0 238 \par
}
UNTERS \par
}
f0 [CHAP.{\b0 10 }\par
}
01. Binary 1001is the maximum count of this unit. When the count tries to advanc
e to 1010,the{\fs18 two }\par
}
{\phpg\posx831\pvpg\posy1636\absw769\absh432 \f20 \fs19 \cf0 \f20 \fs19 \cf0 Is{
\i (}{\i D}{\dn006 \f10 \fs13 = }
to}{\fs18 0000. }\par
}
{\phpg\posx1573\pvpg\posy1638\absw897\absh216 \f20 \fs18 \cf0 \f20 \fs18 \cf0 1a
nd{\i \fs19 B}{\dn006 \f10 \fs13 = }\par
}
){\fs18 are}{\fs18 fed}{\fs18 into}{\fs18 the}{\fs18 NAND}{\fs18 gate.}{\fs
18 The}{\fs18 NAND}{\fs18 gate}{\fs18 is}{\fs18 activated,}{\fs18 resettin
g}{\fs18 the}{\fs18 display }\par
}
\fs19 \cf0 A{\b0 \fs18 general}{\b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \fs18
is}{\b0 \fs18 sometimes}{\b0 \fs18 used}{\b0 \fs18 for}{\b0 \fs18 a}{\b0 \

fs18 counter}{\b0 \fs18 when}{\b0 \fs18 bought}{\b0 \fs18 in}{\b0 \fs19 IC}
{\b0 \fs18 form.}{\b0 \fs18 The}{\b0 \fs18 logic}{\b0 \fs18 symbol }
\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-10b}{\b0 \fs18 m
ight}{\b0 \fs18 be}{\b0 \fs18 substituted}{\b0 \fs18 for}{\b0 \fs18 the}{\b0
\fs18 decade}{\b0 \fs18 counter}{\b0 \fs18 diagram}{\b0 \fs18 in}{\b0 \fs18
Fig.}{\b0 \fs18 10-IOa.}{\fs18 A}{\b0\i \fs18 clear}{\b0 \fs18 (or }
\b0 \fs18 reset)}{\b0 \fs18 input}{\b0 \fs18 has}{\b0 \fs18 been}{\b0 \fs18
added}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 decade}{\b0 \fs18 counter}{\b0
\fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-lob.}{\b0 \fs18 This}{\b0 \fs18 cle
ar}{\b0 \fs18 input}{\b0 \fs18 does}{\b0 \fs18 not}{\b0 \fs18 appear}{\b0 \f
s18 on }
\b0 \fs18 the}{\b0 \fs18 decade}{\b0 \fs18 counter}{\b0 \fs18 shown}{\b0 \fs1
8 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-10a.}{\b0 \fs18 A}{\b0 \fs18 logical}{\b
0 \fs18 0}{\b0 \fs18 activates}{\b0 \fs18 the}{\b0 \fs18 reset}{\b0 \fs18
and}{\b0 \fs18 clears}{\b0 \fs18 the}{\b0 \fs18 output}{\b0 \fs18 to}{\b0 \f
s18 0000. }
fi361 It{\b0 \fs18 was}{\b0 \fs18 mentioned}{\b0 \fs18 that}{\b0 \fs18 some
}{\b0 \fs18 counters}{\b0 \fs18 count}{\b0 \fs18 downward.}{\b0 \fs18 Figure
}{\b0 \fs18 10-11}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 diagram}{\b0 \fs18 o
f}{\b0 \fs18 such}{\b0 \fs18 a}{\b0 \fs18 down }
\b0 \fs18 counter.}{\b0 \fs18 This}{\b0 \fs18 unit}{\b0 \fs18 is}{\b0 \fs1
8 a}{\b0 \fs18 3-bit}{\b0 \fs18 ripple}{\b0 \fs18 down}{\b0 \fs18 coun
ter.}{\b0 \fs18 The}{\b0 \fs18 binary}{\b0 \fs18 count}{\b0 \fs18 would}
{\b0 \fs18
be}{\b0 \fs18 111,110,}{\b0 \fs18 101,100, }
\b0 \fs18 011,010,001,000,}{\b0 \fs18 followed}{\b0 \fs18 by}{\b0 \fs18 a}{\b0
\fs18 recycle}{\b0 \fs18 to}{\b0 \fs18 111,}{\b0 \fs18 and}{\b0 \fs18 so}{\
b0 \fs18 forth.}{\b0 \fs18 Note}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10
-11a}{\b0 \fs18 that}{\b0 \fs18 the}{\b0 \fs18 ripple}{\b0 \fs18 down }
\b0 \fs18 counter}{\b0 \fs18 is}{\b0 \fs18 very}{\b0 \fs18 similar}{\b0 \fs18
to}{\b0 \fs18 the}{\b0 \fs18 up}{\b0 \fs18 counter.}{\b0 \fs18 The}{\b0 \f
s18 "trigger}{\b0 \fs18 line"}{\b0 \fs18 from}{\b0 \fs18 FF1}{\b0 \fs18 to}
{\b0 \fs18 FF2}{\b0 \fs18 goes}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18
output }
\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 input}{\b0 \fs18
instead}{\b0 \fs18 of}{\b0 \fs18 from}{\b0 \fs18 the}{\b0\i \fs18 Q}{\b0
\fs18 output}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 clock.}{\b0 \fs18 O
therwise,}{\b0 \fs18 the}{\b0 \fs18 up}{\b0 \fs18 counter}{\b0 \fs18 and
}{\b0 \fs18 down }\par
}
I \par
}
f0 . \par
}
f0 I \par
}
cf0 output \par
}

cf0 Clock
put \par
}
\cf0 crrq.:..{\i0 \f10 \fs78 I }\par
}
cf0 FF3 \par
}
s16 \cf0 K
}{\phpg\posx4443\pvpg\posy6543\absw1752\absh537 \b\i \f30 \fs16 \cf0 {\b0\i0 \f2
0 \fs15 *CLK} Q
\cf0 \fi432 {\b0 \f10 \fs12 (a)}{\i0 \f20 \fs15 Logic}{\i0 \f20 \fs15 diagram
}\par
}
cf0 FF2 \par
}
0 &A \par
}
s15 \cf0 C \par
}
i \par
}
\cf0 Clock \par
}
\fs14 \cf0 1
f0 {\fs15 input}{\b0 \f10 --c> }\par
}
cf0 J \par
}
\cf0 Q - ' \par
}
s17 \cf0 Q- \par
}
\cf0 1 J \par
}
\cf0 Q \par
}
\cf0 - l l J \par
}
{\phpg\posx5467\pvpg\posy12010\absw256\absh168 \f10 \fs14 \cf0 \f10 \fs14 \cf0 a> \par
}

\par
}
\f20 \fs15 \cf0 B
{\i0 \fs15 Binary }
{\i0 \fs15 output }\par
}
s15 \cf0 A \par
}
\fs15 \cf0 FF{\fs14 1 }
\b0 \fs15 CLK }\par
}
--O> \par
}
\fs15 \cf0 FF2
\b0 CLK }\par
}
\fs15 \cf0 FF3
\b0 CLK }\par
}
/ \par
}
\cf0 Q \par
}
\cf0 1 K \par
}
\cf0 6 \par
}
\cf0 Fig. 10-11{\f10 \fs16 A}{\b0 3-bit}{\fs16 ripple}{\b0 down}{\b0 \fs1
6 counter }\par
}
0 CHAP.{\b0 101 }\par
}
UNTERS \par
}
\par
}
ounter are wired in the same way. Note also that each{\b\i \fs19 JK} fli
p-flop is{\fs19 in} its toggle mode{\b\i (}{\b\i J} and{\i \fs19 K }

\par}{\phpg\posx869\pvpg\posy1374\absw9134\absh1498 \sl-239 \f20 \fs18 \cf0 equa
l 1).
54 The waveform in Fig. 10-116 aids in the understanding of the operation of th
e down counter. The
\par}{\phpg\posx869\pvpg\posy1374\absw9134\absh1498 \sl-242 \f20 \fs18 \cf0 top
line is the CLK input to FF1. The bottom line is the binaiy count.
Note that the binary count
\par}{\phpg\posx869\pvpg\posy1374\absw9134\absh1498 \sl-239 \f20 \fs18 \cf0 star
ts at 111on the left. Two outputs{\f10 \fs17 ((2} and
are shown for bot
h FF1 and FF2. Output{\i \fs17 Q} is shown
FF3. The outputs attached to the binary indicators are shown with shading on the
timing diagram.
945 {\i \f10 \fs36 a) }
\fi365 Consider pulse{\fs18 1} (Fig. 10-116).{\fs18 All} flip-flops are se
t. The binary output on the indicators is 111. \par
}
{\phpg\posx877\pvpg\posy3039\absw7670\absh427 \f20 \fs18 \cf0 \f20 \fs18 \cf0 On
the H-to-I, transition of pulse 1, FF1 toggles. Output{\i \fs18 Q} goes fro
m HIGH to LOW
\par}{\phpg\posx877\pvpg\posy3039\absw7670\absh427 \sl-239 \f20 \fs18 \cf0 LOW t
o HIGH). The binary count is now 110. \par
}
{\phpg\posx8543\pvpg\posy2816\absw439\absh469 \f20 \fs41 \cf0 \f20 \fs41 \cf0 (e
\par
}
{\phpg\posx8847\pvpg\posy3039\absw948\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 go
es from \par
}
\cf0 Look at pulse 2 (Fig. 10-116). On the H-to-L transition of the c
lock pulse, FF1 toggles. This
\par}{\phpg\posx875\pvpg\posy3515\absw8993\absh425 \sl-237 \f20 \fs18 \cf0 cause
s output{\f10 \fs17 (2} to go from LOW{\fs18 to} HIGH. Output
goes
from HIGH to LOW, thereby causing \par
}
{\phpg\posx869\pvpg\posy3992\absw6103\absh426 \f20 \fs18 \cf0 \f20 \fs18 \cf0 FF
2 to toggle. FF2 toggles, and output{\i \fs19 Q} goes from HIGH to LOW
\par}{\phpg\posx869\pvpg\posy3992\absw6103\absh426 \sl-238 \f20 \fs18 \cf0 The b
inary count is now 101. \par
}
cf0 (a \par
}
oes from LOW to HIGH). \par
}
onsider pulse 3, Fig. 10-116. Pulse 3 triggers{\fs19 FF1.} Output{\i \fs19
Q} of FFl goes LOW while \par
}
{\phpg\posx877\pvpg\posy4711\absw6912\absh419 \f20 \fs18 \cf0 \f20 \fs18 \cf0 HI
GH. The binary output is now 100.
0 {\b \fs18 Look} at pulse{\fs19 4} (Fig. 10-1lb). Pulse 4 triggers FFI. FF1 is
set, and output \par
}
{\phpg\posx877\pvpg\posy5185\absw5069\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 LO
W. That causes FF2{\fs18 to} toggle. FF2 is set, and output \par
}
\par
}
oes from HIGH to \par
}
oes from HIGH to{\fs19 LOW.} That in turn \par
}
{\phpg\posx9335\pvpg\posy4467\absw454\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 go
es \par
}
auses FF3{\fs18 to} toggle and reset.{\fs18 The} binary output after pulse 4
is then 011.
62 {\b \fs19 Look} over the rest of the waveform. Particularly note the
light vertical lines that show the
\par}{\phpg\posx875\pvpg\posy5418\absw9071\absh1337 \sl-239 \f20 \fs18 \cf0 trig
gering of the next flip-flop. Remember that the Q outputs connect to the output
indicators but the
32 outputs of FF1 and FF2 trigger the next flip-flop.
}
cf0 10.16{\b0 \fs18 A}{\b0 \fs18 decade}{\b0 \fs18 counter}{\b0 \fs18 ha
s }
}
ounts and therefore is{\fs18 also} called a modulo- \par
}
unter. \par
}
\cf0 A{\b0 decade}{\b0 counter}{\b0 has}{\b0 \fs17 10}{\b0 counts}{\b0
and}{\b0 is}{\b0 called}{\b0 a}{\b0 modulo-10}{\b0 counter. }\par
}
cf0 10.17{\b0 \f20 \fs18
The}{\b0 \f20 \fs18 maximum}{\b0 \f20 \fs18 binary
}{\b0 \f20 \fs18 count}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18
3-bit}{\b0 \f20 \fs18 counter}{\b0 \f20 \fs18 is }
}
{\phpg\posx6397\pvpg\posy8209\absw1628\absh211 \f10 \fs15 \cf0 \f10 \fs15 \cf0 {\f20 \fs18 (binary}{\f20 \fs18 number). }\par
}
\cf0 The maximum binary count for{\fs16 a} 3-bit counter is binary 111.
\b \fs18 10.18}{\fs18
Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-86.}{\fs18 Th
e}{\fs18 job}{\fs18 of}{\fs18 the}{\fs18 NAND}{\fs18 gate}{\fs18 in}{\fs18

this}{\fs18 mod-6}{\fs18 counter}{\fs18 is}{\fs18 to }\par
}
he flip-flops{\fs18 to }
\par}{\phpg\posx1475\pvpg\posy9618\absw1485\absh729 \sl-240 \f20 \fs18 \cf0 (bin
ary number).
}
{\phpg\posx8797\pvpg\posy9385\absw958\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 (r
eset, set) \par
}
binary number) after the counter's maximum number{\fs18 of }\par
}
6 \cf0 The job{\fs16 of} the{\fs17 NAND} gate shown in Fig. 10-8h is
to reset the flip-flops to 000 after the counter's
588 maximum number of binary{\fs16 101. }
{\b \fs18 10.19}{\fs18
Refer}{\fs18 to}{\fs17 Fig.}{\fs18 10-9.Which}{\
fs18 flip-flop(s)}{\fs18 toggle}{\fs18 on}{\fs18 the}{\fs18 H-to-L}{\fs18
transition}{\fs18 of}{\fs18 clock}{\fs18 pulse}{\fs18 4? }
\fi596 {\b \fs16 Solution: }
944 All three flip-flops toggle on the H-to-L transition{\fs17 of} cloc
k pulse{\b \f30 \fs17 4} (Fig. 10-9).
{\b \f10 \fs17 10.20}{\fs18
Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-3.The}{
\fs18 time}{\fs18 lag}{\fs18 after}{\fs18 clock}{\fs18 pulse}{\f10 \fs17 4
}{\fs18 shown}{\fs18 with}{\fs18 the}{\fs18 dashed}{\fs18 line}{\fs18 is}{
\b\i \f10 \fs16 caused}{\b\i \fs18 by}{\fs18 the }
1281 {\fs18 delay}{\fs18 of}{\fs18 the}{\fs18 flip-flops. }
948 The time lag shown{\b \fs17 by} the dashed line after pulse{\b \f30 \fs17
4} (Fig. 10-3) is caused{\b by} the propagation delay{\fs17 of }
590 the flip-flops. \par
}
\par
}
UNTERS \par
}
AP. 10 \par
}
cf0 10.21{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-9.}{\b0 Why}{\b0 is}{\b0 t
he}{\b0 pulse}{\b0 at}{\b0 point}{\i a}{\b0 \fs18 very}{\b0 short? }

i942 {\b0 \fs17 The}{\b0 \fs17 pulse}{\b0 \fs17 at}{\b0 \fs17 point}{\b0 \
fs17 a,}{\b0 \fs17 Fig.}{\b0 \fs17 10-9,}{\b0 \fs17 is}{\b0 \fs17 very}
{\b0 \fs17 short}{\b0 \fs17 because,}{\b0 \fs17 as}{\b0 \fs16 it}{\b0 \f
s17 goes}{\b0 \fs17 HIGH,}{\b0 \fs17 both}{\b0 \fs17 FF2}{\b0 \fs17 and
}{\b0 \fs17 FF3}{\b0 \fs17 are}{\b0 \fs17 set, }
i582 {\b0 \fs17 which}{\b0 \fs17 causes}{\b0 \fs17 the}{\b0 \fs17 NAND}{\b0
\fs17 gate}{\b0 \fs17 (see}{\b0 \fs17 Fig.}{\b0 \fs17 10-8b)}{\b0 \fs17
to}{\b0 \fs17 reset}{\b0 \fs17 all}{\b0 \fs17 three}{\b0 \fs17 flip-fl
ops. }\par
}
cf0 10.22{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-11a}{\b0 and}{\b0\i \fs18
b.}{\b0 List}{\b0 the}{\b0 next}{\b0 ten}{\b0 binary}{\b0 counts}{\b0 aft
er}{\b0 010}{\b0 on}{\b0 this}{\b0 counter. }
i942 {\b0 \fs17 The}{\b0 \fs17 next}{\b0 \fs17
ten}{\b0 \fs17
binary}{\b
0 \fs17 counts}{\b0 \fs17
after}{\b0 \fs17
010}{\b0 \fs17 on}{\b0 \fs1
7 the}{\b0 \fs17
3-bit}{\b0 \fs17 down}{\b0 \fs17 counter}{\b0 \fs17
of}{\b0 \fs17
Fig.}{\b0 \fs17
10-11}{\b0 \fs17 are}{\b0 \fs17
as}{\b
0 \fs17 follows: }
i588 {\b0 \fs17 001,000,111,110,101,100,011,010,001,000. }\par
}
cf0 10.23{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-lla.}{\b0 This}{\b0 is}{\b0
a}{\b0 mod- }
i947 {\b0 \fs17 This}{\b0 \fs17 is}{\b0 \fs17 a}{\b0 \fs17 mod-8}{\b0 \fs1
7 ripple}{\b0 \fs17 down}{\b0 \fs17 counter. }\par
}
ripple, synchronous) down counter. \par
}
cf0 10.24{\b0 List}{\b0 the}{\b0 binary}{\b0 counting}{\b0 sequence}{\b0
of}{\b0 a}{\b0 mod-9}{\b0 up}{\b0 counter. }
i944 {\b0 \fs17 The}{\b0 \fs17 binary}{\b0 \fs17 counting}{\b0 \fs17 sequenc
e}{\b0 \fs17 of}{\b0 \fs17 a}{\b0 \fs17 mod-9}{\b0 \fs17 up}{\b0 \fs17 c
ounter}{\b0 \fs17 is}{\b0 \fs17 as}{\b0 \fs17 follows:}{\b0 \fs17 0000,0001
,0010,0011,0100,0101, }
i590 {\b0 \fs17 0110,0111,1000. }\par
}
cf0 10.25{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-10a.}{\b0 If}{\b0 this}
{\b0 unit}{\b0 were}{\b0 converted}{\b0 to}{\b0 a}{\b0 mod-9}{\b0 c
ounter,}{\b0 the}{\b0 two}{\b0 inputs}{\b0 to}{\b0 the }\par
}
AND{\fs18 gate}{\fs18 would}{\fs18 be }

}
s21 \cf0 (D,{\b0\i0 \f20 \fs19 C,}{\b0 \f20 \fs19 B,}{\f20 \fs19 A}{\f20 \fs19
)}{\b0\i0 \f20 \fs18 and }\par
}
\cf0 ( D ,{\i0 \fs19 C,} B,{\b \fs18 A). }\par
}
\cf0 If the unit shown{\fs17 in} Fig. 10-10a were converted to a mo
d-9 counter, the two inputs to the NAND
would be{\b\i \f10 \fs15 A} and{\b\i \f30 \fs19 D,}{\fs17 so} all flip-flo
ps would be reset immediately upon hitting the binary 1001 count. \par
}
\cf0 10.26{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-11a.}{\b0 List}{\b0 two}{\
b0 wiring}{\b0 changes}{\b0 that}{\b0 will}{\b0 convert}{\b0 this}{\b0 3bit}{\b0 down}{\b0 counter}{\b0 to}{\b0 an}{\b0 up }
fi592 {\b0 counter. }
fi946 {\b0 \fs17 The}{\b0 \fs17 down}{\b0 \fs17 counter}{\b0 \fs17 shown}{
\b0 \fs16 in}{\b0 \fs17 Fig.}{\b0 \fs17 10-lla}{\b0 \fs17 can}{\b0 \fs17
be}{\b0 \fs17 converted}{\b0 \fs17 to}{\b0 \fs17 an}{\b0 \fs17 up}{\b
0 \fs17 counter}{\b0 \fs17 by}{\b0 \fs17 making}{\b0 \fs17 the}{\b0 \fs1
7 changes }
fi592 {\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 10-llc: }
fi966 {\b0 \fs16 1.}{\b0 \fs17
Move}{\b0 \fs17 the}{\b0 \fs17 wire}{\b0 \f
s17 coming}{\b0 \fs17 from}{\b0 \fs16 Q}{\b0 \fs17 of}{\b0 \fs17 FF1}{\
b0 \fs17 to}{\b0 \fs17 output}{\b0\i \fs16 Q}{\b0 \fs17 of}{\b0 \fs17
FF1. }
fi952 {\b0 \fs17 2.}{\b0 \fs17
Move}{\b0 \fs17 the}{\b0 \fs17 wire}{\b0 \
fs17 coming}{\b0 \fs17 from}{\b0 \fs17
of}{\b0 \fs17 FF2}{\b0 \fs17
to}{\b0 \fs17 output}{\b0\i \fs16 Q}{\b0 \fs17 of}{\b0 \fs17 FF2. }\par
}
\cf0 10.27{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-llb.}{\b0 The}{\b0 clock}
{\b0 input}{\b0 triggers}{\b0 FF1;}{\b0 the }\par
}
FF2;{\fs18 and}{\fs18 the }
}
s19 \cf0 (Q,{\b0 \f10 \fs27 G) }\par
}
5 \cf0 \par}{\phpg\posx7097\pvpg\posy10873\absw2627\absh341 \sl-191 \f10 \fs15 \cf0 {\i
\f20 \fs18 (Q,}{\i \f20 \fs18 Q}{\i \f20 \fs18 )}{\f20 \fs18 output}{\f20 \f
s18 of}{\f20 \fs19 FF1}{\f20 \fs18 triggers }\par
}
output of FF2 triggers{\fs19 FF3} in this ripple counter. \par
}
7 \cf0 The clock triggers FF1; the{\fs16 Q} output{\fs16 of} FF1 triggers
FF2; and the
ripple counter shown in Fig. 10-llb. \par
}
output{\fs16 of} FF2 triggers FF3 in \par
}
\cf0 10-5 lTL{\fs19 IC} COUNTERS
fi364 {\b0 Counters}{\b0 can}{\b0 be}{\b0 constructed}{\b0 from}{\b0 indivi
dual}{\b0 flip-flops}{\b0 and}{\b0 gates}{\b0 or}{\b0 be}{\b0 purchased}
{\b0 from}{\b0 manufac- }
\b0 turers}{\b0 in}{\b0 IC}{\b0 form.}{\b0 Several}{\b0 typical}{\b0 gener
al-purpose}{\b0 TTL}{\b0 counter}{\b0 ICs}{\b0 will}{\b0 be}{\b0 detailed
}{\b0 in}{\b0 this}{\b0 section. }\par
}
0 CHAP.{\b0 101 }\par
}
cf0 COUNTERS \par
}
f0 241 \par
}
\cf0 The 74192 IC is described by the manufacturers as a{\i \fs19 TTL}{\i \fs
19 synchronous}{\i \fs19 BCD}{\i \fs19 up/down}{\i \fs19 counter.}{\b A }
k symbol of the 74192 IC decade counter is shown in Fig. 10-12.Note the use of d
ual clock{\fs19 (CLK) }
ts. If the count-up clock input is pulsed, the counter will count upward from 00
00 to 1001{\fs18 (0} to{\fs18 9 }
\par}{\phpg\posx847\pvpg\posy1356\absw9241\absh1074 \sl-232 \f20 \fs18 \cf0 in d
ecimal). If the count-down clock input is pulsed, the counter will count d
ownward from 1001 to
18 0000} (9 to{\fs18 0} in decimal). The counter toggles on the L-to-H transiti
on of the clock pulse. \par
}
{\phpg\posx4049\pvpg\posy3437\absw275\absh666 \f10 \fs56 \cf0 \f10 \fs56 \cf0 \{
\par
}
0 =; \par
}
14 \cf0 A \par
}

\cf0 Load-data\par}{\phpg\posx3043\pvpg\posy4346\absw1237\absh933 \sl-280 \f20 \fs15 \cf0 \fi1
96 Count-up
\par}{\phpg\posx3043\pvpg\posy4346\absw1237\absh933 \sl-297 \f20 \fs15 \cf0 Coun
t-down
78 Clear- \par
}
{\phpg\posx4577\pvpg\posy4626\absw908\absh679 \f20 \fs15 \cf0 \f20 \fs15 \cf0 >C
LK
\fs21 >} CLK
4 {\b \f10 \fs14 (74192) }\par
}
0 \fs17 \cf0 Fig.{\f10 \fs16 10-12}{\b0
The}{\fs17 74192}{\b0 synchronous
}{\b0 BCD}{\b0 up/ciown}{\b0
counter}{\b0 IC }
f0 \fi354 {\b0 \fs18 The}{\b0 \fs18 asynchronous}{\b0 \fs18 clear}{\b0 \fs18
input}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 74192}{\b0 \fs18 counter}{\b0
\fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 10-12}{\b0 \fs18 i
s}{\b0 \fs18 activated}{\b0 \fs18 by}{\b0 \fs18 a}{\b0 \fs19 HIGH. }
\b0 \fs18 When}{\b0 \fs18 activated,}{\b0 \fs18 the}{\b0 \fs18 clear}{\b0
\fs18 input}{\b0 \fs18 resets}{\b0 \fs18 all}{\b0\i \fs18 Q}{\b0 \fs18
outputs}{\b0 \fs18 to}{\b0 \fs18 LOW}{\b0 \fs19 (0000).}{\b0 \fs18 The}{\b
0 \fs18 clear}{\b0 \fs18 input}{\b0 \fs18 overrides}{\b0 \fs18 all }
\b0 \fs18 other}{\b0 \fs18 inputs.}{\b0 \fs18 The}{\b0 \fs18 74192}{\b0 \fs18
counter}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 preset}{\b0 \fs18 to}{\b0
\fs18 any}{\b0 \fs18 number}{\b0 \fs18 by}{\b0 \fs18 activating}{\b0 \fs18
the}{\b0 \fs18 load-data}{\b0 \fs18 input}{\b0 \fs18 with}{\b0 \fs18 a }
\b0 \fs18 LOW.}{\b0 \fs18 With}{\b0 \fs19 a}{\b0 \fs18 LOW}{\b0 \fs18 at
}{\b0 \fs18 the}{\b0 \fs18 load-data}{\b0 \fs18 input,}{\b0 \fs18 the}{\
b0 \fs18 data}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18
inputs}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 asynchronously }\par
}
{\phpg\posx881\pvpg\posy7141\absw5249\absh430 \f20 \fs18 \cf0 \f20 \fs18 \cf0 tr
ansferred to the{\fs19 BCD} output{\b\i \f10 \fs18 (}{\b\i \f10 \fs18 A}{\f
10 \fs14 =}{\i \fs18 QA,}{\i \fs19 B}{\f10 \fs14 =}{\i \fs18 QB,}{\fs19 C}{
\f10 \fs13 =}{\i \fs18 Q,,}{\i \fs19 D }
4 The BCD outputs shown in Fig. 10-12{\i \fs18 <Q,,Q,,Q,,Q,) }\par
}
{\i \f20 \fs17 Q,). }
50 {\f20 \fs18 are}{\f20 \fs18 the}{\f20 \fs18 normal}{\f20 \fs18 outputs}
{\f20 \fs18 from}{\f20 \fs18 the}{\f20 \fs18 four }\par
}
puts
{\fs15 Data }\par
}
\cf0 BCD
\par}{\phpg\posx4829\pvpg\posy3618\absw1005\absh321 \sl-167 \f20 \fs15 \cf0 up/d

ownQDh \par
}
puts \par
}
{\phpg\posx5511\pvpg\posy4344\absw175\absh409 \f20 \fs10 \cf0 \f20 \fs10 \cf0 QB
\b\i \f10 \fs9 QA }\par
}
{\phpg\posx6073\pvpg\posy4906\absw557\absh436 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Bo
rrow
\par}{\phpg\posx6073\pvpg\posy4906\absw557\absh436 \sl-295 \f20 \fs15 \cf0 Carry
\par
}
lip-flops in the 74192 IC. The carry output is used when{\i \fs19 cascading} s
everal counters together. Figure
3 shows two 74192{\fs19 ICs} cascaded to form an up counter that will coun
t from BCD{\fs19 0000}{\fs19 0000} to
1001{\fs19 (0} to 99 in decimal). Note that the carry output of the 1s up coun
ter is connected directly to
count-up clock input of the 10s up counter. For a cascaded down counter (99 to{\
fs19 0} in decimal), the
\par}{\phpg\posx877\pvpg\posy7618\absw9094\absh1286 \sl-236 \f20 \fs18 \cf0 borr
ow output of the 1s counter is connected directly into the count-down inpu
t of the{\fs19 10s} counter.
count-down input on the 1s counter then becomes the clock input. \par
}
\cf0 UP
\par}{\phpg\posx2591\pvpg\posy9488\absw884\absh301 \sl-159 \f20 \fs15 \cf0 count
er{\b\i \f10 \fs15
QA }\par
}
\fs14 \cf0 (1s)
b0 \fs19 >}{\f20 \fs15 CLK }\par
}
s10 \cf0 QB
\cf0 {\f10 \fs9 Q}{\f10 \fs9 C }
\cf0 {\f10 \fs9 Q}{\f10 \fs9 C }\par
}
}
CD \par
}
\cf0 (74192) \par
}

ount\par}{\phpg\posx3517\pvpg\posy11706\absw524\absh328 \sl-177 \f20 \fs15 \cf0 \fi1
35 {\fs14 U}{\fs14 P }\par
}
\cf0 1
\b0 \f20 \fs15 0 }\par
}
\cf0 Load
02 {\b \f10 \fs10 Q }
\par}{\phpg\posx3613\pvpg\posy12446\absw414\absh435 \sl-156 \f20 \fs15 \cf0 Clea
r \par
}
ounter
4 {\b \f10 \fs14 (10s)}{\b\i \f10 \fs11
Qc. }
78 QB
78 QA \par
}
I \par
}
\cf0 (74192) \par
}
\cf0 Fig.{\fs17 10-13}{\b0 \fs17
Cascading}{\b0 \fs17 two}{\fs17 74192}{\
b0 \fs17 ICs}{\b0 \fs16 to}{\b0 \fs17 form}{\b0 \fs17 a}{\b0 \fs17 0--99}{\
b0 \fs17 BCD}{\fs16 up}{\b0 \fs17 counter }\par
}
\par
}
cf0 COUNTERS \par
}
}
\fs19 \cf0 A{\b0 \fs18 manufacturer's}{\b0 \fs18 timing}{\b0 \fs18 diagram
}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 74192}{\b0 \fs18 decade}{\b0 \f
s18 counter}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig
.}{\b0 \fs19 10-14.}{\b0 \fs18 Shown }
b0 \fs18 from}{\b0 \fs18 left}{\b0 \fs18 to}{\b0 \fs18 right}{\b0 \fs18 are}
{\b0 \fs18 typical}{\b0 \fs18 clear,}{\b0 \fs18 load}{\b0 \fs18 (preset),}{\
b0 \fs18 count-up,}{\b0 \fs18 and}{\b0 \fs18 count-down}{\b0 \fs18 sequences
.}{\b0 \fs18 The}{\b0 \fs18 manufac- }
b0 \fs18 turer's}{\b0 \fs18 waveforms}{\b0 \fs18 give}{\b0 \fs18 much}{\b0 \f
s18 information}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 operation}{\b0 \fs1

8 of}{\b0 \fs18 an}{\b0 \fs18 IC. }\par
}
\cf0 Carry
orrow \par
}
{\phpg\posx3223\pvpg\posy7392\absw31\absh94 \f10 \fs7 \cf0 \f10 \fs7 \cf0 I \par
}
\par
}
}
\par
}
}
\par
}
}
par
}
}
}
}
}
cf0 101 \par
}
cf0 171 \par
}
15 \cf0 Clear
Preset
Sequence:{\b \f10 \fs13
(1)} Clear outputs to zero.
835 {\b \fs15 (2)} Load (preset){\fs15 to} BCD seven.
831 {\b (3)} Count up to eight, nine, carry, zero, one, and two.
831 {\b \f10 \fs13 (4)} Count down{\fs14 to} one, zero, borrow, nine, eight,
and seven. \par
}
{\phpg\posx1995\pvpg\posy9360\absw491\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 No
tes: \par
}
\cf0 (a){\b0 \fs15 Clear}{\b0 \fs15 overrides}{\b0 \fs15 load,}{\b0 \fs15
data,}{\b0 \fs15 and}{\b0 \fs15 count}{\b0 \fs15 inputs. }

\i \fs14 (b)}{\b0 \fs15 When}{\b0 \fs15 counting}{\b0 \fs15 up,}{\b0 \fs15
count-down}{\b0 \fs15 input}{\b0 \fs15 must}{\b0 \fs15 be}{\b0 \f10 \fs13
HIGH}{\b0 \f10 \fs13 ;}{\b0 \fs15 when}{\b0 \fs15 counting}{\b0 \fs15 dow
n, }
fi293 {\b0 \fs15 count-up}{\b0 \fs15 input}{\b0 \fs15 must}{\b0 \fs15 be}{\
fs15 HIGH. }\par
}
\cf0 Fig.{\f10 \fs15 10-14}{\b0
Manufacturer's}{\b0 timing}{\b0 diagrarn
}{\b0 for}{\b0 thc}{\b0 \fs17 741}{\b0 92}{\b0 decade}{\b0 counter}{\b0
\fs17 IC}{\b0\i \fs17 (Courtesy}{\b0\i \fs17 oj}{\b0\i \fs17 National}{\b0
\i \fs17 Semiconductor }
fi887 {\i Corp.) }\par
}
0 \fs18 \cf0 A{\b0 \fs18 second}{\b0 \fs18 counter}{\b0 \fs18 in}{\b0 \fs1
8 1C}{\b0 \fs18 form}{\b0 \fs18 is}{\b0 \fs18 detailed}{\b0 \fs18 in}{\
b0 \fs18 Fig.}{\b0 \fs18 10-15.} A{\b0 \fs18 block}{\b0 \fs18 diagram}{\
b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 TTL}{\b0 \fs18 7493}{\b0 \fs18 4-b
it }
{\b0 \fs18 binary}{\b0\i \fs18 counter}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \
fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-15a.}{\b0 \fs18 Note}{\b0 \fs18 t
he}{\b0 use}{\b0 \fs18 of}{\b0 \fs18 four}{\b0\i \fs19 JK}{\b0 \fs18 f
lip-flops}{\b0 \fs18 each}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 toggle}{
\b0 \fs18 mode. }
\fi21 {\b0 \fs18 Inputs}{\b0\i \fs25 D,}{\b0 \fs18 and}{\b0\i \f30 \fs26 p,}
{\b0 \fs18 are}{\b0\i \fs18 clock}{\b0 \fs18
inputs.}{\b0 \fs18 Note}{\b0
\fs18 that}{\b0 \fs18 normal}{\b0 \fs18 output}{\b0 Q}{\b0 \fs18 of}{
\b0 \fs18 the}{\b0 \fs18 left-hand}{\b0 \fs18 flip-flop,}{\b0 \fs18 Fig.
}
\fi31 {\b0 \fs18 10-150,}{\b0 \fs18 is}{\b0\i \fs18 not}{\b0\i \fs18 connecte
d}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 input}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 second}{\b0 \fs18 FF.}{\b0 \fs18 To}{\b0 \fs
18 form}{\b0 \fs18 a}{\b0 \fs18 4-bit}{\b0 \fs18 mod-16}{\b0 \fs18 ripple}{
\b0 \fs18 counter, }
{\b0 \fs18 an}{\b0 \fs18 external}{\b0 \fs18 connection}{\b0 \fs18 must}{\b0
\fs18 be}{\b0 \fs18 made}{\b0 \fs18 from}{\b0\i \fs19 Q,,}{\b0 \fs18 to}{\
b0 \f10 \fs23 @,}{\b0 \fs17 (pin}{\b0 \fs18 12}{\b0 \fs18 to}{\b0 \fs17 p
in}{\b0 \fs18 1,}{\b0 \fs18 Fig.}{\b0 \fs18 10-156),with}{\b0 \fs24 Go}{\b0
\fs18 serving }
{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 counter}{\b0 \fs18 clock}{\b0 \fs18
input. }
\fi363 {\b0 \fs18 The}{\b0 \fs18 7493}{\b0 \fs18 IC}{\b0 \fs18 has}{\b0 \fs18
two}{\b0 \fs18 reset}{\b0 \fs18 inputs}{\b0\i \fs19 (}{\b0\i \fs19 M}{\b0
\i \fs19 R}{\b0\i \fs19 ,}{\b0 \fs18 and}{\b0\i \fs19 MR,)}{\b0 \fs18 as}
{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-15a.}{\fs17 A}
{\b0 \fs18 mode}{\b0 \fs18 select}{\b0 \fs18 table }
{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 reset}{\b0 \fs18 inputs}{\b0 \fs18
is}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-15c.}{\b0 \fs18 Under}{\b0 \f
s18 normal}{\b0 \fs18 use,}{\b0 \fs18 the}{\b0 \fs18 reset}{\b0 \fs18 input
s}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 7493}{\b0 \fs18 IC}{\b0\i \fs18 m
ust}{\b0 \fs18 not}{\b0 \fs18 be}{\b0 \fs18 left }
{\b0\i \fs18 disconnected}{\b0 \fs18 (floating).}{\b0 \fs18 The}{\b0 \fs18
reset}{\b0 \fs18 pins}{\b0 \fs18 float}{\b0 \fs18 HIGH,}{\b0 \fs18 which}{
\b0 \fs18 places}{\b0 \fs18 the}{\b0 \fs18 IC}{\b0 \fs18 in}{\b0 \fs18 t
he}{\b0 \fs18 reset}{\b0 \fs18 mode.}{\b0 \fs18 While}{\b0 \fs19 in }
{\b0 \fs18 the}{\b0 \fs18 reset}{\b0 \fs18 mode,}{\b0 \fs18 the}{\b0 \fs18
7493}{\b0 \fs19 IC}{\b0 \fs18 cannot}{\b0 \fs18 count.}{\b0 \fs18 The
}{\b0 \fs18 reset}{\b0 \fs18 inputs}{\b0 \fs18 are}{\b0 \fs18 asynchrono
us}{\b0 \fs18 and}{\b0 \fs18 override}{\b0 \fs18 both }
{\b0 \fs18 clocks. }\par
}
0 CHAP.{\b0 \fs17 101 }\par
}
UNTERS \par
}
f0 243 \par
}
20 \fs16 \cf0 CP,
M R l E \par
}
\par
}
16 \cf0 MR2 \par
}
-ia,{\b\i \f30 \fs18 CP, }
30 \fs24 13)}{\b\i \f20 \fs15 NC }
30 \fs23 12)}{\b\i \f20 \fs16 Qo }
20 \fs26 D}{\b\i \f20 \fs11 Q3 }
30 \fs28 lo>}{\f20 \fs14 GND }
\i \f20 \fs27 BQ, }
s23 _S,}{\b\i \f20 \fs11 Q2 }\par
}
fs15 \cf0 NC{\b0\i0 \f10 \fs19 (4 }
0 {\b0 \fs18 vcc}{\b0\i0 \f10 \fs19 (5 }
0 \fi30 {\fs15 NC}{\b0\i0 \f10 \fs25 E }
0 \fi30 {\fs15 NC}{\b0\i0 \f10 \fs22 (7 }

\cf0 \fi640 {\fs15 (b)}{\b0\i0 \fs14 Pin}{\b0\i0 \fs14 diagram }\par
}
{\f10 \fs10 =} HIGH voltage level
\par}{\phpg\posx2739\pvpg\posy6544\absw1682\absh342 \sl-198 \f20 \fs14 \cf0 L{\f
10 \fs10 =} LOW voltage level \par
}
\cf0 (c){\b0 \f20 \fs14
Mode}{\b0 \f20 \fs14 select}{\b0 \f20 \fs14 table }
\par
}
\par
}
tput \par
}
\fs16 \cf0 8
fi71 {\b0 \fs16 9 }
\b0 \fs16 10 }
\fs16 11 }
\b0 12 }
\fs16 13 }
\b0 \f10 \fs15 14 }
\b0 \f10 \fs15 15 }\par
}
\cf0 H
\par}{\phpg\posx6333\pvpg\posy8257\absw167\absh1472 \sl-220 \b \f30 \fs18 \cf0 H
\par
}
\fs18 \cf0 L
\fs18 L }
fi34 {\fs18 L }
\fs18 L }

\fs18 H }
\fs18 H }
\fs18 H }
\fs18 H }\par
}
\fs18 \cf0 L
fi27 {\fs18 L }
\fs18 H }
\fs18 H }
\fs18 L }
\fs18 L }
\fs18 H }
\fs18 H }\par
}
\fs19 \cf0 L
\fs18 H }
fi29 {\fs18 L }
\fs18 H }
fi29 {\fs18 L }
\fs18 H }
\fs18 L }
\fs18 H }\par
}
14 \cf0 Output{\b\i \fs14 Qo}{\b \fs14 is} connected to{\i \f30 \fs27 e,. }
2970 {\b\i \fs15 (d)} Counting sequence for 4-bit counter
\fi2830 {\b \fs16 Fig.}{\b \fs16 10-15}{\fs16
7493}{\fs16 4-bit}{\fs16 bi
nary}{\fs16 counter}{\fs16 IC }
\fi360 {\fs18 The}{\fs18 table}{\fs18 in}{\fs18 Fig.}{\fs18 10-1%}{\fs18
shows}{\fs18 the}{\fs18 binary}{\fs18 counting}{\fs18 sequence}{\fs18 f
or}{\fs18 the}{\fs18 7493}{\fs18 IC}{\fs18 wired}{\fs18 as}{\fs18 a}{\fs1
8 mod-16 }
s18 ripple}{\fs18 counter.}{\fs18 In}{\fs18 Fig.}{\fs18 10-15b,}{\fs18 n
ote}{\fs18 the}{\fs18 unusual}{\fs18 power}{\fs18 connections}{\i \fs18
<Vcc }{\dn006 \f10 \fs11 =}{\fs18 pin}{\fs19 5}{\fs18 and}{\fs18 GND}{\dn0
06 \f10 \fs13 =}{\fs18 pin}{\fs18 10) }

s18 on}{\fs18 the}{\fs18 7493}{\fs18 counter}{\fs18 IC. }
}
\cf0 10.28{\b0 \fs18 The}{\b0 \fs18 74192}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0
a }
fi590 {\b0 \fs18 and}{\b0 \fs18 down). }
f0 \fi596 {\fs16 Solution: }\par
}
(binary, decade) counter that will count \par
}
(down, up, both{\b \fs17 up }\par
}
6 \cf0 The 74192{\fs16 IC}{\fs16 is} a decade counter that will count b
oth up and down depending{\fs17 on} which clock input
\par}{\phpg\posx1495\pvpg\posy13487\absw8232\absh388 \sl-217 \f20 \fs16 \cf0 is
used. \par
}
\par
}
UNTERS \par
}
AP.{\fs16 10 }\par
}
\cf0 10.29{\b0 \fs18 List}{\b0 \fs18 the}{\b0 \fs19 BCD}{\b0 \fs18 outputs
}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 74192}{\b0 \fs18 IC}{\b0 \fs18 co
unter}{\b0 \fs18 after}{\b0 \fs18 each}{\b0 of}{\b0 \fs18 the}{\b0 \fs18
input}{\b0 \fs18 clock}{\b0 \fs18 pulses}{\b0 \fs18 shown}{\b0 \fs18 in }
fi589 {\b0 \fs18 Fig.}{\b0 10-16. }
f0 \fi7921 {\fs15 BCD }
fi7489 {\fs15 output}{\fs15 indicators }\par
}
cf0 Carry \par
}
cf0 0 \par
}
cf0 (74{\f10 \fs14 192) }\par
}
0 \fs15 \cf0 Inputs
f0 {\fs16 Fig.}{\f10 \fs15 10-16}{\b0 \fs16

Up/down}{\b0 \fs16
counter}{\
b0 \fs16 pulse-train}{\b0 \fs16 problem }\par
}
\cf0 Solution:
fi364 {\b0 \fs16 Refer}{\b0 \fs16 to}{\b0 \fs16 the}{\b0 \fs16 waveforms}{\b
0 \fs17 in}{\b0 \fs16 Fig.}{\b0 \fs16 10-14.The}{\b0 \fs16 BCD}{\b0 \fs16
outputs}{\b0 \fs16 for}{\b0 \fs16 the}{\b0 \fs16 74192}{\b0 \fs16 IC}{\b
0 \fs16 counter}{\b0 \fs16 shown}{\b0 in}{\b0 \fs16 Fig.}{\b0 \fs16 10-16
}
\b0 \fs16 are: }\par
}
ulse{\i \f10 \fs13 a}{\f10 \fs11 =} 0000 (clear input overrides all input
s)
e{\i \fs16 b}{\f10 \fs11 =}{\fs16 0001} (count-up input pulsed)
e{\b\i \f10 \fs13 c}{\f10 \fs11 =} 0010 (count up) \par
}
lse{\b\i \fs17 d }\par
}
{\f20 \fs16 0101}{\f20 \fs16 (load}{\f20 \fs16 input}{\f20 \fs16 activated
}{\f20 \fs16 with}{\f20 \fs16 a }
94 {\f20 \fs17 LOW;}{\f20 \fs16 the}{\f20 \fs16 0101}{\f20 \fs16 at}{\f20 \f
s16 the}{\f20 \fs16 data}{\f20 \fs16 inputs }
89 {\f20 \fs16 is}{\f20 \fs16 loaded}{\f20 \fs16 into}{\f20 \fs16 the}{\f2
0 \fs16 counter) }\par
}
}
000{\fs16 (count}{\fs16 down) }\par
}
pulse{\i \f10 \fs15 j}{\f10 \fs11
=}{\fs16 1001} (count-down counter cycl
es to
1189 BCD 1001)
se{\b\i \fs17 k}{\f10 \fs11 =} 1000 (count-down input pulsed)
se{\b\i \f10 \fs16 1}{\f10 \fs11 =}{\fs16 0111} (count down)
se{\b\i \f30 \fs17 m}{\dn006 \f10 \fs11
=}{\fs17 1000} (count-up input pul
sed)
se{\i n}{\f10 \fs11 =}{\fs16 1001} (count up)
se o{\f10 \fs11 =} 0000 (clear input overrides{\fs17 all} other
1281 inputs) \par
}

ulse e{\f10 \fs11 =}{\fs17 0100} (count-down input pulsed)
e{\i \f30 \fs19 f}{\dn006 \f10 \fs11 =}{\fs17 001}{\fs17 1} (count down)
e{\fs15 g}{\f10 \fs11 =}{\fs17 0010} (count down)
e{\i \fs17 h}{\dn006 \f10 \fs11 =}{\fs17 0001} (count down) \par
}
cf0 10.30{\b0 \fs18 The}{\b0 \fs18 counters}{\b0 \fs18 are}{\b0 \fs18 said}
{\b0 \fs18 to}{\b0 \fs18 be }\par
}
cascaded, paralleled) when the carry output{\fs18 of} one 74192 \par
}
C counter is fed into the clock input of the next IC.
\fs16 Solution: }
57 {\fs16 When}{\fs16 the}{\fs16 carry}{\fs16 output}{\fs16 of}{\fs16
one}{\fs16 74192}{\fs16 IC}{\fs16 is}{\fs16 fed}{\fs16 into}{\fs16 t
he}{\fs16 CLK}{\fs16 input}{\fs16 of}{\fs16 the}{\fs16 next}{\fs16 I
C,}{\fs16 the}{\fs16 counters}{\fs16 are }
16 said}{\fs16 to}{\fs16 be}{\fs16 cascaded. }\par
}
\cf0 10.31{\b0 \fs18 The}{\b0 \fs18 7493}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0 \
fs18 a }
}
(ripple-, synchronous-) type counter. \par
}
\cf0 The 7493 IC is a ripple-type counter.
{\b \fs18 10.32}{\fs18 The}{\fs18 reset}{\fs18 inputs}{\i \fs18 (}{\i \fs18
M}{\i \fs18 R}{\i \fs18 ,}{\fs18 and}{\i \fs19 MR,)}{\fs18 on}{\fs18 t
he}{\fs18 7493}{\fs18 IC}{\fs18 are}{\fs18 active }
94 {\b \fs16 Solution: }\par
}
(HIGH,{\fs18 LOW)}{\fs18 inputs. }\par
}
\cf0 See mode table in Fig.{\fs16 10-15c.} The 7493{\b \fs17 IC} has ac
tive HIGH reset inputs.
{\b \fs18 10.33}{\fs18 List}{\fs18 the}{\fs18 binary}{\fs18 output}{\fs1
8 from}{\fs18 the}{\fs18 7493}{\fs18 counter}{\b \fs18 1C}{\fs18 after
}{\fs18 each}{\fs18 input}{\fs18 clock}{\fs18 pulse}{\fs18 shown}{\fs18
in}{\fs18 Fig. }
05 {\fs18 10-17. }\par
}
0 CHAP.{\b0 \f10 \fs15 103 }\par
}
UNTERS \par
}
\par
}
nary
4 output }\par
}
14 \cf0 +5{\b0\i0 \f20 \fs23 v }\par
}
\par
}
puts \par
}
\cf0 Q3
\fi431 {\b \fs15 7493 }
i \fs15 MR}{\fs14 Counter}{\fs11
Q1 }
70 {\i QO }\par
}
\par
}
\par
}
20 \fs16 \cf0 Fig.{\fs16 10-17}{\b0 \fs16
Counter}{\b0 \fs16 pulse-train}{\
b0 \fs16 problem }
cf0 Sohtion:
\fi365 {\b0 \fs16 Refer}{\b0 \fs16 to}{\b0 \fs16 Fig.}{\b0 \fs16 10-15}{\b0
\fs16 for}{\b0 \fs16 assistance.}{\b0 \fs16 The}{\b0 \fs16 binary}{\b0 \fs
16 outputs}{\b0 \fs16 from}{\b0 \fs16 the}{\b0 \fs16 7493}{\b0 \fs16 co
unter}{\b0 \fs17 IC}{\b0 \fs16 shown}{\b0 \fs16 in}{\b0 \fs16 Fig.}{\b0 \
fs16 10-17 }
{\b0 \fs16 are}{\b0 as}{\b0 \fs16 follows: }\par
}
lse{\i\dn006 \f10 \fs10
U}{\dn006 \f10 \fs10 = }
6 pulse}{\i \fs16 h}{\dn006 \f10 \fs10 = }
6 pulse}{\fs16 c}{\dn006 \f10 \fs11 = }\par
}
000 (reset)
0 \fs15 0001} (count up)
\par}{\phpg\posx2259\pvpg\posy5983\absw1362\absh583 \sl-222 \f20 \fs16 \cf0 O O
I O (count up) \par
}
lse{\b\i \f10 \fs15 d}{\dn006 \f10 \fs10 = }
{\b \fs16 c}{\dn006 \f10 \fs10 = }\par
}
01{\fs16 1} (count up)
(count up) \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =}{\fs17 01}10 (count up)
e{\b\i \fs17 h}{\dn006 \f10 \fs11 =}{\fs17 01}{\fs16 11} (count up)
e{\b\i \f30 \fs18 i}{\f10 \fs15 --} 1000 (count up) \par
}
ulse{\i \f30 \fs18 f=}{\fs16 0101} (count up) \par
}
cf0 10.34{\b0 \fs18 The}{\b0 \fs18 7493}{\b0 \fs18 counter}{\b0 \fs18 IC
}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-17}{\b0 \f
s18 is}{\b0 \fs18 in}{\b0 \fs18 the }
i586 {\b0 \fs18 pulse}{\b0\i \f10 \fs15 a. }
}
ode of operation during clock \par
}
he{\fs16 7493}{\fs16 IC}{\fs16 shown}{\fs16 in}{\fs16 Fig.}{\fs16 10-1
7}{\fs16 is}{\fs16 in}{\fs16 the}{\fs16 reset}{\fs16 mode}{\fs16 duri
ng}{\fs16 clock}{\fs16 pulse}{\i \f10 \fs14 a. }\par
}
cf0 10.35{\b0 \fs18 The}{\b0 \fs18 7493}{\b0 \fs18 counter}{\b0 \fs18 IC
}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-17}{\b0 \f
s18 is}{\b0 \fs18 in}{\b0 \fs18 the }
i590 {\b0 \fs18 pulse}{\b0\i \fs18 b. }
}
ode of operation during clock \par
}
he 7493 IC shown{\fs16 in} Fig. 10-17is{\fs16 in} the count mode durin
g clock pulst:{\i b. }\par
}
\cf0 10-6 CMOS IC{\fs18 COUNTERS }
\fi355 {\f10 \fs17 A}{\b0 \fs18 variety}{\b0 \fs18 of}{\b0 \fs18 counters}
{\b0 \fs18 are}{\b0 \fs18 available}{\b0 \fs18 from}{\b0 \fs18 IC}{\b0 \
fs18 manufacturers}{\b0 \fs18 using}{\b0 \fs18 the}{\b0 \fs18 CMOS}{\b0
\fs18 technology.}{\b0 \fs18 Two }
{\b0 \fs18 representative}{\b0 \fs18 CMOS}{\b0 \fs18 counter}{\b0 \fs18 in
tegrated}{\b0 \fs18 circuits}{\b0 \fs18 are}{\b0 \fs18 featured}{\b0 \fs18
in}{\b0 \fs18 this}{\b0 \fs18 section.}{\b0 \fs18 The}{\b0 \fs18 firs
t}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 simple }
{\b0 \fs18 ripple}{\b0 \fs18 counter}{\b0 \fs18 and}{\b0 \fs18 the}{\b0 \fs
18 second}{\b0 \fs18 a}{\b0 \fs18 more}{\b0 \fs18 sophisticated}{\b0 \fs18
presettable}{\b0 \fs18 synchronous}{\b0 \fs18 up/down}{\b0 \fs18
counter
. }
\fi367 {\b0 \fs18 Manufacturer's}{\b0 \fs18 data}{\b0 \fs18 on}{\b0 \fs18
the}{\b0 \fs18 first}{\b0 \fs18 CMOS}{\b0 \fs18 counter}{\b0 \fs18 is}{\
b0 \fs18 reproduced}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-18.}{\f1
0 \fs17 A}{\b0 \fs18 logic}{\b0 \fs18 diagram }
{\b0 \fs18 (called}{\b0 \fs18 a}{\b0 \fs18 function}{\b0 \fs18 diagram}{\b0
\fs18 by}{\b0 \fs18 the}{\b0 \fs18 manufacturer)}{\b0 \fs18 is}{\b0 \fs18
shown}{\b0 \fs18 in}{\b0 Fig.}{\b0 \fs18 10-18a}{\b0 \fs18 for}{\b0 \fs18 t
he}{\b0 \fs18 CMOS}{\b0\i \fs18 74HC393}{\b0\i \f10 \fs17 dud }
{\b0\i 4-bit}{\b0\i binary}{\i \fs17 ripple}{\b0\i counter}{\b0 \fs18 IC.
} A{\b0 \fs18 more}{\b0 \fs18 detailed}{\b0 \fs18 logic}{\b0 \fs18 diagram}
{\b0 \fs18 of}{\b0 \fs18 each}{\b0 \fs18 4-bit}{\b0 \fs18 ripple}{\b0 \fs
18 counter}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in }
{\b0 \fs18 Fig.}{\b0 10-18c.}{\b0 \fs18 Note}{\b0 \fs18 the}{\b0 \fs18 use
}{\b0 \fs18 of}{\b0 \fs18 four}{\b0\i \fs18 T}{\b0 \fs18 flip-flops.}{\b0
\fs18 The}{\b0 \fs18 clock}{\b0 \fs18 inputs}{\b0 \fs18 (1-}{\b0 \fs18
and}{\b0\i \fs19 2D)}{\b0 \fs18 are}{\b0 \fs18 edge-triggered}{\b0 \fs18 on
}
{\b0 \fs18 the}{\b0 \fs18 HIGH-to-LOW}{\b0 \fs18 transition}{\b0 \fs18 of}
{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 as}{\b0 \fs1
8 indicated}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18 pin}{\b0 \fs18 des
cription}{\b0 \fs18 table}{\b0 \fs18 in}{\b0 \fs18 Fig. }
\fi23 {\b0 \fs18 10-18h.}{\b0 \fs18 The}{\b0 \fs18 master}{\b0 \fs18 reset}{
\b0 \fs18 pins}{\b0 \fs18 (1MR}{\b0 \fs18 and}{\b0\i \fs18 2}{\b0\i \fs18
M}{\b0\i \fs18 R}{\b0\i \fs18 )}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 74
HC393}{\b0 \fs18 counter}{\b0 \fs18 are}{\b0 \fs18 active}{\b0 \fs18 HIGH}{\
b0 \fs18 inputs.}{\b0 \fs18 The }
{\b0 \fs18 flip-flop}{\b0 \fs18 outputs}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \f
s18 counter}{\b0 \fs18 are}{\b0 \fs18 labeled}{\b0 \fs18 as}{\b0 \fs18
Q,,}{\b0 \fs18 to}{\b0\i \fs17 Q3}{\b0 \fs18 with}{\b0\i Q,,}{\b0 \fs18 b
eing}{\b0 \fs18 the}{\b0 \fs18 LSB}{\b0 \fs18 while}{\i \fs18 Q3}{\b0 \fs
18 holds}{\b0 \fs18 the }
{\b0 \fs18 MSB}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 4-bit}{\b0 \fs18 bina
ry}{\b0 \fs18 number.}{\b0 \fs18 The}{\b0 \fs18 74HC393}{\b0 \fs18 dual}{\b
0 \fs18 4-bit}{\b0 \fs18 binary}{\b0 \fs18 counter}{\b0 \fs18 is}{\b0 \fs18
packaged}{\b0 \fs18 in}{\b0 \fs18 a}{\b0 \fs18 14-pin}{\b0 \fs18 DIP }

{\b0 \fs18 IC}{\b0 \fs18 which}{\b0 \fs18 is}{\b0 \fs18 illustrated}{\b0 \fs
18 in}{\b0 Fig.}{\b0 \fs18 10-18d.}{\b0 \fs18 The}{\b0 \fs18 74HC393}{\b0
\fs18 counter}{\b0 \fs18 requires}{\b0 \fs18 a}{\b0 \fs19 5-V}{\b0 \fs18
dc}{\b0 \fs18 power}{\b0 \fs18 supply. }\par
}
0 246 \par
}
cf0 COUNTERS \par
}
AP. 10 \par
}
f0 I \par
}
f0 - \par
}
f0 1 \par
}
IN NO.
{\fs14 1,}{\fs15 13 }
15 2,}{\fs15 12 }
\fs15 3,} 475,{\b \fs14 6, }
15 11,}{\b \fs14 10,}{\fs14 9,}{\fs15 8 }
15 7 }
par
}
YMBOL
19 lcp,}{\fs15 2cp }
15 IMR,}{\fs15 2MR }
15 lQ,}{\fs14 to}{\fs15 lQ3. }
15 2Q0}{\fs15 to}{\fs15 2Q3 }
17 GND }
i \f30 vc}{\i \fs15 c }\par
}
NAME{\fs15 AND} FUNCTION
ck{\fs15 inputs} (HIGH-to-LOW,edge-triggered)

\par}{\phpg\posx6153\pvpg\posy2309\absw3390\absh1772 \sl-193 \f20 \fs17 \cf0 asy
nchronousmaster{\fs15 reset}{\fs15 inputs} (activeHIGH)
s14 flip-flop}outputs
{\fs14 ground}{\fs14 (0}{\b \fs15 V) }
s14 positive} supply voltage
\fi253 {\i \fs14 (}{\i \fs14 b}{\i \fs14 ) }\par
}
{\phpg\posx1639\pvpg\posy5803\absw259\absh305 \f10 \fs15 \cf0 \f10 \fs15 \cf0 \par}{\phpg\posx1639\pvpg\posy5803\absw259\absh305 \sl-154 \f10 \fs15 \cf0 {\b\i
\f20 \fs15 CP }\par
}
15 \cf0 MR \par
}
{\phpg\posx3845\pvpg\posy7211\absw245\absh221 \f20 \fs19 \cf0 \f20 \fs19 \cf0 Q,
\par
}
\cf0 1cp
{\b\i \fs15 1MR }
\fi87 {\fs15 1Qn }
\fi95 {\fs15 IQ, }
\fi116 {\fs15 lQ2 }
\fi109 {\fs15 IQ3 }
17 GND }\par
}
cf0 393 \par
}
15 \cf0 Q n \par
}
10 \cf0 Q 2 \par
}
{\phpg\posx5501\pvpg\posy7300\absw183\absh117 \f20 \fs10 \cf0 \f20 \fs10 \cf0 Q3
\par
}
{\phpg\posx863\pvpg\posy8025\absw8832\absh392 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Fi
g.{\b \fs16
10-18}{\fs17
CMOS}{\fs17
dual}{\fs17
4-bit}{\fs17
bin
ary}{\fs17
counter}{\fs17
IC}{\fs17
(74HC393)}{\b\i \f10 \fs14
(}{\b
\i \f10 \fs14 a}{\b\i \f10 \fs14 )}{\fs17
Function}{\fs17
diagram.}{\i \
fs17
(b)}{\fs17 Pin}{\fs17
descriptions. }
7 {\i \fs16 (}{\i \fs16 c}{\i \fs16 )}{\fs17 Detailed}{\fs17 logic}{\fs17
diagram.}{\b\i \f10 \fs16 (}{\b\i \f10 \fs16 d}{\b\i \f10 \fs16 )}{\fs17 Pin
}{\fs17 diagram.}{\i \fs17 (Courtesy}{\i \fs17 of}{\i \fs17 Signetics}{\i
\fs17 Corporation) }\par
}

\cf0 The second featured CMOS counter is the{\b\i 74HC193} presettable
synchronous 4-bit{\fs18 up}{\i \fs19 /down }
ter{\b\i \fs19 IC.} Details of the 74HC193 counter are shown{\fs19 in}
the manufacturer's data in Fig.{\fs19 10-19.}{\b A }
tion diagram, table of pin descriptions, and pin diagram for the 74HC193 c
ounter are shown in
10-19a,{\i \fs18 b,} and c. The 74HC193 counter has two edge-triggered
clock inputs{\i \fs19 (CPU} and{\i \fs19 CP,) }
h operate on the LOW-to-HIGH transition of the clock pulse. One clock
input is used when
ting up{\i \fs19 (CP,,)} while the other is for counting down{\i \fs18 (CP,).
} When using the count up{\i \fs18 (CPU)}input
implementing an up counter, the count down{\i \fs18 (CP,)} pin must be tied
to HIGH or{\i \fs19 +5} V.
64 {\b \fs18 A} truth table detailing the operating modes of the 74HC193CMOS cou
nter is in Fig.{\fs19 10-19d.}The
t mode asynchronously clears the outputs{\i \fs18 (Q3,}{\i\dn006 \f10 \fs1
1 Q2,}{\fs18
Q,,} and{\i \fs18 Q,,)} to binary 0000. The reset pin
\fs19 (}{\i \fs19 M}{\i \fs19 R}{\i \fs19 )} is an active HIGH input which
overrides all other inputs (such as the load, count, and data
ts). The reset{\i \fs19 (}{\i \fs19 M}{\i \fs19 R}{\i \fs19 )} input is
activated with a HIGH briefly on the left side of the waveform
\par}{\phpg\posx871\pvpg\posy9215\absw9162\absh4365 \sl-232 \f20 \fs18 \cf0 diag
ram in Fig. 10-19e when it cleais all flip-flops to{\fs18 0.} The par
allel load inputs on the 74HC193
ter IC include the four data pins{\i (}{\i D}{\i o} to{\i D3)} and t
he parallel load pin{\i \fs25 (E).T}he parallel load
ts are for presetting the counter to any given 4-bit count.{\b \fs18 A} preset
sequence is shown near the left
he waveform diagram in Fig. 10-19e with the
activated with a LOW. Durin
g the parallel load
ation, binary information from the data inputs{\i (}{\i D}{\i 3}{\i
,}{\i D,,}{\i \fs19
D,,} and{\i
Do)} is asynchronously
sferred to the outputs{\i \fs17 (Q3,Q2,}{\fs18 Q,,} and{\i \fs18 Q,,).} In
this example (Fig. 10-19e),binary 1101 is being
\par}{\phpg\posx871\pvpg\posy9215\absw9162\absh4365 \sl-237 \f20 \fs18 \cf0 load
ed into the counter. The reset{\b\i \fs19 (}{\b\i \fs19 M}{\b\i \fs19 R
}{\b\i \fs19 )} input must be LOW during the parallel load operation.
cal count-up and count-down sequences are also shown on the waveform diagram in
Fig. 10-19e.
\par}{\phpg\posx871\pvpg\posy9215\absw9162\absh4365 \sl-237 \f20 \fs18 \cf0 Duri
ng the count-up and count-down sequences, the operation of the carry{\b\i \fs2
5 (E,,) a}{\dn006 nd} borrow{\b\i \fs25 (E,) }\par
}
0 CHAP.{\b0 \fs16 103 }\par
}
UNTERS \par
}
\par
}
{\phpg\posx4503\pvpg\posy2607\absw945\absh111 \f20 \fs9 \cf0 \f20 \fs9 \cf0 PIN
DESCRIPTION \par
}
par
}
{\phpg\posx4659\pvpg\posy2797\absw394\absh111 \f20 \fs9 \cf0 \f20 \fs9 \cf0 PINN
O. \par
}
\par
}
{\phpg\posx5443\pvpg\posy2796\absw475\absh113 \f20 \fs10 \cf0 \f20 \fs10 \cf0 SY
MBOL \par
}
\cf0 NAME AND FIIN('TI<)N
0 \fs19 -- }
40 {\f10 \fs9 flip-flop}{\f10 \fs8 outputs }
37 {\b \f10 \fs7 count}{\f10 \fs8 down}{\f10 \fs8 clock}{\f10 \fs8 inpiit*
}
40 {\f10 \fs8 count}{\f10 \fs8
up}{\f10 \fs8 cluck}{\f10 \fs8 input* }
38 {\f10 \fs8 ground}{\b \f10 \fs8 II)VJ }
40 {\f10 \fs8 asynchionou\\}{\f10 \fs8 parallel}{\f10 \fs9 Iodd}{\f10 \fs8
input}{\f10 \fs8 (active}{\b \fs9 i}{\b \f10 \fs9 OW) }
40 {\f10 \fs8 terniin;il}{\f10 \fs8
count}{\b \fs8
up}{\f10 \fs8 (carry
)}{\f10 \fs8 output}{\f10 \fs8 (active}{\f10 \fs8
LOW) }
40 {\f10 \fs8 tcrrnin;il}{\f10 \fs8
count}{\f10 \fs8 down}{\f10 \fs8 (ho
rrtiu)}{\f10 \fs8 output}{\f10 \fs8
(active }
43 {\f10 \fs9 LOW) }
40 {\f10 \fs8 asynchvonou\\}{\b \fs9 mabter}{\f10 \fs8
r}{\f10 \fs8 o}{\f10
\fs8 e}{\f10 \fs8 (}{\f10 \fs8
lnput}{\f10 \fs8
(d~tive}{\b \f10 \fs9 1
11G11~ }
32 {\f10 \fs8 data}{\f10 \fs8
inputs }
37 {\f10 \fs8 posltlvf'}{\b \fs9 supply}{\b \fs9 vultagc }\par
}

{\b \f20 \fs9 LOW-to-IIIGH.}{\fs8 edgc}{\fs8
triggered }\par
}
-{\b\i \f20 \fs10 K',.,}{\fs7 =}{\fs9 <'PI}{\fs8
at}{\fs8
terminal}{\f
s8
cuunt}{\fs8
up}{\b \f20 \fs9 (llHl1HJ }
11 **}{\fs7 - }
2 {\i \fs9 K,,}{\fs7 --}{\fs8
c.P,>}{\fs7
at}{\fs8
terminal}{\fs8
count}{\fs8
down}{\f20 \fs9 (1.i.I.L) }\par
}
0 11 \par
}
}
f0 1.{\b0 \fs6
=}{\b0 \f20 \fs9 I.0W}{\b0 \fs8
voltage}{\b0 \f20 \fs9
level }
f30 \fs11 X}{\b0 \fs6
=}{\b0 \fs8 don't}{\b0 \fs8
care }\par
}
{\phpg\posx5115\pvpg\posy8238\absw73\absh111 \f10 \fs9 \cf0 \f10 \fs9 \cf0 T \pa
r
}
{\phpg\posx5199\pvpg\posy8238\absw1524\absh290 \f10 \fs6 \cf0 \f10 \fs6 \cf0 ={\
b \fs8 1.OW-to}{\b \f20 \fs9 l11GH}{\fs8
clock}{\fs8
traiivtion }
1 (4 }\par
}
0 IllGH{\b0 \f10 \fs8
voltage}{\b0 \f10 \fs8
level }\par
}
\cf0 Fig.{\f10 \fs15 10-19}{\b0 \fs17
CMOS}{\b0 \fs16 prcsettable}{\b0 \fs
16 4-bit}{\b0 \fs16 synchronous}{\b0 \fs16 up/down}{\b0 \fs16
counter}{\
f10 \fs15 1C}{\b0 \fs17 (74HC193)}{\b0\i \fs16 (}{\b0\i \fs16 a}{\b0\i \fs1
6 )}{\b0 \fs16 Function}{\b0 \fs16 diagram.}{\b0\i \fs16 (}{\b0\i \fs16 b
}{\b0\i \fs16 )}{\b0 \fs17 Pin }
fi886 {\b0 \fs16 descriptions.}{\b0\i \fs16 (}{\b0\i \fs16 c}{\b0\i \fs16 )}{
\b0 \fs17 Pin}{\b0 \fs16 diagram.}{\i \fs17 (}{\i \fs17 d}{\i \fs17 )}{\b0
\fs16 Truth}{\b0 \fs16 table.}{\b0 \fs16 (e)}{\b0 \fs16 Typical}{\b0 \fs16
clear,}{\b0 \fs16 preset,}{\b0 \fs16 and}{\b0 \fs16 count}{\b0 \fs16 seque
nce.}{\i \fs16 (Courtesy }
fi884 {\b0\i \fs16 of}{\i \fs15 Signetrc,}{\b0\i Corporation) }\par
}
\par
}
UNTERS \par
}
AP. 10 \par
}
tputs can be noted. These carry and borrow outputs are used when cascading cou
nters (producing
fs19 8-,} 12-,or 16-bit devices) as either up or down counters. Note that the ca
rry and borrow outputs \par
}
37 \cf0 (w, \par
}
enerate{\fs18 a} negative pulse for either a carry or a borrow. The 74HC193 cou
nter{\fs19 is} housed in \par
}
{\phpg\posx867\pvpg\posy1843\absw359\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 and
\par
}
cf0 zD) \par
}
16-pin DIP and operates on a{\fs19 5-V} dc power supply. \par
}
OLVED{\fs16 PROBLEMS }
\f20 \fs18 10.36}{\f20 \fs18 Refer}{\f20 \fs18 to}{\f20 \fs18 Fig.}{\f20 \
fs18 10-18.}{\f20 \fs18 The}{\f20 \fs18 74HC393}{\b \f20 \fs19 IC}{\f20 \
fs18 contains }
94 {\f20 \fs18 (ripple,synchronous)}{\f20 \fs18 counters}{\f20 \fs18 in}{\f20
\fs18 a}{\f20 \fs18 single}{\f20 \fs18 DIP}{\f20 \fs18 package. }
54 {\f20 The}{\f20 74HC393}{\f20 IC}{\f20 contains}{\f20 two}{\f20 4-bit}
{\f20 binary}{\f20 ripple}{\f20 counters. }\par
}
one,{\fs19 two,} four) 4-bit binary \par
}
cf0 10.37{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-18.}{\b0 The}{\b0 clock
}{\b0 inputs}{\b0 to}{\b0 the}{\b0 74HC393}{\b0 counters}{\b0 are }\
par
}
riggered on the
}
H-to-L, L-to-H) edge of the clock pulse. \par
}
edge, level)- \par
}
\cf0 See Fig. 10-18b.The clock inputs to the 74HC393 counters are edge-trigg
ered on the H-to-L edge of

clock pulse. \par
}
cf0 10.38{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 10-18
.}{\b0 \fs18 Each}{\b0 \fs18 counter}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \f
s18 74HC393}{\b0 \fs19 IC}{\b0 \fs18 contains }
i590 {\b0 \fs18 flip-flops. }
i954 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 10-18c.Each}{\b0 \fs17 count
er}{\b0 \fs17 in}{\b0 \fs17 the}{\b0 \fs17 74HC393}{\b0 \fs17 IC}{\b0 \fs
17 contains}{\b0 \fs17 four}{\b0\i \fs17 T}{\b0 \fs17 flip-flops. }\par
}
three{\i \fs19 D,} four{\i \fs19 T}{\i \fs19 ) }\par
}
cf0 10.39{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-18.}{\b0 The}{\b0 reset}{\
b0 pins}{\b0 to}{\b0 the}{\b0 counter}{\b0 in}{\b0 the}{\b0 74HC393}{\b0
are}{\b0 active }
i593 {\b0 LOW)}{\b0 inputs. }
}
IGH, \par
}
ee Fig. 10-18h. The reset pins (1MR and{\b\i \fs17 2MR)} on the 74HC393
counter are active HIGH inputs. \par
}
\cf0 10.40{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 10-18.The}{\b0 normal}{\b0 co
unting}{\b0 sequence}{\b0 of}{\b0 a}{\b0 4-bit}{\b0 counter}{\b0 (74HC393)
}{\b0 would}{\b0 be}{\b0 from }\par
}
0000{\fs18 through }
}
n binary. \par
}
7 \cf0 Normal counting sequence for the 4-bit counter (74HC393) would be fro
m{\fs16 0000,} through 111l,, and
\par}{\phpg\posx1463\pvpg\posy11415\absw8247\absh385 \sl-215 \f20 \fs17 \cf0 wit
h continued clock pulses, the count would recycle back to 0000, 0001, etc.
\par
}
\cf0 10.41{\b0 Draw}{\b0 the}{\b0 4-bit}{\b0 binary}{\b0 counter}{\b0 wi
red}{\b0 to}{\b0 operate}{\b0 as}{\b0 a}{\b0 decade}{\b0 (mod-10)}{\b0 co
unter.}{\b0 Use}{\b0 a}{\b0 74HC393 }

\fi589 {\b0 4-bit}{\b0 counter}{\b0 and}{\b0 a}{\b0 2-input}{\b0 AND}{\b0
gate. }
\fi951 {\b0 \fs17 One}{\b0 \fs17 method}{\b0 \fs17 of}{\b0 \fs17 convertin
g}{\b0 \fs17 a}{\b0 \fs17 4-bit}{\b0 \fs17 binary}{\b0 \fs17 counter}{\b
0 \fs17 into}{\b0 \fs17 a}{\b0 \fs17 decade}{\b0 \fs17 counter}{\b0 \fs1
7 using}{\b0 \fs17 the}{\b0 \fs17 74HC393}{\fs17 IC}{\b0 \fs17 is }
\fi591 {\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 10-20. }\p
ar
}
. 101 \par
}
UNTERS \par
}
\par
}
\fs16 \cf0 vcc
0 {\b\i0 \fs15 Counter }\par
}
0 L?3 \par
}
0 \par
}
{\phpg\posx1731\pvpg\posy2669\absw3060\absh688 \f20 \fs60 \cf0 \f20 \fs60 \cf0 --m \par
}
cf0 Clockinput \par
}
ucc) \par
}
cf0 Q2 \par
}
{\phpg\posx6411\pvpg\posy3042\absw368\absh682 \f20 \fs27 \cf0 \f20 \fs27 \cf0 e,
7 eo }\par
}
}
15 \cf0 c>{\f20 CP }\par
}
dt \par
}
4 \par
}
17 \cf0 MR \par
}
cf0 I ( \par
}
cf0 (74HC393)
0 \fi180 {\fs15 GND }
i275 {\b0 \f10 \fs31 -- }\par
}
\cf0 Fig.{\fs17 10-20}{\fs17 A}{\b0 \fs17 decade}{\b0 \fs17 (mod-10)counter
}{\b0 \fs17 circuit }\par
}
cf0 10.42{\b0 \f20 \fs19
The}{\b0 \f20 \fs19 74HC193}{\b0 \f20 \fs19 IC}{\b
0 \f20 \fs19 is}{\b0 \f20 \fs19 described}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19
a(n) }
i587 {\b0 \f20 \fs19 up/down}{\b0 \f20 \fs19
counter}{\b0 \f20 \fs19 manufac
tured}{\b0 \f20 \fs19 using }
}
4,8)-bit presettable
79 {\fs19 (CMOS,} 7TL) technology. \par
}
ripple, synchronous) \par
}
he 74HC193 IC is described as a CMOS presettable 4-bit synchronous up/down
counter. \par
}
\cf0 10.43{\b0 \f20 \fs19
Refer}{\b0 \f20 \fs18 to}{\b0 \f20 \fs19 Fig.}{\b
0 \f20 \fs19 10-19.Why}{\b0 \f20 \fs19 does}{\b0 \f20 \fs19 the}{\b0 \f20 \fs
19 74HC193}{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 have}{\b0 \f20 \fs18 two}
{\b0 \f20 \fs19 clock}{\b0 \f20 \fs19 inputs? }
f0 \fi586 {\f20 \fs16 Solution: }
fi944 {\b0 \f20 \fs17 The}{\b0 \f20 \fs17 74HC193}{\b0 \f20 \fs17 counter}{\b0
\f20 \fs17 has}{\i \f20 CPU}{\b0 \f20 \fs17 (count}{\b0 \f20 \fs17 up)}{\b
0 \f20 \fs17 and}{\i \f30 \fs19 CP,}{\b0 \f20 \fs17 (count}{\b0 \f20 \fs17
down)}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 inputs.}{\b0 \f20 \fs17 The}{\i
\f20 \fs17 CPU}{\b0 \f20 \fs17 pin}{\f20 is}{\b0 \f20 \fs17 used }
fi590 {\b0 \f20 \fs16 if}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 design}{\b0 \f2
0 \fs17 calls}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 an}{\b0 \f20 \fs17 up}{\
b0 \f20 \fs17 counter}{\b0 \f20 \fs17 or}{\b0 \f20 \fs17 the}{\b0\i \f20 \
fs17 CP,}{\b0 \f20 \fs17
input}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 used}{
\b0 \f20 \fs17 when}{\b0 \f20 \fs17 developing}{\b0 \f20 \fs17 a}{\b0 \f20 \
fs17 down}{\b0 \f20 \fs17 counter.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs16 two
}
fi586 {\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 inputs}{\b0 \f20 \fs17 make}{\b0
\f20 \fs17 the}{\b0 \f20 \fs17 74HC193}{\b0 \f20 \fs17 counter}{\b0 \f20 \f
s17 a}{\b0 \f20 \fs17 more}{\b0 \f20 \fs17 versatile}{\b0 \f20 \fs17 IC.
}\par
}
\cf0 10.44{\b0 \f20 \fs19
\b0 \f20 \fs19 10-19.}{\b0 \f20 \fs19 The }\par
}
(parallel load, reset) pin is an asynchronous active HIGH \par
}
input that causes the output of the 74HC193 counter to be cleared to 0000 when
activated.
353 {\fs17 The}{\fs17 reset}{\b\i \fs17 (MR)}{\fs17 pin}{\b \fs17 is}{\fs
17 an}{\fs17 asynchronous}{\fs17 active}{\fs17 HIGH}{\fs17 input}{\fs17
that}{\fs17 causes}{\fs17 the}{\fs17 output}{\fs17 of}{\fs17 the}{\
fs17 74HC193 }
s17 counter}{\fs17 to}{\b \fs16 be}{\fs17 cleared}{\fs17 to}{\fs16 0000
}{\fs17 when}{\fs17 activated. }\par
}
\cf0 10.45{\b0 \f20 \fs19
Draw}{\fs16 a}{\b0 \f20 \fs18 mod-6}{\b0 \f20 \
fs19 counter}{\b0 \f20 \fs19 that}{\b0 \f20 \fs19 has}{\b0 \f20 \fs19 a}{\b0
\f20 \fs19 counting}{\b0 \f20 \fs19 sequence}{\b0 \f20 \fs19 of}{\b0 \f20 \f
s19 001,010,011,100,101,110,001,010,}{\b0 \f20 \fs19 etc. }
\fi585 {\b0 \f20 \fs19 This}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 the}{\b0 \f20 \
fs17 type}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 counter}{\b0 \f20 \fs19 that}{
\b0 \f20 \fs19 might}{\b0 \f20 \fs19 be}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19
to}{\b0 \f20 \fs19 simulate}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 roll}{\b0 \f
20 \fs18 of}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 die}{\b0 \f20 \fs19 in}{\b0 \f
20 \fs19 a}{\b0 \f20 \fs19 dice}{\b0 \f20 \fs19 game.}{\b0 \f20 \fs19 Use }
\fi589 {\b0 \f20 \fs19 the}{\b0 \f20 \fs19 74HC193}{\f20 \fs18 IC}{\b0 \f20 \f
s19 and}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 3-input}{\b0 \f20 \fs19 NAND. }
\fi592 {\f20 \fs16 Solution: }
\fi950 {\b0 \f20 \fs17 See}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs17 10-21. }\par
}
0 250 \par
}
UNTERS \par
}

f0 [CHAP.{\b0 \fs16 10 }\par
}
puts \par
}
- \par
}
ock \par
}
\cf0 0
06 0
\fi306 {\fs15 0 }
16 {\fs15 1 }
i \f10 \fs14 +5}{\fs22 v }\par
}
\cf0 Fig.{\fs16 10-21}{\f10
A}{\b0 \fs16 mod-6}{\b0 \fs16 counter}{\b0 \f
s16 circuit}{\b0 \fs16 (counts}{\b0 \fs16 1}{\b0 \fs16 to}{\fs16 6) }\par
}
nary output \par
}
\cf0 +5{\f20 \fs22 v }
\fi167 {\fs19 -}{\i \f20 \fs16
vcc }
\fs15 c}{\i \f20 \fs15 PL }\par
}
unter \par
}
}
\cf0 0
36 {\b \fs14 1 }
32 {\fs15 1 }
\fi332 {\fs15 1 }
{\f10 \fs14 4-5}{\fs22 v }\par
}
\par
}
\par
}

\par
}
4 \par
}
puts \par
}
{\phpg\posx5421\pvpg\posy10146\absw27\absh65 \f10 \fs5 \cf0 \f10 \fs5 \cf0 ' \pa
r
}
10 \cf0 D3
{\b0 \fs14 D2 }
cf0 {\i0 \f10 \fs13 01 }
cf0 {\b0 \fs15 Do }\par
}
\par
}
{\phpg\posx7201\pvpg\posy9862\absw316\absh503 \f20 \fs10 \cf0 \f20 \fs10 \cf0 Qi
\i \fs18 Q" }\par
}
{\phpg\posx5423\pvpg\posy10490\absw624\absh926 \f10 \fs21 \cf0 \f10 \fs21 \cf0 ~
>{\b\i \f20 \fs14 CPD }
\fi28 {\fs20 >}{\b\i\dn006 \fs13 CPU }
06 {\b\i \f20 \fs15 MR }\par
}
74HC193) \par
}
ND
00 {\f10 \fs27 -}{\f10 \fs27 - }\par
}
1 \par
}
\cf0 Fig.{\fs16 10-22}{\b0
Counter}{\b0 pulse-train}{\b0 problem }\par
}
0 CHAP.{\b0 \fs17 101 }\par
}
UNTERS \par
}
\fs19 1 }\par
}
.}{\b0 \fs18 The}{\b0 \fs18 74HC193}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0 \fs1
8 wired}{\b0 \fs18 as}{\b0 \fs18 a}{\b0 \fs18 mod- }
i589 {\b0 \fs18 circuit. }
}
number) counter in this \par
}
\cf0 The 74HC193{\fs17 IC} is wired as a{\fs17 mod-10} (decade) counter i
n the circuit in Fig. 10-22.
{\b \fs18 10.47}{\fs18
Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-22.}{\fs18 L
ist}{\fs18 the}{\fs18 mode}{\fs18 of}{\fs18 operation}{\fs18 during}{\fs18
each}{\fs18 pulse}{\i \fs19 a}{\fs18 to}{\fs19 f.}{\fs18 (Use}{\fs18 ans
wers}{\fs18 parallel }
91 {\fs18 load,}{\fs18 count}{\fs18 up,}{\fs18 or}{\fs18 count}{\fs18 down.
) }
45 pulse{\b\i \fs17 a}{\f10 \fs13 =} parallel load
43 pulse{\i \fs16 b} to{\i \f30 \fs19 f}{\i \f30 \fs19 =} count up
{\b \fs18 10.48}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 10-22.}{\fs18 L
ist}{\fs18 the}{\fs18 binary}{\fs18 output}{\fs18 for}{\fs18 the}{\fs18 7
4HC193}{\fs18 counter}{\fs18 after}{\fs18 each}{\fs18 pulse}{\fs19 a}{\f
s18 to}{\b\i \f30 \fs20 f. }
43 The binary output{\fs16 of} the decade counter in Fig. 10-22after e
ach pulse is as follows:
45 pulse{\b\i \fs16 a}{\dn006 \f10 \fs11 =} 0111 (parallel load{\fs16 to}
01{\fs17 11) }
51 pulse{\i b}{\dn006 \f10 \fs11 =} 1000
51 pulse{\b \f10 \fs13 c}{\dn006 \f10 \fs11 =} 1001
51 pulse{\b\i \f10 \fs16 d}{\dn006 \f10 \fs11 =} 0000 (reset to{\fs17 000
0) }
45 pulse{\b\i \fs17 e}{\dn006 \f10 \fs11 =} 0001
45 pulse{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =} 0010 \par
}
\cf0 10-7{\fs18
FREQUENCY}{\fs18 DMSION:}{\fs19 THE}{\fs19 DIGITAL}{\fs18
CLOCK }
fi360 {\b0 \fs18 The}{\b0 \fs18 idea}{\b0 \fs18 of}{\b0 \fs18 using}{\b0 \fs1
8 a}{\b0 \fs18 counter}{\b0 \fs18 for}{\b0 \fs18 frequency}{\b0 \fs18 divis

ion}{\b0 \fs18 was}{\b0 \fs18 introduced}{\b0 \fs18 in}{\b0 \fs18 Sec.}{\b0
\fs18 10-2.}{\b0 \fs18 It}{\b0 \fs18 was}{\b0 \fs18 mentioned }
\b0 \fs18 that,}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs18 4-bit}{\b0 \fs18 co
unter}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-2,}{\b0 \
fs18 the}{\i \f10 \fs17 A}{\b0 \fs18 output}{\b0 \fs18 could}{\b0 \fs18 b
e}{\b0 \fs18 considered}{\b0 \fs18 a}{\b0 \fs18 divide-by-2}{\b0 \fs18 outp
ut }
\b0 \fs18 because}{\b0 \fs18 it}{\b0 \fs18 divides}{\b0 \fs18 the}{\b0 \fs18
clock}{\b0 \fs18 input}{\b0 \fs18 frequency}{\b0 \fs18 in}{\b0 \fs18 half.
}{\b0 \fs18 Likewise,}{\i \fs19 B}{\b0 \fs18 (Fig.}{\b0 \fs18 10-2)can}{\b0
\fs18 serve}{\b0 \fs18 as}{\b0 \fs18 a}{\b0 \fs18 divide-by-4 }
\b0 \fs18 output,}{\i \fs19 C}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 divideby-8}{\b0 \fs18 output,}{\b0 \fs18 and}{\b0\i \fs19 D}{\b0 \fs18 is}{\b0
\fs18 a}{\b0 \fs18 divide-by-16}{\b0 \fs18 frequency}{\b0 \fs18 division}{\b
0 \fs18 output. }
fi371 {\b0 \fs18 One}{\b0 \fs18 digital}{\b0 \fs18 system}{\b0 \fs18 that}{\b
0 \fs18 makes}{\b0 \fs18 extensive}{\b0 \fs18 use}{\b0 \fs18 of}{\b0 \fs18
counters}{\b0 \fs18 is}{\b0 \fs18 diagrammed}{\b0 \fs18 in}{\b0 \fs18 Fig.}
{\b0 \fs18 10-23.The}{\b0 \fs18 digital }
\b0 \fs18 clock}{\b0 \fs18 uses}{\b0 \fs18 counters}{\b0 \fs18 as}{\b0\i \f
s18 frequency}{\i \fs19 diriders}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs18
lower}{\b0 \fs18 section.}{\b0 \fs18 'The}{\b0 \fs18 counters}{\b0 \fs18 sho
wn}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-23}{\b0 \fs18 are }
\b0 \fs18 also}{\b0 \fs18 used}{\b0 \fs19 as}{\b0\i \fs18 count}{\b0\i \fs19
accumulators.}{\b0 \fs18 The}{\b0 \fs18 count}{\b0 \fs18 accumulator's}{\b0
\fs18 job}{\b0 \fs18 is}{\b0 \fs18 to}{\b0 \fs18 count}{\b0 \fs18 the}{\b0
\fs18 input}{\b0 \fs18 pulses}{\b0 \fs18 and}{\b0 \fs18 serve}{\b0 \fs18 as
}
\b0 \fs18 a}{\b0 \fs18 temporary}{\b0 \fs18 memory}{\b0 \fs18 while}{\b0 \fs1
8 passing}{\b0 \fs18 the}{\b0 \fs18 current}{\b0 \fs18 time}{\b0 \fs18 thro
ugh}{\b0 \fs18 the}{\b0 \fs18 decoders}{\b0 \fs18 onto}{\b0 \fs18 the}{\b0 \
fs18 time}{\b0 \fs18 displays.}{\b0 \fs18 The }
\b0 \fs18 block}{\b0 \fs18 diagram}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18
10-23represents}{\b0 \fs18 a}{\b0 \fs18 6-digit}{\b0 \fs18 24-h}{\b0 \fs18
digital}{\b0 \fs18 clock. }
fi367 {\b0 \fs18 The}{\b0 \fs18 input}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18
frequency}{\b0 \fs18 dividers}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fi
g.}{\b0 \fs18 10-23is}{\b0 \fs19 a}{\b0 \fs18 60-Hz}{\b0 \fs18 square}{\b0 \
fs18 wave.}{\b0 \fs18 The}{\b0 \fs18 divide-by-60 }
\b0 \fs18 blocks}{\b0 \fs18 could}{\b0 \fs18 be}{\b0 \fs18 constructed}{\b0
\fs18 by}{\b0 \fs18 using}{\b0 \fs18 a}{\b0 \fs18 divide-by-6}{\b0 \fs1
8 counter}{\b0 \fs18 feeding}{\b0 \fs18 a}{\b0 \fs18 divide-by-10}{\b0 \f
s18 counter.}{\fs18 A}{\b0 \fs18 block }
\b0 \fs18 diagram}{\b0 \fs18 of}{\b0 \fs18 such}{\b0 \fs18 an}{\b0 \fs18
arrangement}{\b0 \fs18 is}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-2
4a.}{\b0 \fs18 The}{\b0 \fs18 divide-by-6}{\b0 \fs18 counter}{\b0 \fs18 on
}{\b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 divides}{\b0 \fs18 the }
\b0 \fs18 60}{\b0 \fs18 Hz}{\b0 \fs18 to}{\b0 \fs18 10}{\b0 \fs19 Hz.}{\b
0 \fs18 The}{\b0 \fs18 divide-by-10}{\b0 \fs18 counter}{\b0 \fs18 on}{\b0
\fs18 the}{\b0 \fs18 right}{\b0 \fs18 divides}{\b0 \fs18 the}{\b0 \fs18
10}{\b0 \fs18 Hz}{\b0 \fs18 to}{\b0 \fs18 1}{\b0 \fs18 Hz,}{\b0 \fs18
or}{\b0 \fs18 1}{\b0 \fs18 pulse}{\b0 \fs18 per }
\b0 \fs18 second.}{\b0 \fs18 The}{\b0 \fs18 divide-by-60block}{\b0 \fs18 is}{
\b0 \fs18 shown}{\b0 \fs18 implemented}{\b0 \fs18 by}{\b0 \fs18 using}{\b0
\fs18 7493}{\b0 \fs19 ICs}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-24b.
}
fi366 {\b0 \fs18 The}{\b0 \fs18 divide-by-10}{\b0 \fs18 counter}{\b0 \fs18
shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-24b}{\b0 \fs18 is}{\b0
\fs18 implemented}{\b0 \fs18 by}{\b0 \fs18 first}{\b0 \fs18 making}{\b0
\fs18 an}{\b0 \fs18 external }
\b0 \fs18 connection}{\b0 \fs18 from}{\b0 \fs19 (Io}{\b0 \fs18 to}{\i \fs25
B,.}{\b0 \fs18 This}{\b0 \fs18 makes}{\b0 \fs18 the}{\b0 \fs18 7493}{\b0 \fs
18 IC}{\b0 \fs18 a}{\b0 \fs18 4-bit}{\b0 \fs18 binary}{\b0 \fs18 counter.}{
\b0 \fs18 Second,}{\b0 \fs18 the}{\b0 \fs18 IC}{\b0 \fs18 must}{\b0 \fs18
be }
\b0 \fs18 converted}{\b0 \fs18 to}{\b0 \fs18 a}{\b0 \fs18 decade}{\b0 \fs18
or}{\b0 \fs18 mod-10}{\b0 \fs18 counter.}{\b0 \fs18 This}{\b0 \fs18 is}{\b0
\fs18 accomplished}{\b0 \fs18 by}{\b0 \fs18 resetting}{\b0 \fs18 the}{\b0
\fs18 counter}{\b0 \fs18 outputs}{\b0 \fs18 to}{\b0 \fs19 0 }\par
}
hen binary 1010first appears. The resetting is done by using the HIGH outputs fr
om{\i\dn006 \f10 \fs11
Q3 }
\par}{\phpg\posx851\pvpg\posy11787\absw7757\absh427 \sl-239 \f20 \fs18 \cf0 back
to the two reset inputs on the 7493{\b \fs19 IC. }\par
}
and Q, tied \par
}
8 \cf0 The divide-by-6 counter shown in Fig. 10-24b is wired like the u
nit diagrammed earlier in Fig.
s19 10-8.}The first flip-flop inside the 7493 IC package is not used,{\fs19 so
}{\b\i \fs25 B,}becomes the clock input to the
\par}{\phpg\posx863\pvpg\posy12263\absw9056\absh1275 \sl-232 \f20 \fs18 \cf0 div
ide-by-6 counter.
354 The{\fs18 0} to 59 count accumulators in the block diagram of the digital c
lock shown in Fig. 10-23 are
\par}{\phpg\posx863\pvpg\posy12263\absw9056\absh1275 \sl-231 \f20 \fs18 \cf0 act
ually two counters.{\b A} block diagram showing more detail of the s
econds count accumulator/
\par}{\phpg\posx863\pvpg\posy12263\absw9056\absh1275 \sl-237 \f20 \fs18 \cf0 dec
oder/display section is sketched in Fig. 10-25.{\b \fs19 A} decade (mod-10) cou
nter is needed to accumulate \par
}
\par
}
UNTERS \par
}
f0 [CHAP.{\b0 \fs17 10 }\par
}
cf0 Fig.{\fs17 10-23}{\b0 \fs17
Block}{\b0 \fs17 diagram}{\b0 \fs17 of}
{\b0 \fs17 a}{\b0 \fs17 digital}{\b0 \fs17 clock}{\b0\i \fs17 (Roger}{\b
0\i \fs17 L.}{\b0\i \fs17 Tokheim,}{\b0 \fs17 Digital}{\b0 \fs17 Electroni
cs,}{\b0\i \f10 \fs16 3d}{\b0\i \fs17 ed.,}{\b0\i \fs17 McGruw-Hill,}{\b0\
i \fs17 New }
i891 {\i \fs17 York,}{\b0\i \fs17 1990) }\par
}
\cf0 0 \par
}
\cf0 0 \par
}
\cf0 O J U U U U L
fi304 {\b0 \fs15 60}{\b0 \fs15 Hz }\par
}
\f20 \fs15 Hz }\par
}
\cf0 (a){\b\i0 \f20 \fs15 Block}{\i0 \f20 \fs14 diagram }\par
}
\cf0 t5{\b0 \f20 \fs21 v }
fi132 {\b0 \f10 \fs15 15 }\par
}
}
utput
\fi140 {\fs14 1}{\fs15 Hz }\par
}
nput
{\fs15 60}{\fs15 Hz }\par
}
b y{\fs15 10 }\par
}
\cf0 2
\fs15 3}{\i \f30 \fs12 M}{\i \f30 \fs12 R}{\i \f30 \fs12 l }
fi133 {\i \fs15 MR2 }\par
}
{\phpg\posx7099\pvpg\posy11498\absw444\absh319 \f20 \fs11 \cf0 \f20 \fs11 \cf0 Q
I{\fs15 ,9 }
33 {\fs15 12 }\par
}
7493){\i \f10 \fs19 G- }\par
}
G1 \par
}
{\f20 \fs15
GND }\par
}
cf0 I \par
}
\cf0 C \par
}
\cf0 (h){\i0 \fs15 Wiring}{\i0 \fs14 diagram}{\i0 \fs15 using}{\i0 \fs14 74
03}{\i0 \fs14 counters }
\fi52 {\b\i0 \fs16 Fig.}{\b\i0 \fs16 10-24}{\i0 \fs17
Divide-by-60}{\i0 \fs1
6 counter }\par
}
0 CHAP.{\b0 101 }\par
}
UNTERS \par
}
\par
}
\cf0 Fig.{\f10 \fs15 10-25}{\b0 \fs16
Detailed}{\b0 \fs16 block}{\b0 \fs1
6 diagram}{\b0 \fs16 of}{\b0 \fs16 the}{\b0 \fs16 seconds}{\b0 \fs16 cou
nt}{\b0 \fs16 accumulator}{\b0 \fs16 of}{\b0 \fs16 the}{\b0 \fs16 digital}
{\b0 \fs16 clock }\par
}
he{\fs19 Is} of seconds. This decade counter is driven directly from
the output of the first divide-by-60
uency divider.{\b \fs18 As} the decade counter sequences from{\fs18 9}
back to 0, it generates{\fs18 a} "carry pulse"
h is sent to the mod-6 10s{\fs19 of} seconds counter. The decoder/drivers s
erve to decode the{\fs19 BCD} to
n-segment display output.
66 The minutes and hours count accumulators shown in Fig. 10-23 are co
nnected similarly to the
\par}{\phpg\posx877\pvpg\posy8474\absw9283\absh2532 \sl-238 \f20 \fs18 \cf0 seco
nds accumulator. The minutes count accumulator would consist of a decade
and mod-6 counter
\par}{\phpg\posx877\pvpg\posy8474\absw9283\absh2532 \sl-237 \f20 \fs18 \cf0 (lik

e the seconds accumulator). However, the hours count accumulator would consis
t{\fs18 of} a decade and
\par}{\phpg\posx877\pvpg\posy8474\absw9283\absh2532 \sl-242 \f20 \fs18 \cf0 a mo
d-3 counter (or mod-2 counter for a 12-h clock).
3 {\b \fs18 10.49} The divide-by-60 block{\fs18 of} the digital clock sh
own in Fig. 10-23 could be constructed by{\fs18 using }\par
}
wo
}
9 \cf0 .
{\f20 \fs16 See}{\f20 \fs16 Fig.}{\f20 \fs16 10-24.}{\f20 \fs16 The}{\f20 \
fs16 divide-by-60}{\f20 \fs16 block}{\f20 \fs16 shown}{\f20 \fs16 in}{\f2
0 \fs16 Fig.}{\f20 \fs17 10-23}{\f20 \fs16 could}{\f20 \fs16 be}{\f20 \fs1
6 wired}{\f20 \fs16 by}{\f20 \fs16 using}{\f20 \fs16 two}{\f20 \fs16 c
ounters. }\par
}
\cf0 10.50{\b0 \fs18 The}{\b0 \fs18 0}{\b0 \fs18 to}{\b0 \fs18 59}{\b0 \fs1
8 count}{\b0 \fs18 accumulator}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 dig
ital}{\b0 \fs18 clock}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \f
s18 10-23}{\b0 \fs18 could}{\b0 \fs18 be}{\b0 \fs18 constructed}{\b0 \fs18
by }\par
}
sing
}
\par
}
6 \cf0 See{\fs17 Fig.}{\fs17 10-25.} The{\fs17 0} to{\fs17 59} count
accumulator shown in Fig.{\fs17 10-23} could be wired{\fs16 by} using
two
\par}{\phpg\posx1495\pvpg\posy13351\absw8237\absh387 \sl-217 \f20 \fs16 \cf0 cou
nters. \par
}
\par
}
UNTERS \par
}
AP. 10 \par
}
cf0 10.51{\b0 \fs18 Draw}{\b0 \fs18 a}{\b0 \fs18 diagram}{\b0 of}{\b0 \fs18
decade}{\b0 \fs18 and}{\b0 \fs18 mod-6}{\b0 \fs18 counters}{\b0 \fs18 wire

d}{\b0 \fs18 to}{\b0 \fs19 form}{\b0 \fs18 the}{\b0 \fs18 count}{\b0 \fs18
accumulator}{\b0 \fs18 shown}{\b0 \fs18 in }
i593 {\b0 \fs18 Fig.}{\b0 \fs18 10-25.}{\b0 \fs19 Use}{\b0 \fs19 two}{\b0 \fs
18 7493}{\b0 \fs18 ICs. }
i954 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 10-26. }\par
}
r \par
}
w \par
}
cf0 Q3 Q2
Qi
i210 {\fs15 Mod-6 }
i173 {\b0 \fs15 count}{\fs15 er }
i207 {\fs15 (7493) }\par
}
cf0 Q3 Q 2 Q i \par
}
cf0 Qo \par
}
cf0 Decade
b0 counter }
i36 {\fs15 (7493) }\par
}
0 \fs16 \cf0 Fig.{\fs16 10-26}{\b0 \fs17
Wiring}{\b0 \fs17 of}{\b0 \fs17
a}{\b0 \fs17 0}{\b0 \fs17 to}{\b0 \fs17 59}{\b0 \fs17 count}{\b0 \fs17 acc
umulator}{\b0 \fs17 circuit }
f0 {\f10 \fs17 10.52}{\b0 \fs18
Draw}{\fs19 a}{\b0 \fs18 diagram}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 divide-by-60}{\b0 \fs18 frequency}{\b0 \fs18
divider}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 10-23.}{\
b0 \fs18 Use}{\b0 \fs19 two}{\b0 \fs18 7493}{\b0 \fs18 ICs. }
fi954 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs16 10-24b. }\par
}
\cf0 10.53{\b0 Why}{\b0 is}{\b0 the}{\b0 7493}{\b0 IC's}{\b0 \f30 \fs38 a,
}
fi589 {\b0 decade}{\b0 counter}{\b0 uses}{\b0 the}{\b0\i \fs24 Do}{\b0 pin}{
\b0 as}{\b0 the}{\b0 clock}{\b0 input? }

fi951 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs16 10-15a.}{\
b0 \fs17 The}{\b0 \fs17 divide-by-6counter}{\b0 \fs17 uses}{\b0 \fs17 only
}{\b0 \fs17 the}{\b0 \fs17 three}{\i \fs17 JK}{\b0 \fs17 flip-flops}{\b0
\fs17 shown}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17 right}{\b0 \fs17 in }
fi592 {\b0 \fs17 Fig.}{\b0 \fs17 10-15a}{\b0 \fs17 and}{\b0 \fs17 uses}{\b0 \
fs17 the}{\b0\i \fs34 a, }
fi597 {\b0 \fs17 IC}{\b0 \fs17 and}{\b0 \fs17 uses}{\b0 \fs17 the}{\fs23 Go
}{\b0 \fs17 pin}{\b0 \fs17 as}{\b0 \fs17 the}{\b0 \fs17 clock}{\b0 \fs17 i
nput. }
f0 \fi3074 {\b0 \f10 \fs22 SupplementaryProblems }
f0 {\f10 \fs16 10.54}{\b0 \fs17
A}{\b0 \fs17 counter}{\b0 \fs17 that}{\
b0 \fs17 counts}{\b0 \fs17 from}{\b0 \fs17 0}{\b0 \fs17 to}{\b0 \f10 \fs1
6 4}{\b0 \fs17 is}{\b0 \fs17 called}{\b0 \fs17 a}{\b0 \fs17 mod-}{\b0 \fs
17
counter.}{\i \fs17
Ans.}{\b0 \fs17
5 }\par
}
in used as the clock input{\fs18 of} the divide-by-6 counter, whereas the \
par
}
in as the clock input. The decade counter uses{\b \fs16 all} four flip-flopsin
the 7493 \par
}
\cf0 10.55{\b0 \f20 \fs17
Draw}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 logic}{
\b0 \f20 \fs17 diagram}{\b0 \f20 \fs16 of}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17
5-bit}{\b0 \f20 \fs17 ripple}{\b0 \f20 \fs17 up}{\b0 \f20 \fs17 counter}{
\b0 \f20 \fs17 using}{\b0 \f20 \fs17 five}{\i \f20 \fs17 JK}{\b0 \f20 \fs17
flip-flops.}{\f20 \fs16
Am.}{\b0 \f20 \fs17
See}{\b0 \f20 \fs17
Fig.}{\b0 \f20 \fs17 10-27. }\par
}
0 d \par
}
\par
}
\cf0 1 \par
}
\par
}
}
f0 + I *{\i \f20 \fs9
J }\par
}
{\phpg\posx4309\pvpg\posy12551\absw210\absh208 \f10 \fs17 \cf0 \f10 \fs17 \cf0 > \par
}
\fs15 \cf0 FF3

\fs15 CLK }\par
}
\cf0 Q{\i0 \fs27 - }\par
}
lock
5 {\b \fs14 input }\par
}
\cf0 1 K
cf0 \fi21 {\fs16 Fig.}{\fs16 10-27}{\fs16 A}{\b0 \fs17 5-bit}{\b0 \fs17 rip
ple}{\b0 \fs17 up}{\b0 \fs17 counter }\par
}
. 101 \par
}
UNTERS \par
}
\par
}
\cf0 10.56{\b0 \f20 \fs17
The}{\b0 \f20 \fs17 maximum}{\b0 \f20 \fs17 b
inary}{\b0 \f20 \fs17 count}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 a}{\b0 \f20
\fs17 5-bit}{\b0 \f20 \fs17 counter}{\b0 \f20 \fs17 is }
fi605 {\b0 \f20 \fs17 decimals.}{\i \f20 \fs17
Ans.}{\i \f20 \fs16
(}{\i \f20 \fs16 a}{\i \f20 \fs16 )}{\b0 \f20 \fs17
11111}{\i \f20 \fs17
(}{\i \f20 \fs17 6}{\i \f20 \fs17 )}{\b0 \f20 \fs17
31 }
f0 {\fs16 10.57}{\b0 \f20 \fs17
In}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 4-b
it}{\b0 \f20 \fs17 counter,}{\b0 \f20 \fs17 FF4}{\b0 \f20 \fs17 is}{\b0 \f
20 \fs17 usually}{\b0 \f20 \fs17 designated}{\b0 \f20 \fs17 as}{\b0 \f20 \f
s17 the }
fi570 {\i \f20 \fs17 Ans.}{\f20 \fs17
MSB}{\b0 \f20 \fs17 (most}{\b0 \f20
\fs17 significant}{\b0 \f20 \fs17 bit) }\par
}
cf0 ( a ) \par
}
binary number), which equals \par
}
cf0 ( 6 ) \par
}
\par
}
\cf0 (LS13, MSB){\b0 \fs17 counter. }\par
}

\cf0 10.58{\b0 \f20 \fs17
\b0 \f20 \fs17 10-3.}{\b0 \f20 \fs17 On}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
H-to-L}{\b0 \f20 \fs17 transition}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 clo
ck}{\b0 \f20 \fs17 pulse}{\b0 \f20 \fs17 8,}{\b0 \f20 \fs17 how}{\b0 \f20 \
fs17 many}{\b0 \f20 \fs17 flip-flops}{\b0 \f20 \fs17 toggle? }
fi581 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
All}{\b0 \f20 \fs17 four }
f0 10.59{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 Fig.}{\
b0 \f20 \fs17 10-3.On}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 trailing}{\b0 \f
20 \fs17 edge}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 puls
e}{\b0 \f20 \fs17 15,which}{\b0 \f20 \fs17 flip-flop(s)}{\b0 \f20 \fs17 togg
le? }
fi581 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
Only}{\b0 \f20 \fs17 FF1}{\b0 \f2
0 \fs17 toggles. }
f0 10.60{\b0 \f20 \fs17
\b0 \f20 \fs17 10-3.}{\b0 \f20 \fs17 With}{\b0 \f20 \fs17 clock}{\b0 \f20 \
fs17 pulse}{\b0 \f20 \fs17 16}{\b0 \f20 \fs17 HIGH,}{\b0 \f20 \fs17 what}{\
b0 \f20 \fs17 is}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 state}{\b0 \f20 \fs17
of}{\b0 \f20 \fs17 each}{\b0 \f20 \fs17 flip-flop? }
fi581 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
All}{\b0 \f20 \fs17 four}{\b0 \f2
0 \fs17 flip-flops}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17 set}{\b0\i \fs16 (Q}
{\b0 \f20 \fs17 outputs}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17 HIGH). }
f0 10.61{\b0 \f20 \fs17
b0 \f20 \fs17 10-3.After}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 trailing}{\b0
\f20 \fs17 edge}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 p
ulse}{\b0 \f20 \fs17 16,}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 binary}{\b0 \f2
0 \fs17 count}{\b0 \f20 \fs17 is}{\i \fs15
(}{\i \fs15 a}{\i \fs15 )}
{\b0 \f20 \fs17
(binary}{\b0 \f20 \fs17 number) }
fi598 {\b0 \f20 \fs17 and}{\b0 \f20 \fs17 all}{\b0 \f20 \fs17 four}{\b0 \f20
\fs17 flip-flops}{\b0 \f20 \fs17 are}{\b0 \f20 \fs17
(6)}{\b0 \f20 \fs1
7
(reset,set).}{\i \f20 \fs17
Ans.}{\i \f20 \fs16
(}{\i \f20 \
fs16 a}{\i \f20 \fs16 )}{\b0 \f20 \fs17
0000}{\b0\i \f20 \fs16
(b)
}{\b0 \f20 \fs17
r}{\b0 \f20 \fs17
e}{\b0 \f20 \fs17
s}{\b0 \f20 \f
s17
r }
f0 10.62{\b0 \f20 \fs17
\b0 \f20 \fs17 10-3.}{\b0 \f20 \fs17 Which}{\b0 \f20 \fs17 flip-flop}{\b0 \
f20 \fs17 affects}{\b0 \f20 \fs17 FF4}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17
makes}{\b0 \f20 \fs17 it}{\b0 \f20 \fs17 toggle? }
fi933 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
Output}{\i \f30 \fs19 Q}{\b0 \f20
\fs17 of}{\b0 \f20 \fs17 FF3}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 connect
ed}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 CLK}{\b0 \f20 \f
s17 input}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 FF4}{\b0 \f20 \fs17 and}{\b
0 \f20 \fs17 makes}{\b0 \f20 \fs17 it}{\b0 \f20 \fs17 toggle}{\b0 \f20 \fs
17 when}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 pulse }
fi587 {\b0 \f20 \fs17 goes}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 HIGH}{\b0 \f20
\fs17 to}{\b0 \f20 \fs17 LOW. }
f0 \fi29 10.63{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17
Fig.}{\b0 \f20 \fs17 10-5.}{\b0 \f20 \fs17 What}{\b0 \f20 \fs17 is}{\b0 \f2
0 \fs17 the}{\b0 \f20 \fs17 binary}{\b0 \f20 \fs17 count}{\b0 \f20 \fs17 a
fter}{\b0 \f20 \fs17 pulse}{\f30 \fs18 4?}{\i \f20 \fs17

Ans.}{\b0 \f
20 \fs17
100 }
f0 10.64{\b0 \f20 \fs17
b0 \f20 \fs17 10-5.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 output}{\b0 \f20 \fs
16 Q}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 FF2}{\b0 \f20 \fs17 will}{\b0 \f2
0 \fs17 go}{\b0 \f20 \fs17 HIGH}{\b0 \f20 \fs17 again}{\b0 \f20 \fs17 on}{
\b0 \f20 \fs17 the}{\b0 \f20 \fs17 trailing}{\b0 \f20 \fs17 edge}{\b0 \f20
\fs17 of}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 pulse }
fi603 {\b0 \f20 \fs17 (5,}{\b0 \f20 \fs17 6).}{\i \f20 \fs17
Ans.}{\b0
\f20 \fs17
6 }
f0 10.65{\b0 \f20 \fs17
0 \f20 \fs17 10-5.The}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 of}{\b0 \f20 \
fs17 FF1}{\b0 \f20 \fs17 will}{\b0 \f20 \fs17 go}{\b0 \f20 \fs17 HIGH}{\b0
\f20 \fs17 on}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
(leading,}
{\b0 \f20 \fs17 trailing)}{\b0 \f20 \fs17 edge}{\b0 \f20 \fs17 of}{\b0 \f20 \
fs17 clock}{\b0 \f20 \fs17 pulse }
fi603 {\b0 \f20 \fs17 5.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
trail
ing }
f0 10.66{\b0 \f20 \fs17
0 \f20 \fs17 10-5.}{\b0 \f20 \fs17 After}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17
pulse}{\b0 \f20 \fs17 7,}{\b0 \f20 \fs17 FF1}{\b0 \f20 \fs17 is}{\b0 \f20 \
fs17
(reset,}{\b0 \f20 \fs17 set),}{\b0 \f20 \fs17 FF2}{\b0
\f20 \fs17 is}{\b0 \f20 \fs17
(reset,}{\b0 \f20 \fs17 set),}
{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 FF3}{\b0 \f20 \fs17 is }\par
}
reset, set).{\b\i
Ans.}
All the flip-flops are set{\i \f10 \fs15
(Q}{\f10 \fs13 =} 1). \par
}
\cf0 10.67{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 Fig.
}{\b0 \f20 \fs17 10-5.}{\b0 \f20 \fs17 Which}{\b0 \f20 \fs17 flip-flop(s)}{\
b0 \f20 \fs17 toggle}{\b0 \f20 \fs17 on}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
H-to-L}{\b0 \f20 \fs17 transition}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 cloc
k}{\b0 \f20 \fs17 pulse}{\b0 \f20 \fs17 7? }
fi582 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
Only}{\b0 \f20 \fs17 FF1}{\b0 \f2
0 \fs17 toggles. }
f0 {\fs15 10.68}{\b0 \f20 \fs17
Fig.}{\b0 \f20 \fs17 10-5.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 binary}{\b0
\f20 \fs17 count}{\b0 \f20 \fs17 after}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs1
7 pulse}{\b0 \f20 \fs17 9}{\b0 \f20 \fs17 will}{\b0 \f20 \fs17 be}{\b0 \f
s19
.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
001 }
f0 {\fs15 10.69}{\b0 \f20 \fs17
The}{\b0 \f20 \fs17
(para
llel,}{\b0 \f20 \fs17 ripple)}{\b0 \f20 \fs17 counter}{\b0 \f20 \fs17 is}{\
b0 \f20 \fs17 an}{\b0 \f20 \fs17 example}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17
a}{\b0 \f20 \fs17 synchronous}{\b0 \f20 \fs17 device.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
parallel }
f0 {\fs15 10.70}{\b0 \f20 \fs17
Fig.}{\b0 \f20 \fs17 10-7.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 fact}{\b0 \
f20 \fs17 that}{\b0 \f20 \fs17 all}{\b0 \f20 \fs17 flip-flops}{\b0 \f20 \fs1
7 toggle}{\b0 \f20 \fs17 at}{\b0 \f20 \fs17 exactly}{\b0 \f20 \fs17 the}{\b
0 \f20 \fs17 same}{\b0 \f20 \fs17 time}{\b0 \f20 \fs17 (see}{\b0 \f20 \fs17
dashed}{\b0 \f20 \fs17 line)}{\b0 \f20 \fs17 means}{\b0 \f20 \fs17 this }
fi606 {\b0 \f20 \fs17 timing}{\b0 \f20 \fs17 diagram}{\b0 \f20 \fs17 is}{\b0
\f20 \fs17 for}{\b0 \f20 \fs17 a(n)}{\b0 \f20 \fs17
(asynch
ronous,}{\b0 \f20 \fs17 synchronous')counter.}{\i \f20 \fs17
Ans.}{\b0
\f20 \fs17
synchronous }
f0 \fi22 {\fs15 10.71}{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \
fs17 Fig.}{\b0 \f20 \fs17 10-7.}{\b0 \f20 \fs17 When}{\b0 \f20 \fs17 cloc
k}{\b0 \f20 \fs17 pulse}{\b0 \f20 \fs17 6}{\f20 \fs17 is}{\b0 \f20 \fs17
HIGH,}{\b0 \f20 \fs17 FF1}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 in}{\b0 \f20
\fs17 its}{\b0 \f20 \fs17 toggle}{\b0 \f20 \fs17 mode,}{\b0 \f20 \fs17
FF2}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 its}{\b0\i \fs14
(}{\b0\i \fs14
a}{\b0\i \fs14 )}{\b0 \f20 \fs17
(hold, }\par
}
\cf0 toggle) mode, and FF3 in its{\i
(}{\i h}{\i )}
(hold, tog
gle) mode.{\b\i
Ans.}{\b\i \fs16
(}{\b\i \fs16 a}{\b\i \fs16 )}
toggle{\i
(b)}{\fs20 hold }
{\b \f10 \fs15 10.72}
The
(parallel, ripple) counter is
the more complicated device.{\b\i
Ans.}
parallel \par
}
\cf0 10.73{\b0 \f20 \fs17
The}{\b0 \f20 \fs17
basic}{\b0 \f20 \fs17 bu
ilding}{\b0 \f20 \fs17 block}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17
combinat
ional}{\b0 \f20 \fs17
logic}{\b0 \f20 \fs17 circuits}{\b0 \f20 \fs17 is}{
\b0 \f20 \fs17 the}{\b0 \f20 \fs17
gate.}{\b0 \f20 \fs17
The}{\b0 \f20 \
fs17 basic}{\b0 \f20 \fs17 building}{\b0 \f20 \fs17 block}{\b0 \f20 \fs17
for }
fi592 {\b0 \f20 \fs17 sequential}{\b0 \f20 \fs17 logic}{\b0 \f20 \fs17 circui
ts}{\f20 \fs16 is}{\b0 \f20 \fs17 the}{\b0 \fs19
.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
flip-flop }\par
}
\par
}
UNTERS \par
}
AP.{\fs16 10 }\par
}
f0 10.74 \par
}
efer to Fig. 10-28. The clear (or reset) input on the counter{\fs17 i
s} activated by a \par
}
HIGH,{\fs17 LOW). }\par
}
\f20 \fs17 \cf0 Ans.{\b0\i0 \fs17
The}{\b0\i0 \fs17 clear}{\b0\i0 \fs17 i
nput}{\b0\i0 \fs17 on}{\b0\i0 \fs17 the}{\b0\i0 \fs17 counter}{\b0\i0 \fs17
shown}{\b0\i0 \fs17 in}{\b0\i0 \fs17 Fig.}{\b0\i0 \fs17 10-28}{\b0\i0 \fs

17 is}{\b0\i0 \fs17 activated}{\b0\i0 \fs17 by}{\b0\i0 \fs17 a}{\b0\i0 \fs1
7 LOW,}{\b0\i0 \fs17 or}{\b0\i0 \fs17 logical}{\b0\i0 0.}{\b0\i0 \fs17 Thi
s}{\i0 is }
{\b0\i0 \fs17 symbolized}{\b0\i0 \fs17 by}{\b0\i0 \fs17 the}{\b0\i0 \fs17
small}{\b0\i0 \fs17 bubble}{\b0\i0 \fs17 at}{\b0\i0 \fs17 the}{\b0\i0 \fs17
clear}{\b0\i0 \fs17 input. }\par
}
nary{\fs15 output }\par
}
cf0 Clock \par
}
+ \par
}
cf0 Clear \par
}
unter
{\b \fs15 CLK }\par
}
cf0 QD
fs15 Qc }
0 {\b \fs9 QB }\par
}
par
}
par
}
par
}
par
}
\par
}
\par
}
par
}
par
}
par
}

par
}
{\b \f20 \fs15 CLR}{\b\i \fs8
QA }\par
}
5 \cf0 (Reset)
{\b \fs16 Fig.}{\b \fs17 10-28}{\fs17 Counter}{\fs17 pulse-train}{\fs17 pro
blem }\par
}
f0 10.75 \par
}
ist the binary output after each{\fs17 of} the clock pulses for the de
cade up counter shown in Fig. 10-28. \par
}
s17 \cf0 Ans.{\b0\i0 \fs17
pulse}{\fs16 a}{\b0\i0 \f10 \fs14 =}{\b0\i0 \f
s17 0000 }
0001 }\par
}
ulse{\b \f10 \fs13 c}{\f10 \fs13 =} 0010
e{\fs16 d}{\f10 \fs13 =} 0011 \par
}
ulse{\fs17 e}{\dn006 \f10 \fs11 =}{\fs17 0100 }
e{\i \f30 \fs19 f}{\dn006 \f10 \fs11 =} 0101 \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 0110
e{\i \fs16 h}{\dn006 \f10 \fs11 =} 0111 \par
}
ulse{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =} 1000
e{\fs15 j}{\f10 \fs13 =} 1001 \par
}
cf0 10.76{\b0 \fs17
Assume}{\b0 \fs17 the}{\b0 \fs17 counter}{\b0 \fs17
shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 10-28is} a{\b0 \fs17 mod-16}{
\b0 \fs17 down}{\b0 \fs17 counter.}{\b0 \fs17 List}{\b0 \fs17 the}{\b0 \fs1
7 binary}{\b0 \fs17 output}{\b0 \fs17 after}{\b0 \fs17 each}{\b0 \fs17 cloc
k }
i589 {\b0 \fs17 pulse. }\par
}
s17 \cf0 Ans.{\b0\i0 \fs17
pulse}{\b0 \f10 \fs14 a}{\b0\i0 \f10 \fs13 =}
{\b0\i0 0000 }
1111 }\par
}
ulse{\i \f10 \fs15 c}{\dn006 \f10 \fs11 =} 1110
e{\fs16 d}{\f10 \fs13 =} 1101 \par
}
ulse{\fs16 e}{\f10 \fs13 =} 1100
e{\fs17 f}{\fs17 =}{\fs16 1011 }\par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 1010
e{\i \fs16 h}{\dn006 \f10 \fs11 =} 1001 \par
}
ulse{\b\i \f30 \fs18 i}{\dn006 \f10 \fs11 =}{\fs17 1000 }
e{\fs14 j}{\dn006 \f10 \fs11 =} 0111 \par
}
cf0 10.77{\b0 \f20 \fs17
Draw}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 logic}{
mod-12}{\b0 \f20 \fs17 ripple}{\b0 \f20 \fs17 up}{\b0 \f20 \fs17 counter}
{\b0 \f20 \fs17 by}{\b0 \f20 \fs17 using}{\b0 \f20 \fs17 four}{\i \f20 \fs1
7 JK}{\b0 \f20 \fs17 flip-flops}{\b0 \f20 \fs17 (with}{\b0 \f20 \fs17 clea
r}{\b0 \f20 \fs17 inputs)}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 a }
i594 {\b0 \f20 \fs17 2-input}{\b0 \f20 \fs17 NAND}{\b0 \f20 \fs17 gate.}{\i \
f20 \fs16
Ans.}{\b0 \f20 \fs17
See}{\b0 \f20 \fs17 Fig.}{\b0 \f2
0 \fs17 10-29. }\par
}
0 t,J \par
}
\cf0 - 1 1 \par
}
{\b \f20 \fs15
K'CLR }\par
}
\cf0 Fig.{\f10 \fs15 10-29}{\b0 \fs17
Mod-12}{\b0 \fs17 ripple}{\fs16 up}
{\b0 \fs17 counter }\par
}
}
cf0 1 \par
}
cf0 1 \par
}
5 \cf0 ,
\fi323 {\i \f20 \fs8 J }

447 {\b \f20 \fs15 FF4 }
20 \fs15 'w>}{\b \f20 \fs15 CLK }
\fi136 {\fs13 1}{\b \f20 \fs15
KCLR }\par
}
\cf0 Q \par
}
\cf0 P \par
}
inary{\fs15 output }\par
}
0 1 \par
}
0 1 \par
}
s15 \cf0 J \par
}
\cf0 Q--( \par
}
-I \par
}
\cf0 Clock
fi21 {\fs14 input }\par
}
\fs15 \cf0 FF2
\b0\dn006 \f10 \fs10 -C>}{\fs15 CLK }
f0 \fi80 {\f10 \fs13 1}{\fs15
KCLR }\par
}
eset \par
}
. 101 \par
}
UNTERS \par
}
\par
}
cf0 10.78{\b0 \fs17
Draw}{\b0 \fs17 a}{\b0 \fs17 logic}{\b0 \fs17 diagram
}{\b0 \fs17 for}{\b0 \fs17 a}{\b0 \fs17 divide-by-5ripple}{\b0 \fs17 counter
}{\b0 \fs17 by}{\b0 \fs17 using}{\b0 \fs17 three}{\i \fs17 JK}{\b0 \fs17 f
lip-flops}{\b0 \fs17 (with}{\b0 \fs17 clear}{\b0 \fs17 inputs)}{\b0 \fs17 an
d}{\b0 \fs17 a }
i590 {\b0 \fs17 2-input}{\b0 \fs17 NAND}{\b0 \fs17 gate.}{\b0 \fs17 Show}{
\b0 \fs17 clock}{\b0 \fs17 input}{\b0 \fs17 and}{\b0 \fs17 only}{\b0 \fs1
7 the}{\b0 \fs17 divide-by5}{\b0 \fs17 output.}{\fs17
Am.}{\b0 \fs1
7
See}{\b0 \fs17 Fig.}{\b0 \fs17 10-30. }\par
}
\par
}
cf0 Q \par
}
\par
}
\par
}
{\phpg\posx3214\pvpg\posy2494\absw73\absh168 \f20 \fs15 \cf0 \f20 \fs15 \cf0 J \
par
}
cf0 Q - \par
}
par
}
{\phpg\posx4557\pvpg\posy2513\absw73\absh162 \f20 \fs14 \cf0 \f20 \fs14 \cf0 J \
par
}
cf0 Clock
i23 {\fs14 input }\par
}
\fs15 \cf0 FF{\b0 \fs14 1 }
fs15 CLK }\par
}
cf0 FF2 \par
}
vide-by-5
6 {\fs15 output }\par
}
cf0 't--a>{\b0 \f20 \fs15 CLK }
0 \fi216 {\f10 \fs13 1}{\b0 \f20 \fs15
KCLR }\par
}
\fs15
KCLR }\par
}
set \par
}
\cf0 Fig.{\fs17 10-30}{\b0 \fs17
Divide-by-5ripple}{\b0 \fs17 counter }\par
}
f0 10.79 \par
}
efer to Fig. 10-31.The clear (CLR) input to the 74192 counter IC{\fs17
is} an active
t.{\b\i
Ans.}
HIGH \par
}
HIGH, LOW) \par
}
. m J + - ' \par
}
{\phpg\posx6477\pvpg\posy8699\absw454\absh178 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Do
wn \par
}
7-r \par
}
\par
}
fs15 \cf0 CLK
\par}{\phpg\posx6967\pvpg\posy8803\absw887\absh653 \sl-287 \b \f20 \fs15 \cf0 CL
R
i270 {\fs15 (74192) }\par
}
cf0 D--{\f20 \fs15 Borrow }
f20 \fs15 *Carry }\par
}
\cf0 Fig.{\fs17 10-31}{\b0 \fs17
Counter}{\b0 \fs17 pulse-train}{\b0 \fs17
problem }\par
}
\cf0 10.80{\b0 \fs17
List}{\b0 \fs17 the}{\b0 \fs17 BCD}{\b0 \fs17 out
puts}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 74192}{\b0 \fs17 IC}{\b0 \fs
17 counter}{\b0 \fs17 after}{\b0 \fs17 each}{\b0 \fs17 of}{\b0 \fs17 t
he}{\b0 \fs17 input}{\b0 \fs17 clock}{\b0 \fs17 pulses}{\b0 \fs17 shown}{
\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 10-31. }\par
}
pulse}{\fs16 a}{\b0\i0 \f10 \fs13 =}{\b0\i0
\fs17 0000}{\b0\i0 \fs17 (clear) }
0 \fi531 {\b0\i0 \fs17 pulse}{\b0 \fs16 b}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17
1001 }
0 \fi531 {\b0\i0 \fs17 pulse}{\fs16 c}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs17 100
0 }
0 \fi532 {\b0\i0 \fs17 pulse}{\b0 \f10 \fs15 d}{\b0\i0 \f10 \fs13 =}{\b0\i0 \
fs17 0111 }
0 \fi528 {\b0\i0 \fs17 pulse}{\b0\i0 \fs16 e}{\b0\i0 \f10 \fs13 =}{\b0\i0 \fs
17 0011}{\b0\i0 \fs17 (load) }\par
}
pulse{\i \f30 \fs19 f=} 0100
se{\fs15 g}{\f10 \fs13 =} 0101
se{\b\i h}{\f10 \fs13 =} 0110
se{\b\i \f30 \fs18 i}{\dn006 \f10 \fs11 =} 0111 \par
}
pulse{\i \f10 \fs15 j}{\f10 \fs13 =}{\fs17 1000 }
se{\b\i k}{\f10 \fs13 =} 0000 (clear)
se{\i \f10 \fs16 1}{\f10 \fs13 =} 0001
se{\b\i \f30 rn}{\f10 \fs13 =} 0010 \par
}
cf0 10.81 \par
}
Refer to Fig. 10-32.List the binary outputs of the 7493 counter IC after
each clock pulse. \par
}
\cf0 Ans.{\i0
pulse}{\b \fs16 a}{\i0 \f10 \fs13 =}{\i0 000}{\i0 (res
et) }
\fi533 {\i0 pulse}{\fs16 b}{\i0 \f10 \fs13 =}{\i0 \fs17 001}{\i0 (count}{\i
0 up) }
\fi535 {\i0 pulse}{\f10 \fs14 c}{\i0\dn006 \f10 \fs11 =}{\i0 010}{\i0 (cou
nt}{\i0 up) }\par
}
pulse{\b\i \fs17 d}{\f10 \fs13 =} 011 (count up)
se{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 100 (count up)
se{\fs17 f}{\f10 \fs13 =} 101(count up) \par
}
pulse{\i \f10 \fs14 g}{\f10 \fs13 =} 110 (count up)
se{\b\i h}{\f10 \fs13 =} 111(count up)
se{\b\i \f30 \fs18 i}{\f10 \fs13 =}{\fs17 000} (count up) \par
}
\par
}
UNTERS \par
}
AP. 10 \par
}
cf0 vcc \par
}
ock \par
}
\cf0 \par}{\phpg\posx6007\pvpg\posy2293\absw503\absh351 \sl-191 \f10 \fs15 \cf0 {\b \
f20 \fs14 G>CPl }\par
}
\par
}
}
cf0 7493{\i \fs11
Q}{\i \fs11 2}{\i \fs11 - }\par
}
\cf0 Fig.{\fs17 10-32}{\b0 \fs17
Counter}{\b0 \fs17 pulse-train}{\b0 \fs17
problem }\par
}
cf0 10.82{\b0 \f20 \fs17
The}{\b0 \f20 \fs17 7493}{\b0 \f20 \fs17 IC}{\b
0 \f20 \fs17 detailed}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs
17 10-32}{\f20 \fs17 is}{\b0 \f20 \fs17 wired}{\b0 \f20 \fs17 as}{\b0 \f20
\fs17 a}{\b0 \f20 \fs17 mod- }\par
}
cf0 10.83{\b0
The}{\b0 7493}{\b0 IC}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0
10-32is}{\b0 in}{\b0 the }
i568 {\i \fs16 Ans.}{\b0
reset}{\b0 (or}{\b0 clear) }\par
}
{\phpg\posx6381\pvpg\posy5129\absw897\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 up
counter. \par
}
mod-8 }\par
}
ode{\fs16 of} operation during clock pulse{\b\i \fs17 a. }\par
}
cf0 10.84{\b0 \f20 \fs17
\b0 \f20 \fs17 10-18.The}{\b0 \f20 \fs17 74HC393}{\b0 \f20 \fs17 IC}{\b0 \f20
\fs17 is}{\b0 \f20 \fs17 described}{\b0 \f20 \fs17 by}{\b0 \f20 \fs17 the}{
\b0 \f20 \fs17 manufacturer}{\b0 \f20 \fs17 as}{\b0 \f20 \fs17 a}{\b0 \f20
\fs17 CMOS}{\b0 \f20 \fs17 dual }
i589 {\b0 \f20 \fs17 4-bit}{\b0 \f20 \fs17 binary)}{\b0 \f20 \fs17 counter.}{\
i \f20 \fs17
Ans.}{\b0 \f20 \fs17
4-bit}{\b0 \f20 \fs17 binary }\p
ar
}
cf0 10.85{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 10-18.The}{\b0 74HC393}{\
b0 IC}{\fs16 is}{\b0 a}{\b0
(ripple,}{\b0 synchronous)}
{\b0 counter. }\par
}
cf0 10.86{\b0 \f20 \fs17
\b0 \f20 \fs17 10-33.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 74HC393}{\b0 \f20 \f
s17 IC}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 wired}{\b0 \f20 \fs17 as}{\b0 \f2
0 \fs17 a}{\b0 \f20 \fs17 mod- }
i570 {\i \f20 \fs16 Ans.}{\b0 \f20 \fs17
8 }\par
}
ecade, \par
}
16 \cf0 Ans.{\b0\i0 \fs17
ripple }\par
}
decimal number) counter in this circuit. \par
}
nary output \par
}
\fs16 \cf0 vcc
0 {\i0 \fs15 Counter }\par
}
10 \cf0 123 \par
}
ock input \par
}
- \par
}
cf0 122 \par
}
\cf0 \par}{\phpg\posx4493\pvpg\posy9811\absw531\absh340 \sl-155 \f10 \fs19 \cf0 {\i \
fs15 c>}{\b\i \f20 \fs15 CP }\par
}
\cf0 Ql
f0 {\i \fs15 Qo }\par
}
{\phpg\posx6389\pvpg\posy10414\absw40\absh113 \f10 \fs9 \cf0 \f10 \fs9 \cf0 . \p
ar
}
\cf0 Fig.{\fs17 10-33 }\par

}
\cf0 10.87{\b0 \f20 \fs17
}{\f20 \fs17 10-33.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 circuit}{\b0 \f20 \
fs17 counts}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 low}{
\b0 \f20 \fs17 of}{\b0 \f20 \fs17 binary}{\b0 \f20 \fs17 0000}{\b0 \f20 \f
s17 to}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 high}{\b0 \f20 \fs17 of }\par
}
\par
}
s17 \cf0 Ans.{\b0\i0 \fs17
0111 }\par
}
\cf0 10.88{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs16 to}{\b0 \f20 \fs17 Fig.}
{\b0 \f20 \fs17 10-19.On}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 74HC193}{\b0 \
f20 \fs17 IC,}{\b0 \f20 \fs17 if}{\b0 \f20 \fs17 both}{\b0 \f20 \fs17 the}
{\b0 \f20 \fs17 reset}{\i \f20 \fs17 (MR)}{\b0 \f20 \fs17 and}{\b0 \f20 \fs1
7 parallel}{\b0 \f20 \fs17 load}{\i \f20 \fs22 (E)}{\b0 \f20 \fs17 pins}{\b0
\f20 \fs17 are}{\b0 \f20 \fs17 activated }
fi594 {\b0 \f20 \fs17 at}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 same}{\b0 \f20
\fs17 time,}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
input}{\f
20 \fs17 will}{\b0 \f20 \fs17 override}{\b0 \f20 \fs16 all}{\b0 \f20 \fs17
others.}{\i \f20 \fs16
Ans.}{\b0 \f20 \fs17
reset}{\i \f20 \fs17
(MR) }\par
}
. 101 \par
}
UNTERS \par
}
\par
}
\cf0 10.89{\b0 \f20 \fs17
{\b0 \f20 \fs17 10-34.}{\b0 \f20 \fs17 What}{\b0 \f20 \fs17 is}{\b0 \f20 \f
s17 the}{\b0 \f20 \fs17 mode}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 operation}
{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 74HC193}{\b0 \f20 \
fs17 counter}{\b0 \f20 \fs17 during}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17
pulse}{\b0 \f20 \fs17 a? }
fi566 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
parallel}{\b0 \f20 \fs17 load }
f0 {\fs16 10.90}{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\f20 \fs17 Fig
.}{\b0 \f20 \fs17 10-34.}{\b0 \f20 \fs17 What}{\b0 \f20 \fs17 is}{\b0 \f20 \
fs17 the}{\b0 \f20 \fs17 mode}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 operatio
n}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 74HC193}{\b0 \f2
0 \fs17 counter}{\b0 \f20 \fs17 during}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs1
7 pulse}{\i \f20 \fs17 b? }
fi564 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
count}{\b0 \f20 \fs17 down }
f0 10.91{\b0 \f20 \fs17
b0 \f20 \fs17 10-34.What}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 the}{\b0 \f20 \
fs17 mode}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 operation}{\b0 \f20 \fs17 f
or}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 74HC193}{\b0 \f20 \fs17 counter}{\b0
\f20 \fs17 during}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 pulse}{\b0 \f20 \fs
17 f}{\b0 \f20 \fs17 ? }
fi570 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
reset}{\b0 \f20 \fs17 (or}{\b0 \
f20 \fs17 clear) }\par
}
14 \cf0 +5{\b0\i0 \f20 \fs22 v }\par
}
\par
}
15 \cf0 vcc \par
}
\cf0 Binary output \par
}
}
\fs14 1 }
\b \fs15 0 }\par
}
cf0 Inputs
0 \fi180 {\fs15 1 }\par
}
f0 1 \par
}
\par
}
t \par
}
cf0 0 \par
}
cf0 Q3 \par
}
10 \cf0 D3
{\fs15 D2 }
{\i0 \fs16 Dl }\par
}
11 \cf0 Q2 \par
}

cf0 Counter \par
}
{\phpg\posx7195\pvpg\posy5267\absw210\absh200 \f10 \fs17 \cf0 \f10 \fs17 \cf0 Qi
\par
}
par
}
cf0 Fig.{\f10 \fs15 10-34 }\par
}
\cf0 10.92{\b0 \f20 \fs17
{\b0 \f20 \fs17 10-34.}{\b0 \f20 \fs17 List}{\b0 \f20 \fs17 the}{\b0 \f20 \fs
17 binary}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17 after}{\b0 \f20 \fs17 each}
{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs
17 pulses}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 74HC193cou
nter}{\b0 \f20 \fs17 circuit. }
fi562 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
pulse}{\i \f20 \fs16 a}{\b0 \fs1
3 =}{\b0 \f20 \fs17 1101 }
fi1094 {\b0 \f20 \fs17 pulse}{\b0\i \fs16 h}{\b0 \fs13 =}{\b0 \f20 \fs17 110
0 }
fi1102 {\b0 \f20 \fs17 pulse}{\b0\i \fs14 c}{\b0\dn006 \fs11 =}{\b0 \f20 \fs
17 1011 }
fi1095 {\b0 \f20 \fs17 pulse}{\b0\i \fs16 d}{\b0\i \fs16 =}{\b0 \f20 \fs17
1010 }
fi1102 {\b0 \f20 \fs17 pulse}{\i \f20 \fs16 e}{\b0 \fs13 =}{\b0 \f20 \fs17 1
001 }
fi1094 {\b0 \f20 \fs17 pulse}{\b0\i \fs16 f}{\b0\i \fs16 =}{\b0 \f20 \fs17 0
000 }
f0 10.93{\b0 \f20 \fs17
\b0 \f20 \fs17 10-2.}{\b0 \f20 \fs17 If}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17
frequency}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 clock}
{\b0 \f20 \fs17 input}{\b0 \f20 \fs17 were}{\b0 \f20 \fs17 1}{\b0 \f20 \fs
17 MHz,}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 frequency}{\b0 \f20 \fs17 at}
{\b0 \f20 \fs17 output}{\i \fs16 A}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 FF
1 }
fi586 {\b0 \f20 \fs17 would}{\b0 \f20 \fs17 be}{\b0 \fs22
.}{\i \f2
0 \fs17
Ans.}{\b0 \f20 \fs17
500}{\b0 \f20 \fs17 kHz,}{\b0 \f20 \f
s17 or}{\b0 \f20 \fs17 0.5}{\b0 \f20 \fs17 MHz }
0.94{\b0 \f20 \fs17
Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 Fig.}{\f20
\fs16 10-2.}{\b0 \f20 \fs17 If}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 frequ
ency}{\b0 \f20 \fs16 of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 clock}{\b0 \f2
0 \fs17 input}{\b0 \f20 \fs17 were}{\b0 \f20 \fs17 1}{\b0 \f20 \fs17 MHz,
}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 frequency}{\b0 \f20 \fs17 at}{\b0 \f2
0 \fs17 output}{\i \f30 \fs19 C}{\f20 \fs17 of}{\f20 \fs17 FF3 }
fi584 {\b0 \f20 \fs17 would}{\b0 \f20 \fs17 be}{\b0 \fs19
.}{\i \f
20 \fs17
Ans.}{\b0 \f20 \fs17
125}{\b0 \f20 \fs17 kHz }\par
}

\cf0 10.95{\b0 \f20 \fs17
{\b0 \f20 \fs17 10-23.Digital}{\b0 \f20 \fs17 devices}{\b0 \f20 \fs17 called
}
fi589 {\b0 \f20 \fs17 digital}{\b0 \f20 \fs17 clock.}{\i \f20 \fs17
An
s.}{\b0 \f20 \fs17
counters,}{\b0 \f20 \fs17 or}{\b0 \f20 \fs17 counter}{
\b0 \f20 \fs17 ICs }
f0 10.96{\b0 \f20 \fs17
b0 \f20 \fs17 10-23.}{\b0 \f20 \fs17 Digital}{\b0 \f20 \fs17 devices}{\b0 \f
20 \fs17 called }
fi585 {\b0 \f20 \fs17 digital}{\b0 \f20 \fs17 clock.}{\i \f20 \fs17
An
s.}{\b0 \f20 \fs17
counters,}{\b0 \f20 \fs17 or}{\b0 \f20 \fs17 counter}{
\b0 \f20 \fs17 ICs }\par
}
are used to implement the divide-by-60circuits in this
\fi22 are used to implement the count accumulators in this \par
}
\cf0 10.97{\b0 \f20 \fs17
}{\b0 \f20 \fs17 10-24a.}{\b0 \f20 \fs17 If}{\b0 \f20 \fs17 the}{\b0 \f20
\fs17 input}{\b0 \f20 \fs17 frequency}{\b0 \f20 \fs17 on}{\b0 \f20 \fs17
the}{\b0 \f20 \fs17 left}{\b0 \f20 \fs17 were}{\b0 \f20 \fs17 600}{\b0 \f
20 \fs17 kHz,}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 output}{\b0 \f20 \fs17
frequency}{\b0 \f20 \fs17 would}{\b0 \f20 \fs17 be }
fi1214 {\b0 \fs19 .}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
10}{\b0 \f2
0 \fs17 kHz. }\par
}
apter{\fs52 11 }\par
}
0 \fs32 \cf0 hift{\fs33 Registers }
2 \cf0 {\f20 \fs18 11-1}{\f20 \fs18
INTRODUCTION }
fi356 {\b0 \f20 \fs18 The}{\b0\i \f20 \fs18 shift}{\b0\i \f20 \fs18 register}{
\b0 \f20 \fs18 is}{\b0 \f20 \fs18 one}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 th
e}{\b0 \f20 \fs18 most}{\b0 \f20 \fs18 widely}{\b0 \f20 \fs18 used}{\b0 \f20
\fs18 functional}{\b0 \f20 \fs18 devices}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18
digital}{\b0 \f20 \fs18 systems.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 simple
}
\b0 \f20 \fs18 pocket}{\b0 \f20 \fs18 calculator}{\b0 \f20 \fs18 illustrates
}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 shift}{\b0 \f20 \fs18 register's}{\b0
\f20 \fs18 characteristics.}{\b0 \f20 \fs18 To}{\b0 \f20 \fs18 enter}{\b0
\f20 \fs18 the}{\b0 \f20 \fs18 number}{\b0 \f20 \fs18 246}{\b0 \f20 \fs18
on}{\b0 \f20 \fs18 the }
\b0 \f20 \fs18 calculator,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 2}{\b0 \f20 \
fs18 key}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 depressed}{\b0 \f20 \fs18 and
}{\b0 \f20 \fs18 released.}{\f20 \fs18 A}{\b0 \f20 \fs18 2}{\b0 \f20 \fs18
is}{\b0 \f20 \fs18 displayed.}{\b0 \f20 \fs18 Next}{\b0 \f20 \fs18 the}{
\b0 \f20 \fs18 4}{\b0 \f20 \fs18 key}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18
depressed}{\b0 \f20 \fs18 and }
\b0 \f20 \fs18 released.}{\f20 \fs18 A}{\b0 \f20 \fs18 24}{\b0 \f20 \fs18 is}
{\b0 \f20 \fs18 displayed.}{\b0 \f20 \fs18 Finally,}{\b0 \f20 \fs18 the}{\b0
\f20 \fs18 6}{\b0 \f20 \fs18 key}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 depresse
d}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 released.}{\b0 \f20 \fs18 The}{\b0 \f20
\fs18 number}{\b0 \f20 \fs18 246}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 display
ed. }
\b0 \f20 \fs18 On}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 typical}{\b0 \f20 \fs18 c
alculator,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 2}{\b0 \f20 \fs18 is}{\b0 \f
20 \fs18 first}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the
}{\b0 \f20 \fs18 right}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 the}{\b0 \f20 \fs1
8 display.}{\b0 \f20 \fs18 When}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 4}{\b0
\f20 \fs18 key}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 depressed, }
\b0 \f20 \fs18 the}{\b0 \f20 \fs19 2}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 shift
ed}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 left}{\b0 \f20 \fs1
8 to}{\b0 \f20 \fs18 make}{\b0 \f20 \fs18 room}{\b0 \f20 \fs18 for}{\b0 \f20
\fs18 the}{\b0 \f20 \fs18 4.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 numbers}{\
b0 \f20 \fs18 are}{\b0 \f20 \fs18 progressively}{\b0 \f20 \fs18 shifted}{\b0
\f20 \fs18 to}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 left}{\b0 \f20 \fs18 on }
\b0 \f20 \fs18 the}{\b0 \f20 \fs18 display.}{\b0 \f20 \fs18 This}{\b0 \f20 \fs
18 register}{\b0 \f20 \fs18 operates}{\b0 \f20 \fs19 as}{\b0 \f20 \fs18 a}{
\b0 \f20 \fs18 shift-left}{\b0 \f20 \fs18 register. }
fi366 {\b0 \f20 \fs18 Besides}{\b0 \f20 \fs18 the}{\b0\i \f20 \fs18 shifting}{
\b0\i \f20 \fs18 characteristic,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 calculat
or}{\b0 \f20 \fs18 also}{\b0 \f20 \fs18 exhibits}{\b0 \f20 \fs18 a}{\b0\i \f
20 \fs18 memory}{\b0\i \f20 \fs18 characteristic.}{\b0 \f20 \fs18 The}{\b0 \
f20 \fs18 proper }
\b0 \f20 \fs18 calculator}{\b0 \f20 \fs18 key}{\b0 \f20 \fs18 (such}{\b0 \f20
\fs18 as}{\b0 \f20 \fs19 2)}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 depressed}{
\b0 \f20 \fs18 and}{\b0 \f20 \fs18 released,}{\b0 \f20 \fs18 but}{\b0 \f20
\fs18 the}{\b0 \f20 \fs18 number}{\b0 \f20 \fs18 still}{\b0 \f20 \fs18 s
hows}{\b0 \f20 \fs18 on}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 display.}{\b0 \
f20 \fs18 The }
\b0 \f20 \fs18 register}{\b0 \f20 \fs18 "remembers"}{\b0 \f20 \fs18 which}{\b
0 \f20 \fs18 key}{\b0 \f20 \fs18 was}{\b0 \f20 \fs18 pressed.}{\b0 \f20 \fs1
8 This}{\b0 \f20 \fs18 temporary}{\b0 \f20 \fs18 memory}{\b0 \f20 \fs18 cha
racteristic}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 vital}{\b0 \f20 \fs18 in}{\b
0 \f20 \fs18 many }
\b0 \f20 \fs18 digita1}{\b0 \f20 \fs18 circuits. }
fi366 {\b0 \f20 \fs18 Shift}{\b0 \f20 \fs18 registers}{\b0 \f20 \fs18 are}{\
b0 \f20 \fs18 classed}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 sequential}{\b0 \
f20 \fs18 logic}{\b0 \f20 \fs18 circuits,}{\b0 \f20 \fs18 and}{\b0 \f20 \f
s18 as}{\b0 \f20 \fs18 such}{\b0 \f20 \fs18 they}{\b0 \f20 \fs18 are}{\b
0 \f20 \fs18 constructed}{\b0 \f20 \fs18 from }
\b0 \f20 \fs18 flip-flops.}{\b0 \f20 \fs18 Shift}{\b0 \f20 \fs18 registers}{\b
0 \f20 \fs18 are}{\b0 \f20 \fs18 used}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 tem
porary}{\b0 \f20 \fs18 memories}{\b0 \f20 \fs18 and}{\b0 \f20 \fs18 for}{\b0
\f20 \fs18 shifting}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18
the}{\b0 \f20 \fs18 left}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 right.}{\b0 \f20
\fs18 Shift }
\b0 \f20 \fs18 registers}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 also}{\b0 \f20 \
fs18 used}{\b0 \f20 \fs18 for}{\b0 \f20 \fs18 changing}{\b0 \f20 \fs18 seria
l}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 parallel}{\b0 \f20 \fs18 data}{\b0 \f20
\fs18 or}{\b0 \f20 \fs18 parallel}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 seria
l}{\b0 \f20 \fs18 data. }
fi371 {\b0 \f20 \fs18 One}{\b0 \f20 \fs18 method}{\b0 \f20 \fs18 of}{\b0 \f20
\fs18 identifVing}{\b0 \f20 \fs18 shift}{\b0 \f20 \fs18 registers}{\b0 \f20
\fs18 is}{\b0 \f20 \fs18 by}{\b0 \f20 \fs18 how}{\b0 \f20 \fs18 data}{\b0 \
f20 \fs18 is}{\b0\i \f20 \fs18 loaded}{\b0\i \f20 \fs18 into}{\b0 \f20 \fs18
and}{\b0\i \f20 \fs18 read}{\i \f30 \fs18 from}{\b0 \f20 \fs18 the}{\b0 \f
20 \fs18 storage }
\b0 \f20 \fs18 units.}{\b0 \f20 \fs18 Figure}{\b0 \f20 \fs18 11-1}{\b0 \f20 \
fs18 is}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 register}{\b0 \f20 \fs19 8}{\b0 \f
20 \fs18 bits}{\b0 \f20 \fs18 wide.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 regi
sters}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 11-1}{\b0 \f2
0 \fs18 are}{\b0 \f20 \fs18 classified}{\b0 \f20 \fs18 as: }
f0 \fi378 {\b0 \f20 \fs18 1.}{\b0 \f20 \fs18
Serial-in}{\b0 \f20 \fs18 seria
l-out}{\b0 \f20 \fs18 (Fig.}{\b0 \f20 \fs18 11-la) }
fi366 {\b0 \f20 \fs19 2.}{\b0 \f20 \fs18
Serial-in}{\b0 \f20 \fs18 parallel
-out}{\b0 \f20 \fs18 (Fig.}{\b0 \f20 \fs18 11-lb) }
fi372 {\b0 \f20 \fs19 3.}{\b0 \f20 \fs18
Parallel-in}{\b0 \f20 \fs18 seria
l-out}{\b0 \f20 \fs18 (Fig.}{\b0\i \f20 \fs18 11-lc) }
fi372 {\b0 \f20 \fs18 4.}{\b0 \f20 \fs18
Parallel-in}{\b0 \f20 \fs18 paral
lel-out}{\b0 \f20 \fs18 (Fig.}{\b0 \f20 \fs18 11-ld) }
f0 \fi372 {\b0 \f20 \fs18 The}{\b0 \f20 \fs18 diagrams}{\b0 \f20 \fs18 in}{\b0
\f20 \fs18 Fig.}{\b0 \f20 \fs18 11-1}{\b0 \f20 \fs18 illustrate}{\b0 \f20 \f
s18 the}{\b0 \f20 \fs18 idea}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 each}{\b0 \f
20 \fs18 type}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 register. }\par
}
\cf0 Fig.{\f10 \fs15 11-1}{\b0 \fs16 Types}{\b0 \fs16 of}{\b0 \fs16 shif
t}{\b0 \fs16 registers }
cf0 \fi1163 {\b0 \fs18 260 }\par
}
.{\fs16 111 }\par
}
{\phpg\posx4449\pvpg\posy561\absw1637\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 SH
IFT REGISTERS \par
}
\par
}
\cf0 11-2{\fs18
S}{\fs18 E}{\fs18 W}{\fs18 -}{\fs18 L}{\fs18 O}{\fs18
A}{\fs18 D}{\fs18 SHIFT}{\fs18 REGISTER }
fi358 {\fs18 A}{\b0 \fs18 simple}{\b0 \fs18 4-bit}{\b0 \fs18 shift}{\b0 \fs1
8 register}{\b0 \fs18 is}{\b0 \fs18 illustrated}{\b0 \fs18 in}{\b0 \fs18

Fig.}{\b0 \fs18 11-2.}{\b0 \fs18 Note}{\b0 \fs18 the}{\b0 \fs18 use}{\b0 \f
s18 of}{\b0 \fs18 four}{\b0\i \fs18 D}{\b0 \fs18 flip-flops.}{\b0 \fs18 Da
ta}{\b0 \fs18 bits }
\b0 \fs19 (OS}{\b0 \fs18 and}{\b0 \fs18 1s)}{\b0 \fs18 are}{\b0 \fs18 fed}
{\b0 \fs18 into}{\b0 \fs18 the}{\b0\i \fs19 D}{\b0 \fs18 input}{\b0 \fs18
of}{\b0 FF1.}{\b0 \fs18 This}{\b0 \fs18 input}{\b0 \fs18 is}{\b0 \fs18 l
abeled}{\b0 \fs18 as}{\b0 \fs18 the}{\b0 \fs18 serial-data}{\b0 \fs18 input
.}{\b0 \fs18 The}{\b0 \fs18 clear }
\b0 \fs18 input}{\b0 \fs18 will}{\b0 \fs18 reset}{\b0 \fs18 all}{\b0 \fs18
four}{\b0 \fs18 flip-flops}{\b0 \fs18 to}{\b0 0}{\b0 \fs18 when}{\b0 \fs18
activated}{\b0 \fs18 by}{\b0 \fs18 a}{\b0 \fs18 LOW.}{\fs18 A}{\b0 \fs18
pulse}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 clock}{\b0 \fs18 input}{\b0 \
fs18 will}{\b0 \fs18 shift }
\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 s
erial-data}{\b0 \fs18 input}{\b0 \fs18 to}{\b0 \fs18 position}{\i \f10 \fs17
A}{\b0\i \fs17 (}{\b0\i \fs17 Q}{\b0 \fs18 of}{\b0 \fs18 FF1).}{\b0 \fs1
8 The}{\b0 \fs18 indicators}{\i \fs18 (}{\i \fs18 A}{\i \fs18 ,}{\b0\i \f
s18 B,}{\b0 \fs19 C,}{\b0\i \fs19 D}{\b0\i \fs19 )}{\b0 \fs18 across}{\b0 \fs
18 the }
\b0 \fs18 top}{\b0 of}{\b0 \fs18 Fig.}{\b0 \fs18 11-2}{\b0 \fs18 show}{\b0
\fs18 the}{\b0 \fs18 contents}{\b0 \fs18 of}{\b0 \fs18 each}{\b0 \fs18 flip
-flop}{\b0 \fs18 or}{\b0 \fs18 the}{\b0 \fs18 contents}{\b0 \fs18 of}{\b0 \f
s18 the}{\b0 \fs18 register.}{\b0 \fs18 This}{\b0 \fs18 register}{\b0 \fs18
can}{\b0 \fs18 be }
\b0 \fs18 classified}{\b0 \fs18 as}{\b0 \fs18 a}{\b0\i \fs19 serial-in}{\b0\i
\fs19 parallel-out}{\b0 \fs18 unit}{\b0 \fs18 if}{\b0 \fs18 data}{\b0 \fs1
8 is}{\b0 \fs18 read}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 parallel}{\b
0 \fs18 outputs}{\i \fs18 (}{\i \fs18 A}{\i \fs18 ,}{\b0\i \fs19 B,}{\b0 \fs
19 C,}{\b0\i \f10 \fs17 0)}{\b0 \fs18 across}{\b0 \fs18 the }
\b0 \fs18 top}{\b0 \fs18 (Fig.}{\b0 \fs18 11-2). }
8 \cf0 \fi4608 {\b0 \fs14 Pa}{\b0\dn006 \fs10 r;i}{\b0 \fs15 I}{\b0 \fs15 I}{\
b0 \fs14 e}{\b0 \f10 \fs14 1}{\b0 \fs14 -d}{\b0\dn006 \f10 \fs8 ;I}{\b0 \f10 \f
s11 t}{\b0 \f10 \fs12 a}{\b0 \fs14 output}{\b0\dn006 \fs9
I}{\b0 \fs14 n}{\
b0 \fs14 d}{\b0 \fs14 ica}{\b0 \f10 \fs11 t}{\b0 \fs14 o}{\b0 \fs14 r}{\b0 \f10
\fs11 s }\par
}
{\phpg\posx2349\pvpg\posy4620\absw447\absh322 \f20 \fs14 \cf0 \f20 \fs14 \cf0 Se
rial\par}{\phpg\posx2349\pvpg\posy4620\absw447\absh322 \sl-175 \f20 \fs14 \cf0 \fi66
data \par
}
puts \par
}
\par
}
ear{\f10 \fs19 - }
fs15 Clock}{\f10 \fs19 - }\par
}

}
A \par
}
0 \fs16 \cf0 Fig.{\fs16 11-2}{\b0 \fs16
Logic}{\b0 \fs16 diagram}{\b0 \fs1
6 of}{\b0 \fs16 a}{\b0 \fs16 4-bit}{\b0 \fs16 serial-load}{\b0 \fs16 sh
ift-right}{\b0 \fs16 register }
f0 \fi368 {\b0 \fs18 Assume}{\b0 \fs18 all}{\b0 \fs18 the}{\b0 \fs18 flip-fl
ops}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 11-2}{\b0 \fs
18 are}{\b0 \fs18 reset}{\b0\i \fs18 (}{\b0\i \fs18 Q}{\b0\dn006 \f10 \fs11
=}{\b0 \fs18 0).}{\b0 \fs18 The}{\b0 \fs18 output}{\b0 \fs18 is}{\b0 \fs18
then}{\b0 \fs19 0000.}{\b0 \fs18 Place}{\b0 \fs18 the }
\b0 \fs18 clear}{\b0 \fs18 input}{\b0 \fs18 at}{\b0 \fs18 1.}{\b0 \fs18 Pl
ace}{\b0 \fs18 a}{\b0 \fs18 1}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 d
ata}{\b0 \fs18 input.}{\b0 \fs18 Pulse}{\b0 \fs18 the}{\b0 \fs18 clock}{\
b0 \fs18 input}{\b0\i \fs19 once.}{\b0 \fs18 The}{\b0 \fs18 outputs}{\b0 \
fs18 will}{\b0 \fs18 then}{\b0 \fs18 read }
fi30 {\b0 \fs19 1000}{\i \fs18 (}{\i \fs18 A}{\b0\dn006 \f10 \fs13 =}{\b0 \fs1
8 1,}{\b0\i \fs19 B}{\b0\dn006 \f10 \fs13 =}{\b0 \fs19 0,}{\b0\i \fs19 C}{\
b0\dn006 \f10 \fs11 =}{\b0 \fs19 0,}{\b0\i \fs18 D}{\b0\dn006 \f10 \fs11
=}{\b0 \fs18 0).}{\b0 \fs18 Place}{\b0 \fs18 a}{\b0 \fs18 0}{\b0 \fs18 at}{
\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 input.}{\b0 \fs18 Pulse}{\b0 \fs18
the}{\b0 \fs18 clock}{\b0 \fs18 input}{\b0 \fs18 a}{\b0 \fs18 second}{\b0 \
fs18 time.}{\b0 \fs18 The }
\b0 \fs18 output}{\b0 \fs18 now}{\b0 \fs18 reads}{\b0 \fs18 0100.}{\b0 \fs1
8 After}{\b0 \fs18 a}{\b0 \fs18 third}{\b0 \fs18 pulse,}{\b0 \fs18 the}
{\b0 \fs18 output}{\b0 \fs18 reads}{\b0 \fs19 0010.}{\b0 \fs18 After}{\b0
\fs18 a}{\b0 \fs18 fourth}{\b0 \fs18 pulse,}{\b0 \fs18 the}{\b0 \fs18 o
utput }
\b0 \fs18 reads}{\b0 \fs18 0001.}{\b0 \fs18 The}{\b0 \fs18 binary}{\b0 \fs18
word}{\b0 \fs18 0001}{\b0 \fs18 has}{\b0 \fs18 been}{\b0 \fs18 loaded}{\
b0 \fs18 into}{\b0 \fs18 the}{\b0 \fs18 register}{\b0 \fs18 one}{\b0 \fs1
8 bit}{\b0 \fs18 at}{\b0 \fs18 a}{\b0 \fs18 time.}{\b0 \fs18 This}{\b0 \
fs18 is}{\b0 \fs18 called }
\b0\i \fs19 serial}{\b0\i \fs19 loading.}{\b0 \fs18 Note}{\b0 \fs18 that,}{\
b0 \fs18 on}{\b0 \fs18 each}{\b0 \fs18 clock}{\b0 \fs18 pulse,}{\b0 \fs18
the}{\b0 \fs18 register}{\b0 \fs18 shifts}{\b0 \fs18 data}{\b0 \fs18 to}{\b
0 \fs18 the}{\b0 \fs18 right.}{\b0 \fs18 This}{\b0 \fs18 register}{\b0 \fs1
8 could }
\b0 \fs18 then}{\b0 \fs18 be}{\b0 \fs18 called}{\b0 \fs18 a}{\b0\i \fs19 s
erial-load}{\b0\i \fs19 shift-right}{\b0\i \fs19 register. }
fi372 {\fs18 As}{\b0 \fs18 with}{\b0 \fs18 other}{\b0 \fs18 sequential}{\b0
\fs18 logic}{\b0 \fs18 circuits,}{\b0 \fs18 waveforms}{\b0 \fs18 (timing}{\
b0 \fs18 diagrams)}{\b0 \fs18 are}{\b0 \fs18 an}{\b0 \fs18 aid}{\b0 \fs18
to}{\b0 \fs18 understanding }
\b0 \fs18 circuit}{\b0 \fs18 operation.}{\b0 \fs18 Figure}{\b0 \fs18 11}{\b
0 \fs19 -3}{\b0 \fs18 illustrates}{\b0 \fs18 the}{\b0 \fs18 operation}{\b0 \
fs18 of}{\b0 \fs18 the}{\b0 \fs18 4-bit}{\b0 \fs18 serial-load}{\b0 \fs18
shift-right}{\b0 \fs18 register.}{\b0 \fs18 The }\par

}
\cf0 Fig.{\fs16 11-3}{\b0 \fs16
Timing}{\b0 \fs16 diagram}{\b0 \fs16 fo
r}{\b0 \fs16 a}{\b0 \fs16 4-bit}{\b0 \fs16 serial-load}{\b0 \fs16 shift-ri
ght}{\b0 \fs16 register }\par
}
0 262 \par
}
cf0 SHIFT{\fs17 REGISTERS }\par
}
f0 [CHAP.{\b0 \fs17 11 }\par
}
hree inputs (serial-data, clear, and clock) to the register are shown
across the top. The parallel
uts are shown in the middle-four lines. Note that the outputs are taken from
the normal output
\fs19 (Q)}of each flip-flop. The bottom line describes several functions of the
shift register.
77 Consider the initial conditions of all the flip-flops shown in Fig. 11-3.
All are set. At point{\i \fs19 a} on
clear-input waveform, all the flip-flops are reset to{\fs19 0000.} The clear in
put operates asynchronously
overrides all other inputs. Note that the clear input is{\fs19 an} active-LOW
input.
72 {\b \fs19 At} point{\b\i \fs19 b} on the serial-data input, a HIGH is place
d on the{\i \fs19 D} input to FF1. On the leading edge
\par}{\phpg\posx835\pvpg\posy1335\absw9054\absh6410 \sl-237 \f20 \fs18 \cf0 of c
lock pulse 1, the HIGH is transferred to output Q of FFI. The output now reads 1
000. Clock pulse
2} transfers a{\fs19 0} to output{\i Q} of{\fs19 FFl.} At the same time, the
1 at input{\i \fs19 D} to FF2 is transferred to output
\par}{\phpg\posx835\pvpg\posy1335\absw9054\absh6410 \sl-237 \f20 \fs18 \cf0 Q of
this flip-flop. The output is now{\fs19 0100.} Clock pulse 3 transfers a{\fs18
0} to the output of FF1. The 1 at
t{\b\i \f30 \fs21 D}{\fs19 of}{\fs19 FF3} is transferred to the output of
this flip-flop. The output of the register{\fs19 is} now 0010.
\par}{\phpg\posx835\pvpg\posy1335\absw9054\absh6410 \sl-237 \f20 \fs18 \cf0 Cloc
k pulse{\b \fs19 4} transfers a{\fs19 0} to the output of FF1. The 1 at input{
\i \fs19 D} of FF4 is transferred to the output
his flip-flop. The output of the register is now 0001. It took four clock pulses
(pulses 1 through 4,
11-3) to serially load the 4-bit word{\fs19 0001} into the register.
73 Consider clock pulse{\i \fs19 5} (Fig. 11-3).Just before pulse{\i \fs19 5,

} the register contents are 0001. Clock pulse
20 5} adds a new{\fs19 0} at the left (at{\b\i \fs18 Q} of FFl), and the 1on t
he right is shifted out of the register and is lost.
result is that the register contents are 0000 after clock pulse{\fs19 5. }
72 Consider clock pulses{\fs19 6} through{\fs18 9} (Fig. 11-3). These f
our pulses are used to serially load the
ry word 1001 into the register. At point{\b\i c} the serial-data inpu
t{\fs19 is} placed at 1. On the L-to-H
sition of clock pulse{\fs19 6,} this{\fs19 1} is transferred from the{\i D}
input of FF1 to its{\i \fs17 Q} output. After pulse{\fs18 6 }
register reads 1000. The serial-data input{\fs18 is} returned to 0 at point{\i
\f10 \fs18 d.} Clock pulses{\fs19 7} and{\fs18 8} shift the
19 1}to the right. After clock pulse{\fs19 8,} the register reads{\fs19 0010.}
The serial data input is placed at 1 at point
i e.} On the leading edge{\fs19 of} clock pulse{\fs18 9,} this 1 is plac
ed at output{\i \fs17 Q} of FF1 and the other data is
\par}{\phpg\posx835\pvpg\posy1335\absw9054\absh6410 \sl-233 \f20 \fs18 \cf0 shif
ted one place to the right. The register contents after clock pulse{\fs18
9} are 1001. It took four clock
es{\b (6} through{\fs18 9)} to serially load 1001 into the register.
65 Consider clock pulses{\fs19 10} through 12 (Fig. 11-3). The serial-data
input remains at 1 during these
es. Before pulse{\fs18 10} the register contents are 1001. On each pulse, a 1 i
s added to output Q of FF1
the other 1s are shifted to the right. After clock pulse{\fs19 12,} the regi
ster contents are 1111.
71 If output{\i \fs19 D} of FF4 in Fig. 11-2 is considered the only output,
this storage unit could be classified
\par}{\phpg\posx835\pvpg\posy1335\absw9054\absh6410 \sl-236 \f20 \fs18 \cf0 as a
serial-in serial-out shift register. \par
}
\cf0 SOLVED{\fs16 PROBLEMS }
fi100 {\f20 \fs19 11.1}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 4-bit}{\b0 \f20 \f
s18 shift}{\b0 \f20 \fs18 register}{\b0 \f20 \fs18 described}{\b0 \f20 \fs18
in}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18 section}{\b0 \f20 \fs18 uses }
fi590 {\b0 \f20 \fs18 flip-flops. }
fi950 {\b0 \f20 \fs17 The}{\b0 \f20 \fs17 4-bit}{\b0 \f20 \fs17 register}{\b
0 \f20 \fs17 uses}{\b0 \f20 \fs17 four}{\i \f30 \fs19 D}{\b0 \f20 \fs17 f
lip-flops. }\par
}

decimal number) \par
}
20 \cf0 (D,{\f20 \fs19 T}{\f20 \fs19 ) }\par
}
\cf0 11.2{\b0 \fs18 The}{\b0 \fs18 flip-flops}{\b0 \fs18 shown}{\b0 \fs18 i
n}{\b0 \fs18 Fig.}{\b0 11-2}{\b0 \fs18 are }
}
(leading-, trailing-) edge triggered. \par
}
The flip-flops shown in Fig. 11-2 are leading-edge triggered. \par
}
\cf0 11.3{\b0 \fs18 In}{\b0 \fs18 Fig.}{\b0 \fs18 11-2,}{\b0 \fs18 the}{\b
0 \fs18 shift-right}{\b0 \fs18 operation}{\b0 \fs18 means}{\b0 \fs18 to}{
\b0 \fs18 shift}{\b0 \fs18 data}{\b0 \fs18 from }
fi487 {\b0 \fs18 (FF1,}{\fs19 FF4). }
fi846 {\fs16 By}{\b0 \fs17 definition,}{\b0 \fs17 shift}{\b0 \fs17 right}{\
b0 \fs17 means}{\b0 \fs17 to}{\b0 \fs17 shift}{\b0 \fs17 data}{\b0 \fs17
from}{\b0 \fs17 FF1}{\b0 \fs17 to}{\b0 \fs17 FF4}{\b0 \fs17 in}{\b0 \f
s17 Fig.}{\b0 \fs17 11-2. }\par
}
(FF1, FF4) to \par
}
. 111 \par
}
IFT{\b \fs17 REGISTERS }\par
}
f0 263 \par
}
cf0 11.4{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs18 Fig.}{\b0 11-2.}{\b0 \fs1
9 Clear}{\b0 \fs19 is}{\b0 \fs19 an}{\b0 \fs19 active- }
}
HIGH,{\fs19 LOW)}{\fs19 input. }\par
}
\cf0 Clear is an active-LOW input in Fig. 11-2, as shown by the bubb
les on the CLR inputs of each{\b\i \f30 \fs19 D }
-flop. \par
}
cf0 11.5{\b0 \f20 \fs19
Refer}{\b0\i \f20 \fs19 to}{\b0 \f20 \fs19 Fig.}{\b
0 \f20 \fs18 11-3.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 clear}{\b0 \f20 \fs18
is}{\b0 \f20 \fs19 a(n) }
}
asynchronous, synchronous) input. \par
}
\cf0 The clear is an asynchronous input to the register (Fig. 11-.3).
\b \fs18 11.6}{\fs19
Refer}{\fs19 to}{\b \fs18 Fig.}{\fs18 11-4.}{\fs19 L
ist}{\fs19 the}{\fs19 states}{\fs19 of}{\fs19 the}{\fs19 output}{\fs19 ind
icators}{\fs19 of}{\fs19 the}{\fs19 shift}{\fs19 register}{\b\i \fs19 afte
r}{\fs19 each}{\fs19 clock }
7 {\fs19 pulse}{\fs19 (bit}{\b\i \f10 \fs17 A}{\fs19 on}{\fs19 left,}{\fs1
9 bit}{\b\i \f30 \fs21 D}{\fs19 on}{\fs19 right). }\par
}
{\phpg\posx5383\pvpg\posy5426\absw471\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Se
rial- \par
}
cf0 D \par
}
cf0 Q+D \par
}
K \par
}
f30 \fs21 \cf0 Q
\fi176 {\b0\i0 \f20 \fs15 FF2 }
{\b0\i0 \f20 \fs15 >CLK }\par
}
{\phpg\posx7659\pvpg\posy5852\absw256\absh191 \f10 \fs16 \cf0 \f10 \fs16 \cf0 -> \par
}
cf0 FF3
5 CLK }
2 {\b \f10 \fs7 n }\par
}
\cf0 FF4
6 >CLK }\par
}
n \par
}
par
}
\par
}
{\phpg\posx4503\pvpg\posy6391\absw459\absh305 \f10 \fs26 \cf0 \f10 \fs26 \cf0 &\par
}
ear \par
}
}
{\phpg\posx6687\pvpg\posy6427\absw192\absh446 \f20 \fs30 \cf0 \f20 \fs30 \cf0 I{
\fs22 I }\par
}
\par
}
A \par
}
\cf0 Solution:
fi350 {\b0 \fs17 The}{\b0 \fs17 output}{\b0 \fs17 states}{\b0 \fs17 of}{\b0
\fs17 the}{\b0 \fs17 register}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17
Fig.}{\b0 \fs17 11-4}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \fs17 follows: }
\par
}
ulse{\b\i \fs16 a}{\f10 \fs13 =} 0000
pulse{\i \fs16 b}{\f10 \fs13 =} 1000 \par
}
lse{\b\i \f30 \fs18 f }\par
}
\f20 \fs17 1000 }\par
}
pulse{\b\i \fs16 c}{\f10 \fs13 =}{\fs16 0100 }\par
}
pulse{\b\i \fs17 d}{\b\i \fs17 =} 1010 \par
}
pulse{\b\i \fs17 e}{\dn006 \f10 \fs11 =} 0000 \par
}
Clear mode resets all FFs
0.
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-215 \f20 \fs17 \cf0 Shi
ft-right mode moves bits
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-223 \f20 \fs17 \cf0 one
position to the right{\fs17 on }
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-210 \f20 \fs17 \cf0 lea
ding edge of clock pulse.

e that the 1 at the D
ut to FF1 is shifted to
{\f10 \fs15 (2} output of FFl.
position to the right.
e that the 0 at the{\b\i \f30 \fs19 D }
ut to FF1 is shifted to
{\i \f10 \fs15 Q} output of FFl.
e that the 1 at{\b\i \f30 \fs19 D} input
FF1{\b \fs16 is} shifted{\fs16 to} the{\i \f10 \fs16 Q }
put of FF1.
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-205 \f20 \fs17 \cf0 Tem
porarily
the
output
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-212 \f20 \fs17 \cf0 goe
s{\fs17
to}{\fs16
0101} on leading
\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-220 \f20 \fs17 \cf0 edg
e{\fs17
of} the clock pulse.
n the clear input is acti\par}{\phpg\posx2979\pvpg\posy8561\absw2174\absh4679 \sl-220 \f20 \fs17 \cf0 vat
ed, resetting all FFs to
s16 0. }\par
}
ulse{\i \f10 \fs14 g}{\f10 \fs13 =} 1100 \par
}
pulse{\b\i \fs17 h}{\f10 \fs13 =} 1110
pulse{\b\i \f30 \fs18 i}{\f10 \fs13 =} 0111 \par
}
pulse{\i \f10 \fs15 j}{\f10 \fs13 =} 0011 \par
}
Shift-right mode moves bits
e
that
a{\fs17
1} is being
\par}{\phpg\posx7523\pvpg\posy8561\absw2157\absh3326 \sl-223 \f20 \fs17 \cf0 shi
fted
into
the
leftmost
\par}{\phpg\posx7523\pvpg\posy8561\absw2157\absh3326 \sl-215 \f20 \fs17 \cf0 pos
ition from input{\fs18
D} of
.
ft-right mode. Note the
s16 0} being loaded into the left
ition from input{\b\i \f30 \fs19 D} of
.
ft-right mode. Note the
\par}{\phpg\posx7523\pvpg\posy8561\absw2157\absh3326 \sl-212 \f20 \fs17 \cf0 0 b
eing loaded into the left
ition. \par
}
\par
}
IFT REGISTERS \par
}
AP.{\fs17 11 }\par
}
cf0 11.7{\b0 \fs19
\b0 \fs19 This}{\b0 \fs19 is}{\b0 \fs19 a }
}
parallel-, serial-) load shift- \par
}
left, right) register. \par
}
he device shown in Fig.{\b \fs16 11-4} is a serial-load shift-right registe
r. \par
}
cf0 11.8{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 11-4.}{\
b0 \fs19 After}{\b0 \fs19 clearing,}{\b0 \fs19 it}{\b0 \fs19 takes }
i487 {\b0 \fs19 register. }
}
lock pulse(s) to load a 4-bit word into this \par
}
t takes four clock pulses to serially load the register shown in Fig. 1
1-4. \par
}
cf0 11.9{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 11-4.}{\b0 The}{\b0 CLK}{\b0 i
nputs}{\b0 to}{\b0 the}{\b0 flip-flops}{\b0 are}{\b0 wired}{\b0 in }
i492 {\b0 therefore}{\b0 all}{\b0 shifts}{\b0 take}{\b0 place}{\b0 at}{\b0
the}{\b0 same}{\b0 time. }
i848 {\b0 \fs17 The}{\fs17 CLK}{\b0 \fs17 inputs}{\b0 \fs17 to}{\b0 \fs17
the}{\b0 \fs17 flip-flops}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{
\fs16 11-4}{\b0 \fs17 are}{\b0 \fs17 wired}{\b0 \fs17 in}{\b0 \fs17 para
llel. }\par
}
parallel, series), and \par
}
\fs18 \cf0 11-3{\fs19
PARALLEL-LOAD}{\fs19 SHIFT}{\fs19 REGISTER }
fi456 {\b0 \fs19 The}{\b0 \fs19 disadvantage}{\b0 \fs19 of}{\b0 \fs19 the}{\b
0 \fs19 serial-load}{\b0 \fs19 shift}{\b0 \fs19 register}{\b0 \fs19 is}{\b0
\fs19 that}{\b0 \fs19 it}{\b0 \fs19 takes}{\b0 \fs19 many}{\b0 \fs19 clock}
{\b0 \fs19 pulses}{\b0 \fs19 to}{\b0 \fs19 load}{\b0 \fs19 the}{\b0 \fs19 u
nit. }
fi94 {\fs19 A}{\b0 \fs19 parallel-load}{\b0 \fs19 shift}{\b0 \fs19 register}
{\b0 \fs19 loads}{\b0 \fs19 all}{\b0 \fs19 bits}{\b0 \fs19 of}{\b0 \fs19 i
nformation}{\b0 \fs19 immediately.}{\b0 \fs19 One}{\b0 \fs19 simple}{\b0 \f
s19 4-bit}{\b0 \fs19 parallel-load }
fi96 {\b0 \fs19 shift}{\b0 \fs19 register}{\b0 \fs19 is}{\b0 \fs19 diagrammed
}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 11-5.}{\b0 \fs19 Note}{\b0 \fs19
the}{\b0 \fs19 use}{\b0 \fs19 of}{\i \fs19 JK}{\b0 \fs19 flip-flops}{\b0
\fs19 with}{\b0 \fs19 both}{\b0 \fs19 CLR}{\b0 \fs19 and}{\b0\i \fs19 PS}{
\b0 \fs19 inputs. }
fi94 {\b0 \fs19 The}{\b0 \fs19 inputs}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \f
s19 left}{\b0 \fs19 are}{\b0 \fs19 the}{\b0 \fs19 clear,}{\b0 \fs19 cl
ock,}{\b0 \fs19 and}{\b0 \fs19 four}{\b0 \fs19 parallel-data}{\b0 \fs19
(parallel-load)}{\b0 \fs19 inputs.}{\b0 \fs19 The}{\b0 \fs19 clock }
fi96 {\b0 \fs19 connects}{\b0 \fs19 each}{\b0 \fs19 CLK}{\b0 \fs19 input}{\b0
\fs19 in}{\b0 \fs19 parallel.}{\b0 \fs19 The}{\b0 \fs19 clear}{\b0 \fs19 c
onnects}{\b0 \fs19 each}{\b0 \fs19 CLR}{\b0 \fs19 input}{\b0 \fs19 in}{\b0 \
fs19 parallel.}{\b0 \fs19 The}{\i \fs19 PS}{\b0 \fs19 input}{\b0 \fs19 for
}
fi100 {\b0 \fs19 each}{\b0 \fs19 flip-flop}{\b0 \fs19 is}{\b0 \fs19 brought}{
\b0 \fs19 out}{\b0 \fs19 for}{\b0 \fs19 parallel-data}{\b0 \fs19 loading.}{\
b0 \fs19 The}{\b0 \fs19 output}{\b0 \fs19 indicators}{\b0 \fs19 across}{\b0
\fs19 the}{\b0 \fs19 top}{\b0 \fs19 of}{\b0 \fs19 Fig.}{\b0 \fs19 11-5 }

fi96 {\b0 \fs19 show}{\b0 \fs19 the}{\b0 \fs19 state}{\b0 \fs19 of}{\b0 \fs19
output}{\b0 \f10 \fs17 (2}{\b0 \fs19 of}{\b0 \fs19 each}{\b0 \fs19 flip-f
lop.}{\b0 \fs19 Note}{\b0 \fs19 the}{\b0 \fs19 wiring}{\b0 \fs19 of}{\b0 \fs
19 the}{\b0\i \fs19 JK}{\b0 \fs19 flip-flops.}{\b0 \fs19 Especially}{\b0 \f
s19 note}{\b0 \fs19 the }
fi94 {\b0 \fs19 two}{\i \fs19 feedback}{\b0 \fs19 lines}{\b0 \fs19 running}{
\b0 \fs19 from}{\b0 \fs19 the}{\i \fs18 Q}{\b0 of}{\b0 \fs19 FF4}{\b0 \fs
19 back}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs18 J}{\b0 \fs19 of}{\b0 \fs19
FF1}{\b0 \fs19 and}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19
of}{\b0 \
fs19 FF4}{\b0 \fs19 back}{\b0 \fs19 to }
fi94 {\b0 \fs19 the}{\b0\i \fs19 K}{\b0 \fs19 of}{\b0 \fs19 FF1.}{\b0 \fs19
These}{\b0 \fs19 are}{\b0 \fs19 recirculating}{\b0 \fs19 lines,}{\b0 \fs19
and}{\b0 \fs19 they}{\b0 \fs19 save}{\b0 \fs19 the}{\b0 \fs19 data}{\b0 \fs1
9 that}{\b0 \fs19 would}{\b0 \fs19 normally}{\b0 \fs19 be}{\b0 \fs19 lost}{
\b0 \fs19 out}{\b0 \fs19 the }
\b0 \fs19 ,right}{\b0 \fs19 end}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19 reg
ister.}{\b0 \fs19 It}{\b0 \fs19 is}{\b0 \fs19 said}{\b0 \fs19 that}{\b0 \fs
19 the}{\b0 \fs19 data}{\b0 \fs19 will}{\b0\i \fs19 recirculate}{\b0 \fs19
through}{\b0 \fs19 the}{\b0 \fs19 register. }
f0 \fi4920 {\b0 \fs14 Parallel-data}{\b0 \fs14 output}{\b0 \fs14 indicators }
\par
}
Q Q \par
}
{\phpg\posx4725\pvpg\posy9353\absw110\absh308 \f10 \fs26 \cf0 \f10 \fs26 \cf0 !
\par
}
\par
}
1 \par
}
\par
}
\f30 \fs12 \cf0 b
\cf0 {\b0 \fs12 6}{\b0\i0 \f20 \fs2
3 }
\cf0 \fi32 {\b0\i0\dn006 \f10 \fs10 4)}{\b0\i0 \f20 \fs15 CLK }\par
}
s15 \cf0 J p s Q .
\fi166 {\i0 FF2 }\par
}
0 \fs12 \cf0 n
\fi27 {\i \f20 \fs15 J}{\i \f20 \fs15 P}{\i \f20 \fs15 S}{\i \f20 \fs15 Q}
{\i \f20 \fs15 ' }
\fi187 {\f20 \fs15 FF3 }

\fi87 {\b0 \f20 \fs15 CLK }
cf0 {\b0 \f20 \fs15 KCLRQ }
\fi261 {\i \f30 \fs13 9 }\par
}
\cf0 5 \par
}
{\phpg\posx2793\pvpg\posy8975\absw311\absh905 \f10 \fs75 \cf0 \f10 \fs75 \cf0 [
\par
}
{\phpg\posx8685\pvpg\posy8758\absw434\absh859 \f30 \fs68 \cf0 \f30 \fs68 \cf0 QI
\par
}
{\phpg\posx2169\pvpg\posy9449\absw623\absh484 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Pa
rallel\par}{\phpg\posx2169\pvpg\posy9449\absw623\absh484 \sl-167 \f20 \fs15 \cf0 \fi13
6 data
{\fs14 (load) }\par
}
15 \cf0 D \par
}
\par
}
\fs12 \cf0 n
\i \f30 \fs16 J}{\i \f20 \fs15 ps}{\b0\i \f20 \fs14 Q }
fi157 {\f20 \fs14 FF4 }\par
}
14 \cf0 A \par
}
\cf0 1
30 {\b \f30 \fs24 A }
98 {\b\i \fs15 -}{\b\i \fs15 J}{\b\i \fs15 p}{\b\i \fs15 s}{\b\i \fs15 Q
}{\b\i \fs15 r }
48 {\b \fs15 FF}{\f10 \fs13 1 }
0 \fs10 ----O>}{\fs15 CLK }\par
}
\cf0 1 \par
}
}
9 \cf0 A& \par
}
{\phpg\posx3775\pvpg\posy11317\absw613\absh307 \f20 \fs15 \cf0 \f20 \fs15 \cf0 K
CLRQ
57 {\b\i \f10 \fs10 0 }\par
}
\cf0 , \par
}
\cf0 Inputs \par
}
> \par
}
> C L K \par
}
}
J \par
}
\cf0 - \par
}
CLRQ
52 {\b \f30 \fs14 u }\par
}
r
}
CLRQ
47 {\b\i \f10 \fs9 0 }\par
}
lock
\par}{\phpg\posx2629\pvpg\posy11791\absw447\absh399 \sl-251 \f20 \fs15 \cf0 Clea
r \par
}
0 A \par
}
0 A \par
}
20 \fs16 \cf0 Fig.{\fs17 11-5}{\b0 \fs17
Logic}{\b0 \fs17 diagram} of{\b0 \
fs17 a}{\b0 \fs17 4-bit}{\b0 \fs17 parallel-load}{\b0 \fs17 recirculating}{
\b0 \fs17 shift-right}{\b0 \fs17 register }
cf0 \fi362 {\b0 \fs19 Note}{\b0 \fs19 from}{\b0 \fs19 the}{\b0\i \fs19 JK}{\b
0 \fs19 flip-flop}{\b0 \fs19 logic}{\b0 \fs19 symbols}{\b0 \fs19 in}{\b0 \f
s19 Fig.}{\b0 \fs19 11-5}{\b0 \fs19 that}{\b0 \fs19 the}{\i \f30 \fs20 PS}{\
b0 \fs19 and}{\b0 \fs19 CLR}{\b0 \fs19 inputs}{\b0 \fs19 are}{\b0 \fs19 act
ive-LOW }
{\b0 \fs19 inputs.}{\b0 \fs19 They}{\b0 \fs19 are}{\b0 \fs19 also}{\b0 \fs19
asynchronous}{\b0 \fs19 and}{\b0 \fs19 override}{\b0 \fs19 all}{\b0 \fs19 o
ther}{\b0 \fs19 inputs.}{\b0 \fs19 Assume}{\b0 \fs19 that}{\b0 \fs19 these}{
\i \fs19 JK}{\b0 \fs19 flip-flops}{\b0 \fs19 are }
{\b0 \fs19 pulse-triggered}{\b0 \fs19 units. }\par
}
.{\fs16 111 }\par
}
IFT REGISTERS \par
}
\par
}
\cf0 A waveform diagram for the{\i \fs19 parallel-load}{\i \fs19 recirculating
}{\i \fs19 shift-right}{\i \fs19 register} is shown in Fig. 11-6.The
\par}{\phpg\posx837\pvpg\posy1375\absw9539\absh851 \sl-237 \f20 \fs18 \cf0 top f
our lines on the diagram are the parallel-data inputs, or load inputs. These ar
e normally{\fs19 HIGH }
\par}{\phpg\posx837\pvpg\posy1375\absw9539\absh851 \sl-240 \f20 \fs18 \cf0 and a
re placed LOW only when loading. The clear and clock inputs are shown near the c
enter of the
\par}{\phpg\posx837\pvpg\posy1375\absw9539\absh851 \sl-234 \f20 \fs18 \cf0 diagr
am. \par
}
0 \fs16 \cf0 Fig.{\fs17 11-6}{\b0 \fs17
Timing}{\b0 \fs17 diagram}{\b0 \fs
17 for}{\b0 \fs17 a}{\b0 \fs17 4-bit}{\b0 \fs17 parallel-load}{\b0 \fs17
recirculating}{\b0 \fs17 shift-right}{\b0 \fs17 register }
f0 \fi359 {\b0 \fs18 The}{\b0 \fs18 four}{\b0 \fs18 shaded}{\b0 \fs18 wave
forms}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 11-6}{\b0 \fs18 are}{\b0 \
fs18 the}{\b0 \fs18 outputs}{\b0 \fs18 at}{\b0 \fs18 Q}{\b0 \fs18 of}{
\b0 \fs18 each}{\b0\i \fs18 JK}{\b0 \fs18 flip-flop.}{\b0 \fs18 Across}{\
b0 \fs18 the }
\b0 \fs18 bottom}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 diagram}{\b0 \fs18
are}{\b0 \fs18 functions}{\b0 \fs18 being}{\b0 \fs18 performed}{\b0 \fs18 b
y}{\b0 \fs18 the}{\b0 \fs18 register. }
fi366 {\b0 \fs18 Consider}{\b0 \fs18 the}{\b0 \fs18 outputs}{\b0 \fs18 on}{
\b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 side}{\b0 \fs18 of}{\b0 \fs18 F
ig.}{\b0 \fs18 11-6.}{\b0 \fs18 The}{\b0 \fs18 outputs}{\b0 \fs18 are}{\b0
\fs18 1111}{\b0 \fs18 before}{\b0 \fs18 point}{\b0\i \f10 \fs16
a}{\b0 \
fs18 on}{\b0 \fs18 the }
\b0 \fs18 clear}{\b0 \fs18 waveform.}{\b0 \fs18 At}{\b0 \fs18 point}{\b0\i
\f10 \fs15
a,}{\b0 \fs18 the}{\b0 \fs18 outputs}{\b0 \fs18 are}{\b0 \f
s18 immediately}{\b0 \fs18 reset}{\b0 \fs18 to}{\b0 \fs18 0000.}{\b0 \fs
18 The}{\b0 \fs18 clear}{\b0 \fs18 input}{\b0 \fs18 is}{\b0 \fs18 asyn
- }
\b0 \fs18 chronous}{\b0 \fs18 and}{\b0 \fs18 therefore}{\b0 \fs18 needs}{\b0
\fs18 no}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 to}{\b0 \fs18 reset}
{\b0 \fs18 the}{\b0 \fs18 register. }
fi359 {\b0 \fs18 At}{\b0 \fs18 point}{\b0\i \fs19
b}{\b0 \fs18 the}{\i \f
s18 A}{\b0 \fs18 and}{\b0\i \fs18 B}{\b0 \fs18
parallel-data}{\b0 \fs18
inputs}{\b0 \fs18 are}{\b0 \fs18 activated.}{\b0 \fs18 Being}{\b0 \fs18
asynchronous}{\b0 \fs18 inputs,}{\b0 \fs18 the }
\b0 \fs18 outputs}{\b0 \fs18 of}{\b0 \fs18 FF1}{\b0 \fs18 and}{\b0 \fs18
FF2}{\b0 \fs18 go}{\b0 \fs19 HIGH}{\b0 \fs18 immediately.}{\b0 \fs18 At}{\
b0 \fs18 point}{\b0\i \fs19 c,}{\b0 \fs18 the}{\i \fs18 A}{\b0 \fs18 an
d}{\b0\i \fs18 B}{\b0 \fs18 parallel-data}{\b0 \fs18 inputs}{\b0 \fs18 a
re }
\b0 \fs18 deactivated.}{\b0 \fs18 The}{\b0 \fs18 register}{\b0 \fs18 is}{\b0
\fs18 now}{\b0 \fs18 loaded}{\b0 \fs18 with}{\b0 \fs18 1100. }
fi367 {\b0 \fs18 On}{\b0 \fs18 the}{\b0 \fs18 trailing}{\b0 \fs18 edge}{\b0 \
fs18 of}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 1,}{\b0 \fs18 the}{\b0
\fs18 two}{\b0 \fs18 1s}{\b0 \fs18 shift}{\b0 \fs18 one}{\b0 \fs18 positio
n}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 right.}{\b0 \fs18 The}{\b0 \fs18
result}{\b0 \fs18 is}{\b0 \fs18 0110 }
\b0 \fs18 after}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs19 1.}{\b0 \fs18
Another}{\b0 \fs18 right}{\b0 \fs18 shift}{\b0 \fs18 takes}{\b0 \fs18 p
lace}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 trailing}{\b0 \fs18 edge}{\b0
\fs18 of}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs18 2.}{\b0 \fs18 The}
{\b0 \fs18 result }
\b0 \fs18 after}{\b0 \fs18 pulse}{\b0 \fs19 2}{\b0 \fs18 at}{\b0 \fs18 the}{
\b0 \fs18 outputs}{\b0 \fs18 of}{\b0 \fs18 the}{\b0\i \fs19 JK}{\b0 \fs18
flip-flops}{\b0 \fs18 is}{\b0 \fs18 0011. }
fi368 {\b0 \fs18 Consider}{\b0 \fs18 clock}{\b0 \fs18 pulse}{\b0 \fs19 3,}{\
b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 11-6.}{\b0 \fs18 T
he}{\b0 \fs18 output}{\b0 \fs18 was}{\b0 \fs18 0011}{\b0 \fs18 before}{\b0
\fs18 pulse}{\b0 \fs19 3.}{\b0 \fs18 On}{\b0 \fs18 the}{\b0 \fs18 trailin
g }
\b0 \fs18 edge}{\b0 \fs18 of}{\b0 \fs18 pulse}{\b0 \fs19 3,}{\b0 \fs18 a}{\b
0 \fs18 right}{\b0 \fs18 shift}{\b0 \fs18 takes}{\b0 \fs18 place.}{\b0 \fs18
The}{\b0 \fs18 1}{\b0 \fs18 at}{\b0 \fs18 Q}{\b0 \fs18 of}{\b0 \fs18 FF4}{
\b0 \fs18 would}{\b0 \fs18 normally}{\b0 \fs18 be}{\b0 \fs18 lost,}{\b0 \fs1
8 but}{\b0 \fs18 because}{\b0 \fs18 of}{\b0 \fs18 the }
\b0 \fs18 recirculating}{\b0 \fs18 lines}{\b0 \fs18 (see}{\b0 \fs18 Fig.}{\b0
\fs18 11-5)}{\b0 \fs18 it}{\b0 \fs18 is}{\b0 \fs18 shifted}{\b0 \fs18 back
}{\b0 \fs18 around}{\b0 \fs18 to}{\b0 \fs18 Q}{\b0 \fs18 of}{\b0 \fs18 FF1
.}{\b0 \fs18 The}{\b0 \fs18 result}{\b0 \fs18 is}{\b0 \fs18 that}{\b0 \fs18
the}{\b0 \fs18 register }
\b0 \fs18 contents}{\b0 \fs18 are}{\b0 \fs18 1001}{\b0 \fs18 after}{\b0 \fs18
clock}{\b0 \fs18 pulse}{\b0 \fs19 3.}{\b0 \fs18 Likewise,}{\b0 \fs18 clock
}{\b0 \fs18 pulse}{\b0 \fs18 4}{\b0 \fs18 shifts}{\b0 \fs18 the}{\b0 \fs18
register}{\b0 \fs18 one}{\b0 \fs18 place}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \
fs18 right. }
\b0 \fs18 The}{\b0 \fs18 1}{\b0 \fs18 at}{\b0 \fs18 Q}{\b0 \fs18 of}{\b0
\fs18 FF4}{\b0 \fs18 is}{\b0 \fs18 shifted}{\b0 \fs18 to}{\b0 \fs18 Q}{
\b0 \fs18 of}{\b0 \fs19 FF1.}{\b0 \fs18 The}{\b0 \fs18 results}{\b0 \fs18
are}{\b0 \fs18 that,}{\b0 \fs18 after}{\b0 \fs18 pulse}{\b0 \fs18 4,}{\

b0 \fs18 the}{\b0 \fs18 register}{\b0 \fs18 contains }
\b0 \fs18 1100.This}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 same}{\b0 \fs18
data}{\b0 \fs18 that}{\b0 \fs18 was}{\b0 \fs18 loaded}{\b0 \fs18 in}{\b0 \fs
18 the}{\b0 \fs18 register}{\b0 \fs18 prior}{\b0 \fs18 to}{\b0 \fs18 clock}
{\b0 \fs18 pulse}{\b0 \fs19 1.}{\b0 \fs18 It}{\b0 \fs18 took}{\b0 \fs18 four
}{\b0 \fs18 pulses}{\b0 \fs18 to }
\b0 \fs18 recirculate}{\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 to}{\b0 \fs1
8 its}{\b0 \fs18 original}{\b0 \fs18 position. }
fi367 {\b0 \fs18 Consider}{\b0 \fs18 point}{\b0\i \f10 \fs17 d}{\b0 \fs18
on}{\b0 \fs18 the}{\b0 \fs18 clear}{\b0 \fs18 waveform}{\b0 \fs18 in}{\b0
\fs18 Fig.}{\b0 \fs18 11-6.}{\b0 \fs18 It}{\b0 \fs18 is}{\b0 \fs18 an}{\
b0 \fs18 asynchronous}{\b0 \fs18 input;}{\b0 \fs18 therefore,}{\b0 \fs18 a
s }
\b0 \fs18 soon}{\b0 \fs18 as}{\b0 \fs18 it}{\b0 \fs18 goes}{\b0 \fs18 LO
W,}{\b0 \fs18 all}{\b0 \fs18 flip-flops}{\b0 \fs18 are}{\b0 \fs18 reset.}
{\b0 \fs18 Clock}{\b0 \fs18 pulse}{\b0\i \fs19 5}{\b0 \fs18 has}{\b0 \fs
18 no}{\b0 \fs18 effect}{\b0 \fs18 because}{\b0 \fs18 the}{\b0 \fs18 c
lear}{\b0 \fs18 input }
\b0 \fs18 overrides}{\b0 \fs18 the}{\b0 \fs18 clock. }\par
}
0 266 \par
}
IFT REGISTERS \par
}
f0 [CHAP.{\b0 \fs16 11 }\par
}
\cf0 Consider point{\i \fs19 e} on the parallel-load waveform in Fig. 116. For a very short time, parallel-data
7 input{\b\i \fs19 D} is activated and then deactivated. It loads 0001 i
nto the register. Clock pulse{\fs18 6} recirculates
2 the{\fs19 1} at output Q{\fs19 of} FF4 to FF1. After pulse{\fs18 6,} the r
egister contains 1000. Pulses{\fs19 7,}{\fs18 8,} and{\fs18 9} shift the
8 single 1 to the right three places. After the four pulses{\fs18 (6}
through{\fs18 9),} the data is the same{\fs19 as} the
1 original:{\fs19 0001. }
80 A careful{\b \fs19 look} at Figs. 11-5and 11-6will show that the{\i \fs19
JK} flip-flops are always operating in either
2 the{\i \fs19 set} or{\i \fs19 reset} modes. Before pulse{\fs18 6} (Fi
g. 11-6), the{\i \fs18 Q} outputs are 0001. However, remember that
1 the complementary{\i \f10 \fs27 0} outputs are at the same instant 1110. On
the trailing edge of clock pulse{\fs18 6,} FF1

1 goes from the reset to the set condition because{\fs17 it} has inputs of{
\i J}{\dn006 \f10 \fs13 =} 1 and{\i \fs19 K}{\dn006 \f10 \fs13 =}{\fs18
0.} FF2 has inputs{\fs19 of }
i J}{\dn006 \f10 \fs13 =}{\fs18 0} and{\i \fs19 K}{\dn006 \f10 \fs13 =}{\
fs18 1} and therefore stays in the reset condition. FF3 has inputs of{\
i \fs19 J}{\dn006 \f10 \fs13 =}{\fs19 0} and{\b\i \fs19 K}{\dn006 \f10 \f
s13 =}{\fs19 1} and
2 therefore stays in the reset condition. FF4 has inputs of{\i J}{\dn006 \f10
\fs13 =}{\fs19 0} and{\i \fs19 K}{\dn006 \f10 \fs13 =} 1. FF4 changes st
ate and goes
1 from the set to the reset condition.
80 The circuit shown in Fig. 11-5 is but{\fs19 one} of many parallelload shift registers. Because these
1 registers are somewhat complicated, they are often purchased{\fs18 in} IC fo
rm.
79 The shift register shown in Fig.{\fs19 11-5}might also be called a{\i \fs19
ring}{\i \fs19 counter}{\fs18 if} a single 1 is loaded into
1 the register. If a continuous series of pulses arrives at the clock
input, the lone{\fs19 HIGH} output will
7 sequence in a "ring"{\fs19 in} the register. Each output{\b\i \f10 \f
s17 (}{\b\i \f10 \fs17 A}{\b\i \f10 \fs17 ,}{\i R,}{\fs18 C,} and{\i \f
s18
0)} can then be turned on
19 (HIGH}{\f10 \fs14 =}{\fs19 on)} in sequence as the ring counter shifts.
\fi22 {\f10 \fs16 SOLVED}{\f10 \fs16 PROBLEMS }
0 {\b \f10 \fs17 11.10} Refer{\fs18 to} Fig. 11-5. The parallel-load recircu
lating register uses four{\i \fs19
(}{\i \fs19 D}{\i \fs19 ,}{\i
\fs19 J}{\i \fs19 K}{\i \fs19 )} flip-flops \par
}
ith asynchronous
}
d \par
}
puts. \par
}
\cf0 The register shown in Fig.{\fs16 11-5} uses four{\b\i \fs17 JK}
flip-flops{\fs16 with} asynchronous clcar{\fs17 (CLR)} and preset
i \fs17 (}{\b\i \fs17 P}{\b\i \fs17 S}{\b\i \fs17 )} inputs. \par
}
cf0 11.11{\b0 \f20 \fs18 Refer}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 Fig.}{\b
0 \f20 \fs18 11-5.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 asynchronous}{\b0 \f
20 \fs18 inputs}{\i \f20 \fs19 (}{\i \f20 \fs19 P}{\i \f20 \fs19 S}{\b0 \f20
\fs18 and}{\b0 \f20 \fs18 CLR)}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 the}{\b
0\i \f20 \fs19 JK}{\b0 \f20 \fs18 flip-flops}{\b0 \f20 \fs18 have}{\b0 \f20
\fs18 active- }
i1277 {\b0 \f20 \fs19 (HIGH,}{\b0 \f20 \fs19 LOW)}{\b0 \f20 \fs18 inputs. }
0 \fi593 {\f20 \fs17 Solution: }
i945 {\b0 \f20 \fs17 The}{\b0 \f20 \fs17 asynchronous}{\b0 \f20 \fs17 inputs}
{\b0 \f20 \fs16 to}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 flip-flops}{\b0 \f2
0 \fs17 shown}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs17 11-5
}{\b0 \f20 \fs17 have}{\b0 \f20 \fs17 active-LOW}{\b0 \f20 \fs17 inputs. }\pa
r
}
cf0 11.12{\b0 \f20 \fs18 Refer}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 Fig.}{\b0
\f20 \fs18 11-5.This}{\b0 \f20 \fs18 register}{\b0 \f20 \fs18 is}{\b0 \f20 \f
s18 a}{\b0 \f20 \fs18 shift- }\par
}
utput{\i \fs19 Q} of
}
FF1,{\fs18 FF4)}{\fs18 to }\par
}
\cf0 (left, right) device because it shifts data from
\par}{\phpg\posx5305\pvpg\posy9623\absw4491\absh427 \sl-240 \f20 \fs18 \cf0 (FF1
, FF4). \par
}
The register shown in Fig. 11-5 is a shift-right device because{\fs16 it}
shifts data from FF1 to FF4. \par
}
\cf0 11.13{\b0 \f20 \fs18
b0 \f20 \fs18 11-5.}{\b0 \f20 \fs18 It}{\b0 \f20 \fs18 takes }
fi592 {\f20 \fs17 Solution: }\par
}
clock pulse(s) to load a 4-bit number in this shift register. \par
}
7 \cf0 It takes zero clock pulses to load the register shown in{\b \fs
16 Fig.}{\fs17 11-5.} The{\b\i \fs17 PS} (parallel-load) inputs are
\par}{\phpg\posx1479\pvpg\posy11757\absw8246\absh381 \sl-209 \f20 \fs17 \cf0 asy
nchronous and therefore do not need a clock pulse to load the register
. \par
}
\cf0 11.14{\b0 \f20 \fs18 Refer}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 Fig.}{\b0
\f20 \fs18 11-5.}{\b0 \f20 \fs18 The}{\i \f20 \fs19 JK}{\b0 \f20 \fs18 f
lip-flops}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 always}{\b0 \f20 \fs18 in}{\b0
\f20 \fs18 either}{\b0 \f20 \fs18 the }
fi586 {\b0 \f20 \fs18 this}{\b0 \f20 \fs18 register. }

}
r the \par
}
ode in \par
}
The{\b\i \fs17 JK} flip-flops are always in either the reset or set mo
de in the register shown in Fig. 11-5. \par
}
. 111 \par
}
IFT REGISTERS \par
}
\par
}
\cf0 11.15{\b0 \fs19 The}{\i \fs19 JK}{\b0 \fs19 flip-flop}{\b0 \fs19 is}{
\b0 \fs19 in}{\b0 \fs19 its}{\b0 \fs19 set}{\b0 \fs19 mode}{\b0 \fs19 when}
{\b0 \fs19 input}{\i J}{\i = }
fi940 {\b0 \fs17 The}{\i \f30 \fs19 JK}{\b0 \fs17 flip-flop}{\b0 \fs17 is}{\
b0 \fs17 in}{\b0 \fs17 its}{\b0 \fs17 set}{\b0 \fs17 mode}{\b0 \fs17 when
}{\i \fs17 J}{\b0 \f10 \fs14 =}{\b0 \fs17 1}{\b0 \fs17 and}{\b0\i \fs18
K }
f0 11.16{\b0 \fs19 The}{\i \fs19 JK}{\b0 \fs19 flip-flop}{\b0 \fs19 is}{\b
0 \fs19 in}{\b0 \fs19 its}{\b0 \fs19 reset}{\b0 \fs19 mode}{\b0 \fs19 when}
{\b0 \fs19 input}{\i \fs19 J}{\b0 \f10 \fs14 = }
}
f20 \fs18 (0,}{\f20 \fs19 1)}{\f20 \fs19 and}{\f20 \fs19 input}{\b\i \f20
\fs19 K}{\fs14 = }\par
}
,{\fs19 1). }\par
}
\f20 \fs17 0. }\par
}
0,{\fs18 1)}{\fs19 and}{\fs19 input}{\b\i \fs19 K}{\f10 \fs14 = }\par
}
cf0 (0,{\b0 \fs19 1). }\par
}
\cf0 The{\b\i \fs17 JK} flip-flop{\b is}{\fs17 in} its reset mode when{
\b\i \fs17 J}{\f10 \fs13 =}{\fs16 0} and{\i \fs17 K}{\f10 \fs13 =} 1.

{\b \fs18 11.17}{\fs19 List}{\fs19 the}{\fs19 state}{\fs18 of}{\fs19 the}{
\fs19 output}{\fs19 indicators}{\b\i \fs19 after}{\fs19 each}{\b \fs19 clo
ck}{\fs19 pulse}{\fs19 on}{\fs19 the}{\fs19 shift-right}{\fs19 register}{\f
s19 shown}{\fs19 in }
89 {\fs19 Fig.}{\fs18 11-7. }
39 The outputs of the register shown in Fig. 11-7 after each clock puls
e are as follows: \par
}
ulse{\b\i \fs16 a}{\f10 \fs13 =}{\fs17 000 }
pulse{\b\i \fs17 b}{\f10 \fs13 =} 010 \par
}
lse{\b\i \f30 \fs18 f }\par
}
\f20 \fs17 000 }\par
}
lear mode resets all FFs
\par}{\phpg\posx7507\pvpg\posy4999\absw2155\absh423 \sl-256 \f20 \fs17 \cf0 to 0
. \par
}
ulse{\fs16 c}{\f10 \fs13 =} 001 \par
}
ulse{\b\i \fs17 d}{\f10 \fs13 =} 100 \par
}
ulse{\b\i \fs17 e}{\f10 \fs13 =} 010 \par
}
Clear mode resets all FFs
0.
\par}{\phpg\posx2783\pvpg\posy4999\absw2158\absh3652 \sl-253 \f20 \fs17 \cf0 Par
allel-load
mode
sets
puts to 100. On trailing
\par}{\phpg\posx2783\pvpg\posy4999\absw2158\absh3652 \sl-258 \f20 \fs17 \cf0 edg
e of pulse, register shifts
\par}{\phpg\posx2783\pvpg\posy4999\absw2158\absh3652 \sl-259 \f20 \fs17 \cf0 rig
ht one position to 010.
ft-right mode shifts{\b bits }
{\fs17 0} at{\b\i \f30 \fs19 C} is recirculated
\par}{\phpg\posx2783\pvpg\posy4999\absw2158\absh3652 \sl-251 \f20 \fs17 \cf0 bac
k to{\b\i \f10 \fs16 A. }
ft-right mode shifts bits

{\fs17 1} at{\b\i \fs17 C} is recirculated
\par}{\phpg\posx2783\pvpg\posy4999\absw2158\absh3652 \sl-261 \f20 \fs17 \cf0 bac
k to{\b\i \fs17 A. }
ft-right mode shifts bits
position to the right. \par
}
pulse{\b\i \f10 \fs14 g}{\f10 \fs13 =} 101
Temporarily
the
parallel
1290 load inputs{\b\i \fs17
B} and{\b\i \fs17 C} load
1290 011 into the register. On
1290 the
trailing
edge of
the
1287 clock pulse, the shift-right
1287 mode causes the
bits to
1290 shift right one position. The
1302 {\fs17 1} at{\b\i \fs17
C} is recirculated to
1290 position{\b\i \f10 \fs16 A. }
se{\b\i \fs17 h}{\f10 \fs14 =}{\fs17 110}
Shift-right mode. The{\fs17
1} at
1296 {\b\i \fs17 C} is recirculated back to{\b\i \f10 \fs15 A. }\par
}
ulse{\b\i \f30 \fs18 i}{\f10 \fs14 =} 011
e{\fs15 j}{\f10 \fs14 =} 111 \par
}
hift-right mode.
\par}{\phpg\posx7513\pvpg\posy8337\absw2157\absh641 \sl-251 \f20 \fs17 \cf0 Para
llel-load mode loads all
\par}{\phpg\posx7513\pvpg\posy8337\absw2157\absh641 \sl-245 \f20 \fs17 \cf0 FFs
with a 1. \par
}
}
cf0 1
0 {\fs12 1 }\par
}
J
\par}{\phpg\posx2545\pvpg\posy10023\absw368\absh619 \sl-374 \f10 \fs24 \cf0 pJ \
par
}
cf0 1
0 {\f20 \fs13 I }\par
}
\cf0 Parallel\par}{\phpg\posx5247\pvpg\posy9986\absw1054\absh463 \sl-154 \f20 \fs13 \cf0 {\f3
0 \fs11 1}
data (load)
\fi458 {\b \f10 \fs8 L }\par
}
{\phpg\posx5245\pvpg\posy10551\absw276\absh82 \f10 \fs6 \cf0 \f10 \fs6 \cf0 --t
\par
}
JTT \par
}
s13 \cf0 B \par
}
cf0 1 \par
}
\par
}
\cf0 I
\f20 \fs31 d }\par
}
f20 \fs13 \cf0 - J P S Q
\fi490 {\i0 \fs13 FF}{\b0\i0 \fs13 I }
{\b0\i0 \f10 \fs19 -+>}{\i0 \fs13
CLK }
\fi73 {\b0\i0 \f10 \fs24 r}{\i0 \fs13 KCLR}{\b0\i0 \fs11 Q}{\b0\i0 \fs11 ,
}\par
}
0 L \par
}
19 -> }\par
}
\f10 \fs8 \cf0 D
\fi85 {\f20 \fs13 J}{\f20 \fs13 P}{\f20 \fs13 S}{\f20 \fs13 Q }
\fi270 {\i0 \f20 \fs13 FF2 }
\fi171 {\i0 \f20 \fs13 CLK }

\cf0 {\i0 \f20 \fs13 -}{\i0 \f20 \fs13 K}{\i0 \f20 \fs13 c}{\i0 \f20 \fs13 L}
{\i0 \f20 \fs13 R}{\i0 \f20 \fs13 Q}{\i0 \f20 \fs13 . }
\fi337 {\fs8 0 }\par
}
s11 \cf0 5
{\b0\i0 \fs18 +> }\par
}
14 \cf0 J \par
}
\f20 \fs12 \cf0 h
\fi107 {\fs15 "}{\fs15 Q}{\fs15 - }
\fi75 {\i0 \fs14 FF3 }
{\i0 \fs13 CLK }\par
}
\par
}
\cf0 ~ K C L R Q ~
\fi353 {\i \f30 \fs10 0 }\par
}
\par
}
{\f20 \fs13 Clock }\par
}
\par
}
cf0 1 \par
}
A-A
3702 {\b\i \f20 \fs13 J}{\b\i \f20 \fs13 K}{\b \f20 \fs12
flip-flops}{\f20
\fs13 are}{\f20 \fs13 pulse}{\f20 \fs13 triggered }
\fi670 {\b \f20 \fs17 Fig.}{\b \f20 \fs17 11-7}{\f20 \fs17
Parallel-load}{\
f20 \fs17 shift-register}{\f20 \fs17 pulse-train}{\f20 \fs17 problem }\par
}
\cf0 0 \par
}
cf0 1 \par
}
Iear \par
}
0 268 \par
}
IFT REGISTERS \par
}
AP.{\fs16 11 }\par
}
\cf0 11.18{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 11-7.}{\b0 What}{\b0 is}{
\b0 the}{\b0 mode}{\b0 of}{\b0 operation}{\b0 of}{\b0 each}{\b0 fl
ip-flop}{\b0 while}{\b0 clock}{\b0 pulse}{\i c}{\b0 is }
fi585 {\b0 HIGH? }
fi944 {\b0 \fs17 The}{\b0 \fs17 modes}{\b0 \fs17 of}{\b0 \fs17 operation}{\
b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 flip-flopswhile}{\b0 \fs17 clock}{
\b0 \fs17 pulse}{\f10 \fs13 c}{\b0 \fs17 is}{\b0 \fs17 HIGH}{\b0 \fs17 (
Fig.}{\b0 \fs16 11}{\b0 \fs17 -7)}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \fs17
follows: }
fi3435 {\b0 \fs16 FF1}{\b0 \fs17 mode}{\b0 \f10 \fs13 =}{\b0 \fs17 reset}{\i
\fs16 (}{\i \fs16 J}{\b0 \f10 \fs13 =}{\b0 \fs16 0,}{\i \fs17 K}{\b0 \f10
\fs13 =}{\b0 \fs16 1) }\par
}
2 mode{\dn006 \f10 \fs11 = }
\par}{\phpg\posx4345\pvpg\posy2879\absw971\absh491 \sl-166 \par\f20 \fs17 \cf0 F
F3 mode{\dn006 \f10 \fs11 = }\par
}
set{\b\i \fs16 (}{\b\i \fs16 J}{\dn006 \f10 \fs11 = }\par
}
{\i \fs17 K}{\dn006 \f10 \fs11 =}{\fs16 1) }\par
}
et{\fs16 (J}{\dn006 \f10 \fs11 =} 1,{\fs17 K}{\f10 \fs13 =} 0) \par
}
\cf0 11.19{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 11-7.}{
\b0 \fs18 What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 mode}{\b0 \fs19 of}{
\b0 \fs18 operation}{\b0 \fs18 of}{\b0 \fs18 each}{\b0 \fs18 flip-flop}{\b
0 \fs18 when}{\b0 \fs18 pulse}{\b0\i \f10 \fs16 j}{\b0 \fs18 is}{\b0 \fs19
HIGH? }
fi950 {\b0 \fs17 All}{\b0 \fs17 flip-flops}{\b0 \fs17 are}{\b0 \fs17 being}
{\b0 \fs17 asynchronously}{\b0 \fs17 preset}{\b0 \fs17 by}{\b0 \fs17 the}
{\b0 \fs17 active}{\b0 \fs17 parallel-data}{\b0 \fs17 inputs.}{\b0 \fs17
All}{\b0 \fs17 flip-flops}{\b0 \fs17 are}{\b0 \fs17 in }
fi594 {\b0 \fs17 the}{\b0 \fs17 set}{\b0 \fs17 mode}{\i \fs17 (}{\i \fs17
J}{\b0 \f10 \fs13 =}{\b0 \fs17 1,}{\b0\i \fs17 K}{\b0 \f10 \fs13 =}{\b0 \fs17
0). }
f0 {\f10 \fs17 11.20}{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \f
s18 11-7.}{\b0 \fs18 This}{\b0 \fs18 digital}{\b0 \fs18 device}{\b0 \fs18
is}{\b0 \fs18 a}{\b0 \fs18
-bit}{\b0 \fs18
(nonreci
rculating,}{\b0 \fs18 recirculating) }\par
}
ift\par}{\phpg\posx1471\pvpg\posy5455\absw803\absh507 \sl-334 \f20 \fs18 \cf0 {\b \
}
left, right) register. \par
}
he digital device shown in Fig. 11-7is a 3-bit, recirculating shift-right
register. \par
}
\cf0 11-4{\f30 \fs21 TTL}{\fs18 SHIFI'}{\fs18 REGISTERS }
fi360 {\b0 Integrated-circuit}{\b0 manufacturers}{\b0 market}{\b0 many}{\b0
shift}{\b0 registers.}{\b0 The}{\b0 one}{\b0 that}{\b0 has}{\b0 been}{\b0
selected}{\b0 for }
\b0 description}{\b0 is}{\b0 a}{\b0 universal}{\b0 shift}{\b0 register
.} A{\b0 block}{\b0 logic}{\b0 symbol}{\b0 for}{\b0 the}{\b0 commerc
ial}{\b0 TTL}{\b0 74194}{\b0 4-bit }
\b0 universal}{\b0 shift}{\b0 register}{\b0 is}{\b0 shown}{\b0 \fs19 i
n}{\b0 Fig.}{\b0 11-8.}{\b0 The}{\b0 74194}{\b0 register}{\b0 has}{\b
0 10}{\b0 inputs}{\b0 and}{\b0 \fs18 4}{\b0 outputs.}{\b0 The }
\b0 \fs18 outputs}{\b0 are}{\b0 connected}{\b0 to}{\b0 the}{\b0 normal}{\b0
\f10 \fs18 ((2)}{\b0 outputs}{\b0 of}{\b0 each}{\b0 flip-flop}{\b0 insid
e}{\b0 the}{\b0 \fs19 IC. }
fi364 {\b0 Consider}{\b0 the}{\b0 inputs}{\b0 \fs18 on}{\b0 the}{\b0 74194}
{\b0 register}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0 11-8.The}{\b0 parallel-loa
d}{\b0 inputs}{\i \f10 \fs17 (}{\i \f10 \fs17 A}{\i \f10 \fs17 ,}{\b0\i B,}{
\b0 \fs18 C,}{\i \f30 \fs20 D) }
\b0 are}{\b0 the}{\b0 top}{\b0 four}{\b0 inputs.}{\b0 The}{\b0 next}{\b0
two}{\b0 inputs}{\b0 are}{\b0 for}{\b0 feeding}{\b0 data}{\b0 into}{\b0 t
he}{\b0 register}{\b0\i serially}{\b0 (one}{\b0 bit}{\b0 at}{\b0 a }
\b0 time).}{\b0 The}{\b0 shift-right}{\b0 serial}{\b0 input}{\i (DSR)}{\b0
feeds}{\b0 bits}{\b0 into}{\b0 position}{\i \f10 A}{\b0\i (Q,)}{\b0 as}{
\b0 the}{\b0 register}{\b0 is}{\b0 shifted}{\b0 to}{\b0 the }
\b0 right.}{\b0 The}{\b0 shift-left}{\b0 serial}{\b0 input}{\i \fs19 (DsL)
}{\b0 feeds}{\b0 bits}{\b0 into}{\b0 position}{\i \fs19 D}{\b0\i (Qu)}{\b
0 as}{\b0 the}{\b0 register}{\b0 is}{\b0 shifted}{\b0 to}{\b0 the }
\b0 left.}{\b0 The}{\b0 clock}{\b0 input}{\b0 (CLK)}{\b0 triggers}{\b0 t
he}{\b0 four}{\b0 flip-flops}{\b0 on}{\b0 the}{\b0 L-to-H}{\b0 transi
tion}{\b0 of}{\b0 the}{\b0 clock}{\b0 pulse. }
\b0 When}{\b0 activated}{\b0 with}{\b0 a}{\b0 LOW,}{\b0 the}{\b0 cle

ar}{\b0 (CLR)}{\b0 input}{\b0 resets}{\b0 each}{\b0 flip-flop}{\b0 to}
{\b0 \fs18 0.}{\b0 The}{\b0 mode}{\b0 controls }\par
}
Output{\fs14 indicators }\par
}
\cf0 Parallel\par}{\phpg\posx3481\pvpg\posy11207\absw1537\absh812 \sl-172 \f20 \fs14 \cf0 \fi
186 load
\fi21 Shift-right
ial input{\i \f30 \fs16 7 }\par
}
\cf0 Shift-left
ial input
340 Clock{\f10 \fs24 -!-- }\par
}
>DSL \par
}
s10 \cf0 D S R \par
}
\cf0 2 \par
}
\cf0 CLK \par
}
\par
}
\cf0 1) \par
}
nputs \par
}
\cf0 (74194) \par
}
LRS, \par
}
s15 \cf0 S, \par
}
5 \cf0 controls{\b\i \fs21 (s,}{\f10 \fs17 I }
{\b \fs16 Fig.}{\b \f10 \fs15 11-8}{\fs17
Logic}{\fs17 symbol}{\fs17 for}
{\fs17 the}{\fs17 74194}{\fs17 universal}{\fs17 shift-register}{\fs17 IC }\
par
}
.{\b 111 }\par
}
cf0 SHIFT{\fs17 REGISTERS }\par
}
f0 269 \par
}
nstruct the register through a gating network to shift right, shift l
eft, parallel-load, or hold (do
\par}{\phpg\posx893\pvpg\posy1357\absw9050\absh1278 \sl-237 \f20 \fs18 \cf0 noth
ing). Of course, the 74194, which is a TTL IC, has a{\i \fs19 +5}{\b \fs18 V
} and GND power-supply connection.
power-supply connections are not usually shown on the logic symbol.
54 {\b \fs18 A} mode-select-function table for the 74194 shift register
is shown in Fig. 11-9. The operating
\par}{\phpg\posx893\pvpg\posy1357\absw9050\absh1278 \sl-237 \f20 \fs18 \cf0 mode
s for the shift register are listed in the left section of the table. The opera
ting modes are reset,
, shift-left, shift-right, and parallel-load. \par
}
\par
}
\par
}
cf0 Inputs \par
}
\par
}
cf0 X I L \par
}
cf0 outputs \par
}
0 \fs17 \cf0 Operating
\fi495 mode
cf0 Reset (clear)
cf0 {\fs17 Hold} (do nothing)
Shift{\b0 \f10 \fs19 -}left
cf0 Shift-right \par
}
cf0 x \par
}
cf0 L \par
}
cf0 ( x \par
}
cf0 X I X \par
}
cf0 x \par
}
cf0 L \par
}
cf0 L \par
}
cf0 L \par
}
\fs17 \cf0 Parallel-load
cf0 {\fs15 H}{\b0 \f10 \fs13 =}{\fs15 HIGH}{\fs15 voltage}{\fs15 level }
{\fs15 h}{\b0 \f10 \fs13 =}{\fs15 HIGH}{\fs15 voltage}{\fs15 level}{\fs15 o
ne}{\fs15 setup}{\fs15 time}{\fs15 prior}{\fs15 to}{\fs15 the}{\fs15 L-toH}{\fs15 clock}{\fs15 transition }
{\fs15 L}{\b0 \f10 \fs13 =}{\fs15 LOW}{\fs15 voltage}{\fs15 level }
{\f10 \fs14 1}{\b0 \f10 \fs13 =}{\fs15 LOW}{\fs15 voltage}{\fs15 level}{\f
s15 one}{\fs15 setup}{\fs15 time}{\fs15 prior}{\fs14 to}{\fs15 the}{\fs15
L-to-H}{\fs15 clock}{\fs15 transition }
{\i \f10 \fs13 d,(q,)}{\b0 \f10 \fs11
=}{\fs15 (Lowercase}{\fs15 letters}{\
fs15 indicate}{\fs15 the}{\fs15 state}{\fs14 of}{\fs15 the}{\fs15 referenc
ed}{\fs15 input}{\b0 \fs15 [or}{\fs15 output]}{\fs15 one}{\fs15 setup }
\fi596 {\fs15 time}{\fs15 prior}{\fs15 to}{\fs15 the}{\fs15 L-to-H}{\fs15 c
lock}{\fs15 transition.) }
{\fs15 X}{\b0 \f10 \fs13 =}{\fs15 don't}{\fs15 care }
{\b0 \fs19 t}{\b0 \f10 \fs13 =}{\fs15 L-to-H}{\fs15 clock}{\fs15 transitio
n }
{\b0 \f10 \fs19 *}{\fs15 The}{\fs15 H-to-L}{\fs15 transition}{\b0 \fs15 of}{
\fs15 the}{\i \fs14 S}{\i \fs14 o}{\fs15 and}{\i \fs15 S}{\i \fs15 ,}{\fs1
5 inputs}{\fs15 on}{\fs15 the}{\fs14 74194}{\fs15 should}{\fs15 only}{\fs
15 take}{\fs15 place}{\fs15 while }
\fi133 {\i \fs15 CK}{\fs15 is}{\fs15 HIGH}{\fs15 for}{\fs15 conventional}{
\fs15 operation. }
cf0 \fi121 {\fs16 Fig.}{\fs16 11-9}{\fs17
Mode} select/function table for
the{\fs16 74194} universal shift-register{\fs17 IC }\par
}
\cf0 Consider the reset (clear) mode of the shift register shown in Fig. 119. When the CLR input is
\par}{\phpg\posx873\pvpg\posy9919\absw9029\absh3619 \sl-230 \f20 \fs18 \cf0 LOW,
{\fs18 it} overrides all other inputs (all other inputs are{\b \fs19 X}{\fs19
on} the table) and clears the outputs to 0000
\par}{\phpg\posx873\pvpg\posy9919\absw9029\absh3619 \sl-243 \f20 \fs18 \cf0 (sho
wn as LLLL in table). Note that the outputs are identified with a{\i \fs18 Qo
} instead of{\b\i \f10 \fs12
Q}{\b\i \f10 \fs12 A}{\b\i \f10 \fs12 ,}{\b\i
\f10 \fs12 Q}{\b\i \f10 \fs12 l }
\fs18 so} forth. Identification of inputs and outputs does vary from manufac
turer to manufacturer.
59 The remaining four modes of operation shown in Fig.{\fs18 11}{\fs18 -9} are
controlled by the mode controls{\fs18 (So }
\i \fs18 S,).} When both mode controls are LOW{\fs18 (So}{\dn006 \f10 \fs
13 =}{\fs18 0,}{\b\i \fs18 S}{\b\i \fs18 ,}{\dn006 \f10 \fs13 =}{\fs18 0)
,} the shift register is in the hold mode
will do nothing. The table shows that the outputs (at{\i \fs18 Qo} through{\i
\fs18 Q3)}are displayed, however.
65 Consider the shift-left line in Fig. 11-9. The two mode controls are set
properly{\i \f10 \fs17 (So}{\dn006 \f10 \fs13 =}{\fs18 0,}{\b\i \fs18 S}{\b\
i \fs18 ,}{\f10 \fs13 =}{\fs18 l), }
data is fed into{\fs18 the} shift-left serial input{\i \fs19 (DsL).}Not
e that the 1s and{\b \fs18 OS} at the shift-left serial
t are transferred to the{\i \fs18 Q3}{\b\i \f30 \fs21 (D)}position as the regis
ter shifts one place to the left. The shift takes
e on the L-to-H transition of the clock pulse,{\fs18 as} shown by the arrow poi
nting upward on the table.
72 Look at the shift-right line in Fig. 11-9.The mode controls are set{\i \fs18
(So}{\f10 \fs14 =} 1,{\i \fs18 S}{\i \fs18 ,}{\f10 \fs14 =}{\fs18 0).} Data
is placed
he shift-right serial input{\i \fs19 (DSR).}On the L-to-H transition{\b \fs18
of} the clock pulse, the bit at input{\b\i \fs19 DSR}is
sferred to the{\i \fs18 Qo}{\b\i \fs19 (}{\b\i \fs19 A}{\b\i \fs19 )}outpu
t as the register shifts one place to the right.
60 The final operating mode for the universal shift register is shown on the bo
ttom line in Fig. 11-9.
19 To} parallel load (also called{\b\i \fs18 broadside}{\b\i load)} the 7
4194 register, set the{\fs18 two} mode controls{\fs18 (So}{\f10 \fs14 =}
1,
\fs18 S}{\i \fs18 ,}{\f10 \fs14 =} 1). On the L-to-H transition{\fs18 of
} the clock pulse, the data at the parallel-load inputs will be \par
}
or{\b\i \fs17 QB, }\par
}
\par
}
IFT{\fs17 REGISTERS }\par
}
AP.{\fs17 11 }\par
}
ransferred to the appropriate outputs. Note that the parallel-load input
s are{\b\i \fs18 not} asynchronous as
\par}{\phpg\posx855\pvpg\posy1358\absw9000\absh3657 \sl-237 \f20 \fs19 \cf0 they
were on the previous parallel-load register. The parallel-load operation takes
place in step with a
\par}{\phpg\posx855\pvpg\posy1358\absw9000\absh3657 \sl-235 \f20 \fs19 \cf0 sing
le clock pulse.
60 The 74194 register is indeed universal. Data can be loaded either serially or
in parallel. Data can
read out in parallel or in serial form [output from one point such as{\b\i
\fs18 QD}{\b\i \fs18 (Q,)].}The register can
(or do nothing) on command. The register can shift right or shift left. Thi
s 4-bit register{\fs18 is} but
of many units manufactured in{\fs19 IC} form.
56 {\b A} few other{\fs19 TTL} shift registers include the 7494 4-bit and 7496
5-bit shift registers.{\b \fs18 Also} listed in
manuals are the 74164 8-bit serial-in, parallel-out and 74165 8-bit serial
/parallel-in, serial-out
t registers. Other shift registers are available from chip manufacturer
s in the various TTL
\par}{\phpg\posx855\pvpg\posy1358\absw9000\absh3657 \sl-238 \f20 \fs19 \cf0 subf
amilies such as the 74LS395A 4-bit cascadeable shift register with 3-state outp
uts.
{\b \f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }
\f30 \fs19 11.21} List the five modes of operation of the 74194 shift register
.
56 {\fs17 The}{\fs17 five}{\fs17 modes}{\fs17 of}{\fs17 operation}{\fs17
of}{\fs17 the}{\fs17 74194}{\fs17 register}{\fs17 are}{\fs17 as}{\fs1
7 follows: }\par
}
s15 \cf0 (a){\b0\i0 \f20 \fs17
reset}{\b0\i0 \f20 \fs17 (clear) }
{\b0 \f20 \fs16 (b)}{\b0\i0 \f20 \fs17
hold }\par
}

) \par
}
ift-left \par
}
s16 \cf0 ( e ){\b0\i0 \fs17
parallel-load }\par
}
s17 \cf0 ( d ){\b0\i0 \fs17
shift-right }\par
}
cf0 11.22{\b0 \f20 \fs19
Refer}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 Fig.}{\b0
\f20 \fs19 11-9.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 single}{\b0 \f20 \fs19
asynchronous}{\b0 \f20 \fs19 input}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 the}{\
b0 \f20 \fs19 74194}{\b0 \f20 \fs19 register}{\b0 \f20 \fs19 that}{\b0 \f20 \
fs19 overrides}{\b0 \f20 \fs19 all}{\b0 \f20 \fs19 other }\par
}
nputs is the
}
put. \par
}
\cf0 The clear is the only asynchronous input on the 74194 register.
{\b \f30 \fs19 11.23}{\fs19
Refer}{\fs19 to}{\fs19 Fig.}{\fs19 11-9.}{\fs1
9 What}{\fs19 effect}{\fs19 does}{\fs19 a}{\fs19 clock}{\fs19 pulse}{\fs1
9 have}{\fs19 when}{\fs19 the}{\fs19 74194}{\fs19 register}{\b \fs18 is}{
\fs19 in}{\fs19 the}{\fs19 hold }
89 {\fs19 mode? }
50 The 74194 register does nothing on a clock pulse when it is in the ho
ld mode. \par
}
cf0 11.24{\b0 \f20 \fs19 Refer}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 Fig.}{\b0
\f20 \fs19 11-9.It}{\b0 \f20 \fs19 takes }
}
lock pulse(s) to parallel load four bits in the 74194 register. \par
}
\cf0 It takes one clock pulse to parallel load the 74194 shift register.
\b \f30 \fs19 11.25}{\fs19
The}{\fs19 74194}{\fs19 input}{\fs19 labeled}{\
b\i \f30 \fs21 D,,}{\fs19 would}{\fs19 be}{\fs19 used}{\fs19 when}{\b \fs
19 So}{\dn006 \f10 \fs14 = }
}

0,{\fs19 1)}{\fs19 and}{\b\i \fs19 S}{\b\i \fs19 ,}{\f10 \fs14 = }\par
}
,{\fs18 1). }\par
}
7 \cf0 The{\b\i \f30 \fs19 D,,} input (shift-right serial input) would b
e used during the shift-right mode, and therefore
\i \f10 \fs15 So}{\f10 \fs13 =}{\fs17 1} and{\b \f10 \fs15 S,}{\f10 \fs13
=}{\fs17 0. }\par
}
\cf0 11.26{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 74194}{\b0 \f20 \fs19 register
}{\b0 \f20 \fs19 uses }
}
(positive-edge, pulse) triggering. \par
}
7 \cf0 The 74194 register uses positive-edge triggering.
{\b \f30 \fs19 11.27}{\fs19 List}{\fs19 the}{\fs19 operating}{\fs19 mode}{
\fs19 of}{\fs19 the}{\fs19 shift}{\fs19 register}{\fs19 (74194)}{\fs19 for
}{\fs19 each}{\fs19 of}{\fs19 the}{\fs19 pulses}{\fs19 shown}{\fs19 in}{\f
s19 Fig.}{\fs19 11-10. }
954 Refer to the{\b \f10 \fs15 S,} and{\b \fs16 So} columns{\fs16 of} t
he mode-select table in Fig. 11-9. The operating mode of the
594 register for each pulse shown in Fig. 11-10is as follows: \par
}
pulse{\b\i \fs17 a}{\f10 \fs13 =} reset (clear)
se{\i b}{\f10 \fs13 =} parallel-load
se{\b\i \fs17 c}{\f10 \fs13 =} shift-left \par
}
pulse{\b\i \fs16 d}{\f10 \fs13 =} shift-left
se{\b\i \fs17 e}{\f10 \fs13 =} shift-left
se{\fs17 f}{\f10 \fs13 =} shift-right \par
}
pulse{\b\i \fs16 g}{\dn006 \f10 \fs11
=} shift-right
se{\b\i h}{\f10 \fs13 =} reset (clear)
se{\b\i \f30 \fs17 i}{\f10 \fs13 =} hold \par
}
pulse{\i \f10 \fs15 j}{\f10 \fs13 =} shift-left \par
}
\cf0 CHAP.{\b0\i0 111 }\par
}
IFT{\b \fs17 REGISTERS }\par
}
f0 271 \par
}
}
rallel
loads \par
}
{\phpg\posx7887\pvpg\posy1948\absw203\absh265 \f10 \fs22 \cf0 \f10 \fs22 \cf0 -.
\par
}
\par
}
\par
}
\par
}
cf0 0
i0 \f20 \fs14 0 }
i34 {\i0 \f20 \fs14 I }
i34 {\b\i0 \fs14 1 }\par
}
13 \cf0 - A
\fi93 {\f20 \fs15 B }
\par}{\phpg\posx6571\pvpg\posy2264\absw251\absh674 \sl-150 \par\par\b\i \f10 \fs
13 \cf0 \fi87 {\b0\i0 \f20 \fs15 D }\par
}
cf0 Shift
\par}{\phpg\posx7069\pvpg\posy2374\absw547\absh323 \sl-170 \f20 \fs15 \cf0 regis
ter \par
}
}
0 Q A \par
}
cf0 0 \par
}
\par
}
cf0 1 \par
}
L L \par
}
0 Q B \par
}
cf0 Qc{\i0 \fs23 - }\par
}
\par
}
\par
}
\par
}
\cf0 Right
33 serial input'
0 \fs26 L }\par
}
14 \cf0 D s ~ \par
}
\cf0 10 \par
}
\fs31 I }\par
}
cf0 0 \par
}
par
}
{\phpg\posx4654\pvpg\posy5077\absw55\absh158 \f20 \fs14 \cf0 \f20 \fs14 \cf0 l \
par
}
par
}
ear \par
}
41{\b \f10 \fs13 94) }\par
}
}
\par
}
\cf0 S,{\i0 \f20 \fs15
Mode}{\i0 \f20 \fs15 controls }\par
}
cf0 0 \par
}
cf0 1 \par
}
\par
}
cf0 0 \par
}
cf0 1 \par
}
\cf0 Fig.{\f10 \fs15 11-10}{\b0
Shift-register}{\b0 pulse-train}{\b0 prob
lem }\par
}
cf0 11.28{\b0 \fs19 List}{\b0 \fs19 the}{\b0 \fs19 state}{\b0 \fs19 of}{\
b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 indicators}{\b0 \fs19 after}{\
b0 \fs19 each}{\b0 \fs19 pulse}{\b0 \fs19 for}{\b0 \fs19 the}{\b0 7419
4}{\b0 \fs19 shift}{\b0 \fs19 register}{\b0 \fs19 shown}{\b0 \fs13 In }
i592 {\b0 \fs19 Fig.}{\b0 \fs19 11-10. }
i946 {\b0 \fs17 The}{\b0 \fs17 output}{\b0 \fs17 indicators}{\b0 \fs17 rea
d}{\b0 \fs17 as}{\b0 \fs17 follows}{\b0 \fs17 for}{\b0 \fs17 the}{\b0 \fs
17 register}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17
11-10}{\i \f10 \fs15 (}{\i \f10 \fs15 A}{\b0 \fs17 on}{\b0 \fs17 left,}{\i
\f30 \fs19 D}{\b0 \fs17 on}{\b0 \fs17 right): }\par
}
pulse{\b\i \f10 \fs15 a}{\f10 \fs14 =}{\fs17 0000}
Reset mode which
clears
1330 all outputs to 0.
se{\fs17 6}{\f10 \fs14 =} 0011
Parallel-load mode which
1331 loads four parallel-load in\par}{\phpg\posx1517\pvpg\posy7817\absw3500\absh3933 \sl-223 \f20 \fs17 \cf0 \fi
1331 puts into register.
se c{\f10 \fs13 =}{\b\i \f10 \fs16 03} 10
Shift-left mode moves bits
1340 one position to the left.

1343 Note that a{\fs17 0} is being seri\par}{\phpg\posx1517\pvpg\posy7817\absw3500\absh3933 \sl-212 \f20 \fs17 \cf0 \fi
1345 ally loaded into position D
1344 from the left serial input.
20 pulse{\b\i \fs17 d}{\f10 \fs13 =}{\b 1100}
Shift-left mode moves b
its
1340 one position to the
left.
1344 Note that a 0 is being seri\par}{\phpg\posx1517\pvpg\posy7817\absw3500\absh3933 \sl-219 \f20 \fs17 \cf0 \fi
1344 ally loaded into position{\b\i \f30 \fs19 D }
1340 from the left serial input.
se{\b \f10 \fs14 e}{\f10 \fs13 =} 1000
Shift-left mode moves bits
1340 one position to the left.
1343 Note that a 0 is being seri\par}{\phpg\posx1517\pvpg\posy7817\absw3500\absh3933 \sl-221 \f20 \fs17 \cf0 \fi
1344 ally loaded into position{\b\i \f30 \fs19 D }
1340 from the left serial input. \par
}
ulse{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =} 1100 \par
}
ulse{\i \f10 \fs14 g}{\f10 \fs13 =} 0110 \par
}
pulse{\b\i \fs17 h}{\dn006 \f10 \fs11 =}{\fs17 0000 }\par
}
pulse{\b\i \f30 \fs17 i}{\f10 \fs13 =}{\fs17 0000 }
pulse{\i \f10 \fs15 j}{\f10 \fs13 =} 0001 \par
}
Shift-right mode moves bits
e that a{\b \fs17 1} is being seri\par}{\phpg\posx7555\pvpg\posy7819\absw2171\absh3929 \sl-220 \f20 \fs17 \cf0 all
y loaded into position{\b\i \f10 \fs15 A }
m the right serial input.
e that a 0 is being seri\par}{\phpg\posx7555\pvpg\posy7819\absw2171\absh3929 \sl-210 \f20 \fs17 \cf0 all
y loaded into position{\b\i \f10 \fs15 A }

m the right serial input.
clear input overrides
other inputs and resets
outputs to 0.
\par}{\phpg\posx7555\pvpg\posy7819\absw2171\absh3929 \sl-230 \f20 \fs17 \cf0 Hol
d mode commands the
\par}{\phpg\posx7555\pvpg\posy7819\absw2171\absh3929 \sl-215 \f20 \fs17 \cf0 reg
ister to do nothing.
ft-left mode moves bits
position to the left.
e that a 1 is being seri\par}{\phpg\posx7555\pvpg\posy7819\absw2171\absh3929 \sl-218 \f20 \fs17 \cf0 all
y loaded into position{\b\i \f30 \fs19 D }
m the left serial input. \par
}
\cf0 11-5{\fs19
CMOS}{\fs19 SHIFT} REGISTERS
fi368 {\fs18 A}{\b0 wide}{\b0 variety}{\b0 of}{\fs19 CMOS}{\b0 shift}{\b0
registers}{\b0 are}{\b0 available}{\b0 from}{\b0 chip}{\b0 manufacturers.}{
\b0 The}{\i 7#HC16#}{\i \fs19 8-bit }
\i \fs19 serial-in}{\i \fs19 parallel-out}{\i \fs19 shift-register}{\i IC}{\b
0 is}{\b0 featured}{\b0 in}{\b0 this}{\b0 section.}{\b0 Information}{\
b0 from}{\b0 the}{\b0 manufacturer's }
\b0 data}{\b0 manual}{\b0 is}{\b0 reproduced}{\b0 in}{\b0 Fig.}{\b0 11-11
, }\par
}
\par
}
}
f0 [CHAP.{\b0 \fs16 11 }\par
}
cf0 8 \par
}
23 \cf0 MR \par
}
cf0 9 \par
}
cf0 Q7 \par
}

cf0 12
b0 13 }\par
}
\f20 \fs20 \cf0 4,
\cf0 \fi135 {\fs10 Dsb }
\cf0 \fi175 {\i0 \fs10 QO }
\cf0 \fi175 {\i0 \fs10 Qi }
\cf0 \fi175 {\i0 \fs10 Q2 }
\cf0 \fi175 {\i0 \fs10 Q3 }
\cf0 {\b0\i0 \fs15 GND }\par
}
\fs16 \cf0 vcc
f0 {\f10 \fs9 Q7 }
f0 {\b \fs10 Q6 }
f0 {\b \f10 \fs15 Q}{\b \f10 \fs15 5 }
f0 {\b\i0 \fs10 Q4 }
\fs29 m }
f0 {\b \fs15 CP }\par
}
9 \cf0 (U){\b0\i0 \f20 \fs15 Simplifiedlogic}{\i0 \f20 \fs15 symbol }\par
}
s15 \cf0 (b){\b0\i0 \fs15 Pin}{\b0\i0 \fs15 diagram }\par
}
\cf0 OSb \par
}
\f30 \fs11 \cf0 D
\cf0 {\f10 \fs7 4}{\f20 \fs10 CP }
\cf0 \fi308 {\i0 \f20 \fs10 FFl }
\cf0 \fi321 {\f10 \fs9 Ru }
\cf0 \fi360 {\b0\i0 \f10 \fs15 I1 }\par
}
cf0 Q \par
}
f0 . \par
}
f0 ; \par
}
par
}
\f30 \fs11 \cf0 D
\cf0 {\b0\i0 \f10 \fs10 --c}{\f20 \fs10 CP }
\cf0 \fi293 {\i0 \f20 \fs10 FF2 }
\fi315 {\f10 \fs9 Ru }
\cf0 \fi360 {\b0\i0 \f10 \fs15 I1 }\par
}
cf0 Q \par
}
f0 = \par
}
cf0 Q . \par
}
cf0 Q , \par
}
\par
}
12 \cf0 Q \par
}
2 \cf0 : \par
}
cf0 Q \par
}
f0 = \par
}
cf0 Q- \par
}
cf0 Q . \par
}
0 \cf0 CP
\b0\i0 \f10 \fs11 - }
\f30 \fs10 MR }\par
}
\par
}
\f30 \fs11 \cf0 D
\cf0 {\b0\i0 \f10 \fs10 -c}{\f20 \fs10
CP }
\cf0 \fi312 {\i0 \f20 \fs10 FF3 }
\fi318 {\f10 \fs9 RI, }
\fi353 {\i0 \f10 \fs16 Y }
\cf0 \fi360 {\i0 \fs9 1 }\par
}
\f10 \fs10 \cf0 D
\cf0 {\i0 \fs7 4}{\f20 \fs10 CP }
\cf0 \fi305 {\i0 \f20 \fs10 FF4 }
\fi324 {\fs9 RU }
\fi356 {\i0 \fs16 Y }
\cf0 \fi363 {\i0 \f30 \fs9 1 }\par
}
{\b\i \f30 \fs12
D }
\fi197 {\fs9 .-c}{\b\i \f20 \fs10
CP }
\fi503 {\b \f20 \fs10 FF5 }
28 {\b\i \fs9 RD }
76 {\b \f30 \fs6 A }
61 {\f20 \fs16 I}{\b \f30 \fs9 1 }\par
}
\f30 \fs11 \cf0 D
\cf0 {\i0 \f10 \fs7 4}{\f20 \fs10 CP }
\cf0 \fi297 {\i0 \f20 \fs10 FF6 }
\fi333 {\f10 \fs6 RD }
\fi356 {\i0 \f10 \fs16 Y }
\cf0 \fi362 {\i0 \fs9 1 }\par
}
f30 \fs12 \cf0 D
cf0 {\i0\dn006 \f10 \fs7 4}{\f20 \fs10 CP }
cf0 \fi321 {\i0 \f20 \fs10 FF7 }
\fi332 {\f10 \fs9 RD }\par

}
f30 \fs11 \cf0 D
cf0 {\b0\i0 \f10 \fs9 --c}CP \par
}
10 \cf0 Q O \par
}
12 \cf0 Q, \par
}
{\phpg\posx4603\pvpg\posy7319\absw175\absh128 \f10 \fs11 \cf0 \f10 \fs11 \cf0 Qz
\par
}
cf0 Q, \par
}
cf0 0.4 \par
}
cf0 Qs \par
}
cf0 Q6 \par
}
s14 \cf0 (c){\b0\i0 \fs15 Detailed}{\b0\i0 \fs15 logic}{\b0\i0 \fs15 diagram }
\par
}
puts \par
}
perating modes
t (clear) \par
}
ift \par
}
{\phpg\posx4511\pvpg\posy8445\absw307\absh1430 \f10 \fs19 \cf0 \f10 \fs19 \cf0 \par}{\phpg\posx4511\pvpg\posy8445\absw307\absh1430
i \f20 \fs15 MR }
3 {\f20 \fs15 L }
\fi65 {\f20 \fs15 H }
0 {\b \f20 \fs15 H }
1 {\f20 \fs15 H }
0 {\f20 \fs15 H }\par
}
s15 \cf0 CP
\sl-153 \f10 \fs19 \cf0 {\b\

\sl-277 \f10 \fs19 \cf0 \fi8
\sl-161 \par\f10 \fs19 \cf0
\sl-244 \f10 \fs19 \cf0 \fi7
\sl-240 \f10 \fs19 \cf0 \fi7
\sl-153 \f10 \fs19 \cf0 \fi7
\f20 \fs15 \cf0 \b\i \f20 \f

\fi37 {\i0 \fs15 X }
\fi67 {\b0\i0 \fs18 t }
\fi71 {\b0\i0 \f30 \fs19 T }
\fi71 {\b0\i0 \fs17 T }
\fi71 {\b0\i0 \f30 \fs19 T }\par
}
0 03, \par
}
\cf0 X
f0 \fi38 {\b0 \fs15 1 }
fi42 {\f10 \fs14 1 }
fi22 {\b0 \fs15 h }
fi22 {\b0 \fs15 h }\par
}
s17 \cf0 Ds,
\fi53 {\i0 \f20 \fs15 X }
\cf0 \fi97 {\b0\i0 \f20 \fs15 1 }
\fi77 {\b0\i0 \f20 \fs15 h }
\fi100 {\i0 \f10 \fs14 1 }
\fi78 {\b0\i0 \f20 \fs15 h }\par
}
\cf0 QO
fi50 {\i0 \fs15 L }
f0 \fi43 {\i0 \fs15 L }
fi49 {\i0 \fs15 L }
fi50 {\i0 \fs15 L }
fi36 {\i0 \fs15 H }\par
}
utputs
\fi372 {\b \fs10 Ql-Q7 }
58 L-L
\fi410 {\b\i \fs13 qO-q6 }
14 {\i \f10 \fs12 qo-q6 }

14 {\i \fs13 qo-q6 }
14 {\i \f10 \fs9 q0-6 }\par
}
{\phpg\posx4735\pvpg\posy10091\absw1590\absh103 \f10 \fs7 \cf0 \f10 \fs7 \cf0 ~~
~-~ \par
}
H{\f10 \fs11 =} HIGH voltage level
i41 h{\f10 \fs11 =} HIGH voltage level one setup time prior to the LOW-to-HIGH
i328 clock transition
i28 L{\f10 \fs11 =} LOW voltage level
i90 1{\f10 \fs11 =} LOW voltage level one setup time prior to the LOW-to-HIGH
i323 clock transition \par
}
\cf0 q{\b0\dn006 \f10 \fs10 = }\par
}
lowercase letters indicate the state of the referenced input
setup time prior to the LOW-to-HIGH clock transiton \par
}
t{\dn006 \f10 \fs11
=}{\fs15 LOW-to-HIGH}{\fs15 clock}{\fs15 transition }
\fi3475 {\b\i \fs15 (}{\b\i \fs15 d}{\b\i \fs15 )}{\fs15 Truth}{\fs15 table
}
\fi2358 {\b \fs16 Fig.}{\b \fs16 11-11}{\fs15 The}{\b \fs16 74HC164}{\fs15
shift}{\fs15 register}{\fs16 IC }\par
}
.{\fs17 113 }\par
}
IFT REGISTERS \par
}
\par
}
\cf0 The 74HC164{\fs19 CMOS} IC is an 8-bit edge-triggered shift regi
ster that permits only serial data
t. Eight parallel outputs are available{\i \fs18 (Qo}to{\i \fs18 Q7)}from e
ach{\fs19 of} the eight internal flip-flops (Fig.
2 11-llc). The clock input{\b\i \fs19 (CP)}to the 74HC164 is edge-triggered and
shifts data on the LOW-to-HIGH

sition of the clock pulse. Data{\fs19 is} entered one bit at a time (serially)
through one{\fs19 of} two data inputs
0 \fs16 (}{\i Dsa} or{\b\i Drh).}The simplified logic diagram in Fig. 11-1{\fs1
8 la} shows that the data inputs{\f10 \fs16 (}{\b\i \fs19 Dsa}and{\b\i \fs19
Dsb)}are
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-237 \f20 \fs19 \cf0 ANDe
d together. This means that one input can be used as an active-HIGH data enabl
e input while
al data is fed into the second data input. If no data enable input is required,
both data inputs{\b\i \f30 \fs21 (Ds, }
\b\i Dsb)}are tied together and used as a single serial data input. In Fig.
11-llc, each clock pulse will
t data one position to the right (from{\fs18 Q,} to{\b \fs19 Q7)}in the shif
t register. The master reset{\i \fs38 (m) }
74HC164 IC is an active-LOW input which resets all eight flip-flops and clears
the outputs to{\fs19 0. }
master reset{\i \fs37 (m) }
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-234 \f20 \fs19 \cf0 regi
ster is packaged in a 14-pin DIP IC, shown in Fig. 11-llb.{\b A} truth t
able detailing the operating
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-233 \f20 \fs19 \cf0 mode
s of the 74HC164 IC is reproduced in Fig. 11-lld. The 74HC164 IC operates on a{
\fs19 5-V} dc power
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-265 \f20 \fs19 \cf0 supp
ly.
60 Manufacturers produce a variety of CMOS shift registers. If{\b \fs18 you} a
re wiring shift registers using{\i D }
-flops, the 4076 and 40174 ICs are available. The 4014 8-stage static shift-regi
ster IC is a serial-in
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-240 \f20 \fs19 \cf0 para
llel-out device. The 4031 64-stage static shift register is a serial-in serialout unit. The 4035 4-bit
t register is a parallel-in parallel-out storage unit, The 4034 &bit static sh
ift register is a universal
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-229 \f20 \fs19 \cf0 3-st
ate bidirectional{\fs18 parallel/serial-input/output}
unit which can input
from and output to bus lines.
\par}{\phpg\posx851\pvpg\posy1360\absw9056\absh4285 \sl-240 \f20 \fs19 \cf0 Many
other shift registers are also available in the 74HC and 74HCT series of CMOS I
Cs. \par
}
{\phpg\posx9139\pvpg\posy3266\absw582\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 pi
n on \par
}
s an asynchronous input that overrides all other inputs. The 74HC164 shift \
par
}
OLVED PROBLEMS

\f20 \fs18 11.29}{\f20 \fs19 Refer}{\f20 \fs19 to}{\f20 \fs19 Fig.}{\f20 \fs
19 11-11.}{\f20 \fs19 The }
02 {\f20 \fs19 activated}{\f20 \fs19 with}{\f20 \fs19 a}{\f20 \fs19 LOW. }
\fi604 {\b \f20 Solution: }\par
}
nput to the 74HC164 shift register overrides all others when \par
}
\cf0 The active-LOW master reset{\i \fs33 (m) }
\fs18 11.30}{\fs19 The}{\fs19 master}{\fs19 reset}{\fs36 (m) }
93 {\fs19 input. }
46 The reset{\fs33 (m) }
{\b \fs18 11.31}{\fs19 Refer}{\fs19 to}{\fs19 Fig.}{\fs19 11-11,}{\fs19 The
}{\fs19 clock}{\fs19 input}{\b\i \f30 \fs21 (CP)}{\fs19 to}{\fs19 the}{\fs19
74HC164}{\fs19 IC}{\fs19 is }\par
}
nput to the 74HC164 shift register overrides all others. \par
}
in on the 74HC164 IC is a(n) \par
}
in on the 74HC164 IC is an asynchronous input. \par
}
and shifts data on the
}
asynchronous, synchronous) \par
}
(edge, pulse)-triggered \par
}
(H-to-L, L-to-H) transition of the clock pulse. \par
}
7 \cf0 The clock input{\b\i \fs17 (CP)}to the 74HC164 IC is edge-triggered and
shifts data{\fs17 on} the L-to-H transition of
clock pulse. \par
}
\cf0 11.32{\b0 \fs19 The}{\b0 \fs19 74HC164}{\b0 \fs19 is}{\b0 \fs19 an}{\b
0 \fs19 8-bit }
}
(parallel, serial)-in parallel-out shift register. \par
}
The 74HC164 is an 8-bit serial-in parallel-out shift register. \par
}
}{\b0 \fs19 Why}{\b0 \fs19 does}{\b0 \fs19 the}{\b0 \fs19 74HC164}{\b0 \fs19
IC}{\b0 \fs19 have}{\b0 \fs18 two}{\b0 \fs19 serial}{\b0 \fs19 data}{\b0 \f
s19 inputs}{\b0 \fs19 (see}{\i \fs19 Dsa}{\b0 \fs19 and}{\i \fs19 Dsb)? }
\par
}
\par
}
IFT REGISTERS \par
}
AP. 11 \par
}
\cf0 Solution:
fi360 {\b0 \fs17 The}{\b0 \fs17 74HC164}{\b0 \fs17 IC}{\b0 \fs17 has}{\b0 \f
s17 two}{\b0 \fs17 ANDed}{\b0 \fs17 serial}{\b0 \fs17 data}{\b0 \fs17 inp
uts}{\i \fs17 (Dsa}{\b0 \fs17 and}{\i \fs17 Dsb).}{\b0 \fs17 Two}{\b0 \fs17
serial}{\b0 \fs17 data}{\b0 \fs17 inputs}{\b0 \fs17 allow}{\b0 \fs17 one }
\b0 \fs17 to}{\b0 \fs17 be}{\b0 \fs17 used}{\b0 \fs17 as}{\b0 \fs17 an}{\b
0 \fs17 active-HIGH}{\b0 \fs17 serial}{\b0 \fs17 data}{\b0 \fs17 enable}{
\b0 \fs17 input}{\b0 \fs17 to}{\b0 \fs17 turn}{\b0 \fs17 the}{\b0 \fs17
data}{\b0 \fs17 input}{\b0 \fs17 on}{\b0 \fs17 and}{\b0 \fs17 off. }\par
}
\cf0 11.34{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 11-1
2.}{\b0 \fs19 The}{\b0 \fs19 74HC164}{\b0 \fs19 shift}{\b0 \fs19 register
}{\b0 \fs19 is}{\b0 \fs19 in}{\b0 \fs19 the }
fi589 {\b0 \fs19 operation}{\b0 \fs19 during}{\b0 \fs19 clock}{\b0 \fs19 pul
se}{\i \f10 \fs16 a. }
fi949 {\b0 \fs17 The}{\b0 \fs17 master}{\b0 \fs17 reset}{\b0\i \fs32 (m) }\
par
}
reset, shift) mode of \par
}
nput is activated with a LOW during pulse{\i \f10 \fs14 a}{\fs17 so}
the shift register is in the \par
}
eset mode. Remember that the reset{\i \fs17 (MR)} input overrides all o
thers. \par
}
cf0 11.35{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 11-12.}{
\b0 \fs19 The}{\b0 \fs19 74HC164}{\b0 \fs19 IC}{\b0 \fs19 is}{\b0 in}{\b0 \
fs19 the }
i584 {\b0 \fs19 clock}{\b0 \fs19 pulse}{\i b. }
}
reset, shift) mode{\fs18 of} operation during \par
}
\cf0 Reset{\i \fs17 (}{\i \fs17 M}{\i \fs17 R}{\i \fs17 )} is deactivated
so the 74HC164 IC shifts right one position loading a 1 bit from the data
t{\b\i (Dsb)}into the{\i \fs16 Q,} position. The results after pulse{\i
\fs16 h} are 10000000. \par
}
cf0 11.36{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 11-12.Th
e}{\b0 \fs19 serial-in}{\b0 \fs19 data}{\b0 \fs19 inputs}{\b0 \fs19 are }
i589 {\b0 \fs19 pulse}{\b0 \fs18 c. }
}
activated, deactivated) during clock \par
}
\cf0 See Fig. 11-12. The top input to the serial data AND gate{\b i
s}{\fs17 LOW} during clock pulse c, which
90 deactivates the entire serial data input.
{\b \fs18 11.37}{\fs19
List}{\fs19 the}{\fs19 state}{\fs19 of}{\fs19 t
he}{\fs19 output}{\fs19 indicators}{\fs19 after}{\fs19 each}{\fs19 clo
ck}{\fs19 pulse}{\fs19 for}{\fs19 the}{\fs19 74HC164}{\fs19 shift}{\fs19
register }
94 {\fs19 shown}{\fs19 in}{\fs19 Fig.}{\fs19 11-12. }
}
\cf0 The output indicators read as follows for the shift register show
n in Fig. 11-12{\i \fs17 (Q,} on left,{\b\i\dn006 \fs11
Q7 }
\par}{\phpg\posx1457\pvpg\posy7922\absw7929\absh395 \sl-220 \f20 \fs17 \cf0 righ
t): \par
}
lse{\i \f10 \fs15 a}{\dn006 \f10 \fs11 = }
{\i \fs16 b}{\dn006 \f10 \fs11 = }\par
}
00{\fs17 0000 }
\fs17 0000 }\par
}
\par
}
pulse{\i \f10 \fs14 c}{\f10 \fs13 =} 0100{\fs17 0000 }
se{\b\i \f10 \fs16 d}{\f10 \fs13 =} 0010{\fs17 0000 }
se{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 0001 0000
se{\fs17 f}{\f10 \fs13 =}{\fs17 0000} 1000
se{\fs15 g}{\dn006 \f10 \fs11 =}{\fs17 0000} 0100
se{\b\i h}{\f10 \fs13 =} 0000 0010
se{\b\i \f30 \fs18 i}{\f10 \fs13 =} 0000 0001
se{\i \f10 \fs15 j}{\f10 \fs13 =} 0000 0000 \par
}
Reset mode
ft right-serial
ft right-serial
ft right-serial
ft right-serial
ft right-serial
ft right-serial
ft right-serial
ft right-serial
ft right-serial \par
}
load a{\fs16 1} into{\b\i \f30 \fs19 Q, }
\par}{\phpg\posx4873\pvpg\posy8564\absw1341\absh2520 \sl-215 \f20 \fs17 \cf0 loa
d a 0 into{\fs16 Q, }
ut disabled
ut disabled
ut disabled
ut disabled
ut disabled
ut disabled
ut disabled
\cf0 \fi485 {\b \fs15 Data }
423 {\fs15 enable}{\fs21 I }\par
}
\cf0 +5{\i0 \fs23 v }\par
}
I I I I I I I I \par
}
\par
}
22 \cf0 I
\cf0 {\b \f20 \fs16 Fig.}{\b \fs15 11-12}{\f20 \fs17
Shift-register}{\f20 \f
s17 pulse-train}{\f20 \fs17 problem }\par
}
0 CHAP.{\b0 \fs17 111 }\par
}
cf0 SHIFT{\b0 \fs17 REGISTERS }\par
}
f0 275 \par
}
\cf0 S{\fs22 u}{\b \f20 \fs24 p}{\b \f20 \fs24 pl}{\fs22 emen}{\b \fs22 tary} P
ro{\b \fs21 b}{\fs21 I}{\fs22 em}{\b \fs22 s }
\b \fs15 11.38}{\f20 \fs17
Draw}{\f20 \fs17 the}{\f20 \fs17 logic}{\f20
\fs17 diagram}{\f20 \fs17 for}{\f20 \fs17 a}{\f20 \fs17 5-bit}{\f20 \fs1
7 serial-load}{\f20 \fs17 shift-right}{\f20 \fs17 register.}{\f20 \fs17
Use}{\f20 \fs17 five}{\i \f20 \fs17 D}{\f20 \fs17 flip-flops.}{\f20 \fs17
Label}{\f20 \fs17 inputs}{\f20 \fs17 as }
6 {\f20 \fs17 clock,}{\f20 \fs17 clear,}{\f20 \fs17 and}{\f20 \fs17 serial-d
ata.}{\f20 \fs17 Label}{\f20 \fs17 outputs}{\b \f20 \fs17 as}{\b\i \f20 \fs
17 A}{\b\i \f20 \fs17 ,}{\b\i \f20 \fs17 B,}{\b\i \f20 \fs17 C,}{\i \f20 \
fs17 D,}{\f20 \fs17 and}{\b\i \f20 \fs18 E.}{\b\i \f20 \fs17
Ans.}
{\f20 \fs17
See}{\f20 \fs17 Fig.}{\f20 \fs17 11-13. }\par
}
\fs15 \cf0 FF{\fs14 1 }
b0 \f10 \fs21 ->}{\fs15
CLK }\par
}
I \par
}
cf0 CLR

0 \fi130 {\b0 \f10 1 }\par
}
cf0 Inputs \par
}
cf0 Clear \par
}
par
}
\fs15 \cf0 FF2
\b0 \f10 \fs21 >}{\fs15 CLK }
f0 \fi216 {\fs15 CLR }
fi326 {\b0\i \fs19 Y }
fi344 {\b0 \f10 \fs23 - }\par
}
\fs15 \cf0 FF3
fs15 >CLK }
0 \fi196 {\fs15 CLR }
i317 {\b0 \fs19 P }\par
}
\par
}
\fs15 \cf0 FF4
b0 \f10 \fs21 ->}{\fs15
CLK }
0 \fi418 {\fs15 CLR }
i538 {\b0 \f10 \fs17 ? }\par
}
\fs15 \cf0 FF5
b0 \f10 \fs21 >}{\fs15 CLK }
0 \fi201 {\fs15 CLR }
i334 {\b0 \fs19 P }\par
}
\cf0 Fig.{\f10 \fs15 11-13}{\b0 \fs17
Logic}{\b0 \fs17 diagram}{\b0 \fs17
for}{\b0 \fs17 a}{\b0 \fs17 5-bit}{\b0 \fs17 serial-load}{\b0 \fs17 shift-ri
ght}{\b0 \fs17 register }\par
}
cf0 11.39{\b0 \f20 \fs17
It}{\b0 \f20 \fs17 takes }\par
}
lock pulse(s) to load a 5-bit serial-load shift register. \par
}
17 \cf0 Ans.{\b0\i0
five }\par
}
cf0 11.40{\b0 \f20 \fs17
{\b0 \f20 \fs17 11-14.}{\b0 \f20 \fs17 The}{\b0\i \fs15 data}{\b0 \f20 \fs1
7 input}{\b0 \f20 \fs17 is}{\b0 \f20 \fs17 a }
i778 {\b0\i \fs15 (}{\b0\i \fs15 c}{\b0\i \fs15 )}{\b0 \f20 \fs17
(left,
}{\b0 \f20 \fs17 right)}{\b0 \f20 \fs17 register.}{\i \f20 \fs17
Ans
.}{\b0\i \f20 \fs17
( }\par
}
{\phpg\posx4984\pvpg\posy6757\absw330\absh389 \i \f10 \fs15 \cf0 \fi21 \i \f10 \
fs15 \cf0 ( a )
f20 \fs17 a }\par
}
\cf0 (parallel, serial) data input to this
\fs17 m}{\fs17
(6)}{\b\i \fs17
3}{\i \f10 \fs15
(c)}
right \par
}
17 \cf0 ( 6 \par
}
17 \cf0 ){\b0\i0 \fs17
-bit}{\b0\i0 \fs17 shift- }\par
}
\cf0 Output indicators \par
}
{\fs70 Q} Q \par
}
\cf0 1 - D{\fs18
Q}{\b
1}{\b .}{\b D}{\i0 \f10 \fs16
QJ }\par
}
cf0 FF2 \par
}
cf0 FF3 \par
}
{\b \f20 \fs15
CLK }
fi438 {\b \f20 \fs15 CLR }
0 {\b \fs26 y }\par
}
{\b \f20 \fs15
CLK }
fi423 {\b \f20 \fs15 CLR }
3 {\b \f20 \fs25 9 }\par

}
{\phpg\posx6373\pvpg\posy8189\absw162\absh441 \f10 \fs19 \cf0 \f10 \fs19 \cf0 \par}{\phpg\posx6373\pvpg\posy8189\absw162\absh441 \sl-247 \f10 \fs19 \cf0 {\i \
f20 \fs15 D }\par
}
cf0 Q \par
}
cf0 FF{\fs14 1 }\par
}
{\phpg\posx6373\pvpg\posy8867\absw597\absh548 \f10 \fs11 \cf0 \f10 \fs11 \cf0 >{
\b \f20 \fs15 CLK }
fi186 {\b \f20 \fs15 CLR }\par
}
\cf0 Fig.{\f10 \fs15 11-14}{\b0 \fs17
Serial-load}{\b0 \fs17 shift-registe
r}{\b0 \fs17 pulse-train}{\b0 \fs17 problem }\par
}
\cf0 11.41{\b0 \f20 \fs17
List}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 outpu
t}{\b0 \f20 \fs17 after}{\b0 \f20 \fs17 each}{\b0 \f20 \fs17 clock}{\b0 \f
20 \fs17 pulse}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 s
hift}{\b0 \f20 \fs17 register}{\b0 \f20 \fs17 shown}{\b0 \f20 \fs17 in}{\b
0 \f20 \fs17 Fig.}{\b0 \f20 \fs17 11-14}{\i \f20 \fs17 (}{\i \f20 \fs17 A}
{\b0 \f20 \fs17 on}{\b0 \f20 \fs17 left,}{\i \f20 \fs17 C}{\b0 \f20 \fs17
on}{\b0 \f20 \fs17 right). }\par
}
fs17 \cf0 Am.{\b0\i0
pulse}{\b0\i0 \fs15 a}{\b0\i0 \f10 \fs13 =}{\b0\i0
000 }
0 \fi530 {\b0\i0 pulse}{\b0 \fs16 b}{\b0\i0 \f10 \fs13 =}{\b0\i0 100 }\par
}
pulse{\b\i \fs17 c}{\f10 \fs13 =} 010
se{\b\i \f10 \fs16 d}{\f10 \fs13 =} 101 \par
}
pulse{\b\i \fs16 e}{\dn006 \f10 \fs11 =} 010
se{\i \f10 \fs16 f}{\i \f10 \fs16 =} 100 \par
}
pulse{\fs15 g}{\dn006 \f10 \fs11 =} 110
se{\i h}{\dn006 \f10 \fs11 =} 011 \par
}
\cf0 11.42{\b0 \f20 \fs17
{\b0 \f20 \fs17 11-14.}{\b0 \f20 \fs17 List}{\b0 \f20 \fs17 the}{\b0 \f20 \f
s17 two}{\b0 \f20 \fs17 synchronous}{\b0 \f20 \fs17 inputs}{\b0 \f20 \fs17
on}{\b0 \f20 \fs17 this}{\b0 \f20 \fs17 register. }\par
}
\cf0 11.43{\b0 \f20 \fs17
}{\b0 \f20 \fs17 11-14.}{\b0 \f20 \fs17 It}{\b0 \f20 \fs17 takes }\par
}
data}{\b0\i0 (serial),}{\b0\i0 clock }\par
}
clock pulse(s) to load this register with 011. \par
}
s17 \cf0 Am.{\b0\i0 \fs17
three }\par
}
\cf0 11.44{\b0 \f20 \fs17
\b0 \f20 \fs17 11-7.This}{\b0 \f20 \fs17 3-bit}{\b0 \f20 \fs17 parallel-load
}{\b0 \f20 \fs17 shift}{\b0 \f20 \fs17 register}{\b0 \f20 \fs17 uses }
fi584 {\b0 \f20 \fs17 (nonrecirculating,}{\b0 \f20 \fs17 recirculating)}{\b0 \
f20 \fs17 unit.}{\i \f20 \fs17
Am.}{\b0\i \fs14
(a)}{\i \f20 \fs17
JK }\par
}
s15 \cf0 ( a ) \par
}
\cf0 ( D ,{\b JK)}{\i0 flip-flops}{\i0 and}{\i0 is}{\i0 a }\par
}
s17 \cf0 ( 6 ) \par
}
@)recirculating \par
}
\par
}
}
AP. 11 \par
}
f0 11.45 \par
}
\cf0 Refer to Fig. 11-7.What is the mode of operation of each{\i \fs17
JK} flip-flop while clock pulse{\b\i \fs16 d}{\fs16 is} HIGH?
i \fs16 Ans.}
FF1 mode{\f10 \fs13 =} set{\i \fs17 (}{\i \fs17 J}{\f10 \fs
11 =}{\fs16 1,}{\i K}{\f10 \fs13 =}{\fs16 0) }\par
}
2 mode{\dn006 \f10 \fs11 = }
\par}{\phpg\posx1951\pvpg\posy1775\absw989\absh387 \sl-215 \f20 \fs17 \cf0 FF3 m
ode{\dn006 \f10 \fs11 = }\par
}
eset{\b\i \f30 \fs17 (1 }{\dn006 \f10 \fs11 =} 0,{\b\i K}{\dn006 \f10 \fs11
=}{\fs16 1) }

t{\i \fs16 (}{\i \fs16 J}{\dn006 \f10 \fs11 =} 0,{\i K}{\dn006 \f10 \fs11
=} 1) \par
}
f0 11.46
11.47 \par
}
efer to Fig. 11-7.The active state for the clear input is
Refer to Fig. 11-7.The output indicators on this register read{\b\i \fs16 A}{\
dn006 \f10 \fs11
= }
pulse{\fs15 g} is HIGH.{\b\i \fs16
Ans.}{\b\i \fs16
(}{\b\i
\fs16 a}{\b\i \fs16 )} 0{\i \fs16
(}{\i \fs16 b}{\i \fs16 )}{\fs16
1}{\i \fs16
(}{\i \fs16 c}{\i \fs16 )}{\fs16
1 }\par
}
,{\fs16 1). }\par
}
16 \cf0 Ans.{\b0\i0 \fs16
0 }\par
}
cf0 ( a ){\i0 \fs17
,}{\b \f20 \fs17 B}{\i0\dn006 \fs11 = }\par
}
6){\f10 \fs17
,}and{\b \fs16 C}{\dn006 \f10 \fs11 = }\par
}
cf0 ( c ) \par
}
f0 11.48 \par
}
efer to Fig. 11-7,What is the mode of operation{\fs16 of} each{\i JK}
flip-flop while clock pulse{\i \fs16 h} is HIGH? \par
}
s16 \cf0 Ans.{\b0\i0 \fs17
FF1}{\b0\i0 \fs17 mode}{\b0\i0\dn006 \f10 \fs11
= }
\fi536 {\b0\i0 \fs17 FF2}{\b0\i0 \fs17 mode}{\b0\i0\dn006 \f10 \fs11 = }
\fi536 {\b0\i0 \fs17 FF3}{\b0\i0 \fs17 mode}{\b0\i0\dn006 \f10 \fs11 = }\par
}
{\phpg\posx2977\pvpg\posy3887\absw629\absh196 \f20 \fs17 \cf0 \f20 \fs17 \cf0 se
t{\b\i \fs16 (}{\b\i \fs16 J}{\dn006 \f10 \fs11 = }\par
}
t{\b\i \fs16 (}{\b\i \fs16 J }\par
}
{\i \fs17 K}{\dn006 \f10 \fs11 =}{\fs16 0) }\par
}
\fs15 1,}{\i \f20 \fs17 K}{\dn006 =}{\f20 \fs16 0) }\par
}
set{\i \fs16 (}{\i \fs16 J}{\dn006 \f10 \fs11 = }\par
}
{\i \fs17 K}{\f10 \fs13 =}{\fs16 1) }\par
}
f0 11.49 \par
}
efer to Fig. 11-7. The two lines{\fs16 with} arrows going back
from FF3 to FFl arc called
\par}{\phpg\posx1437\pvpg\posy4805\absw7500\absh389 \sl-218 \f20 \fs17 \cf0 (rec
irculating, reset) lines.{\b\i \fs16
Ans.}
recirculating \par
}
cf0 11.50{\b0 \f20 \fs17
{\b0 \f20 \fs16 11-7.}{\b0 \f20 \fs17 The}{\b0\i \f20 \fs17 JK}{\b0 \f20 \f
s17
flip-flops}{\b0 \f20 \fs17 arc}{\b0 \f20 \fs17 triggered}{\b0 \f20 \f
s17 on}{\b0 \f20 \fs17 the }\par
}
OW) transition of the clock pulse. \par
}
cf0 ( a ) \par
}
HIGH, LOW)-to-{\fs16
(6) }\par
}
IGH, \par
}
s16 \cf0 Ans.{\b0 \fs16
(}{\b0 \fs16 a}{\b0 \fs16 )}{\b0\i0 \fs17
HIGH
}{\b0\i0 \fs17 (h)LOW }\par
}
cf0 11.51{\b0 \f20 \fs17
\b0 \f20 \fs17 12-7.List}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 outputs}{\b0 \f2
0 \fs17 of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 register}{\b0 \f20 \fs17 whi
le}{\b0 \f20 \fs17 each}{\b0 \f20 \fs17 clock}{\b0 \f20 \fs17 pulse}{\b0 \f20
\fs17 is}{\b0 \f20 \fs17 HIGH}{\b0 \f20 \fs17 (just}{\b0 \f20 \fs17 befor
e}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 H-to-L }\par
}
\cf0 transition of the clock).
i \fs16 Ans.}
pulse a{\f10 \fs13 =}{\fs16 000 }
36 pulse{\i b}{\dn006 \f10 \fs11 =} 100
35 pulse{\f10 \fs15 c}{\f10 \fs13 =} 010 \par
}
ulse{\i \f10 \fs16 d}{\f10 \fs13 =}{\fs16 001 }
e{\i e}{\dn006 \f10 \fs11 =}{\fs16 100 }
e{\f10 \fs16 .f'=}{\fs16 000 }\par

}
ulse{\i \f10 \fs14 g}{\f10 \fs13 =}{\fs16 01}{\fs16 1 }
e{\i \fs16 h}{\dn006 \f10 \fs11 =} 101
e{\b\i \f30 \fs17 i}{\dn006 \f10 \fs11 =} 110 \par
}
lse{\i \f10 \fs14 j }\par
}
\f20 \fs16 11}{\f20 \fs16 1 }\par
}
f0 11.52 \par
}
efer to Fig. 11-15. The clock input triggers the shift register on the
\par
}
HIGH, LOW) transition of the clock pulse. \par
}
cf0 ( a ) \par
}
HIGH, LOW)-to- \par
}
cf0 ( b ) \par
}
s16 \cf0 Ans.{\b0 \fs16
(}{\b0 \fs16 a}{\b0 \fs16 )}{\b0\i0 \fs17
LOW
}{\b0\i0 \fs17
-HIGH }\par
}
cf0 1 \par
}
\par
}
f0 0 \par
}
rallel
loads \par
}
utput{\fs14 indicators }\par
}
14 \cf0 A
{\f30 \fs16 B }
{\b0 \f20 \fs15 C }

{\b0 \f20 \fs15 D }\par
}
{\phpg\posx7103\pvpg\posy8949\absw627\absh460 \f20 \fs14 \cf0 \f20 \fs14 \cf0 Un
iversal
2 {\fs14 shift }
{\fs14 register }\par
}
\cf0 Q A \par
}
\cf0 QL3 \par
}
\par
}
cf0 I \par
}
cf0 1 \par
}
cf0 '
f20 \fs14 LOW }\par
}
\cf0 Right
al{\fs14 input}{\i \fs14
D.w }\par
}
f0 QC \par
}
, \par
}
Mode controls \par
}
cf0 0 \par
}
\par
}
\par
}
\cf0 Fig.{\f10 \fs15 11-15}{\b0 \fs17
Universal}{\b0 \fs17 shift-register}
{\b0 \fs17 pulse-train}{\b0 \fs17 problem }\par
}
cf0 11.53 \par
}
Refer to Fig. 11-15.The clear connection to the 74194 register is an ac
tive
overrides{\fs16 all} others.{\b\i \fs16
Ans.}
LOW \par
}
(HIGH, LOW) input \par
}
. 111 \par
}
IFT REGISTERS \par
}
\par
}
f0 11.54 \par
}
ist the operating mode of the 74194 shift register for each clock pulse
shown in Fig. 11-15. \par
}
\cf0 Ans.{\i0
pulse}{\fs17 a}{\i0\dn006 \f10 \fs11 =}{\i0 parallel-load
}
fi536 {\i0 pulse}{\fs16 b}{\i0\dn006 \f10 \fs11 =}{\i0 shift-right }
fi535 {\i0 pulse}{\i0 \f10 \fs13 c}{\i0\dn006 \f10 \fs10 =}{\i0 shift-right
}\par
}
ulse{\fs16 d}{\dn006 \f10 \fs11 =} parallel-load
e{\fs16 e}{\dn006 \f10 \fs11 =} hold
e{\b\i \f30 \fs18 f}{\dn006 \f10 \fs11 =} shift-right \par
}
ulse{\fs15 g}{\f10 \fs13 =} shift-right
e{\i \fs17 h}{\dn006 \f10 \fs11 =} shift-left \par
}
f0 11.55 \par
}
ist the states of the output indicators of the register shown in Fig. 11-15w
hile each clock pulse is{\fs17 HIGH. }\par
}
\cf0 Ans.{\i0 \fs16
pulse}{\dn006 \f10 \fs10
U}{\i0\dn006 \f10 \fs11 =
}{\i0 \fs16 1111 }
fi531 {\i0 \fs16 pulse}{\b \f30 b}{\i0\dn006 \f10 \fs11 =}{\i0 \fs16 0111 }\
par
}
ulse{\f10 \fs13 c}{\dn006 \f10 \fs10 =}{\fs16 0011 }
e{\fs16 d}{\dn006 \f10 \fs11 =} 0110 \par
}
ulse{\fs16 e}{\dn006 \f10 \fs11 =} 0110
e{\i \f30 \fs19 f}{\i \f30 \fs19 =} 0011 \par
}
ulse{\fs15 g}{\dn006 \f10 \fs11 =} 0001
e{\i \fs16 h}{\dn006 \f10 \fs11 =} 0010 \par
}
f0 11.56 \par
}
efer to Fig. 11-15.Just{\b\i \f30 \fs17 before} clock pulse{\b\i \f30 \fs18
d,} the output indicators read \par
}
\f20 \fs16 Why? }\par
}
\cf0 Ans.{\i0
Because}{\i0 of}{\i0 the}{\i0 clear}{\i0 pulse,}{\i0
the}{\i0 output}{\i0 indicators}{\i0 read}{\i0 \fs17 0000}{\i0 just}{
\i0 before}{\i0 clock}{\i0 pulse}{\f10 \fs16 d}{\i0 (Fig.}{\i0 11-15
). }\par
}
\cf0 Refer to Fig. 11-15. During pulse{\i \f10 \fs14 a,} this register is
set up for
Ans.}
parallel \par
}
nother term for parallel loading is
loading. \par
}
parallel, serial) loading. \par
}
f0 11.57 \par
}
f0 11.58 \par
}
s16 \cf0 Am.{\b0\i0
broadside }\par
}
cf0 11.59{\f20 \fs16
A}{\b0 \f20 \fs16 shift}{\b0 \f20 \fs16 register}{
\b0 \f20 \fs16 is}{\b0 \f20 \fs16 classified}{\b0 \f20 \fs16 as}{\b0 \f20 \
fs16 a }\par
}

combinational, sequential) logic circuit. \par
}
s17 \cf0 Ans.{\b0\i0 \fs16
sequential }\par
}
cf0 11.60{\b0 \f20 \fs16
The}{\b0 \f20 \fs16 storage}{\b0 \f20 \fs16 unit
}{\b0 \f20 \fs16 shown}{\b0 \f20 \fs16 in}{\b0 \f20 \fs16 Fig.}{\b0 \f20 \
fs16 11-4}{\b0 \f20 \fs16 might}{\b0 \f20 \fs16 be}{\b0 \f20 \fs16 classi
fied}{\b0 \f20 \fs16 as}{\b0 \f20 \fs16 a}{\b0 \f20 \fs16 serial-in }
i567 {\i \f20 \fs16 Ans.}{\b0 \f20 \fs16
parallel }\par
}
f0 11.61
11.62 \par
}
efer to Fig. 11-5.The recirculating shift register might also be called a
\par
}
{\phpg\posx7563\pvpg\posy6143\absw995\absh190 \f20 \fs16 \cf0 \f20 \fs16 \cf0 -o
ut register. \par
}
unter. \par
}
16 \cf0 Ans.{\b0\i0 \fs16
ring }\par
}
\cf0 Refer to Fig. 11-16. Which part of the figure illustrates the ide
a of a serial-in parallel-out register?
Ans.}
part{\i \fs16 b }\par
}
\cf0 Fig.{\f10 \fs15 11-16}{\b0 \fs16
Types}{\b0 \fs16 of}{\b0 \fs16 regi
sters }\par
}
cf0 11.63 \par
}
cf0 11.64 \par
}
6 \cf0 Refer to Fig. 11-16. Which part of the figure illustrates the i
dea of a parallel-in serial-out register?
i Ans.}
part{\f10 \fs13 c }
0 \fi23 The 74HC164 IC is best represented by which type of register pic
tured in Fig. 11-16?
i Ans.}{\i \fs17
b} (serial-in parallel-out) \par
}
0 278 \par
}
IFT REGISTERS \par
}
AP. 11 \par
}
cf0 11.65{\b0 \fs17
Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 11
-12.This}{\b0 \fs17 shift}{\b0 \fs17 register}{\b0 \fs17 is}{\b0 \fs17 a
n}{\b0 \fs17 example}{\b0 \fs17 of}{\b0 \fs17 a }\par
}
cf0 11.66{\b0 \fs17
}{\b0 \fs17 The}{\b0 \fs17 master}{\b0 \fs17 reset }\par
}
nd overrides all others.{\fs17
Ans. }\par
}
CMOS,{\fs17 TI'L)} IC. \par
}
s15 \cf0 Ans.{\b0\i0 \f20 \fs17
CMOS }\par
}
\cf0 pin{\fs17 on} the 74HC164 is an active}{\phpg\posx4383\pvpg\posy1803\absw3014\absh234 \f20 \fs17 \cf0 {\i \fs33 (m) }\
par
}
HIGH, LOW) input \par
}
{\phpg\posx4263\pvpg\posy2019\absw462\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 LO
W \par
}
cf0 11.67{\b0 \fs17
Refer}{\b0 \fs17
to}{\b0 \fs17 Fig.}{\b0 \fs17 11
-12.}{\b0 \fs17 The}{\b0 \fs17 data}{\b0 \fs17 enable}{\i \f10 \fs15 (OS,
)}{\b0 \fs17 input}{\b0 \fs17
is}{\b0 \fs17 an}{\b0 \fs17
active- }
i590 {\b0 \fs17 example.}{\i
Ans.}{\b0 \fs17
HIGH }\par
}
HIGH, LOW) input in this \par
}
cf0 11.68{\b0 \fs17
Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 1112.}{\b0 \fs17 Assuming}{\b0 \fs17 the}{\b0 \fs17 data}{\b0 \fs17 enable}{\
i (OS,>i}{\b0 \fs17 nput}{\b0 \fs17 is}{\b0 \fs17 HIGH}{\i \fs17 the}{\b0
\fs16 entire}{\i \fs16 time}{\b0 \fs17 (pulses}{\i \f10 \fs15 a}{\b0 \fs17
to}{\i \f30 \fs17 i), }\par
}
st the \par
}
\cf0 states of the output indicators for the shift register after each
clock pulse{\i \fs16 (Q,}{\fs17 on} left,{\b\i \fs16 Q7}{\fs17 on} righ
t).
\i \f10 \fs15 Ans.}
Assuming{\b\i \f30 \fs19 D,,}input{\dn006 \f10 \fs13 =}
HIGH, then
523 pulse{\b\i \f10 \fs14 a}{\f10 \fs13 =} 0000 0000
523 pulse{\i \fs16 b}{\dn006 \f10 \fs11 =} 1000{\fs17 0000 }
523 pulse{\b\i \fs16 c}{\f10 \fs13 =}{\fs17 0100}{\fs17 0o00 }
526 pulse{\b\i \fs17 d}{\dn006 \f10 \fs11 =} 1010 0000
526 pulse{\b\i e}{\f10 \fs13 =} 0101 0000
523 pulse{\b\i \f30 \fs18 f}{\b\i \f30 \fs18 =} 1010 1000
525 pulse{\fs15 g}{\dn006 \f10 \fs11 =} 11010100
523 pulse{\b\i h}{\f10 \fs13 =} 0110 1010
523 pulse{\b\i \f30 \fs18 i}{\f10 \fs13 =} 0011 0101
523 pulse{\i \f10 \fs15 j}{\f10 \fs13 =} 1001 1010 \par
}
{\b \fs33 Microcomputer}{\b \fs33 Memory }\par
}
\cf0 12-1{\fs18
INTRODUCTION }
fi368 {\b0 \fs18 In}{\b0 \fs18 a}{\b0 \fs18 new}{\b0 \fs18 electronic}{\b0 \f
s18 product,}{\b0 \fs18 designers}{\b0 \fs18 must}{\b0 \fs18 choose}{\b0 \
fs18 to}{\b0 \fs18 use}{\b0 \fs18 either}{\b0 \fs18 analog}{\b0 \fs18 or}
{\b0 \fs18 digital}{\b0 \fs18 devices.}{\b0 \fs18 If}{\b0 \fs18 the }
\b0 \fs18 unit}{\b0 \fs18 must}{\b0 \fs18 input,}{\b0 \fs18 process,}{\b0 \
fs18 or}{\b0 \fs18 output}{\b0 \fs18 alphanumeric}{\b0 \fs18 data,}{\b0 \f
s18 the}{\b0 \fs18 choice}{\b0 \fs18 is}{\b0 \fs18 clearly}{\b0 \fs18 dig
ital.}{\b0\i \fs18 Also,}{\b0 \fs18 if}{\b0 \fs18 the}{\b0 \fs18 unit }
\b0 \fs18 has}{\b0 \fs18 any}{\b0 \fs18 type}{\b0 \fs18 of}{\b0 \fs18 memo
ry}{\b0 \fs18 or}{\b0 \fs18 stored}{\b0 \fs18 program,}{\b0 \fs18 the}{\b0
\fs18 choice}{\b0 \fs18 is}{\b0 \fs18 clearly}{\b0 \fs18 digital.}{\b0 \fs
18 Digital}{\b0 \fs18 circuitry}{\b0 \fs18 is}{\b0 \fs18 becoming }
\b0 \fs18 more}{\b0 \fs18 popular,}{\b0 \fs18 but}{\b0 \fs18 most}{\b0 \fs18
complex}{\b0 \fs18 electronic}{\b0 \fs18 systems}{\b0 \fs18 contain}{\b0 \
fs18 both}{\b0 \fs18 analog}{\b0 \fs18 and}{\b0 \fs18 digital}{\b0 \fs18 d
evices. }
fi359 {\b0 \fs18 Microcomputer}{\b0 \fs18 memory}{\b0 \fs18 is}{\b0 \fs18 one
}{\b0 \fs18 example}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 application}{\b0
\fs18 of}{\b0 \fs18 data}{\b0 \fs18 storage}{\b0 \fs18 devices}{\b0 \fs18
called}{\b0 \fs18 memory. }

\b0 \fs18 A}{\b0 \fs18 simplified}{\b0 \fs18 microcomputer}{\b0 \fs18 system}
{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 12
-1.}{\b0 \fs18 The}{\b0 \fs18 keyboard}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs
18 input}{\b0 \fs18 device,}{\b0 \fs18 while}{\b0 \fs18 the }
\b0 \fs18 output}{\b0 \fs18 device}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18
video}{\b0 \fs18 monitor.}{\b0 \fs18 The}{\b0 \fs18 central}{\b0 \fs18 p
rocessing}{\b0 \fs18 unit}{\b0 \fs19 (CPU)}{\b0 \fs18 controls}{\b0 \fs18
the}{\b0 \fs18 operation}{\b0 \fs18 of}{\b0 \fs18 the }
\b0 \fs18 microcomputer}{\b0 \fs18 system}{\b0 \fs18 and}{\b0 \fs18 processes
}{\b0 \fs18 data.}{\b0 \fs18 The}{\b0 \fs18 internal}{\b0 \fs18 memory}{\b0
\fs18 of}{\b0 \fs18 a}{\b0 \fs18 typical}{\b0 \fs18 microcomputer}{\b0 \fs18
system}{\b0 \fs18 is }
\b0 \fs18 composed}{\b0 \fs18 of}{\b0 \fs18 three}{\b0 \fs18 types}{\b0 \f
s18 of}{\b0\i \fs18 semiconductor}{\b0\i \fs18 memory.}{\b0 \fs18 The}{\b0\
i \fs18 nonL1olatile}{\b0 \fs18 semiconductor}{\b0 \fs18 memory}{\b0 \fs18
is}{\b0 \fs18 shown }
\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 12-1}{\b0 \fs18 as}{\b0\i \fs18 ROM}{
\b0\i \fs18 (read-only}{\b0\i \fs18 memory)}{\b0 \fs18 and}{\b0\i \fs18 NV
RAM}{\b0\i \fs18 (nomlolatile}{\b0\i \fs19 RAM).}{\b0 \fs18 The}{\b0\i \fs18
uolatile}{\b0 \fs18 semiconductor }
\b0 \fs18 memory}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 as}{\b0\i \fs19
RAM}{\b0\i \fs18 (random-access}{\b0\i \fs18 memory). }\par
}
20 \fs15 \cf0 Fig.{\fs16 12-1 }
cf0 \fi367 {\b0 \fs18 Data}{\b0 \fs18 and}{\b0 \fs18 most}{\b0 \fs18 progr
ams}{\b0 \fs18 are}{\b0 \fs18 commonly}{\b0 \fs18 stored}{\b0 \fs18 on}{\
b0\i \fs18 magnetic}{\b0\i \fs18 bulk}{\b0\i \fs18 storage}{\b0 \fs18 de
vices}{\b0 \fs18 such}{\b0 \fs18 as}{\b0\i \fs17 floppy }
{\b0\i \fs18 disks}{\b0 \fs18 or}{\b0\i \fs18 hard}{\b0\i \fs18 disks.}{\b0 \
fs18 The}{\b0 \fs18 disk}{\b0 \fs18 drive}{\b0 \fs18 is}{\b0 \fs18 the}{\b0
\fs18 unit}{\b0 \fs18 that}{\b0 \fs18 reads}{\b0 \fs18 from}{\b0 \fs18 or
}{\b0 \fs18 writes}{\b0 \fs18 to}{\b0 \fs18 either}{\b0 \fs18 the}{\b0 \fs18
floppy}{\b0 \fs18 disk}{\b0 \fs18 or}{\b0 \fs18 the }
{\b0 \fs18 hard}{\b0 \fs18 disk.}{\b0 \fs18 Strictly}{\b0 \fs18 speaking,}{
\b0 \fs18 each}{\b0 \fs18 device,}{\b0 \fs18 such}{\b0 \fs18 as}{\b0 \fs
18 the}{\b0 \fs18 keyboard,}{\b0 \fs18 video}{\b0 \fs18 monitor,}{\b0 \fs1
8 disk}{\b0 \fs18 drive,}{\b0 \fs18 and}{\b0 \fs19 CPU, }
{\b0 \fs18 has}{\b0 \fs18 smaller}{\b0 \fs18 memory}{\b0 \fs18 devices.}{\b0
\fs18 These}{\b0 \fs18 memory}{\b0 \fs18 devices}{\b0 \fs18 usually}{\b0 \fs
18 take}{\b0 \fs18 the}{\b0 \fs18 form}{\b0 \fs18 of}{\b0 \fs18 registers}{
\b0 \fs18 and}{\b0 \fs18 latches,}{\b0 \fs18 but }
{\b0 \fs18 they}{\b0 \fs18 can}{\b0 \fs18 contain}{\b0 \fs18 smaller}{\b0 \fs
18 ROM}{\b0 \fs18 and}{\b0 \fs18 RAM}{\b0 \fs18 semiconductor}{\b0 \fs18
memory}{\b0 \fs18 devices. }
\fi4281 {\b0 \fs18 279 }\par
}
\par
}
{\phpg\posx3967\pvpg\posy543\absw2673\absh194 \f20 \fs17 \cf0 \f20 \fs17 \cf0 MI
CROCOMPUTER MEMORY \par
}
AP.{\fs17 12 }\par
}
\cf0 The RAM and ROM storage devices come as ICs and are typically mount
ed on printed-circuit
\par}{\phpg\posx865\pvpg\posy1355\absw9027\absh632 \sl-232 \f20 \fs18 \cf0 board
s as depicted in Fig. 12-1. It is usual to have at least one ROM a
nd many RAM ICs in a
\par}{\phpg\posx865\pvpg\posy1355\absw9027\absh632 \sl-235 \f20 \fs18 \cf0 micro
computer. \par
}
\cf0 12-2{\f20 \fs18
RANDOM-ACCESS}{\f20 \fs19 MEMORY}{\b0 \f20 \fs18 (RAM)
}
fi364 {\b0 \f20 \fs18 Semiconductor}{\b0 \f20 \fs18 memories}{\b0 \f20 \fs18 a
re}{\b0 \f20 \fs18 classified}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 volatile}{\b
0 \f20 \fs18 and}{\b0 \f20 \fs18 nonvolatile.}{\b0 \f20 \fs18 A}{\b0 \f20 \
fs18 volatile}{\b0 \f20 \fs18 memory}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 one}
{\b0 \f20 \fs18 that }
\b0 \f20 \fs18 loses}{\b0 \f20 \fs18 its}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18
when}{\b0 \f20 \fs18 power}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 turned}{\b0 \f
20 \fs18 off.}{\b0 \f20 \fs18 The}{\b0\i \f20 \fs19 RAM}{\b0\i \f20 \fs19 (
random-accessmemory)}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 vola
tile}{\b0 \f20 \fs18 semiconductor }
\b0 \f20 \fs18 memory}{\b0 \f20 \fs18 widely}{\b0 \f20 \fs18 used}{\b0 \f20 \f
s18 in}{\b0 \f20 \fs18 modern}{\b0 \f20 \fs18 microcomputers}{\b0 \f20 \fs18
to}{\b0 \f20 \fs18 hold}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 and}{\b0 \f20
\fs18 programs}{\b0 \f20 \fs18 temporarily.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs
18 RAM}{\b0 \f20 \fs18 is }
\b0 \f20 \fs18 also}{\b0 \f20 \fs18 described}{\b0 \f20 \fs18 as}{\b0 \f20 \fs
18 a}{\b0\i \f20 \fs19 read/write}{\b0\i \f20 \fs19 memory.}{\b0 \f20 \fs18
Storing}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18 a}{\b0 \f20 \
fs18 RAM}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 called}{\b0 \f20 \fs18 the}{\b0\
i \f20 \fs19 write}{\b0\i \f20 \fs19 operation}{\b0 \f20 \fs18 or}{\b0 \f20 \
fs18 writing. }
\b0 \f20 \fs18 Detecting}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 recalling}{\b0 \f2
0 \fs18 data}{\b0 \f20 \fs18 from}{\b0 \f20 \fs18 RAM}{\b0 \f20 \fs18 is}{\b
0 \f20 \fs18 called}{\b0 \f20 \fs18 the}{\b0\i \f20 \fs19 read}{\b0\i \f20 \f
s19 operation}{\b0 \f20 \fs18 or}{\b0 \f20 \fs18 reading.}{\b0 \f20 \fs18 Wh
en}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 read}{\b0 \f20 \fs
18 from }
\b0 \f20 \fs18 memory,}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 contents}{\b0 \f20
\fs19 of}{\b0 \f20 \fs18 RAM}{\b0 \f20 \fs18 are}{\b0 \f20 \fs18 not}{\b0 \
f20 \fs18 destroyed. }
fi364 {\b0 \f20 \fs18 Consider}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 table}{\b0
\f20 \fs18 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs18 12-2.This}{\b0 \f20 \fs18
is}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 representation}{\b0 \f20 \fs18 of}{\b0
\f20 \fs18 the}{\b0 \f20 \fs18 inside}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18
a}{\b0 \f20 \fs18 64-bit}{\b0 \f20 \fs18 memory.}{\b0 \f20 \fs18 The}{\b0 \f2
0 \fs18 64 }
\b0 \f20 \fs18 squares}{\b0 \f20 \fs18 (mostly}{\b0 \f20 \fs18 blank)}{\b0 \
f20 \fs18 represent}{\b0 \f20 \fs18 the}{\b0 \f20 \fs18 64}{\b0 \f20 \fs18
memory}{\b0 \f20 \fs18 cells}{\b0 \f20 \fs18 inside}{\b0 \f20 \fs18 the
}{\b0 \f20 \fs18 64-bit}{\b0 \f20 \fs18 memory.}{\b0 \f20 \fs18 The}{\b0 \
f20 \fs18 memory}{\b0 \f20 \fs19 is }
\b0 \f20 \fs18 organized}{\b0 \f20 \fs18 into}{\b0 \f20 \fs18 16}{\b0 \f20 \
fs18 groups}{\b0 \f20 \fs19 of}{\b0 \f20 \fs18 4}{\b0 \f20 \fs18 bits}{\b0 \
f20 \fs18 each.}{\b0 \f20 \fs18 Each}{\b0 \f20 \fs18 4-bit}{\b0 \f20 \fs18 g
roup}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 called}{\b0 \f20 \fs18 a}{\i \f20 \f
s18 word.}{\b0 \f20 \fs18 This}{\b0 \f20 \fs18 memory}{\b0 \f20 \fs18 is}{\b
0 \f20 \fs18 said}{\b0 \f20 \fs18 to}{\b0 \f20 \fs18 be }
\b0 \f20 \fs18 organized}{\b0 \f20 \fs18 as}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18
16}{\b0 \fs15 X}{\b0 \f20 \fs18 4}{\b0 \f20 \fs18 memory.}{\b0 \f20 \fs19
It}{\b0 \f20 \fs18 contains}{\b0 \f20 \fs19 16}{\b0 \f20 \fs18 words}{\b0
\f20 \fs18 of}{\b0 \f20 \fs18 4}{\b0 \f20 \fs18 bits}{\b0 \f20 \fs18 each
.}{\b0 \f20 \fs18 The}{\b0 \f20 \fs18 representation}{\b0 \f20 \fs18 of}{\b0
\f20 \fs18 the}{\b0 \f20 \fs18 64-bit }
\b0 \f20 \fs18 memory}{\b0 \f20 \fs18 shown}{\b0 \f20 \fs18 in}{\b0 \f20 \fs18
Fig.}{\b0 \f20 \fs18 12-2is}{\b0 \f20 \fs18 a}{\b0 \f20 \fs18 programmer's}
{\b0 \f20 \fs18 view}{\b0 \f20 \fs18 of}{\b0 \f20 \fs18 this}{\b0 \f20 \fs18
unit.}{\b0 \f20 \fs18 Electronically}{\b0 \f20 \fs18 it}{\b0 \f20 \fs18 is}{
\b0 \f20 \fs18 organized}{\b0 \f20 \fs18 somewhat }
\b0 \f20 \fs18 differently. }\par
}
{\phpg\posx2585\pvpg\posy9381\absw620\absh545 \f20 \fs16 \cf0 \f20 \fs16 \cf0 Wo
rd{\fs17 5 }
\par}{\phpg\posx2585\pvpg\posy9381\absw620\absh545 \sl-197 \par\f20 \fs16 \cf0 W
ord{\b \fs16 6 }\par
}
\cf0 Fig.{\f10 \fs15 12-2}{\b0
Organization}{\b0 \fs16 of}{\b0 a}{\b0
64-bit}{\b0 \fs17 memory }\par
}
8 \cf0 Consider the memory shown in Fig. 12-2to be a RAM. If the RAM (read/write
memory) were in
{\i \fs19 write}{\i \fs19 mode,} data (such as 1101)could be written into the
memory as shown after word{\fs19 5.} The write
cess is similar to writing on a scratch pad. If the RAM were in the{\i \fs19 r
ead}{\i \fs19 mode,} data (such as 1101)
\par}{\phpg\posx857\pvpg\posy11523\absw9265\absh1701 \sl-234 \f20 \fs18 \cf0 cou
ld be read from the memory. The process is similar to reading the 1101 fr
om word location{\i \fs19 5} in
. 12-2.{\b A}{\fs19 RAM} memory{\fs18 of} this type is sometimes called
a{\i \fs19 scratch-pad}{\i \fs19 memory.} Reading word{\i \fs19 5 }
01) does not destroy the contents of the memory;{\fs17 it} is said that the re
ad process is{\i \fs19 nondestructive. }
memory in Fig. 12-2 is a{\i \fs19 random-access}{\i \fs19 memory} beca
use one can skip down to word{\i \fs19 5} or any
\par}{\phpg\posx857\pvpg\posy11523\absw9265\absh1701 \sl-239 \f20 \fs18 \cf0 oth
er word with ease. \par
}
0 CHAP.{\fs17 121 }\par
}
cf0 MICROCOMPUTER MEMORY \par
}
\par
}
\cf0 A logic diagram{\fs18 of} a simple{\b \f30 \fs21 RAM}{\fs19 IC} is draw
n in Fig. 12-3a. 'The 74F189{\b TTL}{\fs19 RAM}{\fs19 IC} is a 64-bit
\par}{\phpg\posx849\pvpg\posy1350\absw9073\absh2143 \sl-243 \f20 \fs19 \cf0 read
/write random-access memory. The 74F189{\fs19 IC} is from the newer Fa
irchild advanced Schottky
18 TT'L,} FAST, a subfamily that exhibits a combination{\fs18 of} performance
and efficiency unapproached by
\par}{\phpg\posx849\pvpg\posy1350\absw9073\absh2143 \sl-241 \f20 \fs19 \cf0 any
other{\fs19 TTL} family. Its internal organization is similar to that shown in
Fig. 12-2. It has 16 words,
of which is 4 bits long for a total{\fs18 of} 64 memory locations.
cf0 \fi6620 {\b \fs15 Inverted}{\b \fs15 data}{\b \fs15 output }
008 {\b \fs15 indicators }
746 {\fs16 +5v }\par
}
3:: \par
}
cf0 64{\fs15 bit }
b0 \fs15 RAM }\par
}
cf0 8s
0 \fi137 {\b0 \f10 c }\par
}
11 \cf0 A2
cf0 {\fs14 A3 }
\fi27 {\b0\i0 \f10 \fs19 - }\par
}

cf0 cs
i0 \f10 \fs19 - }\par
}
W E \par
}
par
}
s14 \cf0 D3
\cf0 {\fs11 D2 }
\cf0 {\fs10 D}{\fs10 i }
\cf0 {\fs15 DO }\par
}
cf0 (74F189) \par
}
cf0 GND \par
}
\par
}
s10 \cf0 (U){\i0 \f20 \fs15 Logic}{\i0 \f20 \fs15 symbol }\par
}
\cf0 Inputs
fi432 {\b0 \f10 \fs19 - }
fi442 {\b0\i \fs15 WE }
fi513 {\fs15 L }
fi500 H
fi503 {\fs15 X }\par
}
fs64 \cf0 c
i0 \f30 \fs90 I }\par
}
\cf0 Address inputs \par
}
\fs15 \cf0 Chip select
f0 \fi236 Write enable
\fs16 L}{\b0\dn006 \f10 \fs11 =} write,{\fs15 H}{\b0 \f10 \fs11 =} read \par
}

fs15 \cf0 Input
\par}{\phpg\posx1699\pvpg\posy5613\absw676\absh367 \sl-211 \b \f20 \fs15 \cf0 co
ntrols \par
}
cf0 r \par
}
10 \cf0 ' 3 \par
}
cf0 Data inputs \par
}
10 \cf0 ' \par
}
\cf0 Operating mode
\par}{\phpg\posx3191\pvpg\posy9149\absw1275\absh775 \sl-270 \b \f20 \fs15 \cf0 W
rite
\par}{\phpg\posx3191\pvpg\posy9149\absw1275\absh775 \sl-200 \b \f20 \fs15 \cf0 R
ead
tore (inhibit) \par
}
{\phpg\posx4795\pvpg\posy8957\absw241\absh948 \f10 \fs19 \cf0 \f10 \fs19 \cf0 \par}{\phpg\posx4795\pvpg\posy8957\absw241\absh948 \sl-153 \f10 \fs19 \cf0 {\b\i
\f20 \fs15 CS }
{\b \f20 \fs15 L }
{\b \f20 \fs15 L }
{\b \f20 \fs15 H }\par
}
\cf0 Condition{\fs15 of} outputs
igh impedance
\par}{\phpg\posx6201\pvpg\posy9141\absw2140\absh779 \sl-195 \b \f20 \fs15 \cf0 C
omplement of stored data
igh impedance \par
}
\f20 \fs15 \cf0 (b){\i0 Operating}{\i0 modes }
0 {\i0 \fs16 Fig.}{\i0 \fs16 12-3}{\i0 \fs17
74F189}{\i0 \fs17 64-bit}{\i0
\fs17 static}{\b0\i0 \fs17 RAM }\par
}
9 \cf0 The modes of operation for the 74F189{\b \fs19 RAM} IC are detailed in
Fig. 12-3b. The first line{\fs18 of} the
During the write operation, the 4 input data bits{\i (D,,}{\i \fs19 D,,}{\i
\fs19 D,,}{\i Do)}are written into the memory word
\par}{\phpg\posx871\pvpg\posy11984\absw8956\absh1070 \sl-240 \f20 \fs19 \cf0 loc
ation specified by the address inputs. For instance, to write 1101 into word l
ocation{\fs19 5} as shown in

. 12-2, the data inputs must be{\i D,}{\f10 \fs14 =} 1,{\b\i \f30 \fs21 D,}{
\f10 \fs14 =} 1,{\b\i \f30 \fs21 D, }{\dn006 \f10 \fs14 =}{\fs18 0,} and{\i
Do}{\f10 \fs14 =}{\fs18 1}and the address inputs must be \par
}
(a
}{\phpg\posx7647\pvpg\posy12080\absw2076\absh360 \f30 \fs35 \cf0 \fi0 {\f20 \fs1
9 and}{\f20 \fs25 E)}{\f20 \fs19 are}{\b \f20 \fs19 LOW. }\par
}
hart illustrates the{\b\i \fs18 write}{\b\i mode.} Note from Fig. 12-3b that b
oth control inputs \par
}
18 \cf0 A,{\b0\i0\dn006 \f10 \fs13 = }\par
}
0,{\b\i \fs18 A}{\b\i \fs18 ,}{\f10 \fs14 =}{\fs19 1,}{\b\i \f10 \fs18 A}
{\b\i \f10 \fs18 ,}{\f10 \fs14 =} 0,{\b\i \fs19 A}{\b\i \fs19 ,}{\f10 \fs14
=}{\fs19 1.}{\fs19 Next,}{\fs19 the}{\fs19 write}{\fs19 enable}{\fs19
input}{\fs25 (WE)}{\fs19 must}{\fs19 be}{\b \fs19 LOW.}{\fs19 Finally,}
{\fs19 the}{\fs19 chip }\par
}
\par
}
}
AP.{\fs17 12 }\par
}
15 \cf0 +5{\b0\i0 \f20 \fs22 v }\par
}
dress
s \par
}
cf0 -iA4 \par
}
cf0 1/01 \par
}
s14 \cf0 (a){\b0\i0 Logic}{\b0\i0 diagram }\par
}
cf0 Row
4 select }\par
}
{\phpg\posx5641\pvpg\posy7542\absw985\absh484 \f20 \fs14 \cf0 \f20 \fs14 \cf0 Me
mory array
1 {\b \f10 \fs14 64}{\fs15 rows }

{\b \fs15 64} columns \par
}
\par
}
olumn{\fs15 1/0} circuits \par
}
\cf0 (h){\i0 \f20 \fs14 Block}{\i0 \f20 \fs14 diagram}{\b \f20 \fs14 (Cour
tesy}{\fs17 of'}{\b \f20 \fs14 Intel}{\b \f20 \fs14 Corporation) }
cf0 \fi247 {\b\i0 \f20 \fs16 Fig.}{\b\i0 \fs15 12-4}{\i0 \f20 \fs17
MOS}{\i0
\f20 \fs16 static}{\i0 \f20 \fs17 RAM}{\b\i0 \f20 \fs17 (1024}{\i0 \fs13 X}
{\b \f20 \fs16 3) }\par
}
.{\fs17 121 }\par
}
}
\par
}
\cf0 (a)
0 \fs18 will}{\f20 \fs18 be}{\f20 \fs18 noted}{\f20 \fs18 that}{\f20 \fs18
the}{\f20 \fs18 outputs}{\f20 \fs18 of}{\f20 \fs18 the}{\f20 \fs18 74F189}
{\f20 \fs18 RAM}{\f20 \fs18 remain}{\f20 \fs18 in}{\f20 \fs18 their}{\f20 \
fs18 high}{\f20 \fs18 impedance}{\f20 \fs18 state}{\f20 \fs18 during}{\f20
\fs18 the }
0 \fs18 write}{\f20 \fs18 operation. }
69 {\f20 \fs18 The}{\f20 \fs18 second}{\f20 \fs18 line}{\f20 \fs19 of}{\f20 \
fs18 the}{\f20 \fs18 table}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20 \fs18 12-3
b}{\f20 \fs18 shows}{\f20 \fs18 the}{\f20 \fs18 read}{\f20 \fs18 mode}{\f20
\fs18 for}{\f20 \fs18 the}{\f20 \fs18 74F189}{\f20 \fs18 RAM.}{\f20 \fs18
The}{\f20 \fs18 input }
178 {\f20 \fs19 LOW }{\dn006 \f10 \fs15 -}{\f20 \fs18 and }{\dn006 \f10 \fs15
-}{\f20 \fs25 E=}{\f20 \fs18 HIGH.}{\f20 \fs18 The}{\f20 \fs18 contents}{\f2
0 \fs19 of}{\f20 \fs18 the}{\f20 \fs18 memory}{\f20 \fs18 location }
0 \fs18 addressed}{\f20 \fs18 will}{\f20 \fs18 appear}{\f20 \fs18 at}{\f20 \f
s18 the}{\f20 \fs18 outputs}{\i \f20 \fs24 (03, }
0 \fs18 at}{\f20 \fs18 the}{\f20 \fs18 outputs}{\f20 \fs18 on}{\f20 \fs18 th
e}{\f20 \fs18 logic}{\f20 \fs18 symbol}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20
\fs18 12-3a.}{\f20 \fs18 For}{\f20 \fs18 example,}{\f20 \fs18 to}{\f20 \fs1
8 read}{\f20 \fs18 the}{\f20 \fs18 contents}{\f20 \fs19 of}{\f20 \fs18 word
}{\f20 \fs19 5}{\f20 \fs18 (address }
355 {\f20 \fs18 must}{\f20 \fs18 be}{\f20 \fs18 activated}{\f20 \fs18 with}
{\f20 \fs18 a}{\f20 \fs18 LOW}{\f20 \fs18 and}{\f20 \fs18 the }

0 \fs18 write}{\f20 \fs18 enable}{\f10 \fs21 (-1 }
96 {\f10 \fs13 =}{\f20 \fs18 1.}{\f20 \fs18 The}{\f20 \fs18 outputs}{\f20 \fs
18 indicate}{\f20 \fs18 0010,}{\f20 \fs18 which}{\f20 \fs18 is}{\f20 \fs18
the}{\f20 \fs18 complement}{\f20 \fs18 of}{\f20 \fs18 the}{\f20 \fs18 tru
e}{\f20 \fs18 data}{\f20 \fs18 1101}{\f20 \fs18 located}{\f20 \fs18 at }
0 \fs18 address}{\f20 \fs18 location}{\i \f20 \fs19 5}{\f20 \fs18 in}{\f20 \f
s18 the}{\f20 \fs18 RAM.}{\f20 \fs18 It}{\f20 \fs18 should}{\f20 \fs18 be}{
\f20 \fs18 understood}{\f20 \fs18 that}{\f20 \fs18 the}{\f20 \fs18 read}{\f2
0 \fs18 operation}{\f20 \fs18 does}{\f20 \fs18 not}{\f20 \fs18 destroy}{\f2
0 \fs18 the }
0 \fs18 stored}{\f20 \fs18 data}{\f20 \fs18 in}{\f20 \fs18 memory}{\f20 \fs18
location}{\i \f20 \fs19 5}{\f20 \fs18 but}{\f20 \fs18 outputs}{\f20 \fs18
an}{\f20 \fs18 inverted}{\b\i \f20 \fs18 copy}{\f20 \fs19 of}{\f20 \fs18
that}{\f20 \fs18 data. }
68 {\f20 \fs18 The}{\f20 \fs18 bottom}{\f20 \fs18 line}{\f20 \fs18 in}{\f20
\fs18 the}{\f20 \fs18 table}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20 \fs18
12-3b}{\f20 \fs18 illustrates}{\f20 \fs18 the}{\f20 \fs18 store}{\f20 \f
s18 or}{\f20 \fs18 inhibit}{\f20 \fs18 mode.}{\f20 \fs18 When}{\f20 \fs18
the}{\f20 \fs18 chip }
71 {\fs37 (a) }
0 \fs18 select}{\f20 \fs18
input}{\f20 \fs18 is}{\f20 \fs18 deactiv
ated}{\f20 \fs18 with}{\f20 \fs18 a}{\f20 \fs18 HIGH,}{\f20 \fs18 the}{\f2
0 \fs18 outputs}{\f20 \fs18 go}{\f20 \fs18 to}{\f20 \fs18 a}{\f20 \fs18 hi
gh}{\f20 \fs18 impedance}{\f20 \fs18 state}{\f20 \fs18 (they}{\f20 \fs18 fl
oat) }
0 \fs18 and}{\f20 \fs18 the}{\f20 \fs18 read}{\f20 \fs18 and}{\f20 \fs18 wr
ite}{\f20 \fs18 operations}{\f20 \fs18 are}{\f20 \fs18 inhibited.}{\f20 \fs18
It}{\f20 \fs18 can}{\f20 \fs18 be}{\f20 \fs18 said}{\f20 \fs18 that}{\f20
\fs18 the}{\f20 \fs18 memory}{\f20 \fs18 is}{\f20 \fs18 "storing"}{\f20 \fs1
8 data. }
69 {\f20 \fs18 The}{\f20 \fs18 74F189}{\f20 \fs18 IC}{\f20 \fs18 is}{\f20
\fs18 an}{\f20 \fs18 example}{\f20 \fs18 of}{\f20 \fs18 a}{\f20 \fs18
static}{\f20 \fs18 RAM.}{\f20 \fs18 A}{\f20 \fs18 static}{\f20 \fs18 RAM
}{\f20 \fs18 can}{\f20 \fs18 be}{\f20 \fs18 fabricated}{\f20 \fs18 using
}{\f20 \fs18 either }
0 \fs18 bipolar}{\f20 \fs18 or}{\f20 \fs18 MOS}{\f20 \fs18 technology.}{\f2
0 \fs18 The}{\f20 \fs18 static}{\f20 \fs18 RAM}{\f20 \fs18 uses}{\f20 \fs18
flip-flops}{\f20 \fs18 (or}{\f20 \fs18 similar}{\f20 \fs18 circuits)}{\f20 \
fs18 as}{\f20 \fs18 memory}{\f20 \fs18 cells}{\f20 \fs18 and }
0 \fs18 holds}{\f20 \fs18 its}{\f20 \fs18 data}{\f20 \fs18 as}{\f20 \fs18
long}{\f20 \fs18 as}{\f20 \fs18 power}{\f20 \fs18 is}{\f20 \fs18 suppli
ed}{\f20 \fs18 to}{\f20 \fs18 the}{\f20 \fs18 chip.}{\f20 \fs18 Large-ca
pacity}{\f20 \fs18 temporary}{\f20 \fs18 storage}{\f20 \fs18 units}{\f20 \fs
18 are }
0 \fs18 usually}{\f20 \fs18 dynamic}{\i \f20 \fs19 RAMs.}{\f20 \fs18 A}{\f2
0 \fs18 dynamic}{\f20 \fs18 RAM'S}{\f20 \fs18 memory}{\f20 \fs18 cell}{\f
20 \fs18 is}{\f20 \fs18 based}{\f20 \fs19 on}{\f20 \fs18 an}{\f20 \fs18
MOS}{\f20 \fs18 device}{\f20 \fs18 that}{\f20 \fs18 stores}{\f20 \fs18

a }
0 \fs18 charge}{\f20 \fs18 (much}{\f20 \fs18 like}{\f20 \fs18 a}{\f20 \fs18
small}{\f20 \fs18 capacitor).}{\f20 \fs18 The}{\f20 \fs18 difficulty}{\f20 \f
s18 with}{\f20 \fs18 dynamic}{\f20 \fs19 RAMs}{\f20 \fs18 (DRAMS)is}{\f20 \f
s18 that}{\f20 \fs18 all}{\f20 \fs18 memory }
0 \fs18 cells}{\f20 \fs18 must}{\f20 \fs18 be}{\f20 \fs18 refreshed}{\f20 \fs
18 every}{\f20 \fs18 few}{\f20 \fs18 milliseconds}{\f20 \fs18 to}{\f20 \fs1
8 retain}{\f20 \fs18 data. }
73 {\f20 \fs18 The}{\f20 \fs18 2114}{\f20 \fs18 static}{\f20 \fs18 RAM}{\f20
\fs18 is}{\f20 \fs18 a}{\f20 \fs18 popular}{\f20 \fs18 MOS}{\f20 \fs18 mem
ory}{\f20 \fs18 IC.}{\f20 \fs18 It}{\f20 \fs18 will}{\f20 \fs18 store}{\f20
\fs18 4096}{\f20 \fs18 bits,}{\f20 \fs18 which}{\f20 \fs18 are}{\f20 \fs18
organized }
0 \fs18 into}{\f20 \fs18 1024}{\f20 \fs18 words}{\f20 \fs18 of}{\f20 \fs18
4}{\f20 \fs18 bits}{\f20 \fs18 each.}{\f20 \fs18 A}{\f20 \fs18 logic}{\f20 \
fs18 diagram}{\f20 \fs18 of}{\f20 \fs18 the}{\f20 \fs18 2114}{\f20 \fs18 RA
M}{\f20 \fs18 is}{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20 \fs18 12-4a.}{\f20 \f
s18 Note}{\f20 \fs18 that}{\f20 \fs18 the}{\f20 \fs18 2114 }
546 {\f20 \fs18 and }
694 {\f20 \fs18 control}{\f20 \fs18 inputs,}{\f20 \fs18 1/01,}{\f20 \fs18 1
/02,}{\f20 \fs18 1/03,}{\f20 \fs18 and}{\f20 \fs19 I/O,}{\f20 \fs18
are}{\f
20 \fs18 inputs}{\f20 \fs18 when}{\f20 \fs18 the}{\fs22 RAM}{\f20 \fs18 is}
{\f20 \fs18 in}{\f20 \fs18 the }
0 \fs18 write}{\f20 \fs18 mode}{\f20 \fs18 and}{\f20 \fs18 outputs}{\f20 \
fs18 when}{\f20 \fs18 the}{\f20 \fs18 IC}{\f20 \fs18 is}{\f20 \fs18 in}{\
f20 \fs18 the}{\f20 \fs18 read}{\f20 \fs18 mode.}{\f20 \fs18 The}{\f20 \f
s18 2114}{\f20 \fs18 RAM}{\f20 \fs18 is}{\f20 \fs18 powered}{\f20 \fs18
by}{\f20 \fs18 a}{\f20 \fs19 +5-V }
0 \fs18 power}{\f20 \fs18 supply. }
76 {\f20 \fs18 A}{\f20 \fs18 block}{\f20 \fs18 diagram}{\f20 \fs18 of}{\f20 \
fs18 the}{\f20 \fs18 2114}{\f20 \fs18 RAM}{\f20 \fs18 is}{\f20 \fs18 shown}
{\f20 \fs18 in}{\f20 \fs18 Fig.}{\f20 \fs18 12-4b.}{\f20 \fs18 Note}{\f20 \f
s18 especially}{\f20 \fs18 the}{\f20 \fs18 three-state}{\f20 \fs18 buffers }
0 \fs18 used}{\f20 \fs18 to}{\f20 \fs18 isolate}{\f20 \fs18 the}{\f20 \fs18
data}{\f20 \fs18 bus}{\f20 \fs18 from}{\f20 \fs18 the}{\f20 \fs18 input/o
utput}{\f20 \fs18 (I/O)}{\f20 \fs18 pins.}{\f20 \fs18 Note}{\f20 \fs18 th
at}{\f20 \fs18 the}{\f20 \fs18 address}{\f20 \fs18 lines}{\f20 \fs18 also}{
\f20 \fs18 are }
0 \fs18 buffered.}{\f20 \fs18 The}{\f20 \fs18 2114}{\f20 \fs18 RAM}{\f20 \fs1
8 comes}{\f20 \fs18 in}{\f20 \fs18 18-pin}{\f20 \fs19 DIP}{\f20 \fs18 IC}{
\f20 \fs18 form. }
69 {\f20 \fs18 Microprocessor-based}{\f20 \fs18 systems}{\f20 \fs18 (such}{\f
20 \fs18 as}{\f20 \fs18 microcomputers)}{\f20 \fs18 typically}{\f20 \fs18 st
ore}{\f20 \fs18 and}{\f20 \fs18 transfer}{\f20 \fs18 data}{\f20 \fs18 in}{\
f20 \fs18 8-bit }
0 \fs18 groups}{\f20 \fs18 called}{\f20 \fs18 words.}{\f20 \fs18 Two}{\f20
\fs18 2114}{\f20 \fs18 RAMs}{\f20 \fs18 are}{\f20 \fs18 connected}{\f20 \fs

18 in}{\f20 \fs18 Fig.}{\f20 \fs18 12-5}{\f20 \fs18 to}{\f20 \fs18 form
}{\f20 \fs18 a}{\f20 \fs18 RAM}{\f20 \fs18 memory}{\f20 \fs19 of}{\f20 \f
s18 1024 }
0 \fs18 words}{\f20 \fs18 each}{\f20 \fs19 8}{\f20 \fs18 bits}{\f20 \fs18
wide.}{\f20 \fs18 This}{\f20 \fs18 is}{\f20 \fs18 referred}{\f20 \fs18 to}{
\f20 \fs18 as}{\f20 \fs19 1K}{\f20 \fs18 of}{\f20 \fs18 memory}{\f20 \fs18
in}{\f20 \fs18 most}{\f20 \fs18 microcomputers,}{\f20 \fs18 that}{\f20
\fs18 is,}{\f20 \fs18 1024 }
0 \fs18 bytes}{\f20 \fs18 (8-bit}{\f20 \fs18 groups)}{\f20 \fs18 of}{\f20 \fs
18 memory.}{\f20 \fs18 Note}{\f20 \fs18 that}{\f20 \fs18 the}{\f20 \fs18 le
ft}{\f20 \fs18 2114}{\f20 \fs18 RAM}{\f20 \fs18 furnishes}{\f20 \fs18 the}{\
f20 \fs18 least}{\f20 \fs18 significant}{\f20 \fs18 4}{\f20 \fs18 bits}{\f20
\fs18 of}{\f20 \fs18 a }\par
}
lect
input must go LOW. Memory address location{\i \fs19 5} (word{\fs
19 5)} now contains the data{\fs19 1101.} It \par
}
{\phpg\posx3543\pvpg\posy2178\absw632\absh438 \f30 \fs37 \cf0 \f30 \fs37 \cf0 a=
\par
}
ntrols must be set{\fs19 so} that \par
}
,,0,,{\i \fs19 0,)}{\fs18 in}{\fs18 complementary}{\fs18 form.}{\fs18 Note}{
\fs18 the}{\fs18 invert}{\fs18 bubbles }\par
}
}
{\phpg\posx5737\pvpg\posy2898\absw924\absh358 \f30 \fs37 \cf0 \f30 \fs37 \cf0 (a
) \par
}
{\phpg\posx849\pvpg\posy3053\absw4844\absh221 \f20 \fs18 \cf0 \f20 \fs18 \cf0 lo
cation{\i \fs19 5)} in the memory in Fig. 12-2, the chip select \par
}
8 \cf0 A ,{\b0\i0\dn006 \f10 \fs13 =}{\b0\i0 \fs19 0,}{\fs19 A, }\par
}
ust be deactivated with a HIGH. The address inputs must be{\b\i A}{\b
\i ,}{\f10 \fs14 =}{\fs19 0,}{\b\i A}{\b\i ,}{\f10 \fs14 =}{\fs19 1, }\p
ar
}
{\phpg\posx8929\pvpg\posy6741\absw924\absh202 \f30 \fs37 \cf0 \f30 \fs37 \cf0 (a
) \par
}
{\phpg\posx851\pvpg\posy6910\absw8312\absh444 \f20 \fs18 \cf0 \f20 \fs18 \cf0 RA
M has 10 address lines which can access 1024 (2") words. It has the familiar ch
ip select
\par}{\phpg\posx851\pvpg\posy6910\absw8312\absh444 \sl-251 \f20 \fs18 \cf0 write
enable{\fs25 (E) }\par
}
\cf0 Fig.{\fs17 12-5}{\b0 \fs17
Combining}{\b0 \fs16 two}{\b0 \fs17 1K}{
\b0 \f10 \fs13 X}{\b0 \fs17 4}{\b0 \fs17 RAMs}{\b0 \fs17 to}{\b0 \fs17 form
}{\b0 \fs17 a}{\b0 \fs17 1K}{\b0 \f10 \fs13 X}{\fs17 8}{\b0 \fs17 RAM }\pa
r
}
\par
}
}
AP. 12 \par
}
ord and the right 2114{\fs19 RAM} furnishes the 4 most significant bits.
The 2114{\fs19 RAM} has the proper
\par}{\phpg\posx847\pvpg\posy1336\absw9354\absh4298 \sl-237 \f20 \fs18 \cf0 buff
ering to interface with the system address bus and data bus.
80 Often-mentioned characteristics of{\fs19 RAMs} are size (in bits) an
d organization (words{\f10 \fs15 X} bits per
\par}{\phpg\posx847\pvpg\posy1336\absw9354\absh4298 \sl-237 \f20 \fs18 \cf0 word
). For the 2114{\fs19 RAM} this would be 4096 bits, or 1024{\f10 \fs14 X} 4.
For the 74F189{\fs19 RAM} this would be 64
\par}{\phpg\posx847\pvpg\posy1336\absw9354\absh4298 \sl-238 \f20 \fs18 \cf0 bits
, or 16{\f10 \fs15 X} 4.{\fs19 A} second characteristic might be the technolo
gy used to fabricate the chip. This would
\par}{\phpg\posx847\pvpg\posy1336\absw9354\absh4298 \sl-237 \f20 \fs18 \cf0 be{\
b\i \fs19 NMOS}{\i \fs19 (N-channel}{\i \fs19 metal}{\i \fs19 oxide}{\i \
fs19 semiconductor)} for the 2114{\fs19 RAM.} The 74F189 uses the ne
w
0 Fairchild advanced Schottky{\fs19 TTL} technology.{\fs19 A} third characteri
stic might be the type of output. Both
0 the 2114 and 74F189{\fs19 RAMs} have three-state outputs.
73 {\fs19 A} fourth characteristic might be the access time (speed) of the m
emory chip. The{\i \fs19 access}{\b\i time} is
time it takes to locate and read data from a{\fs19 RAM.} The access time of the
2114{\fs19 RAM} may be from
19 50} to 450 ns, depending on which version you specify. The access time
of the 74F189{\fs19 RAM}{\fs19 is} only
3 about 10 ns. The 74F189 is said to be a faster memory. Faster memories are mor
e expensive than their
3 slower counterparts.
80 {\fs19 A} fifth characteristic might be the type of memory: either sta
tic{\fs19 (SRAM)} or dynamic{\fs19 (DRAM). }
3 Both the 2114 and 74F189{\fs19 ICs} are static{\fs19 RAMs.} The packa
ging and power supply voltage are{\fs19 two }
\par}{\phpg\posx847\pvpg\posy1336\absw9354\absh4298 \sl-237 \f20 \fs18 \cf0 othe
r common specifications for{\fs19 RAMs.} The 2114{\fs19 RAM} is packaged in an
18-pin{\fs19 DIP.} The 74F189{\b \fs19 IC }

3 is housed in either a 16-pin{\fs19 DIP} or in a 16-pin{\fs19 LCC} (leadless
chip carrier) package. Both the 2114 and
3 74F189{\fs19 RAMs} operate on a{\fs19 5-V} dc power supply.
}
cf0 12.1{\b0
The}{\b0 letters}{\b0 \fs19 ROM}{\b0 stand}{\b0 for }
}
par
}
n digital electronics. \par
}
he letters ROM stand for read-only memory. \par
}
cf0 12.2{\b0
The}{\b0 letters}{\b0 \fs19 RAM}{\b0 literally}{\b0 stand}{
\b0 for }
i1283 {\b0 memory. }
}
par
}
emory, but in practice they designate{\fs18 a }\par
}
\cf0 The letters RAM literally stand for random-access memory, bu
t in practice they designate a
\par}{\phpg\posx1461\pvpg\posy8235\absw8257\absh390 \sl-220 \f20 \fs17 \cf0 read
/write memory. \par
}
cf0 12.3{\b0
The}{\b0 \fs19 ROM}{\b0 is }
}
nonvolatile, volatile), whereas the{\fs19 RAM}{\fs19 is} a \par
}
{\phpg\posx8089\pvpg\posy8963\absw844\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 me
mory. \par
}
\cf0 12.4{\b0
The }
fi589 {\b0 the }
}

he ROM is nonvolatile, whereas the RAM{\fs16 is} a volatile memory.
\fi761 {\fs18 (read,}{\fs18 write)}{\fs18 process}{\fs18 in}{\fs18 a}{\fs19
RAM}{\fs18 consists}{\fs18 of}{\fs18 putting}{\fs18 data}{\fs18 into}{\fs1
8 the}{\fs18 memory,}{\fs18 whereas }
85 {\fs18 (read,}{\fs18 write)}{\fs18 process}{\fs18 consists}{\fs18 of}{\fs
18 revealing}{\fs18 the}{\fs18 stored}{\fs18 contents}{\fs18 of}{\fs18 a}{
\fs18 memory}{\fs18 location. }\par
}
7 \cf0 The write process in a RAM consists of putting data into the
memory, whereas the read process
sists{\fs16 of} revealing the stored contents of a memory location. \par
}
\cf0 12.5{\b0
The }
}
9 \cf0 (RAM, ROM){\fs18 is}{\fs18 easily}{\fs18 erased. }
{\fs17 The}{\fs17 RAM}{\fs17 is}{\fs17 easily}{\fs17 erased. }\par
}
\cf0 12.6{\b0 \fs19
A}{\b0 32}{\b0 \f10 \fs15 X}{\b0 \fs18 8}{\b0 memory
}{\b0 would}{\b0 contain }
fi1281 {\b0 bits. }
}
words, each \par
}
bits long, for a total capacity of \par
}
A{\b \fs17 32}{\f10 \fs13 X} 8 memory would contain 32 words, each 8 bits
long, for a total capacity of{\fs17 256} bits. \par
}
. 121 \par
}
}
\par
}
\cf0 12.7{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 mode}{\b0 \fs19 of}{\b
0 \fs19 operation}{\b0 \fs19 of}{\b0 \fs19 the}{\fs18 74F189}{\fs19 RAM}{\b
0 \fs19 for}{\b0 \fs19 each}{\b0 \fs19 input}{\b0 \fs19 pulse}{\b0 \fs19 sh
own}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs18 12-6. }

fi947 {\b0 \fs17 The}{\b0 \f10 \fs20 %!?}{\b0 \fs17 and}{\b0 \fs17
in
puts}{\b0 \fs17 in}{\b0 \fs17 the}{\b0 \fs17 memory}{\b0 \fs17 control}{
\b0 \fs17 the}{\b0 \fs17 operation}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs
17 RAM.}{\b0 \fs17 The}{\b0 \fs17 modes}{\b0 \fs17 of}{\b0 \fs17 opera
tion }
fi590 {\b0 \fs16 for}{\b0 \fs17 the}{\b0 \fs17 RAM}{\b0 \fs17 in}{\b0 \fs1
7 Fig.}{\b0 \fs17 12-6}{\b0 \fs17 are}{\b0 \fs17 as}{\b0 \fs17 follows:
}
fi590 {\b0 \fs17 pulses}{\i \fs16 a}{\b0 \fs17 to}{\b0 \fs16 i}{\b0\dn006
\f10 \fs11 =}{\b0 \fs17 write }
fi590 {\b0 \fs17 pulse}{\b0 \fs15 j}{\b0 \f10 \fs13 =}{\b0 \fs17 stored}{\b0
\fs17 (inhibit}{\b0 \fs17 read}{\b0 \fs17 and}{\b0 \fs17 write) }
fi589 {\b0 \fs17 pulse}{\i \fs17 k}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 read
}
fi590 {\b0 \fs17 pulse}{\b0 \fs17 1}{\b0 \f10 \fs13 =}{\b0 \fs17 read }\par
}
\cf0 Output{\fs15 indicators }\par
}
\cf0 ) O @ @ \par
}
}
14 \cf0 +5{\b0\i0 \f20 \fs22 v }\par
}
5 \cf0 l \par
}
15 \cf0 k \par
}
5 \cf0 j \par
}
5 \cf0 i \par
}
15 \cf0 h \par
}
5 \cf0 g \par
}
5 \cf0 f \par
}
15 \cf0 e

{\b0\i0 0 }\par
}
15 \cf0 d \par
}
5 \cf0 c \par
}
15 \cf0 b \par
}
15 \cf0 a \par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\cf0 Fig. 12-6{\b0 \fs17
Static}{\fs17 RAM}{\b0 \fs17 pulse-train}{\b0 \fs1
7 problem }\par
}
cf0 12.8{\b0 \fs19
List}{\b0 \fs19 the}{\b0 \fs19 memory}{\b0 \fs19 conte
nts}{\b0 \fs18 of}{\b0 \fs19 word}{\b0 \fs19 Iocations}{\b0 \fs18 0}{\b0 \fs
19 through}{\b0 \fs18 8}{\b0 \fs19 after}{\b0 \fs19 pulse}{\b0\i \fs19 I}{
\b0\i \fs19 ,}{\b0 \fs19 Fig.}{\fs18 12-6. }
i947 {\b0 \fs17 The}{\b0 \fs17 memory}{\b0 \fs17 contents}{\b0 \fs17 of}{\
b0 \fs17 the}{\b0 \fs17 74F189}{\b0 \fs17 RAM}{\b0 \fs17 (Fig.}{\b0 \fs1
7 12-6)}{\b0 \fs17 after}{\b0 \fs17 pulse}{\b0 \fs17 1}{\b0 \fs17 are}{\
b0 \fs17 as}{\b0 \fs17 follows: }\par
}
word 0{\f10 \fs13 =} 0001
0 word{\fs16 1}{\dn006 \f10 \fs11 =} 0010
0 word{\fs16 2}{\dn006 \f10 \fs11 =} 0011
0 word 3{\f10 \fs13 =} 0100
0 word 4{\dn006 \f10 \fs11 =} 0101
0 word{\fs17 5}{\dn006 \f10 \fs11 =} 0110
0 word 6{\dn006 \f10 \fs11 =} 0111

0 word 7{\dn006 \f10 \fs11 =} 1000
0 \fi20 word 8{\dn006 \f10 \fs11 =} 1001 \par
}
Written into memory loca\par}{\phpg\posx5933\pvpg\posy10083\absw2161\absh3497 \sl-210 \f20 \fs17 \cf0 ti
on 0 during pulse{\b\i \fs16 a }
\par}{\phpg\posx5933\pvpg\posy10083\absw2161\absh3497 \sl-215 \f20 \fs17 \cf0 Wr
itten into memory loca\par}{\phpg\posx5933\pvpg\posy10083\absw2161\absh3497 \sl-215 \f20 \fs17 \cf0 ti
on{\fs16 l} during pulse{\fs16 b }
on 2 during pulse{\fs16 c }
on{\b 3} during pulse{\b\i \f10 \fs16 d }
on{\b \f30 \fs17 4} during pulse{\b\i \fs17 e }
on{\i \fs17 5} during pulse{\i \f30 \fs19 f }
on 6 during pulse{\b\i \fs15 g }
on 7 during pulse{\fs17 h }
on 8 during pulse{\b\i \f30 \fs17 i }\par
}
0 286 \par
}
}
f0 [CHAP.{\b0 \fs17 12 }\par
}
\cf0 12.9{\b0
What}{\b0 is}{\b0 the}{\b0 state}{\b0 of}{\b0 the}{\b0
output}{\b0 indicators}{\b0 during}{\b0 input}{\b0 pulse}{\i \fs19 k}{\b0
in}{\b0 Fig.}{\b0 12-6? }

fi958 {\b0 \fs17 Output}{\b0 \fs17 indicators}{\b0 \fs17 read}{\b0 \fs17 10
01}{\b0 \fs17 during}{\b0 \fs17 pulse}{\i \fs17 k}{\b0 \fs17
which}{\b0 \
fs17 is}{\b0 \fs17 a}{\b0 \fs17 copy}{\b0 \fs17 of}{\b0 \fs17 the}{\b0
\fs17 contents}{\b0 \fs17 of}{\b0 \fs17 memory}{\b0 \fs17 location}{\b0
\fs17 8. }
f0 12.10{\b0 What}{\b0 is}{\b0 the}{\b0 state}{\b0 of}{\b0 the}{\b0 outp
ut}{\b0 indicators}{\b0 during}{\b0 input}{\b0 pulse}{\f10 \fs18 2}{\b0
in}{\b0 Fig.}{\b0 12-6? }
fi958 {\b0 \fs17 Output}{\b0 \fs17 indicators}{\b0 \fs17 read}{\b0 \fs17 10
00}{\b0 \fs17 during}{\b0 \fs17 pulse}{\b0\i \f10 \fs16 1}{\b0 \fs17 which}
{\b0 \fs17 is}{\b0 \fs17 a}{\b0 \fs17 copy}{\b0 \fs17 of}{\b0 \fs17 the}
{\b0 \fs17 contents}{\b0 \fs17 of}{\b0 \fs17 memory}{\b0 \fs17 location}{
\b0 \fs17 7. }\par
}
cf0 12.11{\b0 The}{\b0 access}{\b0 time}{\b0 for}{\b0 the }
i589 {\b0 faster}{\b0 chip. }
}
2114, 74F189) RAM is shorter, and therefore it is considered a \par
}
\cf0 The access time for the 74F189{\b \fs17 RAM} is shorter.
{\b \fs18 12.12}{\fs18 Each}{\fs18 memory}{\fs18 cell}{\fs19 of}{\fs18 thi
s}{\fs18 static}{\fs19 RAM}{\fs18 is}{\fs18 similar}{\fs18 to}{\fs18 a }
51 Each memory cell in a static{\b \fs17 RAM} is similar to a flip-flop.
\par
}
capacitor, flip-flop). \par
}
cf0 12.13{\b0 See}{\b0 Fig.}{\b0 12-4.}{\b0 The}{\b0 10}{\b0 address}{
\b0 lines}{\b0 entering}{\b0 the}{\b0 2114}{\b0 RAM}{\b0 can}{\b0
address }
i582 {\b0 words. }
}
{\phpg\posx8941\pvpg\posy6115\absw799\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 di
fferent \par
}
\cf0 The 10 address lines on the 2114 shown in Fig. 12-4can address a tot
al of 1024(2l") words in{\b \fs17 RAM. }
{\b \fs18 12.14}{\fs18 What}{\fs18 is}{\fs18 meant}{\fs18 when}{\fs18 a}{\
fs18 microcomputer}{\fs18 is}{\fs18 said}{\fs18 to}{\fs18 have}{\fs18 16

K}{\fs18 of}{\fs18 memory? }
72 {\b \fs17 A} computer said to have{\b 16K}{\b \fs17 of} memory has
a 16384-byte memory. Such a memory would have a
12 total capacity of 131072 bits (16384{\f10 \fs13 X} 8{\f10 \fs13 =} 1310
72).
{\b \fs18 12.15}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 12-5.}{\fs18 Why
}{\fs18 can}{\fs18 the}{\fs18 1/0}{\fs18 pins}{\fs18 of}{\fs18 the}{\fs18
RAMs}{\fs18 be}{\fs18 connected}{\fs18 directly}{\fs18 to}{\fs18 the}{\fs
18 data}{\fs18 bus? }
50 The 2114{\fs17 RAMs} shown in Fig. 12-5 have three-state buffered{\fs1
7 1/0} terminals. \par
}
cf0 12.16{\b0 The}{\b0 time}{\b0 it}{\b0 takes}{\b0 to}{\b0 locate}{\b0
and}{\b0 read}{\b0 data}{\b0 from}{\b0 a}{\b0 RAM}{\b0 is}{\b0 called}{\b
0 the }
i593 {\b0 time. }
i954 {\b0 \fs17 The}{\b0 \fs17 time}{\b0 \fs17 it}{\b0 \fs17 takes}{\b0 \fs
17 to}{\b0 \fs17 locate}{\b0 \fs17 and}{\b0 \fs17 read}{\b0 \fs17 data}{\
b0 \fs17 from}{\b0 \fs17 a}{\fs17 RAM}{\b0 \fs17 is}{\b0 \fs17 called}{
\b0 \fs17 the}{\b0 \fs17 access}{\b0 \fs17 time. }\par
}
\cf0 12.17{\b0 The}{\b0 2114}{\fs19 IC}{\b0 shown}{\b0 in}{\b0 Fig.}{\b0
12-4}{\b0 is}{\b0 a }
}
(dynamic, static) RAM. \par
}
access, interface) \par
}
7 \cf0 The 2114{\fs17 IC} shown in Fig. 12-4 is{\b a} static{\b \fs17 RAM.
}
{\b \f30 \fs19 12-3}{\b \fs18 READ-ONLY}{\b \fs18 MEMORY}{\b \fs18 (ROM) }
366 {\fs18 Microcomputers}{\fs18 must}{\fs18 store}{\fs18 permanent}{\fs18
information}{\fs18 in}{\fs18 the}{\fs18 form}{\fs18 of}{\fs18 a}{\fs18
system}{\fs18 or}{\fs18 monitor}{\fs18 program, }
s18 typically}{\fs18 in}{\fs18 a}{\b\i \fs19 read-on2y}{\i \fs19 memory}{\b
\i \fs19 (ROM).}{\fs18 The}{\fs18 ROM}{\fs18 is}{\fs18 programmed}{\fs18 b
y}{\fs18 the}{\fs18 manufacturer}{\fs18 to}{\fs18 the}{\fs18 user's }

s18 specifications.}{\fs18 Smaller}{\fs19 ROMs}{\fs18 can}{\fs18 be}{\fs18
used}{\fs18 to}{\fs18 solve}{\fs18 combinational}{\fs18 logic}{\fs18 probl
ems}{\fs18 (to}{\fs18 implement}{\fs18 truth }
s18 tables). }\par
}
.{\fs17 121 }\par
}
}
f0 287 \par
}
\cf0 ROMs are classified as nonvolatile storage devices because they d
o not lose their data when
r is turned{\fs19 off.} The read-only memory{\fs18 is} also referred to
as the{\i mask-programmed}{\i \fs19 ROM.} The
\par}{\phpg\posx883\pvpg\posy1409\absw9236\absh2365 \sl-238 \f20 \fs18 \cf0 ROM
is used only in high-volume production applications because the initial s
et-up costs are high.
\par}{\phpg\posx883\pvpg\posy1409\absw9236\absh2365 \sl-242 \f20 \fs18 \cf0 Vari
eties{\fs19 of} programmable read-only memories (PROMS)might be used for low-v
olume applications.
61 Consider the problem of converting from decimal to Gray code (see Sec.{\i 23).} The truth table for
\par}{\phpg\posx883\pvpg\posy1409\absw9236\absh2365 \sl-238 \f20 \fs18 \cf0 this
problem is in Fig.{\i 12-7a.} This conversion could be made{\fs17 by}
using a simple diode ROM circuit
\par}{\phpg\posx883\pvpg\posy1409\absw9236\absh2365 \sl-242 \f20 \fs18 \cf0 such
as the one shown in Fig.{\i 12-76.} If the rotary switch has selected the deci
mal{\i 2} position, what will
ROM output indicators display? The outputs{\i \fs19 (}{\i \fs19 D}{\i \fs19 ,
}{\fs19 C,}{\i \fs19 B,}{\b\i A}{\b\i )}will indicate LLHH or{\i 0021.} The{
\i D} and
19 C} outputs are connected directly to ground through the resistor and read LOW
. The{\i \fs19 B} and{\b\i A} outputs
connected to{\i \fs19 +5} V through two forward-biased diodes, and the
output voltage will read about
6 {\i +2-3} V, which is a logical HIGH. \par
}
cf0 +5{\i0 \fs20 v }\par
}
put \par
}
cf0 97 \par
}
0 I'i, \par
}
I
\fi3007 {\f20 \fs15 t}{\f20 \fs15
Output }
\fi1193 {\fs14 1.5 }\par
}
tput \par
}
Output indicators,
328 {\fs14 Gray} code \par
}
8 \cf0 Note that the pattern of diodes in the diode ROM matrix (Fig.{\i 12-7
6)}is similar to the pattern{\fs18 of }
\par}{\phpg\posx875\pvpg\posy12411\absw9158\absh1499 \sl-237 \f20 \fs18 \cf0 1s
in the truth table (Fig.{\i 12-7a).} The circuit in Fig.{\i 12-7b}{\fs18 is}
considered a ROM that is permanently
grammed as a decimal-to-Gray code decoder. Each new position of the rotary s
witch will give the
\par}{\phpg\posx875\pvpg\posy12411\absw9158\absh1499 \sl-237 \f20 \fs18 \cf0 cor
rect Gray code output as defined in the truth table. In{\fs19 a} memory, s
uch as the one shown in Fig.
12-7,} each position{\fs18 of} the rotary switch is referred to as an{\i
address. }
352 {\b A} slight refinement in the diode ROM is shown in Fig.{\i 12-8.} Figur
e{\i 12-8a} is the truth table for a
\par}{\phpg\posx875\pvpg\posy12411\absw9158\absh1499 \sl-242 \f20 \fs18 \cf0 bin
ary-to-Gray
code converter. The diode ROM circuit shown in Fig.{\i
12-86} has an added 1-of-10 \par
}
\cf0 (a){\i0 \f20 \fs15 Truth}{\i0 \f20 \fs14 table }\par
}
20 \fs14 \cf0 (b){\i0 \fs15 Diode}{\i0 \fs15 ROM }
Decimal-to-Gray}{\i0 \fs1
6
code}{\i0 \fs16 conversion }\par
}
0 288 \par
}
CROCOMPUTERMEMORY \par
}
AP.{\b \fs16 12 }\par
}
\par
}
\cf0 1 8 s
f0 \fi218 {\b0 \fs16 0 }
fi218 {\b0 \fs15 0 }
fi218 {\b0 \fs15 0 }
fi218 {\b0 \fs15 0 }
fi222 {\b0 \fs15 0 }
fi218 {\b0 \fs15 0 }
fi218 {\b0 \fs15 0 }
fi218 {\b0 \fs15 0 }
fi235 {\b0 \fs15 1 }
fi235 {\b0 \fs15 1 }\par
}
cf0 Binary
0 {\fs16 4s}{\b0 \f10 \fs15
2s }\par
}
15 0 }
15 0 }
15 0 }
15 1 }
15 1 }
15 1 }
15 1 }
15 0 }
15 0 }\par
}
\sl-257 \f10 \fs16 \cf0 {\fs

\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-255 \f10 \fs16 \cf0 {\fs
\sl-251 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-254 \f10 \fs16 \cf0 {\fs
\fs16 \cf0 \f10 \fs16 \cf0 0

15 0 }
15 1 }
15 1 }
15 0 }
15 0 }
15 1 }
15 1 }
15 0 }
15 0 }\par
}
s
\fi20 {\fs16 0 }
4 1
4 1
5 0
5 1 \par
}
r
}
cf0 Gray{\fs17 code }\par
}
s16 \cf0 D
\cf0 {\b0\i0 \f10 \fs16 0 }
{\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
\fi22 {\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
\fi42 {\b0\i0 \f10 \fs15 1 }
\fi35 {\b0\i0 \f10 \fs15 1 }\par

}
16 \cf0 C{\fs16
B }\par
}
15 0 }
15 0 }
15 0 }
15 1 }
15 1 }
15 1 }
15 1 }
15 1 }
15 1 }\par
}
\sl-254 \f10 \fs16 \cf0 {\fs
15 0 }
15 1 }
15 1 }
15 1 }
15 1 }
15 0 }
15 0 }
15 0 }
15 0 }\par
}
s16 \cf0 A
\cf0 {\b0\i0 \f10 \fs16 0 }
\fi26 {\b0\i0 \f10 \fs15 1 }
\fi26 {\b0\i0 \f10 \fs15 1 }
{\b0\i0 \f10 \fs15 0 }
{\b0\i0 \f10 \fs15 0 }
\sl-254 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs

\sl-257 \f10 \fs16 \cf0 {\fs
\sl-251 \f10 \fs16 \cf0 {\fs
\sl-255 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-251 \f10 \fs16 \cf0 {\fs
\fs16 \cf0 \f10 \fs16 \cf0 0
\sl-257 \f10 \fs16 \cf0 {\fs

\sl-257 \f10 \fs16 \cf0 {\fs
\sl-251 \f10 \fs16 \cf0 {\fs
\sl-255 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-257 \f10 \fs16 \cf0 {\fs
\sl-251 \f10 \fs16 \cf0 {\fs
\f20 \fs16 \cf0 \b\i \f20 \f
\sl-200 \par\b\i \f20 \fs16
\sl-254 \b\i \f20 \fs16 \cf0
\sl-257 \b\i \f20 \fs16 \cf0
\sl-257 \b\i \f20 \fs16 \cf0
\sl-251 \b\i \f20 \fs16 \cf0
\sl-255 \b\i \f20 \fs16 \cf0
\fi26 {\b0\i0 \f10 \fs15 1 }

{\b0\i0 \f10 \fs15 1 }
{\b0\i0 \f10 \fs15 0 }
\fi20 {\b0\i0 \f10 \fs15 0 }
\fi31 {\b0\i0 \f10 \fs15 1 }\par
}
\cf0 (a) Truth table \par
}
cf0 +5{\i0 \fs22 v }\par
}
cf0 Input \par
}
cf0 1 \par
}
li- \par
}
cf0 0 \par
}
cf0 1 \par
}
{\b \fs14 4s} 2s \par
}
cf0 0 \par
}
It \par
}
15 \cf0 Output indicators,
3260 {\fs15 Gray} code
782 {\b\i \fs15 (b)} Diode{\b \fs15 ROM} decoder
{\b \fs16 Fig.}{\b \f30 \fs17 12-8}{\fs17 Binary-to-Gray}{\fs17
code}{\f
s17 conversion }\par
}
0 CHAP.{\fs17 121 }\par
}
cf0 MICROCOMPUTERMEMORY \par
}
f0 289 \par
}
\fs15 \cf0 NC
f0 {\fs15 A12 }
f0 \fi63 {\fs15 A7 }
f0 \fi71 A6
f0 \fi83 A5
f0 \fi71 {\fs15 A4 }
f0 \fi71 {\b0 A3 }
f0 \fi67 {\i \f30 \fs17 A2 }
f0 \fi56 {\fs15 A1 }
f0 \fi68 {\fs15 A0 }
f0 \fi62 {\fs15 Q1 }
f0 \fi72 {\fs15 Q2 }
f0 \fi72 {\fs15 Q3 }
f0 \fi27 {\b0 \fs16 vss }\par
}
\cf0 241{\b\i0 \f20 \fs15 A9 }
\par}{\phpg\posx6005\pvpg\posy2902\absw968\absh1298 \sl-371 \i \f10 \fs27 \cf0 2
31{\b\i0 \f20 \fs15 A}{\b\i0 \f20 \fs15 l}{\b\i0 \f20 \fs15 l }
\b \f20 \fs30 g}{\b\i0 \f20 \fs15
Sl/Sl }
\fs21 21(}{\b\i0 \f20 \fs15 A10 }\par
}
0 r \par
}
s16 \cf0 (a){\i0 \fs15 Pin}{\i0 \fs15 diagram} (Reprinted{\f10 \fs14 by} permi
ssion{\f30 \fs16 of}{\fs15 Texas} Instruments) \par
}
7:; \par
}
fs15 \cf0 ROM
KX8 \par
}
\fs14 \cf0 A4
\i \fs20 -4 }
f0 \fi81 {\f20 \fs15 A7 }

f0 \fi81 {\f20 \fs15 A9 }
fi86 {\f20 \fs15 A10 }
fi81 {\f20 \fs15 All }
fi81 {\f20 \fs15 A12 }
fi81 {\f20 \fs15 A}{\dn006 \f20 \fs10 13 }\par
}
\cf0 UMS47256) \par
}
\cf0 Chip enable/power down
\fi1021 Chip select \par
}
\f20 \fs15 \cf0 (b){\i0 \fs15 Logic}{\i0 \fs15 diagram }
\cf0 {\i0 \fs16 Fig.}{\i0 \f30 \fs17 12-9}{\i0 \fs17 TMS47256}{\i0 \fs17 32K
}{\b0\i0 \f10 \fs13 X}{\i0 \fs17 8}{\i0 \fs17 ROM }\par
}
\cf0 Address inputs \par
}
cf0 Q2
\par}{\phpg\posx6703\pvpg\posy7837\absw848\absh859 \sl-193 \b \f20 \fs15 \cf0 Q3
dn006 Q4}{\b0 \f10 \fs29 -}{\b0 \f10 \fs29 I }
i \f30 \fs16 Q5 }\par
}
{\phpg\posx7071\pvpg\posy8748\absw518\absh274 \f10 \fs23 \cf0 \f10 \fs23
\par
}
{\phpg\posx7071\pvpg\posy8868\absw614\absh597 \f10 \fs50 \cf0 \f10 \fs50
I \par
}
cf0 MSB \par
}
cf0 Q6
\cf0 {\
\cf0 {\
\cf0 \cf0 \fs15 \
\fs15 \
\cf0 Q7
\par}{\phpg\posx6699\pvpg\posy8975\absw285\absh697 \sl-294 \b \f20 \fs15 \cf0 Q8

\par
}
\cf0 f
{\fs31 1 }\par
}
cf0 Data{\fs11 Outputs }\par
}
\cf0 MSB \par
}
\cf0 inputs \par
}
s16 \cf0 E{\i0 \fs15 or}{\i0 \fs15 S2 }
\cf0 {\i0 \f10 \fs14 S1 }\par
}
\par
}
}
f0 [CHAP.{\b0 \f10 \fs16 12 }\par
}
\cf0 decoder (TTL 7442 IC) and inverters used to activate{\i \fs18 only}{\i \
fs19 one} ofthe{\i \f10 \fs17 10} rows in the diode ROM. The
21 example in Fig. 12-86 shows a binary input of 0101 (decimal{\i \fs19 5).
} This activates output{\i \fs19 5} of the 7442
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 wit
h a LOW; and that drives the inverter, which outputs a HIGH. The HIGH forward-bi
ases the three
21 diodes connected to the row{\i \fs19 5} line. The outputs will be{\fs19 L
HHH} or 0111. This is also specified in the
22 truth table.
380 The primitive diode ROMs have many disadvantages. Their logic levels ar
e marginal, and they
22 have very limited drive capability. They do not have the input and output b
uffering that is needed to
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 wor
k with systems that contain data and address busses.
372 Practical mask-programmable ROMs are available from many manufacturer
s. They can range
m very small units to quite large capacity ROMs. Some of these comme
rcial ROMs can be
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 pur
chased in familiar DIP form. ROMs are manufactured using{\fs19 TTL,} CMO
S, NMOS, PMOS, and
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-238 \f20 \fs18 \cf0 GaA
s (gallium arsenide) process technologies. The GaAs technology yields v
ery fast digital ICs.
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 Cur
rently ROMs using either NMOS or CMOS seem to be{\fs18 very} popular. A
s an example, one very
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-238 \f20 \fs18 \cf0 sma

ll unit is the Harris 82HM141C 512{\f10 \fs19 x}{\fs18 8} NMOS ROM wi
th an access time of under 70 ns. A
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-236 \f20 \fs18 \cf0 sim
ilar unit, the{\fs18 very} fast 14GM048 GaAs ROM is manufactured by Tri Quint S
emiconductor and has
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 acc
ess time{\fs18 of} less than 1.5 ns. One large unit is the Sharp LH5316000 2M{
\f10 \fs14 X}{\fs18 16} CMOS ROM, with an
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 acc
ess time{\fs18 of} less than 200 ns.
379 ROMs are used to hold permanent data and programs. Computer system
programs, look-up
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-239 \f20 \fs18 \cf0 tab
les, decoders, and character generators are but a few{\fs19 uses} of the ROM.
They can also be used for
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-236 \f20 \fs18 \cf0 sol
ving combinational logic problems. General-purpose microcomputers contain a larg
er proportion of
21 RAM for their internal memory. Dedicated computers allocate more addresses
to ROM and usually
tain only smaller amounts{\fs18 of} RAM. According to one recent list
ing, more than 300 different
mercial ROMs are available.
371 As an example, a{\fs17 pin} diagram of a commercial TMS47256 ROM is sho
wn in Fig. 12-9a. A logic
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-242 \f20 \fs18 \cf0 dia
gram for the ROM is illustrated in Fig. 12-9b. The TMS47256 is an NMOS 262 14
4-bit read-only
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-234 \f20 \fs18 \cf0 mem
ory organized as 32768 words of &bit length. From a practical point,
this is called a{\fs18 32K}{\f10 \fs14 X}{\fs18 8 }
21 ROM, or in most microprocessor-based systems this would be 32K of RO
M (32K bytes of ROM).
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 Whi
le a 28-pin DIP IC is pictured in Fig. 12-9a, the ROM is also available in a 32
-lead plastic leaded
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-230 \f20 \fs18 \cf0 chi
p carrier package designed for surface mount applications. The TMS47256{\fs19 i
s} compatible with most
s19 TTL} and CMOS logic devices. The access time for the TMS47256 ROM is less t
han 200 ns.
373 The TMS47256 ROM has 15 address inputs{\b\i \f10 \fs17 (Ao}to{\b\i \f10
\fs17 A,,),} which can address 32768{\b \f30 \fs20 (215)}words.
{\b\i \f10 \fs18 A,} input is the{\fs19 LSB} of the address, while{\b
\i \f10 \fs17 A,,} is the MSB. Pin 22 (see Fig. 12-9a) can be
grammed during mask fabrication by the manufacturer as either active-HI
GH or active-LOW
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-230 \f20 \fs18 \cf0 chi
p-select input. Pin{\fs18 20} can be programmed during mask fabrication{\fs18
to} be a chip-enabZe/power-down
ut{\b\i \fs19 (}{\b\i \fs19 E} or{\b\i \fs25 E}{\b\i \fs25 )} or a secondary
chip-select pin (S2 or{\fs25 E).}Each option can{\fs18 be} either activeLOW or
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-236 \f20 \fs18 \cf0 act
ive-HIGH. When the chip-enable/power-down pin is inactive, the chip is put{\fs
18 in} the standby mode.
standby mode reduces the power consumption.
371 The eight outputs{\i \fs18 (Q,} to{\i\dn006 \fs12
Q8)} are in the three
-state high-impedance state when disabled. To read
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-233 \f20 \fs18 \cf0 dat
a from a given address, both the chip select (pin 22) and the chip-en
able/power-down (pin 20)
trol inputs must be enabled. When both controls are enabled, the 8-bit output wo
rd{\fs19 from} a given
ress can be read from the outputs. Output Q, is considered the LSB{\f10 \fs20 ,
}while{\i\dn006 \fs11
Q8} is the MSB.{\b A}{\fs19 5-V }
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-247 \f20 \fs18 \cf0 dc
power supply is used with{\i \fs19
+5}{\b V} connected to the{\i \f
s18 Vcc} (pin 28) and the negative (ground)
nected to{\i \fs18 Vss} (pin 14).
363 A computer program is typically referred to as software. When a co
mputer program is stored
\par}{\phpg\posx851\pvpg\posy1376\absw9189\absh10238 \sl-237 \f20 \fs18 \cf0 per
manently in a ROM, it is commonly called firmware because{\fs18 of} the diff
iculty of making changes in
code.
}
\cf0 12.18{\b0 \fs18 A }
}
8 \cf0 (RAM, ROM) is classified as a nonvolatile storage device.
{\b \fs16 A}{\fs17 ROM}{\fs16 is}{\fs16 classified}{\fs16 as}{\fs16 a}
{\fs16 nonvolatile}{\fs16 storage}{\fs16 device}{\fs16 because}{\fs16 i
t}{\fs16 does}{\fs16 not}{\fs16 lose}{\fs16 its}{\fs16 data}{\fs16 when}
{\fs16 power}{\fs16 is }\par
}
urned{\fs17 off. }\par
}
. 121 \par
}

}
\par
}
cf0 12.19{\fs19 A- }
}
\cf0 (RAM,{\fs19 ROM)}{\fs19 is}{\fs19 programmed}{\fs19 by}{\fs19 the}{\
fs19 computer}{\fs19 operator. }
{\b \fs17 A}{\b \f30 \fs19 RAM}{\b \fs17 is}{\fs17 programmed}{\fs17 by}{\
fs17 the}{\fs17 computer}{\fs17 operator. }\par
}
\cf0 12.20{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 12-86.}
{\b0 \fs19 What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 function}{\b0 \fs19
of}{\b0 \fs19 the}{\b0 \fs19 diode}{\b0 \fs19 ROM? }
fi943 {\b0 \fs17 The}{\b0 \fs17 function}{\b0 \fs17 of}{\b0 \fs17 the}{\b0
\fs17 ROM}{\b0 \fs17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 12
-86}{\b0 \fs17 is}{\b0 \fs17 as}{\b0 \fs17 a}{\b0 \fs17 simple}{\b0 \fs17
binary-to-Gray}{\b0 \fs17
code}{\b0 \fs17 converter. }
f0 12.21{\b0 \fs19 Refer}{\b0 \fs19 to}{\b0 \fs19 Fig.}{\b0 \fs19 12-86.}
{\b0 \fs19 List}{\b0 \fs19 the}{\b0 \fs19 state}{\b0 \fs19 of}{\b0 \fs19 th
e}{\b0 \fs19 output}{\b0 \fs19 for}{\b0 \fs19 each}{\b0 \fs19 binary}{\b0 \f
s19 input}{\b0 \fs19 from}{\b0 \fs19 0000}{\b0 \fs19 to}{\b0 \fs19 1001. }
fi949 {\b0 \fs17 See}{\b0 \fs17 the}{\b0 \fs17 Gray}{\b0 \fs17 code}{\b0 \fs
17 output}{\b0 \fs17 for}{\b0 \fs17 each}{\b0 \fs17 binary}{\b0 \fs17 c
ount}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 12-8a. }
f0 12.22{\b0 \fs19
\b0 \fs19 When}{\b0 \fs19 the}{\b0 \fs19 binary}{\b0 \fs19 input}{\b0 \fs19
is}{\b0 \fs19 0001,}{\b0 \fs19 output}{\b0 \fs19 1}{\b0 \fs19 is}{\b0 \fs1
9 activated}{\b0 \fs19 and}{\b0 \fs19 the}{\b0 \fs19 output}{\b0 \fs19 of}{
\b0 \fs19 its }\par
}
nverter goes
i \f10 \fs18 (}{\b\i \f10 \fs18 A}{\b\i \f10 \fs18 ,}{\b\i B,}{\b\i \fs19 C,}{
\i \f10 \fs17 0)}column.
}
HIGH,{\fs19
LOW),}{\fs19
thereby}{\fs19
forward-biasing}{\fs19 a}{\fs
19
diode}{\fs19
in}{\fs19
the }\par
}
\cf0 Binary 0001 activates output 1, Fig. 12-86. This causes the inv
erter output to{\fs16 go} HIGH, which

52 forward-biases the single diode in the{\b\i \fs17 A} column. The ROM
output reads 0001.
{\b \fs18 12.23}{\fs19 Refer}{\fs19 to}{\fs19 Fig.}{\fs19 12-10.}{\fs19 Li
st}{\fs19 the}{\fs19 state}{\fs19 of}{\fs19 the}{\fs19 ROM}{\fs19 outputs}
{\fs19 during}{\fs19 each}{\fs19 pulse. }
43 The ROM outputs during each pulse are as follows: \par
}
ulse a{\f10 \fs13 =}{\fs17 0011} (address{\dn006 \f10 \fs11 =}{\fs16 0) }
e{\i b}{\f10 \fs13 =} 0110 (address{\f10 \fs13 =} 3)
e{\b\i \fs16 c}{\f10 \fs13 =} 1100 (address{\f10 \fs13 =}{\fs16 9) }
e{\b\i \fs17 d}{\f10 \fs14 =} 1010(address{\f10 \fs13 =} 7) \par
}
ulse{\b\i \fs16 e}{\f10 \fs13 =} 1001 (address{\f10 \fs13 =}{\b 6) }
ef{\f10 \fs11
=} 0100 (address{\dn006 \f10 \fs11 =}{\fs17 1) }
e{\fs15 g}{\f10 \fs13 =} 1011 (address{\f10 \fs13 =} 8) \par
}
ulse{\b\i h}{\f10 \fs13 =} 0101 (address{\f10 \fs13 =} 2)
e{\b\i \f30 \fs18 i}{\dn006 \f10 \fs11 =} 0111 (address{\f10 \fs14 =} 4)
e{\i \f10 \fs15 j}{\f10 \fs13 =} 1000 (address{\f10 \fs13 =}{\b\i \f10 \fs1
6 5}{\b\i \f10 \fs16 ) }\par
}
cf0 12.24{\b0 \fs19 The}{\b0 \fs19 TMS47256}{\b0 \fs19 RAM}{\b0 \fs19 shown
}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 12-9can}{\b0 \fs19 address }
i577 {\b0 \fs19 wide. }
}
ords. Each word is \par
}
{\phpg\posx9381\pvpg\posy8982\absw414\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 -b
its \par
}
he TMS47256{\b \f30 \fs19 RAM} can address 32768 (32K) words each 8-bits
wide. \par
}
\cf0 12.25{\b0 \fs19
The}{\b0 \fs19 TMS47256}{\fs19 IC}{\b0 \fs19 is}{\b0
\fs19 a }
}
(field, mask)-programmable read-only memory. \par
}
7 \cf0 The TMS47256 IC is a mask-programmable ROM which is programmed by t
he manufacturer to the
\par}{\phpg\posx1481\pvpg\posy11041\absw8244\absh387 \sl-215 \f20 \fs17 \cf0 use
r's specifications. \par
}
\cf0 12.26{\b0 \fs19 The}{\b0 \fs19 TMS47256}{\b0 \fs19 ROM}{\b0 \fs19 has
}
fi587 {\b0 \fs19 bytes}{\b0 \fs19 of}{\b0 \fs19 memory. }
}
(number) address lines which can address \par
}
\cf0 (16,{\b0 \fs19 32)K }\par
}
7 \cf0 See Fig. 12-9b. The TMS47256 ROM has 15 address lines{\b\i \fs17 (}{
\b\i \fs17 A}{\b\i \fs17 o}to{\b \fs17 A14)}which{\b can} address{\b \fs17
32K} bytes
\par}{\phpg\posx1481\pvpg\posy12684\absw8255\absh399 \sl-221 \f20 \fs17 \cf0 of
memory. \par
}
\cf0 12.27{\b0 \fs19 With}{\b0 \fs19 the}{\b0 \fs19 chip-enable/power-down}{
\b0 \fs19 pin}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19 TMS47256}{\b0 \fs19
ROM }
fi589 {\b0 \fs19 chip}{\b0 \fs19 goes}{\b0 \fs19 into}{\b0 \fs19 the}{\b0 \fs
19 standby}{\b0 \fs19 mode,}{\b0 \fs19 which}{\b0 \fs19 reduces}{\b0 \fs19
power}{\b0 \fs19 consumption. }\par
}
(disabled, enabled), the \par
}
16 \cf0 +5{\i0 \f20 \fs22 v }\par
}
cf0 Binary
fs15 inputs }\par
}
cf0 7 \par
}
cf0 0
0 {\b\i0 \fs14 1 }\par
}
cf0 0
0 \fi24 {\i0 \fs14 1 }\par
}
cf0 0 \par
}
\par
}
cf0 0 \par
}
1 \par
}
cf0 g \par
}
cf0 I
8 1 }\par
}
\par}{\phpg\posx4372\pvpg\posy2517\absw124\absh548 \sl-210 \par\f10 \fs14 \cf0 1
\par
}
\par
}
\cf0 \par}{\phpg\posx4838\pvpg\posy2000\absw451\absh1053 \sl-393 \par\f20 \fs30 \cf0
{\f10 \fs30 1 }\par
}
\par
}
\par
}
cf0 1
\i \fs14 0 }
\i \fs15 b }\par
}
\par
}
\par
}
cf0 ' \par
}

f0 -+ \par
}
\par
}
cf0 f \par
}
f0 j \par
}
cf0 0
\par}{\phpg\posx2198\pvpg\posy3219\absw110\absh358 \sl-201 \i \f10 \fs15 \cf0 i
\par
}
cf0 h \par
}
cf0 0
fs13 e }\par
}
cf0 d \par
}
fs14 \cf0 1
b0\i \fs15 n }\par
}
\par
}
4 {\f20 \fs15 1 }\par
}
cf0 o \par
}
\cf0 Fig.{\f10 \fs16 12-10}{\fs17
ROM}{\fs16 pulse-train}{\fs16 problem }\
par
}
cf0 292 \par
}
.{\fs17 121 }\par
}
}
\par
}
\cf0 Solution:
fi360 {\b0 \fs16 With}{\b0 \fs16 the}{\b0 \fs16 chip-enable/power-down}{\b0
\fs16
input}{\b0 \fs16 (pin}{\b0 20)}{\b0 \fs16 disabled,}{\b0 \fs16
the}{\b0 \fs16 chip}{\b0 \fs16 goes}{\b0 \fs16 into}{\b0 \fs16 the}{\b0
\fs16 standby}{\b0 \fs16 mode, }
\b0 \fs16 which}{\b0 \fs16 reduces}{\b0 \fs16 power}{\b0 \fs16 consumption.
}\par
}
\cf0 12.28{\b0 Refer}{\b0 to}{\b0 \fs18 Fig.}{\b0 12-9.}{\b0 Which}{\b0
two}{\b0 control}{\b0 inputs}{\b0 to}{\b0 the}{\b0 TMS47256}{\b0 R
OM}{\b0 must}{\b0 be}{\b0 enabled}{\b0 for }
fi592 {\b0 stored}{\b0 data}{\b0 to}{\b0 be}{\b0 read}{\b0 from}{\b0 the}
{\b0 outputs? }
fi950 {\b0 \fs16 Both}{\b0 \fs16 the}{\b0 \fs16 chip-select}{\b0 \fs16 (pin
}{\b0 \fs17 22)}{\b0 \fs16 and}{\b0 \fs16 chip-enable/power-down}{\b0 \fs1
6
(pin}{\b0 \fs17 20)}{\b0 \fs16 control}{\b0 \fs16 inputs}{\b0 \fs16
must}{\b0 \fs16 be}{\b0 \fs16 enabled }
fi591 {\b0 \fs16 for}{\b0 \fs16 stored}{\b0 \fs16 date}{\b0 \fs16 to}{\b0 \
fs16 be}{\b0 \fs16 read}{\b0 \fs16 from}{\b0 \fs16 the}{\b0 \fs16 outp
uts. }\par
}
\cf0 12-4 PROGRAMMABLEREAD-ONLY MEMORY
fi368 {\b0 Mask-programmable}{\b0 ROMs}{\b0 are}{\b0 programmed}{\b0 by}{\b0
the}{\b0 manufacturer}{\b0 by}{\b0 using}{\b0 photographic}{\b0 masks}{\b
0 to }
\b0 expose}{\b0 the}{\b0 silicon}{\b0 die.}{\b0\i \fs19 Mask-programmable}{\
b0\i ROMs}{\b0 have}{\b0 long}{\b0 development}{\b0 times,}{\b0 and}{\b0
their}{\b0 initial}{\b0 costs }
\b0 are}{\b0 high.}{\b0 They}{\b0 are}{\b0 usually}{\b0 referred}{\b0 to}
{\b0 simply}{\b0 as}{\b0 ROMs. }
fi362 {\b0 Field}{\b0\i \fs19 programmable}{\b0\i \fs19 ROMs}{\b0\i \fs19
(PROMS)}{\b0 also}{\b0 are}{\b0 available.}{\b0 They}{\b0 shorten}{\b0
development}{\b0 time}{\b0 and }
\b0 lower}{\b0 costs.}{\b0 It}{\b0 is}{\b0 also}{\b0 much}{\b0 easier}{\b0
to}{\b0 correct}{\b0 program}{\b0 errors}{\b0 and}{\b0 update}{\b0 produ
cts}{\b0 when}{\b0 PROMs}{\b0 can}{\b0 be }
\b0 programmed}{\b0 (burned)}{\b0 by}{\b0 the}{\b0 local}{\b0 developer.}{\
b0 The}{\b0 regular}{\b0 PROM}{\b0 can}{\b0 be}{\b0 programmed}{\b0 only}
{\b0 once}{\b0 like}{\b0 a }
\b0 ROM,}{\b0 but}{\b0 its}{\b0 advantage}{\b0 is}{\b0 that}{\b0 it}{\b
0 can}{\b0 be}{\b0 made}{\b0 in}{\b0 limited}{\b0 quantities}{\b0 and
}{\b0 can}{\b0 be}{\b0 programmed}{\b0 in}{\b0 the }

\b0 local}{\b0 lab}{\b0 or}{\b0 shop. }
fi360 {\fs19 A}{\b0 variation}{\b0 \fs19 of}{\b0 the}{\b0 PROM}{\b0 is
}{\b0 an}{\b0\i \fs19 erasable}{\b0\i \fs19 PROM}{\b0\i \fs19 (EPROM).}{
\b0 The}{\b0 EPROM}{\b0 is}{\b0 programmed}{\b0 or }
\b0 burned}{\b0 at}{\b0 the}{\b0 local}{\b0 level}{\b0 by}{\b0 using}{\b0
a}{\b0\i \fs19 PROM}{\b0\i \fs19 burner.}{\b0 \fs19 If}{\b0 the}{\b0 EPRO
M}{\b0 must}{\b0 be}{\b0 reused}{\b0 or}{\b0 reprogrammed,}{\b0 a }
\b0 special}{\b0 quartz}{\b0 window}{\b0 on}{\b0 the}{\b0 top}{\b0 of}{\b0
the}{\b0 IC}{\b0 is}{\b0 used.}{\b0 Ultraviolet}{\b0 (UV)}{\b0 light}{\b
0 is}{\b0 directed}{\b0 at}{\b0 the}{\b0 EPROM }
\b0 chip}{\b0 under}{\b0 the}{\b0 window}{\b0 for}{\b0 about}{\b0 an}{\b0
hour.}{\b0 The}{\b0 UV}{\b0 light}{\b0 erases}{\b0 the}{\b0 EPROM}{\b0 b
y}{\b0 setting}{\b0 all}{\b0 the}{\b0 memory }
\b0 cells}{\b0 to}{\b0 a}{\b0 logical}{\b0 1.}{\b0 The}{\b0 EPROM}{\b0 can
}{\b0 then}{\b0 be}{\b0 reprogrammed.}{\b0 Figure}{\b0 12-11}{\b0 illustr
ates}{\b0 a}{\b0 typical}{\b0 24-pin }
\b0 EPROM}{\b0 DIP}{\b0 IC.}{\b0 Note}{\b0 the}{\b0 rectangular}{\b0 EPROM
}{\b0 chip}{\b0 visible}{\b0 through}{\b0 the}{\b0 quartz}{\b0 window}{\b0
on}{\b0 top}{\b0 of}{\b0 the }
\b0 IC.}{\b0 These}{\b0 units}{\b0 may}{\b0 sometimes}{\b0 be}{\b0 called}
{\b0\i \fs19 UV-erasable}{\b0\i \fs19 PROMs. }\par
}
20 \fs16 \cf0 Fig. 12-11{\b0 \fs17
UV}{\b0 \fs16 erasable}{\b0 \fs17 PROM }
cf0 \fi360 {\fs18 A}{\b0 \fs18 third}{\b0 \fs18 variation}{\b0 \fs18 of}{\b0
\fs18 the}{\b0 \fs18 PROM}{\b0 \fs18 is}{\b0 \fs18 an}{\b0\i \fs19 electri
cally}{\b0\i \fs19 erasable}{\b0\i \fs19 PROM,}{\b0 \fs18 also}{\b0 \fs18 r
eferred}{\b0 \fs18 to}{\b0 \fs18 as}{\b0 \fs18 an}{\b0 \fs18 EEPROM }
{\b0 \fs18 or}{\b0 \fs18 E2PROM.}{\b0 \fs18 Because}{\b0 \fs18 an}{\b0 \fs18
EEPROM}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 erased}{\b0 \fs18 electrical
ly,}{\b0 \fs18 it}{\b0 \fs18 is}{\b0 \fs18 possible}{\b0 \fs18 to}{\b0 \fs18
erase}{\b0 \fs18 and}{\b0 \fs18 reprogram}{\b0 \fs18 it }
{\b0 \fs18 while}{\b0 \fs18 it}{\b0 \fs18 remains}{\b0 \fs18 on}{\b0 \fs18 t
he}{\b0 \fs18 circuit}{\b0 \fs18 board.}{\b0 \fs18 This}{\b0 \fs18 is}{\b0 \
fs18 not}{\b0 \fs18 possible}{\b0 \fs18 with}{\b0 \fs18 the}{\b0 \fs18 PROM
}{\b0 \fs18 or}{\b0 \fs18 the}{\b0 \fs18 UV-erasable}{\b0 \fs18 PROM. }
{\b0 \fs18 The}{\b0 \fs18 EEPROM}{\b0 \fs18 can}{\b0 \fs18 also}{\b0 \fs18 r
eprogram}{\b0 \fs18 parts}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 code}{\b0
\fs18 on}{\b0 \fs18 the}{\b0 \fs18 chip}{\b0 \fs18 1}{\b0 \fs18 byte}{\b0 \
fs18 at}{\b0 \fs18 a}{\b0 \fs18 time. }
\fi364 {\fs18 A}{\b0 \fs18 fourth}{\b0 \fs18 variation}{\b0 \fs18 of}{\b0 \f
s18 the}{\b0 \fs18 PROM}{\b0 \fs18 is}{\b0 \fs18 the}{\b0\i \fs19 flash}
{\b0\i \fs19 EPROM.}{\b0 \fs18 The}{\b0 \fs18 flash}{\b0 \fs18 EPROM}{\b0 \
fs18 is}{\b0 \fs18 very}{\b0 \fs18 similar}{\b0 \fs18 to}{\b0 \fs18 the
}
{\b0 \fs18 EEPROM}{\b0 \fs18 in}{\b0 \fs18 that}{\b0 \fs18 it}{\b0 \fs18 can
}{\b0 \fs18 be}{\b0 \fs18 reprogrammed}{\b0 \fs18 while}{\b0 \fs18 on}{\b0 \

fs18 the}{\b0 \fs18 circuit}{\b0 \fs18 board.}{\b0 \fs18 The}{\b0 \fs18 fla
sh}{\b0 \fs18 EPROM}{\b0 \fs18 is}{\b0 \fs18 different }\par
}
0 294 \par
}
}
}
ood{\fs15 fuse} means
\par}{\phpg\posx5801\pvpg\posy1447\absw1207\absh336 \sl-179 \f20 \fs15 \cf0 stor
ed logical{\fs15 1 }\par
}
nary
\par
}
7 {\fs32 *' }\par
}
\cf0 -0
7 {\fs15 1-of-4 }
7 row
\par}{\phpg\posx3755\pvpg\posy2424\absw599\absh760 \sl-190 \f20 \fs15 \cf0 decod
er \par
}
cf0 2 \par
}
cf0 3 \par
}
a){\fs15 Before}{\fs15 programming}{\fs15 (all}{\fs15 logical}{\b Is) }\p
ar
}
lown fuse means
ed logical{\fs16 0 }\par
}
nary
5 input }\par
}
.{\dn006 \f20 \fs15
1-of-4 }\par
}
\par
}
\cf0 row
\par}{\phpg\posx3995\pvpg\posy8738\absw568\absh330 \sl-177 \f20 \fs15 \cf0 decod
er \par
}
\cf0 (6){\b0 After}{\b0 programming}{\b0 (selected}{\b0 addresses}{\b0 c
hanged}{\f10 \fs12 to}{\i OS) }
cf0 \fi1037 {\b0 \fs16 Fig.}{\f10 \fs15 12-12}{\fs17
Diode}{\b0 \fs17 PROM
}\par
}
.{\fs17 121 }\par
}
}
\par
}
rom the EEPROM in that the entire chip is erased and then reprogrammed. The a
dvantages of the
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-237 \f20 \fs18 \cf0 flas
h EPROM over the older EEPROM is it has a simpler storage unit{\fs18 so} more b
its can be stored on a
le chip.{\i \fs19 Also} flash EPROMs can be erased and reprogrammed much faste
r than EEPROMs. The
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-237 \f20 \fs18 \cf0 disa
dvantages of the flash EPROM are that 12 or 12.75{\fs18 V} are required for
reprogramming and that{\fs18 a }
le byte cannot{\fs17 be} reprogrammed as on an EEPROM.
61 The basic idea of a programmable{\fs19 ROM} (PROM) is illustrated{\fs1
8 in} Fig. 12-12a. This is a simple
1 16-bit (4{\f10 \fs19 x} 4) PROM. It is similar to the diode ROM studied in
the preceding section. Note that each
he memory cells contains a diode and a good fuse. That means that each of
the memory cells in
12-12a contains a logical 1, which is how the PROM might{\fs18 look} befor
eprogramming.
62 The PROM shown in Fig. 12-12b has been programmed with seven{\fs18 OS.}
To program or burn the
\fs19 PROM,} tiny fuses must be blown as shown{\fs18 in} Fig. 12-12b. A blo
wn fuse in this case disconnects the
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-239 \f20 \fs18 \cf0 diod
e and means that a logical{\fs18 0} is permanently stored in the memory cell. B

ecause of the permanent
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-234 \f20 \fs18 \cf0 natu
re of burning a PROM, the unit cannot be reprogrammed.{\b \f10 \fs18 A}
PROM of the type shown in Fig.
4 12-12 can{\fs18 be} programmed only once.
61 A popular EPROM family is the 27XX series. It is available from many m
anufacturers such as
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-232 \f20 \fs18 \cf0 Inte
l and Advanced Micro Devices.{\b \f10 \fs18 A} short summary of some models in
the 27XX series is shown{\fs19 in }
12-13. Note that all models are organized with byte-wide (8-bit-wide) output
s. Many versions{\fs18 of }
of these basic numbers are available. Examples are low-power CMOS un
its, EPROMs with
\par}{\phpg\posx845\pvpg\posy1365\absw9183\absh4054 \sl-233 \f20 \fs18 \cf0 diff
erent access times, and even pin-compatible PROMS, EEPKOMs, and ROMs. \par
}
PROM
23 {\fs16 27XX }
\fi116 {\fs16 2708 }
22 {\fs16 2716 }
16 {\fs16 2732 }
22 {\fs16 2764 }
16 {\fs16 27128 }
22 {\fs16 27256 }
16 {\fs16 27512 }\par
}
rganization
\fi194 1 024{\i \f10 \fs14 x} 8
74 2 048{\i \f10 \fs14 x} 8
72 4 096{\i \f10 \fs14 x} 8
74 8 192{\i \f10 \fs14 x} 8
13 16384{\i \f10 \fs14 x} 8
00 32 768{\i \f10 \fs14 x} 8
00 65 536{\i \f10 \fs14 x} 8 \par
}
Number{\fs16 of} bits

\fi496 8 192
407 16384
394 32 768
388 65 536
316 {\b \f10 \fs15 131} 072
302 262 144
307 524 288 \par
}
\cf0 Fig.{\f10 \fs15 12-13}{\b0 \fs16
Selected}{\b0 \fs16 members}{\b0 \fs
17 of}{\b0 \fs16 the}{\b0 \fs16 277XX}{\b0 \fs16 series}{\b0 \fs17 EPROM}
{\b0 \fs16 family }\par
}
\cf0 A sample{\b \fs19 IC} from the 27XX series EPROM family is shown in Fig.
12-14.The pin diagram in Fig.
0 12-14a is for the{\i \fs19 2732.4}{\i \fs19 32K}{\b\i (4K}{\f10 \fs14 X}{
\fs18 8)} Ultrauiolet Erasable{\b\i \fs19 PROM.} The 2732A EPROM has 12 addres
s
\par}{\phpg\posx847\pvpg\posy9889\absw9290\absh1544 \sl-242 \f20 \fs18 \cf0 pins
{\b\i \fs19 (}{\b\i \fs19 A}{\b\i \fs19 ,}{\b \fs19 --All)}which can access
the 4096 (212)byte-wide words in the memory. The 2732A EPROM
916 {\f30 \fs36 (a) }
\par}{\phpg\posx847\pvpg\posy9889\absw9290\absh1544 \sl-475 \f20 \fs18 \cf0 writ
ing. Under normal use the EPROM is being read.{\b \f10 \fs17 A} LOW at the outp
ut enable{\i \fs35 (m) }\par
}
ses a{\fs19 5-V} power supply and can be erased by using ultraviolet{\fs18 (UV
)} light. The chip enable \par
}
\cf0 (m) \par
}
nput \par
}
s like the chip select
inputs seen on other memory chips.{\fs18 It} is
activated with{\fs18 a} LOW. \par
}
8 \cf0 The{\b\i ?%!?/Vpfi,}pin serves a dual purpose; it has one purpose
during reading and another during
7786 pin during a
\par}{\phpg\posx851\pvpg\posy11089\absw9065\absh2356 \sl-242 \f20 \fs18 \cf0 mem
ory read activates the three-state output buffers driving the data bus of the co
mputer system. The
\par}{\phpg\posx851\pvpg\posy11089\absw9065\absh2356 \sl-229 \f20 \fs18 \cf0 eig
ht output pins on the 2732 EPROM are labeled{\i \fs18 0,}{\f10 \fs15 -}{\i \f
s18 0,.} The block diagram in Fig. 12-14b shows

organization of the 2732A EPROM{\fs18 IC. }
356 When the 2732A EPROM is erased, all memory cells are returned to logical 1.
Data is introduced
\par}{\phpg\posx851\pvpg\posy11089\absw9065\absh2356 \sl-234 \f20 \fs18 \cf0 by
changing selected memory cells to 0s. The 2732A is in the programmin
g mode (writing into
\par}{\phpg\posx851\pvpg\posy11089\absw9065\absh2356 \sl-319 \f20 \fs18 \cf0 EPR
OM) when the dual-purpose{\fs35 m/V,,} input is at 21{\b \fs18 V.} During prog
ramming (writing), the input
a is applied to the data output pins{\fs18 (0,}{\f10 \fs19 -}{\fs18 0,).}The
word to be programmed into the EPROM is
ressed{\b \fs17 by} using the 12 address lines. A very short (less than{\i \f
s19 55} ms) TTL level LOW pulse is then
\par}{\phpg\posx851\pvpg\posy11089\absw9065\absh2356 \sl-245 \f20 \fs18 \cf0 app
lied to the{\f10 \fs23 @} input. \par
}
0 296 \par
}
}
f0 [CHAP. 12 \par
}
cf0 A 7 C{\b\i0 \f10 \fs14 1 }
0 {\b \fs11 A}{\b \fs11
6}{\b \fs11
C}{\b\i0 \fs15
2 }\par
}
15 \cf0 A S C \par
}
\par
}
24{\i \f20 \fs17 I}{\i \f20 \fs17 V}{\i \f20 \fs17 c}{\i \f20 \fs17 c }
\b\i \f20 \fs15 3}{\b\i \f20 \fs15 A}{\b\i \f20 \fs15 s }
\par}{\phpg\posx3129\pvpg\posy1510\absw1322\absh2168 \sl-296 \f10 \fs14 \cf0 {\d
n006 22}{\b\i \f30 \fs20 3}{\b \f20 \fs15 A, }
\b \fs10 2}{\b \fs10
4}{\b \fs10
1 }
20}{\b\i \f30 \fs20 3}{\i \fs18 OEf}{\b\i \f30 \fs23 vpp }
\fi23 {\b\i \fs10 1}{\b\i \fs10 9}{\b\i \fs10 3}{\b\i \fs10 A}{\b\i \fs10
I}{\b\i \fs10 0 }
497 {\fs15 - }
23 {\b \fs14 18}{\b\i \f20 \fs15 2}{\b\i \f20 \fs15 C}{\b\i \f20 \fs15 E }

{\fs14 17}{\i \f20 \fs15 2}{\i \f20 \fs15 0}{\i \f20 \fs15 , }
{\fs14 16}{\i \f20 \fs15 3}{\i \f20 \fs15 0}{\i \f20 \fs15 , }\par
}
cf0 A 4 C{\b0 \f10 \fs14 4 }\par
}
14 \cf0 A 3 C \par
}
14 \cf0 5 \par
}
}
{\phpg\posx7283\pvpg\posy2532\absw443\absh1337 \f10 \fs83 \cf0 \f10 \fs83 \cf0 \par}{\phpg\posx7283\pvpg\posy2532\absw443\absh1337 \sl-836 \f10 \fs83 \cf0 - \p
ar
}
\par
}
3{\f10 \fs57
1 }\par
}
cf0 decoder \par
}
s57 1 }\par
}
I \par
}
\fs18 \cf0 vcc{\b \f30 \fs9 o-----.) }
\i0 \fs15 GND}{\b\i0 \f10 \fs10 0-w }\par
}
\fs15 \cf0 Data outputs
fi443 {\f30 \fs17 OQ}{\b0 \f10 \fs10 -07 }
\b0\i \f30 \fs19 c----A--7 }\par
}
14 \cf0 A 2 C{\f20 \fs15 6 }
{\b0\i0 \f20 \fs15 A}{\b0\i0 \f20 \fs15 l}{\b0\i0 \f20 \fs15 C}{\b0\i0 \fs14
7 }
{\b0 \f20 \fs17 A}{\b0 \f20 \fs17 o}{\b0 \f20 \fs17 C}{\i0 \fs14 8 }
\fi36 {\b0\i0 \fs20 ooc}{\b0\dn006 \fs14 9 }\par
}
}
32A \par
}
19 \cf0 OEl{\fs22 vpp }\par
}
cf0 Program \par
}
\cf0 -{\b \f20 \fs15
OE}{\b \f20 \fs15 and }
\f20 \fs15 CE}{\b \f20 \fs15
CElogic }\par
}
I \par
}
\cf0 Output buffers \par
}
ND
\fi130 {\b \fs17 Pin}{\b \fs17 Names }\par
}
cf0 Ao-All
i22 address
i60 inputs \par
}
\par
}
\fs16 \cf0 Y
fs15 decoder }
0 \fi220 {\i \fs15 X }\par
}
\fs15 \cf0 Y-gating
0 {\fs15 32} 768-bit
\par}{\phpg\posx8063\pvpg\posy4263\absw855\absh813 \sl-180 \b \f20 \fs15 \cf0 ce
ll matrix \par
}
I \par
}
cf0 Chip{\b0 \fs17 enable }\par
}
s13 \cf0 (a){\i0 \f20 \fs15 Pin}{\i0 \f20 \fs15 diagram }\par
}
s15 \cf0 (h){\i0 \fs15 Block}{\i0 diagram }\par
}
\cf0 Fig.{\fs17 12-14}{\fs17 The}{\fs17 2732A}{\fs17 32K}{\fs17 UV}{\fs17
erasable}{\fs17 PROM}{\b0\i \fs17 (Courtesy}{\b0\i \fs17 of}{\b0\i \fs17 Int
el}{\b0\i \fs17 Corporation) }\par
}
\cf0 EPROM erasing and programming is handled by special equipment called PROM
burners. After
\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-234 \f20 \fs18 \cf0 eras
ing and reprogramming, it is common to cover the EPROM window (see Fig. 1
2-11) with an
\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-233 \f20 \fs18 \cf0 opaq
ue sticker. The sticker protects the chip from UV light from fluorescent lights
and sunlight. The
\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-243 \f20 \fs18 \cf0 EPRO
M can be erased by direct sunlight in about one week or room level flu
orescent lighting{\fs18 in }
\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-238 \f20 \fs18 \cf0 abou
t three years.
86 One of the disadvantages of the typical RAM is that it is volatile. When po
wer is turned{\fs18 off,} all
6 data is lost.{\fs19 To} solve this problem, nonvolatile static RAM
s have been developed. Currently
1 nonvolatile read/write memories are implemented by{\fs18 (1)} using a CMO
S SRAM with battery backup
1 or (2) using a newer semiconductor NVSRAM (nonvolatile static{\fs19 RAM). }
82 Static{\fs19 RAMs} have both read and write capabilities but are volatile me
mories. One straightforward
2 solution to the volatility problem is to furnish a{\i \fs18 battery}{\i \fs18
backup} for the S U M . CMOS RAMs are used
battery backup because they consume little power. A long-life battery (such as
a lithium battery)
2 {\b \fs19 is} used to back up data on the normally volatile CMOS SRAM when th
e power fails. During normal
0 operation the regular dc power supply provides power for the SRAM. When
power is turned off, a
2 special circuit senses the drop in voltage and switches the SRAM to its standb
y battery power. Backup
\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-240 \f20 \fs18 \cf0 batt
eries have life expectancies of about{\fs18 10} years.
74 {\b A} newer product called a{\i \fs18 nonvolatile}{\i RAM} has be
come available. The nonvolatile RAM is
0 commonly referred to as a{\i NVRAM,}{\i NOKUAM,} or{\i NVSRAM.} The NVRAM
has the advantage of

\par}{\phpg\posx835\pvpg\posy7756\absw9194\absh5536 \sl-230 \f20 \fs18 \cf0 havi
ng both read and write capabilities but does not have the disadvantage{\fs18 of
} being a volatile memory
0 or having a battery backup.
74 A logic diagram of a commercial NVSRAM is shown in{\fs17 Fig.}{\i \fs18
12-15a.} The names of the pins are
0 given in the chart in Fig.{\i \fs18 12-156.} Notice from the logic diagram t
hat the NVSRAM has{\i \fs19 two} parallel
0 memory arrays. The front memory array is a normal static RAM, while the back i
s an EEPROM. Each
2 SRAM storage location has a parallel EEPROM memory cell. During normal oper
ation the{\b SRAM }
6 array is written into and read from just like with any SRAM. When the dc power
supply voltage drops,
2 {\fs19 a} circuit automatically senses the drop in dc supply voltage and perfo
rms the{\i \fs18 store} operation, and all \par
}
.{\fs16 121 }\par
}
}
f0 297 \par
}
15 \cf0 A3
cf0 A4
cf0 A5 \par
}
11 \cf0 A7 \par
}
atic{\b \f30 \fs17 RAM }
2 array
256{\f10 \fs11 X} 256 \par
}
par
}
par
}
20 \fs15 \cf0 A9
cf0 A12 \par
}
s15 \cf0 DQo
\fi22 DQi
\cf0 DQ2
\cf0 \fi22 DQ3
\fi22 DQ4
\cf0 DQ5
\cf0 DQ6
\cf0 DQ7 \par
}
ore,'
recall
\par}{\phpg\posx8381\pvpg\posy5201\absw590\absh534 \sl-201 \f20 \fs15 \cf0 contr
ol \par
}
L \par
}
I \par
}
\par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 Logic}{\b0\i0 \f20 \fs15 diagram }\par
}
\par
}
{\phpg\posx3735\pvpg\posy8899\absw73\absh232 \f10 \fs19 \cf0 \f10 \fs19 \cf0 [ \
par
}
15 \cf0 &-Al2
{\b0 \f10 \fs18 i7 }
cf0 {\fs10 0120-0127 }\par
}
Addressinputs
\par}{\phpg\posx5261\pvpg\posy8951\absw1033\absh1249 \sl-300 \f20 \fs15 \cf0 Wri
te enable
\par}{\phpg\posx5261\pvpg\posy8951\absw1033\absh1249 \sl-275 \f20 \fs15 \cf0 Dat
a in/out
\par}{\phpg\posx5261\pvpg\posy8951\absw1033\absh1249 \sl-308 \f20 \fs15 \cf0 Chi
p enable
Output enable \par
}
{\phpg\posx6783\pvpg\posy8899\absw73\absh232 \f10 \fs19 \cf0 \f10 \fs19 \cf0 [ \
par
}
\par
}
\cf0 vcc \par
}
15 \cf0 Nonvolatile enable
i474 Power{\f10 \fs13 (+}5{\fs15 V) }
i474 Ground
0 {\b\i (b)}Pin names \par
}
\cf0 Fig.{\f10 \fs15 12-15}{\b0 \fs17
STKlOC68}{\b0 \fs17 CMOS}{\b0 \fs15
nonvolatile}{\b0 \fs17 SRAM}{\i (Cou:rtesy}{\b0 \fs17 of}{\i \fs16 Sirntek
}{\i \fs16 Corporation) }\par
}
data on the volatile SRAM array{\fs18 is} stored in the nonvolatile EiEPROM ar
ray. This store operation is
wn with an arrow pointing from the SRAM to the EEPROM on the logic diagram in Fi
g.{\i \f10 \fs18 12-15a. }
\fs13 \\With}{\b \fs13 the}{\b \fs9 nnuipr}{\b \f10 \fs12 niT}{\b \fs13
the}{\b \fs13
EEPRnM}{\b \fs10 arrgw}{\b \fs13 ixrithin}{\b \fs13 the}{\
b \fs13 NVCR}{\b \fs13 A}{\b \fs13 M}{\b \fs13 hnldc}{\b \fs10
a}{\b \f
s13 diinliratp}{\b \f10 \fs11 nf}{\b \fs13 the}{\b \fs11 lact}{\b \fs13
dsta}{\b \fs13
in}{\b \fs13 the }
\par}{\phpg\posx869\pvpg\posy12560\absw9014\absh1275 \sl-286 \f20 \fs19 \cf0 SRA
M array. When power to the chip{\fs17 is} turned on, the{\b \fs17 NVSRAM} a
utomatically performs the{\i \f10 \fs16 recall }
\par}{\phpg\posx869\pvpg\posy12560\absw9014\absh1275 \sl-232 \f20 \fs19 \cf0 ope
ration shown with an arrow pointing from the EEPROM{\fs18 to} the SRAM in{\fs17
Fig.} 12-15a. The recall
\par}{\phpg\posx869\pvpg\posy12560\absw9014\absh1275 \sl-241 \f20 \fs19 \cf0 ope
ration copies all the data from the EEPROM array in the NVSRAM to the SRAM array
. \par
}
\par
}
}
AP. 12 \par
}

\cf0 The NVSRAM detailed in Fig. 12-15a is for an STK10C68 CMOS NVSR
AM produced by
\par}{\phpg\posx855\pvpg\posy1339\absw9124\absh2679 \sl-237 \f20 \fs18 \cf0 Simt
ek. The STK10C68 NVSRAM is organized as an{\fs18 8K}{\f10 \fs14 X}{\fs18 8} m
emory. The STK10C68NVSRAM uses
4 {\fs18 13} address lines{\b\i \f10 \fs18 (A,} to{\b\i \f10 \fs18 A12)t}o ac
cess the 8192 (213)words, each{\fs18 8} bits wide. The access time of the
\par}{\phpg\posx855\pvpg\posy1339\absw9124\absh2679 \sl-235 \f20 \fs18 \cf0 STK1
0C68 NVSRAM is about 25 ns. The SRAM can be read from or written to an unlimited
number
imes, while independent nonvolatile data resides in the EEPROM array. Data can
be transferred
the SRAM to the EEPROM array (store operation), or from the EEPROM{\fs18 to} t
he SRAM array
\par}{\phpg\posx855\pvpg\posy1339\absw9124\absh2679 \sl-238 \f20 \fs18 \cf0 (rec
all operation), using the
pin. The STK10C68 NVSRAM can handle
more than 10000
e-to-EEPROM operations and an unlimited number of recall-from-EEPROM oper
ations. The
\par}{\phpg\posx855\pvpg\posy1339\absw9124\absh2679 \sl-232 \f20 \fs18 \cf0 STK1
0C68 operates on a{\fs19 5-V} dc power supply. The STK10C68 is packaged in
a variety of standard
\par}{\phpg\posx855\pvpg\posy1339\absw9124\absh2679 \sl-245 \f20 \fs18 \cf0 28-p
in packages.
}
cf0 12.29{\b0 The}{\b0 letters}{\b0 PROM}{\b0 stand}{\b0 for }
}
par
}
he letters PROM stand for programmable read-only memory. \par
}
cf0 12.30{\b0 The}{\b0 letters}{\b0 EPROM}{\b0 stand}{\b0 for }
}
\par
}
he letters EPROM stand for erasable programmable read-only memory. \par
}
cf0 12.31{\b0 The}{\b0 letters}{\b0 NVRAM}{\b0 stand}{\b0 for }
}
par
}
he letters NVRAM stand for nonvolatile random-access memory (nonvolatile RA
M). \par
}
cf0 12.32 A{\b0 PROM}{\b0 can}{\b0 be}{\b0 programmed }
}
many times, only once). \par
}
\cf0 A PROM can be programmed only once.
{\b \fs18 12.33}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 12-12b.}{\b \fs19
A}{\fs18 blown}{\fs18 fuse}{\fs18 in}{\fs18 this}{\fs18 PROM}{\fs18 mean
s}{\fs18 that}{\fs18 memory}{\fs18 cell}{\fs18 stores}{\fs18 a}{\fs18 logi
cal }
92 {\fs18 (0,1). }
46 A blown fuse in the PROM in Fig. 12-126 means that memory cell is
storing a logical{\fs16 0. }\par
}
\cf0 12.34{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 12-12b.}{\b0 List}{\b0 the}{
\b0 outputs}{\b0 from}{\b0 the}{\b0 PROM}{\b0 for}{\b0 the}{\b0 binary}{\
b0 inputs}{\b0 of}{\b0 \fs18 00,}{\b0 01,}{\b0 10,}{\b0 and }
fi602 {\b0 11. }
fi941 {\b0 \fs17 The}{\b0 \fs17 outputs}{\b0 \fs17 from}{\b0 \fs17 the}{\b0
\fs17 PROM}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 12-126}{\b0 \fs17
for}{\b0 \fs17 each}{\b0 \fs17 address}{\b0 \fs17 are}{\b0 \fs17 as}{\b0
\fs17 follows: }\par
}
address{\fs16 00} output{\f10 \fs13 =} 1001 (row 0)
ress 01 output{\f10 \fs13 =} 0111 (row 1) \par
}
address 10 output{\f10 \fs13 =} 1110{\fs17 (row} 2)
ress 11 output{\f10 \fs13 =} 1000{\b \fs16 (row} 3) \par
}
\cf0 12.35{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 12-11.}{\b0 What}{\b0 is}{\b0
the}{\b0 purpose}{\b0 of}{\b0 the}{\b0 window}{\b0 in}{\b0 the}{\b0 EPR
OM? }
fi944 {\b0 \fs16 A}{\b0 \fs17 strong}{\b0 \fs17 ultraviolet}{\b0 \fs17 (UV
)}{\b0 \fs17 light}{\b0 \fs17 directed}{\b0 \fs17 through}{\b0 \fs17 the
}{\b0 \fs17 window}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 IC}{\b0 \fs17
in}{\b0 \fs17 Fig.}{\b0 \fs17 12-11}{\b0 \fs17 will}{\b0 \fs17 erase}{
\b0 \fs17 the }
fi586 {\b0 \fs17 EPROM}{\b0 \fs17 chip. }\par
}
.{\fs17 121 }\par
}
}
\par
}
cf0 12.36{\b0 \fs19 What}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 advantage}
{\b0 \fs19 of}{\b0 \fs19 an}{\b0 \fs19 EPROM}{\b0 \fs19 over}{\b0 \fs19 a}
{\b0 \fs19 PROM? }
i944 {\b0 \fs17 The}{\b0 \fs17 EPROM}{\b0 \fs17 can}{\b0 \fs17 be}{\b0 \fs
17 erased}{\b0 \fs17 and}{\b0 \fs17 used}{\b0 \fs17 over,}{\b0 \fs17 wh
ereas}{\b0 \fs17 the}{\b0 \fs17 PROM}{\b0 \fs17 can}{\b0 \fs17 be}{\b0 \f
s17 programmed}{\b0 \fs17 only}{\b0 \fs17 once. }\par
}
cf0 12.37{\b0 \fs19 The}{\fs19 2732A}{\fs19 1C}{\b0 \fs19 shown}{\b0 \fs19
in}{\b0 \fs19 Fig.}{\b0 \fs19 12-14is}{\b0 \fs19 a(n) }
}
EPROM,{\fs19 RAM)} memory unit. \par
}
\cf0 The 2732A IC shown in Fig. 12-14 is an EPROM memory unit.
{\b \fs18 12.38}{\fs19 Refer}{\fs19 to}{\fs19 Fig.}{\fs19 12-11.}{\fs19 Wh
y}{\fs19 would}{\fs19 an}{\fs19 opaque}{\fs19 sticker}{\fs19 be}{\fs19 pl
aced}{\fs19 over}{\fs19 the}{\fs19 window}{\fs19 of}{\fs19 the}{\fs19 EPRO
M }
89 {\fs19 after}{\fs19 programming? }
37 {\b\i \f10 \fs15 An} opaque sticker is commonly placed over the windo
w of an EPROM (see Fig. 12-11) to keep
86 sunlight and fluorescent light from erasing the memory unit.
{\b \fs18 12.39}{\fs19
Refer}{\fs19 to}{\fs18 Fig.}{\fs19 12-14.}{\fs19 W
hat}{\fs19 is}{\fs19 the}{\fs19 purpose}{\fs19 of}{\fs19 the}{\i \fs19 m/
V,,}{\fs19 input}{\fs19 pin}{\fs19 on}{\fs19 the}{\b \fs19 2732A}{\fs19 EP
ROM? }
46 The{\i \f10 \fs15 =/I$,}
pin on the 273214 EPROM shown in Fig.
12-14 has a dual purpose.{\fs17 In} the read mode,
90 the{\f10 \fs21 @} pin is the output enable to turn on the three-stat
e buffers so they can drive the data bus. In the
85 program mode, the{\b\i \fs19 I}{\b\i \fs19 /}{\b\i \fs19 p}{\b\i \fs19 p}
pin is held at 21 V, which allows writing into the EPROM through
the{\fs17 0,-0, }
84 pins. \par
}
cf0 12.40{\b0 \fs19 The}{\b0 \fs19 letters}{\b0 \fs19 SRAM}{\b0 \fs19 stand
}{\b0 \fs19 for }
}
par
}
he letters SRAM stand for static RAM, or static random-access memory. \pa
r
}
cf0 12.41{\b0 \fs19 The}{\b0 \fs19 letters}{\b0 \fs19 NVSRAM}{\b0 \fs19 sta
nd}{\b0 \fs19 for }
}
par
}
\cf0 The letters NVSRAM stand for nonvolatile static random-access memory
.
{\b \fs18 12.42}{\fs19 What}{\fs19 two}{\fs19 methods}{\fs19 are}{\fs19 cu
rrently}{\fs19 used}{\fs19 to}{\fs19 form}{\fs19 nonvolatile}{\fs19 stati
c}{\b \fs19 RAMS? }
41 Currently nonvolatile SRAM memories are produced by{\f10 \fs15 (1)}
using a CMOS SRAM with battery
88 backup and (2) using a NVSRAM (see Fig. 12-15a). \par
}
\cf0 12.43{\b0 \fs19 SRAMs}{\b0 \fs19 with}{\b0 \fs19 battery}{\b0 \fs19 b
ackup}{\b0 \fs19 generally}{\b0 \fs19 use}{\b0 \fs19 a}{\b0 \fs19 long-l
ife}{\b0 \fs19 battery}{\b0 \fs19 such}{\b0 \fs19 as}{\b0 \fs19 a }
fi589 {\b0 \fs19 lithium)}{\b0 \fs19 battery}{\b0 \fs19 to}{\b0 \fs19 supply}
{\b0 \fs19 standby}{\b0 \fs19 power}{\b0 \fs19 when}{\b0 \fs19 the}{\b0 \fs1
9 dc}{\b0 \fs19 power}{\b0 \fs19 supply}{\b0 \fs19 is}{\b0 \fs19 turned}{\

b0 \fs19 off. }
}
(carbon-zinc, \par
}
0 \fs17 \cf0 SRAMs{\b0 with}{\b0 battery}{\b0 backup}{\b0 commonly}{\b0
use}{\b0 lithium}{\b0 batteries}{\b0 to}{\b0 supply}{\b0 standby}{\b0
power}{\b0 when}{\b0 the}{\b0 dc }
{\b0 power}{\b0 supply}{\b0 is}{\b0 off. }\par
}
\cf0 12.44{\b0 \fs19 The}{\b0 \fs19 NVSRAM}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\
b0 \fs19 12-15might}{\b0 \fs19 also}{\b0 \fs19 be}{\b0 \fs19 called}{\b0 \fs
19 a}{\b0 \fs19 NVRAM}{\b0 \fs19 or }
}
(DRAM, NOVRAM). \par
}
The NVSRAM in Fig. 12-15 might also be called a NVRAM or NOVRAM. \par
}
0 300 \par
}
}
AP. 12 \par
}
cf0 12.45{\b0 \f20 \fs19
The}{\b0 \f20 \fs19 NVSRAM}{\b0 \f20 \fs19 contai
ns}{\b0 \f20 \fs19 both}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 static}{\b0 \f20
\fs19 RAM}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 nonvolatil
e }
i588 {\b0 \f20 \fs19 the}{\b0 \f20 \fs19 same}{\b0 \f20 \fs19 size. }
}
EEPROM, ROM){\fs18 of }\par
}
\cf0 See Fig. 12-15a. The NVSRAM contains both a static RAM and a nonvolatil
e EEPROM of the same
89 size.
{\b \f10 \fs17 12.46}{\fs19
Refer}{\fs19 to}{\fs19 Fig.}{\fs19 12-15.}{\
fs19 As}{\fs19 power}{\fs19 is}{\fs19 turned}{\fs19 off,}{\fs19 the}{\f
s19 STK10C68}{\fs19 NVSRAM}{\fs19 automatically }

85 {\fs19 (recalls,}{\fs19 stores)}{\fs19 the}{\fs19 data}{\fs19 on}{\fs19
the}{\fs19 SRAM}{\fs19 to}{\fs19 the}{\fs19 EEPROM. }
45 As power is turned off, the STKlOC68 NVSRAM automatically stores (c
opies) the data on the
91 {\b \fs17 SRAM} to the EEPROM.
{\b \f10 \fs17 12.47}{\fs19
Refer}{\fs19 to}{\fs19 Fig.}{\fs19 12-15.As}{\
fs19 power}{\fs19 is}{\fs19 first}{\fs19 turned}{\fs19 on,}{\fs19 the}{\fs
19 STK10C68}{\fs19 NVSRAM}{\fs19 automatically }
85 {\fs19 (recalls,}{\fs19 stores)}{\fs19 the}{\fs19 data}{\fs19 from}{\fs19
the}{\fs19 EEPROM}{\fs19 to}{\fs19 the}{\fs19 SRAM. }
45 {\b As} power is first turned on, the STKlOC68 NVSRAM automatically
recalls (copies) data{\fs17 from} the
91 EEPROM to the SRAM.
{\b \f10 \fs17 12.48}{\fs19
Refer}{\fs19 to}{\fs19 Fig.}{\fs19 12-15.}{\fs
19 What}{\fs19 is}{\fs19 the}{\fs19 purpose}{\fs19 of}{\fs19 the}{\fs19
eight}{\i \fs18 DQ}{\fs19 pins}{\fs19 on}{\fs19 the}{\fs19 STK10C68}{\fs1
9 NVSRAM? }
58 The{\b\i \f30 \fs20 DQ} pins serve as eight parallel data outputs d
uring memory read operations or data inputs
03 during a memory write operation. \par
}
\cf0 12-5{\f20 \fs19
MICROCOMPUTER}{\f20 \fs19 BULK}{\f20 \fs19 STORAGE }
fi362 {\b0 \f20 \fs19 Program}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 data}{\b0
\f20 \fs19 storage}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
computer}{\b0 \f20 \fs19 system}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 sometim
es}{\b0 \f20 \fs19 classified}{\b0 \f20 \fs19 as}{\b0 \f20 \fs19 either}{\
b0 \f20 \fs19 internal}{\b0 \f20 \fs19 or }
\i \f20 \fs19 external.}{\b0 \f20 \fs19 In}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
microcomputer,}{\b0 \f20 \fs19
the}{\b0 \f20 \fs19 internal}{\b0 \f20 \f
s19 storage}{\b0 \f20 \fs19 devices}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19
semiconductor}{\b0 \f20 \fs19
RAM,}{\b0 \f20 \fs19 ROM}{\b0 \f20 \fs19 (o
r }
\b0 \f20 \fs19 EPROM),}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 various}{\b0 \f20 \
fs19 registers.}{\b0 \f20 \fs19 Currently}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19
most}{\b0 \f20 \fs19 common}{\b0 \f20 \fs19 form}{\b0 \f20 \fs19 of}{\b0 \
f20 \fs19 external}{\b0 \f20 \fs19 storage}{\b0 \f20 \fs19 for}{\b0 \f20 \fs
19 microcom- }
\b0 \f20 \fs19 puters}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19
magnetic}{\b0 \f20 \fs19 disk.}{\b0 \f20 \fs19 Magnetic}{\b0 \f20 \fs19

disks}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 subdivided}{\b0 \f20 \fs19 into
}{\b0 \f20 \fs19 hard}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19 floppy}{\b0 \f20
\fs19 disks.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 most }
\b0 \f20 \fs19 common}{\b0 \f20 \fs19 form}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19
magnetic}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 with}{\b0
\f20 \fs19 microcomputers}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 the}{\b0\i \f2
0 \fs17 floppy}{\i \f20 \fs19 disk.}{\b0 \f20 \fs19 Typical}{\b0 \f20 \fs19
types}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 memory }
\b0 \f20 \fs19 devices}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 in}{\b0 \f20 \fs1
9 microcomputers}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 summarized}{\b0 \f20 \f
s19 in}{\b0 \f20 \fs18 Fig.}{\b0 \f20 \fs19 12-1.}{\b0 \f20 \fs19 External
}{\b0 \f20 \fs19 storage}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 also}{\b0 \f20 \
fs19 referred}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 as }
\i \f20 \fs19 bulk}{\i \f20 \fs19 storage. }
fi362 {\b0 \f20 \fs19 Data}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 stored}{\b0 \f20
\fs19 on}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disks}{\b0 \f20 \fs19 in}{\
b0 \f20 \fs19 much}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 same}{\b0 \f20 \fs19
way}{\b0 \f20 \fs19 it}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19
magnetic}{\b0 \f20 \fs19 tapes.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 disk}{
\b0 \f20 \fs19 drive}{\b0 \f20 \fs19 unit }
\b0 \f20 \fs19 reads}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 writes}{\b0 \f20 \f
s19 on}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disk.}{
\b0 \f20 \fs19 This}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 like}{\b0 \f20 \fs1
9 the}{\b0 \f20 \fs19 play}{\b0 \f20 \fs19 and}{\b0 \f20 \fs19 record}{\
b0 \f20 \fs19 functions}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 a}{\b0 \f20 \fs
19 tape}{\b0 \f20 \fs19 recorder. }
\b0 \f20 \fs19 Reading}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
disk}{\b0 \f20 \fs19 has}{\b0 \f20 \fs19 an}{\b0 \f20 \fs19 advantage}{\b0 \
f20 \fs19 over}{\b0 \f20 \fs19 reading}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19
a}{\b0 \f20 \fs19 tape}{\b0 \f20 \fs19 because}{\b0 \f20 \fs19 the}{\b0 \f20
\fs19 disk}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 random-acc
ess }
\b0 \f20 \fs19 instead}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 s
equential-access}{\b0 \f20 \fs19 device.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19
disk}{\b0 \f20 \fs19 drive}{\b0 \f20 \fs19 can}{\b0 \f20 \fs19 access}{\b0 \f
20 \fs19 any}{\b0 \f20 \fs19 point}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 the}{\
b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19
a}{\b0 \f20 \fs19 very }
\b0 \f20 \fs19 short}{\b0 \f20 \fs19 time.}{\b0 \f20 \fs19 In}{\b0 \f20 \fs19
contrast,}{\b0 \f20 \fs19 access}{\b0 \f20 \fs19 to}{\b0 \f20 \fs19 informat
ion}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 tape}{\b0 \f20 \fs1
9 is}{\b0 \f20 \fs19 very}{\b0 \f20 \fs19 slow. }
fi361 {\b0 \f20 \fs19 Floppy}{\b0 \f20 \fs19 disks,}{\b0 \f20 \fs19 or}{\b0 \f
20 \fs19 diskettes,}{\b0 \f20 \fs19 come}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19
several}{\b0 \f20 \fs19 sizes.}{\b0 \f20 \fs19 Those}{\b0 \f20 \fs19 most}{\b
0 \f20 \fs19 commonly}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19 with}{\b0 \f20 \fs
19 microcomputers }
\b0 \f20 \fs19 are}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 5.25-in}{\b0 \f20 \fs19
and}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 newer}{\b0 \f20 \fs19 3.5-in}{\b0 \
f20 \fs19 sizes.}{\b0 \f20 \fs19 There}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 al
so}{\b0 \f20 \fs19 an}{\b0 \f20 \fs19 8-in}{\b0 \f20 \fs19 version}{\b0 \f20
\fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disk}{\b
0 \f20 \fs19 available.}{\f20 \fs18 A }
typical}{\b0 \f20 \fs19 5.25-in}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disk}
{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 shown}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19
Fig.}{\b0 \f20 \fs19 12-16a.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 thin,}{\
b0 \f20 \fs19 circular,}{\b0 \f20 \fs19 plastic}{\b0 \f20 \fs19 floppy}{\b
0 \f20 \fs19 is }
\b0 \f20 \fs19 permanently}{\b0 \f20 \fs19 enclosed}{\b0 \f20 \fs19 in}{\b0
\f20 \fs19 a}{\b0 \f20 \fs19 plastic}{\b0 \f20 \fs19 jacket.}{\b0 \f20 \fs1
9 The}{\b0 \f20 \fs19 plastic}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 is}{\
b0 \f20 \fs19 coated}{\b0 \f20 \fs19 with}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19
magnetic}{\b0 \f20 \fs19 material,}{\b0 \f20 \fs19 iron }
\b0 \f20 \fs19 oxide}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19 barium}{\b0 \f20 \fs19
ferrite.}{\b0 \f20 \fs19 Several}{\b0 \f20 \fs19 holes}{\b0 \f20 \fs19 are}
{\b0 \f20 \fs19 cut}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 both}{\b0 \f20 \fs19
sides}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 jacket.}{\b0 \f2
0 \fs19 These}{\b0 \f20 \fs19 are}{\b0 \f20 \fs19 illustrated}{\b0 \f20 \fs19
in}{\b0 \f20 \fs19 Fig. }
\b0 \f20 \fs19 12-16a. }
fi360 {\b0 \f20 \fs19 The}{\b0 \f20 \fs19 round}{\b0 \f20 \fs19 center}{\b0 \f
20 \fs19 hole}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 jacket}
{\b0 \f20 \fs19 provides}{\b0 \f20 \fs19 access}{\b0 \f20 \fs19 to}{\b0 \f20
\fs19 the}{\b0 \f20 \fs19 center}{\b0 \f20 \fs19 area}{\b0 \f20 \fs18 of}{\
b0 \f20 \fs19 the}{\b0 \f20 \fs19 disk.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19
hub}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the }
\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 drive}{\b0 \f20 \fs19 clamps}{\b0 \f20 \fs
19 on}{\b0 \f20 \fs19 this}{\b0 \f20 \fs19 area}{\b0 \f20 \fs19 to}{\b0 \f20
\fs19 spin}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 at}{\b0
\f20 \fs19 a}{\b0 \f20 \fs19 constant}{\b0 \f20 \fs19 speed}{\b0 \f20 \fs18
(300}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19 360}{\b0 \f20 \fs19 rpm).}{\b0 \f20
\fs19 The}{\b0 \f20 \fs19 larger}{\b0 \f20 \fs19 hole}{\b0 \f20 \fs19 in }
\b0 \f20 \fs19 the}{\b0 \f20 \fs19 jacket}{\b0 \f20 \fs19 near}{\b0 \f20 \fs19
the}{\b0 \f20 \fs19 bottom}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 the}{\b0 \f20
\fs19 disk}{\b0 \f20 \fs19 shown}{\b0 \f20 \fs19 in}{\b0 \f20 \fs19 Fig.}{\
b0 \f20 \fs19 12-16a}{\b0 \f20 \fs19 exposes}{\b0 \f20 \fs19 part}{\b0 \f20 \
fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 to}{\b0 \f2
0 \fs19 the}{\b0 \f20 \fs19 read/write }
\b0 \f20 \fs19 head}{\b0 \f20 \fs19 of}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 di
sk}{\b0 \f20 \fs19 drive.}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 read/write}{\b0
\f20 \fs19
head}{\b0 \f20 \fs19 touches}{\b0 \f20 \fs19 the}{\b0 \f20 \fs1
9 spinning}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 to}{\
b0 \f20 \fs19 store}{\b0 \f20 \fs19 data}{\b0 \f20 \fs19 on}{\b0 \f20 \fs19
the}{\b0 \f20 \fs19 disk }
\b0 \f20 \fs19 (to}{\b0 \f20 \fs19 write)}{\b0 \f20 \fs19 or}{\b0 \f20 \fs19
retrieve}{\b0 \f20 \fs19 data}{\b0 \f20 \fs19 from}{\b0 \f20 \fs19 it}{\b0 \f
20 \fs19 (to}{\b0 \f20 \fs19 read).}{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 smal
l}{\b0 \f20 \fs19 round}{\b0 \f20 \fs19 hole}{\b0 \f20 \fs19 cut}{\b0 \f20 \
fs19 in}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 jacket}{\b0 \f20 \fs19 and}{\b0
\f20 \fs19 disk}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 used}{\b0 \f20 \fs19
}\par
as
}
0 CHAP.{\b0 121 }\par
}
}
\par
}
s14 \cf0 (a){\i0 \fs15 Features}{\i0 \fs15 of}{\i0 \fs15 the}{\i0 \fs15 disk
}\par
}
cf0 Inside track
\par}{\phpg\posx3109\pvpg\posy5495\absw952\absh374 \sl-199 \b \f20 \fs17 \cf0 (t
rack{\fs17 34) }\par
}
cf0 .ck \par
}
s15 \cf0 (b){\i0 \fs15 Location}{\i0 \fs15 of}{\i0 \fs15 invisible}{\i0 \fs15
tracks}{\i0 \fs15 on}{\i0 \fs15 disk }\par
}
\cf0 (c){\fs15 Location}{\fs15 of}{\fs15 invisible}{\fs15 sectors}{\fs15
on}{\fs15 disk }
cf0 {\fs17 Fig.}{\f30 \fs17 12-16}{\fs17 A}{\b0 \fs17 5.25-in}{\fs16 floppy
}{\fs17 disk }\par
}
\par
}
}
AP.{\fs17 12 }\par
}
n index hole by disk drives on a few computers. If covered, the wri
te-protect notch on the 5.25-in
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-244 \f20 \fs18 \cf0 flop
py disk prevents data from being written to the disk. When the write-protect
notch is open, as in
12-16a, the disk drive can both write to and read from the disk.
66 Floppy disks are organized in tracks and sectors. Figure 12-16b show
s how one microcomputer
facturer formats the 5.25-in floppy disk. The disk is organized into 35 circula
r tracks numbered
{\fs19 00} to 34{\fs19 (00} to 22 in hexadecimal). Each track is divided into
{\fs19 16} sectors, which are shown in Fig.
6c. Each sector has 35 short tracks, as shown near the bottom of Fig. 12-16c. B
y using this format,
short track can hold 256 eight-bit words, or 256 bytes.
58 When formatted as shown in Fig. 12-16c, a floppy disk can hold about 140K byt
es of data. That is
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-240 \f20 \fs18 \cf0 abou
t{\fs19 1}million bits{\fs19 of} data on a single 5.25-in floppy disk. It shou
ld be noted that there is no standard
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-242 \f20 \fs18 \cf0 meth
od{\fs19 of} formatting floppy disks. Many microcomputer manufacturers f
ormat their disks to hold
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-239 \f20 \fs18 \cf0 much
more data. That includes reading and writing on both sides of the disk.
60 The floppy disk is a random-access bulk storage memory device which is wid
ely used with home,
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-242 \f20 \fs18 \cf0 scho
ol, and office microcomputers. Care must be taken when handling floppy disks.{
\fs19 Do} not touch the
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-238 \f20 \fs18 \cf0 magn
etic disk itself, and do not press hard when writing on the plastic j
acket (5.25-in and %in).{\b \fs18 A }
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-238 \f20 \fs18 \cf0 felt
-tip pen is recommended for labeling floppy disks. Magnetic fields and high tem
peratures also can
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-239 \f20 \fs18 \cf0 harm
data stored on floppy disks. Because{\fs18 of} the danger of surface
abrasion, keep disks in a clean
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-238 \f20 \fs18 \cf0 area
and protect the thin magnetic coating from scratches.
60 {\b \fs19 A} diagram{\fs18 of} the 3.5-in floppy disk is shown in Fig
. 12-17. The case is made of rigid plastic for
\par}{\phpg\posx851\pvpg\posy1407\absw9186\absh4304 \sl-244 \f20 \fs18 \cf0 maxi
mum protection of the floppy disk housed inside. The drawing{\fs19 of} the 3.
5-in disk in Fig. 12-17 is a \par
}
\cf0 Fig.{\fs16 12-17}{\fs17
A}{\b0 \fs17 3.5-in}{\fs15 floppy}{\fs17 d
isk }\par
}
. 121 \par
}
}
\par
}

iew from the{\i \fs19 underside} of the storage unit. The center of the pl
astic case is cut out (on the bottom
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-239 \f20 \fs18 \cf0 only
), revealing a metal drive hub which is connected to the floppy disk.{\b \fs19
A} sliding metal cover is shown
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-238 \f20 \fs18 \cf0 in F
ig. 12-17 moved to the right, revealing a rectangular cutout in the rigid pla
stic case exposing the
py disk. The floppy disk is accessible from both the bottom and top sides of
the disk{\fs19 so} the disk
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-239 \f20 \fs18 \cf0 driv
e read/write heads can retrieve/store data on both sides. When released, the
sliding metal cover,
h is spring-loaded, snaps back to the left (in Fig. 12-17)to protect the surface
of the floppy disk.{\b \fs19 A }
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-242 \f20 \fs18 \cf0 writ
e-protect notch is shown at the lower right of the 3.5-in disk in Fig. 12-17.If
the write-protect hole
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-239 \f20 \fs18 \cf0 is c
losed by sliding the built-in cover upward (as shown in Fig. 12-17),the disk dri
ve can both write to
read from the disk. This is sometimes called the unlocked position. If the hole
is open (slide cover
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-237 \f20 \fs18 \cf0 down
ward in Fig. 12-17), the disk drive can{\i \fs19 only} read from the
disk. This{\fs19 is} sometimes called the
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-238 \f20 \fs18 \cf0 lock
ed position.{\b\i \f10 \fs17 An} index hole is cut in the metal hub for timin
g purposes.
65 The 3.5-in disk shown in Fig. 12-17 is a newer development, compared
to the 5.25-in and 8-in
py disks. Precision disk drives commonly access{\fs19 80} tracks on bo
th sides of the disk. Common
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-242 \f20 \fs18 \cf0 form
ats on the 3.5-in disk allow it to store either 400K, 720K, or{\fs19 800K} by
tes. Available with suitable
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-237 \f20 \fs18 \cf0 disk
drives, high-density 3.5-in disks (FDHD-floppy
disk high density) have stora
ge capacity of 1.44M
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-239 \f20 \fs18 \cf0 byte
s. Most modern microcomputers come with at least one disk drive used to read fro
m and write to
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-242 \f20 \fs18 \cf0 3.5in floppy disks.
65 Another bulk storage method that is very popular on microcomputers, as wel
l as large computer
ems, is the{\i \fs19 hard}{\i \fs19 disk,} a rigid metal disk coated
with magnetic material. These disks may be
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-238 \f20 \fs18 \cf0 arra
nged as shown in Fig. 12-18. Notice that read/write heads float just
above the surface of the
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-239 \f20 \fs18 \cf0 spin
ning hard disks. The motor spins the hard disk at about 3000 rpm, which is a
bout{\fs19 10} times faster
the rotation of a floppy disk. The drive units are very precise, a
nd the hard disk may be
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-242 \f20 \fs18 \cf0 perm
anently mounted with the air filtered to keep out unwanted dust and smoke wh
ich can hamper
ation. Removable hard disks, such as the 5.25-in cartridge drive, are a
lso available. Currently
\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-242 \f20 \fs18 \cf0 20M, 40M-, and 80M-byte hard drives are common on home, school, and small busin
ess microcom\par}{\phpg\posx909\pvpg\posy1332\absw9132\absh5827 \sl-237 \f20 \fs18 \cf0 pute
rs. Larger-capacity units are also widely used in business. Two advanta
ges of hard disks over
py disks are (1)they store many times more information and (2) they can access i
nformation faster. \par
}
\cf0 Fig.{\f10 \fs15 12-18}{\b0
Hard}{\b0 disk}{\b0 drive}{\b0 mechanis
m }\par
}
8 \cf0 Hard disk drives are sometimes called{\i \fs19 Winchester} drives
. Microcomputers with hard drives are
\par}{\phpg\posx929\pvpg\posy12568\absw9153\absh1075 \sl-242 \f20 \fs18 \cf0 ver
y common and typically also have a floppy disk drive attached to the
system{\fs19 so} the data and
grams on the hard drive can be backed up for use in the event of hard disk f
ailure.
373 Still another bulk storage method that shows great promise is the{\i \fs19
optical}{\i \fs19 disk.} The optical disk is a
\par}{\phpg\posx929\pvpg\posy12568\absw9153\absh1075 \sl-240 \f20 \fs18 \cf0 rel
ative of the laser videodisk. Optical disks are available in three types: (1)
read-only, (2) write-once \par
}
0 304 \par
}
}
AP. 12 \par
}
ead-many (WORM), and (3) read/write. The read-only disk (optical ROM) is good
for prerecorded
\par}{\phpg\posx855\pvpg\posy1368\absw9644\absh6508 \sl-237 \f20 \fs19 \cf0 info
rmation like an encyclopedia. The WORM optical disk can be written to once and t
hen read from
\par}{\phpg\posx855\pvpg\posy1368\absw9644\absh6508 \sl-237 \f20 \fs19 \cf0 many
times.

86 Read/write optical disks have large storage capacities and are similar in fu
nction to a hard disk.
1 The technology used for writing and reading with the optical disk is differen
t from the magnetic hard
1 disk. The{\b\i \fs19 magneto-optical} disk drive uses a laser in conjunction
with a coil of wire to erase, write to,
5 and read from the metal-coated disk.{\b A} popular magneto-optical disk has
a storage capacity of 128M
\par}{\phpg\posx855\pvpg\posy1368\absw9644\absh6508 \sl-237 \f20 \fs19 \cf0 byte
s{\fs19 on} a removable 3.5-in optical disk. These optical disks look
much like the 3.5-in floppy disk
2 except they are thicker and contain an optical disk. These removable
{\fs18 disks} are sometimes called
i \fs19 rewritable}{\b\i \fs19 magneto-optical}{\b\i \f30 \fs20 disks.}{\b \fs
19 A} 5.25-in magneto-optical disk drive is also available with removable
0 cartridges with a storage capacity of 650M bytes. Because the magneto-optic
al disk can be removed
the disk drive, it is a suitable medium for backup storage or for transferr
ing large amounts of
or programs from one machine to another.
81 One of the least expensive methods for storing vast amounts of data for backu
p is to use magnetic
\par}{\phpg\posx855\pvpg\posy1368\absw9644\absh6508 \sl-235 \f20 \fs19 \cf0 tape
. Some drives are available that use inexpensive digital audio tape (DAT); howev
er, access to data
ape{\fs19 is} very slow.
\f10 \fs17 12.49} Refer to Fig. 12-1.Which device(s) on the microcomputer sho
wn could be classified as internal
09 storage?
64 {\fs17 Both}{\fs17 the}{\fs17 semiconductor}{\fs17 RAM,}{\fs17 ROM,}{\f
s17 and}{\fs17 NVRAM}{\fs17 on}{\fs17 the}{\fs17 microcomputer}{\fs17
shown}{\fs17 in}{\fs17 Fig.}{\fs17 12-1}{\fs17 could }
04 {\fs17 both}{\fs17 be}{\fs17 classified}{\fs17 as}{\fs17 internal}{\fs1
7 storage.}{\fs17 The}{\fs17 floppy}{\fs17 disk}{\fs17 is}{\fs17 external
}{\fs17 storage. }
\fi20 {\b \f10 \fs17 12.50} What two types of magnetic disks are used on micro
computers?
70 {\fs17 Both}{\fs17
hard}{\fs17
and}{\fs17 floppy}{\fs17 disks}{\fs1
7 are}{\fs17 used}{\fs17 on}{\fs17 microcomputers}{\fs17 for}{\fs17
external}{\fs17 bulk}{\fs17 storage}{\fs17 of}{\fs17
data}{\fs17 and
}
10 {\fs17 programs. }\par
}
cf0 12.51{\b0 \f20 \fs19 The}{\b0 \f20 \fs19 magnetic}{\b0 \f20 \fs19 disk}{
\b0 \f20 \fs19 is}{\b0 \f20 \fs19 a }
}
random-, sequential-) access device. \par
}
\cf0 The magnetic disk is a random-access device, which means it can find da
ta in a very short time.
{\b \f10 \fs17 12.52}{\fs19 What}{\fs19 are}{\fs19 three}{\fs19 sizes}{\fs1
9 of}{\fs19 floppy}{\fs19 disks? }
52 Floppy disks come in the{\i \fs17 3.5,}{\i \fs17 5.25,} and 8-in sizes.
\par
}
\cf0 12.53{\f20 \fs18
A}{\b0 \f20 \fs19 typical}{\b0 \f20 \fs19 disk}{\b0 \
f20 \fs19 drive}{\b0 \f20 \fs19 spins}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19 fl
oppy}{\b0 \f20 \fs19 disk}{\b0 \f20 \fs19 at}{\b0 \f20 \fs19 a}{\b0 \f20 \fs1
9 constant}{\b0 \f20 \fs19 speed}{\b0 \f20 \fs19 of }
}
(300, 3000){\fs19 rpm. }\par
}
0 \fs17 \cf0 A{\b0 \fs17 disk}{\b0 \fs17 drive}{\b0 \fs17 spins}{\b0 \fs17 t
he}{\b0 \fs17 floppy}{\b0 \fs17 disk}{\b0 \fs17 at}{\fs16 a}{\b0 \fs17 co
nstant}{\b0 \fs17 speed}{\b0 \fs17 of}{\b0 \fs17 300}{\b0 \fs17 rpm}{\b0
\fs17 (one}{\b0 \fs17 manufacturer's}{\b0 \fs17 specification). }
{\b0 \fs17 Hard}{\b0 \fs17 disks}{\b0 \fs17 might}{\b0 \fs17 spin}{\b0 \fs1
7 at}{\b0 \fs17 3000}{\b0 \fs17 rpm. }\par
}
\cf0 12.54{\b0 \f20 \fs19
To}{\b0 \f20 \fs19 store}{\b0 \f20 \fs19 data}{\b
0 \f20 \fs19 on}{\b0 \f20 \fs19 a}{\b0 \f20 \fs19 floppy}{\b0 \f20 \fs19 dis
k}{\b0 \f20 \fs19 is}{\b0 \f20 \fs19 called }
}
\par
}
\cf0 To{\b0 \fs17 store}{\b0 \fs17 data}{\b0 \fs17 on}{\b0 \fs17 a}{\b0 \
fs17 floppy}{\b0 \fs17 disk}{\b0 \fs17 is}{\b0 \fs17 called}{\b0 \fs17 writ
ing}{\b0 \fs17 (write}{\b0 \fs17 operation). }\par
}
.{\fs17 121 }\par
}
}
f0 305 \par
}
cf0 12.55{\b0 \fs19 Briefly,}{\b0 \fs19 how}{\b0 \fs19 is}{\b0 \fs19 data}{
\b0 \fs19 organized}{\b0 \fs19 on}{\b0 \fs19 a}{\b0 \fs19 floppy}{\b0 \fs19
disk? }
i944 {\b0 \fs17 Data}{\b0 \fs17 is}{\b0 \fs17 organized}{\b0 \fs17 in}{\b0 \
fs17 tracks}{\b0 \fs17 and}{\b0 \fs17 sectors.}{\b0 \fs17 See}{\b0 \fs17 F
ig.}{\b0 \fs17 12-16b}{\b0 \fs17 and}{\b0\i \f10 \fs14 c}{\b0 \fs17 for}{\
b0 \fs17 more}{\b0 \fs17 detail}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17
format}{\b0 \fs17 used}{\b0 \fs17 by }
i582 {\b0 \fs17 one}{\b0 \fs17 microcomputer}{\b0 \fs17 manufacturer. }\par
}
6c.}{\b0 \fs19 By}{\b0 \fs19 using}{\b0 \fs19 this}{\b0 \fs19 format,}{\
b0 \fs19 a}{\b0 \fs19 floppy}{\b0 \fs19 disk}{\b0 \fs19 can}{\b0 \fs19
hold}{\b0 \fs19 about }
fi590 {\b0 \fs19 information. }
fi947 {\b0 \fs17 By}{\b0 \fs17 using}{\b0 \fs17 the}{\b0 \fs17 format}{\b0 \f
s17 shown}{\b0 \fs17 in}{\b0 \fs17 Fig.}{\b0 \fs17 12-16c,a}{\b0 \fs17 flo
ppy}{\b0 \fs17 disk}{\b0 \fs17 can}{\b0 \fs17 hold}{\b0 \fs17 about}{\b0 \f
s17 140K(16}{\b0 \f10 x}{\b0 \fs17 256}{\b0 \f10 x}{\b0 \fs17 35 }
fi580 {\b0 \fs17 bytes)}{\b0 \fs17 of}{\b0 \fs17 information. }\par
}
{\phpg\posx9007\pvpg\posy2916\absw803\absh215 \f20 \fs19 \cf0 \f20 \fs19 \cf0 by
tes{\fs19 of }\par
}
\f20 \fs17 143360 }\par
}
\cf0 12.57{\b0 \fs19 List}{\b0 \fs19 some}{\b0 \fs19 precautions}{\b0 \fs19
that}{\b0 \fs19 must}{\b0 \fs19 be}{\b0 \fs19 observed}{\b0 \fs19 when}{\b
0 \fs19 5.25-in}{\b0 \fs19 floppy}{\b0 \fs19 disks}{\b0 \fs19 are}{\b0 \fs19
handled. }
fi941 {\b0 \fs17 The}{\b0 \fs17 followingare}{\b0 \fs17 some}{\b0 \fs17 pre
cautions}{\b0 \fs17 when}{\b0 \fs17 floppy}{\b0 \fs17 disks}{\b0 \fs17 are
}{\b0 \fs17 handled: }
fi988 {\b0 \fs17 1.}{\b0 \fs17
Do}{\b0 \fs17 not}{\b0 \fs17 touch}{\b0 \f
s17 the}{\b0 \fs17 magnetic}{\b0 \fs17 disk}{\b0 \fs17 itself. }
fi973 {\fs17 2.}{\b0 \fs17
Mark}{\b0 \fs17 the}{\b0 \fs17 disk}{\b0 \fs1
7 lightly}{\b0 \fs17 or}{\b0 \fs17 with}{\b0 \fs17 felt-tip}{\b0 \fs17 pe
ns}{\b0 \fs17 when}{\b0 \fs17 labeling. }
fi973 {\b0 \fs17 3.}{\b0 \fs17
Keep}{\b0 \fs17 the}{\b0 \fs17 disk}{\b0
\fs17 away}{\b0 \fs17 from}{\b0 \fs17 strong}{\b0 \fs17 magnetic}{\b0 \fs1
7 fields. }
fi975 {\f30 \fs18 4.}{\b0 \fs17
Keep}{\b0 \fs17 the}{\b0 \fs17 disk}{\b0
\fs17 away}{\b0 \fs17 from}{\b0 \fs17 high}{\b0 \fs17 temperatures. }
fi973 {\b0\i \fs17 5.}{\b0 \fs17
Keep}{\b0 \fs17 the}{\b0 \fs17 disk}{\b
0 \fs17 clean. }
fi974 {\b0 \fs17 6.}{\b0 \fs17
Protect}{\b0 \fs17 the}{\b0 \fs17 disk}{\
b0 \fs17 from}{\b0 \fs17 scratches}{\b0 \fs17 or}{\b0 \fs17 surface}{\b0 \
fs17 abrasion. }
fi973 {\b0 \fs17 7.}{\b0 \fs17
Do}{\b0 \fs17 not}{\b0 \fs17 bend}{\b0 \f
s17 or}{\b0 \fs17 fold}{\b0 \fs17 the}{\b0 \fs17 disk. }\par
}
cf0 12.58{\b0 \fs19 What}{\b0 \fs19 advantage}{\b0 \fs19 does}{\b0 \fs19 a
}{\b0 \fs19 hard}{\b0 \fs19 disk}{\b0 \fs19 drive}{\b0 \fs19 have}{\b0 \fs1
9 over}{\b0 \fs19 a}{\b0 \fs19 floppy}{\b0 \fs19 disk? }
i940 {\b0 \fs17 The}{\b0 \fs17 hard}{\b0 \fs17 drive}{\b0 \fs17 has}{\b0 \fs
17 a}{\b0 \fs17 much}{\b0 \fs17 greater}{\b0 \fs17 storage}{\b0 \fs17 c
apacity}{\b0 \fs17 and}{\b0 \fs17 a}{\b0 \fs17 quicker}{\b0 \fs17 access}
{\b0 \fs17 time. }\par
}
cf0 12.59{\b0 \fs19 The}{\b0 \fs19 WORM}{\b0 \fs19 optical}{\b0 \fs19 disk
}{\b0 \fs19 can}{\b0 \fs19 be}{\b0 \fs19 written}{\b0 \fs19 to }
i587 {\b0 \fs19 many}{\b0 \fs19 times. }
}
once, about 10000 times) and read from \par
}
he{\fs17 WORM} (write-once read-many) optical disk can be written to onc
e and read from many times. \par
}
\cf0 12.60{\b0 \fs19 The }\par
}
(magnetic hard disk, magneto-optical disk) drive uses a laser in conjunction wit
h a \par
}
coil of wire to erase, write to, and read from the disk.
352 {\fs17 The}{\fs17 magneto-optical}{\fs17 disk}{\fs17 drive}{\fs17 uses
}{\fs17 a}{\fs17 laser}{\fs17 in}{\fs17 conjunction}{\fs17 with}{\fs17
a}{\fs17 coil}{\fs17 of}{\fs17 wire}{\fs17 to}{\fs17 erase,}{\fs17 write
}{\fs17 to,}{\fs17 and }
s17 read}{\fs17 from}{\fs17 the}{\fs17 optical}{\fs17 disk. }\par
}
\cf0 12.61{\b0 \fs19 The}{\b0 \fs19 popular}{\b0 \fs19 removable}{\b0 \fs1
9 3.5-in}{\b0 \fs19 rewritable}{\b0 \fs19 magneto-optical}{\b0 \fs19 disk}
{\b0 \fs19 has}{\b0 \fs19 a}{\b0 \fs19 capacity}{\b0 \fs19 of}{\b0 \fs19 a
bout }
\fi590 {\b0 \fs19 (400K,}{\b0 \fs19 128M)}{\b0 \fs19 bytes}{\b0 \fs19 and}{\b
0 \fs19 is}{\b0 \fs19 commonly}{\b0 \fs19 used}{\b0 \fs19 for}{\b0 \fs19 ba
ckup}{\b0 \fs19 storage}{\b0 \fs19 or}{\b0 \fs19 for}{\b0 \fs19 transferring
}{\b0 \fs19 large}{\b0 \fs19 amounts }
\fi589 {\b0 \fs19 of}{\b0 \fs19 data}{\b0 \fs19 from}{\b0 \fs19 one}{\b0 \fs1
9 machine}{\b0 \fs19 to}{\b0 \fs19 another. }
\fi944 {\b0 \fs17 The}{\b0 \fs17 popular}{\b0 \fs17 removable}{\b0 \fs17 3
.5-in}{\b0 \fs17 rewritable}{\b0 \fs17 magneto-optical}{\b0 \fs17 disk}{\b
0 \fs17 has}{\b0 \fs17 a}{\b0 \fs17 capacity}{\b0 \fs17 of}{\b0 \fs17 a
bout}{\b0 \fs17 128M}{\b0 \fs17 bytes. }\par
}
0 306 \par
}
}
AP.{\fs16 12 }\par
}
\fi28 {\b \f20 \fs16 12.62}{\f20 \fs17
Refer}{\f20 \fs17 to}{\f20 \fs17
Fig.}{\f20 \fs16 12-1.}{\f20 \fs17 List}{\f20 \fs17 the}{\f20 \fs17 five}
{\f20 \fs17 types}{\f20 \fs17 of}{\f20 \fs17 memory}{\f20 \fs17 used}{\f20
\fs17 by}{\f20 \fs17 this}{\f20 \fs17 microcomputer}{\f20 \fs17 system.
}
91 {\b\i \f20 \fs16 Ans.}{\f20 \fs17
RAM,}{\f20 \fs17 ROM,}{\f20 \fs17 N
VRAM,}{\f20 \fs17 floppy}{\f20 \fs17 disk,}{\f20 \fs17 and}{\f20 \fs17 h
ard}{\f20 \fs17 disk }
\fi28 {\b \f20 \fs16 12.63}{\f20 \fs17
Refer}{\f20 \fs17 to}{\f20 \fs17
Fig.}{\f20 \fs16 12-1.}{\f20 \fs17 Which}{\f20 \fs17 type}{\f20 \fs17 of}{

\f20 \fs17 memory}{\f20 \fs17 in}{\f20 \fs17 this}{\f20 \fs17 system}{\f20
\fs17 is}{\f20 \fs17 volatile? }
91 {\b\i \f20 \fs16 Ans.}{\f20 \fs17
RAM}{\f20 \fs17 (read/write}{\f20 \f
s17
memory) }
{\b \f20 \fs16 12.64}{\f20 \fs17
Refer}{\f20 \fs17 to}{\f20 \fs17 Fig.}{
\f20 \fs16 12-1.}{\f20 \fs17 What}{\f20 \fs17 three}{\f20 \fs17 types}{\f
20 \fs17 of}{\f20 \fs17 storage}{\f20 \fs17 devices}{\f20 \fs17 are}{\f20
\fs17 semiconductor}{\f20 \fs17 memories}{\f20 \fs17 in}{\f20 \fs17 thi
s}{\f20 \fs17 system? }
64 {\b\i \f20 \fs16 Ans.}{\f20 \fs17
RAM,}{\f20 \fs17 ROM,}{\f20 \fs17 a
nd}{\f20 \fs17 NVRAM }\par
}
cf0 12.65{\b0 \fs17
Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 12-1.}{\b
0 \fs17 The}{\b0 \fs17 medium}{\b0 \fs17 for}{\b0 \fs17 storing}{\b0 \fs17
data}{\b0 \fs17 on}{\b0 \fs17 the }
i566 {\i Ans.}{\b0 \fs17
floppy}{\b0 \fs17 disk }
0 12.66{\b0 \fs17
A}{\b0 \fs17 read/write}{\b0 \fs17
memory}{\b0 \fs17
could}{\b0 \fs17 be}{\b0 \fs17 a}{\b0 \fs17
(RAM,}{\b0 \
fs17 ROM). }\par
}
floppy disk, RAM) is magnetic. \par
}
s16 \cf0 Ans.{\b0\i0 \fs17
RAM }\par
}
cf0 12.67{\b0 \fs17
0 \fs17 This}{\b0 \fs17 semiconductor}{\b0 \fs17 memory}{\b0 \fs17 has}{\
b0 \fs17 the}{\b0 \fs17 read/write}{\b0 \fs17
capabilities}{\b0 \fs17
of}{\b0 \fs17 a}{\b0 \fs17 RAM}{\b0 \fs17 with}{\b0 \fs17
the }
i590 {\b0 \fs17 nonvolatile}{\b0 \fs17 characteristics}{\b0 \fs17 of}{\b0 \fs
17 a}{\b0 \fs17 ROM.}{\i
Ans.}{\b0 \fs17
NVRAM }\par
}
cf0 12.68{\b0 \fs17
The}{\b0 \fs17 RAM}{\b0 \fs17 is}{\b0 \fs17 a }
i590 {\b0 \fs17 the}{\b0 \fs17 power. }\par
}
f0 12.69{\b0 \fs17
The }\par
}
cf0 ( a ) \par
}
nonvolatile, volatile) memory that \par
}
\cf0 ( b ){\i0 \fs17
(can,}{\i0 \fs17 cannot)}{\i0 \fs17 be}{\i0 \fs17
erased}{\i0 \fs17 by}{\i0 \fs17 turning}{\i0 \fs17 off }\par
}

\f20 \fs16 \cf0 Ans.{\b0 \f10 \fs14
(a)}{\b0\i0 \fs17
volatile}{\b0 \f10
\fs16
(6)}{\b0\i0 \fs17
can }
\cf0 {\b0\i0 \fs17 (dynamic,}{\b0\i0 \fs17 static)}{\b0\i0 \fs17 RAM}{\b0\i0
\fs17 uses}{\b0\i0 \fs17 a}{\b0\i0 \fs17 memory}{\b0\i0 \fs17 cell}{\b0\i0
\fs17 similar}{\b0\i0 \fs17 to}{\b0\i0 \fs17 a}{\b0\i0 \fs17 flip-flop. }
\par
}
cf0 12.70{\b0 \fs17
0 \fs17 The}{\b0 \fs17 system}{\b0 \fs17 is}{\b0 \fs17 said}{\b0 \fs17
to}{\b0 \fs17 have }
0 12.71{\b0 \fs17
A}{\b0 256}{\b0 \f10 \fs13 X}{\b0 4}{\b0 \fs17 memory
}{\b0 \fs17 would}{\b0 \fs17 contain}{\b0\i \f10 \fs14
(}{\b0\i \f10 \f
s14 a}{\b0\i \f10 \fs14 )}{\b0 \fs17
words,}{\b0 \fs17 each }
i594 {\b0 \fs17 bits.}{\i
Ans.}{\i \fs16
(}{\i \fs16 a}{\i \fs16
)}{\b0
256}{\b0\i \fs16
(b)}{\b0
4}{\b0\i \fs17
(c)}{\b0
1024
}\par
}
cf0 12.72{\b0 \fs17
Entering}{\b0 \fs17 data}{\b0 \fs17 in}{\b0 \fs17
a}{\b0 \fs17 RAM}{\fs17 is}{\b0 \fs17 the }\par
}
cf0 12.73{\b0 \fs17
The }
i589 {\b0 \fs17 location. }
0 12.74{\b0 \fs17
A }\par
}
lK, 8K){\fs17 of}{\fs17 memory, }\par
}
cf0 ( b ) \par
}
s16 \cf0 Ans.{\b0\i0 \fs17
static }
\cf0 Ans.{\b0\i0
1K}{\b0\i0 (1024}{\b0\i0 \fs17 bytes) }\par
}
its long, for a total capacity of \par
}
16 \cf0 ( c ) \par
}
read, write) operation. \par
}
16 \cf0 Ans.{\b0\i0 \fs17
write }\par
}
\cf0 (read, write) mode{\fs17 of} operation{\fs16 of} a RAM means r
evealing the contents of a memory
40 {\b\i \fs16 Ans.}

read
(RAM, ROM) can be repeatedly programmed by the user.{\b\i \fs16
Ans.}
RAM \par
}
cf0 12.75{\fs17
A}{\b0 \fs17 ROM}{\b0 \fs17 is}{\b0 \fs17 a }\par
}
cf0 12.76
A \par
}
permanent, temporary) memory. \par
}
s16 \cf0 Ans.{\b0\i0 \fs17
permanent }\par
}
(RAM, ROM) is programmed by the manufacturer to the user's specifications
. \par
}
\f20 \fs16 \cf0 Ans.{\b0\i0 \fs17
ROM }
\cf0 {\i0 12.77}{\b0\i0 \fs17
Refer}{\b0\i0 \fs17 to}{\b0\i0 \fs17 Fig.
}{\b0\i0 12-7b.}{\b0\i0 \fs17 What}{\b0\i0 \fs17 is}{\b0\i0 \fs17 the}{\b0
\i0 \fs17 function}{\b0\i0 \fs17 of}{\b0\i0 \fs17 this}{\b0\i0 \fs17 simp
le}{\b0\i0 \fs17 diode}{\b0\i0 \fs17 ROM? }
0 \fi569 Ans.{\b0\i0 \fs17
decimal-to-Gray}{\b0\i0 \fs17
code}{\b0\i0 \
fs17 decoder }
\cf0 {\i0 12.78}{\b0\i0 \fs17
Refer}{\b0\i0 \fs17 to}{\b0\i0 \fs17 Fig.}
{\b0\i0 12-7b.}{\b0\i0 \fs17 List}{\b0\i0 \fs17 the}{\b0\i0 \fs17 state}{\
b0\i0 \fs17 of}{\b0\i0 \fs17 the}{\b0\i0 \fs17 outputs}{\b0\i0 \fs17 for}
{\b0\i0 \fs17 each}{\b0\i0 \fs17 decimal}{\b0\i0 \fs17 input}{\b0\i0 (0-9
). }
0 \fi571 Ans.{\b0\i0 \fs17
See}{\b0\i0 \fs17 the}{\b0\i0 \fs17 table}{\b
0\i0 \fs17 in}{\b0\i0 \fs17 Fig.}{\b0\i0 12-7a. }
\cf0 {\i0 12.79}{\b0\i0 \fs17
Refer}{\b0\i0 \fs17 to}{\b0\i0 \fs17 Fig.
}{\b0\i0 12-7b.}{\b0\i0 \fs17 Which}{\b0\i0 \fs17 diode(s)}{\b0\i0 \fs17 a
re}{\b0\i0 \fs17 forward-biased}{\b0\i0 \fs17 when}{\b0\i0 \fs17 the}{\b0\i
0 \fs17 input}{\b0\i0 \fs17 switch}{\b0\i0 \fs17 is}{\b0\i0 \fs17 at}{\b0
\i0 \fs17 decimal}{\b0\i0 2? }
0 \fi569 Ans.{\b0\i0 \fs17
two}{\b0\i0 \fs17 diodes}{\b0\i0 \fs17 in}{\b0
\i0 \fs17 columns}{\fs17 A}{\b0\i0 \fs17 and}{\fs17 B}{\b0\i0 \fs18 in
}{\b0\i0 \fs17 row}{\b0\i0 2}{\b0\i0 \fs17 in}{\b0\i0 \fs17 Fig.}{\b0\i0
12-7b. }
\cf0 \fi22 {\i0 12.80}{\b0\i0 \fs17
Larger-capacity}{\b0\i0 \fs17 ROMs}{\
b0\i0 \fs17 (such}{\b0\i0 \fs17 as}{\b0\i0 512K}{\b0\i0 \f10 \fs13 X}{\b0
\i0 8}{\b0\i0 \fs17 ROMs)}{\b0\i0 \fs17 use}{\b0\i0 \fs17
(bipolar,}{\b0\i0 \fs17
CMOS)}{\b0\i0 \fs17 technology}{\b0\i0 \fs17 i
n}{\b0\i0 \fs17 their }\par
}
\cf0 manufacture.{\b\i \fs16
Am.}{\fs16
CMOS }

{\b \fs16 12.81}
A{\fs16 131072}{\f10 \fs13 X} 8 ROM would have a total
capacity of \par
}
its \par
}
1048576 }\par
}
. 121 \par
}
}
f0 307 \par
}
cf0 12.82{\f10 \fs15
A}{\b0 65536}{\b0 \f10 \fs18 x}{\b0 8}{\b0 ROM}{
\b0 would}{\b0 need }\par
}
8, 16){\fs17 address}{\fs17 line}{\fs17 pins}{\fs17 on}{\fs17 the}{\fs1
7 IC. }\par
}
cf0 12.83{\b0
What}{\b0 is}{\b0 a}{\b0 computer}{\b0 program}{\b0
called}{\b0 when}{\b0 it}{\b0 is}{\b0 permanently}{\b0 stored}{\b0 in
}{\b0 a}{\b0 ROM? }\par
}
16}{\i0 \fs16 (216}{\b0\i0 \f10 \fs13 =}{\b0 \fs17
65}{\i0 \fs17 536) }
\cf0 \fi86 Ans.{\b0\i0
firmware }\par
}
\cf0 12.84{\b0
In}{\b0 a}{\b0 general-purpose}{\b0 microcomputer,}{\b0
a}{\b0 greater}{\b0 proportion}{\b0 of}{\b0 internal}{\b0 memory}{\b0
is}{\b0 probably}{\b0 allocated}{\b0 to }
fi583 {\b0 (RAM,}{\b0 ROM).}{\i
Ans.}{\b0
RAM }
f0 12.85{\b0
In}{\b0 a}{\b0 dedicated}{\b0
computer,}{\b0 a}{\b0
greater}{\b0 proportion}{\b0 \fs16
of}{\b0
internal}{\b0
memory}{\b0
is}{\b0 probably}{\b0
allocated}{\b0 to }
fi583 {\b0 (RAM,}{\b0 ROM).}{\i
Ans.}{\b0
ROM }
f0 12.86{\b0
The}{\b0 letters}{\b0 EEPROM}{\b0 stand}{\b0 for}{\b0 \
f10 \fs19
. }\par
}
f20 \fs17 \cf0 Ans.{\b0\i0
electrically}{\b0\i0 erasable}{\b0\i0 program
mable}{\b0\i0 read-only}{\b0\i0 memory }
cf0 {\i0 12.87}{\b0\i0

A}{\b0\i0 mask-programmable}{\b0\i0 read-only}{\b0
\i0 memory}{\b0\i0 is}{\b0\i0 commonly}{\b0\i0 called}{\b0\i0 a(n) }\pa
r
}
cf0 12.88{\b0
Refer}{\b0\i \fs17 to}{\b0 Fig.}{\b0 12-12.}{\b0 This}
{\b0 is}{\b0 an}{\b0 example}{\b0 of}{\b0 a(n) }\par
}
par
}
EPROM, PROM). \par
}
ROM }
\cf0 Ans.{\b0\i0
PROM }\par
}
cf0 12.89{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 12-12b.}{\f10 \fs15 A}{\b0
good}{\b0 fuse}{\b0 (see}{\b0 row}{\b0 \fs17 0,}{\b0 column}{\b0\i \fs17
D}{\b0\i \fs17 )}{\b0 in}{\b0 the}{\b0 PROM}{\b0 means}{\b0 that}{\b0
the}{\b0 memory}{\b0 cell}{\b0 stores }
i590 {\b0 a}{\b0 logical}{\b0 \fs17
(0,}{\b0 1).}{\i
Ans.}{\b0 \fs16
1 }\par
}
cf0 12.90{\b0
Refer}{\b0 to}{\fs16 Fig.}{\b0 12-11.}{\b0 This}{\b0
IC}{\b0 is}{\b0 a(n) }
i563 {\i Ans.}{\b0
EPROM}{\b0 (ultraviolet-erasable}{\b0 PROM) }\par
}
cf0 12.91
An{\b0 EPROM} is{\b0 considered}{\b0 a }\par
}
\cf0 (EPROM, ROM).
(nonvolatile, volatile) memory device. \par
}
nonvolatile }\par
}
cf0 12.92{\b0
The}{\b0 abbreviation}{\b0 E2PROM}{\b0 stands}{\b0 for }
\par
}
par
}
electrically}{\b0\i0 erasable}{\b0\i0 programmable
}{\b0\i0 read-only}{\b0\i0 memory}{\b0\i0 (same}{\b0\i0 as}{\b0\i0 EEP
ROM) }\par
}
cf0 12.93{\b0
EPROMs}{\b0 are}{\b0 programmed}{\b0 in}{\b0 the}{\b0
(factory,}{\b0 local}{\b0 lab). }

0 12.94{\b0
What}{\b0 \fs16 is}{\b0 the}{\b0 equipment}{\b0 that}{\b
0 is}{\b0 used}{\b0 to}{\b0 program}{\b0 EPROMs}{\b0 called? }\par
}
cf0 12.95{\b0
The}{\b0 letters}{\b0 SRAM}{\b0 stand}{\b0 for }
0 12.96{\b0
The}{\b0 letters}{\b0 RWM}{\b0 stand}{\b0 for }\par
}
par
}
local}{\b0\i0 lab }
\cf0 \fi240 Ans.{\b0\i0
PROM}{\b0\i0 burner }\par
}
static}{\b0\i0 random-access}{\b0\i0 memory}{\b0\i0
(static}{\b0\i0 \fs17 RAM) }\par
}
hen dealing with semiconductor memories. \par
}
f20 \fs17 \cf0 Ans.{\b0\i0
read/write}{\b0\i0
memory}{\b0\i0 (same}{\b
0\i0 as}{\b0\i0 RAM) }
cf0 {\i0 12.97}{\b0\i0
A}{\b0\i0 RWM}{\b0\i0 is}{\b0\i0 more}{\b0\i0
commonly}{\b0\i0 referred}{\b0\i0 to}{\b0\i0 as}{\b0\i0 a(n) }\par
}
cf0 12.98{\b0
Magnetic }\par
}
par
}
RAM }\par
}
disks, tapes) are random-access devices and have a short access time. \p
ar
}
17 \cf0 Ans.{\b0\i0
disks }\par
}
\cf0 12.99{\b0
To}{\b0 retrieve}{\b0 data}{\b0 from}{\b0 a}{\b0 fl
oppy}{\b0 disk}{\b0 is}{\b0 called }\par
}
\par
}
reading }\par
}
\cf0 12.100{\b0 "Winchester"}{\b0 is}{\b0 another}{\b0 name}{\b0 for}{
\b0 what}{\b0 magnetic}{\b0 storage}{\b0 device? }\par
}
\cf0 12.101{\b0 The}{\b0 74F189}{\b0 RAM}{\b0 IC}{\b0 is}{\b0 from}{
\b0 the}{\b0 newer }\par
}
performance and efficiency. \par
}
hard}{\b0\i0 disk}{\b0\i0 drive }\par
}
subfamily that exhibits an outstanding combination of \par
}
Fairchild}{\b0\i0 advanced}{\b0\i0 Schottky}{\b0\
i0 TTL,}{\b0\i0 FAST }\par
}
\cf0 12.102 A{\b0 short}{\b0 access}{\b0 time}{\b0 for}{\b0 a}{\b0
RAM,}{\b0 ROM,}{\b0 or}{\b0 PROM}{\b0 means}{\b0 it}{\b0 is }
fi568 {\i Ans.}{\b0
faster}{\b0 (A}{\b0 faster}{\b0 chip}{\b0 can}{\b
0 be}{\b0 used}{\b0 in}{\b0 higher-frequency}{\b0 circuits.) }\par
}
\cf0 12.103{\b0 Semiconductor}{\b0 memory}{\b0 ICs}{\b0 manufactured}{\b0
using}{\b0 the }
fi588 {\b0 fastest}{\b0 chips.}{\i
Ans.}{\b0
GaAs}{\b0 (gallium}
{\b0 arsenide) }\par
}
(faster, slower). \par
}
(CMOS, GaAs) process technology are the \par
}
\cf0 12.104{\b0 Refer}{\b0 \fs16 to}{\b0 Fig.}{\b0 12-9.}{\b0 The}{\b0
TMS47256}{\b0 32K}{\b0 \f10 \fs13 X}{\b0 \fs17 8}{\b0 ROM}{\b0 IC}{\b
0 would}{\b0 have }
fi583 {\b0 data}{\b0 outputs.}{\i
Ans.}{\b0
15}{\i (}{\i A}{\i
o}{\b0 to}{\i A,,),}{\b0 8}{\b0\i \fs18 (Q,}{\b0 to}{\i\dn006 \fs10
Q
}{\i\dn006 \fs10 8}{\i\dn006 \fs10 ) }\par
}
address inputs and \par
}
0 308 \par
}
}
f0 [CHAP.{\i0 \fs17 12 }\par
}
cf0 12.105{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 flash}{\b0 \f20 \fs17 EPROM}{\
b0 \f20 \fs17 is}{\b0 \f20 \fs17 very}{\b0 \f20 \fs17 similar}{\b0 \f20 \fs
17 to}{\b0 \f20 \fs17 the }
0 12.106{\b0 \f20 \fs17
The}{\b0 \f20 \fs17 letters}{\b0 \f20 \fs17 NVSRA
M}{\b0 \f20 \fs17 stands}{\b0 \f20 \fs17 for }\par
}
EEPROM, NOVRAM). \par
}
EEPROM }\par
}
par
}
f20 \fs17 \cf0 Ans.{\b0\i0
nonvolatile}{\b0\i0 static}{\b0\i0 random-acces
s}{\b0\i0 memory,}{\b0\i0 or}{\b0\i0 nonvolatile}{\b0\i0 static}{\b0\i0 RA
M }
cf0 {\i0 \f10 \fs15 12.107}{\b0\i0
Refer}{\b0\i0 to}{\b0\i0 Fig.}{\b0\i0
12-15.}{\b0\i0 The}{\b0\i0 STK10C68}{\b0\i0 NVSRAM}{\b0\i0 has}{\i0 \fs1
7 64K}{\b0\i0 bits}{\b0\i0 of}{\b0\i0 memory}{\b0\i0 organized}{\b0\i0
with }
\fi590 {\b0\i0 each}{\b0\i0
-bits}{\b0\i0 wide.}
Ans.{
\b0\i0
8K}{\b0\i0 (8192}{\b0\i0 words),}{\b0\i0 8 }\par
}
cf0 12.108{\b0 \f20 \fs17
\b0 \f20 \fs17 12-15.The}{\b0 \f20 \fs17 STK10C68}{\b0 \f20 \fs17 IC}{\b0 \f
20 \fs17 is}{\b0 \f20 \fs17 considered}{\b0 \f20 \fs17 a }
i566 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
nonvolatile}{\b0 \f20 \fs17 (does
}{\b0 \f20 \fs17 not}{\b0 \f20 \fs17 lose}{\b0 \f20 \fs17 data}{\b0 \f20 \f
s17 on}{\b0 \f20 \fs17 loss}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 power) }\p
ar
}
{\phpg\posx9229\pvpg\posy2439\absw497\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 wo
rds \par
}
nonvolatile, volatile) memory unit. \par
}
\cf0 12.109{\b0 \f20 \fs17
\b0 \f20 \fs17 12-17.Disk}{\b0 \f20 \fs17 drives}{\b0 \f20 \fs17 that}{\b0 \
f20 \fs17 use}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 3.5-in}{\b0 \f20 \fs17 f
loppy}{\b0 \f20 \fs17 disk}{\b0 \f20 \fs17 most}{\b0 \f20 \fs17 often}{\b0 \f
20 \fs17 read}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 wri
te}{\b0 \f20 \fs17 to }
fi590 {\b0 \f20 \fs17 (both}{\b0 \f20 \fs17 sides,}{\b0 \f20 \fs17 one}{\b0 \
f20 \fs17 side)}{\b0 \f20 \fs17 of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 mem
ory}{\b0 \f20 \fs17 disk.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
both
}
f0 12.110{\b0 \f20 \fs17 Refer}{\b0 \f20 \fs17 to}{\b0 \f20 \fs17 Fig.}{\b0
\f20 \fs17 12-17.}{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 3.5-in}{\b0 \f20 \fs17
floppy}{\b0 \f20 \fs17 disk}{\b0 \f20 \fs17 is}{\i \f20 \fs16 write-prot
ected}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 can}{\b0 \f20 \fs17 only}{\b0 \f
20 \fs17 be}{\b0 \f20 \fs17 read}{\b0 \f20 \fs17 from}{\b0 \f20 \fs17 when
}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 hole}{\b0 \f20 \fs17 in }
fi595 {\b0 \f20 \fs17 the}{\b0 \f20 \fs17 write-protect}{\b0 \f20 \fs17 slot}
{\b0 \f20 \fs17 is}{\b0 \f20 \fs17
(closed,}{\b0 \f20 \fs17
open). }
fi566 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
open}{\b0 \f20 \fs17 (This}{\b0
\f20 \fs17 is}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 opposite}{\b0 \f20 \fs17
of}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 5.25-in}{\b0 \f20 \fs17 disk}{\b0 \
f20 \fs17 in}{\b0 \f20 \fs17 Fig.}{\b0 \f20 \fs17 12-16a.) }
f0 12.111{\b0 \f20 \fs17 The}{\b0 \f20 \fs17
(floppy,}{\b0
\f20 \fs17 hard)}{\b0 \f20 \fs17 disk}{\b0 \f20 \fs17 has}{\b0 \f20 \fs17
the}{\b0 \f20 \fs17 advantage}{\b0 \f20 \fs17 over}{\b0 \f20 \fs17 the}{\b0
\f20 \fs17 other}{\b0 \f20 \fs17 in}{\b0 \f20 \fs17 that}{\b0 \f20 \fs17
it}{\b0 \f20 \fs17 can}{\b0 \f20 \fs17 store}{\b0 \f20 \fs17 more}{\b0 \
f20 \fs17 data}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 can }
fi597 {\b0 \f20 \fs17 access}{\b0 \f20 \fs17 the}{\b0 \f20 \fs17 information}
{\b0 \f20 \fs17 faster.}{\i \f20 \fs17
Ans.}{\b0 \f20 \fs17
hard
}
f0 12.112{\b0 \f20 \fs17 The}{\b0 \f20 \fs17 3.5-in}{\b0 \f20 \fs17
(magnetic}{\b0 \f20 \fs17 floppy,}{\b0 \f20 \fs17 rewritable}{\b
0 \f20 \fs17 magneto-optical)}{\b0 \f20 \fs17 disk}{\b0 \f20 \fs17 has}{\b
0 \f20 \fs17 a}{\b0 \f20 \fs17 storage}{\b0 \f20 \fs17 capacity}{\b0 \f20
\fs17 of}{\b0 \f20 \fs17 about }
fi606 {\b0 \f20 \fs17 128M}{\b0 \f20 \fs17 bytes}{\b0 \f20 \fs17 and}{\b0 \f2
0 \fs17 uses}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17 laser}{\b0 \f20 \fs17 diod
e}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 coil}{\b0 \f20 \fs17 of}{\b0 \f20 \fs
17 wire}{\b0 \f20 \fs17 for}{\b0 \f20 \fs17 erasing,}{\b0 \f20 \fs17 readin
g,}{\b0 \f20 \fs17 and}{\b0 \f20 \fs17 writing. }
fi570 {\i \f20 \fs17 Ans.}{\b0 \f20 \fs17
rewritable}{\b0 \f20 \fs17 magn
eto-optical }\par
}
{\b \fs32 Other}{\b \fs32 Devicesand}{\b \fs32 Techniques }\par
}
\cf0 13-1 INTRODUCTION
fi366 {\b0 In}{\b0 examining}{\b0 manufacturers'}{\b0 TTL,}{\b0 \fs18 CM
OS,}{\b0 and}{\b0 memory}{\b0 data}{\b0 manuals,}{\b0 you}{\b0 would}
{\b0 find}{\b0 several }
\b0 types}{\b0 of}{\b0 \fs19 ICs}{\b0 that}{\b0 have}{\b0 not}{\b0 b
een}{\b0 investigated}{\b0 in}{\b0 the}{\b0 first}{\b0\i \fs18 12}{\b0
chapters}{\b0 of}{\b0 this}{\b0 book.}{\b0 This}{\b0 will}{\b0 be}
{\b0 a }

\b0 "catchall"}{\b0 chapter}{\b0 \fs18 to}{\b0 include}{\b0 devices}{\b0 an
d}{\b0 techniques}{\b0 that}{\b0 do}{\b0 not}{\b0 fit}{\b0 neatly}{\b0 i
nto}{\b0 other}{\b0 chapters}{\b0 but}{\b0 are }
\b0 topics}{\b0
that}{\b0
are}{\b0
included}{\b0
in}{\b0
many}{\b
0
of}{\b0
the}{\b0
standard}{\b0
textbooks}{\b0
in}{\b0
the}{\
b0
field.}{\b0
Included}{\b0
will}{\fs18
be }
\b0 multiplexers/data}{\b0
selectors}{\b0 and}{\b0 multiplexing,}{\b0 demu
ltiplexers,}{\b0 an}{\b0 introduction}{\b0 to}{\b0 digital}{\b0 data}{\b0
transmis- }
\b0 sion,}{\b0 latches}{\b0
and}{\b0 three-state}{\b0
buffers,}{\b0
programmable}{\b0
logic}{\b0 devices,}{\b0 magnitude}{\b0
comparators,
}{\b0 and }
\b0 Schmitt}{\b0 trigger}{\b0 devices. }\par
}
\cf0 13-2 DATA SELECTOR/ MULTIPLEXERS
fi358 {\fs18 A}{\b0\i \fs18
data}{\b0\i \fs18 selector}{\b0
is}{\b0 th
e}{\b0 electronic}{\b0 version}{\b0 of}{\b0
a}{\b0 one-way}{\b0 rot
ary}{\b0 switch.}{\b0 Figure}{\b0\i \fs18 13-1}{\b0 shows}{\b0 a }
\b0 single-pole,}{\b0 eight-position}{\b0 rotary}{\b0 switch}{\b0 on}{\b0 t
he}{\b0 left.}{\b0 The}{\b0 eight}{\b0 inputs}{\b0\i \fs18 (0-7)}{\b0 are}
{\b0 shown}{\b0 on}{\b0 the}{\b0 left,}{\b0 and}{\b0 a }
\b0 single}{\b0 output}{\b0 on}{\b0 the}{\b0 right}{\b0 is}{\b0 labeled}{
\i \f30 \fs20 Y.}A{\b0 data}{\b0 selector}{\b0 is}{\b0 shown}{\b0 on}{\b0
the}{\b0 right.}{\b0 The}{\b0 data}{\b0 at}{\b0 input}{\fs18 2}{\b0 (a
}
\b0 logical}{\b0 1)}{\b0 is}{\b0 being}{\b0 transferred}{\b0 through}{\b0
the}{\b0 contacts}{\b0 of}{\b0 the}{\b0 rotary}{\b0 switch.}{\b0 Similar
ly,}{\b0 the}{\b0 data}{\b0 at}{\b0 input}{\fs18 2 }
\b0 (a}{\b0 logical}{\b0 1)}{\b0 is}{\b0 being}{\b0 transferred}{\b0
through}{\b0 the}{\b0 circuitry}{\b0 of}{\b0 the}{\b0 data}{\b0 sele
ctor}{\b0 on}{\b0 the}{\b0 right.}{\b0 The}{\b0 data }
\b0 position}{\b0 is}{\b0 selected}{\b0 by}{\b0 mechanically}{\b0 turn
ing}{\b0 the}{\b0 rotor}{\b0 on}{\b0 the}{\b0 rotary}{\b0 switch.}{\
b0 The}{\b0 data}{\b0 position}{\b0 is }
\b0 selected}{\b0 in}{\b0 the}{\b0 data}{\b0 selector}{\b0 by}{\b0 placing
}{\b0 the}{\b0 proper}{\b0 binary}{\b0 number}{\b0 on}{\b0 the}{\b0 dataselect}{\b0 inputs}{\i \fs19 (C,}{\i \fs18 B,}{\i \fs18 A). }
\b0 The}{\b0 data}{\b0 selector}{\b0 permits}{\b0 data}{\b0 to}{\b0 f
low}{\b0 only}{\b0 from}{\b0 input}{\b0 to}{\b0 output,}{\b0 whereas}{\b
0 the}{\b0 rotary}{\b0 switch}{\b0 allows }
\b0 data}{\b0 to}{\b0 flow}{\b0 in}{\b0 both}{\b0 directions.} A{\b0 data}
{\b0 selector}{\b0 can}{\b0 be}{\b0 thought}{\b0 of}{\b0 as}{\b0 being}{\
b0 similar}{\b0 to}{\b0 a}{\b0 one-way}{\b0 rotary }
\b0 switch. }\par
}
puts \par
}
puts \par
}
cf0 0 \par
}
\cf0 5 \par
}
\fs15 3 }
{\b \f10 \fs13 4 }\par
}
cf0 / \par
}
\cf0 0 \par
}
tput \par
}
\par
}
tput
fi180 {\b\i \fs15 Y }
2 {\b \f10 \fs13 : }\par
}
cf0 1 \par
}
\cf0 1 \par
}
\cf0 1 \par
}
{\phpg\posx4303\pvpg\posy10478\absw119\absh329 \f10 \fs27 \cf0 \f10 \fs27 \cf0 \
\ \par
}
' I \par
}
0 \fs13 \cf0 7
cf0 {\b0 \f20 \fs15 Mechanical}{\b0 \f20 \fs15 data}{\b0 \f20 \fs15 selector
}\par
}

\cf0 Fig.{\fs16 13-1}{\b0 \fs17
Comparison}{\b0 \fs17 of}{\b0 \fs17 a}{\
b0 \fs17 rotary}{\b0 \fs17 switch}{\b0 \fs17 and}{\b0 \fs17 a}{\b0 \fs17 da
ta}{\b0 \fs17 selector }\par
}
0 \fs18 \cf0 A{\b0 commercial}{\b0 data}{\b0 selector}{\b0 is}{\b0 sho
wn}{\b0 in}{\b0 block-diagram}{\b0 form}{\b0 in}{\b0 Fig.}{\b0\i \fs18
13-2a.}{\b0 This}{\b0 TTL}{\fs19 IC}{\b0 is }
{\b0 identified}{\b0 as}{\b0 a}{\b0\i \fs18 74150}{\b0\i \fs18 16-input}{\b
0\i \fs18 data}{\b0\i \fs18 selector}{\b0\i \fs18 /multiplexer} by{\b0 the}
{\b0 manufacturers.}{\b0 Note}{\b0 the}{\b0\i \fs18 16}{\b0 data}{\b0 inpu
ts }
{\b0 at}{\b0 the}{\b0 top}{\b0 left.}{\b0 The}{\b0\i \fs18 74150}{\b0 has}
{\b0 a}{\b0 single}{\b0 inverted}{\b0 output}{\b0 labeled}{\b0\i W.}{\b0
Four}{\b0 data-select}{\b0 inputs}{\i \f30 \fs21 (D, }
\fi8127 {\i \fs18 C,}{\i \fs19 B,}{\i \fs18 A}{\i \fs18 ) }
{\b0 are}{\b0 identified}{\b0 at}{\b0 the}{\b0 lower}{\b0 left}{\b0 in}{\
b0 Fig.}{\b0\i \fs18 13-2a.} A{\b0 \fs18 LOW}{\b0 at}{\b0 the}{\b0 strobe}
{\b0 input}{\b0 will}{\b0 enable}{\b0 the}{\b0 data}{\b0 selector }
{\b0 and}{\b0 can}{\b0 be}{\b0 thought}{\b0 of}{\b0 as}{\b0 a}{\b0 main}
{\b0 \fs18 on-off}{\b0 switch. }
\fi4281 {\b0\i \fs18 309 }\par
}
\cf0 I{\b0 \f10 \fs18 o+$ }
f0 {\f30 \fs16 0 }\par
}
Electronic data selector \par
}
I \par
}
\cf0 (a){\f30 \fs16 Block}{\fs15 logic}{\fs15 symbol }\par
}
\par
}
cf0 OTHER DEVICES AND TECHNIQUES \par
}
f0 [CHAP.{\b0 \fs16 13 }\par
}
\fs17 \cf0 Inputs
0 Select
0 {\i \fs16 C}{\i \fs16

B}{\i \fs16
A }\par
}
fs15 \cf0 selector/
\par}{\phpg\posx3119\pvpg\posy2281\absw930\absh329 \sl-170 \b \f20 \fs15 \cf0 mu
ltiplexer \par
}
16 \cf0 D \par
}
cf0 output \par
}
\cf0 x x x x
{\fs17 L}{\fs17
L}{\fs17
L}{\fs17
L }
{\fs17 L}{\fs17
L}{\fs17
L}{\fs17
H }
{\fs17 L}{\fs17
L}{\fs17
H}{\fs17
L }
{\fs17 L}{\fs17
L}{\fs17
H}{\fs17
H }
{\fs17 L}{\fs17
H}{\fs17
L}{\fs17
L }
{\fs17 L}{\fs17
H}{\fs17
L}{\fs17
H }
\fi21 {\fs17 L}{\fs17
H}{\fs17
H}{\fs17
L }
\fi21 {\fs17 L}{\fs17
H}{\fs17
H}{\fs17
H }
\fi23 {\fs17 H}{\fs17
L}{\fs17
L}{\fs17
L }
\fi27 {\fs17 H}{\fs17
L}{\fs17
L}{\fs17
H }
\fi27 {\fs17 H}{\fs17
L}{\fs17
H}{\fs17
L }
\fi31 {\fs17 H}{\fs17
L}{\fs17
H}{\fs17
H }
\fi35 {\fs17 H}{\fs17
H}{\fs17
L}{\fs17
L }
\fi35 {\fs17 H}{\fs17
H}{\fs17
L}{\fs17
H }
\fi37 {\fs17 H}{\fs17
H}{\fs17
H}{\fs17
L }
\fi37 {\fs17 H}{\fs17
H}{\fs17
H}{\fs17
H }\par
}
0 j: \par
}
\fs12 \cf0 I
f0 \fi61 {\b\i0 \f30 \fs12 9 }
\b\i0 \f10 \fs11 10 }
\b\i0 \fs13 I}{\b\i0 \fs13 t }
\i0 \f10 \fs11 12 }

\b\i0 \f30 \fs12 13 }
\b\i0 \f10 \fs11 14 }
\i0 \f10 \fs11 I}{\i0 \f10 \fs11 S }\par
}
cf0 Strobe \par
}
13 \cf0 Vcc{\b0\i0 \f10
'}{\i0 \f30 \fs15 8 }\par
}
fs15 \cf0 Data
fs15 inputs }\par
}
cf0 (74150) \par
}
cf0 Enable \par
}
fs15 \cf0 select
puts \par
}
17 \cf0 D \par
}
\cf0 Strobe
f0 \fi200 {\i \fs16 S }
f0 \fi193 {\fs17 H }
fi206 {\fs17 L }
fi206 {\fs17 L }
fi208 {\fs17 L }
fi208 {\fs17 L }
fi208 {\fs17 L }
fi207 {\fs17 L }
fi211 {\fs17 L }
fi215 {\fs17 L }
fi219 {\fs17 L }
fi221 {\fs17 L }
fi221 {\fs17 L }
fi221 {\fs17 L }
fi227 {\fs17 L }
fi227 {\fs17 L }
fi229 {\fs17 L }
fi229 {\fs17 L }\par
}
cf0 output
0 \fi216 {\i \fs16 W }\par
}
\fs17 \cf0 H
fi30 {\b0 \f10 \fs15 - }
fi30 {\b0 \f10 \fs15 - }
fi37 {\fs17 E0 }
fi30 {\b0 \f10 \fs15 - }
fi37 {\fs17 El }
fi30 {\b0 \f10 \fs15 - }
fi41 {\fs17 E2 }
fi35 {\b0 \f10 \fs15 - }
fi41 {\fs17 E3 }
fi35 {\b0 \f10 \fs15 - }
fi43 {\fs17 E4 }
f0 \fi37 {\b0 \f10 \fs11 - }
fi43 {\i \f30 \fs18 E5 }
fi41 {\b0 \f10 \fs15 - }
fi50 {\i \fs16 E6 }
fi41 {\b0 \f10 \fs15 - }
fi51 {\fs17 E8 }
\b0 \f10 \fs15 - }\par
}
f20 \fs17 \cf0 E7
\cf0 \fi43 {\b0\i0 \f10 \fs11 - }

\fi55 {\i0 \fs17 E9 }
{\b0\i0 \f10 \fs15 - }
{\i0 \fs17 El}{\i0 \fs16 1 }
{\b0\i0 \f10 \fs15 - }\par
}
\cf0 E{\fs17 10 }
\b0 \f10 \fs15 - }
\par}{\phpg\posx8433\pvpg\posy5135\absw364\absh1172 \sl-172 \b \f20 \fs17 \cf0 E
12
13
\b0 \f10 \fs15 - }
14
15 \par
}
cf0 Data inputs
i143 {\f30 \fs15 1}{\f30 \fs15 1}{\f30 \fs16
12 }\par
}
s15 \cf0 (b){\i0 \fs15 Truth}{\i0 \fs15 table}{\i0 \fs14 (Courtesy}{\i0 \f10
\fs13 of}{\fs15 Texas}{\i0 \fs14 Instruments,}{\i0 \fs14 Inc.) }
\cf0 \fi980 {\i0 \fs15 Data-select }
\fi152 {\i0 \f30 \fs16 14}{\i0 \f30 \fs15 15'}{\f10 \fs14
A}{\fs16
B}{\f30 \fs17
C }\par
}
0 - \par
}
14 \cf0 W{\fs15
DI }\par
}
cf0 Y I \par
}
cf0 9 \par
}
cf0 10 \par
}
cf0 13 \par
}
15 \cf0 IE6 \par
}
s17 \cf0 E5{\i0 \fs16 E4} E3{\fs15 E2}{\i0 \fs17 El}{\fs15 E0 }\par
}
cf0 S \par
}
I I I I l l \par
}
\cf0 6{\f30 \fs15
5}{\f30 \fs15
4}{\f30 \fs16
3}{\f30 \fs15
2}{\f30
\fs15
1 }
fi611 {\fs15 Data}{\fs15 inputs }\par
}
cf0 7 \par
}
\cf0 0{\f20 \fs15 Strobe}{\b0\i \f20 \fs14
W}{\i \f20
D}{\f20 \fs15
GND }
fi662 {\f20 \fs15 Out-}{\f20 \fs15 Data- }
fi707 {\f20 \fs15 put}{\f20 \fs15
select }\par
}
i \f20 \fs14 \cf0 ( c ){\i0 \fs15 Pin}{\i0 \fs15 diagram} (Courtesy{\f30 \fs15
of}{\fs15 Texas} Instruments, Inc.)
0 \fi2249 {\i0 \fs16 Fig.}{\i0 \fs16 13-2}{\i0 \fs17
The}{\i0 \fs17 TTL}{\
i0 \fs17 74150}{\i0 \fs17 data}{\i0 \fs17 selector/multiplexer}{\i0 \fs17
IC }
\cf0 \fi363 {\b0\i0 \fs18 Consider}{\b0\i0 \fs18 the}{\b0\i0 \fs18 74150}{\b0
\i0 \fs18 data}{\b0\i0 \fs18 selector}{\b0\i0 \fs18 truth}{\b0\i0 \fs18 tabl
e}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0\i0 \fs18 13-2b.}{\b0\i0 \fs18 Lin
e}{\b0\i0 \fs18 1}{\b0\i0 \fs18 shows}{\b0\i0 \fs18 the}{\b0\i0 \fs18 strobe}
{\b0\i0 \fs18 (enable)}{\b0\i0 \fs18 input }
0 {\b0\i0 \fs19 HIGH,}{\b0\i0 \fs18 which}{\b0\i0 \fs18 disables}{\b0\i0 \fs
18 the}{\b0\i0 \fs18 entire}{\b0\i0 \fs18 unit.}{\b0\i0 \fs18 Line}{\b0\i0
\fs19 2}{\b0\i0 \fs18 shows}{\b0\i0 \fs18 all}{\b0\i0 \fs18 the}{\b0\i0
\fs18 data-select}{\b0\i0 \fs18 inputs}{\b0\i0 \fs18 LOW}{\b0\i0 \fs18 a
s}{\b0\i0 \fs18 well}{\b0\i0 \fs18 as}{\b0\i0 \fs18 the }
0 {\b0\i0 \fs18 strobe}{\b0\i0 \fs18 input}{\b0\i0 \fs18 being}{\b0\i0 \fs18
LOW.}{\b0\i0 \fs18 This}{\b0\i0 \fs18 enables}{\b0\i0 \fs18 the}{\b0\i0 \fs18
information}{\b0\i0 \fs18 at}{\b0\i0 \fs18 data}{\b0\i0 \fs18 input}{\b0\i0
\fs18 0}{\b0\i0 \fs18 to}{\b0\i0 \fs18 be}{\b0\i0 \fs18 transferred}{\b0\i0
\fs18 to}{\b0\i0 \fs18 output}{\b0 \fs18 W. }
0 {\b0\i0 \fs18 The}{\b0\i0 \fs18 data}{\b0\i0 \fs18 at}{\b0\i0 \fs18 output}
{\b0 \fs18 W}{\b0\i0 \fs18 will}{\b0\i0 \fs18 appear}{\b0\i0 \fs18 in}{\b0\
i0 \fs18 its}{\b0\i0 \fs18 inverted}{\b0\i0 \fs18 form,}{\b0\i0 \fs18 as}{\b
0\i0 \fs18 symbolized}{\b0\i0 \fs18 by}{\b0\i0 \fs18 the}{\b0\i0 \fs18
in}{\b0\i0 \fs18 the}{\b0\i0 \fs18 output}{\b0\i0 \fs18 column }
0 {\b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 truth}{\b0\i0 \fs18 table.
}{\i0 \fs18 As}{\b0\i0 \fs18 the}{\b0\i0 \fs18 binary}{\b0\i0 \fs18 count}{\
b0\i0 \fs18 increases}{\b0\i0 \fs18 (0001,}{\b0\i0 \fs18 0010,}{\b0\i0 \fs18
0011,}{\b0\i0 \fs18 and}{\b0\i0 \fs18 so}{\b0\i0 \fs18 forth)}{\b0\i0 \fs18

down}{\b0\i0 \fs18 the}{\b0\i0 \fs18 truth}{\b0\i0 \fs18 table, }
0 {\b0\i0 \fs18 each}{\b0\i0 \fs18 data}{\b0\i0 \fs18 input}{\b0\i0 \fs18 in}
{\b0\i0 \fs18 turn}{\i0 \fs18 is}{\b0\i0 \fs18 connected}{\b0\i0 \fs18 to}{
\b0\i0 \fs18 output}{\b0 \fs18 W}{\b0\i0 \fs18 of}{\b0\i0 \fs18 the}{\b0\i0
\fs18 data}{\b0\i0 \fs18 selector. }
0 \fi371 {\b0\i0 \fs18 The}{\b0\i0 \fs18 74150}{\b0\i0 \fs19 IC}{\b0\i0 \fs18
is}{\b0\i0 \fs18 packaged}{\b0\i0 \fs18 in}{\b0\i0 \fs18 a}{\b0\i0 \fs18 24
-pin}{\b0\i0 \fs18 package.}{\b0\i0 \fs18 The}{\b0\i0 \fs18 pin}{\b0\i0 \fs18
diagram}{\b0\i0 \fs18 for}{\b0\i0 \fs18 this}{\b0\i0 \fs18 IC}{\b0\i0 \fs18
is}{\b0\i0 \fs18 shown}{\b0\i0 \fs18 in}{\b0\i0 \fs18 Fig.}{\b0\i0 \fs18 1
3-2c. }
0 {\b0\i0 \fs18 Besides}{\b0\i0 \fs18 the}{\b0\i0 \fs18 21}{\b0\i0 \fs18 inpu
ts}{\b0\i0 \fs18 and}{\b0\i0 \fs18 one}{\b0\i0 \fs18 output}{\b0\i0 \fs18 sh
own}{\b0\i0 \fs18 on}{\b0\i0 \fs18 the}{\b0\i0 \fs18 block}{\b0\i0 \fs18 dia
gram,}{\b0\i0 \fs18 the}{\b0\i0 \fs18 pin}{\b0\i0 \fs18 diagram}{\b0\i0 \fs18
also}{\b0\i0 \fs18 identifies}{\b0\i0 \fs18 the }
0 {\b0\i0 \fs18 power}{\b0\i0 \fs18 connections}{\b0 \fs18 (Vcc}{\b0\i0 \fs18
and}{\b0\i0 \fs18 GND).}{\b0\i0 \fs18 Being}{\b0\i0 \fs18 a}{\b0\i0 \fs18 T
TL}{\b0\i0 \fs18 IC,}{\b0\i0 \fs18 the}{\b0\i0 \fs18 74150}{\b0\i0 \fs18 req
uires}{\b0\i0 \fs18 a}{\b0\i0 \fs18 5-V}{\b0\i0 \fs18 power}{\b0\i0 \fs18 s
upply. }
0 \fi363 {\b0\i0 \fs18 Note}{\b0\i0 \fs18 the}{\b0\i0 \fs18 use}{\b0\i0 \fs1
8 of}{\b0\i0 \fs18 the}{\b0\i0 \fs18 term}{\b0\i0 \fs18 "data}{\b0\i0 \f
s18 selector/muZtzpZexer"}{\b0\i0 \fs18 to}{\b0\i0 \fs18 identify}{\b0\i0 \
fs18 the}{\b0\i0 \fs18 74150}{\b0\i0 \fs18 IC.}{\i0 \fs18 A}{\b0\i0 \fs18
74150}{\b0\i0 \fs18 digital }
0 {\b0\i0 \fs18 multiplexer}{\b0\i0 \fs18 can}{\b0\i0 \fs18 be}{\b0\i0 \fs18
used}{\b0\i0 \fs18 to}{\b0\i0 \fs18 transmit}{\b0\i0 \fs18 a}{\b0\i0 \fs1
8 16-bit}{\b0\i0 \fs18 parallel}{\b0\i0 \fs18 word}{\b0\i0 \fs18 into}{\b
0\i0 \fs18 serial}{\b0\i0 \fs18 form.}{\b0\i0 \fs18 This}{\b0\i0 \fs18 i
s}{\b0\i0 \fs18 accomplished}{\b0\i0 \fs18 by }\par
}
0 CHAP. 131 \par
}
}
\par
}
onnecting a counter to the data-select inputs and counting from{\fs18
0000} to{\fs19 1111.} The 16-bit parallel
\par}{\phpg\posx843\pvpg\posy1362\absw9085\absh1497 \sl-242 \f20 \fs18 \cf0 word
at the data inputs (0-15) is then transferred to the output in{\b\i serial
}{\b\i \f30 \fs19 form} (one at a time).
63 The 74150 data selector/multiplexer
can also be used to solve dif
ficult combinational logic
lems. Consider the truth table{\fs19 on} the left in Fig. 13-3. The{\b\i \fs18
simplified} Boolean expression for this
\par}{\phpg\posx843\pvpg\posy1362\absw9085\absh1497 \sl-370 \f20 \fs18 \cf0 trut
h table is{\i \fs37 2s}{\f10 \fs27
+}{\b\i \fs19
ABCD}{\f10 \fs14 =}{\b\i
\fs19 Y.} Many{\fs19 ICs} would
needed to implement this complicated expression by using{\fs19 AND-OR}
logic or{\fs19 NAND} combina\par}{\phpg\posx843\pvpg\posy1362\absw9085\absh1497 \sl-234 \f20 \fs18 \cf0 tion
al logic circuits. The data selector is an easy method of solving this oth
erwise difficult problem. \par
}
O{\b\i \fs19
ABCE}{\i \fs19 +zBCB}{\b\i \fs18 +AB}{\i \fs19 CD}{\b\i \fs1
9 +ABcD}{\i \fs19 +xBCD}{\f10 \fs28 + }\par
}
cf0 Line \par
}
\fs17 \cf0 Inputs
f0 {\i D}{\i
C}{\i
B}{\i
A }\par
}
\fs16 0 }
\fs16 0 }
\fs16 0 }
\fs16 0 }
\fs16 0 }
\fs16 0 }
\fs16 0 }
2 {\b \fs16 1 }
8 {\b \fs16 1 }
3 {\b \fs16 1 }
6 {\b \fs16 1 }
6 {\b \fs16 1 }
0 {\b \fs16 1 }
0 {\b \fs16 1 }
3 {\b \fs16 1 }\par
}
\sl-217 \f10 \fs16 \cf0 {\b

\sl-220 \f10 \fs16 \cf0 {\b
\sl-217 \f10 \fs16 \cf0 {\b
\sl-216 \f10 \fs16 \cf0 {\b
\sl-215 \f10 \fs16 \cf0 {\b
\sl-222 \f10 \fs16 \cf0 {\b
\sl-217 \f10 \fs16 \cf0 {\b
\sl-212 \f10 \fs16 \cf0 \fi3
\sl-240 \f10 \fs16 \cf0 \fi3
\sl-210 \f10 \fs16 \cf0 \fi4
\sl-206 \f10 \fs16 \cf0 \fi4
\sl-207 \f10 \fs16 \cf0 \fi4
\sl-240 \f10 \fs16 \cf0 \fi5
\sl-217 \f10 \fs16 \cf0 \fi5
\sl-216 \f10 \fs16 \cf0 \fi5
\fs16 \cf0 \f10 \fs16 \cf0 0
\fs16 0 }
\fs16 0 }
\fs16 0 }
\fs16 1 }
\fs16 1 }
\fs16 1 }
\fs16 1 }
1 {\b \fs16 0 }
7 {\b \fs16 0 }
2 {\b \fs16 0 }
5 {\b \fs16 0 }
5 {\b \fs16 1 }
9 {\b \fs16 1 }
8 {\b \fs16 1 }
3 {\b \fs16 1 }\par
}
\sl-217 \f10 \fs16 \cf0 {\b
\fs16 0 }
\fs16 1 }
\fs16 1 }
\fs16 0 }
\fs16 0 }
\fs16 1 }
0 {\b \fs16 1 }
1 {\b \fs16 0 }
7 {\b \fs16 0 }
0 {\b \fs16 1 }
5 {\b \fs16 1 }
5 {\b \fs16 0 }
9 {\b \fs16 0 }
\sl-217 \f10 \fs16 \cf0 {\b
\sl-220 \f10 \fs16 \cf0 {\b

\sl-217 \f10 \fs16 \cf0 {\b
\sl-216 \f10 \fs16 \cf0 {\b
\sl-215 \f10 \fs16 \cf0 {\b
\sl-222 \f10 \fs16 \cf0 {\b
\sl-217 \f10 \fs16 \cf0 {\b
\sl-212 \f10 \fs16 \cf0 \fi3
\sl-240 \f10 \fs16 \cf0 \fi3
\sl-210 \f10 \fs16 \cf0 \fi4
\sl-206 \f10 \fs16 \cf0 \fi4
\sl-207 \f10 \fs16 \cf0 \fi4
\sl-240 \f10 \fs16 \cf0 \fi4
\sl-217 \f10 \fs16 \cf0 \fi4
\sl-216 \f10 \fs16 \cf0 \fi5
\fs16 \cf0 \f10 \fs16 \cf0 0
\sl-220 \f10 \fs16 \cf0 {\b

\sl-217 \f10 \fs16 \cf0 {\b
\sl-216 \f10 \fs16 \cf0 {\b
\sl-215 \f10 \fs16 \cf0 {\b
\sl-222 \f10 \fs16 \cf0 {\b
\sl-217 \f10 \fs16 \cf0 \fi2
\sl-212 \f10 \fs16 \cf0 \fi3
\sl-240 \f10 \fs16 \cf0 \fi3
\sl-210 \f10 \fs16 \cf0 \fi4
\sl-206 \f10 \fs16 \cf0 \fi4
\sl-207 \f10 \fs16 \cf0 \fi4
\sl-240 \f10 \fs16 \cf0 \fi4
\sl-217 \f10 \fs16 \cf0 \fi4
6 {\b \fs16 1 }
3 {\b \fs16 1 }\par
}
\fs16 1 }
\fs16 0 }
\fs16 1 }
\fs16 0 }
4 {\b \fs16 1 }
\fs16 0 }
6 {\b \fs16 1 }
1 {\b \fs16 0 }
7 {\b \fs16 1 }
8 {\b \fs16 0 }
5 {\b \fs16 1 }
5 {\b \fs16 0 }
9 {\b \fs16 1 }
4 {\b \fs16 0 }
3 {\b \fs16 1 }\par
}
\fs16 \cf0 1
fi53 {\fs16 2 }
fi60 {\fs16 3 }
fi53 4
fi60 {\fs16 5 }
fi65 6
fi68 {\b0 \fs16 7 }
fi68 8
fi68 {\f20 \fs17 9 }
0
1
2
3
4
5
6 \par
}
\cf0 output
f0 \fi247 {\i \fs17 Y }
f0 \fi263 {\f10 \fs16 1 }
fi243 {\b0 \f10 \fs16 0 }
fi243 {\b0 \f10 \fs16 0 }
fi265 {\f10 \fs16 1 }
fi247 {\b0 \f10 \fs16 0 }
fi251 {\b0 \f10 \fs16 0 }
fi271 {\f10 \fs16 1 }
fi251 {\b0 \f10 \fs16 0 }
fi257 {\b0 \f10 \fs16 0 }
fi283 {\f10 \fs16 1 }
fi284 {\f10 \fs16 1 }
fi265 {\b0 \f10 \fs16 0 }
fi287 {\f10 \fs16 1 }
fi270 {\b0 \f10 \fs16 0 }
fi271 {\b0 \f10 \fs16 0 }\par
}
\cf0 Data inputs
fi373 {\f10 \fs14 1 }
fi351 {\f30 \fs16 0 }
fi347 {\f10 \fs14 0 }
fi367 {\f10 \fs14 1 }
fi347 {\f10 \fs14 0 }
fi351 {\f10 \fs14 0 }
fi367 {\f10 \fs14 1 }

fi351 {\fs15 0 }
fi347 {\f10 \fs14 0 }
fi361 {\f10 \fs14 1 }
fi366 {\f10 \fs14 1 }
fi347 {\f10 \fs14 0 }
fi367 {\f10 \fs14 1 }
fi353 {\f10 \fs14 0 }
fi353 {\f10 \fs14 0 }
fi373 {\f10 \fs14 1 }\par
}
\cf0 v \par
}
f0 0
\par}{\phpg\posx6071\pvpg\posy4882\absw90\absh317 \sl-196 \b \f10 \fs11 \cf0 {\b
0 \fs11 i }\par
}
\par
}
\fs12 \cf0 4
fi58 5
fi54 {\i \f20 \fs12 6 }
fi60 {\f20 \fs13 7 }
fi84 {\f20 \fs12 8 }
fi65 {\b0 \fs11 9 }
\fs11 10 }
\b0 11 }
2
\b0 \fs11 13 }
\fs11 14 }
\f20 \fs13 I5 }\par
}
{\phpg\posx5909\pvpg\posy6412\absw79\absh324 \b \f20 \fs12 \cf0 \fi23 \b \f20 \f
s12 \cf0 '
\par}{\phpg\posx5909\pvpg\posy6412\absw79\absh324 \sl-202 \b \f20 \fs12 \cf0 {\b
0 \f10 \fs11 - }\par
}
cf0 16-input
i121 data
\par}{\phpg\posx6471\pvpg\posy5238\absw708\absh556 \sl-173 \b \f20 \fs16 \cf0 se
lector \par
}
16 \cf0 W \par
}
cf0 output
i187 {\i \f30 \fs17 Y }\par
}
cf0 (74150) \par
}
\fs16 \cf0 Strobe
nable{\f10 \fs14 a}{\i \f10 \fs14
A}{\i \f10 \fs14
13 }\par
}
22 \cf0 c \par
}
15 \cf0 D \par
}
\cf0 Fig.{\fs16 13-3}{\b0 \fs16
Using}{\b0 \fs16 the}{\b0 \fs17 74150}{\b0
\fs16 data}{\b0 \fs16 selector}{\b0 \fs16 to}{\b0 \fs16 solve}{\b0 \fs16 a
}{\b0 \fs16 combinational}{\b0 \fs16 logic}{\b0 \fs16 problem }\par
}
0 \fs18 \cf0 A{\b0 combinational}{\b0 Iogic}{\b0 problem}{\b0 is}{\b0 pose
d}{\b0 by}{\b0 the}{\b0 truth}{\b0 table}{\b0 in}{\b0 Fig.}{\b0 13-3.} A{
\b0 16-input}{\b0 data}{\b0 selector}{\b0 is }
{\b0 being}{\b0 used}{\b0 to}{\b0 solve}{\b0 the}{\b0 problem.}{\b0
The}{\b0 16}{\b0 data}{\b0 inputs}{\b0 (0-15)}{\b0
to}{\b0 the}{\fs
18 74150}{\b0 IC}{\b0 have}{\b0 logic}{\b0 levels }
{\b0 corresponding}{\b0 to}{\b0 the}{\b0 output}{\b0 column}{\b0 of}{\b0 t
he}{\b0 truth}{\b0 table.}{\b0 Line}{\b0 1}{\b0 in}{\b0 the}{\b0 truth}{\
b0 table}{\b0 has}{\b0 an}{\b0 input}{\b0 of}{\b0 binary }
{\b0 \fs18 0000}{\b0 (decimal}{\b0 \fs18 0)}{\b0 and}{\b0 an}{\b0 output}{
\b0 of}{\b0 1.}{\b0 The}{\b0 1}{\b0 is}{\b0 then}{\b0 applied}{\b0 t
o}{\b0 the}{\b0 \fs18 0}{\b0 data}{\b0 input}{\b0 of}{\b0 the}{\b0 data
}{\b0 selector. }
{\b0 Line}{\b0 \fs19 2}{\b0 in}{\b0 the}{\b0 truth}{\b0 table}{\b0 has
}{\b0 an}{\b0 input}{\b0 of}{\b0 binary}{\b0 0001}{\b0 (decimal}{\b0
1)}{\b0 and}{\b0 an}{\b0 output}{\b0 of}{\b0 \fs18 0.}{\b0 The}{\b0 \f
s18 0}{\b0 is}{\b0 then }
{\b0 applied}{\b0 to}{\b0 the}{\b0 1}{\b0 input}{\b0 \fs18 of}{\b0 the}{\b
0 data}{\b0 selector.}{\b0 The}{\b0 input}{\b0 logic}{\b0 levels}{\i \fs19
(}{\i \fs19 D}{\i \fs19 ,}{\b0 \fs18 C,}{\b0\i \fs19 B,}{\i A}{\i )}{\b0
from}{\b0 the}{\b0 truth}{\b0 table}{\b0 are }
{\b0 applied}{\b0 to}{\b0 the}{\b0 data-select}{\b0 inputs}{\b0 of}{\b0 th
e}{\fs18 74150}{\b0 data}{\b0 selector.}{\b0 The}{\b0 enable}{\b0 input}{\
b0 of}{\b0 the}{\fs18 74150}{\b0 \fs18 IC}{\b0 is}{\b0 placed }
{\b0 at}{\b0 \fs18 0,}{\b0 and}{\b0 the}{\b0 unit}{\b0 solves}{\b0 the}{\b
0 logic}{\b0 problem}{\b0 in}{\b0 the}{\b0 truth}{\b0 table.}{\b0 Note}{\
b0 that,}{\b0 because}{\b0 \fs18 of}{\b0 the}{\b0 inverted}{\b0 output }
{\b0 of}{\b0 the}{\b0 74150}{\b0 data}{\b0 selector,}{\b0 an}{\b0 inv
erter}{\b0 is}{\b0 shown}{\b0 added}{\b0 at}{\b0 the}{\b0 right}{\b0
in}{\b0 Fig.}{\b0 13-3.}{\b0 The}{\b0 data}{\b0 selector }
{\b0 solution}{\b0 to}{\b0 this}{\b0 combinational}{\b0 logic}{\b0 problem}
{\b0 was}{\b0 a}{\b0 quick}{\b0 and}{\b0 easy}{\b0 one-package}{\b0 solut
ion. }\par
}
\par
}
HER DEVICES{\b \fs17 AND} TECHNIQUES \par
}
AP. 13 \par
}
cf0 SOLVED{\fs16 PROBLEMS }
f20 \fs19 13.1}{\f20 \fs19
A}{\b0 \f20 \fs18 data}{\b0 \f20 \fs18 selector
}{\b0 \f20 \fs18 is}{\b0 \f20 \fs18 also}{\b0 \f20 \fs18 called}{\b0 \f20 \fs
18 a }
}
par
}
\cf0 A{\b0 \f20 \fs17 data}{\b0 \f20 \fs17 selector}{\b0 \f20 \fs17 is}{\b0
\f20 \fs17 also}{\b0 \f20 \fs17 called}{\b0 \f20 \fs17 a}{\b0 \f20 \fs17
multiplexer. }\par
}
cf0 13.2{\fs18
A}{\b0 \fs18 data}{\b0 \fs18 selector}{\b0 \fs18 is}{\b0 \
fs18 comparable}{\b0 \fs18 to}{\b0 \fs18 a}{\b0 \fs18 mechanical }
}
{\phpg\posx6315\pvpg\posy3129\absw682\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 sw
itch. \par
}
\cf0 A{\b0 \fs17 data}{\b0 \fs17 selector}{\b0 \fs17 is}{\b0 \fs17 compar
able}{\b0 \fs17 to}{\fs17 a}{\b0 \fs17 mechanical}{\b0 \fs17 one-way}{\b0
\fs17 rotary}{\b0 \fs17 switch. }\par
}
cf0 13.3{\b0 \fs18
\b0 \fs18 If}{\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 selects}{\b0 \fs18 o
n}{\b0 \fs18 the}{\b0 \fs18 74150}{\b0 \fs18 IC}{\b0 \fs18 equal}{\i \fs19
D}{\b0\dn006 \f10 \fs13 = }\par
}
he chip is enabled by a \par
}
{\fs19 C}{\f10 \fs14 =} 0,{\b\i \fs19 B }\par
}
\f20 \fs18 1,}{\b\i \f20 \fs18 A}{\dn006 = }\par
}
and if \par
}
HIGH,{\fs19 LOW)} at the strobe input, \par
}
inverted, normal) \par
}
ata{\fs19 will} be transferred from data input
}
decimal number) to output{\i \fs19 W. }\par
}
\cf0 Based{\fs17 on} the truth table in Fig. 13-2, if the data selects o
n the 74150 IC equal 1011{\fs17 (HLHH} in truth
e) and{\fs17 if} the chip is enabled by a{\fs17 LOW} at the strobe input,
inverted data will be transferred from data
t 11 to output{\i \fs17 W. }\par
}
cf0 13.4{\b0 \fs18
\fs18 A}{\b0 \fs18 HIGH}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 strobe}{\b
0 \fs18 input}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 74150}{\b0 \fs18 IC}{
\b0 \fs18 will }
i590 {\b0 \fs18 the}{\b0 \fs18 data}{\b0 \fs18 selector. }
i941 {\fs17 A}{\b0 \fs17 HIGH}{\b0 \fs17 at}{\b0 \fs17 the}{\b0 \fs17 st
robe}{\b0 \fs17 input}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 74150}{\b0
\fs17 IC}{\b0 \fs17 will}{\b0 \fs17 disable}{\b0 \fs17 the}{\b0 \fs17 da
ta}{\b0 \fs17 selector. }\par
}
disable, enable) \par
}

cf0 13.5{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 13-3.If}{
\b0 \fs18 the}{\b0 \fs18 data-select}{\b0 \fs18 inputs}{\b0 \fs18 equal}{\i
\fs19 D}{\b0\dn006 \f10 \fs13 = }\par
}
{\phpg\posx1467\pvpg\posy8719\absw807\absh503 \f20 \fs18 \cf0 \f20 \fs18 \cf0 be
}
,{\fs19 C}{\dn006 \f10 \fs13 =}{\fs19 0,}{\b\i \fs19 B}{\f10 \fs14 =}{\fs19
1,}{\b\i A}{\dn006 \f10 \fs13 = }\par
}
, the output{\b\i \fs19 Y} will \par
}
\cf0 (HIGH,{\fs19 LOW). }
{\fs17 If}{\fs17 the}{\fs17 data-select}{\fs17 inputs}{\fs17 equal}{\fs17
1010,}{\fs17 output}{\fs17 Y}{\fs17 of}{\fs17 the}{\fs17 data}{\fs17
selector}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs17 13-3will}{\fs17 be}
{\fs17 HIGH. }\par
}
\cf0 13.6{\b0 \fs18
Often}{\b0 \fs18 the}{\b0 \fs18 single-packagemethod}
{\b0 of}{\b0 \fs18 solvinga}{\b0 \fs18 combinationallogic}{\b0 \fs18 problem
}{\b0 \fs18 involves}{\b0 \fs18 using }
\fi583 {\b0 \fs18 (a}{\b0 \fs18 data}{\b0 \fs18 selector,}{\b0 \fs19 NAND}{\b
0 \fs18 logic). }
\fi950 {\b0 \fs17 Often}{\b0 \fs17 the}{\b0 \fs17 single-package}{\b0 \fs17
method}{\b0 \fs17
of}{\b0 \fs17 solving}{\b0 \fs17 a}{\b0 \fs17 combi
national}{\b0 \fs17 logic}{\b0 \fs17 problem}{\b0 \fs17 involves}{\b0 \fs1
7 using}{\b0 \fs17 a}{\b0 \fs17 data }
\fi590 {\b0 \fs17 selector. }\par
}
\cf0 13.7{\b0 \fs18
Draw}{\b0 \fs18 a}{\b0 \fs18 block}{\b0 \fs18 diagram
}{\b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 74150}{\b0 \fs18 data}{\b0 \fs18 sel
ector}{\b0 \fs18 being}{\b0 \fs18 used}{\b0 \fs18 to}{\b0 \fs18 solve}{\b0 \
fs18 the}{\b0 \fs18 logic}{\b0 \fs18 problem}{\b0 \fs18 described }\par
}
by the Boolean expression{\i \fs25 zB}{\b\i \fs19 CD}{\f10 \fs27 + }
}
fs19 \cf0 ZBCD{\b0\i0 \f10 \fs28 +}ABCD{\b0\i0 \f10 \fs28 +}{\fs19 AB }\par
}
+{\b\i \f20 \fs19 ABCD}{\dn006 \fs13 =}{\b\i\dn006 \f20 \fs19 Y. }\par
}
7 \cf0 See Fig. 13-4.The procedure is to first prepare from the Boolean e
xpression a truth table similar to
\par}{\phpg\posx1457\pvpg\posy12817\absw8249\absh776 \sl-220 \f20 \fs17 \cf0 tha
t in Fig. 13-3.Each 0 and 1in the output column of the truth table will be
placed{\fs17 on} the corresponding
a input of the data selector.{\b \fs17 An} inverter is placed at outp
ut{\i \fs17 W} of the 74150 data selector to read out
\par}{\phpg\posx1457\pvpg\posy12817\absw8249\absh776 \sl-215 \f20 \fs17 \cf0 non
inverted data at{\i Y. }\par
}
0 CHAP.{\b0 \fs16 131 }\par
}
}
f0 313 \par
}
17 \cf0 ABCD \par
}
14 \cf0 ABCD
{\b0 \f20 \fs18 ABCD }\par
}
15 \cf0 ABCD
{\fs15 ABCD }\par
}
\cf0 Data inputs
fi336 {\b0\i \f10 \fs14 0 }
fi357 {\b0 \f10 \fs14 1 }
fi343 {\b0\i \f10 \fs14 0 }
fi346 {\b0\i \f10 \fs13 0 }
fi343 {\b0\i \f10 \fs14 0 }
fi337 {\b0\i \f10 \fs14 0 }
fi337 {\f30 \fs15 0 }
fi360 {\f10 \fs13 1 }
fi367 {\b0 \f10 \fs13 1 }
fi346 {\b0\i \f10 \fs14 0 }
fi343 {\b0\i \f10 \fs13 0 }
fi346 {\b0\i \f10 \fs14 0 }

fi346 {\b0\i \f10 \fs13 0 }
fi337 {\b0\i \f10 \fs13 0 }
fi367 {\f10 \fs14 1 }
fi371 {\f10 \fs14 1 }
f0 \fi200 Enable \par
}
\par}{\phpg\posx4939\pvpg\posy1813\absw55\absh489 \sl-187 \par\f20 \fs12 \cf0 {\
f10 \fs16 . }\par
}
\cf0 0
\i0 \fs12 I }
\i0 \fs13 2 }
\i0 3 }
\b\i0 \fs11 4 }
\fs12 5 }
\b\i0 \fs11 6 }
\b \fs12 7 }
\b\i0 \f30 \fs12 8 }
\i0 \fs11 9 }\par
}
cf0 16-input
i116 data
\par}{\phpg\posx5467\pvpg\posy2005\absw708\absh485 \sl-172 \b \f20 \fs15 \cf0 se
lector \par
}
cf0 output \par
}
14 \cf0 W \par
}
\b \fs11 10 }\par
}
}
I
fs13 I2 }
\par}{\phpg\posx5035\pvpg\posy3725\absw234\absh811 \sl-192 \f20 \fs12 \cf0 {\b 1
3 }
f10 \fs11 14 }
f30 \fs14 I}{\b \f30 \fs14 5 }\par
}
cf0 (74150) \par
}
cf0 Strobe
i80 {\i \f10 \fs14 A}{\i \fs16
B }\par
}
cf0 c \par
}
{\phpg\posx4047\pvpg\posy4927\absw4223\absh881 \f10 \fs74 \cf0 \f10 \fs74 \cf0 [
{\fs73 *?I }\par
}
{\phpg\posx4083\pvpg\posy5977\absw450\absh440 \f10 \fs37 \cf0 \f10 \fs37 \cf0 I"
\par
}
\par
}
fs15 \cf0 Data\par}{\phpg\posx3587\pvpg\posy5547\absw897\absh483 \sl-171 \par\b \f20 \fs15 \cf
0 inputs \par
}
\cf0 Fig.{\fs17 13-4}{\fs17
Solution}{\fs17 of}{\fs17 a}{\fs17 combinatio
nal}{\fs17 logic}{\fs17 problem}{\fs17 by}{\fs17 using}{\fs17 a}{\fs17 741
50}{\fs17 data}{\fs17 selector }\par
}
\cf0 13-3{\fs18
MULTIPLEXlNG}{\fs18 DISPLAYS }
fi364 {\b0 \fs18 Many}{\b0 \fs18 electronic}{\b0 \fs18 systems}{\b0 \fs18 use
}{\b0 \fs18 alphanumeric}{\b0 \fs18 displays.}{\b0 \fs18 In}{\b0 \fs18 fact,
}{\b0 \fs18 alphanumeric}{\b0 \fs18 displays}{\b0 \fs18 are}{\b0 \fs18 a}{\b
0 \fs18 first}{\b0 \fs18 clue }
\b0 \fs18 that}{\b0 \fs18 an}{\b0 \fs18 electronic}{\b0 \fs18 system}{\b0 \fs
18 contains}{\b0 \fs18 at}{\b0 \fs18 least}{\b0 \fs19 some}{\b0 \fs18 digit
al}{\b0 \fs18 circuitry. }
fi360 {\fs19 A}{\b0 \fs18 simple}{\b0 \fs18 0}{\b0 \fs18 to}{\b0 \fs18 99}{\
b0 \fs18 counter}{\b0 \fs18 system}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18
digital}{\b0 \fs18 readout}{\b0 \fs18 is}{\b0 \fs18 diagrammed}{\b0 \fs18
in}{\b0 \fs18 Fig.}{\fs18 13-5.}{\b0 \fs18 The}{\b0 \fs18 0}{\b0 \fs18 t
o}{\b0 \fs19 99 }
\b0 \fs18 counter}{\b0 \fs18 system}{\b0 \fs18 is}{\b0 \fs18 used}{\b0 \fs
18 to}{\b0 \fs18 illustrate}{\b0 \fs18 the}{\b0 \fs18 idea}{\fs18 of}{
\i display}{\i multiplexing.}{\b0 \fs18 The}{\b0 \fs18 counters}{\b0 \fs
18 are}{\b0 \fs18 driven}{\b0 \fs18 by}{\fs19 a }
\b0 \fs18 low-frequency}{\b0 \fs18 clock}{\fs18 (1}{\fs18 Hz).}{\b0 \fs18 T
he}{\b0 \fs18 outputs}{\b0 \fs18 from}{\b0 \fs18 the}{\b0 \fs18 two}{\b0 \fs
18 decade}{\b0 \fs18 counters}{\b0 \fs18 are}{\b0 \fs18 alternately}{\b0 \fs
18 fed}{\b0 \fs18 through}{\b0 \fs18 the }\par
}
\par
}
}
cf0 MUX \par
}
\par
}
cf0 100{\b \f30 \fs18 Hz }
\fs14 nnMiuL }\par
}
\par
}
f0 x \par
}
\cf0 Decoder \par
}
\cf0 Fig.{\fs17 13-5}{\fs17
Block}{\fs17 diagram}{\fs17 of}{\fs17 0}{\fs
16 to} 99{\fs17 counter}{\fs17 using}{\fs17 multiplexed}{\fs17 displays }\p
ar
}
\fs17 \cf0 LOW{\b0 \f10 \fs14 =}{\f20 \fs15
Is}{\f20 \fs15 count }
{\f20 \fs15 HIGH}{\b0 \f10 \fs14 =}{\f20 \fs15 10s}{\f20 \fs15 count }\par
}
U- \par
}
\cf0 counter \par
}
. 131 \par
}
HER DEVICES AND TECHNIQUES \par
}
{\phpg\posx9405\pvpg\posy531\absw359\absh221 \f20 \fs19 \cf0 \f20 \fs19 \cf0 3{\
fs19 15 }\par
}
ultiplexer (MUX), decoded, and applied to{\i \fs19 both} seven-segment LED d
isplays. The multiplex clock
\par}{\phpg\posx861\pvpg\posy1350\absw9184\absh6396 \sl-237 \f20 \fs18 \cf0 (MUX
clock) generates a higher-frequency signal{\fs19 (100} Hz). This signal altern
ately lights the{\fs19 1s} count
he display at the right or the{\fs19 10s} count on the seven-segment{\fs19 LE
D} display at the left.
71 The block diagram in Fig.{\fs19 13-5} suggests that the{\fs19 1s} count
is passed through the multiplexer and
\par}{\phpg\posx861\pvpg\posy1350\absw9184\absh6396 \sl-237 \f20 \fs18 \cf0 deco
ded and the{\fs19 1s} display is activated when the MUX clock signal is LOW.
When the MUX clock
al goes HIGH, the{\fs19 10s} count is passed through the multiplexer and decod
ed and the{\fs19 10s} display is
1 activated. In effect, the seven-segment displays are alternately tu.rned{\fs19
on} and{\fs19 off} about{\fs19 100} times per
1 second. The human eye interprets that as both seven-segment LED displays bei
ng lit continuously.
81 In this example,{\i \fs19 multiplexing} reduces display power consurnp
tion and reduces the need for an
1 extra decoder. Multiplexing is widely used with displays to save power. There
is less need to multiplex
1 LCD-type displays because they already consume very little power. For this a
nd other reasons, LCD
lays are often driven directly and not multiplexed.
63 The logic diagram in Fig.{\fs19 13-6} is an implementation of the{\fs19 0}
to 99 counter using TTL ICs. All of
ICs used were examined in some detail earlier in the book except the multiplexer
. The{\fs19 74157}{\i \fs19 TTL }
\fs19 2-line-to-1-linemultiplexer} serves the purpose of alternately switch
ing either the{\fs19 1s} count or the{\fs19 10s }
t onto the input of the decoder. Note that, when the{\i \fs19 select}{\i \fs19
line} of the{\fs19 74157} MUX is LOW, the{\b \fs19 A }
(BCD from{\fs19 1s} counter) is passed to the decoder. At the same time, the{
\fs19 7404} inverter's output is
, which allows the{\fs19 1s} seven-segment display to light. The{\fs19 10
s} display is turned{\fs19 off} when the
\par}{\phpg\posx861\pvpg\posy1350\absw9184\absh6396 \sl-232 \f20 \fs18 \cf0 MUX
clock is LOW because the anode is grounded.
73 When the select line to the{\fs19 74157} MUX in Fig.{\fs19 13-6} go
es HIGH, the{\fs19 B} data is passed to the
1 decoder. At the same instant, the anode of the{\fs19 10s} seven-segment displ
ay is HIGH, which allows it to

2 light. The{\fs19 1s} display is turned off during this time because its anode
is grounded by the LOW from the
1 output of the inverter. The{\fs19 150-0} resistors limit the current through
the display LEDs to a safe level.
73 The circuit shown{\fs18 in} Fig.{\fs19 13-6} will actually operate. To d
emonstrate that'the displays are being
\par}{\phpg\posx861\pvpg\posy1350\absw9184\absh6396 \sl-229 \f20 \fs18 \cf0 mult
iplexed, substitute a 150-kfl resistor for{\i \fs19 R,} in the MUX clock
circuit. This will slow down the
1 MUX clock{\fs19 so} you can see the action of the multiplexer as the dis
plays flash alternately on and{\fs18 off. }
6 {\b \fs18 13.8}
Refer to Fig.{\fs19 13-5.} When the MUX clock signal is HI
GH, the{\fs19
(Is,}{\fs19 10s)} count is lit on \par
}
e
}
\cf0 (left, right) seven-segment LED display.
{\fs17 When}{\fs17 the}{\fs17 MUX}{\fs17 signal}{\fs17 shown}{\fs17 in}
{\fs17 Fig.}{\fs17 13-5}{\fs17 is}{\fs17 HIGH}{\fs17 the}{\fs17 10s}{
\fs17 count}{\fs17 is}{\fs17 lit}{\fs17 on}{\fs17 the}{\fs17 left}{\fs1
7 LED}{\fs17 display. }\par
}
f0 13.9 \par
}
hy are displays multiplexed?
\fs17 Solution: }
60 {\fs17 Multiplexing}{\fs17 of}{\fs17 LED}{\fs17 displays}{\fs17 reduce
s}{\fs17 power}{\fs17 consumption}{\fs17 and}{\fs17 simplifies}{\fs17 wi
ring. }\par
}
\cf0 13.10{\b0 \fs18
}{\b0 \fs18 Technically,}{\b0 \fs18 are}{\b0\i \fs19 60th}{\b0 \fs18 seven-s
egment}{\b0 \fs18 displays}{\b0 \fs18 ever}{\b0 \fs18 lit}{\b0 \fs18 at}{\b0
\fs18 the}{\b0 \fs18 same}{\b0 \fs18 time? }
\fi943 {\b0 \fs17 Technically,}{\b0 \fs17 both}{\b0 \fs17 seven-segment}{\b0
\fs17 displays}{\b0 \fs17 shown}{\b0 \fs17 in}{\fs16 Fig.}{\b0 \fs17
13-6}{\b0 \fs17 are}{\b0 \fs17 never}{\b0 \fs17 lit}{\b0 \fs17 at}{\b0 \f
s17 the}{\b0 \fs17 same}{\b0 \fs17 time.}{\b0 \fs17 To}{\b0 \fs17 the
}
\fi590 {\b0 \fs17 human}{\b0 \fs17 eye}{\b0 \fs17 they}{\b0 \fs17 both}{\b
0 \fs17 appear}{\b0 \fs17 to}{\b0 \fs17 be}{\b0 \fs17 continuously}{\b0 \
fs16 lit}{\b0 \fs17 because}{\b0 \fs17 they}{\b0 \fs17 are}{\b0 \fs17 f
lashing}{\b0 \fs17 at}{\b0 \fs17 100}{\fs17 Hz. }
cf0 13.11{\b0 \fs18
\b0 \fs18 What}{\b0 \fs18 effect}{\b0 \fs18 would}{\b0 \fs18 reducing}{\b0 \f
s18 the}{\b0 \fs18 MUX}{\b0 \fs18 clock}{\b0 \fs18 frequency}{\b0 \fs18 to}
{\b0 \fs19 5}{\b0 \fs18 Hz}{\b0 \fs18 have}{\b0 \fs18 on}{\b0 \fs18 the }
\fi590 {\b0 \fs18 appearance}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 displays
? }
\fi945 {\b0 \fs17 If}{\b0 \fs17 the}{\b0 \fs17 frequency}{\b0 \fs17 of}{\b
0 \fs17 the}{\b0 \fs17 MUX}{\b0 \fs17 clock}{\b0 \fs17 shown}{\b0 \fs17
in}{\b0 \fs17 Fig.}{\b0 \fs17 13-6}{\b0 \fs17 were}{\b0 \fs17 reduced}{\
b0 \fs17 to}{\b0 \fs17 5}{\b0 \fs17 Hz,}{\b0 \fs17 the}{\b0 \fs17 eye}{
\b0 \fs17 would}{\b0 \fs17 see}{\b0 \fs17 the }
\fi586 {\b0 \fs17 multiplexing}{\b0 \fs17 action}{\b0 \fs17 as}{\b0 \fs17
a}{\b0 \fs17 flashing}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 displays. }
\par
}
0 316 \par
}
}
AP.{\b \fs17 13 }\par
}
cf0 13.12{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 13-6.The
}{\b0 \fs18 logic}{\b0 \fs18 level}{\b0 \fs18 on}{\b0 \fs18 the }\par
}
nput to the 74157{\b \fs19 MUX} determines if the{\fs19 Is }\par
}
\cf0 or the{\fs19 10s} count will be passed on to the decoder.
50 {\fs17 The}{\fs17 logic}{\fs17 level}{\fs17 of}{\fs17 the}{\fs17 sel
ect}{\fs17 input}{\fs17 to}{\fs17 the}{\b \fs17 74157}{\fs17 MUX}{\fs17
in}{\fs17 Fig.}{\fs17 13-6}{\fs17 determines}{\fs17 if}{\fs17 the}{\
b \fs17 1s}{\fs17 or}{\fs17 10s}{\fs17 count }
88 {\fs17 will}{\fs17 be}{\fs17 passed}{\fs17 on}{\fs17 to}{\fs17 the}
{\fs17 decoder. }
{\b \fs18 13.13} Refer to Fig. 13-6. If the{\fs19 MUX} clock is{\fs19 LOW,}
the 1s count is passed through the decoder to
80 which seven-segment display(s)?

48 {\fs17 When}{\fs17 the}{\fs17 MUX}{\fs17 clock}{\fs17 shown}{\fs17 in}{
\fs17 Fig.}{\fs17 13-6}{\fs17 is}{\fs17 LOW,}{\fs17 the}{\b \fs17 1s}{\fs
17 count}{\fs17 is}{\fs17 passed}{\fs17 through}{\fs17 the}{\fs17 decoder
}{\fs17 to-both }
90 {\fs17 displays.}{\fs17 However,}{\fs17 only}{\fs17 the}{\b \fs17 1s}{\f
s17 display}{\fs17 lights}{\fs17 because}{\fs17 only}{\fs17 its}{\fs17 an
ode}{\fs17 is}{\fs17 HIGH. }
{\b \fs18 13.14} Refer to Fig. 13-6. What is the job of the 7404 inverter?
50 {\fs17 The}{\fs17 inverter}{\fs17 shown}{\fs17 in}{\fs17 Fig.}{\fs17
13-6}{\fs17 activates}{\fs17 the}{\fs17 anodes}{\fs17 of}{\fs17 the}{
\fs17 displays}{\fs17 alternately.}{\fs17 A}{\fs17 HIGH}{\fs17 at}{\fs
17 the }
02 {\fs17 anode}{\fs17 will}{\fs17 activate}{\fs17 the}{\fs17 display. }
{\b \fs18 13-4}{\b \fs19
DEMULTIPLEXERS }
56 The operation{\fs19 of} a{\b\i \fs19 demultiplexer}{\b\i \fs19 (DEMUX)}
is illustrated in Fig. 13-7. The demultiplexer reverses
operation{\fs19 of} the multiplexer (see Fig.{\fs19 13-1).}The single-pole, ei
ght-position rotary switch at the left
Fig. 13-7 shows the fundamental idea of the demultiplexer. Notice that t
he demultiplexer has a
le input and eight outputs. The data at the input can be distributed to one of e
ight outputs by the
\par}{\phpg\posx863\pvpg\posy1582\absw9124\absh6069 \sl-235 \f20 \fs18 \cf0 mech
anical wiper arm on the rotary.switch at the left. In the example in Fig. 13-7
, the{\fs19 HIGH} at the
t is routed to output 2 by the rotary switch.
\fi5202 {\b \fs15 Inputs}{\b \fs15
o
utputs }
892 {\b \fs15 outputs }\par
}
\cf0 Demultiplexer \par
}
cf0 HIGH \par
}
x- \par
}
cf0 3 \par
}
cf0 InputHIGH \par

}
{\phpg\posx7865\pvpg\posy9366\absw975\absh590 \f10 \fs50 \cf0 \f10 \fs50 \cf0 (j
l= \par
}
cf0 7 \par
}
0
0 {\b \fs15 1 }
i \fs23 o}{\i \fs23 c }
i263 {\b Electronic}{\b data}{\b s:lector }\par
}
\cf0 Mechanical data selector \par
}
\cf0 7 \par
}
20 \fs17 \cf0 Fig.{\fs16 13-7}{\b0
Comparison}{\b0 \fs16 of}{\b0 a}{\b0
rotary}{\b0 switch}{\b0 and}{\b0 a}{\b0 demultiplexer}{\b0 (data}{\b0 dis
tributor) }
cf0 \fi355 {\fs18 A}{\b0 \fs18 logic}{\b0 \fs18 symbol}{\b0 \fs18 for}{\b0 \f
s18 a}{\b0 \fs18 simplified}{\b0 \fs18 electronic}{\b0 \fs18 demultiplexer}{
\b0 \fs18 is}{\b0 \fs18 drawn}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 right
}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-7.Note}{\b0 \fs18 the }
{\b0 \fs18 single}{\b0 \fs18 data}{\b0 \fs18 input}{\b0 \fs18 with}{\b0 \f
s18 eight}{\b0 \fs18 outputs.}{\b0 \fs18 The}{\b0 \fs18 demultiplexer}{\
b0 \fs18 also}{\b0 \fs18 has}{\b0 \fs18 three}{\b0 \fs18 data-select}{\b
0 \fs18 inputs}{\b0 \fs18 (address }
{\b0 \fs18 inputs)}{\b0 \fs18 for}{\b0 \fs18 choosing}{\b0 \fs18 which}{\b0
\fs18 output}{\b0 \fs18 is}{\b0 \fs18 selected.}{\b0 \fs18 In}{\b0 \fs18
the}{\b0 \fs18 example}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-7,
}{\b0 \fs18 the}{\b0 \fs19 HIGH}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18
input }
{\b0 \fs18 appears}{\b0 \fs18 at}{\b0 \fs18 output}{\b0 \fs19 2}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 electronic}{\b0 \fs18 demultiplexer}{\b0 \
fs18 because}{\b0 \fs18 010,}{\b0 \fs19 (2}{\b0 \fs18 in}{\b0 \fs18 de
cimal)}{\b0 \fs18 is}{\b0 \fs18 applied}{\b0 \fs18 to}{\b0 \fs18 the }
{\b0 \fs18 data-select}{\b0 \fs18 inputs.}{\b0 \fs18 The}{\b0 \fs18 demultipl
exer}{\b0 \fs18 is}{\b0 \fs18 also}{\b0 \fs18 called}{\b0 \fs18 a}{\b0\i \f
s19 decoder}{\b0 \fs18 and}{\b0 \fs18 sometimes}{\b0 \fs18 a}{\i \fs19 d
ata}{\i \fs19 distributor. }
\fi361 {\b0 \fs18 The}{\b0 \fs18 electronic}{\b0 \fs18 demultiplexer}{\b0 \fs1
8 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-7}{\b0 \fs18 only}{\b0 \fs18 allows}{\b
0 \fs18 data}{\b0 \fs18 to}{\b0 \fs18 flow}{\b0 \fs18 from}{\b0 \fs18 input
}{\b0 \fs18 to}{\b0 \fs18 output,}{\b0 \fs18 whereas }
{\b0 \fs18 the}{\b0 \fs18 rotary}{\b0 \fs18 switch}{\b0 \fs18 permits}{\b0 \f
s18 data}{\b0 \fs18 to}{\b0 \fs18 flow}{\b0 \fs18 in}{\b0 \fs18 both}{\b0 \
fs18 directions.}{\fs19 A}{\b0 \fs18 data}{\b0 \fs18 distributor,}{\b0 \fs18
or}{\b0 \fs18 demultiplexer,}{\b0 \fs18 can}{\b0 \fs18 be }
{\b0 \fs18 thought}{\b0 \fs18 of}{\b0 \fs18 as}{\b0 \fs18 being}{\b0 \fs18 s
imilar}{\b0 \fs18 to}{\b0 \fs18 a}{\b0 \fs18 one-way}{\b0 \fs18 rotary}{\b0
\fs18 switch. }\par
}
0 CHAP.{\fs17 131 }\par
}
}
f0 317 \par
}
cf0 outputs \par
}
0 \cf0 3 \par
}
s15 \cf0 (a){\i0 \fs15 Logic}{\i0 \fs15 symbol }\par
}
cf0 outputs
fs15 7}{\fs15
8 }\par
}
\cf0 2
3
4
5{\fs14
6 }\par
}
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L \par
}
\cf0 x x x x
x x x x
x x x x \par
}
H
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}
cf0 Data\par}{\phpg\posx3689\pvpg\posy5849\absw541\absh509 \sl-187 \b \f20 \fs15 \cf0 se
lect
puts \par
}
\fs15 \cf0 Function Table
fi643 Inputs
\b0 \fs15 G1}{\fs15
G2}{\i \fs15
D}{\i \fs15
C}{\i \fs15
B}{\i \
fs15
A }\par
}
\cf0 L
0 L
2 L
0 L
0 L
0 L
0 L
0 L
0 L
2 L
0 L
0 L
0 L
1 L
ar
}
\sl-200 \f20 \fs15 \cf0 \fi2

\sl-194 \f20 \fs15 \cf0 \fi2
\sl-197 \f20 \fs15 \cf0 \fi2
\sl-198 \f20 \fs15 \cf0 \fi2
\sl-194 \f20 \fs15 \cf0 \fi2
\sl-198 \f20 \fs15 \cf0 \fi2
\sl-197 \f20 \fs15 \cf0 \fi2
\sl-197 \f20 \fs15 \cf0 \fi2
\sl-197 \f20 \fs15 \cf0 \fi2
\sl-198 \f20 \fs15 \cf0 \fi2
\sl-194 \f20 \fs15 \cf0 L
\sl-200 \f20 \fs15 \cf0 \fi2
\sl-195
\sl-200
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\par}{\phpg\posx2591\pvpg\posy8021\absw149\absh3380 \sl-195 \f20 \fs15 \cf0 H \p
ar
}
par
}
cf0 1 \par
}
\par
}

\cf0 1 0 1 1 1 2 1 3 1 4 1 5 \par
}
H{\f10 \fs11 =} High{\b \fs15 Level,} L{\dn006 \f10 \fs10 =} Low{\b \fs15 L
evel,}{\b X}{\f10 \fs11 =}{\b \fs15 Don't}{\b \fs15 Care }
\fi975 {\b\i \fs15 (b)}{\b \fs15 Function}{\b \fs15 table}{\b\i \fs15 (Courte
sy}{\b\i \fs15 of}{\b\i \fs15 National}{\b\i \fs15 Semiconductor}{\b\i \fs15
Corporation}{\f10 \fs13 ) }
\fi1203 {\b \fs16 Fig.}{\b \fs16 13-8}{\b \fs17 The}{\b \fs17 74LS154}{\b \
fs17 decoder/dernultiplexer}{\b \fs17
IC }\par
}
\par
}
}
AP. 13 \par
}
\fs19 \cf0 A{\b0 \fs18 commercial}{\b0 \fs18 demultiplexer}{\b0 \fs18 is}{\b
0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-8.The}{\b0 \fs18
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fs18 13-8is}{\b0 \fs18 described }
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logic}{\b0 \fs18 diagram}{\b0 \fs18 in }
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8 to}{\b0 15)}{\b0 \fs18 with}{\b0 \fs18 4 }
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}{\b0 \fs18 LOW}{\b0 \fs18 when}{\b0 \fs18 activated.}{\b0 \fs18 The}{\b0 \
fs18 74LS154}{\b0 \fs18 has}{\b0 \fs18 two}{\b0 \fs18 data}{\b0 \fs18 input
s}{\b0 \f30 \fs37 (a}{\b0\i \fs37 a) }
\b0 \fs18 are}{\b0 \fs18 NORed}{\b0 \fs18 together}{\b0 \fs18 to}{\b0 \fs1
8 generate}{\b0 \fs18 the}{\b0\i \fs18 single}{\b0 \fs18 data}{\b0 \fs18
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}{\b0 \fs18 are}{\b0 \fs18 both}{\b0 \fs18 active-LOW }
\b0 \fs18 inputs. }
fi360 {\b0 \fs18 The}{\b0 \fs18 74LS154}{\b0 \fs18 demultiplexer}{\b0 \fs18
is}{\b0 \fs18 sometimes}{\b0 \fs18 described}{\b0 \fs18 as}{\b0 \fs18
a}{\i \f30 2-of-16}{\b0\i \fs18 decoder.}{\b0 \fs18

The}{\b0 \fs18 74LS154
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\b0 \fs18 member}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 TTL}{\b0 \fs18 lo
w-power}{\b0 \fs18 Schottky}{\b0 \fs18 family.}{\b0 \fs18 The}{\b0 \fs18 7
4LS154}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 fast}{\b0 \fs18 decoder}{\b0
\fs18 with}{\b0 \fs18 a}{\b0 \fs18 propagation }
\b0 \fs18 delay}{\b0 \fs18 of}{\b0 \fs18 less}{\b0 \fs18 than}{\b0 \fs18 30}
{\b0 \fs18 ns. }
fi358 A{\b0 \fs18 truth}{\b0 \fs18 table}{\b0 \fs19 (or}{\b0 \fs18 function}
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8 decoder/demultiplexer}{\b0 \fs18 IC}{\b0 \fs18 is}{\b0 \fs18 reproduced}{
\b0 \fs18 in}{\b0 \fs18 Fig. }
fi3542 {\b0 \f30 \fs37 (a}{\b0\i \fs37 m) }
\b0 \fs18 activated.}{\b0 \fs18 The}{\b0 \fs18 data-select}{\b0 \fs18 inpu
ts}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 thought}{\b0 \fs18 of}{\b0 \f
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8 of}{\b0 \fs18 the}{\b0 \fs18 use}{\b0 \fs18 of}{\b0 \fs18 the }
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18 decoder.}{\b0 \fs18 For}{\b0 \fs18 instance,}{\b0 \fs18 it}{\b0 \fs18 mi
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\b0 \fs18 chips. }
fi366 {\b0 \fs18 Both}{\b0 \fs18 TTL}{\b0 \fs18 and} CMOS{\b0 \fs18 versions}
{\b0 \fs18 of}{\b0 \fs18 demultiplexers/decoders}{\b0 \fs18 are}{\b0 \fs18
available.}{\b0 \fs18 Common}{\b0 \fs18 units}{\b0 \fs18 include }
\b0 \fs18 1-of-4,}{\b0 \fs18 1-of-8,}{\b0 \fs18 1-of-10,}{\b0 \fs18 and}{\b0
\fs18 1-of-16}{\b0 \fs18 decoders/demultiplexers. }\par
}
nd
which \par
}
-8b. Note that both the data inputs
and
must be LOW be
fore{\fs18 1}{\fs18 of} the 16 outputs is \par
}
LVED PROBLEMS \par
}
cf0 13.15 A
}
\cf0 (demultiplexer, shift register) reverses the action of a multiplexer.
{\fs17 The}{\fs17 demultiplexer}{\fs17 reverses}{\fs17 the}{\fs17 action
}{\fs17 of}{\fs17 the}{\fs17 multiplexer}{\fs17 (compare}{\fs17 Figs.}{
\fs17 13-1}{\fs17 and}{\fs17 13-7). }\par
}
cf0 13.16{\b0 The}{\b0 demultiplexer}{\b0 on}{\b0 the}{\b0 right}{\b0

in}{\b0 Fig.}{\b0 13-7}{\b0 could}{\b0 also}{\b0 be}{\b0 referred}{
\b0 to}{\b0 as}{\b0 a }
i604 {\b0 1-of-16)}{\b0 decoder. }
}
-of-8, \par
}
\cf0 The demultiplexer on the right in Fig. 13-7 distributes data fr
om a single input to one of eight
uts. It is therefore commonly called a{\fs16 I-of-8} decoder. \par
}
cf0 13.17{\b0 Demultiplexers}{\b0 are}{\b0 commonly}{\b0 called}{\b0 d
ata }
i587 {\b0 (decoders,}{\b0 gates). }
}
distributors, multivibrators) or \par
}
emultiplexers are commonly called data distributors or decoders. \par
}
\cf0 13.18{\b0 The}{\b0 74LS154}{\b0 demultiplexer}{\b0 is}{\b0 a }
fi589 {\b0 LOW)}{\b0 data}{\b0 inputs}{\b0 and}{\b0 active- }
}
8 \cf0 (1-of-8, 1-of-16) decoder with active\par}{\phpg\posx4813\pvpg\posy10325\absw3618\absh419 \sl-232 \f20 \fs18 \cf0 (HI
GH, LOW) outputs. \par
}
HIGH, \par
}
\cf0 See Fig. 13-8. The 74LS154 demultiplexer is a 1-of-16 decoder with
active-LOW data inputs and
96 active-LOW outputs.
{\b \fs18 13.19}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 13-8.}{\fs18 Both
}{\fs18 data}{\fs18 inputs}{\fs18
and}{\fs24 G2}{\fs18 must}{\fs18 b
e}{\fs18
(HIGH,}{\fs18 LOW)}{\fs18 to}{\fs18 activate}{\fs18 t
he }\par
}
selected output on the 74LS154 demultiplexer{\b \fs19 IC. }

}
See{\fs16 Fig.} 13-8b. Both data inputs \par
}
(z{\i \f20 \fs34 m) }\par
}
and
must be LOW to activate the selected output. \par
}
\cf0 13.20{\b0 Which}{\b0 output}{\b0 \fs18 of}{\b0 the}{\b0 74LS154}{
\b0 demultiplexer}{\b0 will}{\b0 be}{\b0 activated}{\b0 \fs18 if }
fi581 {\b0 while}{\b0 the}{\b0 data-select}{\b0 inputs}{\b0 are}{\b0 all}{
\b0 HIGH. }\par
}
and{\fs24 G2} are both LOW \par
}
. 131 \par
}
}
f0 319 \par
}
\cf0 Solution:
fi352 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 13-8.Output}{\b0 \fs17 15wil
l}{\b0 \fs17 be}{\b0 \fs17 activated}{\b0 \fs17 (LOW)}{\b0 \fs17 when}{\b0 \
fs17 data}{\b0 \fs17 inputs }\par
}
0 \fs34 \cf0 (m{\f20 \fs33 m) }
\par}{\phpg\posx883\pvpg\posy1503\absw7410\absh1126 \sl-292 \par\par\i \f30 \fs3
4 \cf0 {\b\i0 \f20 \fs18 13.21}{\i0 \f20 \fs19 Which}{\i0 \f20 \fs19 output}
{\i0 \f20 \fs19 of}{\i0 \f20 \fs19 the}{\i0 \f20 \fs19 74LS154}{\i0 \f20 \
fs19 demultiplexer}{\i0 \f20 \fs19 will}{\i0 \f20 \fs19 be}{\i0 \f20 \fs19
activated}{\i0 \f20 \fs19 if}{\i0 \f20 \fs19
and }\par
}
nd
are LOW and all the \par
}
ata-select inputs are HIGH. The address at the data-select inputs is{\fs1
6 llll,,} which is decimal 15. \par
}
hile the data-select inputs are{\i D}{\dn006 \f10 \fs13 = }
}
OW,{\b\i \f30 \fs20 C}{\dn006 \f10 \fs13 =} LOW,{\i B}{\dn006 \f10 \fs13 =
}\par
}
IGH, and{\b\i \fs18 A}{\dn006 \f10 \fs11
= }
00 {\f30 \fs33 (a }\par
}
\cf0 See Fig. 13-8. Output 3 will be activated (LOW) when data inputs
\par}{\phpg\posx1481\pvpg\posy3393\absw5634\absh389 \sl-218 \f20 \fs17 \cf0 addr
ess at the data-select inputs is 0011, (decimal 3). \par
}
a{\f20 \fs19
are}{\f20 \fs19 both}{\f20 \fs19 LOW }
934 {\f20 \fs19 HIGH? }
\fi300 {\f20 \fs17 and}{\b\i \f20 \fs23 E)}{\f20 \fs17 are}{\f20 \fs17 LOW}{
\f20 \fs17 and}{\f20 \fs17 the }\par
}
\cf0 13-5{\fs19
LATCHES} AND{\fs19 THREE-STATE}{\fs19 BUFFERS }
fi362 {\b0 \fs19 Consider}{\b0 \fs19 the}{\b0 \fs19 simple}{\b0 \fs19 digi
tal}{\b0 \fs19 system}{\b0 \fs19 shown}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0
\i \fs19 13-9a.}{\b0 \fs19 When}{\b0 \fs19 7}{\b0 \fs19 is}{\b0 \fs19 pr
essed}{\b0 \fs19 on}{\b0 \fs19 the}{\b0 \fs19 keyboard,}{\b0 \fs19 a }
\b0 \fs19 decimal}{\b0 \fs19 7}{\b0 \fs19 appears}{\b0 \fs19 on}{\b0 \fs19 t
he}{\b0 \fs19 display.}{\b0 \fs19 However,}{\b0 \fs19 when}{\b0 \fs19 the}{\
b0 \fs19 key}{\b0 \fs19 is}{\b0 \fs19 released,}{\b0 \fs19 the}{\b0 \fs19 7
}{\b0 \fs19 disappears}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \fs19 output }
\b0 \fs19 display.}{\b0 \fs19 To}{\b0 \fs19 solve}{\b0 \fs19 this}{\b0 \fs19
problem,}{\b0 \fs19 a}{\b0\i \fs19 4-bit}{\b0\i \fs19 latch}{\b0 \fs19 ha
s}{\b0 \fs19 been}{\b0 \fs19 added}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19
system}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \fs19 13-9b}{\b0 \fs19 so}{\b0
\fs19 that,}{\b0 \fs19 when }
\b0 \fs19 the}{\b0 \fs19 key}{\b0 \fs19 is}{\b0 \fs19 pressed}{\b0 \fs19 an
d}{\b0 \fs19 released,}{\b0 \fs19 the}{\b0 \fs19 decimal}{\b0 \fs19 number}
{\b0 \fs19 will}{\b0 \fs19 remain}{\b0 \fs19 lit}{\b0 \fs19 on}{\b0 \fs19
the}{\b0 \fs19 seven-segment}{\b0 \fs19 display.}{\b0 \fs19 It }
\b0 \fs19 can}{\b0 \fs19 be}{\b0 \fs19 said}{\b0 \fs19 that}{\b0 \fs19 the}{
\b0 \fs19 number}{\b0 \fs19 7}{\b0 \fs19 is}{\b0\i \fs19 latched}{\b0 \fs19
on}{\b0 \fs19 the}{\b0 \fs19 display.}{\b0 \fs19 The}{\b0 \fs19 latch}{\b0
\fs19 could}{\b0 \fs19 also}{\b0 \fs19 be}{\b0 \fs19 referred}{\b0 \fs19 t
o}{\b0 \fs19 as}{\b0 \fs19 a}{\b0\i \fs19 buger }
\b0 \fs19 memory. }\par
}
20 \fs17 \cf0 Fig. 13-9{\b0 \fs17
Block}{\b0 \fs17 diagram}{\b0 \fs17 of}{\
b0 \fs17 simple}{\b0 \fs17 digital}{\b0 \fs17 systems }
cf0 \fi367 {\fs19 A}{\b0 \fs19 simple}{\b0 \fs19 latch}{\b0 \fs19 manufact
ured}{\b0 \fs19 in}{\b0 \fs19 IC}{\b0 \fs19 form}{\b0 \fs19 is}{\b0 \fs1
9 detailed}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \fs19 13-10.}{\b0 \fs19
This}{\b0 \fs19 is}{\b0 \fs19 the}{\b0 \fs19 TTL}{\b0 \fs19 7475}{\b0\i

\fs19 4-bit }
{\b0\i \fs19 transparent}{\b0\i \fs19 latch}{\b0\i \fs19 IC.}{\fs19 A}{\b0 \
fs19 logic}{\b0 \fs19 diagram}{\b0 \fs19 for}{\b0 \fs19 the}{\b0 \fs19 74
75}{\b0 \fs19 latch}{\b0 \fs19 is}{\b0 \fs19 shown}{\b0 \fs19 in}{\b0 \fs19
Fig.}{\b0\i \fs19 13-10a}{\b0 \fs19 with}{\b0 \fs19 its}{\b0 \fs19 trut
h}{\b0 \fs19 table }
{\b0 \fs19 detailed}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0\i \fs19 13-lob.}{\b
0 \fs19 The}{\b0 \fs19 7475}{\b0 \fs19 IC}{\b0 \fs19 has}{\b0 \fs19 four
}{\b0 \fs19 data}{\b0 \fs19 inputs}{\b0 \fs19 which}{\b0 \fs19 accept}{\b
0 \fs19 parallel}{\b0 \fs19 data.}{\b0 \fs19 The}{\b0 \fs19 data}{\b0 \fs
19 at }
{\b0\i \fs19 Do-D,}{\b0 \fs19
pass}{\b0 \fs19 through}{\b0 \fs19 the}{\b0
\fs19 7475}{\b0 \fs19 to}{\b0 \fs19 both}{\b0 \fs19 normal}{\b0 \fs19
and}{\b0 \fs19 complementary}{\b0 \fs19 outputs}{\b0 \fs19 when}{\b0 \fs19
the}{\b0\i \fs19 data-enable }
{\b0 \fs19 inputs}{\b0 \fs19 are}{\b0 \fs19 HIGH.}{\b0 \fs19 With}{\b0 \fs19
the}{\b0 \fs19 data-enable}{\b0 \fs19 inputs}{\b0 \fs19 HIGH}{\b0 \fs19 t
he}{\b0 \fs19 latch}{\b0 \fs19 is}{\b0 \fs19 said}{\b0 \fs19 to}{\b0 \fs19
be}{\b0\i \fs19 transparent}{\b0 \fs19 in}{\b0 \fs19 that}{\b0 \fs19 any
}
{\b0 \fs19 change}{\b0 \fs19 in}{\b0 \fs19 data}{\b0 \fs19 at}{\b0 \fs19 th
e}{\b0 \fs19 data}{\b0 \fs19 inputs}{\b0 \fs19 is}{\b0 \fs19 immediately}{\b
0 \fs19 passed}{\b0 \fs19 to}{\b0 \fs19 the}{\b0 \fs19 data}{\b0 \fs19 o
utputs.}{\b0 \fs19 When}{\b0 \fs19 the}{\b0 \fs19 data-enables }
{\b0 \fs19 are}{\b0 \fs19 activated}{\b0 \fs19 with}{\b0 \fs19 a}{\b0 \fs19
LOW,}{\b0 \fs19 data}{\b0 \fs19 is}{\b0 \fs19 latched}{\b0 \fs19 (or}{\b0 \f
s19 held)}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \fs19 outputs.}{\b0 \fs19 When}
{\b0 \fs19 latched,}{\b0 \fs19 changes}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \fs
19 data }
{\b0 \fs19 inputs}{\b0 \fs19 do}{\b0 \fs19 not}{\b0 \fs19 cause}{\b0 \fs19 a
ny}{\b0 \fs19 changes}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \fs19 outputs. }\par
}
0 320 \par
}
HER{\fs17 DEVICES}{\fs17 AND} TECHNIQUES \par
}
AP. 13 \par
}
\cf0 Data inputs for
2 {\i \fs15 Do} and{\i \fs15 D}{\i \fs15 ,} latches
cf0 Data inputs for
\fs15 D2} and{\i \fs15 D3} latches \par
}
{\phpg\posx3929\pvpg\posy1591\absw832\absh1003 \f10 \fs38 \cf0 \f10 \fs38 \cf0 \

{\par}{\phpg\posx3929\pvpg\posy1591\absw832\absh1003 \sl-607 \f10 \fs38 \cf0 {\fs
40 \{}{\fs19 - }\par
}
cf0 QO \par
}
ormal and
lementary
uts{\fs15 for}{\i \fs15 Do }
\i \fs15 D}{\i \fs15 ,} latches \par
}
cf0 4-bit
b0 latch }
0 {\b0 \f10 \fs15 7475) }\par
}
cf0 Qi \par
}
\cf0 1{\f10 \fs13 =}{\fs14 data}{\fs14 enable }
15 0}{\dn006 \f10 \fs13 =}{\fs14 latch}{\fs14 enable }\par
}
cf0 E,{\i0\dn006 \f10 \fs10
1 }
0 {\fs11 '2-3 }\par
}
cf0 Q3 \par
}
ormal and
lementary
uts{\fs15 for}{\i \fs15 D2 }
\i \fs15 D}{\i \fs15 ,} latches \par
}
\cf0 (a){\i0 \f20 \fs14 Logc}{\i0 \f20 \fs14 diagram }\par
}
\fs15 \cf0 QO
f0 \fi119 DO
f0 \fi122 Dl
f0 {\b\i0 \fs11 '2-3 }

fi54 {\fs18 vcc }
f0 \fi106 D2
f0 \fi108 D3
fi136 {\i0 \f10 \fs11 - }
fi114 {\b \fs11 Q3 }\par
}
\cf0 QO
\fs17 Q}{\fs17 I }
f0 Ql
f0 {\b \f30 \fs12 E04 }
fi36 {\b\i0 \fs15 GND }
fi50 {\i0 \f10 \fs7 - }
fi26 {\fs11 Q2 }
f0 Q2
f0 {\fs11 Q3 }\par
}
s15 \cf0 (b){\b0\i0 \fs14 Truth}{\i0 table }\par
}
\cf0 (c){\i0 \f20 \fs14 Pin}{\i0 \f20 \fs14 diagram }\par
}
\cf0 Fig.{\fs17 13-10}{\b0 \f10 \fs16
7475}{\fs17 4-bit}{\b0 \fs16 latch }
\par
}
\cf0 The 7475 latch comes in a standard DIP IC. The pin diagram for the
7475 IC is drawn in Fig.
2 {\i \fs18 13-1Oc.} 7475 latch is considered a parallel-in parallel-out regis
ter.
76 Microprocessor-based systems (such as microcomputers) use a two-way{\i \fs1
8 data}{\i \fs19 bus} to transfer data
\par}{\phpg\posx855\pvpg\posy9295\absw9611\absh3863 \sl-232 \f20 \fs18 \cf0 back
and forth between devices. The block diagram in Fig.{\i \fs18 13-11} shows a s
imple microprocessor-based
4 system using a 4-bit bidirectional data bus. For a data bus to work
properly, each device must be
\fs18 isolated}{\b\i \fs19 from}{\i \fs18 the}{\i \fs18 bus,} by using a{\i \
fs18 three-state}{\i \fs18 buffer.}{\b \f10 \fs17 A} familiar keyboard inpu
t{\fs18 is} shown with an added
2 three-state buffer to disconnect the latched data from the data bus for all bu
t a very short time when
1 the microprocessor sends a LOW{\i \fs18 read} signal. When the buffer
's control input{\b\i \fs19 C} is activated, the
2 latched data drives the data bus lines either HIGH or{\fs19 LOW} de
pending on the data present. The
4 microprocessor then latches this data off the data bus and deactivates the
buffer (control{\b\i \fs19 C} back to
4 HIGH).
55 The three-state buffer shown in block form in Fig.{\i \fs18 13-11} mi
ght be implemented using the TTL
\fs19 74125}{\i \fs18 quad}{\i \fs18 three-state}{\i \fs18 buffer}{\b\i \fs19
IC.}{\b \fs19 A} logic symbol for a single{\i \fs18 noninverting}{\i \fs18 b
uger} is drawn in Fig.{\i \fs18 13-12a. }
\fs19 A} pin diagram{\fs18 of} the{\i \fs18 74125} IC is in Fig.{\i \fs18 13126,} and a truth table is in Fig.{\i \fs18 13-12c.} When the control
t is LOW, data{\fs19 is} passed through the buffer with no inversion
. When the control input goes
, the output of the buffer goes to the{\i \fs18 high-impedance} state
. This is like creating an open
een input{\b\i \fs19 A} and output{\i \fs19 Y} in Fig.{\i \fs18 13-12a.
} Output{\i \fs19 Y} then floats to the voltage level of the data
\par}{\phpg\posx855\pvpg\posy9295\absw9611\absh3863 \sl-237 \f20 \fs18 \cf0 bus
line to which it is connected. \par
}
0 CHAP.{\i0 \fs17 131 }\par
}
}
\par
}
\cf0 Fig.{\fs16 13-11}{\b0 \fs16
Buffers}{\b0 \fs16 used}{\b0 \fs16 to}{\b
0 \fs16 isolate}{\b0 \fs16 devices}{\b0 \fs16 from}{\b0 \fs16 a}{\b0 \fs16
data}{\b0 \fs16 bus }\par
}
8 \cf0 Three-state buffers are commonly built into devices designed to interf
ace with a microcomputer
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-237 \f20 \fs18 \cf0 bus
. Figure 13-11shows the buffer as part of the microprocessor and RAM (random-acc
ess memory or
20 read/write memory). Many devices called{\i \fs19 peripheral}{\i \fs19 i
nterface}{\i \fs19 adapters}{\f10 \fs17 (}{\b\i \f30 \fs21 PIAS)}which contai
n latches,
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-238 \f20 \fs18 \cf0 buf
fers, registers, and control lines are available. These special ICs ar
e available for each specific
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-242 \f20 \fs18 \cf0 mic
roprocessor and take care of the input/output needs of the system.
371 A variety of latches are available in both TTL and CMOS. Latches commonly co
me in 4- or 8-bit
D} flip-flop versions. Some latches have three-state outputs.
375 Many buffer ICs are available using either TTL or CMOS technology. T
TL buffers come with
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-239 \f20 \fs18 \cf0 tot
em-pole, open-collector, or three-state outputs. Buffers may be of the
inverting or noninverting
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-237 \f20 \fs18 \cf0 typ
es. Many buffers, such as the 74125 in Fig. 13-12, allow data to pass through th
e unit only in one
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-242 \f20 \fs18 \cf0 dir
ection.{\b A} variation of the buffer is the{\b\i \fs19 bus}{\i \fs19 transce
iuer} which allows{\i \fs19 two-way} flow to or from{\fs19 a} bus.
buffers identified as part of the microprocessor and RAM in Fig. 13-11are real
ly two-way buffers
\par}{\phpg\posx831\pvpg\posy10421\absw9536\absh2790 \sl-237 \f20 \fs18 \cf0 or
bus transceivers. \par
}
\par
}
}
AP.{\fs17 13 }\par
}
ntrol \par
}
puts \par
}
{\phpg\posx3555\pvpg\posy2030\absw370\absh170 \f20 \fs15 \cf0 \f20 \fs15 \cf0 Da
ta \par
}
tput
\par}{\phpg\posx6449\pvpg\posy2000\absw980\absh332 \sl-179 \f20 \fs15 \cf0 (noni
nverted) \par
}
s12 \cf0 (a){\b0\i0 \f20 \fs15 Logic}{\b0\i0 \f20 \fs15 symbol}{\i0 \f20 \fs1
5 of}{\b0\i0 \f20 \fs15 a}{\b0\i0 \f20 \fs15 three-state}{\b0\i0 \f20 \fs15
buffer }\par
}
\cf0 1c
f0 {\f20 \fs15 1A }
f0 {\f30 \fs18 1Y }\par
}
cf0 4c \par
}
0 -+ \par
}
nputs
Output \par
}
L{\fs17
L }\par
}
cf0 L
\par
}
cf0 H
\par}{\phpg\posx6872\pvpg\posy4984\absw168\absh431 \sl-255 \b \f20 \fs17 \cf0 X
\par
}
fs17 \cf0 H
f10 \fs15 (Z) }\par
}
\cf0 (c){\b0 \f20 \fs15 Truth}{\b0 \f20 \fs15 table }\par
}
\cf0 Fig.{\fs17 13-12}{\b0 \fs17 74125}{\b0 \fs17 quad}{\b0 \fs17 three-st
ate}{\b0 \fs17 buffer}{\b0 \fs17 IC }\par
}
\f10 \fs14 \cf0 4A
\cf0 \fi1283 {\i0 \f30 \fs17 4Y }
\cf0 {\i0 \f30 \fs23 ,-p3c }\par
}
s15 \cf0 (b){\b0\i0 \fs15 Pin}{\b0\i0 \fs15 diagram }\par
}
OLVED PROBLEMS
\f20 \fs19 13.22}{\f20 \fs19 Refer}{\f20 \fs19 to}{\f20 \fs19 Fig.}{\f20 \fs
19 13-9a.}{\f20 \fs19 Why}{\f20 \fs19 does}{\f20 \fs19 the}{\f20 \fs19 out
put}{\f20 \fs19 show}{\f20 \fs19 decimal}{\f20 \fs19 7}{\f20 \fs19 only}{\f2
0 \fs19 when}{\f20 \fs19 the}{\f20 \fs19 key}{\f20 \fs19 is}{\f20 \fs19 pre
ssed}{\f20 \fs19 on}{\f20 \fs19 the }
89 {\f20 \fs19 keyboard}{\f20 \fs19 and}{\f20 \fs19 not}{\f20 \fs19 when}{\f
20 \fs19 it}{\f20 \fs19 is}{\f20 \fs19 released? }

50 {\f20 \fs17 The}{\f20 \fs17 system}{\f20 \fs17 shown}{\f20 \fs17 in}{\f
20 \fs17 Fig.}{\f20 \fs17 13-9a}{\f20 \fs17 does}{\f20 \fs17 not}{\f20 \
fs17 contain}{\f20 \fs17 a}{\f20 \fs17 latch}{\f20 to}{\f20 \fs17 hold
}{\f20 \fs17 the}{\f20 \fs17 data}{\f20 \fs17 at}{\f20 \fs17 the}{\f20 \
fs17 inputs}{\f20 \fs17 to}{\f20 \fs17 the }
98 {\f20 \fs17 decoder.}{\f20 \fs17 To}{\f20 \fs17 latch}{\f20 \fs17 data,}
{\f20 \fs17 the}{\f20 \fs17 system}{\f20 \fs17 must}{\f20 \fs17 be}{\f20 \
fs17 modified}{\f20 \fs17 to}{\f20 \fs17 the}{\f20 \fs17 one}{\f20 \fs17
shown}{\f20 \fs17 in}{\f20 \fs17 Fig.}{\f20 \fs17 13-96. }\par
}
\cf0 13.23{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-13.}{\b0 The}{\b0 7475}{\b
0 \fs19 IC}{\b0 has}{\b0 active }
}
(HIGH,{\fs19 LOW)}{\fs19 enable}{\fs19 inputs. }\par
}
7 \cf0 The bubbles at the enable inputs to the 7475 IC shown in Fig.
13-13 mean these are active LOW
uts. \par
}
\cf0 13.24{\b0 \f20 \fs19
0 \f20 \fs19 13-13.}{\b0 \f20 \fs19 List}{\b0 \f20 \fs19 the}{\b0 \f20 \fs19
mode}{\b0 \f20 \fs18 of}{\b0 \f20 \fs19 operation}{\b0 \f20 \fs19 of}{\b0 \f2
0 \fs19 the}{\b0 \f20 \fs19 7475}{\b0 \f20 \fs19 latch}{\b0 \f20 \fs19 for}
{\b0 \f20 \fs19 each}{\b0 \f20 \fs19 time}{\b0 \f20 \fs19 period. }
}
time period{\b\i \fs16 t}{\b\i \fs16 ,}{\f10 \fs13 =} data enabled
\par}{\phpg\posx1785\pvpg\posy12811\absw2345\absh801 \sl-220 \f20 \fs17 \cf0 tim
e period{\b\i \fs16 t,}{\f10 \fs13 =} data latched
e period{\b\i \fs16 t}{\b\i \fs16 ,}{\f10 \fs13 =} data latched
e period{\b\i \fs16 t,}{\f10 \fs14 =} data enabled \par
}
time period{\b\i \fs16 t,}{\dn006 \f10 \fs11 = }\par
}
ata enabled \par
}
time period{\b\i \fs16 t,}{\f10 \fs13 =} data latched
e period{\b\i \fs16 t}{\b\i \fs16 ,}{\dn006 \f10 \fs11 =} data latched \pa
r
}
. 131 \par
}
}
\par
}
cf0 c1 \par
}
{\phpg\posx5473\pvpg\posy1695\absw541\absh178 \f20 \fs15 \cf0 \f20 \fs15 \cf0 (T
ime) \par
}
\cf0 \\
32 ------ }\par
}
{\phpg\posx5465\pvpg\posy3396\absw844\absh189 \f10 \fs16 \cf0 \f10 \fs16 \cf0 /\par
}
\cf0 4-2 \par
}
13 \cf0 t7 \par
}
11 \cf0 '6
cf0 \fi21 {\b0\i0 \f20 \fs15 1 }\par
}
12 \cf0 t5
cf0 \fi43 {\b0\i0 \fs14 1 }\par
}
cf0 t4 \par
}
\par
}
12 \cf0 t 3
cf0 {\b0\i0 \f10 \fs14 0 }\par
}
14 \cf0 t 2
cf0 \fi51 {\b0\i0 \f10 \fs14 1 }\par
}
puts
}{\phpg\posx5945\pvpg\posy2473\absw459\absh173 \f20 \fs15 \cf0 \fi0 {\fs15 Data
}\par
}
\par
}
\par
}
f0 I \par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
14 \cf0 D1
{\f20 \fs15 D, }
cf0 {\f20 \fs16 D3 }\par
}
{\phpg\posx7035\pvpg\posy3114\absw385\absh339 \f20 \fs14 \cf0 \f20 \fs14 \cf0 4bit
5 latch }\par
}
3
{\b\i Q2 }
{\i \fs16 Q}{\i \fs16 , }
{\b\i \fs11 QO }\par
}
I \par
}
475) \par
}
\par
}
cf0 0 \par
}
cf0 0 \par
}
\par
}
\par
}
cf0 Eo-{\b\i0 \f30 \fs12 1 }\par
}
0 \fs16 \cf0 Fig. 13-13{\b0 \fs17
Latch}{\b0 \fs17 pulse-train}{\b0 \fs17
problem }
f0 {\fs18 13.25}{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18
13-13.}{\b0 \fs18 List}{\b0 \fs18 the}{\b0 \fs18 4-bit}{\b0 \fs18 binary}{\b
0 \fs18 output}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 indicators}{\b0 \fs18
of}{\b0 \fs18 the}{\b0 \fs18 7475}{\b0 \fs19 IC}{\b0 \fs18 for}{\b0 \fs18
each}{\b0 \fs18 time }
fi581 {\b0 \fs18 period. }
f0 \fi591 Solution: \par
}
ime period{\b\i \fs16 t}{\b\i \fs16 ,}{\f10 \fs13 =} 0001 (data enabled)
period{\b\i \fs16 t}{\f10 \fs13
=} 0001 (data latched)
period{\b\i \fs16 t,}{\f10 \fs13 =} 0001 (data latched)
period{\b\i \fs16 t}{\b\i \fs16 ,}{\f10 \fs13 =}{\fs16 1000} (data enab
led) \par
}
ime period{\b\i \fs16 t,}{\dn006 \f10 \fs11 = }\par
}
111 (data enabled) \par
}
ime period{\b\i \fs15 t}{\b\i \fs15 ,}{\f10 \fs13 =}{\fs16 01}11 (data l
atched)
period{\b\i \fs16 t}{\b\i \fs16 ,}{\f10 \fs13 =} 0111 (data latched) \pa
r
}
cf0 13.26{\b0 Each}{\b0 device}{\b0 connected}{\b0 to}{\b0 a}{\b0 dat
a}{\b0 bus}{\b0 (such}{\b0 as}{\b0 the}{\b0 one}{\b0 shown}{\b0 in}{\b0
Fig.}{\b0 13-11)}{\b0 must}{\b0 be}{\b0 isolated }\par
}
rom the bus by a
}
par
}
\cf0 Devices on a data bus are isolated from the bus by using a three-state buf
fer. This buffer{\b is} often built
\par}{\phpg\posx1489\pvpg\posy8775\absw8222\absh392 \sl-220 \f20 \fs17 \cf0 into
the peripheral interface adapter or memory ICs. A two-way buffer{\fs16
is} called a bus transceiver. \par
}
\cf0 13.27{\b0
Refer}{\b0 to} Fig.{\b0 13-11.}{\b0 If}{\b0 the}{\b0 \
fs18 9}{\b0 were}{\b0 pressed}{\b0 on}{\b0 the}{\b0 keyboard,}{\b0
what}{\b0 might}{\b0 be}{\b0 the}{\b0 sequence}{\b0 \fs18 of }
fi584 {\b0 events}{\b0 for}{\b0 the}{\b0 microprocessor}{\b0 \fs19 to}{\b0
read}{\b0 this}{\b0 number? }
fi950 {\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 13-11.}{\b
0 \fs17 Closing}{\b0 \fs17 the}{\b0 \fs17 9}{\b0 \fs17 key}{\b0 \fs17 c
auses}{\b0 \fs17 binary}{\b0 \fs17 1001}{\b0 \fs17 to}{\b0 \fs17 be}{\b0
\fs17 latched}{\b0 \fs17 and}{\b0 \fs17 the}{\b0 \fs17 microprocessor }
fi581 {\i \fs16 interrupted}{\b0 \fs17
(signaled}{\b0 \fs17 that}{\b0 \fs17
keyboard}{\b0 \fs17 is}{\b0 \fs17 sending}{\b0 \fs17 data).}{\b0 \fs17
The}{\b0 \fs17 microprocessor}{\b0 \fs17 completes}{\b0 \fs17 its}{\b0 \
fs17 current}{\b0 \fs17 task}{\b0 \fs17 and }
fi583 {\b0 \fs17 sends}{\b0 \fs17 a}{\b0 \fs17 LOW}{\i \fs16 read}{\b0 \fs
17 signal}{\b0 \fs17 to}{\b0 \fs17 the}{\b0 \fs17 three-state}{\b0 \fs17
buffer.}{\b0 \fs17 Data}{\b0 \fs17 (binary}{\b0 \fs17 1001)}{\b0 \fs17
flows}{\b0 \fs17 through}{\b0 \fs17 the}{\b0 \fs17 buffer}{\b0 \fs17 onto
}{\b0 \fs17 the }
fi583 {\b0 \fs17 data}{\b0 \fs17 bus.}{\b0 \fs17 The}{\b0 \fs17 microprocess
or}{\b0 \fs17 latches}{\b0 \fs17 this}{\b0 \fs17 data}{\b0 \fs17 off}{\b0
\fs17 the}{\b0 \fs17 data}{\b0 \fs17 bus}{\b0 \fs17 and}{\b0 \fs17 disa
bles}{\b0 \fs17 the}{\b0 \fs17 read}{\b0 \fs17 signal}{\b0 \fs17 (read}{\b
0 \fs17 output }
fi584 {\b0 \fs17 back}{\b0 \fs17 to}{\b0 \fs17 HIGH).}{\b0 \fs17 The}{\b0 \
fs17 outputs}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 three-state}{\b0 \f
s17 buffer}{\b0 \fs17 return}{\b0 \fs17 to}{\b0 \fs17 their}{\b0 \fs17
high-impedance}{\b0 \fs17 state. }\par
}
\cf0 13.28{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-11.}{\fs19 If}{\b0 the}{\
b0 latched}{\b0 data}{\b0 is}{\b0 binary}{\b0 1001}{\b0 and}{\b0 the}{\
b0 control}{\b0\i \fs18 C}{\b0 input}{\b0 \fs19 to}{\b0 the}{\b0 buffer}
{\b0 \fs18 is }
\fi584 {\b0 \fs19 HIGH,}{\b0 then}{\b0 the}{\b0 outputs}{\b0 of}{\b0 the}{
\b0 three-state}{\b0 buffer}{\b0 are}{\b0 at}{\b0 what}{\b0 logic}{\b0
levels? }
\fi944 {\b0 \fs17 The}{\b0 \fs17 HJGH}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \f
s17 control}{\i \f30 C}{\b0 \fs17
pin}{\b0 \fs16 of}{\b0 \fs17 the}{\b
0 \fs17 three-state}{\b0 \fs17 buffer}{\b0 \fs17 places}{\b0 \fs17 the}{
\b0 \fs17 outputs}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs17 buffers}{\b0 \
fs17 in}{\b0 \fs17 a }
\fi590 {\b0 \fs17 high-impedance}{\b0 \fs17 state.}{\b0 \fs17 That}{\b0 \fs17
means}{\b0 \fs17 the}{\b0 \fs17 buffer}{\b0 \fs17 outputs}{\b0 \fs17 w
ill}{\b0 \fs16 float}{\b0 \fs17 to}{\b0 \fs17 whatever}{\b0 \fs17 logic}
{\b0 \fs17 levels}{\b0 \fs17 exist}{\b0 \fs17 on}{\b0 \fs17 the}{\b0 \fs17
data }
\fi583 {\b0 \fs17 bus. }\par
}
0 324 \par
}
}
AP.{\fs17 13 }\par
}
cf0 13.29{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0\i \fs18 13-12
.}{\b0 \fs18 The}{\b0\i \fs18 74125}{\b0 \fs18 IC}{\b0 \fs18 contains}{\b0
\fs18 four }
i580 {\b0 \fs18 buffers. }
}
inverting, noninverting) three-state \par
}
efer to Fig. 13-12. The{\fs17 74125} IC contains four noninverting threestate buffers. \par
}
\cf0 13.30{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0\i \fs18 1311.}{\b0 \fs18 What}{\b0 \fs18 might}{\b0 \fs18 be}{\b0 \fs18 the}{\b0 \fs
18 difference}{\b0 \fs18 between}{\b0 \fs18 the}{\b0 \fs18 keyboard}{\b0 \
fs18 buffers}{\b0 \fs18 compared}{\b0 \fs18 to }
fi589 {\b0 \fs18 the}{\b0 \fs18 buffers}{\b0 \fs18 in}{\b0 \fs18 the}{\b0 \fs
18 RAM? }
fi944 {\b0 \fs16 The}{\b0 \fs16 buffers}{\b0 \fs16 between}{\b0 \fs16 the}
{\b0 \fs16 keyboard}{\b0 \fs16 and}{\b0 \fs16 the}{\b0 \fs16 data}{\b0 \
fs16 bus}{\b0 \fs16 pass}{\b0 \fs16 information}{\b0 \fs16 in}{\b0 \fs16
only}{\b0 \fs16 one}{\b0 \fs16 direction}{\b0 \fs16 (onto}{\b0 \fs16 th
e }
fi591 {\b0 \fs16 data}{\b0 \fs16 bus).}{\b0 \fs16 However,}{\b0 \fs16 the}
{\b0 \fs16 RAM}{\b0 \fs16 buffers}{\b0 \fs16 must}{\b0 \fs16 be}{\b0 \fs
16 able}{\b0 \fs16 to}{\b0 \fs16 send}{\b0 \fs16 data}{\b0 \fs16 to}{\

b0 \fs16 and}{\b0 \fs16 accept}{\b0 \fs16 data}{\b0 \fs16 from}{\b0 \fs1
6 the}{\b0 \fs16 data}{\b0 \fs16 bus. }\par
}
\cf0 13-6{\fs18
DIGITAL}{\fs18 DATA}{\fs18 TRANSMISSION }
fi360 {\b0 \fs18 Digital}{\b0 \fs18 data}{\b0 \fs18 transmission}{\b0 \fs18
is}{\b0 \fs18 the}{\b0 \fs18 process}{\b0 \fs18 of}{\b0 \fs18 sending}
{\b0 \fs18 information}{\b0 \fs18 from}{\b0 \fs18 one}{\b0 \fs18 part}{\
b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs18 system}{\b0 \fs18 to }
\b0 \fs18 another.}{\b0 \fs18 Sometimes}{\b0 \fs18 the}{\b0 \fs18 locations}{
\b0 \fs18 are}{\b0 \fs18 close,}{\b0 \fs18 and}{\b0 \fs18 sometimes}{\b0 \fs
18 they}{\b0 \fs18 are}{\b0 \fs18 many}{\b0 \fs18 miles}{\b0 \fs18 apart.}{
\b0 \fs18 Either}{\b0 \fs18 parallel }
\b0 \fs18 or}{\b0 \fs18 serial}{\b0 \fs18 data}{\b0 \fs18 transmission}{\b
0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18 used.}{\b0 \fs18 Serial}{\b0 \fs18
data}{\b0 \fs18 transmission}{\b0 \fs18
is}{\b0 \fs18 more}{\b0 \fs18
useful}{\b0 \fs18 when}{\b0 \fs18 sending }
\b0 \fs18 information}{\b0 \fs18 long}{\b0 \fs18 distances. }
fi359 {\b0 \fs18 Figure}{\b0\i \fs18 13-14a}{\b0 \fs18 illustrates}{\b0 \fs18
the}{\b0 \fs18 idea}{\b0 \fs18 of}{\b0\i \fs18 parallel}{\b0\i \fs18 data
}{\b0\i \fs18 transmission.}{\b0 \fs18 This}{\b0 \fs18 is}{\b0 \fs18 typica
l}{\b0 \fs18 inside}{\b0 \fs18 microproces- }
\b0 \fs18 sor-based}{\b0 \fs18 systems}{\b0 \fs18 where}{\b0 \fs18 entire}{\b
0 \fs18 groups}{\b0 \fs18 of}{\b0 \fs18 bits}{\b0 \fs18 (called}{\b0\i \fs18
words)}{\b0 \fs18 are}{\b0 \fs18 transferred}{\b0 \fs18 at}{\b0 \fs18 th
e}{\b0 \fs18 same}{\b0 \fs18 time.}{\b0 \fs18 In}{\b0 \fs18 Fig. }
\b0\i \fs18 13-14a}{\b0 \fs18 eight}{\b0 \fs18 lines}{\b0 \fs18 are}{\b0 \fs
18 needed}{\b0 \fs18 to}{\b0 \fs18 transmit}{\b0 \fs18 the}{\b0 \fs18 pa
rallel}{\b0 \fs18 data.}{\fs18 A}{\b0 \fs18 parallel}{\b0 \fs18 system}{\b
0 \fs18 is}{\b0 \fs18 used}{\b0 \fs18 when}{\b0 \fs18 speed}{\b0 \fs18 i
s }
\b0 \fs18 important.}{\b0 \fs18 The}{\b0 \fs18 disadvantage}{\b0 \fs18 of}{\b
0 \fs18 parallel}{\b0 \fs18 transmission}{\b0 \fs18 is}{\b0 \fs18 the}{\b
0 \fs18 cost}{\b0 \fs18 of}{\b0 \fs18 providing}{\b0 \fs18 many}{\b0 \fs18
registers,}{\b0 \fs18 latches, }
\b0 \fs18 and}{\b0 \fs18 conductors}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs
18 many}{\b0 \fs18 bits}{\b0 \fs18 of}{\b0 \fs18 data.}{\b0 \fs18 The}{
\b0 \fs18 data}{\b0 \fs18 bus}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18
Fig.}{\b0\i \fs18 13-11}{\b0 \fs18 is}{\b0 \fs18 another}{\b0 \fs18 exam
ple}{\b0 \fs18 of }
\b0 \fs18 parallel}{\b0 \fs18 data}{\b0 \fs18 transmission}{\b0 \fs18 inside}
{\b0 \fs18 a}{\b0 \fs18 microcomputer.}{\b0 \fs18 In}{\b0 \fs18 the}{\b0 \fs
18 case}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 bus}{\b0 \fs18 system,}{\b0
\fs18 data}{\b0 \fs18 can}{\b0 \fs18 flow}{\b0 \fs18 in}{\b0 \fs18 both }
\b0 \fs18 directions}{\b0 \fs18 and}{\b0 \fs18 additional}{\b0 \fs18 bufferin
g}{\b0 \fs18 for}{\b0 \fs18 each}{\b0 \fs18 device}{\b0 \fs18 connected}{\b0
\fs18 to}{\b0 \fs18 the}{\b0 \fs18 bus}{\b0 \fs18 is}{\b0 \fs18 required.
}

fi365 {\b0 \fs18 Figure}{\b0\i \fs18 13-14b}{\b0 \fs18 illustrates}{\b0 \fs18
the}{\b0 \fs18 idea}{\b0 of}{\b0\i \fs18 serial}{\b0\i \fs18 data}{\b0\i \
fs18 transmission.}{\b0 \fs18 There}{\b0 \fs18 is}{\b0 \fs18 only}{\b0 \fs18
one}{\b0 \fs18 transmission}{\b0 \fs18 line, }
\b0 \fs18 and}{\b0 \fs18 data}{\b0 \fs18 is}{\b0 \fs18 sent}{\b0 \fs18 seria
lly}{\b0 \fs18 (one}{\b0 \fs18 bit}{\b0 \fs18 at}{\b0 \fs18 a}{\b0 \fs18
time)}{\b0 \fs18 over}{\b0 \fs18 the}{\b0 \fs18 line.}{\b0 \fs18 One}{\b0 \
fs18 format}{\b0 \fs18 for}{\b0 \fs18 sending}{\b0 \fs18 asynchronous}{\b0
\fs18 data }
\b0 \fs18 serially}{\b0 \fs18 is}{\b0 \fs18 shown}{\b0 \fs18 in}{\b0 \fs18 F
ig.}{\b0\i \fs18 13-14b.}{\b0 \fs18 A}{\b0 \fs18 7-bit}{\b0 \fs18 ASCII}{\b0
\fs18 code}{\b0 \fs18 (see}{\b0 \fs18 ASCII}{\b0 \fs18 code}{\b0 \fs18 in}
{\b0 \fs18 Fig.}{\b0\i \fs18 2-11)}{\b0 \fs18 can}{\b0 \fs18 be}{\b0 \fs18
sent}{\b0 \fs18 by}{\b0 \fs18 using }
\b0 \fs18 this}{\b0 \fs18 serial}{\b0 \fs18 format.}{\b0 \fs18 The}{\b0 \fs18
line}{\b0 \fs18 is}{\b0 \fs18 normally}{\b0 \fs18 HIGH,}{\b0 \fs18 as}{\b0
\fs18 shown}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 left}{\b0 \fs18 of}{\b
0 \fs18 the}{\b0 \fs18 waveform.}{\b0 \fs18 The}{\b0 \fs18 LOW}{\b0\i \fs18
start }
\b0\i \fs18 bit}{\b0 \fs18 signals}{\b0 \fs18 the}{\b0 \fs18 start}{\b0 of
}{\b0 \fs18 a}{\b0 \fs18 word.}{\b0 \fs18 The}{\b0 \fs18 data}{\b0 \fs18
bits}{\b0 \fs18 are}{\b0 \fs18 transmitted}{\b0 \fs18 one}{\b0 \fs18 at}{
\b0 \fs18 a}{\b0 \fs18 time}{\b0 \fs18 with}{\b0 \fs18 the}{\b0 \fs18 LS
B}{\b0\i \fs18 (Do)}{\b0 \fs18 first. }
\b0 \fs18 After}{\b0 \fs18 the}{\b0 \fs18 7}{\b0 \fs18 data}{\b0 \fs18 bits}
{\b0\i \fs18 (Do}{\b0 \f10 \fs15 -}{\b0\i \fs18 D6),}{\b0 \fs18 a}{\b0 \fs18
parity}{\b0 \fs18 bit}{\b0 \fs18 for}{\b0 \fs18 error}{\b0 \fs18 detection}{
\b0 \fs18 is}{\b0 \fs18 transmitted.}{\b0 \fs18 Finally,}{\b0 \fs18 two}{\b0
\fs18 HIGH}{\b0\i \fs18 stop }
f0 \fi3266 {\b0 \f10 \fs23 n}{\b0 \f10 \fs17
I }\par
}
\par
}
.;ice \par
}
vice
0 {\fs15 2 }\par
}
U{\fs34
I }\par
}
\cf0 (a){\i0 \f20 \fs14 Parallel}{\i0 \f20 \fs14 data}{\i0 \f20 \fs14 transm
issions }\par
}
0 \fs14 \cf0 ( h ){\i0 \fs14 Serial}{\i0 \fs14 data}{\i0 \fs14 transmissions
}
cf0 {\b\i0 \fs16 Fig.}{\b\i0 \f30 \fs17 13-14}{\i0 \fs16 Digital}{\i0 \fs16
data}{\i0 \fs16 transmission}{\i0 \fs16 methods }\par
}
0 CHAP.{\fs16 131 }\par
}
HER DEVICES AND TECHNIQIJES \par
}
f0 325 \par
}
\cf0 bits{\i0 \fs18 indicating}{\i0 \fs18 that}{\i0 \fs18 the}{\i0 \fs18
character}{\i0 \fs18 is}{\i0 \fs18 complete}{\i0 \fs18 are}{\i0 \fs18 sen
t.}{\i0 \fs18 These}{\fs18 11}{\i0 \fs18 bits}{\i0 \fs18 transmit}{\i0 \
fs18 one}{\i0 \fs18 ASCII}{\i0 \fs18 character }
\i0 \fs18 representing}{\i0 \fs18 a}{\i0 \fs18 letter,}{\i0 \fs18 number,}{\i
0 \fs18 or}{\i0 \fs18 control}{\i0 \fs18 code. }
fi365 {\i0 \fs18 Note}{\i0 \fs18 that}{\i0 \fs18 both}{\i0 \fs18 devices}{\f
s18 1}{\i0 \fs18 and}{\i0 \fs18 2}{\i0 \fs18 in}{\i0 \fs18 the}{\i0 \fs18
parallel}{\i0 \fs18 transmission}{\i0 \fs18 system}{\i0 \fs18 in}{\i0 \fs
18 Fig.} 13-14a{\i0 \fs18 would}{\i0 \fs18 require }
\i0 \fs18 parallel-in}{\i0 \fs18 parallel-out}{\i0 \fs18 type}{\i0 \fs18 r
egisters.}{\i0 \fs18 In}{\i0 \fs18 the}{\i0 \fs18 serial}{\i0 \fs18 data
}{\i0 \fs18 transmission}{\i0 \fs18 system}{\i0 \fs18 shown}{\i0 \fs18 in
}{\i0 \fs18 Fig.} 13-14{\b \fs19 b, }
\i0 \fs18 device}{\fs19 1}{\i0 \fs18 would}{\i0 \fs18 require}{\i0 \fs18
a}{\i0 \fs18 parallel-in}{\i0 \fs18 serial-out}{\i0 \fs18 register.}{\i0
\fs18 Device}{\i0 \fs19 2}{\i0 \fs18 in}{\i0 \fs18 Fig.} 13-14b{\i0 \fs
18 would}{\i0 \fs18 require}{\i0 \fs18 a }
\i0 \fs18 serial-in}{\i0 \fs18 parallel-out}{\i0 \fs18 storage}{\i0 \fs18 un
it}{\i0 \fs18 to}{\i0 \fs18 reassemble}{\i0 \fs18 the}{\i0 \fs18 data}{\i0
\fs18 back}{\i0 \fs18 into}{\i0 \fs18 parallel}{\i0 \fs18 format. }
fi371 {\i0 \fs18 Manufacturers}{\i0 \fs18 produce}{\i0 \fs18 specialized}{\i0
\fs18 complex}{\i0 ICs}{\i0 \fs18 that}{\i0 \fs18 perform}{\i0 \fs18 the}{\
i0 \fs18 task}{\i0 \fs18 of}{\i0 \fs18 serial}{\i0 \fs18 data}{\i0 \fs18 tr
ansmission. }
\i0 \fs18 One}{\i0 \fs18 such}{\i0 \fs18 device}{\i0 \fs18 is}{\i0 \fs18 the
} universal asynchronous receiver-transmitter{\i0 \f10 \fs20 ,}{\i0 \fs18 or}{\
b \fs19 UART.}{\i0 \fs18 The}{\i0 \fs18 UART}{\i0 \fs18 takes}{\i0 \fs18 car
e}{\i0 \fs18 of }
\i0 \fs18 the}{\i0 \fs18 parallel-to-serial}{\i0 \fs18 and}{\i0 \fs18 seri
al-to-parallel}{\i0 \fs18 conversions}{\i0 \fs18 for}{\i0 \fs18 the}{\i0 \
fs18 transmitter}{\i0 \fs18 and}{\i0 \fs18 receiver.}{\i0 \fs18 A}{\i0 \
fs18 typical }
\i0 \fs18 UART}{\i0 \fs18 is}{\i0 \fs18 the} AY-5-1013{\i0 \fs18 by}{\i0
\fs18
General}{\i0 \fs18
Instrument.}{\i0 \fs18
Other}{\i0 \fs18 comp
lex}{\i0 \fs18
ICs}{\i0 \fs18 that}{\i0 \fs18
handle}{\i0 \fs18
seria
l}{\i0 \fs18 data }

\i0 \fs18 transmission}{\i0 \fs18 are}{\i0 \fs18 the}{\i0 \fs18 Motorola}{
\i0 6850} asynchronous communication interface adapter{\b \f10 \fs17 (ACL
4)}{\i0 \fs18 and}{\i0 \fs18 the }
\i0 \fs18 Intel}{\i0 825}{\fs18 1} unir;ersalsynchronous-asynchronous receiver
-transmitter{\b (USART). }
fi371 {\i0 \fs18 Serial}{\i0 \fs18 data}{\i0 \fs18 transmissions}{\i0 \fs18 c
an}{\i0 \fs18 be}{\i0 \fs18 either}{\i0 \fs18 asynchronous}{\i0 \fs18 or}{\i
0 \fs18 synchronous.}{\i0 \fs18 Asynchronous}{\i0 \fs18 formats}{\i0 \fs18 n
eed }
\i0 \fs18 start}{\i0 \fs18 and}{\i0 \fs18 stop}{\i0 \fs18 bits}{\i0 \fs18 (s
ee}{\i0 \fs18 Fig.} 13-146).{\i0 \fs18 There}{\i0 \fs18 are}{\i0 \fs18 also}{
\i0 \fs18 several}{\i0 \fs18 synchronous}{\i0 \fs18 serial}{\i0 \fs18 protoc
ols.}{\i0 \fs18 Two}{\i0 \fs18 of}{\i0 \fs18 them }
\i0 \fs18 are}{\i0 \fs19 IBM's} binary synchronous protocol{\b (BISYNC)}{\i0
\fs18 and}{\i0 \fs18 IBM's} synchronous data link control{\fs19 (SDLC).
}
fi365 {\i0 \fs18 The}{\i0 \fs18 speed}{\i0 \fs18 at}{\i0 \fs18 which}{\i0 \fs
18 serial}{\i0 \fs18 data}{\i0 \fs18 is}{\i0 \fs18 transmitted}{\i0 \fs18
is}{\i0 \fs18 referred}{\i0 \fs18 to}{\i0 \fs18 as,}{\i0 \fs18 the} baud ra
te.{\b\i0 \fs18 As}{\i0 \fs18 an}{\i0 \fs18 example,}{\i0 \fs18 look }
\i0 \fs18 at}{\i0 \fs18 Fig.} 13-14b.{\i0 \fs18 It}{\i0 \fs18 takes}{\fs18
11}{\i0 \fs18 bits}{\i0 \fs18 to}{\i0 \fs18 send}{\i0 \fs18 a}{\i0 \fs18 si
ngle}{\i0 \fs18 character.}{\i0 \fs18 If} 10{\i0 \fs18 characters}{\i0 \fs18
per}{\i0 \fs18 second}{\i0 \fs18 are}{\i0 \fs18 transmitted, }
\i0 \fs18 then} 110{\i0 \fs18 bits}{\i0 \fs18 are}{\i0 \fs18 sent}{\i0 \f
s18 per}{\i0 \fs18 second.}{\i0 \fs18 The}{\i0 \fs18 rate}{\i0 \fs18 o
f}{\i0 \fs18 data}{\i0 \fs18 transfer}{\i0 \fs18 will}{\i0 \fs18 then}{\
i0 \fs18 be}{\i0 110} baud (110{\i0 \fs18 bits}{\i0 \fs18 per }
\i0 \fs18 second).}{\i0 \fs18 Confusion}{\i0 \fs18 sometimes}{\i0 \fs18 occur
s}{\i0 \fs18 if}{\i0 \fs18 baud}{\i0 \fs18 rate}{\i0 \fs19 is}{\i0 \fs18 co
mpared}{\i0 \fs18 with} data{\i0 \fs18 bits}{\i0 \fs18 transmitted}{\i0 \fs
18 per}{\i0 \fs18 second. }
\i0 \fs18 In}{\i0 \fs18 the}{\i0 \fs18 above}{\i0 \fs18 example,}{\i0 \fs18
the}{\i0 \fs18 10}{\i0 \fs18 words}{\i0 \fs18 transmitted}{\i0 \fs18 per}{\
i0 \fs18 second}{\i0 \fs18 contain}{\i0 \fs18 only}{\i0 \fs19 70}{\i0 \fs18
data}{\i0 \fs18 bits.}{\i0 \fs18 Therefore,} 110
\i0 \fs18 baud}{\i0 \fs18 equals}{\i0 \fs18 only}{\i0 \fs18 70}{\i0 \fs18 d
ata}{\i0 \fs18 bits}{\i0 \fs18 per}{\i0 \fs18 second. }
fi372 {\i0 \fs18 Many}{\i0 \fs18 microcomputer}{\i0 \fs18 owners}{\i0 \fs18
use}{\i0 \fs18 parallel}{\i0 \fs18 and}{\i0 \fs18 serial}{\i0 \fs18 da
ta}{\i0 \fs18 transmission}{\i0 \fs18 when}{\i0 \fs18 interfacing}{\i0 \fs
18 with }
\i0 \fs18 peripheral}{\i0 \fs18 equipment.}{\i0 \fs18 They}{\i0 \fs18 may}{
\i0 \fs18 use}{\i0 \fs18 either}{\i0 \fs18 parallel}{\i0 \fs18 or}{\i0 \
fs18 serial}{\i0 \fs18 interfaces}{\i0 \fs18 for}{\i0 \fs18 their}{\i0 \
fs18 printers.}{\i0 \fs18 They}{\i0 \fs18 may }

\i0 \fs18 use} modems{\i0 \fs18 (modulator-demodulators)}{\i0 \fs18 for}{\i0
\fs18 sending}{\i0 \fs18 and}{\i0 \fs18 receiving}{\i0 \fs18 data}{\i0 \fs1
8 over}{\i0 \fs18 phone}{\i0 \fs18 lines.}{\i0 \fs18 Some}{\i0 \fs18 seria
l }
\i0 \fs18 interface}{\i0 \fs18 devices}{\i0 \fs18 used}{\i0 \fs18 with}{\i0 \
fs18 home}{\i0 \fs18 computers}{\i0 \fs18 send}{\i0 \fs18 and}{\i0 \fs18 re
ceive}{\i0 \fs18 data}{\i0 \fs18 at}{\i0 \fs18 speeds}{\i0 \fs18 of}{\i0 \fs
18 9600}{\i0 \fs18 baud. }\par
}
LVED PROBLEMS
f20 \fs18 13.31}{\f20 \fs18 Digital}{\f20 \fs18 data}{\f20 \fs18 can}{\f20 \
fs18 be}{\f20 \fs18 transmitted}{\f20 \fs18 in}{\f20 \fs18 either}{\f20 \fs1
8 parallel}{\f20 \fs18 or }
6 {\b \f20 \fs16 Solution: }\par
}
{\phpg\posx6755\pvpg\posy8237\absw530\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 fo
rm. \par
}
igital data can be transmitted in either parallel or serial form. \par
}
f0 13.32 \par
}
\cf0 (parallel, serial) data transmission is the process{\fs19 of} transferri
ng whole data words at the
\par}{\phpg\posx1469\pvpg\posy9690\absw8390\absh973 \sl-242 \f20 \fs18 \cf0 same
time.
\fs16 Solution: }
62 {\fs16 Parallel}{\fs16 data}{\fs16 transmission}{\fs16 is}{\fs16 the}{\f
s16 process}{\fs16 of}{\fs16 transferring}{\fs16 whole}{\fs16 data}{\fs
16 words}{\fs16 at}{\fs16 the}{\fs16 same}{\fs16 time. }\par
}
\cf0 13.33{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0\i \fs19 13-14
a.}{\b0 \fs18 Device}{\b0 \fs18 1}{\b0 \fs18 must}{\b0 \fs18 be}{\b0 \fs18
a }
}
{\phpg\posx5783\pvpg\posy11371\absw414\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 in-- \par
}
-out type register. \par
}
Device{\b \fs16 1} (Fig.{\b 13-14a)} must be a parallel-in parallel-out
register. \par
}
\cf0 13.34{\b0 \fs18
Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0\i \fs19 13-1
46.}{\b0 \fs18 Device}{\b0 \fs18 2}{\b0 \fs18 must}{\b0 \fs18 be}{\b0 \fs18
a }
}
{\phpg\posx5775\pvpg\posy12827\absw256\absh211 \f20 \fs18 \cf0 \f20 \fs18 \cf0 in \par
}
-out register. \par
}
Device{\b \fs17 2} (Fig.{\b 13-14b)} must be{\b \fs16 a} serial-in parallel
-out device. \par
}
\par
}
}
AP. 13 \par
}
cf0 13.35{\b0 \fs18
1.}{\b0 \fs18 The}{\b0 \fs18 data}{\b0 \fs18 bus}{\b0 \fs18 system}{\b0 \
fs18 is}{\b0 \fs18 an}{\b0 \fs18 example}{\b0 \fs18 of }
i595 {\b0 \fs18 transmission. }
}
parallel, serial) data \par
}
\cf0 A data bus system is an example of parallel data transmission.
Bus systems are widely used{\fs17 in }
\par}{\phpg\posx1467\pvpg\posy2237\absw8233\absh390 \sl-218 \f20 \fs17 \cf0 micr
oprocessor-based equipment, including microcomputers. \par
}
cf0 13.36{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 the}{\b0 \fs18 wavefo
rm}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 13-14b.}{\b0 \fs18 The}{\b0 \
fs19 11}{\b0 \fs18 bits}{\b0 \fs18 transmit}{\b0 \fs18 one }
i593 {\b0 \fs18 character}{\b0 \fs18 representing}{\b0 \fs18 a}{\b0 \fs18 le
tter,}{\b0 \fs18 number,}{\b0 \fs18 or}{\b0 \fs18 control}{\b0 \fs18 code. }
i948 {\b0 \fs17 The}{\b0 \fs17 11}{\b0 \fs17 bits}{\b0 \fs17 shown}{\b0 \fs
17 in}{\b0 \fs17 Fig.}{\b0 \fs17 13-14b}{\b0 \fs17 serially}{\b0 \fs17 tr
ansmit}{\b0 \fs17 one}{\b0 \fs17 ASCII}{\b0 \fs17 character. }\par
}
ASCII,{\fs18 Basic) }\par
}
\cf0 13.37{\b0 \fs18 List}{\b0 \fs18 at}{\b0 \fs18 least}{\b0 \fs18 one}{\b
0 \fs18 complex}{\b0 \fs19 IC}{\b0 \fs18 that}{\b0 \fs18 can}{\b0 \fs18 han
dle}{\b0 \fs18 the}{\b0 \fs18 task}{\b0 \fs18 of}{\b0 \fs18 serial}{\b0 \fs1
8 data}{\b0 \fs18 transmission. }
fi946 {\b0 \fs17 Several}{\b0 \fs17 complex}{\b0 \fs17 ICs}{\b0 \fs17 used
}{\b0 \fs17 for}{\b0 \fs17 serial}{\b0 \fs17 data}{\b0 \fs17 transmissio
n}{\b0 \fs17 are}{\b0 \fs17 available}{\b0 \fs17 from}{\b0 \fs17 manufac
turers.}{\b0 \fs17 Three}{\b0 \fs17 of }
fi590 {\b0 \fs17 these}{\b0 \fs17
specialized}{\b0 \fs17 ICs}{\b0 \fs17 a
re}{\b0 \fs17 the}{\b0 \fs17
universal}{\b0 \fs17 asynchronous}{\b0 \fs17
receiver-transmitter}{\b0 \fs17
(UART),}{\b0 \fs17 the}{\b0 \fs17
asy
nchronous }
fi586 {\b0 \fs17 communication}{\b0 \fs17 interface}{\b0 \fs17
adapter}{\b0
\fs17 (ACIA),}{\b0 \fs17 and}{\b0 \fs17 the}{\b0 \fs17 universal}{\b0 \
fs17 synchronous-asynchronous}{\b0 \fs17 receiver-trans- }
fi592 {\b0 \fs17 mitter}{\b0 \fs17 (USART). }
f0 13.38{\b0 \fs19 A}{\b0 \fs18
(modem,}{\b0 \fs18 parallel-i
n}{\b0 \fs18 parallel-out}{\b0 \fs18 register)}{\b0 \fs18 is}{\b0 \fs18 t
he}{\b0 \fs18 complex}{\b0 \fs18 device}{\b0 \fs18 used}{\b0 \fs18 to}{\
b0 \fs18 send}{\b0 \fs18 and }
fi592 {\b0 \fs18 receive}{\b0 \fs18 serial}{\b0 \fs18 data}{\b0 \fs18 over}{\
b0 \fs18 telephone}{\b0 \fs18 lines. }
fi941 {\b0 \fs17 A}{\b0 \fs17 modem}{\b0 \fs17 (modulator-demodulator)}{\b0 \
fs17 is}{\b0 \fs17 the}{\b0 \fs17 device}{\b0 \fs17 used}{\b0 \fs17 to}{
\b0 \fs17 send}{\b0 \fs17 and}{\b0 \fs17 receive}{\b0 \fs17 data}{\b0 \fs
17 over}{\b0 \fs17 phone}{\b0 \fs17 lines. }\par
}
\cf0 13-7{\fs18
PROGRAMMABLE}{\fs18 LOGIC}{\fs18 ARRAYS }
fi360 {\b0 \fs19 A}{\b0 \fs19 programmable}{\b0 \fs19 logic}{\b0 \fs19 array
}{\b0\i \fs19 (}{\b0\i \fs19 P}{\b0\i \fs19 U}{\b0\i \fs19 )}{\b0 \fs18 is}
{\b0 \fs18 an}{\b0 \fs19 IC}{\b0 \fs18 that}{\b0 \fs18 can}{\b0 \fs18 be}{\
b0 \fs18 programmed}{\b0 \fs18 to}{\b0 \fs18 execute}{\b0 \fs18 a}{\b0 \fs1
8 complex}{\b0 \fs18 logic }
\b0 \fs18 function.}{\b0 \fs18 They}{\b0 \fs18 are}{\b0 \fs18 commonly}{\b0 \
fs18 used}{\b0 \fs18 to}{\b0 \fs18 implement}{\b0 \fs18 combinational}{\b0
\fs18 logic,}{\b0 \fs18 but}{\b0 \fs18 some}{\b0 \fs19 PLAs}{\b0 \fs18 can
}{\b0 \fs18 be}{\b0 \fs18 used}{\b0 \fs18 to }
\b0 \fs18 implement}{\b0 \fs18 sequential}{\b0 \fs18 logic}{\b0 \fs18 desig
ns.}{\b0 \fs18 The}{\b0 \fs19 PLA}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs18 one
-package}{\b0 \fs18 solution}{\b0 \fs18 to}{\b0 \fs18 many}{\b0 \fs18 logic
}{\b0 \fs18 problems}{\b0 \fs18 that }
\b0 \fs18 may}{\b0 \fs18 have}{\b0 \fs18 many}{\b0 \fs18 inputs}{\b0 \fs18 a
nd}{\b0 \fs18 multiple}{\b0 \fs18 outputs.}{\b0 \fs18 Programmable}{\b0 \fs18

logic}{\b0 \fs18 arrays}{\b0 \fs18 are}{\b0 \fs18 closely}{\b0 \fs18 relat
ed}{\b0 \fs18 to}{\b0 \fs18 PROMS }
\b0 \fs18 and}{\b0 \fs18 are}{\b0 \fs18 programmed}{\b0 \fs18 much}{\b0 \f
s18 like}{\b0 \fs18 a}{\b0 \fs18 PROM.}{\b0 \fs19 A}{\b0 \fs19 PLA}{\b
0 \fs18 may}{\b0 \fs18 also}{\b0 \fs18 be}{\b0 \fs18 called}{\b0 \fs18
a}{\b0 \fs19 programmable}{\b0 \fs19 logic}{\i \fs19 device }
\b0\i \fs19 (PLD).}{\b0 \fs18 Both}{\b0 \fs19 PLA}{\b0 \fs18 and}{\b0 \fs19
PLD}{\b0 \fs18 seem}{\b0 \fs18 to}{\b0 \fs18 be}{\b0 \fs18 generic}{\b0 \fs
18 terms}{\b0 \fs18 used}{\b0 \fs18 for}{\b0 \fs18 these}{\b0 \fs18 progr
ammable}{\b0 \fs18 logic}{\b0 \fs18 units.}{\b0 \fs18 One }
\b0 \fs18 popular}{\b0 \fs18 programmable}{\b0 \fs18 logic}{\b0 \fs18 devic
e}{\b0 \fs18 is}{\b0 \fs18 the}{\i \fs19 PAL,@}{\b0 \fs19 (programmable}{\
b0 \fs19 array}{\b0 \fs19 logic),}{\b0 \fs18 available}{\b0 \fs18 from}{\b0
\fs18 several }
\b0 \fs18 manufacturers. }
fi360 {\b0 \fs18 Using}{\b0 \fs19 PLDs}{\b0 \fs18 cuts}{\b0 \fs18 cost}{\b0 \
fs18 because}{\b0 \fs18 fewer}{\b0 \fs19 ICs}{\b0 \fs18 are}{\b0 \fs18 us
ed}{\b0 \fs18 to}{\b0 \fs18 implement}{\b0 \fs18 a}{\b0 \fs18 logic}{\b0
\fs18 circuit.}{\b0 \fs19 PLDs}{\b0 \fs18 are}{\b0 \fs18 faster }
\b0 \fs18 than}{\b0 \fs18 using}{\b0 \fs18 many}{\fs19 SSI}{\b0 \fs18 gate}{
\b0 \fs19 ICs}{\b0 \fs18 on}{\b0 \fs18 a}{\b0 \fs18 printed}{\b0 \fs18 circ
uit}{\b0 \fs18 board.}{\b0 \fs18 Software}{\b0 \fs18 tools}{\b0 \fs18 are}{\
b0 \fs18 available}{\b0 \fs18 for}{\b0 \fs18 programming }
\b0 \fs18 the}{\b0 \fs19 PLDs,}{\b0 \fs18 making}{\b0 \fs18 it}{\b0 \fs18 ea
sy}{\b0 \fs18 to}{\b0 \fs18 add}{\b0 \fs18 changes}{\b0 \fs18 in}{\b0 \fs18
the}{\b0 \fs18 prototype}{\b0 \fs18 designs.}{\b0 \fs18 Other}{\b0 \fs18 a
dvantages}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs19 PLDs}{\b0 \fs18 are }
\b0 \fs18 the}{\b0 \fs18 lower}{\b0 \fs18 cost}{\b0 \fs18 of}{\b0 \fs18 inve
ntory}{\b0 \fs18 because}{\b0 \fs18 they}{\b0 \fs18 are}{\b0 \fs18 somewhat}
{\b0 \fs18 generic}{\b0 \fs18 components}{\b0 \fs18 and}{\b0 \fs18 the}{\b0
\fs18 moderate}{\b0 \fs18 cost}{\b0 \fs18 of }
\b0 \fs18 upgrades}{\b0 \fs18 and}{\b0 \fs18 modifications.}{\b0 \fs18 The}{
\b0 \fs19 PLD}{\b0 \fs18 is}{\b0 \fs19 a}{\b0 \fs18 very}{\b0 \fs18 reliabl
e}{\b0 \fs18 component.}{\b0 \fs18 Proprietary}{\b0 \fs18 logic}{\b0 \fs18 d
esigns}{\b0 \fs18 can}{\b0 \fs18 be }
\b0 \fs18 hidden}{\b0 \fs18 from}{\b0 \fs18 competitors}{\b0 \fs18 by}{\b0 \f
s18 using}{\b0 \fs18 the}{\b0 \fs18 security}{\b0 \fs18 fuse}{\b0 \fs18 pro
vided}{\b0 \fs18 by}{\b0 \fs18 the}{\b0 \fs18 manufacturer. }
fi360 {\b0 \fs19 A}{\b0 \fs18 logic}{\b0 \fs18 diagram}{\b0 \fs18 for}{\b0 \f
s18 a}{\b0 \fs18 simple}{\b0 \fs18 PLA}{\b0 \fs18 device}{\b0 \fs18 is}{\b0
\fs18 shown}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs19 13-15a.}{\b0 \fs18 Not
e}{\b0 \fs18 that}{\b0 \fs18 this}{\b0 \fs18 unit}{\b0 \fs18 has}{\b0 \fs18
only}{\b0 \fs19 two }
\b0 \fs18 inputs}{\b0 \fs18 and}{\b0 \fs18 a}{\b0 \fs18 single}{\b0 \fs18 ou
tput.}{\b0 \fs19 A}{\b0 \fs18 typical}{\b0 \fs18 commercial}{\b0 \fs18 produ
ct}{\b0 \fs18 may}{\b0 \fs18 have}{\b0 \fs19 12}{\b0 \fs18 inputs}{\b0 \fs18
and}{\b0 \fs19 10}{\b0 \fs18 outputs,}{\b0 \fs18 as}{\b0 \fs18 is}{\b0 \f
s18 the }
\b0 \fs18 case}{\b0 \fs18 for}{\b0 \fs18 the}{\b0 \fs19 PAL12LlOA}{\b0 \fs
19 IC.}{\b0 \fs18 In}{\b0 \fs18 Fig.}{\b0 \fs19 13-15a}{\b0 \fs18 note}{
\b0 \fs18 the}{\b0 \fs19 AND-OR}{\b0 \fs18 pattern}{\b0 \fs18 of}{\b0 \f
s18 logic}{\b0 \fs18 gates}{\b0 \fs18 which}{\b0 \fs18 can }
\b0 \fs18 implement}{\b0 \fs18 any}{\b0 \fs18 minterm}{\b0 \fs18 (sum}{\b0 \f
s18 of}{\b0 \fs18 products)}{\b0 \fs18 Boolean}{\b0 \fs18 expression.}{\b0 \
fs18 The}{\b0 \fs18 simplified}{\b0 \fs19 PLA}{\b0 \fs18 in}{\b0 \fs18 Fig.
}{\b0 \fs19 13-15a}{\b0 \fs18 has }
\b0 \fs18 intact}{\b0 \fs18 fuses}{\b0 \fs18 (fusible}{\b0 \fs18 links)}{\b0
\fs18 used}{\b0 \fs18 for}{\b0 \fs18 programming}{\b0 \fs18 the}{\b0 \fs19
AND}{\b0 \fs18 gates.}{\b0 \fs18 The}{\b0 \fs18 OR}{\b0 \fs18 gate}{\b0 \fs
18 is}{\b0 \fs18 not}{\b0 \fs18 programmed}{\b0 \fs18 in }\par
}
his unit. The{\fs19 PLA} in Fig.{\fs19 13-15a} shows the device as it comes fr
om the manufacturer-with
\par}{\phpg\posx925\pvpg\posy12704\absw8062\absh838 \sl-230 \f20 \fs18 \cf0 inta
ct. The{\fs19 PLA} in Fig.{\fs19 13-15a} needs to be programmed by burning op
en selected fuses.
\fi22 {\fs17 PAL@Registered}{\fs17 Trademark}{\fs17 of}{\fs17 Advanced}{\f
s17 Micro}{\fs17 Devices,}{\fs17 Inc. }\par
}
ll fuses \par
}
cf0 OTHER DEVICES{\f30 \fs20 AND} T E C ~ N I ~ ~ E S \par
}
f0 327 \par
}
15 \cf0 A \par
}
cf0 B \par
}
\fs16 \cf0 Fuses used for
\par}{\phpg\posx5573\pvpg\posy1970\absw1649\absh348 \sl-181 \b \f20 \fs16 \cf0 m
mingthe{\fs16 AND} gates \par
}
18 \cf0 Y \par
}
s10 \cf0 (U){\i0 \f20 \fs16 Fuses}{\i0 \f20 \fs16 intact}{\i0 \f20 \fs16 (as
}{\i0 \f20 \fs16 from}{\i0 \f20 \fs16 manufacturer) }\par
}
cf0 Input
i187 {\i \fs15 A }\par
}
\cf0 Burn~d-openfuses \par
}
fs15 \cf0 (b){\i0 \fs16 Selected}{\i0 \fs16 fuses}{\i0 \fs16 burned}{\i0 \fs1
6 open}{\i0 to}{\i0 \fs16 solve}{\i0 \fs16 logic}{\i0 \fs16 problems }\par
}
0 328 \par
}
AP.{\fs17 13 }\par
}
17 \cf0 B \par
}
15 \cf0 A \par
}
15 \cf0 X \par
}
{\phpg\posx4121\pvpg\posy3222\absw112\absh96 \f10 \fs7 \cf0 \f10 \fs7 \cf0 \\# \
par
}
par
}
par
}
{\phpg\posx5141\pvpg\posy3213\absw119\absh103 \f10 \fs7 \cf0 \f10 \fs7 \cf0 \\#
\par
}
par
}
par
}
\par
}
par
}
15 \cf0 Y \par
}
\par}{\phpg\posx4135\pvpg\posy6298\absw119\absh158 \f10 \fs7 \cf0 {\b\i 0\\ }\pa
r
}
\par}{\phpg\posx4471\pvpg\posy6292\absw119\absh161 \sl-84 \f10 \fs7 \cf0 {\b\i \
fs7 0\\ }\par
}

\par}{\phpg\posx4805\pvpg\posy6292\absw119\absh162 \sl-84 \f10 \fs7 \cf0 {\b\i 0
\\ }\par
}
}{\phpg\posx5155\pvpg\posy6334\absw140\absh96 \f10 \fs7 \cf0 /\\ \par
}
s13 \cf0 (a){\i0 \f20 \fs15 All}{\i0 \f20 \fs15 fusesintact }\par
}
\cf0 Burned-openfuses
fi238 (noconnection) \par
}
\cf0 output \par
}
fs19 \cf0 A.B+X.B {\b0\i0\dn006 \f10 \fs10 =}{\fs15 Y }\par
}
\f20 \fs15 \cf0 (b>{\i0 \fs15 Selected}{\i0 \fs15 fuses}{\i0 \fs15 burned}{\i
0 \fs15 open}{\i0 \fs15 to}{\i0 \fs15 solve}{\i0 \fs15 logic}{\i0 \fs15 pro
blems }
\cf0 {\i0 \fs16 Fig.}{\i0 \fs16 13-16}{\i0 \fs16
Simple}{\i0 \fs17 PLA}{\i
0 \fs16 using}{\i0 \fs16 abbreviated}{\i0 \fs16 notation}{\i0 \fs16 system}{
\i0 \fs16 (fuse}{\i0 \fs16 map) }\par
}
0 CHAP.{\b\i0 \fs17 131 }\par
}
cf0 OTHER DEVICES{\b0 AND} TECHNIQUES \par
}
f0 329 \par
}
he{\b PLA} in Fig{\b \fs19 13-1%} has been programmed to implement t
he minterm Boolean expression \par
}
18 \cf0 A{\b0\i0 \fs27 -}{\f30 \fs26 B}{\b0 \f30 \fs28 +A. }\par
}
cf0 B \par
}
{\b\i \f20 \fs19 Y.}{\f20 \fs19 Notice}{\f20 \fs19 that}{\f20 \fs19 the}{\f2
0 \fs19 top}{\f20 \fs19 4-input}{\b \f20 \fs19 AND}{\f20 \fs19 gate}{\f20 \f
s19 (gate}{\f20 \fs18 1)}{\f20 \fs19 has}{\f20 \fs19 two}{\f20 \fs19 fusib
le}{\f20 \fs19 links}{\f20 \fs19 burned}{\f20 \fs19 open, }\par
}
{\phpg\posx897\pvpg\posy1747\absw1988\absh284 \f20 \fs19 \cf0 \f20 \fs19 \cf0 le
aving the{\b\i \f10 \fs17 A} and{\b\i \f30 \fs28 B }\par
}

erms connected. Gate{\b \fs18 1} ANDs the{\b\i \f10 \fs18 A} and{\b\i \
f10 \fs23 8} terms.{\b AND} gate 2 has{\fs19 two }\par
}
{\phpg\posx891\pvpg\posy1979\absw2994\absh284 \f20 \fs19 \cf0 \f20 \fs19 \cf0 bu
rned-open fuses, leaving the{\i \f30 \fs28 A }\par
}
nd{\i \fs19 B} inputs connected. Gate 2{\b ANDs} the \par
}
nd{\b B} terms. AND \par
}
{\phpg\posx897\pvpg\posy2296\absw9111\absh426 \f20 \fs19 \cf0 \f20 \fs19 \cf0 ga
te 3 is{\i \fs19 not}{\i \fs19 needed} to implement this Boolean expressio
n. All fuses are left intact as shown in Fig.
b, which means the output{\fs19 of} AND gate{\b \fs19 3} will always be a logi
cal{\fs19 0.} This logical{\fs19 0} will have no \par
}
{\phpg\posx897\pvpg\posy2679\absw7993\absh318 \f20 \fs19 \cf0 \f20 \fs19 \cf0 ef
fect on the operation{\fs19 of} the OR gate. The OR gate in Fig.{\b \fs19 13-1
%} logically ORs the{\b\i \fs19 A}{\f10 \fs27 - }\par
}
{\phpg\posx895\pvpg\posy2892\absw7793\absh355 \f20 \fs19 \cf0 \f20 \fs19 \cf0 te
rms implementing the Boolean expression. In this simplest example, the{\b\i A}
{\f10 \fs27 -}{\b\i \f30 \fs27 B}{\f10 \fs29 +}{\i \f10 \fs24 2.}{\b\i\dn006
B }\par
}
38 \cf0 x}{\phpg\posx9303\pvpg\posy2608\absw667\absh372 \b\i \f30 \fs38 \cf0 \fi0 {\f20 \
fs19 B }\par
}
d \par
}
{\b\i \f20 \fs19 Y}{\f20 \fs19 mintenn }\par
}
xpression was implemented using a programmable logic array. Recall that
the Boolean expression
92 {\f10 \fs7 * }
g a 2-input XOR gate{\b \fs19 SSI}{\fs19 IC. }
\fi1062 {\b \fs16 Inputs }\par
}
8 \cf0 A \par
}
s27 \cf0 B{\b0 \fs28 +A. }
}{\phpg\posx1163\pvpg\posy3401\absw8584\absh312 \b\i \f30 \fs27 \cf0 \fi0 {\dn00
6 \f20 \fs19 B}{\b0\i0\dn006 \f10 \fs13 =}{\f20 \fs19 Y}{\b0\i0 \f20 \fs19 d
escribes}{\b0\i0 \f20 \fs19 the}{\b0\i0 \f20 \fs19 2-input}{\b0\i0 \f20 \fs19
XOR}{\b0\i0 \f20 \fs19 function}{\b0\i0 \f20 \fs19 which}{\b0\i0 \f20 \fs19
could}{\b0\i0 \f20 \fs19 probably}{\b0\i0 \f20 \fs19 be}{\b0\i0 \f20 \fs19 im
plemented}{\b0\i0 \f20 \fs19 cheaper }\par

}
s51 \cf0 "i" \par
}
\par
}
15 \cf0 C \par
}
15 \cf0 D \par
}
\cf0 U{\i0 \fs23
I }
fi833 {\b \fs15 ABCD }\par
}
cf0 Ouputs
0 \fi202 {\fs15 YI }\par
}
I' \par
}
\cf0 Fig.{\fs16 13-17}{\fs17
PLA}{\fs16 with}{\fs16 four}{\fs16 inputs}{
\fs17 and}{\fs16 three}{\fs16 outputs }\par
}
\par
}
}
AP.{\fs17 13 }\par
}
\cf0 An abbreviated notation system used with PLAs is illustrated in Fi
g. 13-16. Note that all{\fs19 AND }
\fs19 OR} gates have only one input, while in reality each AND gate has four in
puts, and the{\fs19 OR} gate
three inputs (see Fig. 13-15a). The PLA has all fuses intact before programming.
This is shown in
13-15a as a regular logic diagram. Figure 13-16a shows all fuses intact
(each{\f10 \fs15
X} represents an
\par}{\phpg\posx857\pvpg\posy1330\absw9115\absh3203 \sl-244 \f20 \fs18 \cf0 inta
ct fuse) by using the abbreviated notation system.
62 The Boolean expression{\b\i \fs19
A}{\f10 \fs23 -}{\b\i\dn006 \fs19
B}{\f10 \fs14 =}{\b\i \fs19 Y} is implemented in Fig. 13-156.
The same Booleanan

ession is implemented in Fig. 13-166 but only using the abbreviated notatio
n system to describe
programming of the PLA. Notice in Fig. 13-166 that an{\f10 \fs14 X} at an int
ersection means an intact fuse
\par}{\phpg\posx857\pvpg\posy1330\absw9115\absh3203 \sl-231 \f20 \fs18 \cf0 whil
e no{\f10 \fs14
X} means a burned-open fuse (no connection).
74 The abbreviated notation system is used because commercial PLAs are
much larger than the
\par}{\phpg\posx857\pvpg\posy1330\absw9115\absh3203 \sl-232 \f20 \fs18 \cf0 simp
lified device drawn in Figs. 13-15 and 13-16. This notation is sometimes calle
d a{\i \f10 \fs16 fuse}{\b\i \fs18 map. }
70 A more complex PAL-type programmable logic device is illustrated in
Fig. 13-17. This PLA
\par}{\phpg\posx857\pvpg\posy1330\absw9115\absh3203 \sl-242 \f20 \fs18 \cf0 feat
ures four inputs and three outputs. It is common for decoders to have many outp
uts (such as the
decoder in Fig. 7-7). The programmable logic device in Fig. 13-17 is not a c
ommercial product.
73 Three combinational logic problems have been solved using the PLA in
Fig. 13-17. First the \par
}
{\phpg\posx871\pvpg\posy4899\absw1772\absh744 \f20 \fs18 \cf0 \f20 \fs18 \cf0 Bo
olean expression
fi802 {\fs15 Inputs }\par
}
\cf0 A. {\dn006 \f20 \fs19 B}{\i0 \f10 \fs27
-}{\dn006 \f20 \fs18 D }\par
}
s18 \cf0 + A{\b0 \fs19
B}{\b0\i0 \f10 \fs23 -}{\fs19 C}{\b0\i0 \f10 \fs27
-}{\b0\dn006 \fs19 D }\par
}
}
\b\i \f30 \fs25 2.}{\fs23 - }\par
}
s19 \cf0 B{\b0 \fs19
C}{\b0\i0 \f10 \fs27 -}{\b0 \fs18 D}{\b0\i0\dn006 \f10
\fs13 = }\par
}
s18 \cf0 Y,{\b0\i0 is}{\b0\i0 implemented}{\b0\i0 using}{\b0\i0 the}{\b0
\i0 upper }\par
}
15 \cf0 outputs
{\fs16 Fig.}{\b \f30 \fs17 13-18}{\fs17 FPLA}{\fs16 (field-programmable}{\f
s16 logic}{\fs16 array)}{\fs16 with}{\fs16 programmable}{\fs17 AND}{\fs16
and}{\fs17 OR}{\fs16 arrays }\par
}
0 CHAP.{\fs17 131 }\par
}
}
\fs18 1 }\par
}
roup of AND-OR gates. Remember that an{\f10 \fs14
X} on the fuse map
means an intact fuse while no{\f10 \fs20 x }
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-246 \f20 \fs18 \cf0 mean
s a burned-open fuse. The second Boolean expression{\b\i \f10 \fs17 A}{\b\i
\fs19
B}{\f10 \fs27 -}{\b\i \fs18 C}{\f10 \fs27 -}{\i \fs19 D}{\i \f30 \
fs27 +A.}{\f10 \fs27 -}{\f10 \fs7
* }
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-237 \f20 \fs18 \cf0 ment
ed using the middle group of AND-OR gates. Note that the bottom AND g
ate in the middle
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-235 \f20 \fs18 \cf0 grou
p is not needed. Therefore it has all eight fuses intact, which means it genera
tes a logical{\fs19 0} which
682 {\f10 \fs18 -}{\f10 \fs18 - }
no effect on the output of the OR gate. The third Boolean expression{\b\i \f10
\fs17 A}{\b\i \fs19
B}{\f10 \fs18
C}{\i \fs19 D}{\b\i \f10 \fs18 +}{
\b\i \f10 \fs18 A}{\b\i \fs19 .}{\b\i \fs19 B}{\f10 \fs18
C}{\f10 \fs27 }{\b\i \fs24 E }
6 {\i \f30 \fs28 +A.}{\f10 \fs23
-}{\i
Y3} is implemented using th
e bottom group of AND-OR gates.
68 {\b\i \f10 \fs17 An} alternative PLA architecture is shown{\fs19 in} Fi
g. 13-18. This PLA provides both programmable
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-230 \f20 \fs18 \cf0 AND
and{\fs19 OR} arrays. The programmable logic devices studied before only c
ontained programmable
gates. This type of device is sometimes called a field-programmable logic{\b\
i \fs18 array}{\i \fs19 (FPLA).} Notice
Fig. 13-18 that each fusible link in both the AND and OR arrays is marked
with an{\f10 \fs14
X,} meaning
all the links are intact (not burned).
68 One catalog{\fs18 of} ICs groups programmable logic devices first by
the process technology used to
facture the units. Second, they are grouped as either one-time programmable
or erasable. The
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-237 \f20 \fs18 \cf0 eras
able units can be either of the{\fs19 UV} (ultraviolet) light type or electri
cally erasable. Third, they are
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-242 \f20 \fs18 \cf0 grou
ped by whether the PLD has combinational logic or registered/latched o
utputs. Traditionally
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-232 \f20 \fs18 \cf0 PLDs
have been uscd to solve complex combinational logic problems. The registe
red PLDs contain
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-242 \f20 \fs18 \cf0 both
gates and flip-flops, providing the means of latching output data or of desig
ning sequential logic
uits such as counters.
59 The PAL10H8 is an example of a small commercial programmable logic device.
The pin diagram
Fig. 13-19a shows a block diagram of the PALlOH8 programmable logic arra
y. Notice that the
k diagram shows 10 inputs and{\fs19 8} outputs along with the programm
able AND array. A more
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-235 \f20 \fs18 \cf0 deta
iled logic diagram of the PALlOH8 is reproduced in Fig. 13-19b.This detailed log
ic diagram looks
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-232 \f20 \fs18 \cf0 much
like the simple programmable logic devices studied earlier. The PALlOH8 IC is a
Schottky TTL
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-237 \f20 \fs18 \cf0 devi
ce with titanium tungsten fusible links. The PALlOH8 has a propagation delay
of less than{\fs19 35} ns.
PALlOH8 requires a standard{\f10 \fs17 5-V} dc power supply. The PALlOH8 is ava
ilable in the 20-pin DIP
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-239 \f20 \fs18 \cf0 (sho
wn in Fig. 13-19a) or a 20-lead plastic chip carrier package for surface mountin
g.
72 Part number decoding and ordering information supplied by National Semiconduc
tor for the{\fs19 PAL }
es of programmable logic arrays is shown in Fig. 13-20. Note that the
letters PAL indicate the
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-239 \f20 \fs18 \cf0 fami
ly of devices.{\fs19 In} this example, the next number (10) indicates the num
ber of inputs to the AND
\par}{\phpg\posx879\pvpg\posy1338\absw9140\absh6642 \sl-236 \f20 \fs18 \cf0 arra
y. The middle letter{\i (}{\i H} in this example) indicates the type of out
put. The{\b\i \fs19 H} means the outputs
active-HIGH. The next number{\fs19 (8} in this example) indicates the number{\
fs19 of} outputs. The trailing \par
}
19 \cf0 B{\b0\i0 \f10 \fs18
C}{\fs24 E}{\b0\i0\dn006 \f10 \fs13 = }\par
}
\cf0 Y2{\i0 \fs18 is}{\i0 \fs18 imple- }\par
}
par
}
}
18 \cf0 B{\b0\i0 \f10 \fs17

C}{\b0 D}{\b0\i0\dn006 \f10 \fs11
= }\par
}
}
}
}
}
0 I \par
}
\fs7 \cf0 \par}{\phpg\posx4347\pvpg\posy12822\absw1998\absh420 \sl-172 \par\b \f20 \fs7 \c
f0 {\i \f10 \fs12 (a)}{\fs15 Pin}{\fs15 and}{\fs15 block}{\fs15 diagram }\pa
r
}
\cf0 Fig.{\fs16 13-19}{\fs17
PAL1OH8}{\fs17 programmable}{\fs17 logic}{\f
s17 device}{\i \fs16 (Courtesy}{\i \f30 \fs16 of}{\i \fs16 National}{\i \fs1
6 Semiconductor}{\i \fs16 Corporation) }\par
}
\par
}
}
AP.{\fs16 13 }\par
}
ip pin numbers
75 Product line first fuse numbers
\fi481 {\f10 \fs14 0}{\f10 \fs14
2}{\f10 \fs14
4}{\f10 \fs14
6}{\f10 \fs14
8 }
\fi1908 {\f10 \fs14 7 }\par
}
put line
numbers \par
}
\par
}
18 \par
}

cf0 Dip pin
\par}{\phpg\posx8327\pvpg\posy1428\absw617\absh352 \sl-202 \f20 \fs15 \cf0 numbe
rs \par
}
{\phpg\posx8789\pvpg\posy1775\absw311\absh497 \f10 \fs42 \cf0 \f10 \fs42 \cf0 J
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
\par
}
19 \par
}
15 \cf0 vc> \par
}
\par
}
\par
}
\par
}
\par
}
{\phpg\posx5143\pvpg\posy8066\absw70\absh89 \f10 \fs6 \cf0 \f10 \fs6 \cf0 -4) \p
ar
}
\par
}
\par
}
2 \par
}
0 \par
}
\par
}
\par
}
0 \fs14 1 }\par
}
\par
}
0 \fs14 3 }\par
}
\par
}
0 \fs14 5 }\par
}
\par
}
\par
}
\par
}
\cf0 I
0 \fs14 9 }\par
}
0 \par
}
\cf0 1
14 11 }\par
}
2 \par
}
4 \par
}
3 \par
}
\sl-230 \f10 \fs14 \cf0 {\f2

\fs14 \cf0 \f10 \fs14 \cf0 6
\fs14 \cf0 \f10 \fs14 \cf0 8
\fs14 \cf0 \f10 \fs14 \cf0 7
\fs26 \cf0 \fi30 \f10 \fs26
\sl-282 \f10 \fs26 \cf0 {\f2
\fs14 \cf0 \f10 \fs14 \cf0 1
\fs27 \cf0 \fi61 \f10 \fs27
\sl-282 \f10 \fs27 \cf0 {\fs
\fs14 \cf0 \f10 \fs14 \cf0 1
\fs14 \cf0 \f10 \fs14 \cf0 1
\fs14 \cf0 \f10 \fs14 \cf0 1

\cf0 I
{\fs13 15 }\par
}
6 \par
}
\par
}
7
19 \par
}
20 \fs15 \cf0 (6){\i0 Logic}{\i0 diagram }
cf0 {\b\i0 \fs16 Fig.}{\b\i0 \f10 13-19}{\i0 \fs16
Continued.}{\fs16 (Court
esy}{\i0 \fs15 of}{\fs16 National}{\fs16 Semiconductor}{\fs16 Corporation
) }\par
}
.{\fs17 131 }\par
}
}
\par
}
Programmable array logic family
\par}{\phpg\posx5103\pvpg\posy1359\absw2282\absh3195 \sl-201 \f20 \fs15 \cf0 Num
ber of array inputs
\par}{\phpg\posx5103\pvpg\posy1359\absw2282\absh3195 \sl-198 \f20 \fs15 \cf0 Out
put type:
162 H{\dn006 \f10 \fs10 =} Active High
166 L{\dn006 \f10 \fs10 =} Active Low
160 C{\dn006 \f10 \fs9 =} Complementary
166 {\fs15 R}{\dn006 \f10 \fs9 =} Registered
162 {\fs15 X}{\dn006 \f10 \fs10 =} Exclusive-ORregistered
162 P{\dn006 \f10 \fs10 =} Programmable polarity
\par}{\phpg\posx5103\pvpg\posy1359\absw2282\absh3195 \sl-195 \f20 \fs15 \cf0 Num
ber of outputs
\par}{\phpg\posx5103\pvpg\posy1359\absw2282\absh3195 \sl-194 \f20 \fs15 \cf0 Spe
ed/power version:
79 No Symbol{\dn006 \f10 \fs9 =}{\fs15 35} ns
76 A{\dn006 \f10 \fs10
=} 25 ns
72 A2{\dn006 \f10 \fs9 =}{\fs15 35} ns, half power
\par}{\phpg\posx5103\pvpg\posy1359\absw2282\absh3195 \sl-197 \f20 \fs15 \cf0 Pac

kage Type:
80 {\fs15 N}{\dn006 \f10 \fs10 =} 20-pin plastic DIP
72 {\fs15 J}{\dn006 \f10 \fs9 =} 20-pin ceramic{\fs15 DIP }
80 {\fs15 V}{\dn006 \f10 \fs10 =} 20-lead plastic chip carrier \par
}
emperature range:
1 C{\dn006 \f10 \fs10 =} commercial{\fs14 (0}{\b \f10 \fs11 1.0 }\par
}
\par
}
{\phpg\posx5373\pvpg\posy5358\absw120\absh113 \f10 \fs9 \cf0 \f10 \fs9 \cf0 = \p
ar
}
\f20 \fs15 75C) }\par
}
5 \cf0 -- \par}{\phpg\posx3261\pvpg\posy5379\absw1653\absh338 \sl-173 \f10 \fs15 \cf0 {\f2
0 \fs15 PAL}{\f20 \fs15
10}{\f20 \fs15
H}{\f20 \fs15
8}{\f20 \fs15 A}
{\f20 \fs15 N}{\f20 \fs15 C }\par
}
ilitary{\f10 \fs13 (-}{\i \fs15 55}{\f10 \fs12 ito}{\fs14 -t}125C) \par
}
\fs16 \cf0 Fig.{\fs16 13-20}{\b0 \fs15 Dccoding}{\b0 \fs16 a}{\b0 \fs15
PAL}{\b0 \fs15 part}{\b0 \fs15 number}{\b0\i \fs16 (Courtesy}{\b0\i \fs17 o
}{\b0\i \fs17 f}{\b0\i \fs16 Nutiond}{\b0\i \fs16 Semicwzductor}{\b0\i \fs16
Corporation) }
f0 {\b0 \fs18 letters}{\b0 \fs18 indicate}{\b0 \fs18 the}{\b0 \fs18 speed/
power}{\b0 \fs18
version,}{\b0 \fs18 package}{\b0 \fs18 type,}{\b0 \fs18
and}{\b0 \fs18 temperature}{\b0 \fs18 range.}{\b0 \fs19 Note}{\b0 \fs18
that}{\b0 \fs18 both }
\b0 \fs18 commercial}{\b0 \fs18 and}{\b0 \fs18 military}{\b0 \fs18 versions}
{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 PALlOH8}{\b0 \fs18 are}{\b0 \fs18
available. }
}
cf0 13.39{\b0 \fs18 The}{\b0 \fs18 letters}{\b0 \fs18 PLA}{\b0 \fs18 stand
}{\b0 \fs18 for }
}
hen dealing with programmable logic Icls. \par
}
\cf0 The letters PLA stand for programmable logic array. PLA and PLD
(programmable logic device)

become generic terms for these ICs. \par
}
cf0 13.40{\b0 \fs18 The}{\b0 \fs18 letters}{\fs18 PAL'"'}{\b0 \fs18 stand}{
\b0 \fs18 for }
}
par
}
\cf0 The letters PAL" stand for programmable array logic.
{\b \fs18 13.41}{\fs18
Programmable}{\fs18 logic}{\fs18 devices}{\fs18
are}{\fs18 commonly}{\fs18 used}{\fs18 to}{\fs18 implement }
85 {\fs18 logic}{\fs18 circuits. }
49 PLDs are commonly used to implement combinational logic circuits. \pa
r
}
\cf0 13.42{\b0 \fs18 The}{\b0 \fs18 letters}{\b0 \fs18 FPL,A}{\b0 \fs18 sta
nd}{\b0 \fs18 for }
}
combinational, fuzzy) \par
}
when dealing with programmable logic{\fs18 ICs. }\par
}
\cf0 The{\fs15 letters}{\fs15 FPLA}{\fs15 stand}{\fs15 for}{\fs15 fie
ld-programmable}{\fs15 logic}{\fs15 array. }
{\b \fs18 13.43}{\fs18
PLAs}{\fs18 and}{\fs18 FPLAs}{\fs18 are}{\fs18 co
mmonly}{\fs18 programmed}{\fs18 by}{\fs18 the }
\fi583 {\b \fs16 Solution: }\par
}
(manufacturer, user). \par
}
PLAs and FPLAs are commonly programmed in the field{\b \fs16 by} the
user.{\f10 \fs15 , }\par
}
AL@is a registered trademark{\fs16 of} Advanced Micro Devices, Inc. \pa
r
}

\par
}
}
AP. 13 \par
}
cf0 13.44{\b0 \fs18 The}{\b0 \fs18 PLA}{\b0 \fs18 is}{\b0 \fs18 a}{\b0 \fs1
8 close}{\b0 \fs18 relative}{\b0 of}{\b0 \fs18 the }
}
PROM, RAM){\fs19 IC. }\par
}
he PLA is a close relative of the PROM (programmable read-only memory).
\par
}
cf0 13.45{\b0 \fs18 Programming}{\b0 \fs18 of}{\b0 \fs18 most}{\b0 \fs18 PL
Ds}{\b0 \fs18 consists}{\b0 \fs18 of}{\b0 \fs18 burning}{\b0 \fs18 open}{\b0
\fs18 selected}{\b0 \fs18 titanium}{\b0 \fs18 tungsten }
i591 {\b0 \fs18 the}{\b0 \fs18 device. }
}
thin \par
}
\cf0 Programming one-time PLDs consists of burning open selected
fuses within the device. Some
\par}{\phpg\posx1455\pvpg\posy3657\absw8263\absh385 \sl-215 \f20 \fs17 \cf0 prog
rammable logic devices are erasable. \par
}
cf0 13.46{\b0 \fs18 What}{\b0 \fs18 is}{\b0 \fs18 the}{\b0 \fs18 fundament
al}{\b0 \fs18 difference}{\b0 \fs18 between}{\b0 \fs18 a}{\fs19 PAL}{\b0 \
fs18 and}{\b0 \fs18 an}{\b0 \fs18 FPLA? }
i950 {\i \f10 \fs15 An}{\b0 \fs17 FPLA}{\b0 \fs17 (see}{\b0 \fs17 Fig.}{\b0
\fs17 13-18)has}{\b0 \fs17 both}{\b0 \fs17 programmable}{\b0 \fs17 AND}{
\b0 \fs17 and}{\b0 \fs17 OR}{\b0 \fs17 gates,}{\b0 \fs17 while}{\b0 \fs17
a}{\b0 \fs17 PAL}{\b0 \fs17 (see}{\b0 \fs17 Fig.}{\b0 \fs17 13-19) }
i596 {\b0 \fs17 contains}{\b0 \fs17 only}{\b0 \fs17 programmable}{\b0 \fs17
AND}{\b0 \fs17 gates. }\par
}
cf0 13.47{\b0 \fs18 PLAs}{\b0 \fs18 are}{\b0 \fs18 organized}{\b0 \fs18 t
o}{\b0 \fs18 implement }
i585 {\b0 \fs18 AND-OR}{\b0 \fs18 pattern}{\b0 \fs18 of}{\b0 \fs18 logic}{\b0
\fs18 gates. }
}
maxterm, minterm) Boolean expressions using an \par
}
\cf0 PLAs are organized to implement minterm (sum-of-products) Boolean expressi
ons using an AND-OR
ern of logic gates. \par
}
cf0 13.48{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 13-19.}
{\b0 \fs18 The}{\b0 \fs18 PALlOH8}{\b0 \fs19 IC}{\b0 \fs18 is}{\b0 \fs18 a}
{\b0 \fs18 programmable}{\b0 \fs18 logic}{\b0 \fs18 device}{\b0 \fs18 with
}\par
}
puts and
}
number) outputs with a programmable \par
}
umber) \par
}
AND, OR) array. \par
}
he PALlOH8 is a PLD{\fs16 with} 10 inputs and{\b \fs16 8} outputs with
a programmable AND array. \par
}
\cf0 13.49{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 \fs18 13-20.E
xplain}{\b0 \fs18 the}{\b0 \fs18 meaning}{\b0 \fs18 of}{\b0 \fs18 a}{\b0 \fs
18 programmable}{\b0 \fs18 logic}{\b0 \fs18 device}{\b0 \fs18 with}{\b0 \fs1
8 a}{\b0 \fs18 part}{\b0 \fs18 number}{\b0 \fs18 of }
fi589 {\b0 \fs18 PAL24LlOA}{\b0 \fs18 from}{\b0 \fs18 National}{\b0 \fs18 Se
miconductor. }
fi949 {\b0 \fs17 Decoding}{\b0 \fs17 the}{\b0 \fs17 part}{\b0 \fs17 number}
{\b0 \fs17 PAL24LlOA}{\b0 \fs16 is}{\b0 \fs17 as}{\b0 \fs17 follows: }
fi596 {\b0 \fs17 PAL}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 programmable}{\b0 \fs
17 array}{\b0 \fs17 logic}{\b0 \fs17 family }
fi590 {\fs17 24}{\b0 \f10 \fs13 =}{\b0 \fs17 24}{\b0 \fs17 inputs }
fi589 {\b0 \fs17 L}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 active-LOW}{\b0 \fs17
outputs }
fi601 {\b0 \fs17 10}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 10}{\b0 \fs17 outputs
}
fi583 {\b0 \fs17 A}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 propagation}{\b0 \fs17
delay}{\b0 \fs17 of}{\b0 \fs17 25}{\b0 \fs17 ns }\par
}
\cf0 13.50{\b0 \fs18 Using}{\b0 \fs18 a}{\b0 \fs18 simple}{\b0 \fs18 fuse}{
\b0 \fs18 map}{\b0 \fs18 like}{\b0 \fs18 the}{\b0 \fs18 one}{\b0 \fs18 pict
ured}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-16a,}{\b0 \fs18 program}{\
b0 \fs18 this}{\b0 \fs18 PLA}{\b0 \fs18 to}{\b0 \fs18 implement }
fi591 {\b0 \fs18 the}{\b0 \fs18 minterm}{\b0 \fs18 Boolean}{\b0 \fs18 expres
sion}{\i \f10 \fs17
A}{\b0 \f10 \fs27 -}{\i \fs19 B}{\i \f10 \fs17 +}{\i \
f10 \fs17 A}{\b0 \f10 \fs22 .}{\i \fs19 B}{\b0\dn006 \f10 \fs13 =}{\i\dn006
\fs18 Y. }
fi951 {\b0 \fs17 See}{\b0 \fs17 Fig.}{\b0 \fs17 13-21. }\par
}
}
0 CHAP.{\fs17 131 }\par
}
HER{\b \fs17 DEVICES}{\b \fs17 AND}{\b \fs17 TECHNIQUES }\par
}
\par
}
cf0 Inputs
0 \fi131 {\i \fs15 A}{\i \fs15 - }\par
}
cf0 B \par
}
par
}
cf0 A
i0 \f10 \fs19 - }\par
}
4 \par
}
\cf0 Fig.{\fs17 13-21}{\fs17
PLA}{\fs17 fuse}{\fs16 map}{\b0 \fs17 soluti
on }\par
}
\fs19 \cf0 13-8 MAGNITUDE COMPARATOR
fi382 {\fs19 A}{\b0 \fs19 magnitude}{\b0 \fs19 comparator}{\b0 \fs19 is}{\b

0 \fs19 a}{\b0 \fs19 device}{\b0 \fs19 that}{\b0 \fs19 compares}{\b0 two}{\
b0 \fs19 binary}{\b0 \fs19 numbers}{\b0 \fs19 and}{\b0 \fs19 outputs}{\b0
\fs19 a}{\b0 \fs19 response }
fi28 {\b0 \fs19 such}{\b0 \fs19 as}{\i \fs19 A}{\b0 \fs19 is}{\b0 \fs19 eq
ual}{\b0 \fs19 to}{\i \fs19 B}{\i \fs19 (}{\i \fs19 A}{\b0\dn006 \f10 \fs
13 =}{\i \fs19 B),}{\i \fs18 A}{\b0 \fs19 is}{\b0 \fs19 greater}{\b0 \fs19
than}{\i \fs19 B}{\i \fs19 (}{\i \fs19 A}{\b0 \f10 \fs22 >}{\i \fs19 B
),}{\b0 \fs19 or}{\i \fs18 A}{\b0 \fs19 is}{\b0 \fs19 less}{\b0 \fs19 tha
n}{\i \fs19 B}{\i \fs19 (}{\i \fs19 A}{\b0 \f10 \fs22 <}{\i \fs19 B).}{\b0
\fs19 One }
fi28 {\b0 \fs19 commercial}{\b0 \fs19 unit}{\b0 \fs19 is}{\b0 \fs19 the}{\
i \fs19 74HC8.5}{\b0 \fs19 4-bit}{\b0 \fs19 magnitude}{\b0 \fs19 cornpara
tor.}{\fs19 A}{\b0 \fs19 DIP}{\b0 \fs19 pin}{\b0 \fs19 diagram}{\b0 \fs1
9 for}{\b0 \fs19 the}{\b0 \fs19 74HC85 }
fi27 {\b0 \fs19 magnitude}{\b0 \fs19 comparator}{\b0 \fs19 is}{\b0 \fs19 draw
n}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 13-22a.}{\b0 \fs19 The}{\b0 \fs19
74HC85}{\b0 \fs19 IC}{\b0 \fs19 has}{\b0 \fs19 eight}{\b0 \fs19 data-compa
ring}{\b0 \fs19 inputs.}{\b0 \fs19 Two }
fi27 {\b0 \fs19 4-bit}{\b0 \fs19 binary}{\b0 \fs19 numbers}{\b0 \fs19 (A3A2
AlAo}{\b0 \fs19 and}{\b0 \fs19 B3B2BIBo)}{\b0 \fs19 are}{\b0 \fs19 entered}
{\b0 \fs19 into}{\b0 \fs19 the}{\b0 \fs19 data-comparing}{\b0 \fs19 inputs.
}{\b0 \fs19 The }
fi27 {\b0 \fs19 74HC85}{\b0 \fs19 IC}{\b0 \fs19 compares}{\b0 \fs19 the}{\b0
\fs18 two}{\b0 \fs19 4-bit}{\b0 \fs19 numbers}{\b0 \fs19 and}{\b0 \fs19
generates}{\b0 \fs19 one}{\b0 \fs19 of}{\b0 \fs19 three}{\b0 \fs19 acti
ve-HIGH}{\b0 \fs19 outputs.}{\b0 \fs19 The }
fi27 {\b0 \fs19 three}{\b0 \fs19 outputs}{\b0 \fs19 are}{\b0 \fs19 either}{\i
\fs19 A}{\b0 \f10 \fs21 >}{\fs19 Bout}{\b0 \fs19 (pin}{\b0 \fs19 5}{\b0 \fs
19 is}{\b0 \fs19 HIGH)}{\b0 \fs19 or}{\i \fs18 A}{\fs19 =Bout}{\b0 \fs19 (p
in}{\b0 \fs19 6}{\b0 \fs19 is}{\b0 \fs19 HIGH)}{\b0 \fs19 or}{\i \fs18 A}{\
fs19 <Bout}{\b0 \fs19 (pin}{\b0 \fs19 7}{\b0 \fs19 is }
fi28 {\b0 \fs19 HIGH).}{\b0 \fs19 Under}{\b0 \fs19 normal}{\b0 \fs19 conditio
ns,}{\b0 \fs19 only}{\b0 \fs19 one}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19
three}{\b0 \fs19 outputs}{\b0 \fs19 is}{\b0 \fs19 HIGH}{\b0 \fs19 for}{\b0 \
fs19 any}{\b0 \fs19 one}{\b0 \fs19 comparison.}{\fs19 A }
fi28 {\b0 \fs19 detailed}{\b0 \fs19 truth}{\b0 \fs19 table}{\b0 \fs19 for}{\b
0 \fs19 the}{\b0 \fs19 74HC85}{\b0 \fs19 4-bit}{\b0 \fs19 magnitude}{\b0 \fs
19 comparator}{\b0 \fs19 is}{\b0 \fs19 reproduced}{\b0 \fs19 in}{\b0 \fs19
Fig.}{\b0 \fs19 13-22b. }
fi379 {\b0 \fs19 The}{\b0 \fs19 74HC85}{\b0 \fs19 is}{\b0 \fs19 a}{\b0 \fs19
high-speed}{\b0 \fs19 CMOS}{\b0 \fs19 magnitude}{\b0 \fs19 comparator}{\b0 \
fs19 having}{\b0 \fs19 a}{\b0 \fs19 propagation}{\b0 \fs19 delay}{\b0 of}{
\b0 \fs19 about }
fi27 {\b0 \fs19 27}{\b0 \fs19 ns.}{\b0 \fs19 This}{\b0 \fs19 74HC85}{\b0 \f
s19 IC}{\b0 \fs19 can}{\b0 \fs19 operate}{\b0 \fs19 on}{\b0 \fs19 a}{\b
0 \fs19 wide}{\b0 \fs19 range}{\b0 \fs19 of}{\b0 \fs19 voltages,}{\b0 \fs
19 from}{\b0 \fs19 2}{\b0 \fs19 to}{\b0 \fs19 6}{\fs18 V.}{\b0 \fs19 T
his}{\b0 \fs19 CMOS}{\b0 \fs19 unit }
fi21 {\b0 \fs19 consumes}{\b0 \fs19 little}{\b0 \fs19 power}{\b0 \fs19 but}{\
b0 \fs19 can}{\b0 \fs19 drive}{\b0 \fs19 up}{\b0 \fs18 to}{\b0 \fs19 10}{\
b0 \fs19 LS-TTL}{\b0 \fs19 loads. }
fi380 {\fs18 A}{\b0 \fs19 single}{\b0 \fs19 74HC85}{\b0 \fs19 IC}{\b0 \fs19
compares}{\b0 \fs19 two}{\b0 \fs19 4-bit}{\b0 \fs19 numbers,}{\b0 \fs19 but}
{\b0 \fs19 it}{\b0 \fs19 can}{\b0 \fs19 easily}{\b0 \fs19 be}{\b0 \fs19 ex
panded}{\b0 \fs19 to}{\b0 \fs19 handle}{\b0 8-,}{\b0 \fs19 12-, }
fi33 {\b0 \fs19 16-bit,}{\b0 \fs19 or}{\b0 \fs19 more}{\b0 \fs19 numbers.}{\b
0 \fs19 The}{\b0 \fs19 cascade}{\b0 \fs19 inputs}{\b0 \fs19 are}{\b0 \fs19
commonly}{\b0 \fs19 used}{\b0 \fs19 when}{\b0 \fs19 expanding}{\b0 \fs19 the
}{\b0 \fs19 word}{\b0 \fs19 size}{\b0 \fs19 of}{\b0 \fs19 the }
fi27 {\b0 \fs19 magnitude}{\b0 \fs19 comparator.}{\b0 \fs19 Typical}{\b0 \fs19
cascading}{\b0 of}{\b0 \fs19 74HC85}{\b0 \fs19 ICs}{\b0 \fs19 is}{\b0 \fs1
9 shown}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 13-23.Note}{\b0 \fs19 that
}{\b0 \fs19 the}{\b0 \fs19 cascade }
fi29 {\b0 \fs19 inputs}{\b0 \fs19 of}{\b0 \fs19
IC,}{\b0 \fs19
are}{\b0
\fs19 permanently}{\b0 \fs19
connected}{\b0 \fs19
as}{\b0 \fs19 follow
s:}{\i \fs19 (}{\i \fs19 A}{\b0 \f10 \fs21 >}{\fs19 Bin) }{\b0\dn006 \f10 \
fs13 =}{\b0 \fs19 LOW,}{\i \fs18 (}{\i \fs18 A}{\fs19 <Bin) }{\b0\dn006 \f
10 \fs13 =}{\b0 \fs19 LOW,}{\b0 \fs19 and }
fi22 {\i \fs18 (}{\i \fs18 A}{\b0 \f10 \fs14 =}{\fs19 Bin)}{\b0 \f10 \fs14 =}{
\b0 \fs19 HIGH.}{\b0 \fs19 The}{\b0 \fs19 cascade}{\b0 \fs19 inputs}{\b0
\fs19 of}{\b0 \fs19 IC2}{\b0 \fs19 are}{\b0 \fs19 fed}{\b0 \fs19 direc
tly}{\b0 \fs19 from}{\b0 \fs19 the}{\i \fs18 A}{\b0 \f10 \fs21 >}{\b0 \fs
19 Bout,}{\i \fs18 A}{\b0\dn006 \f10 \fs13 =}{\b0 \fs19 Bout,}{\b0 \fs19 and }
\i \fs19 A}{\fs19 <Bout}{\b0 \fs19 outputs}{\b0 \fs19 of}{\b0 \fs19 the}{\b0
\fs19 previous}{\b0 \fs19 74HC85}{\b0 \fs19 (ICl).}{\b0 \fs19 The}{\b0 \fs1
9 circuit}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19 13-23}{\b0 \fs19 compar
es}{\b0 \fs19 the}{\b0 \fs19 magnitude}{\b0 \fs19 of }
fi28 {\b0 two}{\b0 \fs19 8-bit}{\b0 \fs19 binary}{\b0 \fs19 numbers}{\b0 \
fs19
A7A6A5A4A3A2AlAO}{\b0 \fs19
and}{\b0 \fs19
B7B6B5B,B3B,B,Bo.}{\b0
\fs19
In}{\b0 \fs19 response}{\b0 \fs19 to}{\b0 \fs19 the }
fi21 {\b0 \fs19 comparison,}{\b0 \fs19 IC2}{\b0 \fs19 drives}{\b0 \fs19 one}{
\b0 \fs19 of}{\b0 \fs19 three}{\b0 \fs19 outputs}{\b0 \fs19 HIGH.}{\fs18 As
}{\b0 \fs19 an}{\b0 \fs19 example}{\b0 \fs19 in}{\b0 \fs19 Fig.}{\b0 \fs19
13-23,if}{\b0 \fs19 A,}{\b0 \fs19 to}{\i \fs18 A}{\i \fs18 ,}{\b0 \fs19
equals }
fi42 {\b0 11111111}{\b0 \fs19 and}{\i \fs19 B,}{\b0 \fs19 to}{\b0\i \fs19
Bo}{\b0 \fs19 equals}{\b0 \fs19 10101010,}{\b0 \fs19 then}{\b0 \fs19 the}{\i
\fs19 A}{\fs19 >Bout}{\b0 \fs19 output}{\b0 \fs19 from}{\b0 \fs19 IC2}{\b
0 \fs19 is}{\b0 \fs19 activated}{\b0 \fs19 and}{\b0 \fs19 driven }
fi29 {\b0 \fs19 HIGH.}{\b0 \fs19 In}{\b0 \fs19 this}{\b0 \fs19 example,}{\b0
\fs19 all}{\b0 \fs19 other}{\b0 \fs19 outputs}{\i \fs18 (}{\i \fs18 A}{\b0\
dn006 \f10 \fs13 =}{\fs19 Bout}{\b0 \fs19 and}{\i \fs18 A}{\b0 \f10 \fs21 <}
{\b0 \fs19 Bout)}{\b0 \fs19 remain}{\b0 \fs19 deactivated}{\b0 \fs19 at}{\b0 \
fs19 a}{\fs19 LOW}{\b0 \fs19 logic }
fi29 {\b0 \fs19 level. }
fi372 {\fs18 A}{\b0 \fs19 simple}{\b0 \fs19 electronic}{\b0 \fs19 game}{\b0 \
fs19 can}{\b0 \fs19 be}{\b0 \fs19 designed}{\b0 \fs19 using}{\b0 \fs19 the}
{\b0 \fs19 74HC85}{\b0 \fs19 magnitude}{\b0 \fs19 comparator.}{\b0 \fs19 The
}{\b0 \fs19 game}{\b0 \fs19 is }
\b0 \fs19 a}{\b0 \fs19 version}{\b0 \fs19 of}{\b0 \fs19 "guess}{\b0 \fs19
the}{\b0 \fs19 number."}{\b0 \fs19 In}{\b0 \fs19 the}{\b0 \fs19 classi
c}{\b0 \fs19 computer}{\b0 \fs19 version,}{\b0 \fs19 a}{\b0 \fs19 random}
{\b0 \fs19 number}{\b0 \fs19 is}{\b0 \fs19 generated }
\b0 \fs19 within}{\b0 \fs19 a}{\b0 \fs19 range,}{\b0 \fs19 and}{\b0 \fs19 th
e}{\b0 \fs19 player}{\b0 \fs19 tries}{\b0 \fs19 to}{\b0 \fs19 guess}{\b0 \fs
19 the}{\b0 \fs19 number.}{\b0 \fs19 The}{\b0 \fs19 computer}{\b0 \fs19 res
ponds}{\b0 \fs19 with}{\b0 \fs19 such}{\b0 \fs19 responses }\par
}
\par
}
}
}
cf0 B3 \par
}
\cf0 A < B A = B A > B A > B A = B A < B{\b\i0 \fs15
GND }\par
}
cf0 data{\i \f10 \fs13
L-v-J }\par
}
cf0 input \par
}
\cf0 Cascade inputs \par
}
12 \cf0 L-v-J \par
}
cf0 outputs \par
}
cf0 Top view \par
}
s13 \cf0 (a){\b0\i0 \f20 \fs15 Pin}{\i0 \f20 \fs15 diagram }\par
}
cf0 Comparing
i172 inputs \par
}
fs9 \cf0 A37{\fs15 B3 }
fs11 A3}{\fs15 >B3 }

fs10 A3}{\fs15 <B3 }
fs11 A3}{\i0 \f10 \fs11 =}{\fs15 B3 }
fs15 A3=B3 }
fs10 A3}{\i0 \f10 \fs11 =}{\fs15 B, }
fs15 A,}{\i0\dn006 \f10 \fs10 =}{\fs15 B3 }
fs11 A3}{\i0 \f10 \fs10 =}{\fs15 B3 }
fs14 A,}{\i0 \f10 \fs10 =}{\fs15 B3 }
fs14 A,}{\i0 \f10 \fs10 =}{\fs15 B3 }
fs11 A3}{\i0 \f10 \fs10 =}{\fs15 B3 }
fs14 A,}{\i0 \f10 \fs11 =}{\fs15 B3 }
fs11 A3}{\i0 \f10 \fs10 =}{\fs15 B3 }
fs15 A,}{\i0 \f10 \fs11 =}{\fs15 B3 }\par
}
\fs15 \cf0 X
fi228 {\fs15 X }
\b0\i \fs15 A,>B2 }
\b0\i \fs11 A2}{\b0\i \fs15 <B2 }
\b0\i \fs15 A,}{\b0\dn006 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs15 A,}{\b0\dn006 \f10 \fs10 =}{\b0\i \fs15 B2 }
\b0\i \fs11 A2}{\b0 \f10 \fs11 =}{\b0\i \fs15 B2 }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs11 =}{\b0\i \fs15 B, }
\b0\i \fs15 A,}{\b0 \f10 \fs11 =}{\b0\i \fs15 B, }
\b0\i \fs11 A2}{\b0 \f10 \fs10 =}{\b0\i \fs15 B2 }
\b0\i \fs14 A,}{\b0 \f10 \fs11 =}{\b0\i \fs15 B2 }\par
}
\fs15 \cf0 X
fi222 {\fs15 X }
fi222 {\fs15 X }
fi222 X
\b0\i \fs15 A}{\b0\i \fs15 l}{\b0\i \fs15 >}{\b0\i \fs15 B}{\b0\i \fs15 l }
\b0\i \fs14 AI}{\b0\i \fs15 <Bl }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs11 =}{\b0\i \fs15 B, }\par
}
\fs15 \cf0 X
fi223 {\fs15 X }
fi221 X
fi221 X
fi221 {\fs15 X }
fi223 {\fs15 X }
\b0\i\dn006 \fs10 A0}{\b0 \f10 \fs17 >}{\b0\i \fs15 B, }
\i\dn006 \f10 \fs10 A0}{\b0\i \fs15 <}{\b0\i \fs15 B}{\b0\i \fs15 , }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\b0\i \fs15 A,=}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs10 =}{\b0\i \fs15 B, }
\i \f10 \fs14 A,}{\b0 \f10 \fs10
=}{\b0\i \fs15 B, }
\b0\i \fs14 A,}{\b0 \f10 \fs11 =}{\b0\i \fs15 B, }\par
}
\cf0 A > B
fi158 {\b\i0 \f30 \fs17 X }
fi158 {\b\i0 \fs15 X }
fi158 {\b\i0 \fs15 X }
fi158 {\b\i0 \fs15 X }
fi154 {\b\i0 \fs15 X }
fi158 {\b\i0 \fs15 X }

fi158 {\b\i0 \fs15 X }
fi158 {\b\i0 \fs15 X }
fi154 {\i0 \fs15 H }
fi168 {\b\i0 \fs15 L }
fi158 {\b\i0 \fs15 X }
fi154 {\i0 \fs15 H }
fi168 {\i0 \fs15 L }\par
}
\cf0 Cascading
fi142 inputs
fi136 {\b0\i \fs15 A}{\b0\i \fs15 <}{\b0\i \fs15 B }
fi293 {\fs15 X }
fi293 {\fs15 X }
fi288 {\fs15 X }
fi288 {\fs15 X }
fi288 {\f30 \fs16 X }
fi293 {\fs15 X }
fi293 {\fs15 X }
fi288 {\fs15 X }
fi303 {\fs15 L }
fi286 {\b0 \fs15 H }
fi293 {\fs15 X }
fi288 {\fs15 H }
fi303 {\fs15 L }\par
}
\cf0 A = B
fi154 {\b\i0 \fs15 X }
fi154 {\b\i0 \fs15 X }
fi154 {\b\i0 \f30 \fs17 X }
fi152 {\b\i0 \fs15 X }
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
fi154 {\b\i0 \fs15 X }

fi154 {\b\i0 \fs15 X }
fi154 {\b\i0 \fs15 X }
fi154 {\b\i0 \fs15 X }
fi166 {\b\i0 \fs15 L }
fi166 {\b\i0 \fs15 L }
fi154 {\b\i0 \fs15 H }
fi168 {\i0 \fs15 L }
fi166 {\b\i0 \fs15 L }\par
}
\cf0 A > B
fi157 {\i0 \fs15 H }
fi171 {\b\i0 \fs15 L }
fi151 {\i0 \fs15 H }
fi167 {\b\i0 \fs15 L }
fi151 {\i0 \fs15 H }
fi171 {\b\i0 \fs15 L }
fi157 {\i0 \fs15 H }
fi167 {\b\i0 \fs15 L }
fi151 {\i0 \fs15 H }
fi167 {\i0 \fs15 L }
fi171 {\b\i0 \fs15 L }
fi171 {\b\i0 \fs15 L }
fi151 {\i0 \fs15 H }\par
}
\cf0 outputs
fi61 {\b0\i \fs15 A}{\b0\i \fs15 <}{\b0\i \fs15 B }
fi236 {\b0 \fs15 L }
fi216 {\b0 \fs15 H }
fi230 {\fs15 L }
fi216 {\b0 \fs15 H }
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\fs15
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
\cf0 \
fi230 {\fs15 L }
fi216 {\fs15 H }
fi230 {\fs15 L }
fi216 {\b0 \fs15 H }
fi230 {\fs15 L }
fi216 {\b0 \fs15 H }
fi230 {\b0 \fs16 L }
fi230 {\fs15 L }
fi216 {\fs15 H }\par
}
\cf0 A = B
fi169 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi171 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }
fi169 {\i0 \fs15 L }
fi165 {\i0 \fs15 L }
fi155 {\i0 \fs15 H }
fi171 {\b\i0 \fs15 L }
fi169 {\b\i0 \fs15 L }\par
}
i \f20 \fs15 \cf0 (b){\i0 Truth}{\i0 table }
\cf0 {\i0 \fs17 Fig.}{\i0 \fs16 13-22}{\i0 \fs17
74HC85}{\i0 \fs17 4-bit}{
\i0 \fs17 magnitude}{\i0 \fs17 comparator}{\b0 \fs16 (Courtesy}{\b0 \fs17 of}
{\b0 \fs16 National}{\b0 \fs16 SemiconductorCorporation) }\par
}
as "Correct," "Too high," or "Too low." The player can then guess again until
reaching the correct
ber. The player with the fewest guesses wins the game.
360 {\b A} logic diagram of the guess-the-number game is illustrated in Fig. 1

3-24. To play the game, first
\par}{\phpg\posx907\pvpg\posy11795\absw9434\absh1696 \sl-244 \f20 \fs18 \cf0 pre
ss switch{\b\i SW,,} allowing clock pulses to reach the clock input{\i
\fs24 (D)}of the 4-bit binary counter
HC393). When the switch is released, the counter will stop at some random binary
count from{\fs19 0000 }
1111. The random count is applied to the{\b\i \fs19 B} data-compar
e inputs{\fs19 of} the 4-bit magnitude
parator. Next the player makes a guess (from 0000 to llll,), which
is applied to the{\b\i \f10
A }
a-compare inputs{\fs18 of} the comparator. The 74HC85 IC compares the magnitu
des{\fs18 of} the guess and \par
}
f0 CHAP. 131 \par
}
}
f0 337 \par
}
D
{\i \fs16 vcc }
fs15 GND }\par
}
15 \cf0 A{\b0\i0 \f10 \fs17 >} Bin
cf0 A{\b0\i0 \f10 \fs10
=} Bin
A <Bin \par
}
15 \cf0 A0
AI
A2
A3 \par
}
15 \cf0 A ,
cf0 A2
A3 \par
}
f20 \fs15 \cf0 74HC85

\fi36 {\i0 \fs15 magnitude }
{\i0 \fs15 comparator }
cf0 \fi264 IC, \par
}
cf0 Inputs \par
}
\cf0 TWO
5 {\b \fs15 8-bit }
fs15 binarywords }\par
}
s15 \cf0 BO
Bl
B2
\cf0 B3 \par
}
15 \cf0 BO
Bl
B2
B3 \par
}
15 \cf0 A{\b0\i0 \f10 \fs18 >} Bout{\b0\i0 \f10 \fs19 - }
A =Bout{\b0\i0 \f10 \fs15
- }
A <Bout{\b0\i0 \f10 \fs15
- }\par
}
15 \cf0 A4
A5 \par
}
15 \cf0 A7 \par
}
15 \cf0 A ,
cf0 A2
A3 \par
}
f20 \fs15 \cf0 74HC85

\fi32 {\i0 \fs15 magnitude }
{\i0 \fs15 comparator }
cf0 \fi264 IC2 \par
}
\cf0 outputs
f0 \fi162 {\i \fs15 A}{\i \fs15 >}{\i \fs15 B }
f0 \fi162 {\i \fs15 A}{\i \fs15 =}{\i \fs15 B }
f0 \fi162 {\i \fs15 A}{\i \fs15 <}{\i \fs15 B }\par
}
15 \cf0 B4
B5
cf0 {\fs10 B6 }
{\fs16 B? }\par
}
15 \cf0 Bo
Bl
B2
B3 \par
}
15 \cf0 A \par
}
\par
}
15 \cf0 Bout \par
}
15 \cf0 A{\b0\i0 \f10 \fs10
=} Bout
{\dn006 A}{\b0\i0 \f10 \fs17 <}Bout \par
}
0 \fs16 \cf0 Fig.{\fs17 13-23}{\fs15
Cascading}{\fs17 74HC85}{\fs15 magnit
ude}{\fs15 comparator }
f0 {\b0 \fs19 random}{\b0 \fs19 inputs}{\b0 \fs19 and}{\b0 \fs19 generates}{\
b0 \fs19 a}{\b0 \fs19 HIGH}{\b0 \fs19 output}{\b0 \fs19 at}{\b0 \fs19 one}{
\b0 \fs19 output,}{\b0 \fs19 lighting}{\b0 \fs19 one}{\b0 \fs19 of}{\b0 \fs1
9 the}{\fs19 LEDs.}{\b0 \fs19 If}{\b0 \fs19 the}{\b0 \fs19 guess}{\b0 \fs19
is }
\b0 \fs19 the}{\b0 \fs19 same}{\b0 \fs19 as}{\b0 \fs19 the}{\b0 \fs19 random
}{\b0 \fs19 number,}{\b0 \fs19 the}{\i \fs19 A}{\i \fs19 =Bout}{\b0 \fs19
output}{\b0 \fs19 goes}{\b0 \fs19 HIGH,}{\b0 \fs19 causing}{\b0 \fs19 the}{

\b0 \fs19 green}{\fs19 LED}{\b0 \fs19 to}{\b0 \fs19 light, }
\b0 \fs19 and}{\b0 \fs19 the}{\b0 \fs19 player}{\b0 \fs19 wins.}{\b0 \fs19 I
f}{\b0 \fs19 the}{\b0 \fs19 guess}{\b0 \fs19 is}{\b0 \fs19 lower}{\b0 \fs19
than}{\b0 \fs19 the}{\b0 \fs19 random}{\b0 \fs19 number,}{\b0 \fs19 the}{\
i \fs19 A}{\fs19 <Bout}{\b0 \fs19 output}{\b0 \fs19 goes}{\b0 \fs19 HIGH,
}
\b0 \fs19 causing}{\b0 \fs19 the}{\b0 \fs19 yellow}{\fs19 LED}{\b0 \fs19 to}
{\b0 \fs19 light.}{\b0 \fs19 If}{\b0 \fs19 the}{\b0 \fs19 guess}{\b0 \fs19
is}{\b0 \fs19 higher}{\b0 \fs19 than}{\b0 \fs19 the}{\b0 \fs19 random}{\b0
\fs19 number,}{\b0 \fs19 the}{\i \fs19 A}{\b0 \fs19 >Bout}{\b0 \fs19 outpu
t }
\b0 \fs19 goes}{\b0 \fs19 HIGH,}{\b0 \fs19 causing}{\b0 \fs19 the}{\b0 \fs19
red}{\b0 \fs19 LED}{\b0 \fs19 to}{\b0 \fs19 light.}{\b0 \fs19 The}{\b0 \fs1
9 person's}{\b0 \fs19 next}{\b0 \fs19 guess}{\b0 \fs19 can}{\b0 \fs19 then}
{\b0 \fs19 be}{\b0 \fs19 adjusted}{\b0 \fs19 based}{\b0 \fs19 on}{\b0 \fs19
the }
\b0 \fs19 information}{\b0 \fs19 gained}{\b0 \fs19 from}{\b0 \fs19 the}{\b0 \
fs19 "Too}{\b0 \fs19 high"}{\b0 \fs19 or}{\b0 \fs19 "Too}{\b0 \fs19 low"}{\
b0 \fs19 outputs}{\b0 \fs19 of}{\b0 \fs19 the}{\b0 \fs19 guess-the-number}{\
b0 \fs19 game. }
fi369 {\b0 \fs19 In}{\b0 \fs19 the}{\b0 \fs19 guess-the-number}{\b0 \fs19 gam
e,}{\b0 \fs19 the}{\b0 \fs19 three}{\b0 \fs19 outputs}{\b0 \fs19 of}{\b0 \fs
19 the}{\b0 \fs19 74HC85}{\b0 \fs19 generate}{\b0 \fs19 information}{\b0 \fs
19 that}{\b0 \fs19 is}{\b0 \fs19 used }
\b0 \fs19 by}{\b0 \fs19 the}{\b0 \fs19 player}{\b0 \fs19 to}{\b0 \fs19 adjus
t}{\b0 \fs19 the}{\b0 \fs19 next}{\b0 \fs19 guess.}{\b0 \fs19 In}{\b0 \fs19
like}{\b0 \fs19 manner,}{\b0 \fs19 magnitude}{\b0 \fs19 comparators}{\b0 \fs
19 may}{\b0 \fs19 be}{\b0 \fs19 used}{\b0 \fs19 in}{\b0 \fs19 digital }
\b0 \fs19 equipment}{\b0 \fs19 to}{\b0 \fs19 generate}{\i \fs19 feedback}{\b
0 \fs19 to}{\b0 \fs19 circuitry}{\b0 \fs19 that}{\b0 \fs19 can}{\b0 \fs19
make}{\b0 \fs19 adjustments}{\b0 \fs19 in}{\b0 \fs19 the}{\b0 \fs19 in
put.}{\b0 \fs19 Feedback}{\b0 \fs19 is}{\b0 \fs19 a }
\b0 \fs19 critical}{\b0 \fs19 item}{\b0 \fs19 in}{\b0 \fs19 automated}{\b0 \f
s19 equipment.}{\b0 \fs19 For}{\b0 \fs19 instance,}{\b0 \fs18 if}{\b0 \fs19
a}{\b0 \fs19 physical}{\b0 \fs19 variable}{\b0 \fs19 (such}{\b0 \fs19 as}{\
b0 \fs19 temperature,}{\b0 \fs19 speed, }
\b0 \fs19 position,}{\b0 \fs19 time,}{\b0 \fs19 light}{\b0 \fs19 intensity
,}{\b0 \fs19 pressure,}{\b0 \fs19 weight,}{\b0 \fs19 etc.)}{\b0 \fs19 is
}{\b0 \fs19 converted}{\b0 \fs19 into}{\b0 \fs19 binary}{\b0 \fs19 form}
{\b0 \fs19 by}{\b0 \fs19 an}{\fs19 A/D }
\b0 \fs19 converter,}{\b0 \fs19
this}{\b0 \fs19 measurement}{\b0 \fs19
c
an}{\b0 \fs19 be}{\b0 \fs19
sent}{\b0 \fs19 to}{\b0 \fs19 one}{\b0 \fs1
9 of}{\b0 \fs19
the}{\b0 \fs19 data-compare}{\b0 \fs19
inputs}{\b0 \fs
19 of}{\b0 \fs19
a}{\b0 \fs19 magnitude }
\b0 \fs19 comparator.}{\b0 \fs19 The}{\b0 \fs19 other}{\b0 \fs19 data-compare
}{\b0 \fs19 inputs}{\b0 \fs19 are}{\b0 \fs19 set}{\b0 \fs19 by}{\b0 \fs19 t
he}{\b0 \fs19 operator}{\b0 \fs19 at}{\b0 \fs19 the}{\b0 \fs19 proper}{\b0 \
fs19 level.}{\b0 \fs19 The}{\b0 \fs19 outputs}{\b0 \fs18 of }

\b0 \fs19 the}{\b0 \fs19 magnitude}{\b0 \fs19 comparator}{\b0 \fs19 will}{\b
0 \fs19 be}{\b0 \fs19 used}{\b0 \fs19 to}{\b0 \fs19 activate}{\b0 \fs19 ci
rcuitry}{\b0 \fs19 to}{\b0 \fs19 drive}{\b0 \fs19 the}{\b0 \fs19 physical}{\
b0 \fs19 variable}{\b0 \fs19 toward}{\b0 \fs19 the }
\b0 \fs19 proper}{\b0 \fs19 level. }
fi354 {\fs18 A}{\b0 \fs19 simple}{\b0 \fs19 example}{\b0 \fs18 of}{\b0 \fs19
how}{\b0 \fs19 a}{\b0 \fs19 magnitude}{\b0 \fs19 comparator}{\b0 \fs19 migh
t}{\b0 \fs19 be}{\b0 \fs19 used}{\b0 \fs19 in}{\b0 \fs19 a}{\b0 \fs19 contr
ol}{\b0 \fs19 application}{\b0 \fs19 is}{\b0 \fs19 shown }
\b0 \fs19 in}{\b0 \fs19 Fig.}{\fs19 13-25.}{\b0 \fs19 In}{\b0 \fs19 this}{\b
0 \fs19 example}{\b0 \fs19 the}{\b0 \fs19 temperature}{\b0 \fs19 in}{\b0 \fs
19 an}{\b0 \fs19 oven}{\b0 \fs19 is}{\b0 \fs19 to}{\b0 \fs19 be}{\b0 \fs19
controlled.}{\b0 \fs19 The}{\b0 \fs19 temperature}{\b0 \fs19 sensor }\par
}
0 338 \par
}
cf0 OTHER DEVICESAND TECHNIQUES \par
}
}
\cf0 Fig.{\fs17 13-24}{\fs17
Electronicguess-the-numbergame }\par
}
\cf0 temperature sensor \par
}
\par
}
cf0 Bout \par
}
L \par
}
fs15 \cf0 Magnitude
mparator \par
}
15 \cf0 A \par
}
15 \cf0 A \par
}
cf0 i. \par
}
cf0 Analog

i47 signal \par
}
10 \cf0 t \par
}
\fs15 \cf0 A/D
nverter \par
}
15 \cf0 B \par
}
{\phpg\posx8879\pvpg\posy11179\absw159\absh100 \f10 \fs7 \cf0 \f10 \fs7 \cf0 If
\par
}
\cf0 Temperature
\fi115 controller \par
}
\cf0 A \par
}
\par
}
\cf0 Feedback-decrease
temperature \par
}
\cf0 Fig.{\fs17 13-25}{\fs17
Temperaturecontrol}{\fs17 applicationwith}{\f
s17 magnitudecomparatorgeneratingfeedback }\par
}
. 131 \par
}
}
\par
}
\cf0 sends an analog signal to the{\b \fs19 A/D} converter which generates a{\
fs18 proportional} binary signal. The binary
6 signal enters the{\i \fs19 B} data-compare inputs{\fs19 of} a magni
tude comparator. The operator sets the{\b\i \f10 \fs18 A }
5 data-compare inputs at the proper temperature. If{\fs18 the} oven te
mperature is too low, the{\b\i A}{\f10 \fs21 >}{\b\i \fs19 Bout }
5 output{\fs18 of} the magnitude comparator is activated with this signal fed
back to the temperature control
5 unit. This unit causes the temperature to be increased.{\b \fs19 If}
the oven temperature is too high, the

i\dn006 \f10 \fs17 A}{\f10 \fs21 <}{\i \fs19 B,,,}
output{\fs18 of} the co
mparator is activated and is fed back to the temperature control unit. The
5 temperature control unit would cause the temperature to be decreased in the ov
en.
\fi28 {\f10 \fs16 SOLVED}{\b \f10 \fs16 PROBLEMS }
5 {\b \fs18 13.51}{\b \f10 \fs18 A}
(magnitude, voltage) compa
rator is a(n)
(analog, digital) device that can
23 compare{\fs18 two} binary numbers and output a response such as{\b\i \f10
\fs17 A}{\dn006 \f10 \fs13 =}{\i \fs19 B,}{\b\i \f10 \fs17 A}{\f10 \fs21 >
}{\b\i \fs19 B,} or{\b\i \f10 \fs18 A}{\f10 \fs22 <}{\i \fs19 B. }
78 {\fs17 A}{\fs17 magnitude}{\fs17 comparator}{\fs17 is}{\fs17 a}{\fs17
digital}{\fs17 device}{\fs17 that}{\fs17 can}{\fs17 compare}{\fs17
two}{\fs17 binary}{\fs17
numbers}{\fs17 and}{\fs17 output}{\fs17 a }
26 {\fs17 response}{\fs17 such}{\fs17 as}{\b\i \f10 \fs16 A}{\f10 \fs13
=}{\i \fs17 B,}{\b\i \f10 \fs15 A}{\f10 \fs19 >}{\i \fs17 B,}{\fs17 or}{\b
\i \f10 \fs15 A}{\f10 \fs19 <}{\i \fs17 B. }\par
}
cf0 13.52{\fs19 A}{\b0 \fs18 single}{\b0 \fs18 74HC85}{\fs18 IC}{\b0 \fs18
will}{\b0 \fs18 compare}{\b0 \fs18 two }\par
}
hree responses such as
}
\par
}
\cf0 (4-,{\fs18 8-,}{\fs18 16-)}bit binary numbers and output one{\fs19 of }
0 \fs20 ,}or{\b\i \fs19 A}{\b\i <}{\b\i B}{\b\i . }\par
}
\cf0 A single 74HC85 IC will compare two 4-bit binary numbers and outpu
t one{\fs17 of} three responses such
\par}{\phpg\posx1479\pvpg\posy6375\absw8240\absh397 \sl-226 \f20 \fs17 \cf0 as{\
b\i \f10 \fs15 A}{\i \fs17 =}{\i \fs17 B}{\i \fs17 ,}{\b\i \f10 \fs16 A}{
\i \fs17 >}{\i \fs17 B}{\i \fs17 ,} or{\b\i \f10 \fs15 A}{\i \fs17 <B. }
\par
}
\cf0 13.53{\b0 \fs18 What}{\b0 is}{\b0 \fs18 the}{\b0 \fs18 purpose}{\b0 \
fs18 of}{\b0 \fs18 the}{\b0 \fs18 cascading}{\b0 \fs18 inputs}{\b0 \fs18 o
n}{\b0 \fs18 the}{\b0 \fs18 74HC85}{\b0 \fs18 IC}{\b0 \fs18 shown}{\b0 \fs18
in}{\b0 \fs18 Fig.}{\b0 \fs18 13-22a? }

fi942 {\b0 \fs17 The}{\b0 \fs17
74HC85}{\fs16
ICs}{\b0 \fs17
can}{\b0 \
fs17
be}{\b0 \fs17
cascaded}{\b0 \fs17
(see}{\b0 \fs17
Fig.}{\b0 \fs
17
13-23)}{\b0 \fs17 to}{\b0 \fs17
make}{\b0 \fs17
an}{\b0 \fs16
8
-,}{\b0 \fs17 12-,}{\b0 \fs17 or}{\b0 \fs17
16-bit}{\b0 \fs17
magnitud
e }
fi581 {\b0 \fs17 comparator.}{\fs17 If}{\b0 \fs17 not}{\b0 \fs17 cascaded,
}{\b0 \fs17 the}{\i \f10 \fs16 A}{\b0 \f10 \fs13 =}{\fs17 Bin}{\b0 \fs17
input}{\b0 \fs17 should}{\b0 \fs17 be}{\b0 \fs17 tied}{\b0 \fs17 to}{\b
0\i \fs17 V,,}{\b0 \fs17
while}{\b0 \fs17 the}{\i \f10 \fs15 A}{\b0 \
f10 \fs19 >}{\fs17 Bin}{\b0 \fs17 and}{\i \f10 \fs16
A}{\b0 \f10 \fs19 <}
{\fs17 Bin }
fi582 {\b0 \fs17 cascade}{\b0 \fs17 inputs}{\b0 \fs17 should}{\b0 \fs17 be}
{\b0 \fs17 grounded. }\par
}
.}{\fs19 If}{\b0 \fs18 the}{\b0 \fs18 inputs}{\b0 \fs18 are}{\i \f10 \fs1
8 A,}{\b0 \fs18 to}{\i \f10 \fs18 A,}{\b0\dn006 \f10 \fs13 = }
i586 {\b0 \fs18 output}{\b0 \fs18 will}{\b0 \fs18 be}{\b0 \fs18 activated? }
}
\fs17 \cf0 If{\i \f10 \fs16 A,}{\b0 \fs17 to}{\i \f10 \fs16 A,}{\b0 \f10
\fs13 =}{\b0 \fs17 00110011}{\b0 \fs17 and}{\b0\i B,}{\b0 \fs17 to}{\b0\
i B,}{\b0\dn006 \f10 \fs11 = }
\b0 \fs17 with}{\b0 \fs17 a}{\b0 \fs17 HIGH. }\par
}
0110011{\fs18 and}{\i \fs19 B,}{\fs18 to}{\b\i \fs19 B,}{\dn006 \f10 \fs1
3 = }\par
}
1110000,{\fs18 which }\par
}
1110000, then the{\b\i \f10 \fs15 A}{\b\i \fs17 <Bout} output{\fs16 of} I
C, will be activated \par
}
\cf0 13.55{\b0 \fs18
}{\b0 \fs18 The}{\b0\i \fs19 555}{\b0 \fs18 timer}{\b0 \fs18 IC}{\b0 \fs18 i
s}{\b0 \fs18 wired}{\b0 \fs18 as}{\b0 \fs18 a(n) }
fi583 {\b0 \fs18 tor}{\b0 \fs18 in}{\b0 \fs18 this}{\b0 \fs18 game}{\b0 \fs18
circuit. }
}
(astable, monostable) multivibra- \par
}
\cf0 The{\i \fs17 555} timer IC in Fig. 13-24 is wired as an astable m
ultivibrator generating a continuous string{\b \fs17 of }

94 clock pulses.
{\b \fs18 13.56}{\fs18 Refer}{\fs18 to}{\fs18 Fig.}{\fs18 13-24.}{\b \fs19
If}{\fs18 the}{\fs18 binary}{\fs18 counter}{\fs18 holds}{\fs18 the}{\fs18
number}{\fs18 0101,}{\fs18 and}{\fs18 your}{\fs18 guess}{\fs18 is}{\fs18
lOOO,,}{\fs18 the }\par
}
8 \cf0 (color){\fs18 LED} will light, indicating your guess{\fs18 is }
}
(correct,{\fs19 too} high,{\fs18 too}{\fs18 low). }\par
}
0 \fs17 \cf0 If{\b0 \fs17 the}{\b0 \fs17 binary}{\b0 \fs17 counter}{\b0 \fs1
7 holds}{\b0 \fs17 the}{\b0 \fs17 number}{\b0 \fs17 0101}{\b0 \fs17 and}{
\b0 \fs17 your}{\b0 \fs17 guess}{\b0 \fs17 is}{\b0 \fs17 1000,}{\b0 \fs17
the}{\b0 \fs17 red}{\fs17 LED}{\b0 \fs17 will}{\b0 \fs17 light,}{\b0 \fs17
indicating }
{\b0 \fs17 your}{\b0 \fs17 guess}{\b0 \fs17 is}{\b0 \fs17 too}{\b0 \fs17 h
igh. }\par
}
0 340 \par
}
HER DEVJCES AND TECHNIQUES \par
}
AP.{\fs17
13 }\par
}
\cf0 13.57{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-25.}{\b0 The}{\b0 magnitu
de}{\b0 comparator}{\b0 in}{\b0 this}{\b0 control}{\b0 application}{\b0
is}{\b0 used}{\b0 to}{\b0 generate }
fi591 {\b0 digital}{\b0
(feedback,}{\b0 random)}{\b0 signals}{\
b0 which}{\b0 cause}{\b0 the}{\b0 temperature}{\b0 controller}{\b0 to
}{\b0 turn}{\b0 the }
fi591 {\b0 oven}{\b0 heating}{\b0 element}{\b0 either}{\b0 on}{\b0 or}{\b0
off. }
fi951 {\b0 \fs16 The}{\b0 \fs16 magnitude}{\b0 \fs16 comparator}{\b0 \fs16
in}{\b0 \fs16 Fig.}{\b0 \fs16 13-25}{\b0 \fs16 is}{\b0 \fs16 used}{\b0 \fs
16 to}{\b0 \fs16 generate}{\b0 \fs16 digital}{\b0 \fs16 feedback}{\b0 \f
s16 signals}{\b0 \fs16 which}{\b0 \fs16 cause}{\b0 \fs16 the }
fi593 {\b0 \fs16 temperature}{\b0 \fs16 controller}{\b0 \fs16 to}{\b0 \fs16
turn}{\b0 \fs16 the}{\b0 \fs16 oven}{\b0 \fs16 heating}{\b0 \fs16 cleme
nt}{\b0 \fs16 either}{\b0 \fs16 on}{\b0 \fs16 or}{\b0 \fs16 off. }\par
}

cf0 13.58{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0
13-25.}{\b0 \fs18 If}{\b0
the}{\b0 preset}{\b0 temperature}{\b0 setting}{\b0 is}{\b0 11110000,
}{\b0 (at}{\b0 input}{\i \f30 \fs20 14)}{\b0 and}{\b0 the }\par
}
emperature signal is 110O111l2 (at input{\i \fs18 B),} then the
\par}{\phpg\posx1441\pvpg\posy3605\absw4917\absh716 \sl-237 \f20 \fs18 \cf0 ture
feedback line will be activated.
}
decrease, increase) tempera- \par
}
\cf0 If{\fs16 the}{\fs16 preset}{\fs16 temperature}{\fs16 setting}{\fs1
6 is}{\fs16 11110000,}{\fs16 and}{\fs16 the}{\fs16 tcmpcrature}{\fs16
signal}{\fs16 is}{\fs16
11001111,,}{\fs16 then}{\fs16 thc }
16 increase}{\fs16 temperature}{\fs16 feedback}{\fs16 line}{\fs16 will}{
\fs16 be}{\fs16 activated. }\par
}
cf0 13.59{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-26.}{\b0 List}{\b0 the}{\b
0\i \fs19 color}{\b0 of}{\b0 the}{\b0 output}{\b0 \fs19 LED}{\b0 that}{\
b0 is}{\b0 lit}{\b0 for}{\b0 each}{\b0 time}{\b0 period}{\b0\i \fs17 (}
{\b0\i \fs17 t}{\b0\i \fs17 l}{\b0 \fs19 to}{\b0\i \fs17 ts). }\par
}
\par
}
\cf0 1 \par
}
\cf0 Fig. 13-26{\b0 \fs16
Magnitude}{\b0 \fs16 comparator}{\b0 \fs16 puls
e-train}{\b0 \fs16 problem }\par
}
\cf0 Solution:
\fi354 {\b0 \fs17 The}{\b0 \fs16 color}{\b0 \fs16 of}{\b0 \fs16 the}{\b0 \
fs16 output}{\b0 \fs16 LED}{\b0 \fs16 that}{\b0 \fs16 is}{\b0 \fs16 li
t}{\b0 \fs16 for}{\b0 \fs16 each}{\b0 \fs16 time}{\b0 \fs16 period}{\b0
\fs16 is}{\b0 \fs16 as}{\b0 \fs16 follows: }
{\b0 \fs16 time}{\b0 \fs16 period}{\b0\i \fs15 t}{\b0\i \fs15 ,}{\b0\dn006
\f10 \fs7
=:}{\b0 \fs16 yellow}{\b0 \fs16 LED}{\b0 \fs16 lit }\par
}
time period{\i t,}{\f10 \fs11 =} green LED{\fs16 lit }
e period{\i t,}{\f10 \fs11 =} red LED{\fs15 lit }
e period{\i t,}{\dn006 \f10 \fs10 =} yellow LED lit
e period{\i t,}{\f10 \fs11 =} green LED{\fs16 lit }\par
}
{\phpg\posx4073\pvpg\posy12923\absw30\absh70 \f10 \fs5 \cf0 \f10 \fs5 \cf0 , \pa
r
}
.{\fs17 131 }\par
}
}
\par
}
\cf0 13-9 SCHMITT TRIGGER DEVICES
fi364 {\b0 \fs18 Waveforms}{\b0 \fs18 with}{\b0 \fs18 fast}{\b0 \fs18 rise}{\
b0 \fs18 times}{\b0 \fs18 and}{\b0 \fs18 fast}{\b0 \fs18 fall}{\b0 \fs18 ti
mes}{\b0 \fs18 are}{\b0 \fs18 preferred}{\b0 \fs18 in}{\b0 \fs18 digital}{
\b0 \fs18 circuits.}{\fs18 A}{\b0 \fs18 square}{\b0 \fs18 wave }
\b0 \fs18 is}{\b0 \fs18 an}{\b0 \fs18 example}{\b0 \fs18 of}{\b0 \fs18 a}{\b
0 \fs18 good}{\b0 \fs18 digital}{\b0 \fs18 signal}{\b0 \fs18 because}{\b0 \f
s18 it}{\b0 \fs18 has}{\b0 \fs18 almost}{\b0 \fs18 vertical}{\b0 \fs18 LOWto-HIGH}{\b0 \fs18 and}{\b0 \fs18 HIGH-to-LOW }
\b0 \fs18 edges.}{\fs18 A}{\b0 \fs18 square}{\b0 \fs18 wave}{\b0 is}{\b0 \f
s18 said}{\b0 \fs18 to}{\b0 \fs18 have}{\b0 \fs18 fast}{\b0 \fs18 rise}{\b0
\fs18 and}{\b0 \fs18 fall}{\b0 \fs18 times. }
fi364 {\fs18 A}{\b0 \fs18 waveform,}{\b0 \fs18 such}{\b0 \fs18 as}{\b0 \fs18
the}{\b0 \fs18 sine}{\b0 \fs18 wave}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs1
8 13-27,}{\b0 \fs18 has}{\b0 \fs18 a}{\b0 \fs18 slow}{\b0 \fs18 rise}{\b0 \
fs18 time}{\b0 \fs18 and}{\b0 \fs18 a}{\b0 \fs18 slow}{\b0 \fs18 fall}{\b0
\fs18 time.}{\b0 \fs18 Using}{\b0 \fs18 a }
\b0 \fs18 sine}{\b0 \fs18 wave}{\b0 \fs18 to}{\b0 \fs18 drive}{\b0 a}{\b0
\fs18 normal}{\b0 \fs18 gate,}{\b0 \fs18 counter,}{\b0 \fs18 or}{\b0 \fs1
8 other}{\b0 \fs18 digital}{\b0 \fs18 device}{\b0 \fs18 will}{\b0 \fs18 c
ause}{\b0 \fs18 unreliable}{\b0 \fs18 operation.}{\b0 \fs18 In }
\b0 \fs18 Fig.}{\b0 \fs18 13-27}{\b0 a}{\b0\i \fs18 Schmitt}{\b0\i \fs18 t
rigger}{\b0 \fs18 inverter}{\b0 \fs18 is}{\b0 \fs18 being}{\b0 \fs18 used
}{\b0 \fs18 to}{\b0 \fs18 "square}{\b0 \fs18 up"}{\b0 \fs18 the}{\b0 \fs1
8 sine}{\b0 \fs18 wave}{\b0 \fs17 by}{\b0 \fs18 forming}{\b0 \fs18 a}{\b0
\fs18 square }
\b0 \fs18 wave}{\b0 \fs18 at}{\b0 \fs18 the}{\b0 \fs18 output.}{\b0 \fs18 Th
e}{\b0 \fs18 Schmitt}{\b0 \fs18 trigger}{\b0 \fs18 inverter}{\b0 \fs18 is}{
\b0 \fs18 reshaping}{\b0 \fs18 the}{\b0 \fs18 waveform.}{\b0 \fs18 Schmitt}{
\b0 \fs18 trigger}{\b0 \fs18 devices}{\b0 \fs18 are }
\b0 \fs18 used}{\b0 \fs18 for}{\b0 \fs18 "squaring}{\b0 \fs18 up"}{\b0 \fs18
waveforms.}{\b0 \fs18 This}{\b0 \fs18 process}{\b0 \fs18 is}{\b0 \fs18 s
ometimes}{\b0 \fs18 called}{\b0\i \fs18 signal}{\b0\i \fs18 conditioning. }
\par
}
\cf0 Fig. 13-27{\b0 \fs17
Schmitt}{\b0 \fs17 trigger}{\b0 \fs17 inverter}{\
b0 \fs17 used}{\b0 \fs17 to}{\b0 \fs17 "square}{\fs15 up"}{\b0 \fs17 wavef
orm }\par
}
\fs18 \cf0 A{\b0 \fs18 voltage}{\b0 \fs18 profile}{\b0 \fs18 of}{\b0 \fs18
a}{\b0 \fs18 common}{\b0 \fs18 7404}{\b0 \fs18 inverter}{\b0 \fs18 IC}{\b
0 \fs18 is}{\b0 \fs18 compared}{\b0 \fs18 with}{\b0 \fs18 that}{\b0 \fs18
of}{\b0 \fs18 a}{\b0 \fs18 7414}{\b0 \fs18 Schmitt}{\b0 \fs18 trigger }
b0 \fs18 inverter}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-28.}{\b0 \fs
18 Of}{\b0 \fs18 special}{\b0 \fs18 interest}{\b0 \fs18 is}{\b0 \fs18 t
he}{\b0 \fs18 switching}{\b0 \fs18 threshold}{\b0 \fs18 of}{\b0 \fs18 th
e}{\b0 \fs18 inverters.}{\b0 \fs18 The}{\b0\i switching }\par
}
\cf0 Switching
63 {\fs15 threshold }
\par}{\phpg\posx567\pvpg\posy12167\absw1173\absh498 \sl-172 \f20 \fs15 \cf0 (neg
ative going) \par
}
\cf0 Fig.{\fs16 13-28}{\b0 \fs17
Input}{\b0 \fs17 switching}{\b0 \fs17 th
resholds }\par
}
\par
}
}
AP.{\fs17 13 }\par
}
hreshold{\fs18 is}{\fs18 the}{\fs18 input}{\fs18 voltage}{\fs18 at}{\fs18
which}{\fs18 the}{\fs18 outputs}{\fs18 of}{\fs18 the}{\fs18 digital}{\fs18
device}{\fs18 flip}{\fs18 to}{\fs18 their}{\fs18 opposite}{\fs18 state.}{\
fs18 In }
18 examining}{\fs18 the}{\fs18 input}{\fs18 voltage}{\fs18 profiles}{\fs18
in}{\fs18 Fig.} 13-28,{\fs18 note}{\fs18 that}{\fs18 the}{\fs18 switching
}{\fs18 threshold}{\fs18 is}{\fs18 always}{\fs18 within }
18 the}{\fs18 unshaded}{\fs18 forbidden}{\fs18 or}{\fs18 undefined}{\fs18
region}{\fs18 of}{\fs18 the}{\fs18 device. }
73 {\fs18 In}{\fs18 Fig.} 13-28a{\fs18 you}{\fs18 will}{\fs18 notice}{\fs18
that}{\fs18 the}{\fs18 switching}{\fs18 threshold}{\fs18 for}{\fs18 the}{\
fs18 standard} 7404{\fs18 inverter}{\fs18 is} 1.2{\b \fs18 V. }
18 For}{\fs18 the} 7404{\fs18 inverter,}{\fs18 as}{\fs18 voltage} increase
s{\fs18 from} 0{\fs18 to}{\fs18 about} 1.1{\fs18 V,}{\fs18 the}{\fs18 inp
ut}{\fs18 is}{\fs18 considered}{\fs18 to}{\fs18 be}{\fs18 LOW }
18 (output}{\fs18 of}{\fs18 inverter}{\fs18 would}{\fs18 be}{\fs18 HIGH).}{
\b \fs18 As}{\fs18 the}{\fs18 voltage}{\fs18 increases}{\fs18 closer}{\fs18
to}{\fs18 the}{\fs18 threshold}{\fs18 voltage}{\fs18 of} 1.2{\fs18 V, }
18 the}{\fs18 output}{\fs18 would}{\fs18 flip}{\fs18 to}{\fs18 the}{\f

s18 opposite}{\fs18 state}{\fs18 (output}{\fs18 of}{\fs18 inverter}{\f
s18 to}{\fs18 LOW).}{\fs18 On}{\fs18 the}{\fs18 standard} 7404
18 inverter,}{\fs18 as}{\fs18 voltage} decreases{\fs18 from}{\fs18 near}{
\i \fs19 5}{\fs18 to} 1.3{\fs18 V,}{\fs18 the}{\fs18 input}{\fs18 is
}{\fs18 considered}{\fs18 to}{\fs18 be}{\fs18 HIGH}{\fs18 (output}{\fs18
of }
18 inverter}{\fs18 would}{\fs18 remain} LOW).{\b \fs18 As}{\fs18 the}{\fs18
voltage}{\fs18 continues}{\fs18 to}{\fs18 decrease}{\fs18 to}{\fs18 the}{
\fs18 threshold}{\fs18 voltage}{\fs18 of} 1.2{\fs18 V, }
18 the}{\fs18 output}{\fs18 would}{\fs18 flip}{\fs18 to}{\fs18 the}{\fs18
opposite}{\fs18 state}{\fs18 (output}{\fs18 of}{\fs18 inverter}{\fs18 to
}{\fs18 HIGH).}{\fs18 The}{\fs18 important}{\fs18 idea}{\fs18 on}{\fs18
the }
18 standard} 7404{\fs18 inverter}{\fs18 is}{\fs18 that}{\fs18 the}{\fs18 th
reshold}{\fs18 voltage}{\fs18 is}{\fs18 the}{\fs18 same}{\fs18 for}{\fs18
both}{\fs18 L-to-H}{\fs18 and}{\fs18 H-to-L}{\fs18 transitions }
\par}{\phpg\posx807\pvpg\posy1328\absw9080\absh7391 \sl-236 \f20 \fs19 \cf0 of{\
fs18 the}{\fs18 input.}{\fs18 This}{\fs18 can}{\fs18 cause}{\fs18 tr
ouble}{\fs18 when}{\fs18 the}{\fs18 input}{\fs18 signal}{\fs18 has}{\f
s18 a}{\fs18 slow}{\fs18 rise}{\fs18 time}{\fs18 because}{\fs18 seve
ral }
18 oscillations}{\fs18 (H-L-H}{\fs18 or}{\fs18 L-H-L)}{\fs18 can}{\fs18 occ
ur}{\fs18 at}{\fs18 the}{\fs18 output}{\fs18 when}{\fs18 the}{\fs18 thresh
old}{\fs18 voltage}{\fs18 is}{\fs18 crossed. }
74 {\fs18 In}{\fs18 Fig.} 13-28b{\fs18 you}{\fs18 will}{\fs18 notice}{\fs18
that}{\fs18 the}{\fs18 switching}{\fs18 threshold}{\fs18 for}{\fs18 the}{
\fs18 Schmitt}{\fs18 trigger} 7414{\fs18 inverter}{\fs18 is }
18 different}{\fs18 for}{\fs18 the}{\fs18 L-to-H}{\fs18 and}{\fs18 H-to-L}
{\fs18 transitions}{\fs18 of}{\fs18 the}{\fs18 input.}{\fs18 For}{\fs18
the}{\fs18 Schmitt}{\fs18 trigger} 7414{\fs18 inverter,}{\fs18 as }
18 the}{\fs18 voltage} increases{\fs18 from} 0{\fs18 to} 1.6{\b \fs18
V,}{\fs18 the}{\fs18 input} is{\fs18 considered}{\fs18 LOW}{\fs18 (out
put}{\fs18 of}{\fs18 inverter}{\fs18 would}{\fs18 be }
18 HIGH).}{\b \fs19 As}{\fs18 the}{\fs18 voltage}{\fs18 increases}{\fs18
to}{\fs18 the}{\fs18 threshold}{\fs18 voltage}{\fs18 of} 1.7{\b \fs1
8 V,}{\fs18 the}{\fs18 output}{\fs18 would}{\fs18 flip}{\fs18 to}{\fs
18 the }
18 opposite}{\fs18 state}{\fs18 (output}{\fs18 of}{\fs18 inverter}{\fs18
would}{\fs18 go}{\fs18 LOW).}{\fs18 On}{\fs18 the}{\fs18 Schmitt}{\fs1
8 trigger} 7414{\fs18 inverter,}{\fs18 as}{\fs18 voltage }
\par}{\phpg\posx807\pvpg\posy1328\absw9080\absh7391 \sl-230 \f20 \fs19 \cf0 decr
eases{\fs18 from}{\fs18 near}{\i \fs19 5}{\fs18 to}{\fs18 1}{\b \fs18
V,}{\fs18 the}{\fs18 input}{\fs18 is}{\fs18 considered}{\fs18 to}{\fs18
be}{\fs18 HIGH}{\fs18 (output}{\fs18 remains}{\fs18 LOW).}{\b \fs18
As}{\fs18 the }
18 voltage}{\fs18 continues}{\fs18 to}{\fs18 decrease}{\fs18 to}{\fs18 the}
{\fs18 threshold}{\fs18 voltage}{\fs19 of} 0.9{\b \fs18 V,}{\fs18 the}{\fs
18 output}{\fs18 would}{\fs18 flip}{\fs18 to}{\fs18 the}{\fs18 opposite }

18 state}{\fs18 (output}{\fs18 of}{\fs18 inverter}{\fs18 to}{\fs18 HIGH)
.}{\fs18 This}{\fs18 difference}{\fs18 in}{\fs18 threshold}{\fs18 voltage}
{\fs18 for}{\fs18 a}{\fs18 positive-going}{\fs18 (L-to-H) }
18 and}{\fs18 a}{\fs18 negative-going}{\fs18 (H-to-L)}{\fs18 input}{\fs18
signal}{\fs18 is}{\fs18 called} hysteresis.{\fs18 Each}{\fs18 input}{\fs
18 of}{\fs18 Schmitt}{\fs18 trigger}{\fs18 devices }
18 has}{\fs18 hysteresis}{\fs18 which}{\fs18 increases}{\fs18 noise}{\fs18
immunity}{\fs18 and}{\fs18 transforms}{\fs18 a}{\fs18 slowly}{\fs18 chang
ing}{\fs18 input}{\fs18 signal}{\fs18 to}{\fs18 a}{\fs18 fast }
18 changing}{\fs18 output. }
67 {\fs18 Note}{\fs18 in}{\fs18 Fig.} 13-28{\fs18 that}{\fs18 the} hysteresi
s{\b\i \fs18 s}{\b\i \fs18 j}{\b\i \fs18 ~}{\b\i \fs18 ~}{\b\i \fs18 6}{\fs
18 is }
337 {\b\i \fs18 0}{\b\i \fs18 l}{\fs18 placed}{\fs18 in}{\fs18 the}{\fs18 c
enter}{\fs18 of}{\fs18 the}{\fs18 logic}{\fs18 symbol}{\fs18 for}{\fs18 t
hose }
18 digital}{\fs18 devices}{\fs18 that}{\fs18 have}{\fs18 Schmitt}{\fs18 tri
gger}{\fs18 inputs.}{\fs18 The}{\fs18 profiles}{\fs18 of}{\fs18 the}{\fs18
output}{\fs18 voltages}{\fs18 are}{\fs18 the}{\fs18 same}{\fs18 from }
18 both}{\fs18 the}{\fs18 standard} 7404{\fs18 and}{\fs18 Schmitt}{\fs18 t
rigger} 7414{\fs18 inverters. }
69 {\fs18 Schmitt}{\fs18 trigger}{\fs18 inputs}{\fs18 are}{\fs18 also}{\fs18
available}{\fs18 in} CMOS.{\fs18 Some}{\fs18 of}{\fs18 these}{\fs18 incl
ude}{\fs18 the} 4093{\fs18 Quad}{\fs18 2-input }
19 NAND}{\fs18 gate}{\fs18 Schmitt}{\fs18 trigger,} 40106{\fs18 Hex}{\fs18
Schmitt}{\fs18 trigger}{\fs18 inverter,}{\fs18 and} 74HC14{\fs18 Hex}{\fs1
8 inverting}{\fs18 Schmitt }
18 trigger}{\b \fs19 ICs.}{\fs18 Other}{\fs18 TTL}{\fs18 devices}{\fs18 wit
h}{\fs18 Schmitt}{\fs18 trigger}{\fs18 inputs}{\fs18 include}{\fs18 the} 74
LS132 (74132){\fs18 and} 74LS13
19 NAND}{\fs18 gate}{\fs18 ICs. }
\fs18 13.60}{\fs18 Refer}{\fs18 to}{\fs18 Fig.} 13-29.{\fs18 The}{\fs18 hys
teresis}{\fs18 sign}{\fs18 in}{\fs18 the}{\fs18 middle}{\fs18 of}{\fs18 th
e}{\fs18 inverter}{\fs18 logic}{\fs18 symbol}{\fs18 indicates}{\fs18 that }
\par
}
his device has
}
puts. \par
}
The hysteresis sign in the inverter logic symbol indicates that this
device has Schmitt trigger inputs. \par
}
\cf0 Fig.{\fs17 13-29}{\b0 \fs16
Sample}{\b0 \fs16 problem }\par
}
\cf0 13.61{\b0 \fs18 Refer}{\b0 \fs18 to}{\b0 \fs18 Fig.}{\b0 13-29.}{\b0 \
fs18 The}{\b0 \fs18 waveform}{\b0 \fs18 on}{\b0 \fs18 the}{\b0 \fs18 output}
{\b0 \fs18 side}{\b0 \fs18 of}{\b0 \fs18 the}{\b0 \fs18 Schmitt}{\b0 \fs18
trigger}{\b0 \fs18 inverter}{\b0 \fs18 would}{\b0 \fs18 be}{\b0 \fs18 a }
fi1282 {\b0 \fs18 (sign,}{\b0 \fs18 square)}{\b0 \fs18 wave. }
fi944 {\b0 \fs16 The}{\b0 \fs16 waveform}{\b0 \fs17 on}{\b0 \fs16 the}{\b0
\fs16 output}{\b0 \fs16 side}{\b0 \fs16 of}{\b0 \fs16 the}{\b0 \fs16 Sc
hmitt}{\b0 \fs16 trigger}{\b0 \fs16 inverter}{\b0 \fs16 would}{\b0 \fs16
be}{\b0 \fs16 a}{\b0 \fs16 square}{\b0 \fs16 wave. }\par
}
. 131 \par
}
}
f0 343 \par
}
cf0 13.62{\b0 \fs18 The}{\b0 \fs18 Schmitt}{\b0 \fs18 trigger}{\b0 \fs18
inverter}{\b0 \fs18 in}{\b0 \fs18 Fig.}{\b0 \fs18 13-29}{\b0 \fs18 is}{\
b0 \fs18 being}{\b0 \fs18 used}{\b0 \fs18 as}{\b0 \fs18 a}{\b0 \fs18 s
ignal }
i587 {\b0 \fs18 multiplexer)}{\b0 \fs18 in}{\b0 \fs18 this}{\b0 \fs18 circui
t. }
}
conditioner, \par
}
\cf0 The Schmitt trigger inverter is being used as a signal conditioner
in this circuit. It "squares up" the
\par}{\phpg\posx1451\pvpg\posy2249\absw8236\absh392 \sl-224 \f20 \fs16 \cf0 tria
ngular waveform to form a square wave. \par
}
\cf0 13.63{\b0 \fs18 What}{\b0 \fs18 is}{\b0 \fs18 hysteresis}{\b0 \fs18 wh
en}{\b0 \fs18 dealing}{\b0 \fs18 with}{\b0 \fs18 a}{\b0 \fs18 Schmitt}{\b0
\fs18 trigger}{\b0 \fs18 digital}{\b0 \fs18 device? }
fi953 {\b0 \fs16 See}{\b0 \fs16 Fig.}{\b0 \fs16
13-28b.}{\b0 \fs16 Hyster
esis}{\b0 \fs16 is}{\b0 \fs16 the}{\b0 \fs16

input}{\b0 \fs16
characte
ristic}{\b0 \fs16
of}{\b0 \fs16
a}{\b0 \fs16 Schmitt}{\b0 \fs16 trigge
r}{\b0 \fs16 device}{\b0 \fs16 that}{\b0 \fs16
sets}{\b0 \fs16 the }
fi599 {\b0 \fs16 switching}{\b0 \fs16 threshold}{\b0 \fs16 higher}{\b0 \fs16
for}{\b0 \fs16 an}{\b0 \fs16 L-to-H}{\b0 \fs16 input}{\b0 \fs16 (about}{\b
0 \fs16 1.7V}{\b0 \fs16 on}{\b0 \fs16 the}{\b0 \fs16 7414}{\b0 \fs16 inver
ter)}{\b0 \fs16 and}{\b0 \fs16 lower}{\b0 \fs16 for}{\b0 \fs16 an}{\b0 \fs16
H-to-L }
fi597 {\b0 \fs16 input}{\b0 \fs16 (about}{\b0 \fs17 0.9}{\b0 \fs16 V}{\b0
\fs16 on}{\b0 \fs16 the}{\b0 \fs16 7414}{\b0 \fs16 inverter).}{\b0 \fs16
This}{\b0 \fs16 greatly}{\b0 \fs16 improves}{\b0 \fs16 its}{\b0 \fs16
noise}{\b0 \fs16 immunity}{\b0 \fs16 and}{\b0 \fs16 its}{\b0 \fs16 abil
ity}{\b0 \fs16 to }
fi597 {\b0 \fs16 "square}{\b0 \fs16 up"}{\b0 \fs16 input}{\b0 \fs16 signal
s}{\b0 \fs16 with}{\b0 \fs17 slow}{\b0 \fs16 rise}{\b0 \fs16 and}{\b0 \fs
16 fall}{\b0 \fs16 times. }\par
}
\cf0 SupplementaryProblems
\b \f20 \fs16 13.64}{\f20 \fs16 The}{\f20 \fs16 74150}{\f20 \fs16 IC}{\f20
\fs16 is}{\f20 \fs16 described}{\f20 \fs16 by}{\f20 \fs16 the}{\f20 \fs1
6 manufacturer}{\f20 \fs16 as}{\f20 \fs16 a}{\f20 \fs16 16-input }
4 {\b\i \f20 \fs17 Ans.}{\f20 \fs16
data-selector/multiplexer }\par
}
cf0 13.65{\b0 \fs16 The}{\b0 \fs16 74150}{\b0 \fs16 IC}{\b0 \fs16 can}{\
b0 \fs16 be}{\b0 \fs16 used}{\b0 \fs16 for}{\b0 \fs16 changing}{\b0\i \f
10 \fs14
(}{\b0\i \f10 \fs14 a}{\b0\i \f10 \fs14 ) }\par
}
par
}
{\phpg\posx7687\pvpg\posy6332\absw150\absh185 \f10 \fs15 \cf0 \f10 \fs15 \cf0 ,/
\par
}
par
}
parallel, serial) input data to \par
}
cf0 ( b ) \par
}
parallel, serial) \par
}
utput data. The 74150 IC can also be used for solving \par
}
roblems.{\b\i \fs17
Ans.}{\b\i \fs16
(}{\b\i \fs16 a}{\b\i \fs16
)} parallel{\i \fs16
(}{\i \fs16 b}{\i \fs16 )} serial \par
}
combinational, sequential) logic \par

}
{\phpg\posx6341\pvpg\posy7341\absw496\absh126 \f10 \fs10 \cf0 \f10 \fs10 \cf0 -_
__ \par
}
cf0 ( c ) \par
}
\cf0 (c){\i0 \fs16
combinational }\par
}
cf0 13.66{\b0 \f20 \fs16
Draw}{\b0 \f20 \fs16 a}{\b0 \f20 \fs16 block}{\b
0 \f20 \fs16 diagram}{\b0 \f20 \fs16 of}{\b0 \f20 \fs16 a}{\b0 \f20 \fs16
74150}{\b0 \f20 \fs16 data}{\b0 \f20 \fs16 seiector}{\b0 \f20 \fs16 bein
g}{\b0 \f20 \fs16 used}{\b0 \f20 \fs16 to}{\b0 \f20 \fs16 solve}{\b0 \f20
\fs16 the}{\b0 \f20 \fs16 logic}{\b0 \f20 \fs16 problem}{\b0 \f20 \fs16 de
scribed}{\b0 \f20 \fs16 by}{\b0 \f20 \fs16 the }\par
}
Boolean expression{\i \fs21 XBcD}{\f10 \fs25 +}{\b\i \fs21 XBCD}{\f10 \fs24 +
}
\fi2555 {\b \fs16 Data }
2503 {\b \fs15 inputs }
\fi2671 {\b\i \f10 \fs14 0- }\par
}
cf0 ABCB
0 {\fs17 XBCE }\par
}
19 \cf0 CD{\b0\i0 \f10 \fs25 + }\par
}
s17 \cf0 ABCD{\b0\i0 \f10 \fs25 +}{\fs17 XBCD}{\b0\i0 \f10 \fs13 =}{\b0 Y. }\
par
}
s17 \cf0 Ans.{\b0\i0 \fs16
See}{\b0\i0 \fs16 Fig.}{\b0\i0 \fs16 13-30.
}\par
}
\cf0 XHCD \par
}
\cf0 ABED
f0 {\fs17 ABCD }\par
}
\fs14 \cf0 1
\i \f10 \fs14 0- }
fi29 {\f30 \fs12 1-4 }
\i \f10 \fs14 0- }
\i \fs15 0- }
\i \fs15 0- }
fi29 {\f30 \fs15 1 }
\i \fs15 0- }
\i \fs15 0- }
fi25 {\f30 \fs16 I- }
\i \f10 \fs14 0- }
\i \f10 \fs14 0- }
fi27 {\f30 \fs12 1-14 }
\i \f10 \fs14 0- }\par
}
\fs12 \cf0 0
fi43 {\f20 I }
f0 \fi33 {\f20 \fs12 3 }
f0 \fi28 {\i \f10 \fs12 5 }
fi26 {\i \f10 \fs11 6 }
fi33 7
fi33 {\f20 \fs12 8 }
fi36 9
\fs13 10 }
\f20 \fs12 1}{\f20 \fs12 1 }
\f20 \fs13 12 }
\f20 13 }
f0 {\f10 \fs11 15 }\par
}
cf0 16-input
i120 {\fs16 data }
fs16 selector }\par
}
s14 \cf0 0 \par
}
\cf0 Strobe \par

}
\par
}
\cf0 (74150)
cf0 {\f30 \fs17 A}{\f30 \fs17 B}{\f30 \fs17 C}{\f30 \fs17 D}{\f30 \fs17 l }\
par
}
\cf0 select \par
}
\cf0 Fig. 13-30{\b0 \fs16
Combinational}{\b0 \fs16 logicproblem}{\b0 \fs16
solved}{\b0 \fs16 by}{\b0 \fs16 using}{\b0 \fs16 a}{\b0 \fs16 74150}{\b0 \f
s16 data}{\b0 \fs16 selector }\par
}
0 344 \par
}
}
AP.{\fs17 13 }\par
}
cf0 13.67{\b0
Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-5.}{\b0 The}{\b0
letters}{\b0 MUX}{\b0 \fs17 on}{\b0 the}{\b0 counter}{\b0 block}{\b0
diagram}{\b0 stand}{\b0 for }
i475 {\i \fs17 Ans.}{\b0
multiplexer }\par
}
cf0 13.68{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-5.}{\b0 When}{\b0 t
he}{\b0 MUX}{\b0 clock}{\b0 signal}{\b0 is}{\b0 LOW,}{\b0 the }\par
}
\cf0 (left, right) seven-segment LED display.
\b 13.69}{\fs17 To} reduce power consumption,
8 {\b\i Ans.}
LED (light-emitting diode) \par
}
17 \cf0 Ans. \par
}
,{\fs17 right }\par
}
par
}
Is, 10s){\fs17 count}{\fs17 is}{\fs17 lit}{\fs17 on}{\fs17 the }\par
}

LCD, LED) displays are most often multiplexed. \par
}
\cf0 13.70{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-5.}{\b0 If}{\b0 t
he}{\b0 MUX}{\b0 clock}{\b0 frequency}{\b0 were}{\b0 reduced}{\b0 to}{
\b0 \fs17 1}{\b0 Hz,}{\b0 what}{\b0 would}{\b0 happen? }
fi478 {\i \fs17 Ans.}{\b0
The}{\b0 displays}{\b0 would}{\b0 flash}{\b0
on}{\b0 and}{\b0 off.}{\b0 The}{\b0 eye}{\b0 would}{\b0 see}{\b0 the
}{\b0 multiplexing}{\b0 action. }
f0 13.71{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-6.}{\b0 A}{\b0
(HIGH,}{\b0 LOW)}{\b0 at}{\b0 the}{\b0 anode}{\b0 termin
al}{\b0 would}{\b0 activate}{\b0 the}{\b0 seven-segment }
fi506 {\b0 display.}{\i \fs17
Ans.}{\b0
HIGH }
f0 13.72{\fs17 A}{\b0 demultiplexer}{\b0 reverses}{\b0 the}{\b0 action
}{\b0 of}{\b0 a(n)}{\b0 \f10 \fs19
.}{\i
Ans.}{\b0
multiplexer }
f0 13.73{\b0 Refer}{\b0 to}{\b0 the}{\b0 demultiplexer}{\b0 at}{\b0 th
e}{\b0 right}{\b0 in}{\b0 Fig.}{\b0 \fs17 13-7.}{\b0 If}{\b0 the}{\b0 d
ata-select}{\b0 inputs}{\b0 are}{\b0\i \fs17 C}{\b0\dn006 \f10 \fs11 =}{\
b0 \fs17 1,}{\b0\i \fs17 B}{\b0\dn006 \f10 \fs11 =}{\b0 \fs17 1,}{\b0 and}
{\b0 \fs17 A}{\b0\dn006 \f10 \fs11 =}{\b0 0, }
fi506 {\b0 then}{\b0 output}{\b0
(number)}{\b0 is}{\b0
selected}{\b0 and}{\b0 a}{\b0 HIGH}{\b0 will}{\b0 appear}{\b0 at}{\b
0 that}{\b0 output.}{\b0 \fs17
Ans.}{\b0
6}{\b0 or}{\b0 \fs1
7 110, }
f0 13.74{\b0 Demultiplexers}{\b0 are}{\b0 also}{\b0 called}{\b0
distributors}{\b0 or}{\b0 \f10 \fs19
.}{\i
Ans
.}{\b0
data}{\b0 distributors,}{\b0 decoders }
f0 13.75{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-8.}{\b0 Which}{\b0
output}{\b0 of}{\b0 the}{\b0 \fs17 74LS154}{\b0 DEMUX}{\b0 is}{\b0 acti
vated}{\b0 \fs17 if}{\b0 G1}{\b0 and}{\b0 G2}{\b0 are}{\b0 both}{\b0
LOW}{\b0 and }
fi503 {\b0 the}{\b0 data-select}{\b0 inputs}{\b0 are}{\i \f30 \fs19 D}{\b0
\f10 \fs13 =}{\b0 \fs17 1,}{\b0\i \fs17 C}{\b0 \f10 \fs13 =}{\b0 \fs17 1,
}{\b0\i \fs17 B}{\b0 \f10 \fs13 =}{\b0 0,}{\b0 and}{\i \f10 \fs16 A}{\b0
\f10 \fs13 =}{\b0 0.}{\i \f10 \fs15
Ans.}{\b0
output}{\b0 12}
{\b0 or}{\b0 1100, }
f0 13.76{\b0 Refer}{\b0
to}{\b0
Fig.}{\b0 \fs17
13-9a.}{\b0 When}{\
b0
the}{\b0
decimal}{\b0 \fs17
7}{\b0
key}{\b0
is}{\b0
pressed
}{\b0
and}{\b0
released,}{\b0
what}{\b0 \fs17
will}{\b0
appear}{\
b0
on}{\b0
the }
fi500 {\b0 seven-segment}{\b0 output}{\b0 display? }
fi470 {\i \f10 \fs15 Ans.}{\b0
nothing}{\b0 (There}{\b0 is}{\b0 \fs17
no}{\b0 latch}{\b0 to}{\b0 hold}{\b0 the}{\b0 \fs17 7}{\b0 at}{\b0
the}{\b0 inputs}{\b0 \fs16 of}{\b0 the}{\b0 decoder.) }\par
}
cf0 13.77{\b0 The}{\b0 \fs17 7475}{\b0 is}{\b0 a}{\b0 TTL}{\b0 4-bit }\

par
}
{\phpg\posx4863\pvpg\posy7723\absw256\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 IC
. \par
}
s15 \cf0 Ans.{\b0\i0 \f20 \fs17
transparent}{\b0\i0 \f20 \fs17 latch }\pa
r
}
cf0 13.78{\b0 Microprocessor-based}{\b0 systems}{\b0 transfer}{\b0 data}{\b
0 back}{\b0 and}{\b0 forth}{\b0 on}{\b0 a}{\b0 bidirectional}{\b0 paralle
l}{\b0 path}{\b0 called}{\b0 a }
i1135 {\b0 \f10 \fs19 .}{\i \f10 \fs15
Ans.}{\b0
data}{\b0 bus }
0 13.79{\fs17 A}{\b0 two-way}{\b0 buffer}{\b0 that}{\b0 will}{\b0 pass}{
\b0 data}{\b0 to}{\b0 and}{\b0 from}{\b0 a}{\b0 data}{\b0 bus}{\b0 an
d}{\b0 serves}{\b0 to}{\b0 isolate}{\b0 a}{\b0 device}{\b0 from}{\b0 th
e}{\b0 bus}{\b0 is }
i502 {\b0 called}{\b0 a(n)}{\b0 \f10 \fs19
.}{\i \f10 \fs15
Ans.}{\b0
bus}{\b0 transceiver}{\b0 or}{\b0 peripheral}{\b0 inte
rface}{\b0 adapter}{\b0 (PIA) }\par
}
cf0 13.80{\b0 If}{\b0 the}{\b0 outputs}{\b0 of}{\b0 a}{\b0 three-state}
{\b0 buffer}{\b0 are}{\b0 in}{\b0 their }
i502 {\b0 to}{\b0 whatever}{\b0 logic}{\b0 levels}{\b0 exist}{\b0 \fs17 on
}{\b0 the}{\b0 data}{\b0 bus. }\par
}
\cf0 (high-impedance, transmit) state, they will float
i \fs17 Ans.}
high-impedance or high-Z \par
}
\cf0 13.81{\b0 Refer}{\b0
to}{\b0 Fig.}{\b0 \fs17 13-11.}{\b0 The}{\b
0 interfaces}{\b0 between}{\b0
the}{\b0 microprocessor}{\b0 and }
fi497 {\b0 bidirectional}{\b0 buffers}{\b0 sometimes}{\b0 called}{\b0 bus}{
\b0 transceivers.}{\i \fs17
Ans.}{\b0
RAM }\par
}
\cf0 13.82{\b0 The}{\b0 \fs17 74125}{\b0 three-state}{\b0 buffer}{\b0 wil
l }
fi473 {\i Ans.}{\b0
pass}{\b0 data}{\b0 through }\par
}
cf0 13.83 \par
}
(keyboard, RAM) are \par
}
(block data, pass data through) when its control input is LOW. \par
}

7 \cf0 (Parallel, Serial) data transmission is transferring data one bit
at a time over a single line.
\i \fs17 Ans.}
Serial \par
}
\cf0 13.84{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-14b.}{\b0 Device}{
\b0 \fs17 1}{\b0 must}{\b0 be}{\b0 a }
fi478 {\i \f10 \fs15 Ans.}{\b0
parallel-in}{\b0 serial-out }
f0 13.85{\b0 The}{\b0 abbreviation}{\b0 UART}{\b0 stands}{\b0 for }\par
}
{\phpg\posx5415\pvpg\posy12115\absw222\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 in \par
}
{\phpg\posx6329\pvpg\posy12107\absw923\absh192 \f20 \fs17 \cf0 \f20 \fs17 \cf0 out device. \par
}
\par
}
fs15 \cf0 Ans.{\b0\i0 \f20 \fs17
universal}{\b0\i0 \f20 \fs17 asynchronous
}{\b0\i0 \f20 \fs17 receiver-transmitter }\par
}
\cf0 13.86{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 \fs17 13-31.}{\b0 Which}{\b
0 part}{\b0 of}{\b0 the}{\b0 figure}{\b0 illustrates}{\b0 the}{\b0
idea}{\b0 of}{\b0 a}{\b0 serial-in}{\b0 parallel-out}{\b0 register? }
fi478 {\b0 \fs17 Ans.}{\b0
part}{\b0 \fs17 b }\par
}
f0 345 \par
}
. 131 \par
}
}
\cf0 Fig.{\fs17 13-31}{\b0 \fs17 Types}{\b0 \fs17 of}{\b0 \fs17 registers }
\par
}
1.}{\b0 \fs17 Which}{\b0 \fs17 part}{\b0 \fs17 of}{\b0 \fs17 the}{\b0 \fs
17 figure}{\b0 \fs17 illustrates}{\b0 \fs17 the}{\b0 \fs17 idea}{\b0 \fs
17 of}{\b0 \fs17 a}{\b0 \fs17 parallel-in}{\b0 \fs17 serial-out}{\b0 \fs
17 register? }
fi475 {\i \fs17 Ans.}{\b0 \fs17
part}{\b0 \fs16 c }
f0 13.88{\b0 \fs17 A}{\b0 \fs17 data}{\b0 \fs17 bus,}{\b0 \fs17 such}{\b0 \
fs17 as}{\b0 \fs17 that}{\b0 \fs17 used}{\b0 \fs17 within}{\b0 \fs17 a}{\b
0 \fs17 microcomputer,}{\b0 \fs17 forms}{\b0 \fs17 a}{\b0 \fs17 bidirectiona

l}{\b0 \fs17 path}{\b0 \fs17 for}{\b0 \fs17 transmitting }
fi499 {\b0 \fs17 (parallel,}{\b0 \fs17 serial)}{\b0 \fs17 data.}{\i \fs17
Ans.}{\b0 \fs17
parallel }
f0 13.89{\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 13-11.
All}{\b0 \fs17 devices}{\b0 \fs17 interfaced}{\b0 \fs17 with}{\b0 \fs17 a
}{\b0 \fs17 data}{\b0 \fs17 bus}{\b0 \fs17 must}{\b0 \fs17 use}{\b0 \fs17
buffers}{\b0 \fs17 having}{\b0 \fs17
(three-state, }
fi504 {\b0 \fs17 totem-pole)}{\b0 \fs17 outputs.}{\i \fs17
Ans.}{\b0 \
fs17
three-state }\par
}
cf0 13.90{\b0 \fs17 The}{\b0 \fs17 letters}{\b0 \fs17 PLD}{\b0 \fs17 sta
nd}{\b0 \fs17 for }
i475 {\i \fs17 Ans.}{\b0 \fs17
programmable}{\b0 \fs17 logic}{\b0 \fs17 d
evice }\par
}
hen dealing with programmable logic. \par
}
a.}{\b0 \fs17 This}{\b0 \fs17 PLA}{\b0 \fs17 would}{\b0 \fs17 be }
i502 {\b0 \fs17 fuses.}{\i \fs17
Ans.}{\b0 \fs17
programmed }\par
}
activated, programmed) by burning open selected \par
}
.}{\b0 \fs17 An}{\b0 \fs17 abbreviated}{\b0 \fs17 notation}{\b0 \fs17 sys
tem,}{\b0 \fs17 sometimes}{\b0 \fs17 called}{\b0 \fs17 a }\par
}
\cf0 was used to document the programming of this PLA.
\b \fs17 13.93} Refer to Fig. 13-18. This is a fuse map for a
3 {\b\i Ans.}
FPLA (field-programmable logic array) \par
}
\f20 \fs17 \cf0 Ans.{\b0\i0
fuse }
\cf0 {\b0\i0 (FPLA,}{\b0\i0 PAL). }\par
}
fuse, Karnaugh) map, \par
}
.} A{\b0 \fs17 programmable}{\b0 \fs17 logic}{\b0 \fs17 device}{\b0 \fs17 w
ith}{\b0 \fs17 a}{\b0 \fs17 part}{\b0 \fs17 number}{\b0 \fs17 of}{\b0 \fs1
7 PAL16L8}{\b0 \fs17 has }
fi502 {\b0 \fs17 inputs,}{\b0 \fs17
(number)}{\b0 \fs17 outp
uts.}{\b0 \fs17 The}{\b0 \fs17 outputs}{\b0 \fs17 are}{\b0 \fs17 active}{

\b0 \fs17
(HIGH,}{\b0 \fs17 LOW)}{\b0 \fs17 pins. }\par
}
\f20 \fs17 \cf0 Ans.{\b0\i0
16,}{\b0\i0 8,}{\b0\i0 LOW }
\cf0 {\i0 \fs17 13.95}{\b0\i0 The}{\b0\i0 74HC85}{\b0\i0 is}{\b0\i0 a}{\b
0\i0 4-bit }\par
}
number) \par
}
comparator IC. \par
}
magnitude }\par
}
6.Which}{\b0 \fs17 color}{\b0 \fs17 LED}{\b0 \fs17 is}{\b0 \fs17 lit}{\b0
\fs17 during}{\b0 \fs17 time}{\b0 \fs17 period}{\i \fs16 t,? }
fi475 {\i \fs17 Ans.}{\b0 \fs17
red}{\b0 \fs17 (The}{\b0 \fs17 output}{\
i \fs17 A}{\b0 \fs17 >Bout}{\b0 \fs17 goes}{\b0 \fs17 HIGH.) }
f0 13.97{\b0 \fs17 Refer}{\b0 \fs17 to}{\b0 \fs17 Fig.}{\b0 \fs17 13-26.
}{\b0 \fs17 During}{\b0 \fs17 time}{\b0 \fs17 period}{\i \fs16
t,,}{\b0
\fs17 the}{\b0 \fs17
(color)}{\b0 \fs17 LED}{\b0 \fs17
is}{\b0 lit}{\b0 \fs17 because}{\b0 \fs17 the }\par
}
goes HIGH.{\b\i
Ans.}
green,{\b\i A}{\b =Bout }\par
}
utput \par
}
\cf0 13.98{\b0 \fs17 When}{\b0 \fs17 74HC85}{\b0 \fs17 ICs}{\b0 \fs17 are
}{\b0 \fs17 connected}{\b0 \fs17 together}{\b0 \fs17 to}{\b0 \fs17 form}
{\b0 \fs17 8-,}{\b0 \fs17 12-,}{\b0 \fs17 16-bit}{\b0 \fs17 magnitude}{\b0
\fs17 comparators,}{\b0 \fs17 it}{\b0 \fs17 is}{\b0 \fs17 said}{\b0 \fs
17 that }
fi498 {\b0 \fs17 they}{\b0 \fs17 are}{\b0 \fs17
(cascaded,}
{\b0 \fs17 multiplied).}{\i \fs17
Ans.}{\b0 \fs17
cascaded}{\b0 \
fs17 (See}{\b0 \fs17 Fig.}{\b0 \fs17 13-23.) }\par
}
0 346 \par
}
}
AP. 13 \par
}
cf0 13.99{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-24.}{\b0 If}{\b0 the}{\b0

74HC393}{\b0 counter}{\b0 stops}{\b0 at}{\b0 1101,}{\b0 and}{\b0 the}{
\b0 player's}{\b0 guess}{\b0 is}{\b0 Olll,,}{\b0 then}{\b0 the }\par
}
\cf0 (color) LED will light, which means the guess is
i \f10 \fs15 Ans.}
yellow, too low \par
}
correct, too high, too low). \par
}
cf0 13.100{\b0 Refer}{\b0 to}{\b0 Fig.}{\b0 13-25.}{\b0 If}{\b0 the}{
\b0 preset}{\b0 temperature}{\b0 setting}{\b0 is}{\b0 00011000,}{\b0
(at}{\b0 input}{\i \f10 \fs15
A}{\i \f10 \fs15 )}{\b0 and}{\b0 the}{\
b0 temperature }
i594 {\b0 signal}{\b0 from}{\b0 the}{\b0
oven}{\b0 is}{\b0 00011011,}
{\b0 (at}{\b0 input}{\i \fs17
B),}{\b0 then}{\b0 the}{\b0
(decrease,}{\b0
increase)}{\b0 temperature }
i593 {\b0 feedback}{\b0 line}{\b0 is}{\b0 activated.}{\i \fs17
An
s.}{\b0
decrease }
0 13.101{\fs17 A}{\b0
(sine,}{\b0 square)}{\b0 wave}{\b0
is}{\b0 said}{\b0 to}{\b0 have}{\b0 fast}{\b0 rise}{\b0 and}{\b0 f
all}{\b0 times.}{\i \fs16
Ans.}{\b0
square }\par
}
cf0 13.102{\b0 The}{\b0 switching }
i589 {\b0 their}{\b0 new}{\b0 state. }\par
}
\cf0 (threshold, time) is the input voltage at which the outputs of
an inverter flip to
i Ans.}
threshold \par
}
cf0 13.103{\b0 Each}{\b0
input}{\b0
of}{\b0
a}{\b0
Schmitt}{\b0
trigger}{\b0 device}{\b0
has }\par
}
ac coupling, hysteresis) which increases noise \par
}
\cf0 immunity and transforms a slowly changing input signal to a fast-cha
nging output.
i \f10 \fs15 Ans.}
hysteresis \par
}
cf0 13.104{\b0 Schmitt}{\b0 trigger}{\b0 devices}{\b0 are}{\b0 commonly
}{\b0 used}{\b0 for}{\b0 signal }
i566 {\i \f10 \fs15 Ans.}{\b0
conditioning }\par
}
conditioning, multiplexing). \par

}
cf0 Index \par
}
ccess time, 284, 286, 307
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-223 \f20 \fs17 \cf0 ACIA
, 325-326
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-224 \f20 \fs17 \cf0 Acti
ve HIGH, 126-127, 164, 208, 248
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-219 \f20 \fs17 \cf0 Acti
ve LOW, 35, 125-127, 145, 148, 164, 204-205,
76 263, 273
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-224 \f20 \fs17 \cf0 A/D
converter, 116, 131-136, 138, 338-339
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-219 \f20 \fs17 \cf0 Adde
r/subtractor, 190- 191, 193- 194, 196- 197
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-225 \f20 \fs17 \cf0 Addr
ess, 287
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-219 \f20 \fs17 \cf0 Addr
ess bus, 283
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-224 \f20 \fs17 \cf0 Alph
anumeric codes, 24-27
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-225 \f20 \fs17 \cf0 Anal
og-to-digital converter{\fs16 (see} A/D converter)
gate, 29-31, 40-41, 43-44, 46, 55-56,{\fs17 58, }
66 326-335
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-228 \f20 \fs17 \cf0 ANDOR gate pattern, 36-39, 44-47, 58-60, 66,
68 69-71, 77-99, 326, 334
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-224 \f20 \fs17 \cf0 Anod
e, 147, 158-159, 161, 168
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-217 \f20 \fs17 \cf0 ASCI
I, 24-27, 324-326
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-228 \f20 \fs17 \cf0 Asta
ble multivibrator (clock), 133-134, 139,
80 154-158, 204, 220-224, 229, 313-315, 338-339
\par}{\phpg\posx863\pvpg\posy2637\absw4029\absh4181 \sl-224 \f20 \fs17 \cf0 Asyn
chronous, 206, 210, 215-216, 227, 232, 263,
60 265-266, 273 \par
}
ase 2 numbers{\fs16 (see} Binary numbers)
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-222 \f20 \fs17 \cf0 Base
{\fs17 8} numbers{\b\i \fs16 (see} Octal numbers)
10 numbers{\fs16 (see} Decimal number system)
16 numbers{\b\i \fs16 (see} Hexadecimal numbers)
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-221 \f20 \fs17 \cf0 Baud
rate, 325
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-219 \f20 \fs17 \cf0 BCD{

\b\i \fs16 (see} Binary-coded-decimal)
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-228 \f20 \fs17 \cf0 BCDI
C, 25
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-221 \f20 \fs17 \cf0 BCDto-binary conversion, 16-17, 19, 26
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-224 \f20 \fs17 \cf0 BCDto-decimal conversion, 16-17, 19, 26, 140-143
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-225 \f20 \fs17 \cf0 BCDto-decimal decoder/driver, 143-146
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-219 \f20 \fs17 \cf0 BCDto-seven-segment code, 147-152, 155-158
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-225 \f20 \fs17 \cf0 BCDto-seven-segment decoder/driver,
147-152,
62 252-253
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-219 \f20 \fs17 \cf0 BCDto-XS3 conversion, 20-21, 23
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-225 \f20 \fs17 \cf0 Bina
ries, 204
ry addition, 170-174, 184-188, 194, 198-203
ry-coded-decimal codes:
80 4221 BCD code, 18-20, 26
80 5421 BCD code, 18-20, 26
80 8421 BCD code, 16-20, 26
ry numbers, 1, 4-6, 14, 16
ry subtraction, 175-180, 188-192, 199-201
ry-to-BCD conversion, 18-19, 26
ry-to-decimal conversion, 1-3,{\fs17
5,} 12, 14
ry-to-Gray-code conversion, 21-23, 27,
60 287-288, 290-291
ry-to-hexadecimal conversion,{\fs17 8,} 10, 14
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-224 \f20 \fs17 \cf0 Bipo
lar technology, 104
\par}{\phpg\posx861\pvpg\posy7663\absw4051\absh5801 \sl-228 \f20 \fs17 \cf0 BISY
NC, 325 \par
}
Bistable multivibrator (flip-flop), 204, 220-221, 223,
i366 229
\par}{\phpg\posx5645\pvpg\posy2649\absw4089\absh10306 \sl-220 \f20 \fs17 \cf0 Bi
t (binary digit), 1, 4, 14
\par}{\phpg\posx5645\pvpg\posy2649\absw4089\absh10306 \sl-221 \f20 \fs17 \cf0 Bo
olean algebra{\b\i \fs16 (see} Laws of Boolean algebra)
\par}{\phpg\posx5645\pvpg\posy2649\absw4089\absh10306 \sl-222 \f20 \fs17 \cf0 Bo
olean expressions:
i186 for AND function, 28-30

\par}{\phpg\posx5645\pvpg\posy2649\absw4089\absh10306 \sl-221
i186 for AND-OR gate pattern, 36-39
i186 for NAND function, 48-50, 63
i186 for NOR function, 50-51, 63
i184 for NOT function, 34-36
i184 for OR-AND gate pattern, 72-75
i184 for OR function, 32-33
i184 for XNOR function, 54-55, 65
i186 for XOR function, 52-54, 64
i184 from truth table (minterm), 37-39, 69-71
i186 from truth table (maxterm), 72-74
i184 simplification of, 82-103
oadside loading, 269-270, 277
ffer memory, 319
ffer, three-state, 320-324, 344
lk storage (memory), 300-305
s transceivers, 321, 344
zzer, 129, 131
te, 283
0 Calculator, 116, 140, 164
thode, 14.7,158-164
amp diode, 130-131
ock{\b\i \fs16 (see} Astable multivibrator)
ock characteristics, 222
ock cycle time, 222-224
ocked{\b\i \fs17 RS} flip-flop, 206-21 1, 227-228
OS, 42, 105-109, 114-118, 137
OS integrated circuits:
i172 ADC0804 8-bit A/D converter IC, 133-136, 139
i180 2732 32K EPROM IC, 295, 299
\f20 \fs17 \cf0 \f

\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 Br
\f20 \fs17 \cf0 Bu
\f20 \fs17 \cf0 Bu
\f20 \fs17 \cf0 Bu
\f20 \fs17 \cf0 Bu
\f20 \fs17 \cf0 Bu
\f20 \fs17 \cf0 By
\par\f20 \fs17 \cf
\f20 \fs17 \cf0 Ca
\f20 \fs17 \cf0 Cl
\f20 \fs17 \cf0 Cl
\f20 \fs17 \cf0 Cl
\f20 \fs17 \cf0 Cl
\f20 \fs17 \cf0 Cl
\f20 \fs17 \cf0 CM
\f20 \fs17 \cf0 CM
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
i172 4002 4-input NOR gate IC, 61, 117

i172 4012 4-input NAND gate IC, 61
i178 4014 Shift register{\fs17 IC,} 273
i178 4024 7-stage binary counter IC, 115
i178 4028 BCLI-to-decimal decoder IC, 146
i178 4030{\b \fs17 XOR} gate IC, 61
i172 4031 64-stage shift register IC, 273
i172 4034 8-bit shift register IC, 273
i172 4049 Inverted buffer IC, 121-122, 222
i172 4050 Noninverted buffer IC, 121-122
i178 4093 Schrnitt trigger NAND gate IC, 342
i178 40106 Schmitt trigger inverter, 342
i172 40175 D flip-flop IC, 2124
i172 40192 Decade counter IC, 116 \par
}
\cf0 347 \par
}
0 348 \par
}
{\phpg\posx4985\pvpg\posy567\absw630\absh190 \f20 \fs17 \cf0 \f20 \fs17 \cf0 IND
EX \par
}
CMOS integrated circuits:{\i (continued) }
183 4511 BCD-to-seven segment decoder IC, 150,
553 161{\f10 \fs15 -}164, 168- 169
179 4543 BCD-to-seven segment decoder IC, 150,
553 156-158
185 4724 8-bit latch IC, 214
187 74COO NAND gate IC, 61
187 74C02 NOR gate IC, 61, 107
187 74C04 Hex inverter IC, 42
191 74C08 AND gate IC, 42, 47, 137

187 74C30 8-input NAND gate, 61
187 74C32 OR gate IC, 42
187 74C42 BCD-to-decimal decoder IC, 146
187 74C48 BCD-to-seven-segment decoder IC, 150
187 74C76{\i \fs17 JK} flip-flop IC, 214
187 74C86 XOR gate IC, 61
187 74C192 Decade counter IC, 115-116
183 74HC04 Hex inverter IC, 106
183 74HC14 Schmitt trigger inverter IC, 342
183 74HC32 2-input OR gate IC, 116
187 74HC42 BCD-to-decimal decoder IC, 146
185 74HC85 Magnitude comparator IC, 335-340, 345
187 74HC147 Encoder IC, 142
187 74HC193 4-bit up/down counter IC, 246-251,
544 258- 259
183 74HC3934-bit counter IC, 245-249,258,338-339,
544 345-346
187 74HC4511 BCD-to-seven-segment decoder IC,
553 150
183 74HC4543 BCD-to-seven-segment decoder IC,
553 150, 156-158, 201
183 74HCT34 Noninverting{\fs17 IC,} 119-121
183 STK10C68NVSRAM IC, 296-300, 308
binational logic circuits, 69, 102, 170, 204, 227,
364 255, 331
binational logic solutions (data selectors),
359 311-313, 343
binational logic solutions (PLAs), 326-335
plement, 35-36
\f20 \fs17 \cf0 \fi

\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Com
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Com
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Com
\f20 \fs17 \cf0 Com
\f20 \fs17 \cf0 Com
plementary metal-oxide semiconductor{\i (see }

363 CMOS)
trol grid (VF tube), 158-163, 168
version time (A/D converter), 134, 136
\par}{\phpg\posx855\pvpg\posy1373\absw4084\absh11307 \sl-221 \f20 \fs17 \cf0 Cou
nt accumulators, 251-253
\par}{\phpg\posx855\pvpg\posy1373\absw4084\absh11307 \sl-215 \f20 \fs17 \cf0 Cou
nters:
179 asynchronous, 232
177 BCD up/down, 241-244
177 cascading, 241-242, 244
177 characteristics{\fs16 of,} 230
179 decade, 237-239, 241-244, 248-251
177 down (3-bit), 238-240
177 down (4-bit), 256
171 4-bit up/down, 247-251
171 5-bit ripple, 254-255
173 as frequency divider, 232, 251-254, 259
171 mod-2, 253
169 mod-3, 253 \par
}
Counters:{\i (continued) }
i187 mod-5, 254, 257
i183 mod-6, 236-237, 239, 249-254
i187 mod-8, 232-233, 240, 258
i183 mod-9, 240
i189 mod-10, 237-238, 241-244, 251-253
i187 mod-12, 256
i187 mod-16, 230-232, 242-25 1, 255
i191 parallel, 234-236, 255
i187 ripple, 230-233, 236-240, 242-249, 254-255
i187 synchronous, 235-236, 246-251, 255
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-218 \f20 \fs17 \cf0 CP
U (central processing unit), 140
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-219 \f20 \fs17 \cf0 Cr

ystal-controlled oscillator, 222-224, 229
0 {\b\i \f30 \fs19 D} flip-flop, 209-212, 228, 261-263, 272
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-218 \f20 \fs17 \cf0 D/
A converter, 116, 132-133, 135, 138
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-219 \f20 \fs17 \cf0 Da
ta bus, 135, 283, 286, 320-321, 323, 326, 344-345
ta distributor{\i (see} Demultiplexer)
ta flip-flop{\i (see}{\i \fs17 D} flip-flop)
ta selector, 69, 102, 309-313, 343
ta transmission, 324-326
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-218 \f20 \fs17 \cf0 De
cimal number system, 1, 4, 14
cimal-to-BCD conversion,{\fs16 16-} 17, 19
cimal-to-BCD encoder, 140-143
cimal-to-binary conversion, 3-6, 14
cimal-to-Gray code converter, 287-288, 306
cimal-to-hexadecimal conversion, 7-9, 14
cimal-to-2s complement conversion, 10- 11, 13,
i380 15
cimal-to-XS3 conversion, 20-21, 23, 27
coder, 16,26,69,102,140,143-153,164,287-288,
i367 316-319, 330, 344
dicated computer, 290
lay flip-flop{\i (see}{\fs17 D} flip-flop)
Morgan's theorems{\i (see} Laws{\fs16 of} Boolean
i364 algebra)
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-222 \f20 \fs17 \cf0 Di
gital clock, 232, 251-254
gital counter{\i (see} Counters)
gital-to-analog converter{\i (see} D/A converter)
gital voltmeter, 134, 138
ode ROM, 287-288, 290-292, 294-295. 306
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-215 \f20 \fs17 \cf0 DI
P{\i (see} Dual-in-line package)
splay multiplexing, 313-316
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-215 \f20 \fs17 \cf0 Do

uble inversion, 34-35, 59, 76-77
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-215 \f20 \fs17 \cf0 DR
AM{\i (see} Dynamic RAM)
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-216 \f20 \fs17 \cf0 DT
L (diode-transistor logic), 104
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-218 \f20 \fs17 \cf0 Du
al-in-line package, 40, 221, 223, 293
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-209 \f20 \fs17 \cf0 Du
ty cycle, 152
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-221 \f20 \fs17 \cf0 Dy
namic RAM, 284
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-215 \f20 \fs17 \cf0 Dy
namic-scattering LCD, 153
0 EBCDIC, 24-27
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-215 \f20 \fs17 \cf0 EC
L (emitter-coupled logic), 104
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-212 \f20 \fs17 \cf0 Ed
ge-triggering, 211-212, 214, 217, 219, 227-228,
i359 248, 262, 270, 273
\par}{\phpg\posx5643\pvpg\posy1377\absw4041\absh11316 \sl-212 \f20 \fs17 \cf0 EE
PROM (electrically-erasable PROM), 293, 295,
i359 307 \par
}
EX \par
}
f0 349 \par
}
PROM (erasable PROM), 293, 295, 298-299, 307
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-221 \f20 \fs17 \cf0 Enco
der, 16, 26, 140-143, 164
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-224 \f20 \fs17 \cf0 Exce
ss-3code{\f10 \fs14 (see} XS.3 code)
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-224 \f20 \fs17 \cf0 Excl
usive-NOR gate, 54-55, 65
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-221 \f20 \fs17 \cf0 Excl
usive-OR gate, 52-53, 64, 68, 190-191, 193,
70 196- 197, 202
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-221 \f20 \fs17 \cf0 Exte
nded Binary-Coded Decimal Interchange Code
58 {\f10 \fs14 (see} EBCDIC)
Fan-out, 107-108, 137
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-228 \f20 \fs17 \cf0 Feed
back, 265, 337-339
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-224 \f20 \fs17 \cf0 Fiel
d-effect LCD{\f10 \fs14 (see} Liquid-crystal display)
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-218 \f20 \fs17 \cf0 Fiel
d Programmable ROM{\f10 \fs14 (see} PROM)
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-228 \f20 \fs17 \cf0 Fila
ment (VF display), 159-164, 168

\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-225 \f20 \fs17 \cf0 Firm
ware, 290, 307
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-219 \f20 \fs17 \cf0 Flas
h PROM, 293-294, 308
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-226 \f20 \fs17 \cf0 Floa
ting inputs, 112-1 14, 117-118, 141, 145, 150,
60 242
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-219 \f20 \fs17 \cf0 Flop
py disk, 279, 300--308
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-224 \f20 \fs17 \cf0 Fluo
rescent display
32 {\f10 \fs14 (see} Vacuum fluorescent display)
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-225 \f20 \fs17 \cf0 FPLA
(field programmable logic array), 331, 333,
68 345
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-219 \f20 \fs17 \cf0 Free
-running multivibrator{\f10 \fs14 (see} Astable
68 mu1tivibrator)
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-227 \f20 \fs17 \cf0 Full
adder, 171-174, 180, 182-188, 193, 198-199
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-221 \f20 \fs17 \cf0 Full
subtractor, 176- 179, 181{\f10 \fs15 -}182, 199-201.
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-226 \f20 \fs17 \cf0 Fuse
map, 328-329, 334-335
\par}{\phpg\posx847\pvpg\posy1375\absw4073\absh5923 \sl-221 \f20 \fs17 \cf0 Fusi
ble links, 326-335 \par
}
allium arsenide (GaAs), 290, 307
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-221 \f20 \fs17 \cf0 Gate
inputs and outputs inverted, 55-58
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Gray
code, 20-24, 27, 287-288, 291
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-225 \f20 \fs17 \cf0 Gray
-code-to-binary conversion, 22, 24, 27
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-219 \f20 \fs17 \cf0 Gues
s-the-number game, 335-338, 345-346
Half adder, 170- 174, 180, 182- 183, 198-{\b 1} 99
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Half
subtractor, 175-179, 181, 200-201
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Hand
ling precautions (CMOS), 117-1 18
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-221 \f20 \fs17 \cf0 Hand
ling precautions (floppy disks), 302, 305
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Hard
disk, 279, 303-308
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-221 \f20 \fs17 \cf0 Heat
er{\f10 \fs14 (see} Filament)
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-226 \f20 \fs17 \cf0 Hexa
decimal numbers,{\fs16 1,} 6-10, 14
decimal-to-binary conversion, 8-10, 14
decimal-to-decimal conversion, 6-7, 9
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Holl

erith code, 25-26
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-219 \f20 \fs17 \cf0 HTL
(high-threshold logic), 105-106
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Hyst
eresis, 342, 346
IC{\f10 \fs14 (see} Integrated circuit)
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-220 \f20 \fs17 \cf0 IC m
arkings, 11{\fs16 1}{\f10 \fs15 -}114
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 IGFE
T, 104
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-221 \f20 \fs17 \cf0 IIL
(integrated-injection logic), 105
\par}{\phpg\posx859\pvpg\posy8335\absw3545\absh5063 \sl-224 \f20 \fs17 \cf0 Inte
grated circuit, 39 \par
}
Interfacing,:
i182 A/D conversion, 131-136
i187 D/A conversion, 131-136
i188 ICs with switches, 125-129
i188 ICs with output devices, 129-131
i188 Printers, 325
i186 TTL ancl CMOS ICs, 118-125
\par}{\phpg\posx5619\pvpg\posy1373\absw4108\absh11316 \sl-214 \f20 \fs17 \cf0 In
terrupt (microprocessor), 134, 136
vert bubble, 35, 48, 51
verter{\b \f10 \fs14 (see} NOT gate)
0 {\b\i \fs17 JK} flip-flop, 212-219, 228-232, 236-239, 264-268
0 Karnaugh mapping:
i188 effect{\fs16 of} don't cares on, 91-93, 101-102
i193 {\f10 \fs15 1}{\i \fs17 oo}p{\fs16 i}{\fs17 n}g variations{\f10 \fs17 ,} 82
{\dn006 \f10 \fs11 -}88
i193 using with maxterms, 88-91, 98, 100-101
i187 2-variable minterm, 82-83
i187 3-variable minterm, 83-85
i185 4-variable minterm, 85-88, 91-93, 97-98
i187 5-variable minterm, 93-96, 102-103
0 K-map{\f10 \fs14 (see} Karnaugh mapping)
0 Latch, 128, 204-205, 319-324
i20 Laws of Boolean algebra:
i188 AND function, 30
i196 DeMorgan's theorems, 75-77, 97-98
i196 NOT function, 35
i196 OR function, 33
i20 LCC (leadlcss chip carrier), 284
i24 LCD display decoders/drivers, 116
i20 Level triggering, 206, 209, 211
i23 Light-emitting diode (LED), 122-125, 138, 150, 166,
i376 313-315, 338, 344
i23 Liquid-cryslal display (LCD), 147, 152-158, 166-167
i23 Logical HIGH, 105-106, 108, 136, 341
i25 Logical LOW, 105-106, 108, 136, 341
i28 Logic symbols:
i200 AND gate, 28-31, 43-44
i208 NAND gate, 49-50, 63, 75
i208 NAND gate (alternate), 55-56, 75, 77-79
i208 NOR gate, 50-51, 63, 75, 79-82
i208 NOR gate (alternate), 55-56, 75
i208 NOT gate, 34-35
i204 NOT gate (alternative), 34-35
i207 {\fs17 OR} gate, 32-34, 43-44
i208 Schmitt trigger inverter, 342
i210 XNOR gate, 54-55, 65
i210 XOR gatc, 52-54, 64, 155-156, 167
i30 LSB (least significant bit), 1
i30 LSI (large scale integration), 104-105, 116
0 \fi37 Magnetic bulk storage, 279, 300-305
i36 Magneto-optical disk{\fs16 (see} Rewritable
i395 magneto-optical disk) \par
\f20 \fs17 \cf0 \f

\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\par\f20 \fs17 \cf
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
}
0 350 \par
}
EX \par
}
Magnitude comparator, 335-340, 345
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-224 \f20 \fs17 \cf0 Mas
k-programmable ROM, 287, 289-291, 293, 307
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-218 \f20 \fs17 \cf0 Mas
ter-slave{\i \fs17 JK} flip-flop, 214, 217-219, 229
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-223 \f20 \fs17 \cf0 Max
term Boolean expression, 72-75, 88-91, 96, 98,
376 100- 101
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-228 \f20 \fs17 \cf0 Mem
ory, 204, 230, 260, 279-308
ory cell, 205
ory size, 283-284, 286, 290-291, 306-307
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-224 \f20 \fs17 \cf0 Mic
rocontroller, 116
roprocessor, 116, 193, 320-321{\f10 \fs19 ,} 323
roprocessor-based system, 10, 136,222, 283, 290,
367 320-321, 344
roprocessor register, 10-12
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-221 \f20 \fs17 \cf0 Min
term Boolean expression, 69-71, 82-88,91-102,
367 311, 326-331
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-227 \f20 \fs17 \cf0 Mil
itary grade IC, 111, 113
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-219 \f20 \fs17 \cf0 Mod
em, 116, 325-326
e of operation/truth table:
192 Clocked{\b\i \f30 \fs19 RS} flip-flop, 207
178 {\fs17 D} flip-flop, 210
174 {\b\i \fs17 JK} flip-flop, 213-214
178 {\b\i \fs17 RS} flip-flop, 205
192 7475 4-bit latch IC, 320
188 7493 4-bit counter IC, 243
192 74125 three-state buffer, 322
192 74194 shift register, 269

191 74F189 RAM, 281
195 74HC85 magnitude comparator, 336
195 74HC154 demultiplexer, 317
199 74HC164 shift register, 272
195 74HC193 up/down counter, 247
ulus of counter, 230
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-228 \f20 \fs17 \cf0 Mon
ostable multivibrator, 204, 220-221, 223-226,
380 229
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-227 \f20 \fs17 \cf0 MOS
FET, 114, 117
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-218 \f20 \fs17 \cf0 MOS
{\b ICs: }
196 2114 Static RAM, 283-286
20 MOS technology, 104-105, 114
22 Motor (electric), 130-131
22 MSB (most significant bit), 1
20 MSI (medium-scale integration), 104- 105, 116- 117,
390 136
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-217 \f20 \fs17 \cf0 Mul
tiplexer, 309-313, 343-344
21 Multiplexing (display), 160, 168, 344
\par}{\phpg\posx871\pvpg\posy1375\absw4119\absh11109 \sl-215 \f20 \fs17 \cf0 MUX
{\b\i \fs16 (see} multiplexer)
\fi20 NAND gate, 48-50, 55-64, 66-68,77-79,
110,
382 205-207
20 NAND logic, 58-60,63, 66-67, 77-79
20 NAND-NAND gate pattern, 58-60, 66-67, 77-79,
380 99
20 Negate, 35-36
20 Nematic fluid{\fs17 (LCD),} 152, 154, 167
20 NMOS ICS, 105, 121, 284, 289-290
20 Noise immunity of IC, 106, 109, 114, 118, 342 \par
}
Nondestructive read, 280
nvolatile memory, 279-280, 287, 290, 296, 306
nvolatile RAM{\i \fs16 (see} NVRAM)
nweighted binary codes, 20-24
R gate, 50-52, 55-56, 68
R logic, 79-82
R-NOR gate pattern, 79-82, 99
T gate, 34-36,41-42,
55-58
VRAM{\i \fs16 (see} NVRAM)
RAM, 279, 296-300, 306, 308
SRAM{\i \fs16 (see} NVRAM)
0 Octal numbers, 1, 14
i24 1s complement, 189, 191-192
e-shot multivibrator{\i \fs16 (see} monostable
i374 mu1tivibrator)
amp{\i \fs16 (see} Operational amplifier)
i3376 {\f10 \fs11 - }
en-collector{\fs17 TTL} outputs, 111, 113, 121 122,
i382 124, 127-128
erational amplifier, 133, 135, 138
tical disk, 303-305
-AND gate pattern, 73-75, 79-82, 96-97, 99
gate, 31-34,41-46,
55-57, 324-325
cillator, 222-223
0 PAL{\i \fs16 (see} PLA)
i22 Parallel adder, 180-188, 193-198, 200-203
rallel data transmission, 324-326, 345
i21 Parallel subtractor, 180- 183, 188-198, 200-202
i23 Parity bit, 324
i21 PIA (peripheral interface adapter), 344
i21 PLA (programmable logic arrays), 69, 102, 326-335,
\f20 \fs17 \cf0 No

\f20 \fs17 \cf0 No
\f20 \fs17 \cf0 No
\f20 \fs17 \cf0 NO
\f20 \fs17 \cf0 NO
\f20 \fs17 \cf0 NO
\f20 \fs17 \cf0 NO
\f20 \fs17 \cf0 NO
\f20 \fs17 \cf0 NV
\f20 \fs17 \cf0 NV
\par\f20 \fs17 \cf
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 On
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 Op
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 Op
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 Op
\f20 \fs17 \cf0 Op
\f20 \fs17 \cf0 OR
\f20 \fs17 \cf0 OR
\f20 \fs17 \cf0 Os
\par\f20 \fs17 \cf
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 Pa
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f
\f20 \fs17 \cf0 \f

i381 345
i23 Plate{\b \fs17 (VF} display), 158-163, 168
i24 {\fs17 PLCC} (plastic leaded chip carrier), 290
i22 PLD{\i \fs16 (see} PLA)
i23 PMOS ICs, 105, 290
i22 Power consumption, 107-108, 113-114, 137
i24 Product-of-sums{\i \fs16 (see} Maxterm Boolean expression)
i24 PROM (programmable read-only memory), 69, 102,
i395 116, 293-300, 307, 326-334
i24 PROM burner, 293, 296, 307
i27 Propagation delay (speed of IC), 106, 108, 113,
i397 115-116, 118, 137, 237, 239, 318
i23 Pull-down resistor, 126-128
i23 Pull-up resistor, 111, 113, 120, 124, 138
i23 Pulse triggering, 213-215, 217-219, 264
0 \fi27 Radix, 1
i24 RAM (random-access memory), 116, 279-286, 306
i30 Read-only memory{\i \fs16 (see} ROM)
i28 Read/write memory,{\fs17 280,} 307
i27 Recirculate, 264, 268, 276
i29 Register{\i \fs16 (see} shift register) \par
}
EX \par
}
\par
}
Relay, 130-131, 138
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-227 \f20 \fs17 \cf0 Res
olution:
187 of A/D converter, 134, 136, 138
183 of D/A converter, 133
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-228 \f20 \fs17 \cf0 Rew
ritable magneto-optical disk, 304-305, 308

g counter, 266
(read-only memory), 69, 102, 279-280, 284,
367 286-293, 306
\i RS} flip-flop, 138, 204-206, 227
\i \f30 \fs19 RS} latch{\fs16 (see}{\b\i \f30 \fs19 RS}
(resistor-transistor logic), 104
Schottky diode, 110
atch-pad memory, 210
C, 325
tor, 301-302, 305
ectric code, 25
uential logic circuits, 204, 213, 230, 232, 255,
364 261, 331
ial adder, 180
ial data transmission, 324-326, 344
ial load{\fs17 (see} shift register)
en-segment displays:
184 fluorescent (VF), 147, 158-164, 168
184 gas-discharge, 147
184 incandescent, 147
188 light-emitting diode (LED), 147-152
184 liquid-crystal (LCD), 147, 152-158, 167
184 segment identification, 147-148, 156-157, 162
ft registers:
188 3-bit parallel-load shift-right, 267-268, 275-276
184 3-bit serial-load shift-right, 261-264, 275
183 4-bit serial-load shift-right, 261-264
183 5-bit serial-load shift-right, 275
187 8-bit serial-in parallel-out, 271-274
\f20 \fs17 \cf0 Rin

\f20 \fs17 \cf0 ROM
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 {\b
\f20 \fs17 \cf0 {\b
flip-flop)
\f20 \fs17 \cf0 RTL
\par\f20 \fs17 \cf0
\f20 \fs17 \cf0 Scr
\f20 \fs17 \cf0 SDL
\f20 \fs17 \cf0 Sec
\f20 \fs17 \cf0 Sel
\f20 \fs17 \cf0 Seq
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Ser
\f20 \fs17 \cf0 Ser
\f20 \fs17 \cf0 Ser
\f20 \fs17 \cf0 Sev
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Shi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
187 characteristics of, 260, 277

183 parallel-load recirculating shift-right, 264-266
187 types, 260
183 universal, 268
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-226 \f20 \fs17 \cf0 Sig
n bit, 10-13, 203
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-220 \f20 \fs17 \cf0 Sig
ned numbers (adding and subtracting), 193-198,
363 203
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-215 \f20 \fs17 \cf0 Sin
king current, 107, 109-110, 150
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-221 \f20 \fs17 \cf0 Sof
tware, 290
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-226 \f20 \fs17 \cf0 Spe
ed of IC{\b\i \fs17 (see} propagation delay)
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-220 \f20 \fs17 \cf0 Sol
enoid, 130- 13{\fs17 1 }
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-225 \f20 \fs17 \cf0 Sou
rcing current, 107, 109-110
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-215 \f20 \fs17 \cf0 SRA
M{\fs17 (see} static RAM)
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-223 \f20 \fs17 \cf0 SSI
(small-scale integration), 104-105, 116-117
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-228 \f20 \fs17 \cf0 Sta
tic RAM, 283, 286, 296-300, 306-307
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-218 \f20 \fs17 \cf0 Sub
traction using adders, 184-188
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-220 \f20 \fs17 \cf0 Suc
cessive-approximation A/D converter, 134, 139
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-223 \f20 \fs17 \cf0 Sum
-of-products{\b \f10 \fs14 (see} Minterm Boolean expression)
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-218 \f20 \fs17 \cf0 Sum
ming amplifier, 132-133, 135
\par}{\phpg\posx863\pvpg\posy1351\absw4067\absh11124 \sl-223 \f20 \fs17 \cf0 Swi
tch bounce, 126-127, 129, 138 \par
}
Switchingthreshold, 341-343, 346
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-218 \f20 \fs17 \cf0 Sy
nchronous, 206, 208, 210, 215, 227, 235-236, 255,
i367 275
0 Temperature control system, 338-340, 346
fs18 T} flip-flop{\fs17 (see} toggle flip-flop)
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-215 \f20 \fs17 \cf0 Th
ermionic emission, 159
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-223 \f20 \fs17 \cf0 Th
ree-state output, 111, 135-136, 284, 286, 290, 345
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-215 \f20 \fs17 \cf0 Ti
mer IC{\b \f10 \fs16 (5551,} 220-224, 314, 338-339
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-220 \f20 \fs17 \cf0 Ti
ming diagrams{\fs17 (see} Waveform diagrams)
\par}{\phpg\posx5637\pvpg\posy1355\absw4083\absh11114 \sl-215 \f20 \fs17 \cf0 To
ggle, 213, 215, 230, 235, 245-246, 248

ggle flip-flop, 213, 228
ne generator, 116
tem-pole output, 110-111, 113
ack, 301-302, 305
iode vacuum tube, 158-159
uth tables:
i180 AND function, 28-31
i188 Comparator IC{\b \f10 \fs14 (see} Mode of operation/truth
i541 table)
i188 Counter ICs{\b\i \fs16 (see} Mode of operation/truth table)
i188 Flip-flop{\b ICs}{\b\i \fs17 (see} Mode of operation/truth table)
i182 NAND function, 48-49, 63
i188 NOR function, 50-52, 63
i181 NOT function, 35
i187 OR function, 31-33, 41-43
i188 {\fs17 RAM} IC{\fs16 (see} Mode of operation/truth table)
i180 XNOR function, 45-55, 65
i182 XOR function, 52-54, 64
L (transistor-transistor logic), 40-41, 43
L integrated circuits:
i181 5400 series, 111, 113
i181 7400 NAND gate IC, 60-62, 67, 137
i181 7403 NAND gate IC, 126, 128-129, 138
i181 7404 Inverter IC, 41, 112, 314, 316, 341-342
i187 7406/7416 Inverted buffer IC, 120-122
i187 7407/7417{\fs17 0.} C. buffer IC, 120-122
i182 7408 AND gate IC, 40-41, 111-112
i188 7410 NAND gate IC, 60-61, 67
i182 7414 Schmitt trigger inverter IC, 341-343
i188 7432 OR gate IC, 41-43
To
To
To
Tr
Tr
Tr
\f
\f
\f
\f
\f
\f
\f
\f
\f
\f
\f
\f
TT
TT
\f
\f
\f
\f
\f
\f
\f
\f
\f
\f

i188 7442 Decoder IC, 143-146, 287-288, 290
i188 7443 Decoder IC, 165-166
i188 7447A Decoder/driver
IC, 148-152, 314
i182 7474{\b\i \f30 \fs19 D} flip-flop IC, 210-212, 214
i188 7475 4-bit latch IC, 214, 319-320, 322-323, 344
i187 7476 JK flip-flop IC, 213-214, 216-220
i188 7483 4-bit adder IC, 181-182, 184, 192, 196, 201
i188 74934-bit counter IC, 242-245,251-254,257-258
i188 74121 One-shot multivibrator IC, 225-226
i188 74125 Three-state buffer IC, 320-324, 344
i188 74147 Encoder IC, 141-143
i188 74148 Encoder IC, 164-165
i188 74150{\b \fs17 Data-selector/multiplexer} IC, 309-313,343 \par
}
0 352 \par
}
EX \par
}
TL{\fs17 integrated}{\fs17 circuits:}{\fs17 (continued) }
93 {\fs17 74157}{\fs17 Multiplexer}{\fs17 IC,}{\fs17 314-316 }
93 {\fs17 74164/74165}{\fs17 8-bit}{\fs17 shift}{\fs17 register}{\fs17 ICs
,}{\fs17 270 }
89 {\fs17 74192}{\fs17 Up/down}{\fs17
counter}{\fs17 IC,}{\fs17 241-244,}
{\fs17
257,}{\fs17 314 }
89 {\fs17 74194}{\fs17 Universal}{\fs17 shift}{\fs17 register}{\fs17 IC,}{
\fs17 268-271, }
99 {\fs17 276-277 }
93 {\fs17 74ALS76}{\fs17 JK}{\fs17 flip-flop}{\fs17 IC,}{\fs17 113-114 }
89 {\fs17 74F189}{\fs17 RAM}{\fs17 IC,}{\fs17 281-286,}{\fs17
307 }
93 {\fs17 74LS154}{\fs17 Demultiplexer}{\fs17 IC,}{\fs17 316-319,}{\fs17
344 }
89 {\fs17 74LS395}{\fs17 4-bit}{\fs17 shift}{\fs17 register}{\fs17 IC,}{\fs
17 270 }
\par}{\phpg\posx863\pvpg\posy1342\absw3926\absh5755 \sl-225 \f20 \fs18 \cf0 TTL{
\fs17 subfamilies: }
87 {\fs17 Advanced}{\fs17 low-power}{\fs17 Schottky,}{\fs17 110-112 }
87 {\fs17 Advanced}{\fs17 Schottky,}{\fs17 106,}{\fs17 110-112 }
87 {\fs17 FAST,}{\fs17 281 }
87 {\fs17 Low-power,}{\fs17 109-113 }
87 {\fs17 Low-power}{\fs17 Schottky,}{\fs17 107,}{\fs17 109,}{\fs17 113,}{\f
s17 123,}{\fs17 318 }
89 {\fs17 Schottky,}{\fs17 109-112 }
90 {\fs17 Standard}{\fs17 TTL,}{\fs17 107,}{\fs17 109-113 }
18 TTL}{\fs17 voltage}{\fs17 levels,}{\fs17 105-106,}{\fs17
108,}{\fs17
136 }
17 2s}{\fs17 complement}{\fs17 addition,}{\fs17 193-197,}{\fs17
203 }
17 2s}{\fs17 complement}{\fs17 numbers,}{\fs17 10-13,}{\fs17
15,}{\fs17
188-198,}{\fs17 203 }
17 2s}{\fs17 complement-to-decimal}{\fs17 conversion,}{\fs17 11-13,}{\fs17
15 }
17 2s}{\fs17 complement}{\fs17 subtraction,}{\fs17 193-198,}{\fs17
203 }
{\fs17 UART,}{\fs17 116,325-326,}{\fs17
344 }
17 ULSI}{\fs17 (ultra-large-scale}{\fs17 integration),}{\fs17 104 }
17 Unipolar}{\fs17 technology,}{\fs17 104 }
17 Universal}{\fs17 gate,}{\fs17 49,}{\fs17 58-60,}{\fs17
77-82 }\par
}
USART, 325-326
\par}{\phpg\posx5651\pvpg\posy1357\absw4041\absh5751 \sl-219 \f20 \fs17 \cf0 UV
erasable PROM{\b \f10 \fs15 (see} EPROM)
Vacuum fluorescent display, 147, 158-164, 168-169
\par}{\phpg\posx5651\pvpg\posy1357\absw4041\absh5751 \sl-224 \f20 \fs17 \cf0 VLS
I (very-large-scaleintegration), 104- 105, 116
\par}{\phpg\posx5651\pvpg\posy1357\absw4041\absh5751 \sl-207 \f20 \fs17 \cf0 Vol
atile memory, 279-280, 284, 296, 306
Waveform diagrams:
187 defining terms, 217
190 for clocked{\b\i \fs17 RS} flip-flop, 207
188 for decade counter, 242

190 for 4-bit parallel-load recirculating register, 265
188 for 4-bit serial-load shift-right register, 261
182 for 4-bit up/down counter, 247
188 for master-slave{\fs18 JK} flip-flop, 218
187 for{\fs17 mod-6} ripple counter, 237
188 for mod-8 down counter, 238
182 for mod-8 parallel counter, 235
182 for mod-16 ripple counter, 231
182 for negative-edge-triggered flip-flop, 217
182 for positive-edge-triggered flip-flop,{\fs17 21}7
ghted binary codes, 16-20
chester (hard disk), 303, 307
d (binary), 280, 283, 324
XNOR{\b \f10 \fs15 (see} Exclusive-NOR gate)
{\b \f10 \fs15 (see} Exclusive-OR gate)
code, 20-21, 23, 26
-to-decimal conversion, 21, 23, 27 \par
}
}
\f20 \fs17 \cf0 \fi

\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 \fi
\f20 \fs17 \cf0 Wei
\f20 \fs17 \cf0 Win
\f20 \fs17 \cf0 Wor
\par\f20 \fs17 \cf0
\f20 \fs17 \cf0 XOR
\f20 \fs17 \cf0 XS3
\f20 \fs17 \cf0 XS3

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