Chapter 4 - Analog Integrated Circuit Design by John Choma

LECTURE SUPPLEMENT #4 . . .
[LS #4]
CHAPTER #04

Circuit Level Models And Basic
Applications Of MOS Technology
Transistors

Dr. John Choma
Professor of Electrical Engineering
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 900890271
2137404692 [USC Office]
2137407581 [USC Fax]
8183841552 [Cell]
johnc@usc.edu

PRELUDE:
In this chapter, you are introduced to MOS technology transistors and in particular, to the circuit
level models that emulate the electrical behavior of the metal-oxide-silicon field effect transistor,
or MOSFET. We present these models in a hierarchical format that proceeds from relatively sim-
ple mathematical forms to progressively more advanced embodiments that reflect trends in state
of the art circuit and system industries. These advanced structures enable an understanding of
how higher order transistor phenomena, inclusive of those that prevail in modern, deep submi-
cron technologies, affect the observable responses of high performance analog networks. Subse-
quent to demonstrating the utility of the simple models in several practical circuit applications,
we shall learn how computer-aided design and the more advanced MOSFET models coalesce to
optimize our first order designs and render them reproducible in the face of a myriad of
processing and manufacturing uncertainties. The chapter concludes with the development of
small signal MOSFET models, which are foundational to the analysis and design of linear, ana-
log MOS technology circuits.
July 2013
Chapter 4 MOSFET Models and Applications

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4.1.0. INTRODUCTION
Integrated electronic circuits realized in metal-oxide-silicon field effect transistor
(MOSFET) technologies are used widely in the technical community. Transistors manufactured
in bipolar technologies, which we studied in the preceding chapter, compete successfully with
their MOSFET counterparts from such performance perspectives as fast switching speed, broad-
band frequency response, and low noise signal processing. Nevertheless, the MOSFET domi-
nates much of the electronic network landscape for at least three reasons. The first of these rea-
sons derives from the fact that the cross section geometry of a MOSFET, when compared to that
of a bipolar junction transistor, and particularly a SiGe BJT, is considerably simpler. This
simplicity affords relative foundry processing ease, which promotes high device yield and there-
fore cost-effective manufacturing. We might interject here that yield is a commonly invoked
integrated circuit processing metric that asserts the percentage of manufactured chip devices that
meet or exceed minimal operating requirements. A second reason underlying MOS technology
popularity is that the surface area consumed on chip, or the footprint, of a MOSFET is invariably
smaller than that of a comparably performing bipolar transistor. This feature allows increased
packing density (number of transistors per unit chip surface area), which is particularly advanta-
geous for digital signal processors that can exploit upwards of millions of transistors for proper
functionality. Finally, MOSFETs deliver good circuit performance at low standby power and
voltages, which is a welcomed attribute in light of the aforementioned high device density of
digital architectures and the portability culture in which we are immersed.
Although bipolar transistors are capable of delivering outstanding (and some would ar-
gue even superior) analog circuit performance, especially at high signal frequencies, adopting
MOSFET technology as a viable alternative for analog signal processing applications makes
sense for several reasons. One reason is that the nature of modern integrated systems is rarely
exclusively digital or exclusively analog. State of the art systems are mixed signal architectures
that combine digital and analog signal processing on the same chip. Because of the simplicity,
packing density, and power dissipation attributes of MOSFETs, the majority of digital architec-
tures, excluding perhaps those in specialized, high performance military systems, is realized in
MOS technology. Engineering prudence therefore encourages a MOSFET technology realiza-
tion of the analog cells implicit to a mixed signal framework if only to facilitate the electrical
interface between the digital and analog circuit cells.
Aside from the operating flexibility and programmability attributes of digital circuit
schema, digital circuits in microcontrollers that are embedded in mixed signal topologies are of-
ten required to ensure and sustain optimal performance in the analog signal flow paths of modern
electronic systems. Unlike most digital networks, high performance analog circuits are sensi-
tized to specific values, or at least specific ranges of values, of several of the key physical and
electrical parameters that define the static and dynamic volt-ampere characteristics of MOSFETs.
Unfortunately, attaining the requisite accuracy in the observed values of these implicit parame-
ters is progressively more challenging as we scale, or downsize, device geometries to meet the
omnipresent demands for the wider system bandwidths that are required to process ever-increas-
ing amounts of information and data. In these high performance systems, suitable compensation
of the analog signal flow paths often derive from digital subcircuits deployed to sense observable
performance metrics and compare these metrics to their respective targeted design goals. What
gets measured is a viable candidate for possible corrective action. To this end, the digital control
units are called upon to reduce the differences between sensed and targeted performance metrics
by adjusting relevant circuit branch parameters and/or the biasing conditions of transistors that

- 314 -
are implicit to the signal path. In effect, the combined digital controllers and analog network be-
have as a seamless adaptive system that automatically corrects for manufacturing uncertainties,
nonzero component tolerances, increased device operating temperatures, and an array of other
environmental phenomena.
4.2.0. MOSFET DEVICE CROSS SECTION
We have seen that two types of bipolar junction transistors are available. Similarly,
MOSFETs come in two flavors: the n-channel MOSFET, or NMOS transistor, whose simplified
cross section is diagrammed in Figure (4.1), and the p-channel MOSFET, or PMOS device, we
depict in Figure (4.2). In the NMOS device, the bulk substrate is p-type, lightly doped to an
average acceptor impurity concentration of N
A
. A representative range of substrate impurity
concentration values is 5(10
14
) atoms/cm
3
< N
A
< 10
16
atoms/cm
3
. The vertical depth of the bulk
substrate, which is not symbolically highlighted in Figure (4.1), is many times larger than the
depth, Y
d
, of the source and drain diffusions or implants. The latter depth is typically of the order
of a few tenths of microns. The source and drain regions, whose widths are indicated as L
diff
and
which are connected electrically to the externally accessible source (S) and drain (D) terminals of
the MOSFET, are very strongly doped. Their donor impurity concentrations border on solid
solubility limits in that N
D
= 10
20
atoms/cm
3
or slightly larger. The width, L
diff
, is typically two-
or three-times the channel length, which we indicate as L in the diagram. In effect, the high
impurity concentration in the source region forges a robust electrical contact between the source
terminal and the source end of the bulk geometry lying directly under the indicated silicon dio-
xide layer. The same statement applies to the drain terminal and its electrical interface with the
drain end of the bulk region. The metallization contact that forms the electrical terminal of the
semiconductor bulk (B) is normally connected to the most negative potential available in the cir-
cuit into which the subject transistor is embedded. Such a connection reverse biases the PN
junctions formed between the bulk and source regions and between the bulk and drain regions.
This reverse biasing ensures that for at least low signal frequencies, the source and drain volumes
are electrically isolated from each other and from the bulk substrate. This reverse biasing serves
also to isolate electrically proximately located other chip transistors.
Lying atop the p-type bulk substrate is an insulating silicon dioxide layer of thickness
T
ox
that extends into the page by an amount equal to the gate width, W. The oxide thickness is of
the order of the low tens of angstroms, where we remind that one angstrom is 10
8
centimeter.
The oxide layer covers the channel region of length L, which separates the source region from
the drain region. Unfortunately, this oxide layer may overlap the source and drain regions by the
amount, L
d
, as we indicate in the diagram. The overlap of the source and drain regions is bad
news in that it can limit the frequency response capabilities in certain types of MOSFET amplifi-
ers. In processes boasting gate self-alignment, L
d
is ideally reduced to zero. But for state of the
art monolithic circuit processes delivering channel lengths as small as 28 nM to 130 nM, gate
self-alignment focused on reducing L
d
to no more than 5% of L is a challenge.
The gate width, W, can be no smaller than the minimum channel length that can be pro-
duced by the foundry process. Subject to this constraint, the gate aspect ratio, W/L, is a designa-
ble parameter. A designable parameter is one that we can select in accordance with our
interpretation of the operating requirements of the circuit application in which we deploy the
considered MOSFET. Depending on circuit application and associated design strategies and tar-
gets, the gate aspect ratio can be as large as several tens or even several hundreds.

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Figure (4.1). A simplified three-dimensional depiction of an n-channel MOSFET (NMOS) and its
corresponding electrical schematic symbol. The diagram is not drawn to scale.

Figure (4.2). A simplified three-dimensional depiction of a p-channel MOSFET (PMOS) and its correspond-
ing electrical schematic symbol. The diagram is not drawn to scale.
N
+
S
o
u
r
c
e
N
+
D
r
a
i
n
P Type
Substrate
[Concentration = N cm ]
A
-3
S G D
B
Silicon Dioxide
T
ox
Y
d
L
diff
L
d
L
d
W
L
G
a
t
e
S
o
u
r
c
e
D
r
a
i
n
Bulk or
Substrate
Metal or
Polysilicon
L
diff
S
G B
I
d
I
b
I
s
I
g
V
ds
V
bs
V
gs
S
V
gd
D D
P
+
S
o
u
r
c
e
P
+
D
r
a
i
n
N Type
Substrate
[Concentration = N cm ]
D
-3
S G D
B
Silicon Dioxide
T
ox
Y
d
L
d
L
d
W
L
G
a
t
e
S
o
u
r
c
e
D
r
a
i
n
Bulk or
Substrate
Metal or
Polysilicon
D
G
S
B
I
s
I
b
I
d
I
g
+
V
sd
+
V
sb
V
dg
S
V
sg
D
L
diff
L
diff

- 316 -
The gate terminal (G) is formed of an electrical contact made of a metallic or a
polycrystalline silicon layer deposited directly on the gate oxide. A popular gate metal is alumi-
num. If the MOSFET under consideration is used in high temperature environments and/or in
applications that exploit low power supply voltages, polycrystalline silicon, which is commonly
referred to as polysilicon or simply poly, supplants the aluminum gate. We observe that the
insulating gate oxide layer comprises a dielectric interface between the gate metal and the
semiconductor bulk. Since the gate metal is obviously conductive and the bulk region is at least
semi-conductive, an effective parallel plate capacitance is forged between the gate contact (G)
and the bulk terminal (B). The capacitance value of this MOS capacitance, or MOSCAP, can be
controlled by static voltages applied between gate and bulk terminals. The capacitance attributed
to the source and drain overlap regions is less sensitive to changes in voltages applied from gate
to source or from gate to drain.
In addition to the simplified cross section diagram of the n-channel MOSFET, Figure
(4.1) inserts the electrical schematic symbol of an NMOS transistor. Of particular interest are
the positive reference conventions adopted for four device currents and four device voltages.
Specifically, positive drain current, I
d
, flows into the transistor, as do the gate current, I
g
, and the
bulk, or substrate, current, I
b
. On the other hand, positive source current, I
s
, flows out of the
transistor. The entire transistor structure can be accorded the stature of a giant, happy circuit
node, whence by Kirchhoffs current law,
s d g b
I I I I . = + + (4-1)
However, since the gate contact is isolated from the semiconductor bulk by an insulating oxide
layer, I
g
is zero in the steady state and at the low frequencies for which the capacitance asso-
ciated with the insulating gate dielectric behaves as an open circuit. Moreover, the bulk current,
I
b
, is likewise almost zero at low signal frequencies, provided, as is usually the case, that the bulk
terminal is connected to the most negative of available circuit potentials. This bulk biasing
serves to reverse bias the PN junctions formed between bulk and drain and between bulk and
source, thereby remanding I
b
to a superposition of invariably small PN junction leakage currents.
Accordingly, the source and drain currents, I
s
and I
d
, respectively, are almost identical when only
relatively low frequency signals are applied to a MOSFET. This observation contrasts with our
bipolar disclosures in the preceding chapter in that the bipolar device emitter current is slightly
larger than the corresponding collector current by an amount that equals the relatively small base
current. We shall demonstrate in the following pages that the static and low frequency values of
the drain, and hence the source, current are controlled dominantly by the gate to source voltage,
V
gs
, modestly by the drain to source voltage, V
ds
, and, to a far lesser extent, by the bulk to source
voltage, V
bs
. Stipulating an additional dependence of drain current on gate to drain voltage V
gd
is
superfluous, for by Kirchhoffs voltage law,
ds gs gd
V V V . = (4-2)
The p-channel MOSFET abstracted in Figure (4.2) is architecturally similar to its
NMOS counterpart. The notable differences are that the bulk substrate in PMOS is n-type and
the source and drain regions are heavily doped with p-type impurities. It follows that electrical
isolation between the source region and the bulk, as well as between the drain region and the
bulk, requires that the bulk substrate terminal of a PMOS device be connected to the most posi-
tive of available circuit potentials. All of the geometrical parameters and their representative
values remain the same as stipulated for NMOS units. The PMOS electrical schematic symbol,
which is also shown in Figure (4.2), differs from the NMOS symbol in that the directions of the
source terminal and bulk terminal arrows are reversed, as are the positive reference directions of

- 317 -
all four transistor currents. While (4-1) remains applicable, the analytical expression for the
drain current, I
d
, which now flows out of the transistor, is more conveniently couched in terms of
the source to gate voltage, V
sg
, the source to drain voltage, V
sd
, and the source to bulk voltage,
V
sb
. The drain -to- gate voltage, V
dg
, derives from
sd sg dg
V V V , = (4-3)
which mirrors (4-2) if we simply multiply both sides of the last equation by negative one.
4.3.0. STATIC MOSFET MODELS
The static volt-ampere characteristics of an n-channel MOSFET relate the drain current,
I
d
, flowing into the transistor to its applied gate-source voltage, V
gs
, drain-source voltage V
ds
, and
bulk-source voltage V
bs
. The characteristics for a p-channel device are analogously defined. But
in a p-channel transistor, the drain current, I
d
, flows out of the device and is expressed as a func-
tion of the source-gate voltage, V
sg
, source-drain voltage V
sd
, and source-bulk voltage V
sb
. In
contrast to the Ebers-Moll and Gummel-Poon bipolar junction transistor models, which define
the transistor volt-ampere characteristics for all possible operating voltage scenarios, the static
volt-ampere curves of MOSFETs are more expediently determined by partitioning the
characteristics into four distinct operating regimes. These regimes are the cutoff region, the
subthreshold region, the ohmic (also known as the triode) regime, and the saturation regime. Al-
though we shall opt for the mathematical and design-oriented convenience of an approximate
four region MOSFET model, we point out that other MOSFET device models, such as the EKV
model, promote a unified approach to physically-based MOSFET modeling that is valid for all
operating regions
[1],[2]
. The EKV model is incorporated in several currently available versions of
the SPICE computer-aided design software. However, we deem the definitive physical model-
ing, which is excellently reflected by the EKV model, to be outside the scope of this circuits-
oriented textbook.
4.3.1. TRANSISTOR IN CUTOFF REGIME
A MOSFET operates in cutoff when its drain current is zero. In an n-channel device,
the condition corresponding to null drain current is a small gate-source voltage, V
gs
, which satis-
fies the inequality,
gs hf
V V , s (4-4)
where V
hf
, adjusted for applied bulk-source voltage V
bs
, is
bs
hf F F
F
V
V V 2V V 1 .
V
u
= + (4-5)
In this relationship, the Fermi potential, V
F
, is given by
sub A
F T T
i i
N N
V V V ,
n n
ln ln
| | | |
= =
| |
\ . \ .
(4-6)
where the bulk substrate concentration, N
sub
, is an acceptor impurity concentration (N
A
) in the
NMOS device. Moreover,
T
V kT q = (4-7)
is the familiar Boltzmann voltage for which k = (1.38)(10
23
) joules/K is Boltzmanns constant,
q = (1.60)(10
19
) coulombs is the magnitude of electron charge, and T represents the absolute

- 318 -
temperature of the surface of the bulk substrate. Parameter n
i
symbolizes the intrinsic
semiconductor concentration of silicon (roughly 10
10
atoms/cm
3
at T = 27 C = 300.16 K). For
most NMOS transistors, V
F
is in the neighborhood of 300 mV at surface temperatures of 27 C.
Also in (4-5), V
, termed the body effect voltage, is

1

2
A s ox
A s
2
ox
ox
qN T
V qN .
C
| |
= =
|
\ .
(4-8)
In this equation,
s
is the dielectric constant of silicon, which is 1.05 pF/cm, and C
ox
is the density
(in units of farads/cm
2
) of the capacitance associated with the gate oxide layer. In particular,
ox
ox
ox
C ,
T
= (4-9)
where
ox
is the dielectric constant of silicon dioxide (345 fF/cm). Recall T
ox
to be the thickness
of the gate oxide layer. We should note that the multiplication of capacitance density C
ox
by the
product of the channel length, L, and gate width W yields the net oxide capacitance observed at
the transistor gate under equilibrium conditions. The body effect voltage, V
, is typically of the
order of only the high hundredths to low tenths of volts. Indeed, we see that for thin gate oxides,
V
in (4-8) converges toward zero.

Two issues surrounding (4-4) and (4-5) are sufficiently compelling to warrant at least
qualitative engineering attention. The first of these issues is that voltage V
hf
is a particular gate-
source voltage that corresponds to one Fermi level, V
F
, established at the interface of the gate
oxide and bulk semiconductor. In other words, (4-4) asserts that MOSFET cutoff is achieved
when the applied gate-source voltage is sufficient to establish a potential of only one Fermi level
at the semiconductor interface immediately under the gate oxide layer. The first term on the
right hand side of (4-5) obviously speaks to this Fermi interfacial potential. The second term on
the right hand side of the subject relationship corrects for applied bulk-source voltage, V
bs
. In
particular, note that negative V
bs
, which is typical of most NMOS topologies, increases V
hf
. This
situation reflects engineering expectations in that V
bs
< 0 pulls the surface potential lower than
the value evidenced for V
bs
= 0. As a result, the gate-source voltage must be increased to offset
the aforementioned pull down of surface potential. In a word, V
gs
must be progressively in-
creased to bring a transistor influenced by negative bulk-source voltage out of cutoff.
The second of the aforementioned two issues is directed toward assuring our
comprehension of the engineering significance of the Fermi potential. To this end, we submit
the simplified MOSFET cross section of Figure (4.3), which depicts an NMOS device to which
is applied a positive gate-source voltage, V
gs
, zero drain-source voltage, V
ds
, and a bulk-source
voltage, V
bs
, which is polarized to ensure either reverse or zero biasing of both the bulk-source
and the bulk-drain PN junctions. When we apply a gate-source voltage, V
gs
, we expect a signifi-
cant percentage of V
gs
to be dropped across the insulating silicon dioxide layer. In Figure (4.3),
we denote this oxide potential drop as voltage V
ox
. The corresponding voltage excess, (V
gs

V
ox
), appears as the interfacial potential, which we highlight as voltage V
y
in Figure (4.3). Ob-
serve that voltage V
y
is dropped from the interface of the oxide-semiconductor bulk to the source
so that in concert with Kirchhoffs voltage law,
gs ox y
V V V . = + (4-10)
In the absence of any significant drain-source bias, the interfacial potential is given by

1
In HSPICE and numerous other forms of SPICE circuit simulators, the body effect parameter is , where
2
= 2V
u
.

- 319 -

Figure (4.3). Simplified NMOS cross section used to illustrate the engineering significance of the
Fermi potential. The diagram is not drawn to scale.
y T
o
n
V V ,
n
ln
| |
=
|
\ .
(4-11)
where parameters n and n
o
respectively denote the actual and equilibrium values of the free elec-
tron concentration at the interface point where voltage V
y
is monitored. Assuming nearly com-
plete ionization of substrate impurity atoms, the free hole concentration in an NMOS substrate
very closely equals N
A
. Additionally, the product of free hole and electron concentrations is the
square of the intrinsic carrier concentration. Thus, we can express (4-11) in as the more
enlightening alternative,
A
y T T
2
o
i
n nN
V V V .
n
n
ln ln
| |
| |
| = =
|
|
\ .
\ .
(4-12)
Equation (4-12) harbors interest because it demonstrates that an increase in voltage V
y
,
which derives from an increase in applied gate-source voltage, as per (4-10), necessarily incurs
an increase in the interfacial density, n, of free electrons. Equation (4-12) supports this conten-
tion because we know that for a given operating temperature, the intrinsic carrier concentration,
n
i
, is a constant, and the average impurity concentration, N
A
, in the semiconductor bulk is like-
wise fixed. Evidently, the immediate effect of applying positive gate-source voltage V
gs
is to at-
tract free electrons, which are the minority carriers in the p-type semiconductor bulk of NMOS,
to the oxide-bulk interface. As V
y
continues to rise, n eventually climbs to the intrinsic carrier
level, n
i
. Interfacial potential V
y
in (4-12) equates to Fermi potential V
F
in (4-11) when the elec-
tron concentration, n, at the surface equals the intrinsic carrier concentration n
i
. In other words,
when the interface potential equals one Fermi level, the semiconductor complexion of the
interfacial region changes from an obvious p-type semiconductor to an intrinsic, neutral
semiconductor; that is, it is neither p-type nor n-type. We can therefore say that when V
y
= V
F
,
the interfacial region is on the cusp of inverting from p-type to n-type semiconductor.
N
+
S
o
u
r
c
e
N
+
D
r
a
i
n
P-Type Substrate (conc. = N cm )
A
-3
S G D
B
Silicon Dioxide

V
gs
V = 0
ds
Depletion
Layer, V = 0
ds
I
d
Channel Of
Free Electrons
V 0
bs
s
V
ox
V
y
+
+

- 320 -
While we associate zero drain current corresponding to the condition posed by (4-4), in
truth, a very small amount of drain current flows when positive drain-source voltage is applied.
This drain current materializes because as V
y
nears the Fermi potential, a small concentration of
electrons, nominally equivalent to the intrinsic carrier concentration, is established at the inter-
face. Because this electron concentration is very small (about 10
10
electrons/cm
3
), the resultant
drain current is typically of the order of at most femtoamperes.
The cutoff criterion for a PMOS device mirrors that of an NMOS transistor. Specifi-
cally, (4-4) and (4-10) become, with the understanding that V
hf
remains a positive voltage,
sg hf
sg ox y
V V
.
V V V
<
= +
(4-13)
It is important to interject that the annotated polarities of voltages V
ox
and V
y
are reversed from
those that are indicated in Figure (4.3). The Fermi potential, which, like V
hf
, remains a positive
number, is now
sub D
F T T
i i
N N
V V V ,
n n
ln ln
| | | |
= =
| |
\ . \ .
(4-14)
where for PMOS, N
sub
= N
D
, the donor impurity concentration of the n-type bulk. In view of (4-
14), the interface potential, V
y
, in (4-12) becomes for PMOS,
D
y T T
2
o
i
p pN
V V V ,
p
n
ln ln
| |
| |
| = =
|
|
\ .
\ .
(4-15)
where we understand that p is the free hole concentration at the interface, and p
o
is the equili-
brium value of this free charge concentration.
4.3.2. TRANSISTOR IN THE SUBTHRESHOLD REGIME
If the gate-source voltage, V
gs
, in an NMOS transistor continues to rise, thereby enabl-
ing the interfacial potential to rise above the Fermi level, V
F
, the free electron concentration at
the oxide-bulk interface surpasses its intrinsic level. This means that the interfacial region we
addressed in the preceding subsection inverts from its original p-type nature to an n-type charac-
ter. In other words, for V
gs
> V
hf
, the concentration of interfacial free electrons exceeds, albeit by
a comparatively small factor, the interfacial concentration of free holes. For
hf gs h
V V V , < < (4-16)
where V
h
is formally introduced here as the threshold, or turn on, voltage of the transistor, we say
that the channel region between the source and drain implants in the cross section diagram of
Figure (4.3) is weakly inverted. It is weakly inverted in that the channel between source and
drain volumes and immediately beneath the gate oxide has an electron concentration that is
larger than intrinsic level, but is nevertheless substantively smaller than the hole concentration,
N
A
, which originally prevailed in this region. This weak inversion condition, which is guaran-
teed by the satisfaction of (4-16), constrains the considered transistor to operate in its subthre-
shold regime.
The engineering significance of the threshold voltage, V
h
, we have introduced in (4-16)
is best appreciated in the context of a MOSFET operating in either its ohmic or saturation do-
mains. For the present, however, it can be stated that this threshold voltage is the minimum gate-
source voltage commensurate with the onset of the conduction of significant drain current when
positive drain-source voltage, V
ds
, is applied to the transistor.

- 321 -
Two important points surround the threshold voltage of a MOSFET. The first of these
points is that V
h
is the specific value of gate-source voltage that establishes an interfacial poten-
tial, V
y
, which is equivalent to twice Fermi level. From (4-12) and (4-11), we see that V
y
= 2V
F
if
the concentration, n, of free electrons at the interface equals N
A
, the impurity concentration in the
bulk. In other words, threshold conditions are manifested when the oxide-bulk interface be-
comes strongly inverted. By strongly inverted, we mean that the interfacial concentration of
free electrons rises to the original interfacial free hole concentration (assuming complete impur-
ity ionization in the bulk substrate) evidenced at equilibrium.
The second of the aforementioned two threshold disclosures is that the turn on voltage
is influenced by nonzero bulk-source voltage, V
bs
, in accordance with a phenomenon known as
body effect, bulk effect, or bulk-induced threshold modulation (BITM). In particular, negative
V
bs
results in an increase in the threshold voltage, which is to say that when V
bs
pulls the bulk be-
low ground, an enhanced gate-source voltage is required to counteract this bulk voltage effect if
transistor turn on is to be sustained. The body effect expression commonly used to quantify the
relationship of threshold voltage V
h
to bulk-source voltage V
bs
is
[3]

bs
h ho F
F
V
V V 2 V V 1 1 .
2V
| |
= +
|
|
\ .
(4-17)
In this expression, V
ho
is the value of threshold voltage V
h
for the special case of zero bulk-source
voltage; that is, V
h
= V
ho
for the zero bias case inferred by V
bs
= 0. Voltage V
ho
is given by
( )
ho F F
V 2 V 2 V V .
u
= + (4-18)
Accordingly,
bs
h F F
F
V
V 2V 2 V V 1 .
2V
u
| |
| = +
|
\ .
(4-19)
We should interject that for NMOS, voltages V
F
and V
remain given by (4-6) and (4-8), respec-

tively. Because voltage V
is small, (4-19) demonstrates that for zero bulk-source bias, the thre-
shold voltage approximates twice the Fermi potential for V
bs
<< 2V
F
.
In Figure (4.4), we graphically display the nature of BITM for three different values of
gate oxide thickness. The subject plot invokes N
A
= 10
15
atoms/cm
3
and room temperature
conditions for which the intrinsic carrier concentration, n
i
, is about 10
10
atoms/cm
3
. Note that the
body effect induces a progressively smaller perturbation in the threshold voltage as the oxide
thickness diminishes. In general, however the threshold shift can be significant. For example, if
the gate oxide thickness is 100 , (V
h
V
ho
) = 52.5 mV for V
bs
= 2.5 V. Given that the zero
bias (V
bs
= 0) threshold voltage, V
ho,
is of the order of 500 mV for a device extolling a minimum
channel length of the order of 500 nM, this computed threshold shift is more than 10% of the
value of the zero bias threshold voltage.
In the subthreshold regime and for low frequency -including static- signal conditions,
the NMOS drain current, I
d
, is given approximately by
[2],[4]
,
( )
ds df
V V gs bs
d ot
T
V V
W
I I 1 ,
L V
exp e
+ | |
| |
~
|
|
\ .
\ .
(4-18)
where W/L is recalled as the designable gate aspect ratio of the transistor. We observe that for
given values of the gate-source voltage, V
gs
, the drain-source voltage, V
ds
, and the bulk-source
voltage, V
bs
, drain current I
d
scales linearly with W/L. Circuit designers are free to alter the gate

- 322 -
geometries of the transistors they utilize in a circuit design undertaking, as long as gate width W
satisfies the constraint, W L L
min
, where L
min
, is the minimal channel length permitted by the
process foundry. In (4-18), saturation current I
ot
, dimensionless parameters and , and voltage
V
df
are empirically deduced from volt-ampere characteristics measured in the laboratory or from
computer simulations of characteristic curves extracted under subthreshold biasing conditions.
For most NMOS and PMOS devices featuring channel lengths L that are no longer than 180 nM,

Figure (4.4). The body effect of bulk-source voltage, V
bs
, on threshold voltage, V
h
, for various gate
oxide thicknesses (T
ox
) in an NMOS transistor. For the purpose of this demonstra-
tion, the bulk impurity concentration, N
A
, is taken to be 10
15
atoms/cm
3
. The interfa-
cial temperature of the transistor is presumed to be 27 C, for which the intrinsic car-
rier concentration, n
i
, is about 10
10
atoms/cm
3
.
18
ot
df
I 10 amperes
0.90 1
.
0.05 0.25
4 volts V 10 volts
q
s
s <
s <
s s
(4-19)
We note an extremely small saturation current, I
ot
. We should appreciate the fact that this minis-
cule saturation current interacts with a gate-source voltage that is necessarily bracketed above by
threshold potential V
h
and drain-source and bulk-source voltages applied in subthreshold regimes
that are generally as small as a volt or so. The immediate upshot of these small voltage scenes is
a very small subthreshold drain current. Typically, these drain currents rarely exceed a few
nanoamperes, and they can be as low as a few femtoamperes. Moreover, the relatively large vol-
tage, V
df
, tends to minimize drain current sensitivity to drain-source voltage. This is to say that
in subthreshold, the drain current is controlled almost exclusively by gate-source voltage V
gs
,
and, to a lesser extent, by bulk-source voltage, V
bs
.
The exponential dependence of transistor drain current on applied gate-source voltage
is reminiscent of the exponential dependence of BJT collector current on applied base-emitter
voltage. Indeed, we note that
0
20
40
60
80
100
120
140
160
180
0.0 -1.0 -2.0 -3.0 -4.0 -5.0
T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e

C
h
a
n
g
e
,

(
V
h
V
h
o
)
(
m
V
)
Bulk-Source Voltage, V
bs
(volts)

- 323 -
( )
ds df
V V
gs
d bs
ot T T
V
I V
1 ,
W L I V V
ln ln e q

| | ( | |
| |
| | ( ~ + +
|
|
| |
(
\ .
\ . \ .
(4-20)
which shows that the subthreshold drain current is semi-logarithmically linear with gate-source
(and also bulk-source) voltages. Because the drain-source voltage, V
ds
, applied to subthreshold
domain MOSFETs is typically small in comparison to the voltage parameter, V
df
, drain-source
voltages generally exert little impact on the semi-logarithmic plot of drain current versus gate-
source voltage.
In this text, very few circuits exploit MOSFETs that are constrained to operate in
subthreshold regimes. One reason for this pedagogical tack is that sub-nanoampere, subthre-
shold drain currents are sufficiently small to risk their being masked by uncorrelated noise cur-
rents that are unavoidably generated in the bulk immediately below the oxide interface. Another
reason derives from the caution flag that must be planted around the fact that for the low signal
frequencies to which the volt-ampere characteristic of (4-18) abides, no less than four empiri-
cally deduced parameters are invoked. Aside from an inherent inability to adjudicate the manner
in which these empiricisms are affected by scaled device geometries, these non-physical parame-
ters render accurate prediction and reproducibility of subthreshold circuit responses improbable
in the absence of design heroics. At a minimum, such heroics include novel feedback measures
and at a maximum, they require embedded microcontrollers that literally adjust node voltages or
branch currents in response to comparing monitored subthreshold circuit performance to design
targets. Yet another reason for deemphasizing subthreshold regime operation is the anemic gains
and constricted bandwidths afforded by the small currents indigenous to transistors that operate
in subthreshold.
One notable advantage of the small drain currents evidenced in subthreshold operating
domains is the virtually negligible heat these currents generate because of classic I
2
R losses.
These virtually negligible losses explain the escalating popularity of subthreshold MOSFETs in
numerous biomedical and neurological applications. Included among these applications are
cochlear implants for the deaf, implantable neurological and biomedical sensing, monitoring, and
cell excitation electronics, and subcutaneous, fully automated, electronic drug delivery systems.
In these and related neurosciences and biomedical applications, internal temperature rises as
small as 1 C to 2 C in the brain and in other human organs are potentially catastrophic.
EXAMPLE #4.1:
The HSPICE Level 3 parameters for an NMOS transistor featuring a minimum permissi-
ble 0.5 m channel length are delineated in Table (4.1). Table (4.2), which is used later
in the text and in the exercises accompanying this chapter, gives HSPICE parameters for
a PMOS transistor that is nominally complementary to the subject NMOS device. Some
of the parameters delineated in the table are curve fit entities for which we need not be
concerned. The engineering significance of other parameters in this table, such as those
that deal with device capacitances, is addressed later in this chapter. Using L = 1 m
and W = 10 m and with the source and bulk terminals both grounded, use SPICE soft-
ware to simulate the room temperature characteristic curves, I
d
-versus- V
gs
for drain-
source voltages, V
ds
, of 0.5 V, 1.5 V, and 2.5 V. Using these simulated results, determine
the nominal range of gate-source voltages for which the transistor is constrained to oper-
ate in its subthreshold regime.


- 324 -
SPICE
SYMBOL
TEXT
SYMBOL
DESCRIPTION
OF PARAMETER
VALUE UNITS
VTO V
ho
Zero Bias Threshold Voltage 550 mV
TOX T
ox
Gate Oxide Thickness 9.5 nM
GAMMA (2V
u
)
0.5
Body Effect Coefficient 0.32 volt
1/2

PHI |2V
F
| Magnitude Of Twice Fermi Potential 700 mV
XJ Y
d
Source & Drain Junction Depth 0.20 M
KP
o
C
ox
Transconductance Parameter 156 mho/volt
NSUB N
A
Average Substrate Doping Concentration 1.4(10
17
) atoms/cm
3

NFS Surface State Subthreshold Parameter 7.2(10
11
)
DELTA Threshold Versus Gate Width Parameter 0.88
LD L
d
Source-Drain Lateral Overlap 50 nM
TPG Gate Material Polarity (Ignored If VTO Is Specified) 1
UO
n
Low Field Carrier Mobility 420 cm
2
/volt-sec
THETA 1/V
ve
Vertical Field Mobility Degradation Parameter 0.23 volt
1

RSH R
sh
Source & Drain Sheet Resistance 2.0 O/Square
VMAX v
sat
Maximum Carrier Drift Velocity (1.8)(10
5
) meter/sec
KAPPA Channel Length Modulation Factor 0.011 volt
1

ETA 1/V
Threshold Parameter For Drain induced barrier lowering 0.02125

CGDO C
gdo
Gate-Drain Overlap Capacitance Density 310 pF/meter
CGSO C
gso
Gate-Source Overlap Capacitance Density 320 pF/meter
CGBO C
gbo
Gate-Bulk Overlap Capacitance Density 550 pF/meter
CJSW C
jsw
Zero Bias Sidewall Capacitance Density 320 pF/meter
CJ C
jo
Zero Bias Bulk Junction Capacitance Density 560 F/meter
2

MJ m
j
Bulk Junction Grading Coefficient 0.34
MJSW m
jsw
Sidewall Junction Grading Coefficient 0.35
PB V
j
Bulk-Drain/Bulk-Source Junction Built-In Potential 1.1 volt
LEVEL Model Type 3
Table (4.1). HSPICE LEVEL 3 model parameters for a representative 500 nM NMOS transistor. In addition to
specifying these parameters, the gate width, W, the channel length, L, and high frequency geometric
parameters P
s
, P
d
, A
s
, and A
d
, must be delineated on the model line of the SPICE circuit file. In the
absence of definitive process information, the latter four parameters are estimated in accordance with
guidelines provided later in the chapter.

SPICE
SYMBOL
TEXT
SYMBOL
DESCRIPTION
OF PARAMETER
VALUE UNITS
VTO V
ho
Zero Bias Threshold Voltage 480 mV
TOX T
ox
Gate Oxide Thickness 9.5 nM
GAMMA (2V
u
)
0.5
Body Effect Coefficient 0.28 volt
1/2

PHI |2V
F
| Magnitude Of Twice Fermi Potential 700 mV
XJ Y
d
Source & Drain Junction Depth 0.20 M
KP
o
C
ox
Transconductance Parameter 144.5 mho/volt
NSUB N
D
Average Substrate Doping Concentration 1.2(10
17
) atoms/cm
3

NFS Surface State Subthreshold Parameter 6.6(10
11
)
DELTA Threshold Versus Gate Width Parameter 0.65
LD L
d
Source-Drain Lateral Overlap 67 nM
TPG Gate Material Polarity (Ignored If VTO Is Specified) 1
UO
p
Low Field Carrier Mobility 220 cm
2
/volt-sec
THETA 1/V
ve
Vertical Field Mobility Degradation Parameter 0.18 volt
1

RSH R
sh
Source & Drain Sheet Resistance 2.0 O/Square
VMAX v
sat
Maximum Carrier Drift Velocity (1.8)(10
5
) meter/sec
KAPPA Channel Length Modulation Factor 0.078 volt
1

ETA 1/V
Threshold Parameter For Drain induced barrier lowering 0.018


- 325 -
SPICE
SYMBOL
TEXT
SYMBOL
DESCRIPTION
OF PARAMETER
VALUE UNITS
CGDO C
gdo
Gate-Drain Overlap Capacitance Density 370 pF/meter
CGSO C
gso
Gate-Source Overlap Capacitance Density 370 pF/meter
CGBO C
gbo
Gate-Bulk Overlap Capacitance Density 430 pF/meter
CJSW C
jsw
Zero Bias Sidewall Capacitance Density 190 pF/meter
CJ C
jo
Zero Bias Bulk Junction Capacitance Density 930 F/meter
2

MJ m
j
Bulk Junction Grading Coefficient 0.48
MJSW m
jsw
Sidewall Junction Grading Coefficient 0.35
PB V
j
Bulk-Drain/Bulk-Source Junction Built-In Potential 0.92 volt
LEVEL Model Type 3
Table (4.2). HSPICE LEVEL 3 model parameters for the 500 nM PMOS complement to the NMOS transistor
parameterized in Table (4.1).
SOLUTION #4.1:
(1). The results of the characteristic curve simulation for gate-source voltages spanning 0 to 700
mV are displayed in Figure (4.5). It is convenient to plot this drain current on a logarithmic
scale so as to convey clearly the exponential dependence of the subthreshold drain current on
the applied gate-source voltage. From (4-17), with recognition given to the fact that SPICE
simulators plot logarithmic axes to base 10,

Figure (4.5). The subthreshold volt-ampere characteristics of the NMOS device considered in
Example (4.1). The bulk-source voltage, V
bs
, in this example is zero volts.
(2). A casual inspection of the simulated results suggests that the gate-source voltage range that
embodies the semi-logarithmically linear subthreshold domain is
gs
150 mV V 550 mV . s s
(E1-1)
If we compare (E1-3) to (4-16), we are led to believe that V
hf
150 mV and V
h
550 mV.
The HSPICE simulation executed to arrive at the curves of Figure (4.5) projects a device
threshold voltage of 563.7 mV, which is only 2.49% larger than our crude estimate of the up-
per gate-source voltage limit to subthreshold regime operation.
ENGINEERING COMMENTARY:
The empirical model parameters, , , and V
df
, can be extracted from the foregoing simulated
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
0 100 200 300 400 500 600 700
D
r
a
i
n

C
u
r
r
e
n
t

(
A
m
p
e
r
e
s
)
Gate-Source Voltage, (mV) V
gs
V = 0.5 V
ds
V = 1.5 V
ds
V = 2.5 V
ds

- 326 -
plots. This task is left as an exercise for the reader.
As we expect, the semi-logarithmic plots of the subthreshold drain current appear to be linear
functions of the applied gate-source voltage. Also as expected, the drain-source voltage has
minimal effect on observed subthreshold drain current. Because of this small impact, the
characteristic equation in (4-18) can be modified is such a way as to project a nominally
semi-logarithmically linear dependence on drain-source voltage.
4.3.3. TRANSISTOR IN OHMIC REGIME
NMOS transistors operate in their ohmic, or triode, regimes when two conditions are
satisfied. The first of these conditions embraces the turn on constraint,
gs h
V V , > (4-21)
which implicitly asserts that the oxide-bulk potential at the interface proximate to the source im-
plant be at least twice the Fermi potential. It follows that in the ohmic domain, the interfacial
channel region near the source site is strongly inverted. The second condition underpinning oh-
mic operation is
ds gs h
V V V . < (4-22)
A useful alternative form to (4-22) derives from an inspection of the device schematic symbol in
Figure (4.1). In particular, we see therein that
ds gs gd
V V V . = (4-23)
If we substitute (4-23) into (4-22), we arrive at an equivalent and more illuminating form of the
second condition for ohmic regime operation; namely,
gd h
V V , > (4-24)
which implies that the oxide-bulk interfacial region near the drain volume must support, like the
region near the source site, twice Fermi potential. When combined with (4-21), we therefore
conclude that (4-22), or its equivalent form in (4-24), stipulates that the necessary condition
commensurate with MOSFET operation in the ohmic regime is that the entire channel extending
from the source site to the drain volume and lying immediately beneath the oxide layer be
strongly inverted.
In the ohmic region, the drain current of an NMOS device is given by the classic
Schichman-Hodges relationship
[5]
,
ds
d n ds gs h
V W
I K V V V ,
L 2
| | | |
=
| |
\ . \ .
(4-25)
where K
n
, the transconductance coefficient (in units of mhos/volt), is
n n ox
K C ; = (4-26)
in turn, the oxide capacitance density, C
ox
, is given by (4-9). In (4-26),
n
represents the mobility
(in units of cm
2
/volt-sec) of free electrons in the strongly inverted channel lying beneath the gate
oxide layer. The electron mobility, which is literally a measure of the ability of an electron to be
moved or transported, is a function of the electric field strength established in the channel by an
applied drain-source voltage. It is also dependent on the absolute surface temperature, T, of the
device. To the latter end, a commonly invoked empirical relationship is
[6]

3 2
o
n n o
T
(T) (T ) ,
T
| |
~
|
\ .
(4-27)

- 327 -
where
n
(T
o
) denotes the mobility of a free electron at the reference temperature, T
o
, which is
traditionally taken as 27 C. We note that the mobility, and hence parameter K
n
, decreases with
increasing operating temperature. Accordingly, we say that an ohmic regime MOSFET boasts a
negative temperature coefficient in that for constant gate-source and drain-source voltages, its
drain current decreases with increasing device operating temperature.
For a PMOS transistor, the ohmic regime drain current expression and its associated
parametric relationships are similar to those of the NMOS unit. In particular, a PMOS device
operates in its ohmic region for
sg h
sd sg h
V V
,
V V V
>
<
(4-28)
where it is understood that the threshold voltage, V
h
, remains positive in these expressions.
When (4-28) is satisfied, the PMOS drain current, I
d
, which flows out of the drain terminal of the
transistor, is
sd
d p sd sg h
V W
I K V V V ,
L 2
| | | |
=
| |
\ . \ .
(4-29)
where transconductance coefficient K
p
is
p p ox
K C , = (4-30)
and
p
is the mobility of holes in the strongly inverted channel of the PMOS transistor. The
temperature dependence of hole mobility mirrors that of electron mobility, per (4-27).
The operational regime under present consideration is referred to as the ohmic regime
because for very small drain-source voltages, the MOSFET emulates a voltage-controlled linear
resistance; in effect, it functions as an electronic potentiometer. We can begin to appreciate this
contention by examining the small signal conductance, say G
ds
, established between the drain
and source terminals of a MOSFET operating in its ohmic regime. By small signal conduc-
tance presented between drain and source terminals, we mean the ratio of a differentially small
change in drain current to a corresponding differentially small change in drain-source voltage, as
opposed to a straightforward drain current to drain-source voltage ratio. For an NMOS device,
(4-25) gives
( )
gs h ds
d d
ds n gs h ds
ds
ds ds
gs h
V V V
I I W
G K V V V .
V
V L V
V V
2
| |
| | | c
| |
= =
| | |
c
\ .
\ .
|
\ .
(4-31)
There are interesting aspects to this result. The first of these is that if V
ds
<< (V
gs
V
h
), which
subscribes to the ohmic constraint of (4-22),
ds gs h
ds gs h
d d
ds
V V V
ds ds
V V V
I I
G .
V V
<<
<<
c
~
c
(4-32)
Equation (4-32) suggests that the subject small signal conductance behaves as a linear conduc-
tance (or resistance). In order to clarify this contention, consider a traditional linear, two ter-
minal resistance, R, which supports a terminal voltage, V. Our friend, George Ohm, teaches I =
V/R. But for this linear, two terminal resistance, we also learn that
I I 1
.
V V R
c
= =
c
(4-33)

- 328 -
which is to say that the small signal and actual conductance of a two-terminal linear resistance
are identical. By comparison of (4-33) and (4-32), we conclude that the conductance between
the drain-source terminals of a MOSFET operated with very small drain-source voltage is
indisputably linear.
The second of the aforementioned two important points is that for very small V
ds
,
( )
ds gs h
ds gs h
d
ds n gs h
V V V
ds
V V V
I W
G K V V ,
V L
<<
<<
c
| |
~
|
c
\ .
(4-34)
which underscores the fact that the observed small signal, and approximately linear, conductance
is controllable via the applied gate-source voltage, V
gs
. In a word, a MOSFET operated in its oh-
mic domain at very small drain-source voltages behaves approximately as a linear two terminal
element whose conductance (resistance) can be adjusted by the applied gate-source voltage, V
gs
.
In effect, the device behaves as an electronic (voltage-controlled) potentiometer, as opposed to a
mechanical one whose resistance is altered by physically rotating a dial that causes the resistance
between two terminals to change. Finally, we note that as V
ds
approaches the voltage difference,
(V
gs
V
h
), the conductance in (4-28) tends toward zero or equivalently, the small signal drain-
source resistance tends toward infinity. On the presumption that drain current nonetheless flows
when V
ds
tends toward (V
gs
V
h
), this means that the MOSFET behaves as an ideal current
source.
As we might surmise from the preceding arguments, MOSFETs operating in ohmic do-
mains enjoy widespread utility as electronically adjustable resistances. Such resistances prove
indispensable when manufacturing or environmental uncertainties compel adjustments in net-
work pole or zero frequencies, gain, impedances, biasing levels, or other performance metrics.
While ohmic regime MOSFETs can function as amplifiers, the gain and bandwidth afforded in
the ohmic regime are muted in comparison to the attainable performance when transistors oper-
ate in the next regime we shall consider; namely, the saturation regime.
4.3.4. TRANSISTOR IN SATURATION REGIME
In the saturation regime, the gate-source and drain-source voltages of an NMOS
transistor satisfy the dual constraints,
gs h
ds gs h dsat
V V
,
V V V V
>
>
(4-35)
where V
dsat
is termed the drain saturation voltage. In saturation, therefore, the interfacial region
near the source is strongly inverted, but the second of the two inequalities in (4-35), which is
tantamount to requiring V
gd
s V
h
, implies that the drain end of the channel is not necessarily in-
verted. Transistors typically operate in saturation for linear signal processing applications. In
this domain, the drain current is given by
( )
2
n
d gs h
K W
I V V .
2 L
| |
=
|
\ .
(4-36)
Since this drain current is postured as independent of the drain-source voltage, V
ds
, we can argue
that to the extent that (4-36) accurately reflects the saturated static characteristic curves of a
MOSFET, the MOSFET behaves as an ideal current source whose current value is controlled by
a quadratic function of gate-source voltage V
gs
. In effect, we see that the saturated MOSFET be-
haves as a nonlinear (square law), voltage controlled current source. For low-power linear

- 329 -
applications, we generally wish to set the quiescent drain-source voltage as close to its drain
saturation value as input signal amplitude conditions and corresponding linearity targets permit.
The saturated drain current given by (4-36) is commonly referenced as the drain satura-
tion current, I
dsat
, which is to say that a drain current of I
dsat
corresponds to an applied drain-
source voltage of V
dsat
. Specifically,
( )
2
2
n n
d gs h dsat
dsat
K K W W
I V V V I .
2 L 2 L
| | | |
= =
| |
\ . \ .
(4-37)
We should advise caution when interpreting current I
dsat
and voltage V
dsat
as constants. While
these two metrics are theoretically independent of the drain-source voltage, V
ds
, they are
functionally dependent on gate-source and drain-source voltages. For example, we shall see that
because of mobility degradation incurred by the lateral drain to source electric fields resulting
from applied drain-source voltages, V
dsat
is dependent on V
ds
.
For PMOS devices (4-35) and (4-36) respectively become
sg h
sd sg h ssat
V V
V V V V
>
>
(4-38)
and
( )
2
p p 2
d sg h ssat
K K
W W
I V V V .
2 L 2 L
| | | |
= =
| |
\ . \ .
(4-39)
The voltage excess, (V
sg
V
h
) is properly interpreted as the source-drain saturation voltage, V
ssat
.
As in the case of the ohmic regime volt-ampere characteristics, threshold voltage V
h
remains a
positive number.
In order to ensure operation in the saturated domain, the minimum permissible drain-
source voltage is the drain saturation voltage, which for NMOS is V
dsat
, as defined by (4-35). In
contrast, the maximum permissible drain-source voltage commensurate with ohmic regime
operation is also V
dsat
. From the ohmic regime drain current expression of (4-25), we note that
when V
ds
= V
dsat
= (V
gs
V
h
), the resultant drain current is identical to the drain saturation cur-
rent, I
dsat
, given by (4-37). Thus, at the cusp of the ohmic and saturation regimes, the ohmic re-
gime current dutifully conflates with the value of the saturation region drain current.
4.3.5. SUMMARY OF TRANSISTOR CHARACTERISTICS
In the interest of future convenience, we summarize herewith the volt-ampere
characteristics of both NMOS and PMOS MOSFETS operated in cutoff, subthreshold, ohmic,
and saturated regimes. For the NMOS transistor,
( )
ds df
gs hf
V V
gs bs
ot hf gs h
T
d
ds
n ds gs h gs h ds gs h
2
n gs h gs h ds gs h
0, for V V
V V
W
I 1 , V V V
L V
I ,
V
2 V V V , V V & V V V
2
V V , V V & V V V
exp e
q
|
|
<
+ | |
| |
| |
|
s <
|
|
|
|
\ .
\ .
\ .
=
| |
> < |
|
\ .
> >
(cutoff)
(subthreshold)
(ohmic)
(saturation)
(4-40)

- 330 -
where we have introduced the convenient shorthand notation of parameter |
n
as,
n
n
K W
.
2 L
| |
|
\ .
(4-41)
We should take care to note that parameter |
n
scales linearly with the gate aspect ratio of the de-
vice. For the PMOS counterpart to the NMOS transistor,
( )
sd df
sg hf
V V
sg sb
ot hf sg h
T
d
sd
p sd sg h sg h sd sg h
2
p sg h sg h sd sg h
0, for V V )
V V
W
I 1 , V V V
L V
I ,
V
2 V V V , V V & V V V
2
V V , V V & V V V
exp e
q
|
|
<
+ | |
| |
| |
|
s <
|
|
|
|
\ .
\ .
\ .
=
| |
> < |
|
\ .
> >
(cutoff
(subthreshold)
(ohmic)
(saturation)
(4-42)
where
p
p
K
W
.
2 L
| |
|
\ .
(4-43)

Figure (4.6). Sample common source volt-ampere characteristics of an n-channel transistor having a threshold
voltage, V
h
, of 500 mV and an effective scaled transconductance parameter, |
n
, of 1 mmho/volt.
Figure (4.6) graphically illustrates the MOSFET static characteristic curves with both
source and bulk terminals grounded. The representative NMOS transistor boasts a threshold vol-
tage of 0.5 V and a scaled transconductance parameter (|
n
) of 1.0 mmho/V. These curves focus
on only the ohmic and saturation relationships delineated in (4-40); that is, we have tacitly taken
subthreshold currents to be zero. We should note that as expected, the volt-ampere characteris-
tics are nominally linear for drain-source voltages in the immediate neighborhood of V
ds
= 0
volts. In addition, these low voltage curves correctly project increasing slope, and hence increas-
ing small signal conductance (decreasing small signal resistance) for increases in the gate-source
voltage. In Figure (4.6), we include a plot, shown as the dashed curve, which highlights the
0
2
4
6
8
10
12
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
,

(
m
A
)
Drain-Source Voltage, V
ds
, (volts)
V
gs
= 2 volts
V
gs
= 3 volts
V
gs
= 4 volts
V
gs
= 5 volts
Ohmic-Saturation
Boundary
Nominally Linear
Characteristics

- 331 -
boundary between ohmic and saturated domains. To the left of this boundary, the ohmic
relationship in (4-40) applies, while to the right of the boundary, constant drain current given by
the saturation equation in (4-40) is evidenced. We shall shortly learn that the characteristic
curves of an actual transistor, such as the one parameterized in Table (4.1), can differ markedly
from the idealized Schichman-Hodges behavior plotted in Figure (4.6).
4.4.0. FIRST ORDER DESIGN STRATEGY
The MOSFET models defined by (4-38) and (4-40) reflect simple and arguable
idealized transistor behavior in that they tacitly ignore numerous second order phenomena that
are loom significant in scaled, deep submicron, MOS technology devices. These higher order
effects, which we shall investigate later in this chapter, include channel length modulation
(CLM), field-induced carrier mobility degradation, drain induced barrier lowering (DIBL), and
high frequency capacitive phenomena. But the Schichman-Hodges model, which is sometimes
referred to as the long channel model, for the ohmic and saturation regimes of operation is
nonetheless attractive because its analytical tractability forges an insightful understanding of first
order, circuit design results. These insights are vital to the design process because they inspire
creative design measures that mitigate the deleterious effects of the aforementioned and other
high order device phenomena. Consequently, circuit designers commonly rely on the simple
models for initial circuit design studies, with the understanding that these first order results must
ultimately be thoroughly investigated, refined, and presumably optimized through extensive
manual and computer-aided analyses that are premised on more realistic device models. The
result of these advanced analytical measures might be adjustments to biasing currents and
voltages, adjustments of gate aspect ratios, and even modifications of circuit architectures.
Another reason for invoking the simple transistor models in first order design calculations is
premised on elegantly elementary logic. In particular, if we cannot get an analog circuit to
function as we wish it to operate for approximate and presumably simple device representations,
we have little chance to get our circuit to work properly when real, refined, accurate, and
necessarily more complex device models are exploited. In other words, the exploitation of
simple device models in a successful first order design venture is a necessary, but admittedly
insufficient, condition for the realization of finalized design architectures.
4.4.1. VOLTAGE-CONTROLLED DIFFERENTIAL AMPLIFIER
Our first demonstration of the utility of the Schichman-Hodges model entails a
consideration of the simple differential amplifier depicted in Figure (4.7). In this schematic dia-
gram, transistors M1 and M2 are integrated transistors having identical gate aspect ratios. Since
the smallest circuit potential is zero, the bulk terminals of both transistors are returned directly to
ground in order to preclude forward current conduction across the bulk-source and bulk-drain
junctions. This action, of course, facilitates electrical isolation between the two active devices.
In view of the fact that the source terminals of the two devices are also grounded in the consi-
dered amplifier, the bulk-source voltages applied to the transistors are zero, thereby nullifying
BITM
2
and rendering the two transistor threshold voltages constant at their zero bias values, V
ho
.
We note that the gate-source voltages, V
gs1
and V
gs2
, applied respectively to M1 and M2 are

2
Remember that BITM stands for bulk-induced threshold modulation, or simply, body (or bulk) effect.

- 332 -
di
gs1 ci
di
gs2 ci
V
V V
2
.
V
V V
2
= +
=
(4-44)
In (4-44), V
ci
is taken as an adjustable bias that is required to assure turn on of the two transistors.
Since voltage V
ci
is a component of both of the two gate-source voltages, it is traditionally re-
ferred to as a common mode input voltage. On the other hand, voltage V
di
is taken as a time
varying signal that the network is called upon to amplify. We note by (4-44) that the difference
of the two applied gate-source voltages, (V
gs1
V
gs2
), is identically V
di
, whence we shall book-
mark V
di
as the differential mode input voltage.

Figure (4.7). Schematic diagram of a simple differential amplifier realized in MOSFET
technology.
Let us assume that we wish the differential amplifier at hand to operate linearly. This is
to say that we wish the indicated output voltage, V
do
, to respond linearly to the applied differen-
tial mode input signal, V
di
. We observe that V
do
is a differential output voltage in that it
represents the difference between the voltages established at the respective drain terminals of
transistors M2 and M1. Since MOSFETs embedded in linear circuit applications are invariably
biased in their saturation regimes, we systematically ensure that for all time,
di
gs1 ci ho
di
gs2 ci ho
V
V V V
2
,
V
V V V
2
= + >
= >
(4-45)
for which a clear necessary design condition is V
ci
> V
ho
. The amount by which voltage V
ci
must
exceed threshold level V
ho
is determined by the amplitude of the applied differential mode signal,
which is to say that care must be exercised to ensure that (4-45) is accommodated for all ex-
pected values of signal voltage V
di
.
But in addition to satisfying (4-45), which merely ensures that the transistors conduct
nonzero drain currents for all time, the individual drain-source voltages of the transistors must be
+
V
ci

M1 M2
V /2
di
V /2
di
I
d1
I
d2
R R
+V
dd
+ V
do

- 333 -
at least as large as their drain saturation voltages. An inspection of the subject schematic dia-
gram reveals that the drain-source voltage, V
ds1
of transistor M1 is, in terms of the M1 drain cur-
rent, I
d1
,
ds1 dd d1
V V I R. = (4-46)
On the other hand, for M2,
ds2 dd d2
V V I R , = (4-47)
where I
d2
is the instantaneous drain current conducted by transistor M2. Accordingly, we require
ds1 dd d1 gs1 ho
ds2 dd d2 gs2 ho
V V I R V V
.
V V I R V V
= >
= >
(4-48)
The relationships in (4-46) mandate that the power line voltage, V
dd
, must be sufficiently large,
while the load resistances, R, in the drain circuits cannot be too large for stipulated drain current
values.
In the saturation regime, the drain currents identified in (4-46) and (4-47) are given by
the Schichman-Hodges expressions,
( )
( )
2
d1 n gs1 ho
2
d2 n gs2 ho
I V V
,
I V V
=
=
(4-49)
where use is made of the fact that since transistors M1 and M2 are identical devices biased with
zero bulk-source voltages, they share the same transconductance coefficient, |
n
, and the same
threshold potential, V
ho
. It follows that the differential drain current, (I
d1
I
d2
), is
( ) ( )
2 2
d1 d2 n gs1 ho gs2 ho
I I V V V V .
(
=
(

(4-50)
We see that the bracketed quantity is of the algebraic form, (a
2
b
2
). It can therefore be factored
as (a + b)(a b), which no doubt enhances the pride our high school algebra teachers have in us.
Thus,
( )( )
d1 d2 n gs1 gs2 ho gs1 gs2
I I V V 2V V V .
(
= +

(4-51)
Using (4-45), this result can be couched into the more useful construct,
( )
d1 d2 n ci ho di
I I 2 V V V . = (4-52)
The differential output voltage response, V
do
, of the subject network now follows as
( ) ( )
do d1 d2 n ci ho di
V R I I 2 R V V V . = = (4-53)
It is worth texting home about the last result. The most notable aspect of (4-53) is that
for constant common mode input voltage, V
ci
, the output voltage response is a linear function of
the input differential input signal, V
di
. In other words, the amplifier linearly processes the ap-
plied signal, V
di
. This linearity follows without any a priori restrictions on either the input signal
amplitude or the precise nature of the biasing established by voltages V
dd
and V
ci
. Indeed, the
only presumption we enforced at the outset is that both transistors in the amplifier operate for all
values of V
ci
, V
di
, and V
dd
in their saturation domains.
A subliminal ramification of (4-53) is that there is no static, or DC, level associated
with the differential voltage response, V
do
. In other words, when V
di
= 0, V
do
= 0. It is one thing
to observe this apparent triviality, but it is quite another thing to understand and appreciate the
phenomenon. We begin by observing that with V
di
= 0, Figure (4.7) indicates an identical vol-

- 334 -
tage in the amount of common mode bias V
ci
activating the gate-source terminals of transistors
M1 and M2. But since M1 and M2 are presumably perfectly matched, (4-49) confirms that the
two transistor drain currents, I
d1
and I
d2
, are identical for V
di
= 0. With identical circuit resis-
tances, R, this means that the static, zero signal voltages developed with respect to ground at the
drain terminals of each transistor are identical; that is, (V
dd
I
d1
R) (V
dd
I
d2
R). Resultantly,
the voltage difference, V
do
, between these two static drain voltages is null. In other words, no
DC differential output voltage prevails when the differential input voltage is null. However, we
note ominously that a static output, or DC offset is manifested when either the two transistors
and/or the two circuit resistances are not respectively matched. Prudently laid out monolithic
networks minimize these mismatches and in addition, suitable feedback measures can mitigate
undesirable static offsets. More about these engineering issues appears later in this text.
Since V
do
is, like V
di
, a voltage that is extracted differentially, we can cleverly advance
the notion that the amplifier in question delivers a differential voltage gain, say A
dv
, of
( )
do
dv n ci ho
di
V
A 2 R V V .
V
= (4-54)
Clearly, this gain can be rendered small or large, depending on the choice of resistance R, pro-
vided, of course, that the constraints associated with saturation region operation are not violated.
But in addition, the gain can be set, for fixed R and fixed V
ci
, by selection of the gate aspect ratio,
to which parameter |
n
is directly proportional. Finally, we note that the voltage gain can be
electronically adjusted through variations in the common mode input voltage, V
ci
. For example,
A
dv
is zero if V
ci
= V
ho
(or even if V
ci
< V
ho
, since negligible current flows through the drain cir-
cuits of transistors biased below threshold), while A
dv
rises linearly with increases in V
ci
.

Figure (4.8). Simulated I/O static transfer response of the amplifier whose schematic diagram ap-
pears in Figure (4.7).
We can confirm the propriety of the foregoing amplifier deliberations by simulating the
circuit in Figure (4.7) using the transistor parameterized in Table (4.1). In particular, we can use
HSPICE or equivalent circuit simulation software to garner the static differential transfer
characteristic, which is a plot of the differential output voltage, V
do
, versus the differential input
0
0.25
0.50
0.75
1.00
1.25
0 100 200 300 400 500
D
i
f
f
e
r
e
n
t
i
a
l

O
u
t
p
u
t

V
o
l
t
a
g
e
,

(
V
)
V
d
o
Half Differential Input Voltage, (mV) V /2
di
V
=
7
5
0
m
V
ci
1
.
2
5

V
1
.
7
5

V
2
.
2
5

V

- 335 -
voltage, V
di
, for several values of the common mode input bias, V
ci
. To this end, we take the gate
aspect ratios of both transistors to be 20 m /1 m. Moreover, we let the power line voltage be
V
dd
= 5 volts, and we choose the drain load resistances to be R = 500 . The simulated transfer
characteristic curves in Figure (4.8) depict, as predicted, excellent linearity over an input voltage
range extending from 0 s V
di
/2 s 500 mV for V
ci
= 0.75 V, 1.25 V, 1.75 V, and 2.25 V. Recalling
(4-54), we see that the differential gain of the circuit is the slope of the individual curves and, as
anticipated, this gain is seen to increase with increasing V
ci
.
Although the circuit in Figure (4.7) proves advantageous from the perspective of enabl-
ing electronic I/O gain control through adjustments in common mode bias, V
ci
, it can be an
undesirable topology in other situations. For example, suppose V
ci
derives as a simple voltage
divider from the power line voltage, V
dd
. Then if variations in V
dd
are incurred because of poor
line regulation, spurious electrical noise coupled to the power bus, or other phenomena, (4-54)
shows that these perturbations are transmitted directly to the differential output voltage response.
In short, parasitic signals can be manifested across the differential output port if the power line
voltage is not implemented and maintained prudently. Moreover, if a signal component prevails
implicitly to V
ci
, perhaps intentionally or through parasitic high frequency coupling, this signal
effectively modulates with the applied differential signal, V
di
, to produce a harmonically rich,
and therefore distorted, output response. For example, let V
ci
contain a sinusoidal signal compo-
nent at radial frequency
ci
and let the fundamental frequency component of V
di
be
di
. Then,
(4-54) can be shown to produce an output voltage response whose frequency spectrum contains
signal components at the frequencies,
ci
,
di
, and (
ci

di
). This response is clearly undesira-
ble in that in a linear circuit, the only frequency component we should witness at the output port
is the given fundamental frequency,
di
, of the applied differential signal
4.4.2. SIMPLE COMMON SOURCE AMPLIFIER
A second demonstration of Schichman-Hodges utility entails the determination and
interpretation of the static transfer characteristic, V
o
-versus- V
i
, of the common source amplifier
in Figure (4.9). In this amplifier, V
i
is the net voltage developed at the input port, which is
formed of circuit ground and the gate terminal of transistor M1. We note that in the given
configuration, V
i
is the superposition of a static (or DC) voltage, V
gg
, and a voltage, V
s
; that is,

Figure (4.9). Schematic diagram of a simple common source amplifier.
+
V
gg

M2
M1
V
o
V
i
V
s
+V
dd
I
d2
I
d1

- 336 -
i s gg
V V V . = + (4-55)
If V
s
is exclusively a signal voltage that contains no static component, voltage V
gg
alone
establishes the quiescent operating point at the amplifier input port. This voltage must exceed
the threshold potential of M1 to ensure that M1 is conductive. Since V
gg
biases the gate-source
terminals of M1, it also establishes the quiescent component, say V
oQ
, of the net output voltage,
V
o
. If we wish to amplify linearly the applied signal, V
s
, transistor M1 is biased preferably in its
saturated regime so that in addition to ensuring V
gg
V
h
, V
oQ
must be at least as large as the
quiescent drain saturation voltage, (V
gg
V
h
). Our derivation of the static transfer characteristic
serves to formulate design guidelines for choosing values of V
gg
and V
oQ
that support the linear
signal processing target.
Before proceeding with the formulation of the static transfer characteristic, several is-
sues and observations surrounding the two transistors embedded in the circuit of Figure (4.9)
should be understood. The first important point is that M1 functions as a common source unit in
that its input port is the gate terminal of M1, while its output port, where the voltage response,
V
o
, is extracted with respect to ground, is the drain terminal of M1. Thus, the source terminal
serves as neither the input port nor the output port, whence the reference to the stage as a
common source amplifier. A second important point is that while transistor M1 operates as an
amplifier, transistor M2 functions as the effective load imposed on the drain of M1. Since the
gate of M2 is connected directly to its drain, M2 is effectively a two terminal load embedded in
series with the drain of transistor M1. To the extent that M2 is biased to operate in a linear
region of its static characteristic curves and to the further extent that device capacitances are
tacitly ignored for this static and low frequency analytical undertaking, M2 behaves effectively
as a resistive load imposed on the M1 drain.
Our continuing inspection of the circuit in Figure (4.9) reveals that both the bulk and
source terminals of transistor M1 are returned to ground. Accordingly, the bulk-source voltage
applied to M1 is zero, thereby negating BITM in M1 and rendering its threshold voltage equal to
the zero bias threshold value, V
ho
. On the other hand, while the bulk terminal of M2 is properly
returned to ground, the source terminal of M2 is connected to the drain of M1, which supports
the indicated output voltage, V
o
. It follows that the bulk-source voltage, V
bs2
, applied to M2 is
V
o
, which means that M2 experiences a potentially significant and signal-dependent body
effect. Nonetheless, we shall assume in our simplified first order analysis that the gate oxide
thicknesses of the transistors are sufficiently small to warrant our tacit neglect of body effect. In
other words, we shall take the threshold voltage of M2 to be identical to that of M1; namely V
ho
3
.
A fourth noteworthy point is that both transistors are realized as on chip elements and
are therefore physically similar. However, the respective gate aspect ratios of these transistors
are typically different. In particular, we shall take the gate aspect ratio of transistor M1 to be
W
1
/L
1
, which engenders a transconductance coefficient in this device of |
n1
. For M2, the gate
aspect ratio is taken to be W
2
/L
2
, whence a transconductance coefficient in M2 of |
n2
. Because
both transistors share the same oxide capacitance density and nominally the same carrier mobil-
ity within their respective inverted channels, (4-41) confirms

3
In some specialized processes, which feature a multi-well cross section, it is possible to connect the bulk terminal
directly to the source without incurring the bulk substrate current flow that would result if the source terminal does
not lie at the lowest circuit potential. In these specialized circumstances, body effect is obviously nullified by the
direct interconnection of bulk and source terminals.

- 337 -
n1 1 1
n2 2 2
W L
.
W L
= (4-56)
We shall learn shortly that performance advantages accrue in the common source stage when |
n1

exceeds |
n2
.
The final, and arguably the most interesting, point to be made is that since the gate and
drain terminals of transistor M2 are electrically tied to one another, the drain-source voltage, V
ds2
,
of M2, which is the voltage difference, (V
dd
V
o
), is identical to the gate-source voltage, V
gs2
, of
the subject transistor. From the second equation in (4-35), we therefore see that M2 always
operates in its saturation domain, regardless of the values of V
dd
and V
i
. This means that for all
operating circumstances, the drain current, conducted by transistor M2 is given by
( ) ( )
2
2
d2 n2 gs2 ho n2 dd o ho
I V V V V V . = = (4-57)
We therefore see that transistor M2 in the amplifier of Figure (4.9) is inextricably biased for
linear operation.
4.4.2.1. The Case Of V
i
< V
ho

When V
i
lies below threshold potential, transistor M1 is cutoff, provided subthreshold
phenomena are ignored. Thus, I
d1
0 but since I
d2
is obviously identical to I
d1
in Figure (4.9),
(4-57) shows that
o dd ho omax
V V V V . = (4-58)
Thus, we surmise that for V
i
< V
ho
and to the extent that subthreshold effects, as well BITM in
M2, are ignored, the output voltage response is clamped to its maximum and constant level,
V
omax
, which is one threshold level below the power supply voltage, V
dd
. The fact that the output
voltage is clamped to a constant is important from the standpoint that this output voltage is
incapable of responding to small changes in the input voltage, V
i
. It follows that no I/O voltage
gain can be achieved when V
i
< V
ho
.
i
V
ho
And Transistor M1 Saturated
At V
i
= V
ho
, transistor M1, and therefore transistor M2, remain nominally non-conduc-
tive. It follows that the output voltage, which is the voltage developed across the drain-source
terminals of transistor M1, continues to be pinned to the comparatively large value, V
omax
, deter-
mined by (4-58). Because this M1 drain-source voltage is relatively large when V
i
= V
ho
, we
envisage transistor M1 operating in its saturated domain as V
i
begins its rise above V
ho
. Thus,
( )
2
d1 n1 i ho
I V V . = (4-59)
Since I
d1
I
d2
, (4-57) and (4-59) yield
( ) ( )
2 2
n2 dd o ho n1 i ho
V V V V V . = (4-60)
We can straightforwardly solve this expression for the desired voltage response, V
o
. In particu-
lar,
( )
n1
o dd ho i ho
n2
V V V V V ,
= (4-61)
or, by (4-58) and (4-56),

- 338 -
( )
1 1
o omax i ho
2 2
W L
V V V V .
W L
= (4-62)
The last result demonstrates that as long as transistor M1 is in its saturation domain, the
output voltage, V
o
, of the common source amplifier in Figure (4.9) is a linear function of the net
voltage, V
i
, which activates the input port of the network. This observation lends credence to our
earlier contentions that linear signal processing is generally effected when the MOSFETs in a
circuit operate in their saturation regimes. Moreover, if we appeal to (4-55), (4-62) becomes
expressible as
( )
1 1
o omax gg s ho
2 2
W L
V V V V V ,
W L
= + (4-63)
which suggests that since the quiescent network state corresponds to the zero signal condition
inferred by V
s
= 0, the quiescent, or standby, output port voltage, V
oQ
, follows as
( )
1 1
oQ omax gg ho
2 2
W L
V V V V .
W L
= (4-64)
This quiescent output level can be adjusted linearly with V
gg
as long as the M1 turn on condition,
V
gg
> V
ho
, is sustained, and M1 operates in saturation. The foregoing two equations combine to
deliver
1 1
o oQ os s
2 2
W L
V V V V .
W L
| |
=
|
|
\ .
(4-65)
The left hand side of (4-65) represents a voltage change about the quiescent operating
point of the output port. Accordingly, it can be viewed, as we indicate, as the signal component,
V
os
, of the net output voltage response. The equation confirms further that this output voltage
perturbation is induced exclusively by input signal voltage V
s
. Therefore, we conclude that the
voltage gain, say A
v
, of the circuit is the ratio of the signal induced change, say V
os
, in output vol-
tage with respect to the output quiescent voltage level to the applied input signal; that is,
o oQ
os n1 1 1
v
s s 2 2 n2
V V
V W L
A .
V V W L
= = = = (4-66)
It is vitally important to see that the foregoing voltage gain is not the output voltage to
input port voltage ratio, V
o
/V
i
; instead, it is the ratio of the signal component of V
o
to the signal
component of V
i
, the latter being V
s
. This gain displays I/O phase inversion in that the gain itself
is a negative number. This phase inversion reflects the fact that in accordance with (4-63), out-
put voltage V
o
decreases as input signal V
s
increases and vice versa. We should additionally re-
joice the observation that the voltage gain magnitude is a highly predictable circuit performance
metric in that it is a ratio of geometric ratios. While individual geometric dimensions can be
controlled on chip to accuracies of no better than 15% to 25%, ratios of dimensions, and in-
deed ratios of dimensional ratios, can be controlled to within an error of 2% or less.
Finally, we must appreciate the fact that (4-64) and (4-65), on which the gain in (4-66)
is premised, rely on the saturation domain operation of transistor M1 in Figure (4.9). In this re-
gime, we are compelled to abide by the constraint, V
o
V
i
V
ho
= V
gg
+ V
s
V
ho
. By (4-63),
this inequality translates to the requirement,

- 339 -
omax dd ho
gg s ho i ho
v v
V V V
V V V V V .
A 1 A 1
+ = s =
+ +
(4-67)
This conclusion serves to stipulate pragmatic circuit design guidelines. In particular, (4-67)
brackets the maximum value of input port voltage, V
i
, which ensures the pertinence of (4-64)
through (4-66). To this end, we notice that voltage V
i
, and hence the amplitude associated with
signal voltage V
s
, can be large only if the power bus voltage, V
dd
, is large and/or the gain magni-
tude, |A
v
|, is small. Equivalently, we may state that the price paid for a need to amplify relatively
large input signals is the potentially large standby power dissipation that accompanies large V
dd
.
Moreover, it is intuitively clear that a large input signal necessarily restricts the gain magnitude
for if it does not, the signal swing, |A
v
|V
s
, manifested in principle at the output port may be suffi-
ciently large to push transistor M1 out of saturation.
The forgoing scrutiny supports a practical guideline to the effect that properly biased
amplifiers can function as linear signal processing networks only when suitably small signals are
earmarked for either amplification or for other forms of linear signal processing. With power
supply voltages in the range of 3 V to 5 V, MOSFETS featuring channel lengths as small as 0.5
m can deliver voltage gain magnitudes of 10 or very slightly larger.
i
V
ho
And Transistor M1 In Ohmic Domain
While transistor M1 operates in saturation, a continuing rise in the net input voltage, V
i
,
incurs a corresponding linear decrease in the output voltage, V
o
, as (4-62) confirms. Ultimately,
V
o
falls to the drain saturation voltage of M1 as V
i
nears its maximum permissible level of V
imax
,
which we define as the M1 gate-source voltage commensurate with operation of transistor M1 in
its saturation domain. The value of V
imax
can be determined by equating V
o
in (4-62) to (V
imax

V
ho
), whence
omax omax
imax ho ho
v n1
n2
V V
V V V .
A 1
1
= + = +
+
+
(4-68)
The output voltage, say V
omin
, corresponding to V
i
= V
imax
and the efficacious exodus of transistor
M1 from its saturation regime is determined by substituting (4-68) back into (4-62), with the re-
sult that
omax omax
omin
v n1
n2
V V
V .
A 1
1
= =
+
+
(4-69)
In other words, when the input voltage, V
i
, satisfies the constraint, V
ho
V
i
V
imax
, which corres-
ponds to the output voltage stipulation, V
omax
V
o
V
omin
, transistor M1 operates in saturation,
and the linear I/O relationship of (4-62) is applicable. On the other hand, when output voltage V
o

falls below V
omin
, which requires V
i
> V
imax
, M1 functions in its ohmic domain.
For V
o
< V
omin
, the third of the equations in (4-40) gives
o
d1 n1 o i ho
V
I 2 V V V .
2
| |
=
|
\ .
(4-70)
Equation (4-57) remains in force for transistor M2 and since I
d1
I
d2
, we arrive at the circuit
equilibrium relationship,

- 340 -
( )
2
o
n1 o i ho n2 dd o ho
V
2 V V V V V V .
2
| |
=
|
\ .
(4-71)
If we expand this equation and make use of (4-66) and (4-58), we arrive at the unfortunately
cumbersome second order algebraic equation,
( )
2
2 2
o i ho o
v v
omax omax omax
V V V V
A 1 2 1 A 1 0 .
V V V
( | | | | | |
+ + + =
( | | |
(
\ . \ . \ .
(4-72)
This relationship can certainly be solved for output voltage V
o
through use of the classic qua-
dratic formula. While we can persevere to crank out this solution, its algebraic complexity is
likely to cloud any design-oriented insights that we might wish to garner. Fortunately, we can
formulate an approximate and more tractable solution by remembering that (4-72) is valid only
for those operational circumstances for which transistor M1 operates in its ohmic regime. In this
regime, where V
i
> V
imax
, we know that output voltage V
o
satisfies V
o
< V
omin
. For sufficiently
small V
omin
, the squared ratio, (V
o
/V
omax
)
2
, is likely to be very small, thereby implying that we
may be afforded the mathematical luxury of ignoring the first term on the left hand side of (4-
72). The resultantly simplified equation delivers the approximate output voltage solution,
omax
o
2
i ho
v
omax
V
V .
V V
2 1 A
V
~
( | |
+
( |
\ .
(4-73)
We can expect that this approximate response result is reasonably accurate for input voltages V
i

that substantially exceed the voltage boundary, V
imax
. In the immediate neighborhood of V
imax
,
analytical errors accrue owing to the neglect of the first term on the left hand side of (4-72).
Nonetheless, (4-73) clearly underscores the anticipated fact that when M1 operates in its ohmic
domain, the output voltage response is a nonlinear function of the net input voltage, V
i
. More-
over, we see that output voltage V
o
converges toward zero for large values of V
i
.
Figure (4.10) graphically summarizes the foregoing analytical disclosures. The subject
plot shows that the output voltage response is clamped to a level, V
omax
, as given by (4-58).
Moreover, the output response is nominally linearly related to the net input voltage, V
i
, for V
ho

V
i
V
imax
, with V
imax
defined by (4-68). For V
i
> V
imax
, the output voltage is a nonlinear function
of V
i
, and it essentially abides by (4-73).
If linear operation is required of a given application, the curve in question suggests that
the amplifier must operate for all time in the indicated linear range of input voltage. In turn, this
means that the input biasing voltage, V
iQ
, which is identical to the applied constant input voltage,
V
gg
, must satisfy V
ho
< V
gg
< V
imax
. Since the input signal voltage, V
s
, superimposes with V
gg
and
swings positively and negatively about V
gg
, enabling maximum signal swing at both the input
and output ports requires V
gg
to nest in the center of the input voltage range that is commensurate
with nominal I/O linearity. Thus,
( )
imax ho dd ho
iQ gg ho
v
V V V V
V V V ,
2 2 A 1
+
= = +
+
(4-74)
We note in (4-74) that the input signal swing, (V
iQ
V
ho
), becomes progressively more restric-
tive with increasing gain magnitude.

- 341 -

Figure (4.10). Sketch of the static transfer response of the common source amplifier whose sche-
matic diagram appears in Figure (4.9). The voltages, V
iQ
and V
oQ
, respectively define
the input and corresponding output quiescent operating points that permit maximal
signal swing in the operating region where I/O linearity prevails.
EXAMPLE #4.2:
The common source amplifier depicted in Figure (4.9) is to be designed for a nominal
voltage gain magnitude of 5 volts/volt, when the power supply voltage, V
dd
, is 3 volts.
The channel length of each transistor, whose HSPICE Level 3 parameters are itemized
in Table (4.1), is chosen to be L = 1 m. At an input biasing voltage that affords maxi-
mum input signal swing for nominal I/O linearity, the standby transistor currents are to
chosen to deliver quiescent power dissipation in the neighborhood of 1.2 mW. Design
the circuit and simulate the resultant static forward transfer characteristics.
SOLUTION #4.2:
(1). We shall initiate our design iteration by taking the gate aspect ratio of the load transistor to be
W
2
= 1 m. Then, with L
1
= L
2
= W
2
= 1 m, and a target voltage gain magnitude of 5
volts/volt, (4-66) delivers W
1
= 25 m. An HSPICE simulation suggests that the centroid of
the linear range of the transfer characteristic lies at approximately 704 mV. With V
gg
in Fig-
ure (4.9) set to 704 mV, the simulated value of current flowing through both the driver and
the load transistors is 60.64 A. In view of the 3 V supply, this current produces a standby
circuit power dissipation of (3)(60.64 A) = 181.9 W.
(2). Since our target quiescent power dissipation is nominally 1.2 mW, the current that both
transistors conduct should be of the order of (1.2 mW)/3 V = 400 A, which is about 6.6-
times larger than the current realized with an M2 gate width of W
2
= 1 m. MOSFET device
currents scale with gate aspect ratio and thus, we theoretically need an M2 gate width of 6.6
m. Since power dissipation has been stipulated to be about 1.2 mW, we shall adopt a
conservative stance by setting W
2
= 6.2 m. Accordingly, our design uses L
1
= L
2
= 1 m,
W
2
= 6.2 m, and, in concert with our gain stipulations, W
1
= (6.2 m)(25) = 155 m. The
resultant simulated static transfer characteristic, which is provided in Figure (4.11) shows that
reasonable I/O linearity is manifested when 562 mV s V
i
s 850 mV, whose center point
corresponds to an input port biasing requirement of V
iQ
= V
gg
= 706 mV. At this input port
Output
Voltage, V
o
Input
Voltage, V
i
V
omax
V
ho
V
imax
V
omin
M1 Cutoff
M
1

S
a
t
u
r
a
t
e
d
M
1

O
h
m
ic
1 1
v
2 2
W L
Slope = A =
W L
V
iQ
V
oQ
0

- 342 -
operating point, which corresponds to an output port operating point of about V
oQ
= 1.25 V,
HSPICE further confirms a standby circuit power dissipation of 1.16 mW, which satisfies the
quoted circuit dissipation target.

Figure (4.11). Simulated static transfer response of the common source amplifier addressed in
Example #4.2 The voltages, V
iQ
and V
oQ
, respectively define the input and
corresponding output quiescent operating points that permit maximal signal swing in
the operating region where I/O linearity ostensibly prevails.
(3). The slope of the simulated transfer characteristic in the immediate neighborhood of the out-
put port quiescent operating point is measured to be 5.77 volts/volt, which differs from the
expected slope, or voltage gain value, of 5 volts/volt by approximately 15.4%.
While the general shape of the simulated static transfer characteristic fundamentally mirrors
the theoretic predilections advanced in Figure (4.10), there are notable discrepancies. These
differences can best be appreciated subsequent to our delving into the concepts that derive
from more advanced modeling measures. Meanwhile, we should nonetheless be mindful of
said differences because the performance estimates we deduce in most first order design ven-
tures are largely premised on simple, and thus more mathematically tractable and
understandable, transistor models. In other words, we should get used to discrepancies be-
tween necessarily first order manual, analytical predictions and inherently higher order
simulated results.
An obvious difference between simulated and theoretic results is the observed transfer
characteristic for a small input port voltage, V
i
. In particular, our theoretic results predict the
response to be a constant, with a value of (V
dd
V
ho
), whenever V
i
< V
ho
. In other words, our
analysis infers zero voltage gain to signal swings that confine the input port voltage to a value
smaller than threshold potential. In contrast, the simulated characteristic in Figure (4.11)
projects a monotonically decreasing output voltage response for small V
i
. To be sure, the
gain magnitude in this region, which is determined by the magnitude of the response slope, is
noticeably smaller than the magnitude of the slope (gain) evidenced in the linear region. But
said slope is assuredly nonzero. The difference in question is precipitated by two assump-
tions we enforced in the course of our manual analyses. The first of these is our tacit neglect
of subthreshold phenomena. Transistors operating in subthreshold domains can deliver at
least limited gains, particularly when relatively large gate aspect ratios are used in the com-
0
0.5
1.0
1.5
2.0
2.5
3.0
0 0.4 0.8 1.2 1.6 2.0
Input Port Voltage, (V) V
i
O
u
t
p
u
t

P
o
r
t

V
o
l
t
a
g
e
,

(
V
)
V
o
V =
706 mV
iQ
V =
1.25 V
oQ
Input Port
Linear Range
Output Port
Linear Range

- 343 -
mon source driver. The second, and invariably dominant, presumption contributing to
analytical errors for V
i
< V
ho
is our tacit neglect of BITM. To be sure, there is no body effect
experienced by transistor M1 in Figure (4.9), but substantial body phenomena is produced in
transistor M2, especially if the quiescent output port voltage is relatively large. For example,
HSPICE simulations show that the threshold voltage of transistor M1 in Figure (4.9) is 560
mV, while the threshold voltage indigenous to transistor M2 is 715 mV. Thus, the V
ho
used in
determining the output level, (V
dd
V
ho
), is not a constant; instead, it is a voltage that mod-
ulates as a nonlinear function of the output voltage, V
o
.
A final noteworthy point is that despite our I/O linearity prediction over the voltage range at
the input port of V
ho
s V
i
s V
imax
, perfect linearity can never be obtained because of numerous
higher order device effects that have yet to enter our modeling culture. These phenomena,
many of which we shall address shortly, include carrier mobility degradation incurred by ap-
plied drain-source voltage, carrier mobility degradation caused by applied gate-source vol-
tage, carrier velocity saturation (which is particularly evident in deep submicron technolo-
gies), CLM and DIBL. Nonzero body effect, DIBL, and other esoteric phenomena in
transistor M2 likely contribute to a simulated gain that is larger than the theoretically pre-
dicted value.
4.4.3. BALANCED DIFFERENTIAL AMPLIFIER
Our third demonstration of Schichman-Hodges model utility focuses on the balanced
differential amplifier, or balanced differential pair, which we depict in Figure (4.12). The two
transistors in this amplifier are identical, inclusive of their gate aspect ratios. Identical resis-
tances R act as passive loads in the transistor drain circuits. While the bulk terminals of the
transistors are not explicitly shown, they are, in fact, connected to circuit ground
4
. Accordingly,
identical body effects prevail in both devices in that voltage V
k
, which is sustained across the
ideal constant tail current, I
k
, is developed respect to ground at both of the transistor source
terminals. This tail current voltage serves to establish a reverse bias of (V
k
) across the bulk-
source junctions of each transistor. The architecture is similar to that of the amplifier in Figure
(4.7) with the exception that the source terminals of the transistors considered herewith are not
grounded. Instead, these source terminals are returned to circuit ground via the tail branch that
sinks the drain currents of both MOSFET devices to ground. In contrast to the situation prevail-
ing in the amplifier of Figure (4.7), we shall see that this architectural modification renders the
differential output voltage response, V
do
, ideally independent of noise or other extraneous
changes, AV
ci
, which may be introduced in the common mode biasing voltage, V
ciQ
.
In order to ensure our understanding of the alleged output response insensitivity to
changes in the common mode input voltage, assume first a zero differential input signal (V
di
= 0)
and AV
ci
= 0 so that
ciQ gs1Q k gs2Q k
V V V V V . = + = + (4-75)
This relationship clearly enforces V
gs1Q
V
gs2Q
. To the extent that saturated transistor drain cur-
rents are almost exclusively determined by applied gate-source voltages, the equality between
the quiescent gate-source voltages applied to the two transistors, coupled with the identical
physical and geometrical natures of transistors M1 and M2, means that equal quiescent drain cur-
rents prevail; that is, I
d1Q
I
d2Q
. Since both transistor drain currents sum to the constant tail cur-
rent, I
k
, we logically conclude that I
d1Q
I
d2Q
= I
k
/2.

4
In general, if transistor bulk connections are not delineated explicitly, we shall presume that these bulk terminals
are connected to a node that offers the lowest potential in the circuit in which the subject transistors are embedded.

- 344 -

Figure (4.12). Basic schematic diagram of a balanced differential amplifier. The
two transistors are identical, inclusive of their respective gate aspect
ratios. Although not explicitly shown, the bulk terminals of each de-
vice are connected to circuit ground.
Now, let us sustain the zero input differential signal condition while allowing the com-
mon mode input biasing voltage to change by the indicated amount of AV
ci
. Accordingly, (4-75)
gives
ci gs1 k gs2 k
V V V V V . = + = + (4-76)
The voltage changes, AV
gs1
and AV
gs2
, are zero in view of the fact that any change in the gate-
source voltage of either transistor manifests a change in the corresponding drain current. But
fluctuations in the quiescent drain currents are resolutely disallowed by the constant tail current.
Thus, the change, AV
ci
, in common mode input voltage necessarily produces a mirrored change,
AV
k
, in the voltage appearing across the current sink. If the current sink emulates an idealized
current branch in the sense of presenting an infinitely large dynamic resistance across its terminal
pairs, a nonzero AV
k
cannot alter the observed current, I
k
. We are therefore assured that despite
nonzero AV
ci
, each drain current remains clamped to I
k
/2. It follows that if I
d1
= I
d2
= I
k
/2, the
differential output voltage, V
do
, remains null; that is, the circuit fails to respond to the changing
common mode input voltage. In the jargon of differential circuit technology, we say that the am-
plifier before us rejects common mode input voltage changes and that the network offers infi-
nitely large common mode rejection. High rejection is a laudable attribute when nonzero AV
ci
is
manifested by poor power bus regulation and/or noise or other spurious signals that couple
parasitically to the bus line from which common mode voltage V
ci
is generated.
Let us now examine the effect of an applied nonzero differential input voltage, V
di
. We
note that V
di
> 0 elevates the gate-source voltage of transistor M1 and simultaneously, it de-
creases the gate-source voltage of M2 by the same amount. Consequently, the drain current, I
d1
,
+
V
ciQ

M1 M2
V /2
di
V /2
di
I
d1
I
d2
R R
+V
dd
+ V
do
I
k
V
i1
V
i2
V
k
+
V
ci

- 345 -
which flows through M1 increases. In contrast, drain current I
d2
in transistor M2 decreases by
the same amount as the increase in I
d1
. This seesaw balance preserves the Kirchhoff current
identity,
d1 d2 k
I I I , + = (4-77)
which is to say that in light of constant I
k
, an increase in I
d1
must be accompanied by a matched
decrease in current I
d2
, and vice versa.
From Figure (4.12) we have
( ) ( )
di gs1 gs2 gs1 h gs2 h
V V V V V V V , = = (4-78)
where V
h
is the effective threshold voltage (with due account made of BITM) of each of the two
transistors. Moreover, the differential output current, I
do
, is
( ) ( )
( )
2 2
do d1 d2 n gs1 h gs2 h
n gs1 gs2 h di
I I I V V V V
V V 2V V ,
(
= =
(

= +
(4-79)
where we have used (4-78) and have exploited (4-40) for the transistor volt-ampere characteristic
in saturation. Now, subsequent to appealing once again to (4-40),
( ) ( ) ( )
gs1 gs2 h gs1 h gs2 h d1 d 2
n
1
V V 2V V V V V I I ,
+ = + = + (4-80)
which gives
( )
2
k d1 d2
gs1 gs2 h
n
I 2 I I
V V 2V .
+
+ = (4-81)
Recalling (4-78),
( ) ( ) ( )( )
2
2
d1 d 2
gs1 h gs2 h gs1 h gs2 h
di
n n
k d1 d 2
n
I I
V V V V V 2 V V V V

I 2 I I
,
(
= = +

=
(4-82)
If this result is combined with (4-81), we find that
2
k n
k d1 d 2 di
gs1 gs2 h
n n
2I V
I 2 I I
V V 2V ,

+
+ = = (4-83)
whereupon (4-79) is expressible as
2 2
k n n
di di
do n di n k di
n k
2I V V
I V 2 I 1 V .
2I
| | | |
| |
= =
| |
| |
\ . \ .
(4-84)
Equation (4-84) relates the differential drain current exclusively to transistor parameter |
n
, tail
current I
k
, and differential input voltage V
di
.
In contrast to the observed performance of the grounded source differential amplifier of
Figure (4.7), (4-84) shows that the differential drain current, I
do
, is not a linear function of the
applied differential input signal, V
di
. Evidently, the price paid for high common mode rejection,
which the former (linear) differential amplifier cannot boast, is I/O nonlinearity. However, it ap-
pears that the subject output current can be rendered approximately linear with V
di
if tail current

- 346 -
I
k
is chosen sufficiently large. Although
2
n
di
k
V
I ,
2
>> (4-85)
distressingly implies increased circuit power dissipation, it gives rise to a differential output cur-
rent expression in (4-84) that collapses to the approximate result,
2 2
n n
di di
do n k di n k di n k di
k k
V V
I 2 I 1 V 2 I 1 V 2 I V .
2I 4I
| |
| |
|
|
= = ~
|
|
|
\ .
\ .
(4-86)
Since |
n
and I
k
are constants, the last result evokes an approximate linear dependence of I
do
on
V
di
. It follows that (4-85) produces a differential voltage gain, A
dv
A V
do
/V
di
, which is virtually
independent of the differential input signal, V
di
. This contention follows immediately from the
observation that since V
do
= R(I
d1
I
d2
) = RI
do
,
2
n
di do
dv n k n k
di k
V
V
A R 2 I 1 R 2 I .
V 2I
| |
|
= ~
|
|
\ .
(4-87)
In light of the foregoing analyses, we conclude that the Schichman-Hodges MOSFET
model predicts that the differential amplifier in Figure (4.12) is capable of producing a differen-
tial output voltage response that is ideally independent of common mode input voltage perturba-
tions. Of course, both transistors in the amplifier must operate in their saturation regimes for all
values net input voltage. For a sufficiently large tail current, the voltage response is also an
approximately linear function of the applied differential input signal. While (4-85) establishes
the linearity condition that precipitates (4-87), both of these relationships can be placed in a bet-
ter engineering perspective that promotes enhanced design comprehension.
To the foregoing end, recall from our earlier bipolar work that the forward transconduc-
tance of any transistor is the partial derivative of its output current (in this case the transistor
drain current) with respect to the controlling input voltage (in this case the gate-source voltage).
For either transistor M1 or M2, the transconductance, g
m
, at the transistor operating point estab-
lished by quiescent drain circuits that are I
k
/2 is
( )
d
m n gs h n d n k
Q Q
gs
Q
I
g 2 V V 2 I 2 I ,
V
c
= = = =
c
(4-88)
where we have once again invoked (4-40) and have noted that the quiescent drain current of ei-
ther transistor in Figure (4.12) is one-half of the circuit tail current, I
k
. Additionally, we know
that the quiescent drain saturation voltage, V
dsatQ
, of either transistor is (V
gsQ
V
h
), whence
dQ
k
dsatQ gsQ h
n n
I
I
V V V .
2
= = = (4-89)
If (4-88) and (4-89) are combined with (4-87), we converge to the gain relationship,
2
2
n
di di
dv n k m
k dsatQ
V
V
A R 2 I 1 g R 1 .
2I 2V
| |
| |
|
= = |
|
|
|
\ .
\ .
(4-90)
The last result collapses to the elegantly simple gain result,

- 347 -
dv m
A g R ~ (4-91)
if the applied differential input signal is small enough to satisfy the constraint,
2
di
dsatQ
V
1 .
2V
| |
<< |
|
\ .
(4-92)
It should be understood that the inequality in (4-92) is equivalent to the linearity condition pro-
jected by (4-85). But (4-92) is a more understandable design condition in that it confirms our
suspicions that too large of an input signal swing inhibits the realization of a nominally linear
amplifier response. We see that for a given differential input signal, the drain saturation voltage
must be sufficiently large, which requires a correspondingly large quiescent gate-source voltage.
In turn, a large quiescent drain current manifests a large circuit tail current. Everything checks
out both intuitively and in an engineering sense.
EXAMPLE #4.3:
The differential amplifier in Figure (4.12) is to be designed so that it dissipates no more
than 10 mW of standby power when a power supply voltage, V
dd
, of 3.3 volts is used.
The quiescent voltage at either of the drain output ports is to be two-thirds of the supply
line voltage, while the differential voltage gain produced by the amplifier is to be 10 dB.
If device nonlinearities are to be precluded from reducing the nominal voltage gain by
no more than 5%, what is the maximum permissible amplitude of the applied differen-
tial input signal, V
di
?
SOLUTION #4.3:
(1). The standby power dissipation, P
diss
, in the circuit of Figure (4.12) is
( )
diss dd d1 d2
P V I I , = + (E3-1)
and since the two transistor drain currents must sum to the tail current, I
k
,
( )
diss dd d1 d2 dd k
P V I I V I . = + = (E3-2)
We are directed to ensure that P
diss
so that it does not exceed 10 mW when V
dd
= 3.3 volts.
Thus I
k
s 3.03 mA. We choose I
k
= 3 mA.
(2). If two-thirds of the supply voltage is to be dropped across each of the two drain output ports
under quiescent or standby conditions, one-third of this supply line potential, or 3.3 volts/3 =
1.1 volts, must appear across each of the drain circuit resistances, R. Because the differential
pair is a balanced circuit architecture, I
d1
= I
d2
= I
k
/2 = 3 mA/2 = 1.5 mA at standby. It fol-
lows that the requisite drain circuit resistance is R = 1.1 volts/1.5 mA = 733.3 .
(3). A gain of 10 dB equates to a differential voltage gain magnitude, |A
d
|, of 10
10/20
= 3.162
volts/volt. From (4-90) and (4-91), this gain, in the absence of distortion phenomena
spawned by excessive differential input voltages, is A
d
= g
m
R. With A
d
= 3.162 volts/volt and
R = 733.3 O, we see that each transistor must deliver a forward transconductance, g
m
, of g
m
=
4.312 mmho. Recalling (4-86), this requirement translates to a transconductance parameter,
|
n
of |
n
= 3.099 mmho/volt.
(4). Using (4-89), the drain saturation voltage, V
dsatQ
, of each transistor at the quiescent operating
condition is V
dsatQ
= 695.7 mV. This calculation underpins a determination of the allowable
differential input signal amplitude. In particular, if nonlinearities caused by large differential
inputs are to degrade the idealized (strictly linear) voltage gain of g
m
R = 3.162 volts/volt by
no more than 5%, (4-90) stipulates the constraint,

- 348 -
2
di
dsatQ
V
1 0.95 ,
2V
| |
> |
|
\ .
(E3-3)
which in turn implies
di
dsatQ
V
0.3122 .
2V
| |
s |
|
\ .
(E3-4)
With V
dsatQ
= 695.7 mV, we conclude that V
di
must be restricted to V
di
s 434.5 mV.
We should interject that in the majority of electronic circuit applications, an input signal
amplitude in the neighborhood of 435 mV is not an extreme limitation. Indeed, an input sig-
nal in the range of hundreds of millivolts is generally viewed as robust. Of course, many
other applications, particularly in the communication systems arena, may are more demand-
ing than a 5% deviation from ideal, linear voltage gain.
Recall that the quiescent voltage across the drain output ports is stipulated to be two-thirds of
the value of the supply line voltage. This requirement is reasonable in that the power line
voltage must supply energy to three branch entities in the circuit of Figure (4.12). These
three entities are the drain circuit resistance, R, the drain-source terminals of each MOSFET,
and the current sink, I
k
. In the absence of other relevant information, it is reasonable to stipu-
late that the power line voltage be partitioned equally among these three electrical branches.
4.4.4. GILBERT MULTIPLIER
Our final demonstration of Schichman-Hodges model utility builds on our experiences
in conjunction with the balanced differential pair to address the Gilbert multiplier, which is
ubiquitous in modern communication systems. The Gilbert cell, whose basic schematic diagram
appears in Figure (4.13), is formed of three interconnected balanced differential pairs
[7],[8]
. All
transistors in the multiplier cell generally operate in their saturation regimes although in some
cell applications that require very low distortion levels, transistors M3 through M6, which are
featured in the upper quad array, are commonly may be operated in their ohmic regimes. While
transistor bulk terminals are not specifically highlighted in the subject schematic diagram, they
are all returned to circuit ground, which is the lowest circuit potential in the indicated multiplier
architecture. The inputs to the analog multiplier are the differential voltages, V
x
and V
y
, while the
output response is taken as the differential voltage, V
do
. With the help of Schichman and
Hodges, we shall show that ideally,
do g x y
V K V V , = (4-93)
where K
g
is akin to a gain metric that is functionally dependent on circuit and transistor parame-
ters. In other words, the idealized output response to the two applied differential input signals,
V
x
and V
y
, is proportional to the product of the two differential inputs. Because (4-93) applies to
any positive or negative input voltages, the Gilbert multiplier in Figure (4.13) is often referenced
as a four-quadrant multiplier. In other words, (4-93) is valid for all four possible positive and
negative combinations of differential voltages V
x
and V
y
.
In the analysis we document below, the bottom two transistors, M1 and M2, to which
we assign transconductance coefficient |
x
, are matched transistors. Similarly, the quad array
comprised of transistors M3 through M6, are matched devices, although these transistors need
not be matched to transistors M1 and M2. These four devices are assigned a transconductance
coefficient of |
y
. We shall also presume that the differential input signals, V
x
and V
y
, derive from

- 349 -
the single-ended excitations
5
, V
x1
, V
x2
, V
y1
, and V
y2
, such that

Figure (4.13).Basic schematic diagram of a Gilbert, four-quadrant multiplier. The
substrate bulk terminals of all transistors, while not shown explicitly, are all re-
turned to circuit ground.
x
x1 xc
x
x2 xc
V
V V
2
,
V
V V
2
= +
=
(4-94)
and
y
y1 yc
y
y2 yc
V
V V
2
,
V
V V
2
= +
=
(4-95)

5
A single-ended voltage at a particular circuit node is the voltage developed at the subject node with respect to
circuit ground.
M3
M1
M5 M4 M6
+
V
y
M2
+
V
x
I
k
V
k
I
s1
I
d3
I
a
I
d5
I
d4
I
d6
V
s1
I
s2
V
s2
V
ds
+
V
y1
V
a1
V
y2
V
x1
V
x2
R
l
R
l
I
b
V
do
+ V
a2
+V
dd

- 350 -
do
a1 ac
do
a2 ac
V
V V
2
.
V
V V
2
= +
=
(4-96)
In (4-93), V
xc
represents the common mode signal applied to the lower differential pair com-
prised of transistors M1 and M2. Similarly, voltage V
yc
in (4-95) is the common mode input sig-
nal pertinent to the upper quad array formed of transistors M3 through M6. Finally, V
ac
is the
common mode component of the single-ended voltage responses developed at the drain terminals
of transistors M3 and M6.
4.4.4.1. Circuit Analysis and Assessment
We may borrow directly from our balanced differential amplifier experience to write
for the differential current response of the M1-M2 balanced pair,
2
x x
s1 s2 x x k
k
V
I I V 2 I 1 .
2I
=
|
| (4-97)
If we presume that the nonlinearity underscored by this expression is weak in the sense that |
x
V
x
2

is substantively smaller than 2I
k
,
2 2
x x x x
s1 s2 x x k x x k
k k
V V
I I V 2 I 1 V 2 I 1 .
2I 4I
| |
|
= ~
|
|
\ .
| |
| | (4-98)
We recognize that I
s1
and I
s2
function individually as the tail currents for the M3-M4 differential
pair and the M5-M6 pair, respectively. It therefore follows from our previously assimilated
understanding of the current responses of a balanced differential pair that
2 2
y y y y
d3 d4 y y s1 y y s1
s1 s1
V V
I I V 2 I 1 V 2 I 1 ,
2I 4I
| |
|
= ~
|
|
\ .
| |
| | (4-99)
and
2 2
y y y y
d6 d5 y y s2 y y s2
s2 s2
V V
I I V 2 I 1 V 2 I 1 ,
2I 4I
| |
| |
| |
|
= ~
|
|
\ .
(4-100)
where |
y
V
y
2
is presumed to be much smaller than the doubled M1 and M2 drain currents, 2I
s1
and
2I
s2
, respectively.
Returning to the schematic diagram in Figure (4.13), the differential output current, I
do
,
is seen as
( ) ( )
do a b d3 d4 d6 d5
I I I I I I I , = = (4-101)
and by (4-99) and (4-100),

- 351 -
2
y y
do y y s1 s2
s2 s1
V
1 1
I V 2 I I .
4 I I
|
|
( | |
| |
( |
|
~ +
( |
|
|
(
\ .
\ .
(4-102)
This rather awkward relationship can be couched into a more design-friendly form by noting that
since transistors M1 and M2 operate in saturation, their respective drain currents, I
s1
and I
s2
, are
given by
( )
( )
2
s1 x gs1 h
2
s2 x gs2 h
I V V
,
I V V
=
=
|
|
(4-103)
where V
h
denotes the threshold voltage of each transistor. Voltages V
gs1
and V
gs2
are, of course,
the gate-source voltages applied to transistors M1 and M2, respectively. Since the differential
input voltage, V
x
, in Figure (4.13) is little more than the gate-source voltage difference (V
gs1

V
gs2
),
( ) ( )
s1 s2 x gs1 h gs2 h x x
I I V V V V V .
(
= =
(

| | (4-104)
Additionally, we can borrow from (4-82) to write
2
k x x
s1 s2
I V
I I .
2
=
|
(4-105)
If we persevere despite the algebraic hardship that ensues when the last two expressions are
substituted into (4-102), we can ultimately proffer the relationship,
2
y y
x x
do x y x y
k
2
x x
V
2 V
I V V 2 1 .
I
1
V
|
|
| |
|
(
| || |
(
| |
(
| |
\ .\ .
(
~ +
(
(
(
(

(4-106)
Since the differential output voltage response, V
do
, is R
l
(I
a
I
b
) = R
l
I
do
,
( )
2
y y
x x
do l do x y l x y
k
2
x x
g x y x y
V
2 V
V R I V V R 2 1
I
1
V
K V V 1 V , V .
|
|
| |
|
u
(
| || |
(
| |
(
| |
\ .\ . (
~ = +
(
(
(
(

(
= +
(

(4-107)
where the gain metric, K
g
, is
g l x y
K R 2 . | | = (4-108)
The term, K
g
V
x
V
y
, in (4-107) is the desired or idealized multiplier output voltage re-
sponse defined by (4-91). It follows that the bracketed term on the right hand side of (4-105)

- 352 -
represents a departure from this idealized design target. Accordingly, (V
x
, V
y
), which is given
analytically by
( )
2
y y
x x
x y
k
2
x x
V
2 V
V , V ,
I
1
V
|
|
u
|
| || |
| |
| |
\ .\ .
=
(4-109)
represents an error term whose minimization is a design priority. Since we have already pre-
sumed that tail current I
k
is large in comparison to 2V
x
2
, a constraint that minimizes distortion in
the bottom balanced pair comprised of transistors M1 and M2, we can reduce (4-109) to the
simpler form,
( )
2
y y
2
y y x x
x y
k
k
2
x x
V
V 2 V
V , V ,
I
2I
1
V
|
| |
u
|
| || |
| |
| |
\ .\ .
= ~
(4-110)
The minimization of the foregoing error term requires adoption of at least one of the
following three engineering strategies. First, |
y
should be relatively small (and possibly much
smaller than |
x
), which is to say that the gate aspect ratios in the transistor quad, M3 through M6,
must be small. Second, the amplitude of differential signal V
y
, which is applied to the upper
transistor quad, should be kept small, and perhaps significantly smaller than voltage V
x
. In tradi-
tional communication system applications, V
y
routinely derives as the relatively small radio fre-
quency (RF) input signal that is identified for processing, while V
x
is usually the relatively larger
output voltage of a local oscillator used to tune the RF communication channel. Finally, twice
the tail current, 2I
k
, must be selected to be significantly larger than the effective signal current
|
y
V
y
2
. In addition to minimizing the distortion evidenced in the bottom balanced pair, a large tail
current serves to foster low distortion in the upper quad array of transistors.
4.4.4.2. Voltage-Controlled Differential Amplifier
Yet another application of the Gilbert configuration shown in Figure (4.13) is that of an
amplifier whose I/O gain is adjustable. This adjustment can be effected either automatically or
manually by setting a static voltage, say V
c
, which is applied to the amplification network. In
this case and as we depict in Figure (4.14), the input signal is applied differentially to the lower
differential pair, while control voltage V
c
derives as V
y
, which we continue applying to the upper
quad array of transistors. Then, if we exercise design care to ensure that the error term in (4-110)
is negligibly small, (4-107) prescribes
do g x c
V K V V . ~ (4-111)
The I/O differential voltage gain, V
do
/V
x
, implied by this simple relationship is
do
g c
x
V
K V ,
V
= (4-112)
whose gain magnitude value is linearly proportional to the differentially applied control voltage,

- 353 -
V
c
. We note zero gain, corresponding to an electronic removal of the amplifier, occurs when V
c

= 0. This result is reasonable in view of the fact that V
c
= 0 is tantamount to applying identical
gate-source voltages to each of the transistors in the upper quad of Figure (4.14). In turn, iden-
tical gate-source voltages spell identical transistor drain currents that result in identical currents
flowing through the circuit load resistances, R
l
. Hence, zero differential output voltage and thus,
zero differential voltage gain, ensues.

Figure (4.14).Basic schematic diagram of a Gilbert, four-quadrant cell that is configured as an am-
plifier featuring voltage-controlled gain adjustment.
4.5.0. REFINEMENTS TO THE STATIC MODEL
As demonstrated in the preceding section of material, we shall use the static volt-am-
pere characteristics in (4-40) and (4-42), or slightly modified versions thereof, in most of our
first order, low frequency, manual analyses. Such analyses, which serve only as a precursor to
far more definitive computer-aided studies of analog MOSFET circuits, establish a sturdy
foundation for developing and executing creative design strategies. To be sure, the use of ma-
nually deduced relationships is likely to incur errors between computed and experimentally
measured or simulated characteristics of deep submicron MOSFETs. These analytical shortfalls
compel the aforementioned follow-up computer-aided analyses that embrace a variety of higher
order, short channel effects. The principle sources of these short channel phenomena are channel
length modulation (CLM), two types of carrier mobility degradation, and drain-induced barrier
M3
M1
M5 M4 M6
+
V
y
M2
+
V
x
I
k
V
k
I
s1
I
d3
I
a
I
d5
I
d4
I
d6
V
s1
I
s2
V
s2
V
ds
+
V
y1
V
a1
V
y2
V
x1
V
x2
R
l
R
l
I
b
V
do
+ V
a2
+V
dd

V
c
2
V
c
2
V
yc
G
a
i
n

C
o
n
t
r
o
l
l
e
r

- 354 -
loading (DIBL).
4.5.1. CHANNEL LENGTH MODULATION
As we have already noted, MOSFETs deployed in analog circuits usually operate in
their saturation regime where for NMOS, V
gs
V
h
and V
ds
(V
gs
V
h
). In saturation, the oxide-
bulk interface near the source site is strongly inverted when the threshold condition, V
gs
> V
h
, is
satisfied. We therefore surmise that the source end of the channel has a plentiful concentration
of free electrons, which establishes a foundation for drain current flow when a positive drain-
source voltage is applied. But since the drain-source voltage is such that V
ds
(V
gs
V
h
), which
implies a gate-drain voltage, V
gd
, satisfying V
gd
V
h
, the drain end of the interfacial channel is
either pinched off (when V
gd
V
h
) or is depleted (if V
gd
< V
h
).
It is important to understand that the charge condition typified in the saturation region
contrasts sharply with the charge profile observed in the ohmic regime. In the ohmic region,
where both gate-source and gate-drain voltages exceed threshold level, an inversion condition
prevails throughout the interfacial channel spacing that separates the source and drain volumes.
This inverted channel effectively establishes an electrical conduit between the source and drain
volumes. Said conduit supports the flow of drain current, for drain current relies on the source to
drain drift of free electrons that is manifested in response to the application of a positive drain-
source voltage. But in saturation where a gate-drain voltage can be smaller than threshold poten-
tial, the aforementioned channel inversion prevails only near the source volume. In other words,
the source to drain conduit containing free electrons is broken, thereby begetting questions as to
how electrons can be transported throughout the source to drain spacing to sustain drain current
conduction. The answers derive from something we learned when we studied the physical
electronics implicit to a PN junction diode. In particular, we learned that electron transport is, in
general, the superposition of drift and diffusion components. However, Shichman and Hodges
considered only drift mechanisms in their formulation of the MOSFET I-V characteristics. To
be sure, electron drift mechanisms dominate in the ohmic region, but drift transport condescends
to significant electron flow by diffusion mechanisms in saturation domains.
To first order, the drain current in saturation for an NMOS device is the drain saturation
current given by (4-36), which is independent of the drain-source voltage, V
ds
; that is,
( ) ( )
2
n
d gs h dsat gs h ds gs h
K W
I V V I for V V , & V V V .
2 L
| |
= > >
|
\ .
(4-113)
The logic that underpins this approximate volt-ampere relationship is that the drain current in the
entire saturation domain is limited by the surface electron concentration established by the drain-
source voltage, V
ds
= (V
gs
V
h
) = V
dsat
. But this drain-source voltage barely supports an inverted
interface that spans the entire source-drain channel spacing. Any increase in the drain-source
voltage above its saturated value, V
dsat
, arguably adds impetus (not embodied by this expression)
to the attractive force exerted on inversion layer electrons by the lateral electric field promoted
by the applied drain-source voltage.
We now comprehend that a problem with (4-113) is its implicit presumption of an elec-
tron inversion layer whose length is identical to the geometric channel length, L. The latter is
often termed the drawn channel length. If V
ds
is set to the drain saturation voltage, V
dsat
, pinch
off is incurred precisely at the drain site; that is, the inversion layer depth is reduced to zero at
the drain site where V
gd
is precisely the threshold potential, V
h
. As illustrated in Figure (4.15a),
the inversion layer and geometric channel lengths are indeed identical under this pinch off

- 355 -
circumstance. But when the transistor operates deeper in its saturation domain where V
ds
> V
dsat
,
pinch off is necessarily achieved within the source-drain spacing, as we suggest in Figure
(4.15b). We now perceive an effective channel length over which free charge carriers (electrons
in the NMOS case) can drift in response to positive drain-source voltage as reduced from L to (L
L). In the subject figure, note that the reduced inversion layer length supports the drain
saturation voltage, V
dsat
, thereby allowing the excess drain voltage, (V
ds
V
dsat
), to be developed
across the depleted region that intervenes the channel pinch off point and the drain site. Make no
mistake that this intervening region is a depletion zone, for the lack of bulk inversion bodes an
absence of free charge carriers (electrons in this case) therein.
Figure (4.15) serves as road map for supporting our earlier drift-diffusion arguments.
Specifically, if the inverted channel region is uniform throughout the source and drain spacing,
as it is for zero or even small drain-source voltages, V
ds
, electron transport from source to drain is
predominantly governed by drift physics. As V
ds
increases, gate-drain voltage V
gd
decreases, the-
reby diminishing the depth of the inversion layer at the drain volume. For V
ds
> 0, electrons con-
tinue to flow via drift mechanisms through the inverted portion of the channel. For those elec-
trons that hover near the oxide-semiconductor interface, the conduction mechanism is
exclusively drift. But those electrons that are transported at a deeper depth within the inverted
channel drift only as far the lower boundary of the effective inverted wedge resulting from posi-
tive V
ds
. The electrons that arrive at this boundary witness the lateral electric field (in the direc-
tion of drain volume to source volume) that arises from V
ds
> 0. The force imparted to the elec-
trons that stampede to the lower edge of the inversion wedge serves to attract them via diffusion
mechanisms across the depletion region observed between inversion layer boundary and drain
volume. Accordingly, the observed net drain current is literally the superposition of drift
(through the inversion wedge) and diffusion (across the inversion boundary-drain volume)
components. As V
ds
continues to increase, the inversion layer length shortens thereby reducing
the drift component constituent of drain current in favor of an increased diffusion component.
Let us now return to the circuit level implications of a shrinking inversion layer length.
Since the saturation domain drain current in (4-113) is predicated on the presumption of equality
between the inversion layer and geometric channel lengths, its application to the case of V
ds
>
V
dsat
must reflect an actual inversion layer length of (L AL), as opposed to merely L. Thus, we
reason that (4-113) must be supplanted by
( )
2
n
d gs h dsat
K W L
I V V I .
2 L L L L
| | | |
= =
| |

\ . \ .
(4-114)
Although an expression for the voltage-induced decrease, AL, in channel length can be
deduced in terms of transistor voltages and various physical transistor parameters, rendering this
expression practical for circuit analysis and design environments is a challenging undertaking.
For most MOSFET applications, a practical empirical expression is
[9]

ds dsat
V V L
1 ,
L L V
~ +
(4-115)
where V
, termed the channel length modulation voltage

6
, is given by the semi-empirical expres-
sion,

6
Many HSPICE and other SPICE simulators use a channel length parameter to compute the degree to which the
drain-source voltage affects the drain saturation current. This channel length parameter, , is = 1/V
.

- 356 -

Figure (4.15). (a). Cross section of an n-channel MOSFET operated in strong inversion with V
ds
=
V
dsat
. (b). Cross section of the MOSFET in (a) operated with V
ds
> V
dsat
. The diagrams
are not drawn to scale.
( )
2
j
T ds dsat j
b F
V
L
V 32 V V V V .
D V
| | | |
= +
| |
|
\ .\ .
(4-116)
In (4-116), V
T
is the familiar thermal voltage, D
b
is the electron Debye, or screening, length,
N
+
S
o
u
r
c
e
N
+
D
r
a
i
n
P-Type
Substrate
S G D
B
Silicon Dioxide

V > V
gs h
V = V
gd h
V = V
ds dsat
V 0
bs
s
Depletion
Layer, V > 0
ds
I
d
Oxide
Electric Field
V
ox
+
y = Y
d
y = 0
x
x = 0 x = L
V
d
s
a
t
+
+

(a).
N
+
S
o
u
r
c
e
N
+
D
r
a
i
n
P-Type
Substrate
S G D
B
Silicon Dioxide

V > V
gs h
V = V
gd h
V > V
ds dsat
V 0
bs
s
Depletion
Layer, V > 0
ds
I
d
Oxide
Electric Field
V
ox
+
y = Y
d
y = 0
x
x = 0 x = L
V
d
s
a
t
V
V
d
s
d
s
a
t
-
+
+

(b).
+
L L A

- 357 -
s T
b
A
V
D ,
qN
c
= (4-117)
and V
j
is the built-in potential of the bulk-drain PN junction. The Debye length is essentially the
radius of the observable electric field established by an electron due to electron charge. For vol-
tage V
j
,
A D
j T
2
i
N N
V V .
n
ln
| |
|
=
|
\ .
(4-118)
In the last expression N
A
, N
D
, and n
i
respectively denote the average impurity concentration in
the bulk substrate, the average impurity concentration in the drain and source implants, and the
intrinsic carrier concentration of silicon. Equation (4-116) delivers acceptable analytical accu-
racy for deep submicron channel lengths and drain-source voltages that are well within break-
down ratings of the considered transistor. We note that for large channel lengths, L, the channel
length modulation voltage is proportionately large, which implies by (4-115) that the channel
length decrease, AL, approaches zero. In turn, small AL collapses the corrected drain current
expression in (4-114) to the elementary form provided in (4-113). This simplification of the
volt-ampere characteristics of a saturated MOSFET explains the common reference to (4-113) as
the long channel approximation of MOSFET drain current in the saturation domain.
We can now formulate the modified, short channel approximation, of the saturated
drain current as
( )
2
n ds dsat ds dsat
d gs h dsat

K V V V V W
I V V 1 I 1 ,
2 L V V
| | | |
| |
~ + = +
| | |
\ .
\ . \ .
(4-119)
where it is understood that the gate-source and drain-source voltages, V
gs
and V
ds
, respectively,
are constrained to the saturation domain requirements, V
gs
> V
h
and V
ds
(V
gs
V
h
) = V
dsat
. Un-
like the drain current that derives from the long channel approximation, the corrected saturation
regime drain current is dependent on the drain-source voltage. This dependence of the drain cur-
rent on progressive increases in the drain-source voltage reflects the increasing significance of
diffused electron transport. We see this current rising with V
ds
at a slope of I
dsat
/V
. For large V
,
which is manifested by a long transistor channel length, L, the voltage rate of current rise with
V
ds
is modest. Indeed, the slope of the current-voltage characteristic curve approaches zero in the
limit as V
approaches infinity.
These observations and (4-119) itself suggest that the drain-source port of a MOSFET
does not behave as an ideal constant current source whose value, I
dsat
, is controlled exclusively
by gate-source voltage V
gs
. Instead, the drain-source port is a practical gate-controlled current
source. We see this source as comprised of a constant current generator, albeit controlled by a
quadratic function of the gate-source voltage, V
gs
, appearing in shunt with a resistive branch. In
an attempt to add further clarification to this observation, we write (4-119) in the form,
ds dsat
d dsat
dsat
V V
I I ,
V I
~ + (4-120)
from which we deduce the static circuit model provided in Figure (4.16). As clever as it might
appear, this model is more useful conceptually than computationally since a change made to V
gs

for the purpose of adjusting the nominal drain current, I
dsat
, influences the resistance value,
V
/I
dsat
, and the voltage offset, V
dsat
, introduced in the drain-source port.

- 358 -

Figure (4.16). A large signal static circuit model for an n-channel MOSFET operating in its
saturation domain.
A complication of the channel length embellishment to the saturation drain current
expression is that (4-120) is discontinuous with the ohmic domain drain current expression in (4-
22) at the transition boundary between the ohmic and saturation domains. Simple software fixes
in commonly available circuit simulators nicely rectify this dilemma. From an analytical
perspective, the problem can be tacitly ignored, if V
in (4-116) abides by the previously dis-

closed voltage restrictions.
For the convenience of the reader, the relevant revised expressions for the volt-ampere
characteristic curves of an n-channel MOSFET are itemized in (4-121). In these relationships,
V
dsat
is the excess gate-source voltage, (V
gs
V
h
); equivalently, we recognize it as the drain
saturation voltage. We must remember that the positive reference direction of the drain current
in NMOS is a current flowing into the drain, while the positive reference voltage polarities re-
flect those highlighted in Figure (4.1). Moreover, we recall V
h
as a threshold potential dependent
on the bulk-source voltage, V
bs
, in accordance with (4-17) or (4-19).
In the interests of clarity and completeness, the PMOS counterpart to (4-121) is (4-
122), where in terms of the source-gate voltage, V
sg
, V
ssat
is now given by, (V
sg
V
h
). Moreover,
the threshold voltage, which is dependent on source-bulk potential V
sb
in (4-17), remains a posi-
tive number in accordance with our adopted modeling tack. The transconductance parameter K
p

is now the product of oxide capacitance density and hole mobility. The positive reference direc-
tion of the drain current in PMOS is a current flowing out of the drain, while the positive refer-
ence voltage polarities reflect those identified in Figure (4.2). And the relevant equations are:
( )
ds df
gs hf
V V
gs bs
ot hf gs h
T
ds
n ds gs h
d
gs h ds gs h
2
n
ds dsat
gs h
0, for V V
V V
W
I 1 , for V V V
L V
V
W
K V V V ,
L 2
I
for V V & V V V
K
V V
W
V V 1
2 L V
exp e
q

<
+ | |
| |
| |
|
s <
|
|
|
|
\ .
\ .
\ .
| |
| |
|
|
|
\ . =
\ .
> <
| |
| |
| +
|

\ .
\ .
(cutoff)
(subthreshold)
(ohmic)
gs h ds gs h
;
,
for V V & V V V
|
> > (saturation)
(4-121)

V
gs

V
bs

+V V
ds dsat
>
I
d
V /I
dsat
I
d
I
dsat
V
dsat

+V V
ds dsat
>

- 359 -
( )
sd df
sg hf
V V
sg sb
ot hf sg h
T
sd
p sd sg h
d
sg h sd sg h
2
p
sd ssat
sg h
0, for V V
V V
W
I 1 , for V V V
L V
V
W
K V V V ,
L 2
I
for V V & V V V
K
V V
W
V V 1
2 L V
exp e
q

<
+ | |
| |
| |
|
s <
|
|
|
|
\ .
\ .
\ .
| |
| |
|
|
|
\ . =
\ .
> <
| |
| |
| +
|

\ .
\ .
(cutoff)
(subthreshold)
(ohmic)
sg h sd sg h
.
,
for V V & V V V
|
> > (saturation)
(4-122)
EXAMPLE #4.4:
Consider an NMOS transistor for which the nominal channel length is 0.25 m,
the gate aspect ratio is 10, the oxide thickness is 50 , the average impurity
concentration in the bulk substrate is 10
15
atoms/cm
3
, and the average donor
concentration in the source and drain volumes is (5)(10
20
) atoms/cm
3
. With zero
bias applied to the bulk-source terminals, the threshold voltage is 650 mV, but
the transistor under investigation is operated with a bulk-source bias of 4.5
volts. Generate the static, common source volt-ampere characteristic curves,
which plot the drain current as a function of the drain-source voltage for several
values of the gate-source voltage. Assume an operating temperature of 27 C,
for which the electron mobility can be taken to be 450 cm
2
/volt-sec.
SOLUTION #4.4:
(1). We must make several background calculations to initiate the solution to this problem.
(a). At an operating temperature of 300.16 K, (4-7) yields a thermal voltage of V
T
= 25.89
mV.
(b). For an intrinsic carrier concentration of n
i
= (4.45)(10
10
) atoms/cm
3
and given the sub-
strate impurity concentration of N
A
= 10
15
atoms/cm
3
, (4-6) delivers a Fermi potential
of V
F
= 288.4 mV at an interfacial temperature of 300.16 K.
(c). Equation (4-117) yields a Debye length of D
b
= (12.95)(10
6
) cm. In this expression,
the dielectric constant, c
s
, of silicon is taken as c
s
= 1.05 pF/cm, while q = (1.6)(10
19
)
coulombs is the magnitude of electron charge.
(d). For a gate oxide thickness of T
ox
= 50 = (50)(10
8
) cm and an oxide dielectric con-
stant of c
ox
= 345 fF/cm, the density of the oxide capacitance is C
ox
= c
ox
/T
ox
= 690.0
nF/cm
2
.
(e). Given the foregoing computation of the oxide capacitance density, (4-8) can be used to
calculate V
u
= 348.5 V for the substrate body effect voltage.
(f). From (4-118) the built-in potential of the substrate-drain and substrate-source PN junc-
tions is V
j
= 917.0 mV.
(2). In view of an electron mobility of 450 cm
2
/volt-sec, (4-26) produces K
n
= 311 mho/volt for
the transconductance coefficient of the transistor. Accordingly, a gate aspect ratio of W/L =
10, yields K
n
(W/L) = 3.11 mmho/volt.

- 360 -
(3). With a bulk-source bias of V
bs
= 4.5 volts and a zero bias threshold voltage of V
ho
= 650 mV,
(4-17) offers an effective threshold voltage for the transistor of V
h
= 668.0 mV. In this case,
we see that the indicated substrate bias perturbs the zero bias value of the threshold voltage
by 2.77%.
(4). The channel length modulation voltage, V
, in (4-116), which is pertinent only to the satura-

tion operating regime of the transistor, is not a constant owing to its dependence on the drain-
source voltage, V
ds
, and the gate-source voltage V
gs
. The latter dependency arises from the
fact that V
dsat
= (V
gs
V
h
). For example, calculations confirm that for V
gs
= 4.5 volts, V
dsat
=
832 mV, and V
varies from 17.057 volts at V

ds
= 840 mV to 34.156 volts for V
ds
= 3 volts. On
the other hand V
gs
= 2.5 volts produces V
dsat
= 4.832 volts, with a resultant modulation vol-
tage variation of V
= 17.057 volts at V
ds
= 4.84 volts to V
= 25.612 volts at V
ds
= 3 volts.
Why is V
the same value, regardless of V

gs
, in the neighborhood of V
ds
= V
dsat
? The answer
to this query derives from (4-116), which confirms that V
in this voltage neighborhood is

dependent on only the junction built-in potential, V
j
, the thermal voltage, V
T
, the Fermi poten-
tial, V
F
, the electron Debye length, D
b
, and the transistor channel length, L. All of these me-
trics and parameters are invariant with transistor terminal voltages.

Figure (4.17). Common source volt-ampere characteristic curves for the NMOS
transistor considered in Example (4.4).
(5). In Figure (4.17) we plot the desired static characteristic curves, as per (4-121). In arriving at
these curves, the subthreshold regime is tacitly ignored in that it generates currents that are
barely discernible in a laboratory determination of the volt-ampere characteristics.
The characteristics curves displayed in Figure (4.17) barely render visible any discontinuities
at the transition boundary between ohmic and saturation operating regimes. The locus of this
boundary is also drawn on the plot. The latter curve derives from (4-115) when I
dsat
is re-
placed by I
d
and (V
gs
V
h
) is equated to V
ds
. Note as expected that the slope of the
characteristic curves in the saturation domain (to the right of the dashed boundary) no longer
project the zero slope predicted by the Schichman-Hodges long channel model.
4.5.2. LATERAL EFECTRIC FIELDS
The NMOS and PMOS volt-ampere characteristic equations in (4-40) and (4-42) are
predicated on several presumptions. One of the more notable of these presumptions is that the
velocity, say v
c
, of drifting carriers in the inverted source to drain channel is directly proportional
to the lateral electric field, E
x
. We understand, of course, that the lateral electric field pierces the
0
1
2
3
4
5
6
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
Drain-Source Voltage (V)
D
r
a
i
n

C
u
r
r
e
n
t

(
m
A
)
Vgs = 2.5
V
gs
= 2.0 V
Vgs = 1.5 V
V
gs
= 1.0 V
Transistion Locus:
Ohmic-Saturation
Transition Regions

- 361 -
channel in the direction of the drain volume to the source volume as a result of the applied, posi-
tive drain-source voltage, V
ds
, (in the case of NMOS) or applied source-drain voltage V
sd
(in the
case of PMOS). In other words, the simplified volt-ampere characteristics exploit the simplifica-
tion of constant, voltage-invariant, carrier mobility. Thus, the simplified MOSFET model in-
vokes
c o x
v E , ~ (4-123)
where
o
represents either the low field value of the electron mobility,
n
, in n-channel devices or
the low field value of the hole mobility,
p
, in PMOS. The absolute value operation on the right
hand side of (4-123) stems from the fact that the carrier velocity, which is always positive, is di-
rected against the direction of the channel field in NMOS. In the case of NMOS transistors,
carriers drift in the direction of the source to the drain, whereas the field induced by positive
drain-source voltage is vectored from drain to source and is therefore negative. For PMOS, no
algebraic sign problems surface, since carriers drift in the same direction as the lateral field, the-
reby yielding positive E
x
.
At least two analytical shortfalls beset (4-123). The first of these shortfalls is that the
low field mobility,
o
, in practical devices is not a constant. Instead, carrier mobility is a physi-
cal metric whose value depends on the intensity of the electric field that influences the mobile
charges in the inverted channel. An electric field imparts energy to free carriers that encourages
enhanced chaos with respect to their transport. In other words, the force exerted on charge carri-
ers by the electric field energizes these carriers to the point where their drift is a more frenzied,
and thus a less uniformly directed, drift from source to drain. The result is that when carriers
rambunctiously bounce around and off one another in the process of their source to drain drift,
their average mobility, which effectively measures the ability of a carrier to move through the
inverted channel, is compromised. In a word,
o
degrades with increasing field E
x
, which, in
turn, arises from an applied drain-source voltage. Logic alone dictates a more pronounced
degradation of mobility as a function of drain-source voltage for deep submicron channels, since
even relatively small voltages applied across deep submicron channels incur intense fields.
A second shortfall to (4-123) is that even if we accept the presumption of constant low-
field carrier mobility, which indeed is implicit to the Shichman-Hodges MOSFET model, the
carrier velocity, v
c
, cannot exceed its saturated limit value, v
max
. In silicon semiconductors, v
max

is of the order of 150 nM/pSEC. This velocity is achieved asymptotically for fields in excess of
the so-called critical electric field, E
c
, which is in the range of 3.5 V/m to 5 V/m (larger by
25% or so in PMOS) Using (4-123), we write
max o c
v E . = (4-124)
In light of the foregoing disclosures, we can now suggest that a more realistic formulation of the
constant mobility model is the piecewise linear representation,
x
o x max x c
c c
max x c
E
E v , for E E
E v .
v , for E E
| |
= s
|
=
\ .
>
(4-125)
The simplicity of (4-125) projects the notion that the carrier drift velocity increases li-
nearly with small electric fields. In fact, such a linear increase is observed at only very small
electric fields. Moreover, (4-125) does not clearly convey the inherent dependence of carrier
mobility on electric field intensity. To these ends, a more meaningful velocity-field empiricism,
which boasts the additional advantage of no discontinuity at critical field value, is

- 362 -
x
max
c o x
c
x x
c c
E
v
E E
v ,
E E
1 1
E E
| |
|
\ .
~ =
+ +
(4-126)
A comparison of (4-126) with (4-123) gives rise to a field-dependent effective mobility,
e
, of
o
e
x
c
.
E
1
E
=
+
(4-127)
The carrier velocity relationship in (4-126), as well as the carrier mobility degradation implied
by (4-127), portends potentially increased device switching time and limited circuit bandwidth.
This contention reflects the fact that longer average carrier transport time in the source-drain
channel gives rise to a longer time required to witness a drain current response to carrier drift in-
itiated near the source volume.
Figure (4.18) sketches the velocity-field relationships implied by (4-125) and (4-126).
We note that the piecewise linear and empirical plots, deduced from (4-125) and (4-126), respec-
tively, match reasonably well at low electric fields for carrier velocities up to about 30% of the
saturated limited velocity. A match to within less than 15% error is achieved for normalized
fields satisfying E
x
/E
c
6.7.
In order to study the first order effect that mobility degradation incurred by strong lat-
eral electric fields has on the ohmic regime drain current of an NMOS device, we replace mobil-
ity
n
in (4-26) and (4-25) by effective mobility
e
in (4-127). We can show that this replace-
ment engenders the modified ohmic regime I-V declaration,
ds
ds gs h
d n
ds
le
V
V V V
2 W
I K ,
V
L
1
V
( | |

( |
| | \ .
(
=
|
(
\ .
+
(

(4-128)
where

Figure (4.18). The dependence of carrier velocity on electric field in a semiconductor. The
normalizing velocity, v
max
, is the saturated limited carrier velocity in silicon.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0 1 2 3 4 5 6 7 8 9 10
N
o
r
m
a
l
i
z
e
d

C
a
r
r
i
e
r

V
e
l
o
c
i
t
y
,

v
c
/
v
m
a
x
Normalized Channel Electric Field, E
x
/E
c
Piecewise Linear
Velocit y Field Expression
Empirical
Velocity Field Expression

- 363 -
max
le c
n
v
V E L L .
| |
= =
|
\ .
(4-129)
We understand that
n
in (4-129) symbolizes the low field value of electron mobility. In this
relationship, voltage V
le
is termed the lateral field modulation voltage. We note that (4-128) dif-
fers from the original form of the ohmic region volt-ampere relationship by a drain-source vol-
tage-related factor that reduces the observable ohmic regime drain current. Appealing to (4-128)
and (4-129), we see that this current reduction factor approaches unity when the channel length,
L, is long and/or the drain-source voltage, V
ds
, is small. These observations match our engineer-
ing intuition in that small V
ds
and relatively long channel lengths produce lateral electric field
intensities that are small enough to minimize carrier mobility degradation.
A complication resulting from (4-128) is that it no longer produces the simple relation-
ship for the drain saturation voltage witnessed in (4-35). We recall that the drain saturation volt-
age, V
dsat
, is the value of the drain-source voltage, V
ds
, for which inversion layer pinchoff occurs
at the drain volume site. This pinchoff state manifests a small signal ohmic regime conductance
of zero, which corresponds to zero slope in the ohmic volt-ampere characteristic. Upon applying
this zero slope condition to (4-128), we deduce a revised drain saturation voltage of
( )
dsat sat gs h
V M V V , = (4-130)
where, with
gs h
le
V V
,
V
(4-131)
sat
1 2 1
M .
+
= (4-132)
We can easily show that M
sat
1 for 0. The relevant upshot is that carrier mobility degrada-
tion incurred by strong lateral channel fields causes a decrease in the low field value of the drain
saturation voltage. While mobility degradation is generally undesirable, the decrease in drain
saturation voltage actually is good news in low distortion, low voltage circuits that exploit MOS-
FETs functioning in their saturated regimes. In particular, a lowering of the drain saturation vol-
tage allows the use of smaller drain-source voltage biases without risking an indiscriminate
transistor entrance into its ohmic regime.
We can evaluate the drain saturation current in the face of a degradation in lateral field
mobility by substituting (4-129) for drain-source voltage V
ds
into (4-128). This effort produces
the aesthetically pleasing result,
( )
2
2 2
n n
dsat gs h sat
dsat
K K W W
I V M V V .
2 L 2 L
| | | |
= =
| |
\ . \ .
(4-133)
In the limit of large channel lengths, V
le
in (4-129) is large, thereby rendering parameter in (4-
131) small. But for very small , M
sat
in (4-132) approaches unity. It is therefore reassuring that
in the limit of the large channel lengths that cannot support large electric fields in the inverted
channel, I
dsat
in (4-133) collapses to (4-25), which, of course, tacitly invokes constant carrier
mobility.
In contrast to relatively long channel lengths, very small channel geometries give rise to
small V
le
and large , whence M
sat
in (4-132) collapses to

- 364 -
sat
small L
large
1 2 1 2
M .

+
= ~ (4-134)
If we combine the last result with (4-133), the short channel value of I
dsat
is found to be
( )
dsat ox max gs h
small L
I WC v V V , ~ (4-135)
where we have also used (4-9). It is interesting that the resultant drain saturation current is
independent of channel length L. This independence stems from the fact that in the limit of very
small channel lengths, carriers (electrons in the presently considered case of NMOS) are trans-
ported through the inverted channel at their saturated limited, or maximum possible, velocity.
This maximum velocity of carrier propagation renders L inconsequential with respect to the aver-
age time of carrier transport from the source to the drain. But perhaps the most interesting aspect
of (4-135) is that the short channel drain saturation current is a linear function of gate-source vol-
tage V
gs
. Before breaking out a bottle of a fine cabernet sauvignon to celebrate this laudable
discovery, we should understand that the effects of other second order phenomena yet to be ad-
dressed compromise the strict linearity projected by (4-135). Compromises aside, it is
nonetheless true that the saturation regime drain current of very short channel devices is more
linear than is implied by the classic square law relationship advanced by Shichman and Hodges.
An immediate benefit of the linearity projected by (4-135) is a forward transconductance, in this
case WC
ox
v
max
, which unlike the transconductance for a long channel transistor operated in any of
its regimes, is a constant, independent of drain current. Unfortunately, however, this
transconductance is small, unless a large gate width is used. But we shall see shortly that large
gate widths can have adverse effects on circuit response speeds.
Of course, (4-130) through (4-132) apply to the saturation regime of device operation.
We can support this contention because in saturation, the drain current is merely the transistor
current, I
dsat
, evidenced at the cusp that separates ohmic and saturation regimes, corrected by
channel length modulation effects. To wit, short channel phenomena imply that for V
gs
V
h
and
V
ds
V
dsat
,
( )
2
2
n ds dsat
d gs h sat
K V V W
I M V V 1 ,
2 L V
| |
| |
= +
| |
\ .
\ .
(4-136)
where it behooves us to remember that the drain saturation voltage, V
dsat
, is now given by (4-
130). Parameter M
sat
in (4-130) is properly viewed as the short channel correction to drain
saturation voltage. Because of (4-136), the square of M
sat
can be accorded the stature of a cur-
rent correction factor for short channel, saturated drain currents. The dependence on parameter
of these correction factors is displayed in the plots submitted in Figure (4.19). The subject
correction factors can be appreciable. For example, consider = 2, which might represent a
gate-source voltage, V
gs
, that is about a volt over the threshold potential. The curves in the figure
at hand suggest an approximately 38% reduction in the drain saturation voltage predicted by the
simple long channel model, which effectively invokes = 0. We also observe that the degraded
mobility incurs about a 62% attenuation of the drain saturation current corresponding to = 2.
Thus, if we ignore mobility degradation caused by lateral electric fields, we should hardly be sur-
prised by measured or simulated values of drain saturation voltage and current that are smaller
than those predicted by simplified analyses.
While (4-136) and (4-130) are arguably analytically elegant, circuit designers typically
disdain elegance in favor of convenient expressions that enable facilitate comprehension. In
light of this situation, an approximate curve fit of both M
sat
and its square is called for. If we

- 365 -
carefully study (4-132), we find that the least mean square approximation,

Figure (4.19). Voltage and current correction factors resulting from large lateral electric
fields in short channel MOSFETs. The parameter, , is the effective gate-
source voltage, (V
gs
V
h
), normalized to the lateral electric field modula-
tion voltage, V
le
.
sat
1 2 1
M 1 ,
4
+
= ~ (4-137)
results in an error of at most 4.8% over 0 5. A similar numerical exercise produces
2
2
sat
1 2 1 1
M
1 0.78
| |
+
= ~
|
|
+
\ .
(4-138)
to a computational error of at most 5.1% for 0 5. For most design-oriented purposes, (4-
130) can therefore be supplanted by
( ) ( )
( )
dsat sat gs h gs h
gs h
gs h
le
V M V V 1 V V
4
V V
1
1 V V ,
4 V
| |
= ~
|
|
\ .
| |
| =
|
\ .
(4-139)
while (4-136) becomes for circuit design applications of MOSFETs operated in saturated re-
gimes,
( )
( )
2
2
n ds dsat
d gs h sat
ds dsat
2
n
gs h
gs h
le
K V V W
I M V V 1
2 L V
V V
1
K V W
V V .
V V 2 L
1 0.78
V
| |
| |
= +
|
|
\ .
\ .
| |
+ |
| |
|
~
|
|
| |
\ .
|
+
|
|
\ . \ .
(4-140)
We should remind that in this relationship, V
dsat
is given by (4-130). The academic purist who
balks at the foregoing empiricisms is respectfully reminded that the mobility expression in (4-
127) and the long channel velocity relationship of (4-126) are hardly grounded in phenomenol-
ogy that is hardened to the level of the Rock of Gibraltar. Moreover, we should advise that there
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5
C
o
r
r
e
c
t
i
o
n

F
a
c
t
o
r
Parameter

- 366 -
are more than 250 parameters implicit to the ubiquitous Level 49 HSPICE and the increasingly
popular BSIM models of a MOSFET. But the vast majority of these 250 or so parameters are
curve fit or lookup table disclosures that bear no direct analytical relationship to the physical
charge storage and charge transport mechanisms that underpin the volt-ampere properties of a
MOSFET.
Those of us who are in need of a life outside of engineering academe are likely to take
solace in two interesting features to (4-140). To begin our philosophical diatribe, we note that
CLM is emulated by the numerator term on the far right hand side of the subject expression. On
the other hand, a first order account of mobility degradation relates to the denominator term on
the far right hand side. Thus, the first of the aforementioned two interesting features is that the
static effects of CLM and mobility degradation partially offset one another. This observation is
delightfully sensible. In particular, increased CLM promotes an enhanced diffusion component
of the net drain current, while carrier mobility degradation stymies the rampant direct transport
of charge carriers (whose collection at the drain site fosters drain current) through the inverted
MOSFET channel. The second appealing feature is that the ratio of the CLM to the mobility
degradation factors in (4-140) multiplies the transconductance parameter, K
n
. This algebraic
gymnastic establishes an effective transconductance parameter whose value depends on drain-
source voltage (due to CLM) and gate-source voltage (due to mobility impairment). One can
certainly envisage a laboratory situation in which an attempt to match a theoretic disclosure of a
MOSFET volt-ampere characteristic curve to its measured counterpart entails a numerical
tweak of the presumably constant transconductance parameter to which the theoretic disclo-
sure is proportional.
4.5.3. VERTICAL EFECTRIC FIELDS
Apart from the carrier mobility degradation incurred by strong lateral fields in the in-
verted channel of a MOSFET, the mobility degradation of carriers in the channel is exacerbated
by vertical electric fields. These fields result from the excess interface potential, (V
gs
V
h
), in
the case of NMOS; (V
sg
V
h
) for PMOS. In NMOS, increases in V
gs
strengthen the vertical field
so that free electrons transported from the source to the drain are encouraged to drift from source
to drain on a conduction path that lies close to the actual oxide-semiconductor interface.
Unfortunately, this interfacial surface is far from a perfectly smooth boundary, if for no other
reason than routine device processing invariably produces ionic contamination therein. The
imperfect boundary results in potentially significant carrier scattering, which in turn diminishes
carrier mobility. In more extreme situations manifested by excessive V
gs
and/or extremely thin
oxide layers, the vertical fields can become so intense as to impart large forces on the free
channel electrons. In turn, these forces may be sufficiently large to enable channel electrons to
surmount the barrier between oxide and interfacial semiconductor. These so-called hot electrons
are lost insofar as drain current is concerned in that they become stray charges that contaminate
the gate oxide.
To first order, the mobility attenuation resulting from increased gate overdrive can be
addressed analytically by replacing the low field mobility,
n
(for NMOS), to which K
n
in (4-23)
is directly proportional, by an effective carrier mobility,
eff
, such that
n
eff
gs h
ve
.
V V
1
V
=
+
(4-141)

- 367 -
In this expression, V
ve
is the vertical electric field modulation voltage, which is nominally
directly proportional to the thickness, T
ox
, of the oxide layer. Of course, an expression analogous
to (4-141) prevails for hole mobility in the inverted channel of PMOS transistors. The magical
empiricism
[10]
,
ve ox
V T 15 , = (4-142)
where T
ox
in units of angstroms returns V
ve
in units of volts, proves reasonable. Because of (4-
142), (4-140) for the saturation domain current becomes
( )
( )
2
gs h
2
n ds dsat
d sat
gs h
ve
ds dsat
2
gs h
n
gs h gs h
ve le
V V
K V V W
I M 1
V V 2 L V
1
V
V V
1
V V
K V W
.
V V V V 2 L
1 1 0.78
V V
| |
| |
= +
| |
| | \ .
\ .
+
|
|
\ .
| |
| +
| | |
~
|
|
| | | | \ .
|
+ +
| |
| | |
\ . \ . \ .
(4-143)
An analogous modification, which amounts to an effective reduction of the transconductance
density parameter, K
n
, can be made to the ohmic domain current. We observe in (4-143) that the
combined effect of lateral and vertical electric fields is to diminish the drain current dependence
on the squared excess gate-source voltage, (V
gs
V
h
). In extreme (and generally unachievable or
unrealistic) conditions, the drain current can be rendered nominally independent of (V
gs
V
h
),
which is to imply the impracticality of a drain current that ceases to be controlled by gate-source
voltage.
4.5.4. DRAIN INDUCED BARRIER LOWERING
Drain induced barrier lowering (DIBL) refers to a reduction in transistor threshold vol-
tage brought about by increased drain-source voltages. It is a phenomenon that is far more pro-
nounced in deep submicron devices than it is in long channel transistors. We recall from the
Boltzmann relationships in (4-11) and (4-12) that the interfacial concentration, n, of free elec-
trons in NMOS is exponentially related to the corresponding surface potential, V
y
. Recall fur-
ther, by (4-10), that we assumed V
y
is the exclusive result of an applied gate-source voltage, V
gs
.
Specifically, we tacitly assumed that V
y
is independent of drain-source voltage, V
ds
, which is an
analytical tack that asserts an effective electrostatic isolation between the interfacial potential and
the drain. This assumption is assuredly valid in the ohmic operating regime where the entire
source-drain channel along the interface is strongly inverted. It is even a valid postulate in long
channel transistors operating in saturation where most of the channel region lying beneath the
gate remains strongly inverted. But in short channel devices, the depletion layer formed by
drain-source voltage spreads progressively closer to the source volume so that an appreciable
fraction of the channel lying beneath the gate is now depleted. In this case, we should expect
potential V
y
to be affected, not only by gate-source voltage V
gs
, but also now by drain-source vol-
tage V
ds
. In particular, we should expect V
y
to increase over and above the value of V
y

established by V
gs
, per (4-10). By virtue of Boltzmann statistics, an increase in free electron
concentration in the inverted portion of the channel accompanies the asserted increase in V
y
. But
for fixed V
gs
, an enhanced free carrier population can be viewed as the ramification of a dimi-
nished threshold voltage. Equivalently, it can also be viewed as a lowering of the barrier that

- 368 -
minority carriers in the bulk must overcome if they are to be granted a passport to enter the in-
verted region of the channel. Thus, we can view an increasing V
ds
in short channel devices as
resulting in a smaller threshold voltage or a lowering of the barrier faced by bulk minority carri-
ers.
Developing a physically sound expression to govern the dependence of threshold vol-
tage V
h
on drain-source voltage V
ds
is not a simple exercise. Most computer-based MOSFET
models adopt the tack of replacing threshold voltage V
h
by an effective threshold value, V
he
,
which is given by
h
he
ds
V
V ,
V
1
V
q
=
+
(4-144)
where V
is an empirical voltage parameter lying in the range of 30 volts < V
< 55 volts. The

30-volt floor corresponds to a deep submicron device, while the 55-volt ceiling reflects long
channel technology
7
. Thus, a first order account of DIBL effects can be made by replacing V
h
in
all of our MOSFET I-V and related other relationships, inclusive of (4-143), by V
he
.
Obviously, (4-143), with or without DIBL phenomena incorporated, is inordinately
more cumbersome than is the square law, volt-ampere characteristic advanced by (4-35) for the
saturation domain. As a result, the design-oriented determination of a suitable gate-source vol-
tage for a desired drain current and corresponding drain-source voltage can be far more challeng-
ing than might be projected by modeling tools embracing only a long channel situation. But in
addition to the computational problems precipitated merely by algebraic complexity, we must
also endure engineering difficulties with respect to accurately evaluating the model metrics, K
n
,
V
h
, V
ve
, V
, V
le
, and V
. These latter difficulties derive from the unfortunate fact that the
mathematical functions that definitively relate device model parameters to such physical device
and charge transport properties as saturation velocity, carrier mobility, regional concentrations,
and other semiconductor performance barometers are invariably unavailable. At best, we can
expect to have presumably reliable, detailed device model parameters suitable for computer-
aided simulation of transistor performance. For example, process foundries routinely supply
their customers with device models in the form of Level 49 HSPICE, BSIM, or other computer-
based files. While these parameters generally allow for satisfying simulations, it is unfortunate
that many, if not most, of the hundreds of numerical entries in these files are themselves non-
physical entities that defy the formulation of satisfying mathematical relationships to the physical
model metrics discussed in earlier paragraphs. These and related other design-oriented problems
can prove exasperating. But as we attempt to demonstrate throughout this text, such problems
tend to be mitigated by intelligently coalescing manual design strategies with design adjustments
premised on calculations and engineering interpretations that derive from computer-based
simulations or actual laboratory measurements of transistor characteristics and overall circuit
performance.
4.5.5. TEMPERATURE EFFECTS
The operating temperature of the inverted interfacial channel affects the drain current of
a transistor in two ways. First, because thermal energy imparted to free carriers increases their
frenzied scattering, the average carrier mobility decreases in response to increased operating

7
In SPICE simulators, an account of DIBL phenomena is made through parameter eta, where eta = 1/V
.

- 369 -
temperatures. To first order and as disclosed earlier, the electron mobility,
n
(T), relates to abso-
lute temperature T as an inverse three-halves power law. We recall that parameter K
n
in (4-26)
and K
p
in (4-30) are directly proportional to the carrier mobility. Moreover, the ohmic and
saturation regime drain currents in (4-40) and (4-42) are directly proportional to parameter
n
(or
p
) which, in turn, is directly related to K
n
(or K
p
). Accordingly, (4-144) implies that the drain
current of a MOSFET offers a negative temperature coefficient to circuits in which it is embed-
ded.
A second effect of increased thermal energy is correspondingly increased threshold vol-
tage, which complements the foregoing negative temperature coefficient nature of the MOSFET
static I-V characteristic.. We can best initiate this thermal assessment by returning to (4-17) to
evaluate the derivative of the threshold voltage, V
h
, with respect to the Fermi potential, V
F
.
Recalling (4-17) and (4-7), and noting that the body effect voltage, V
, in (4-8) is independent of
temperature,
h h ho bs
F F F F
h ho F
dV V V V V V
2 ,
dV V 2V 2V
V V 2 V V
| |
| |
= + + + |
|
|
+
\ .
\ .
(4-145)
where V
ho
is recalled as the zero bias (V
bs
= 0) value of the threshold potential. We note that the
last two terms on the right hand side of this expression vanish when a MOSFET is operated with
V
bs
= 0. The sensitivity of the threshold voltage, say S
h
, with respect to temperature follows as
h h F
h
F
dV dV dV
S .
dT dV dT
= = (4-146)
The temperature derivative of the Fermi potential derives from (4-6), with the proviso that due
account be made of the temperature dependence of the intrinsic carrier concentration, n
i
. To this
end, a commonly used empirical formula is
( )
o n
T T T
i io
n n 2 ,
= (4-147)
where T
n
is generally taken to be 10 C. Assuming the reference temperature, T
o
, is 27 C, n
io
,
the intrinsic carrier concentration at T = T
o
, is about (4.5)(10
10
) atoms/cm
3
. With T
n
= 10 C, (4-
147) allows n
i
to double for each T
n
C rise above the reference temperature. Armed with (4-
147), (4-7) produces
F F T
n
dV V V
2 .
dT T T
ln = (4-148)
Equations (4-148) and (4-146) combine to yield the result,
h ho bs F T
h
F F F n h ho F
V V V V V V V
S 2 2 .
V 2V 2V T T V V 2 V V
ln
( | |
| | | |
( = + + + |
| |
|
+ (
\ . \ .
\ .
(4-149)
The indicated temperature derivative of the threshold voltage is invariably a positive number. It
typically lies in the range of 1.5 mV/C to 3.0 mV/C. Thus, the threshold voltage increases with
increasing operating temperature, thereby leading to a decrease in the drain current. In other
words, the temperature dependence of both the carrier mobility and the threshold voltage com-
bine to encourage a drain current boasting a negative temperature coefficient.
The algebraic form of (4-149) is depressing and is hardly a relationship stored in the
biological memories of circuit designers. Fortunately, for MOSFETs featuring thin gate oxides
(at most 50 ) substrate doping concentrations no smaller than 10
14
atoms/cm
3
, and near zero
bulk-source voltage, (4-149) can be reduced to the simpler form,

- 370 -
h ho F
h
F
V V 2V
S 1
4V T
| |
| ~ +
|
\ .
(4-150)
where we remember that (4-17) applies for the voltage difference, (V
h
V
ho
). For first order
manual circuit analyses that we execute as a prelude to definitive computer-aided analyses, (4-
150) proves acceptable.
Figure (4.20) plots the threshold voltage temperature sensitivity decreed by (4-149) for
two values of bulk-source voltages. We note with some interest that for any temperature in the
25 C to +125 C temperature range, the subject thermal sensitivity is smaller for negative
bulk-source voltage than it is for V
bs
= 0. At the reference temperature of 27 C, the threshold
voltage sensitivity zero bulk-source bias is under 2 mV/C.

Figure (4.20). Temperature sensitivity of the threshold voltage for an NMOS transistor
featuring T
o
= 27 C, T
n
= 10 C, T
ox
= 70 , n
io
= 4.5(10
10
) atoms/cm
3
,
and N
A
= 5(10
15
) atoms/cm
3
.
4.5.6. TRANSISTOR CAPACITANCES
The volt-ampere characteristic equations given by (4-40), (4-42), (4-140), and (4-143)
pertain to MOSFETs operated under static or low frequency signal conditions. When high fre-
quency signals are processed, the current responses of transistors are unavoidably slowed by de-
vice capacitances that arise from charges stored in the inverted channel and within the depletion
regions formed about the source and drain implants. The circuit ramifications of the resultant
inability of drain currents to respond quickly to signal excitations are constrained bandwidths,
substantive frequency dependent group delays, and exacerbated rise, fall, and settling times to
the transient responses produced by step and other forms of abrupt input excitations. In extreme
cases, the interaction of transistor capacitances with the energy storage elements implicit to the
circuit into which the MOSFETs are embedded can produce pronounced underdamping in the
frequency and time domains, as well as even outright instability.
4.5.6.1. Depletion Capacitances
The depletion capacitances associated with the PN junctions formed about both the
drain and the source are the first of two principle sources of transistor capacitances. Each of
these two transition capacitances is comprised of a superposition of a planar component and a
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
T
e
m
p
e
r
a
t
u
r
e

S
e
n
s
i
t
i
v
i
t
y
.

S
h
(
m
V
/
d
e
g

C
)
Temperature (deg C)

- 371 -
sidewall component that derives from charge storage at the perimeter of the source and drain vo-
lumes. The planar component consists of the depletion layer established between the bulk sub-
strate region and the underbody of the source and drain regions. The sidewall capacitance em-
braces the depletion layers in the areas of the source and drain regions that are proximate to the
front surface, the back surface, and the side surface areas of the active channel region. For the
bulk-drain depletion capacitance, C
bd
, we have
j jsw
d j d jsw
bd
M M
bd bd
j j
A C P C
C .
V V
1 1
V V
= +
| | | |

| |
| |
\ . \ .
(4-151)
We see that the terms on the right hand side of this expression mirror the traditional depletion, or
transition, capacitance associated with back biased PN junctions. This observation is reassuring
in that the bulk and drain forge a reverse biased PN junction for routine MOSFET operation
where the bulk is electrically connected to the most negative potential available in the circuit into
which the transistor is embedded. In (4-151), V
j
is the built-in potential of the bulk- drain junc-
tion. Capacitance parameter C
j
is the zero bias (meaning, V
bd
= 0), value of the capacitance den-
sity, in units of farads/meter
2
, associated with the planar component of the bulk-drain capacit-
ance. On the other hand, C
jsw
represents the zero bias lineal capacitance, in units of farads/meter,
of the aforementioned sidewall perimeters. Parameters M
j
and M
jsw
are junction grading coeffi-
cients whose numerical values lie is the range of 1/3 to 1/2. The planar drain area, A
d
, is
d diff
A WL , = (4-152)
where L
diff
is, with an appeal Figures (4.1) and (4.2), recalled to represent the width of the drain
region. This width usually mirrors the width of the source implant. In general, the dimension
L
diff
must be extracted empirically from measured data but as a rule of thumb, L
diff
is nominally of
the order of twice the drawn channel length, L. Parameter P
d
, is the effective perimeter of the
sidewall area, which we delineate as
d diff
P W 2L W 4L . = + ~ + (4-153)
As we might expect the capacitance expression for the bulk-source junction is analog-
ous to the relationship in (4-151). Specifically,
j jsw
s j s jsw
bs
M M
bs bs
j j
A C P C
C ,
V V
1 1
V V
= +
| | | |
| |
| |
\ . \ .
(4-154)
where,
s d diff
s d diff
A A WL 2WL
.
P P W 2L W 4L
= ~
= + ~ +
(4-155)
4.5.6.2. Gate Capacitances
The second source of MOSFET capacitance is the net gate capacitance, which is com-
prised of three components. The first of these components appears between the gate and the
bulk. This capacitance has a very small nonzero frequency value in both weak and strong chan-
nel inversion modes, which suggests that the channel inversion layer effectively shields the gate
from the bulk substrate
[11]
. Because the gate-bulk capacitance is invariably small, it has little

- 372 -
consequence to MOSFET circuit performance at high signal frequencies. We shall opt to simpl-
ify our engineering life by ignoring this capacitance.
The other two components of net gate capacitance are the gate-source capacitance, C
gs
,
and the gate-drain capacitance, C
gd
. Each of these energy storage elements is a superposition of
an intrinsic component, which is incurred by the relevant effects of the gate, gate oxide, and in-
verted channel, and an extrinsic constituent, which is incurred by gate oxide overlap at the source
and drain sites. Since the inversion layer extends from source to drain in only the ohmic regime
of operation, the relevant capacitance values differ for the ohmic and saturated regimes.
The maximum possible intrinsic capacitance established between the gate and the
inversion layer is clearly WLC
ox
. In the ohmic operating regime, where the inversion layer spans
the entire length of the drawn channel, a viable first order approximation divides this maximum
capacitance equally between the source and the drain to give identical intrinsic gate-source and
gate-drain capacitance values; namely, WLC
ox
/2. Accordingly, in the ohmic regime, the effective
gate-source capacitance is
ox
gs gso
WLC
C WC ,
2
= + (4-156)
where C
gso
is the capacitance per unit length associated with the oxide-source overlap. Similarly,
the effective gate-drain capacitance in the ohmic operating regime is
ox
gd gdo
WLC
C WC ,
2
= + (4-157)
where C
gdo
is the drain overlap capacitance counterpart to the source overlap capacitance. Typi-
cally, C
gso
and C
gdo
are as small as 0.25 fF/m in minimal geometry transistors. Thus, for a
transistor characterized by L = 180 nM, W/L = 20, and an oxide thickness of T
ox
= 30 , C
gs
=
C
gd
= 4.63 fF. We observe somewhat interestingly that the net overlap capacitance is WC
gso
=
WC
gdo
= 0.9 fF, which is almost 20% of the total gate-source (or gate-drain) capacitance.
The gate capacitance situation in saturation is a bit more intricate than that prevailing in
the ohmic regime. In saturation where V
ds
> V
dsat
, pinch off occurs within the source-drain chan-
nel, thereby leaving a depletion zone that is free of mobile charges within the channel and near to
the drain volume. We can therefore argue that the drain-source voltage exerts hardly any influ-
ence on the channel charge. The resultant gate-drain capacitance therefore derives exclusively
from the oxide overlap with the drain; that is, the gate-drain capacitance, C
gd
, in saturation is
simply
gd gdo
C WC . = (4-158)
In contrast to the charge depletion prevailing in the channel region adjacent to the
drain, a large free carrier population is concentrated near the source. Since this concentration is
influenced strongly by interface potential, which is determined by the applied gate-source volt-
age, it is only logical to expect a gate-source capacitance that is comparatively larger than the
gate-drain capacitance. To this end, we take the gate-source capacitance, C
gs
, to be
[12]

gs ox gso
2
C WLC WC .
3
= + (4-159)
It is important to underscore the fact the first term on the right hand side of this relationship is an
approximation that derives from the presumption of negligible carrier mobility degradation
within the MOSFET channel. Accordingly, we are compelled to advise that the computed gate-
source capacitance value must be tempered by capacitance values extracted from scattering

- 373 -
parameter or other types of two port parameter characterizations of transistor performance at
high signal frequencies.
4.5.6.3. Large Signal Model
At this point of MOSFET model development, the large signal, or nonlinear, model of
NMOS is the structure offered in Figure (4.21). Depending on whether the transistor undergoing
assessment is operated in its subthreshold, ohmic, or saturated regions, the equation for the indi-
cated controlled current source, I
d
, derives from expressions formulated in Section (4.3.0) or, for
that matter, the model refinements addressed in Section (4.5.0). The depletion capacitances, C
bs

and C
bd
, are not affected by the domain of transistor operation, but the appropriate regional val-
ues of the gate-source and gate-drain capacitances, C
gs
and C
gd
, respectively, must be extracted in
accord with the disclosures of the preceding subsection.

Figure (4.21). The large signal model of an n-channel MOSFET (NMOS). A topologically identical
equivalent circuit applies for a p-channel MOSFET (PMOS).
The model in Figure (4.21) incorporates four resistive elements. The resistances, r
d
and
r
s
, are respectively associated with the strongly doped drain and source regions, respectively.
These resistances are specified in circuit simulation software by a sheet resistance parameter, R
sh
,
and drain and source geometric parameters, N
rd
and N
rs
. In particular,
d rd sh
s rs sh
r N R
,
r N R
=
=
(4-160)
where parameter R
sh
is cast in units of ohms per square. Owing to the high impurity doping
concentrations in the drain and the source volumes, which begets small sheet resistance R
sh
,
resistances r
d
and r
s
are small enough to justify their neglect in most analog circuit studies. In
contrast, resistance, r
b
, which represents a spreading resistance in the bulk substrate, can be as
large as the high tens to low hundreds of ohms. Despite its relatively large value, its impact on
analog circuit performance is nonetheless muted by the fact that the bulk rarely conducts signifi-
cant currents, even at high signal frequencies. Indeed, the flow of substantial bulk currents war-
rants careful engineering scrutiny, since the existence of bulk currents normally indicates a de-
vice processing issue, a layout error, or a circuit design oversight. In a subsequent chapter,
S
S
G
G
D
B
I
d
I
b
I
s
I
g
V
ds
V
bs
V
gs
S
V
gd
D
C
gs
C
bs
V
gs
V
bs
V
ds
+
r
g
r
s
C
gd
C
bd
V
gd
V
bd
+

+
r
d
r
b
B
D
I
d

- 374 -
however, we provide engineering evidence that the bulk spreading resistance influences the ther-
mal noise characteristics of the drain-source channel.
Like resistance r
b
, the gate resistance, r
g
, is likewise important from a thermal noise
perspective in that it captures the salient circuit level effects of thermally agitated mobile charge
carriers in the channel. It also looms significant with respect to design problems associated with
maximum signal power transfer in radio frequency (RF) circuits. This resistance is computed
as
[13],[14]

( )
g
2
gs ch
5
r ,
C R
= (4-161)
where R
ch
represents the V
ds
= 0 value of the drain-source channel resistance. Recalling (4-28),
( )
sat dsat
ch
dsat
n gs h
M V 1
R ,
W 2I
K V V
L
= =
| |

|
\ .
(4-162)
where we have relied on (4-130) and (4-133). Because of the inverse dependence of r
g
on the
square of radial signal frequency, , r
g
is infinitely large under quiescent operating circums-
tances and remains relatively large for low to even reasonably high frequencies. From a purely
analog analytical perspective for which noise is not addressed, resistance r
g
is generally taken to
infinitely large.
4.6.0. SMALL SIGNAL OPERATION
As we conjectured earlier, MOSFETs are often the active device of choice in high
performance analog integrated circuits. When the fundamental objective of these analog net-
works is linear I/O signal processing, MOSFETs embedded in these networks are commonly bi-
ased in their saturation domains. The quiescent operating point selected in the saturation regime
is chosen to ensure that for all applied input signals, the instantaneous drain-source voltage, v
ds
,
(source-drain voltage for PMOS) is never any smaller than the drain-source saturation voltage,
v
dsat
(source-drain saturation voltage for PMOS). To be sure, linear signal processing can also be
achieved when transistors operate in their ohmic regimes. But when excellent performance, in
such senses as high gain, wide bandwidth, low distortion, and acceptable driving point output
impedances, are critical design objectives, saturation is the preferred operating domain. Accor-
dingly, you will be delighted to hear that ohmic linear equivalent circuits of transistors are ig-
nored herewith and left for your own personal edification as an exercise at the conclusion of this
chapter.
An inspection of (4-143) suggests that the instantaneous drain current, i
d
, flowing in an
NMOS transistor is a function of three device voltages: the instantaneous gate-source voltage,
v
gs
, the instantaneous drain-source voltage, v
ds
, and the instantaneous bulk-source voltage, v
bs
.
Recall that the last voltage covertly influences the threshold potential, V
h
. An analogous state-
ment applies to PMOS transistors, subject to the current and voltage conventions adopted earlier.
Thus, we generalize (4-143) as

- 375 -
( )
( )
ds dsat
2
gs h
n
d gs ds bs
gs h gs h
ve le
v v
1
v V
K V W
i f v , v , v .
v V v V 2 L
1 1 0.78
V V
| |
| +
| | |
~ =
|
|
| | | | \ .
|
+ +
| |
| | |
\ . \ . \ .
(4-163)
Under zero signal conditions, which is tantamount to operating the considered MOSFET at its
quiescent operating point (Q-point), it is understood that (4-163) delivers
( )
dQ gsQ dsQ bsQ
I f V , V , V , = (4-164)
where the indicated upper case variables designate static, or standby, quiescent device currents
and voltages. In other words, the MOSFET whose quiescent volt-ampere characteristics are ab-
stracted by (4-164) is in a standby mode awaiting the application of time-varying signals that are
earmarked for linear signal processing. Prior to signal excitation, the transistor maintains quies-
cent values of drain current, gate-source voltage, drain-source voltage, and bulk-source voltage
that respectively equal I
dQ
, V
gsQ
, V
dsQ
, and V
bsQ
. As in the case of bipolar junction transistors
(BJTs), the Q-point must be judiciously selected. In particular, the quiescent operating point
must be located in a reasonably linear portion of the static I-V characteristic curves. The
terminology, reasonably linear, serves to concede that perfect I/O linearity in practical
semiconductor devices is a clarion impossibility. But it also means that the aforementioned
perturbations induced in these static variables by an applied input signal (or signals) remain
nominally linear functions of the amplitudes of said signals.
Let us assign the variable I
da
, to the signal-induced change in the static drain current,
I
dQ
. Similarly, let V
ga
designate the signal-induced change in Q-point gate-source voltage V
gsQ
,
and allow V
da
to represent the signal-induced perturbation to the Q-point drain-source voltage,
V
dsQ
. Finally, we shall stipulate V
ba
as the signal change about the quiescent bulk-source voltage,
V
bsQ
. Since the signal variables, I
da
, V
ga
, V
da
, and V
ba
can be positive or negative, depending on
network topology and the nature of the driving input signal, these signal components can be
viewed as signal swings about their respective quiescent components. If the Q-point is in a
reasonably linear segment of the transistor static I-V curves, each of these Q-point variables
superimpose with their respective signal constituents to quantify the corresponding instantaneous
values of device current or voltage. In short,
d dQ da
gs gsQ ga
ds dsQ da
bs bsQ ba
i I I
v V V
.
v V V
v V V
= +
= +
= +
= +
(4-165)
In concert with (4-165), the MOSFET under consideration is said to operate linearly if
and only if the signal-induced changes, I
da
, V
ga
, V
da
, and V
ba
, interrelate linearly and if and only if
the Q-point currents and voltages, I
dQ
, V
gsQ
, V
dsQ
, and V
bsQ
, remain constant and independent of
all signal components. It is crucial to understand that operational linearity in an electronic device
does not imply linear relationships among the instantaneous device variables, nor does it imply
linearity among the corresponding quiescent values of these variables. Instead, operational
linearity implies only that a selected variable in the set of four perturbed variables is linearly re-
lated to any other device signal component and any signal branch current or signal node voltage
in the circuit in which the subject transistor is embedded.

- 376 -
4.6.1. SMALL SIGNAL MODEL
Because of the obviously nonlinear nature of (4-163), we can reasonably question the
reality of achieving the aforementioned linearity condition among the perturbed signal variables.
Despite its inherently nonlinear nature, (4-163) is mercifully well behaved, thereby enabling
approximating the desired linearity by judiciously limiting all signal excursions about respective
operating point values to sufficiently small levels. This sufficiently small signal mandate, which
is identical in principle to the constraint we invoked with BJTs, synergizes with the concept of
small signal analysis. Moreover, the small signal condition leads to a small signal MOSFET
model. The small signal approximation is deemed both valid and appropriate for specific circuit
applications if the retention of only the linear terms of the Taylor series expansion of (4-163)
about the operating point of the considered device leads to suitably small errors in the resultant
expression for the signal component of the net drain current. Thus, since the venerable Taylor
series, approximated to include only linear terms, is tailor made (pun intended again) to investi-
gate the effects of small perturbations about a fixed operating point,
( ) ( ) ( )
d d d
d dQ gs gdQ ds dsQ bs bsQ
gs ds bs
Q Q
Q
i i i
i I v V v V v V .
v v v
c c c
~ + + +
c c c
(4-166)
We emphasize that the three derivatives on the right hand side of this expression are evaluated at
the Q-point of the MOSFET; that is, at i
d
= I
dQ
, v
gs
= V
gsQ
, v
ds
= V
dsQ
, and v
bs
= V
bsQ
. Using (4-
165) and noting that each of the three subject derivatives is a constant having units of conduc-
tance, we can couch the small signal implications of (4-166) in the form,
da
da m ga mb ba
o
ga
ga
g
V
I g V g V
r
,
V
I 0
r
~ + +
~ ~
(4-167)
where we have taken gate resistance r
g
to be infinitely large. Moreover,
d
m
gs
Q
d
o ds
Q
d
mb
bs
Q
i
g
v
i 1
.
r v
i
g
v
c
c
c
c
c
c
(4-168)
Equation (4-167) gives rise to the small signal, low frequency equivalent circuit in Fig-
ure (4.22a). The subject circuit becomes the small signal, high frequency MOSFET model if the
four previously discussed capacitances, C
gs
, C
gd
, C
bd
, and C
bs
, are appended as indicated in Fig-
ure (4.22b). We underscore the fact that neither of the models in Figure (4.22) gives direct
information about the net instantaneous electrical variables of a MOSFET, nor does either model
allow for the computation of the quiescent values of these variables. Indeed, the models at hand
require a priori knowledge of the Q-point since the small signal parameters, g
m
, r
o
, and g
mb
, de-
pend on the operating point, as is underscored by (4-168). Moreover, the four capacitive ele-
ments in the model of Figure (4.22b) likewise depend on the Q-point at which the considered

- 377 -
transistor is biased. In short, the models in Figure (4.22) give reasonably accurate, first order
approximations of the interrelationships among only the small signal components, I
da
, V
ga
, V
da
,
and V
ba
, of the net currents and voltages indigenous to a MOSFET.

Figure (4.22). (a). Small signal, low frequency equivalent circuit of an n-channel MOSFET. (b).
Small signal, high frequency equivalent circuit of an n-channel MOSFET. The
topological structures of either model apply to both the ohmic and saturation re-
gimes of operation.
Although the circuit topologies of both the models drawn in Figure (4.22) pertain to
both the ohmic and saturation regimes of n-channel MOSFET operation, the equations we de-
velop shortly for the low frequency parameters of these models apply only to the saturation re-
gion. The topological identity stems from the fundamental fact that the small signal models
intertwine only signal-induced, suitably small changes of device currents and voltages about
their respective quiescent values, as opposed to interrelating net device currents and voltages. In
an attempt to dispel possible confusion, we offer the latter (PMOS) models in Figure (4.23).
Note that in this model, we have altered the sign convention in all of the signal components of
the instantaneous device variables. This innocuous alteration, which exploits the observation
that signal components can assume positive or negative values, allows the convenience of a
PMOS small signal model that is topologically identical to its NMOS counterpart.
In the low frequency models of either Figure (4.22a) or Figure (4.23a) the signal
component of the bulk current, I
ba
, flows into an open circuit because, the bulk-drain and bulk-
source junctions of devices embedded in analog networks are commonly reversed biased. The
low frequency signal component of the gate current, I
ga
, is very nearly zero because the gate
S
S
G
D
B
i
b
i
g
v =V +V
ds dsQ da
v =V +V
bs bsQ ba
v =V +V
gs gsQ ga
S
i =I +I
d dQ da
I
da
I
sa
i
s
I
ga
g V
m ga
g V
mb ba
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(a).
S
I
da
I
ga
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(b).
C
gs
C
bd
C
bs
r
g
C
gd
r
g
g V
m ga
g V
mb ba

- 378 -
resistance, r
g
, in (4-161) is inversely proportional to the square of the radial signal frequency. Of
course, both of these currents are larger at high frequencies where the capacitances in the subject
models become poor approximations of the open circuits they emulate at low signal frequencies.

Figure (4.23). (a). Small signal, low frequency equivalent circuit of a p-channel MOSFET. (b).
Small signal, high frequency equivalent circuit of a PMOS device.
In the foregoing small signal equivalent circuits, the parameter, g
m
, is termed the
forward transconductance. It is a critical analog circuit metric in that it serves as a measure of
achievable forward gain. In particular, parameter g
m
, when multiplied by the applied gate-source
signal voltage, V
ga
, determines the amount of signal drain current, I
da
, which results from the
applied gate-source signal. On the other hand, the bulk transconductance, g
mb
, measures an
effective leakage from the applied bulk-source signal, V
ba
, to the signal drain current. Parameter
g
mb
is small, thereby minimizing a signal drain current response to an applied bulk-source signal
voltage, particularly if the gate oxide thickness is small. However, we should note in passing
that depending on the selected quiescent operating point for deep submicron transistors,
parameter g
mb
can be as much as 10% to 20% of the forward transconductance, g
m
. However,
the current, g
mb
V
ba
, is zero in analog circuits that configure their utilized MOSFETs by
connecting together their bulk and source terminals, thereby rendering V
ba
= 0. Finally, r
o
, the
drain-source channel resistance, appears as a shunting resistance across the drain and source
terminals. If r
o
is infinitely large (which is not a great approximation in practical MOSFETs and
particularly for deep submicron channel MOSFETs) the drain-source small signal port of a
MOSFET behaves as an ideal Norton equivalent current source. In such a case, the load current
D
G
S
B
i
b
i
g
v =V V
sd sdQ da
v =V V
sb sbQ ba
v =V V
sg sgQ ga
D
i
s
i =I I
d dQ da
S
S
I
da
I
sa
I
ga
g V
m ga
g V
mb ba
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(a).
S
I
da
I
ga
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(b).
C
gs
C
bd
C
bs
r
g
C
gd
r
g
g V
m ga
g V
mb ba

- 379 -
level, a dominant component of which is g
m
V
ga
, is unaffected by modulations in the drain-source
signal voltage, V
da
. It follows that if the gate-source terminals serve as an input signal port
boasting infinitely large impedance and the drain-source terminals function as the output port,
the MOSFET emulates an ideal transconductance amplifier if the channel resistance, r
o
, is large.
The determination of the three low frequency parameters defined in (4-168) requires
that the indicated derivatives of the drain current expression in (4-163) be evaluated. We can
appreciate that this evaluation is an algebraically daunting task bordering on engineering futility
in that we are rarely privy to accurate numerical information that fixes the values of the physical
parameters implicit to (4-163). We shall therefore either rely on computer-based disclosures of
the numerical values of these parameters or condescend to first order approximations of the sub-
ject small signal parameters. To the latter end, replace (4-163) with the simpler, but still useful,
expression,
( )
2
n ds dsat
d gs h
K v v W
i v V 1 ,
2 L V
| |
| |
~ +
| |
\ .
\ .
(4-169)
which tacitly ignores the influence of both lateral and vertical electric fields in the MOSFET
channel. In (4-163), we see that the immediate effect of these electric fields is to modulate the
transconductance coefficient, K
n
, which we recall to be directly proportional to the mobility of
carriers in the channel. This observation provides us the engineering option of curve fitting. In
particular, in the immediate neighborhood of a desired operating point, K
n
can be adjusted to en-
sure a reasonable match of the volt-ampere characteristic curve of (4-169) either to measured re-
sults or to data deriving from simulations premised on definitive device models. By ignoring the
effects of lateral fields, parameter M
sat
in (4-132) is one, whence the drain saturation voltage in
(4-130) is simply the voltage difference, v
dsat
= (v
gs
V
h
). Accordingly, (4-140) and (4-141)
yield a forward transconductance of
dQ dQ
d
m
gs gsQ hQ Q dsQ dsatQ
Q
2I I
i
g ,
v V V V V V
c
~
c +
(4-170)
where it is understood that all indicated transistor variables and metrics are evaluated at the Q-
point of the transistor undergoing study. Biasing voltage and standby power constraints ordina-
rily compel that the transistor be biased at a drain-source voltage that is only slightly above the
drain saturation voltage, assuming, of course, that the transistor continues to operate in its satura-
tion regime for anticipated drain-source voltage swings. This proviso means that the signal
swing we witness in the drain-source voltage must be smaller than the quiescent voltage differ-
ence, (V
dsQ
V
dsatQ
). We can therefore expect V
Q
to be much larger than (V
dsQ
V
dsatQ
). Moreo-
ver, V
Q
is virtually assured of being significantly larger than V
dsatQ
/2. It follows that the second
term on the right hand side of (4-170) is generally negligible, whereupon (4-136) and (4-170)
deliver
( )
dQ
d
m n dQ
gs gsQ hQ
Q
2I
i
g 2K W L I .
v V V
c
~ ~
c
(4-171)
This result suggests that the forward transconductance of a MOSFET increases with nominally
the square root of the product of transistor gate aspect ratio and quiescent drain current. We
therefore perceive that high gain requirements in certain MOSFET amplifiers compel relatively
large standby drain currents and/or suitably large gate widths. Unfortunately, the former tack
conflicts with low power dissipation budgets, and the latter gives rise to increased device
capacitances and hence, potentially degraded frequency responses. We observe that while the

- 380 -
term in V
Q
in (4-170) is usually negligibly small, significant channel length modulation (which
translates to small V
Q
) tends to limit achievable voltage gain.
It may be prudent to interject that (4-171) highlights a MOSFET deficiency with re-
spect to its bipolar competition. In particular, g
m
in (4-171) is seen as rising with the square root
of the Q-point drain current. In contrast, BJTs have their transconductances rising linearly with
their quiescent collector currents. Thus, for example, doubling the forward transconductance of
a BJT requires only a doubling of its Q-point collector current. In contrast, the same doubling of
a MOSFET forward transconductance mandates a quadrupling of is quiescent drain current,
which begets a potentially significant power dissipation penalty.
An evaluation of the bulk transconductance, g
mb
, requires that (4-169) be considered
analytically in conjunction with the threshold voltage term in (4-14). After enduring some messy
algebra, we conclude that
d
mb b m
bs
Q
i
g g ,
v
c
~
c
(4-172)
where
b
, which we reference as a bulk modulation factor, is
( ) ( )
ox A s
b
ox
F bsQ F bsQ
V T qN
.
2 2V V 2 2V V
| |
= =
|

\ .
(4-173)
In arriving at the final form on the right hand side of (4-173), we have exploited (4-8) for the
body effect voltage, V
. We recall that the bulk transconductance, g

mb
, may be insignificant in
comparison to the small signal ramifications of the forward transconductance, g
m
. From (4-172)
and (4-173),
b
, and hence g
mb
, are small if the gate oxide thickness, T
ox
, is thin. We also note in
(4-173) that the small values of the bulk modulation factor arising from thin oxides are made
even smaller by increases in the quiescent reverse bias applied between from bulk to source.
Finally, the drain-source channel resistance, r
o
, in (4-168) is readily confirmed to be
Q dsQ dsatQ
d
o
ds dQ
Q
V V V
i
r 1 .
v I
+
c
~
c
(4-174)
The result shows that a large quiescent value of the channel length modulation voltage, V
Q
,
which is typified by long drawn channel lengths, L, produces a large channel resistance, r
o
. In
turn, large channel resistances imply that the drain-source port of a MOSFET emulates the volt-
ampere characteristics of an ideal voltage controlled current source. For typical values of V
Q
,
we project that a small quiescent drain current, I
dQ
, delivers a large r
o
.
4.6.2. UNITY GAIN FREQUENCY
The models of Figures (4.22) and (4.23) establish an analytical path for computing a
commonly invoked figure of merit for MOSFETs; namely, the unity gain frequency. In radial
units we symbolize this unity gain frequency metric as
T
. Although this metric offers a basis
for comparing the high frequency signal processing attributes of competing transistors and their
associated fabrication processes, its value to bracketing the achievable bandwidths and response
speeds of MOSFET circuits is dubious. Recall that we argued this point when we investigated
the unity gain frequency properties of bipolar junction transistors. The very definition of the me-
tric causes doubts as to its circuit level propriety. In particular,
T
is the signal frequency at
which the magnitude of the small signal, short circuit current gain of a common source amplifier
degrades to unity. The circuit of relevance is the topology of Figure (4.24a), in which a current

- 381 -
signal, I
s
is applied to the gate of a MOSFET whose source and bulk terminals are grounded.
The inductive radio frequency choke (RFC) offers a conduit for establishing a gate-source bias,
V
gsQ
, above threshold, while providing an impedance in series with the gate biasing voltage that
is large enough to cajole the injection of most of the input signal current directly into the transis-
tor gate.

Figure (4.24). (a). Common source MOSFET configured for evaluating the unity gain frequency,
T
, of
the transistor. (b). Small signal, high frequency equivalent circuit of the network in (a).
An input current applied to a gate port that behaves as an open circuit to low frequen-
cies is hardly a compelling demonstration of circuit and system rationality. This alleged
irrationality is magnified by the fact that the drain terminal, where the small signal current re-
sponse, I
da
, to input signal current I
s
is extracted, is connected directly to the power supply rail,
V
dd
. The latter connection renders the drain terminal short circuited to signal ground (hence the
nomenclature, short circuit current gain). In other words, the current gain, I
da
/I
s
, is computed
for a common source amplifier whose gate is driven by signal current and whose drain is short
circuited to signal ground, which is hardly a viable amplifier. Analog circuit viability
notwithstanding, we should nonetheless understand that the unity gain frequency metric does
convey at least limited information about the transistor we choose to examine. In particular, the
forward bias invoked across the gate-source terminals of a MOSFET manifests strong inversion
at the oxide-semiconductor interface. In turn, the supply line bias, V
dd
, encourages the transport
of free charge carriers in the inverted channel of an NMOS device from the source to the drain,
thereby yielding a drain current response to the signal excitation applied to the gate. By operat-
ing the drain at signal ground, we understand that two engineering circumstances prevail. First,
we perceive the observed drain current as a maximum current response since the current divider
realized between the short circuited drain load and the channel resistance is precisely unity.
Second, we suspect that the speed at which carriers are transported from the source to the drain is
similarly maximized in that any bulk-drain or other capacitances prevailing at the drain site are
shorted to ground. In general, these capacitances cannot be charged instantaneously by finite
currents that roll through them. But no time is required to charge a short circuited capacitor.
Thus,
T
effectively comprises a measure of an optimized transit time required of free carriers to
traverse the inverted channel. In short, the inverse of
T
is effectively the idealized carrier tran-
sit time trough the inverted channel of a considered transistor. The metric,
T
, is especially prac-
tical when it is used to compare competing MOSFETs or MOSFET processing technologies for
in effect, it defines the fastest possible time at which a transistor can respond to applied excita-
tion at the gate port.
I +I
dQ da

V
gsQ

R
F
C
+V
dd
I
s
S
I
da
I
s
g V
m ga
r
o
+ V
ga
+ V
ba G
D
B
(b).
C
gs
C
gd
r
g
(a).
S

- 382 -
Assuming that the transistor at hand operates in saturation, the small signal equivalent
model of the circuit in Figure (4.24a) is the structure given in Figure (4.24b). Because the drain,
in addition to the bulk and the source, is grounded for signal conditions, the current gain, I
da
/I
s
,
tacitly ignores the high frequency effects of bulk-drain and bulk-source transistor capacitances.
Moreover, the connection of the bulk terminal to the source, which renders signal voltage V
ba

null, obviates the need for the bulk transconductance generator,
b
g
m
V
ba
, in the model. Addition-
ally, short circuiting the drain terminal to the source terminal makes the channel resistance, r
o
,
superfluous. Accordingly, an analysis of the topology in Figure (4.24b) yields
da m ga gd ga
ga
s gs ga gd ga
g
I g V jC V
V ,
I jC V jC V
r
=
= + +
(4-175)
which delivers a short circuit current transfer function of
( )
( )
m g gd m
da
s
g gs gd
g r 1 jC g
I
.
I
1 jr C C
=
+ +
(4-176)
Since r
g
in (4-161) is infinitely large at zero signal frequency, the short circuit gain is seen to be
infinity at zero frequency, which is hardly shocking in that the gate behaves as an open circuit at
zero frequency. In addition, r
g
is likely to remain very large in the neighborhood of the 3-dB fre-
quency projected by this gain relationship so that
( )
da m
s
gs gd
I g
.
I
j C C
~
+
(4-177)
In (4-177), we have presumed that the frequency, g
m
/C
gd
, of the right half plane zero evidenced
in (4-176) is significantly larger than the aforementioned 3-dB bandwidth
8
. This presumption is
tantamount to neglecting the gate to drain feedforward through the gate-drain overlap capacit-
ance, C
gd
, in comparison to the I/O feedforward promoted by the transistor transconductance, g
m
.
While this approximation is arguably dubious at very high signal frequencies, the approxima-
tions leading to (4-177) allow us to extrapolate
m
T T
gs gd
g
2f
C C
= =
+
(4-178)
as the value of the unity gain frequency. It is important to reiterate that f
T
is a highly optimistic
estimate of achievable circuit performance, for it pertains expressly to the special case of a drain
that is short circuited to the source terminal. This short circuit quashes the impact on circuit
bandwidth of bulk-drain and any load capacitances
Using previously developed expressions for transconductance and pertinent device
capacitances, the reader can confirm the following alternative expression for the unity gain fre-
quency:

8
Care should be exercised when asserting g
m
>> C
gd
in the neighborhood of the current gain 3-dB bandwidth, for
deep submicron transistors. In particular, the forward transconductance is somewhat anemic for reasonable drain
currents in these device types, and gate-self alignment, which ideally achieves C
gd
= 0 in saturation, is imperfect.

- 383 -
( )
( )
n gs h
T T
gso gdo
2
ox
3 V V
2f .
3 C C
2L 1
2LC
= ~
(
+
(
+
(

(4-179)
This relationship reasonably reflects a direct dependence of the unity gain frequency on free car-
rier mobility. The result also infers that to the extent that 2LC
ox
>> 3(C
gso
+ C
gdo
), which may
indeed be an engineering stretch for minimal geometry, deep submicron devices, f
T
is inversely
proportional to the square of channel length. A significant increase in f
T
is therefore realized by
even a relatively modest trimming of the channel length. The fact that the unity gain frequency
is common corporate banter in the marketing of state of the art transistors arguably renders
understandable the widespread device processing penchant for progressively decreased channel
lengths.
With the gate resistance, r
g
, presumed very large over the signal frequency range of
interest, the resultant short circuit current gain in (4-177) is dependent on only frequency-inva-
riant small signal transistor parameters. Equation (4-178) therefore allows (4-177) to be genera-
lized in the complex frequency domain as,
da T
s
I
.
I s
~ (4-180)
Moreover, the model in Figure (4.23b) reduces to the equivalent circuit shown in Figure (4.25a),
where signal current I
ga
is identified as the current conducted by the gate-source capacitance, C
gs
.
Since signal voltage V
ga
is clearly I
ga
/sC
gs
, we can equate the voltage controlled current, g
m
V
ga
,
to current I
ga
as
( )
T gs gd ga
m ga g T
m ga ga
gs gs
C C I
g I k
g V I ,
sC sC s
+
| |
= = =
|
\ .
(4-181)
where
gd
g
gs
C
k 1 .
C
= + (4-182)
Equation (4-181) allows the voltage controlled current source form of the model shown in Figure
(4.25a) to be transformed into the alternative current controlled structure appearing in Figure
(4.25b). The latter form proves useful in assessing the performance of amplifiers, such as certain
forms of low noise bandpass structures, which utilize source terminal inductive degeneration.
4.7.0. DESIGN-ORIENTED ANALYSIS
When MOSFETs are exploited for linear analog signal processing applications, an ini-
tial design requirement entails the implementation of predictable biasing that is reproducible
across the chip and from chip to chip. Generally, this biasing must ensure that for all relevant
signal levels, each transistor used to supply gain, impedance conversion, constant current, con-
stant voltage, or other linear signal processing properties operates in its saturated domain where
its drain-source voltage, V
ds
, is at least as large as its drain saturation voltage, V
dsat
. When V
ds

V
dsat
, (4-140) is the applicable relationship for ascertaining a gate-source voltage, V
gs
,
commensurate with a target drain current, I
d
, conducted at a given or desired value of drain-
source voltage, V
ds
.

- 384 -

Figure (4.25). (a). Small signal MOSFET equivalent circuit in which the forward transconductance
derives from a voltage controlled current source directed from drain to source termin-
als. (b). Alternative form of the small signal MOSFET model. The voltage con-
trolled current source directed from drain to source terminals is supplanted by a cur-
rent controlled current source, where the controlling current is the small signal current
conducted by gate-source capacitance C
gs
.
Unfortunately, academic contentment does not commonly accompany the engineering
reality that underlies predictable, reliable, and reproducible integrated circuits. For the biasing
issue at hand, (4-140) is fraught with peril. One problem is that owing to a variety of analytical
liberties exploited with respect to charge storage, charge transport, carrier mobility, and the other
phenomenological issues, (4-140) is only an approximation and indeed, a cumbersome one of
the static volt-ampere characteristics of a MOSFET operated in saturation,. Even if (4-140) were
a supremely accurate disclosure of the aforementioned static characteristics, challenges surround
its utilization because circuit and system designers are rarely privy to the physical and process
parameters on which the metrics, K
n
, V
h
, V
dsat
, V
ve
, V
le
, and V
, can be based analytically.

4.7.1. ALTERNATIVE VOLT-AMPERE EXPRESSION
On the tacit presumption that the foregoing six model variables can be extracted
satisfactorily from measurement and/or simulation, (4-140) might be supplanted by the more
compact relationship,
( )
2
ds dsat
d n gs h
V V
I V V 1 ,
V
| |
= +
|
\ .
(4-183)
where
n
symbolizes the voltage-dependent, effective NMOS transconductance coefficient,
S
I
da
I
gs
I
ga
g V
m ga
g V
mb ba
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(a).
C
gs
C
bd
C
bs
C
gd
S
I
da
I
gs
I
ga
g V
mb ba
r
o
+ V
ga
G S
D
V +
ba
I
ba
B
+
V
da
(b).
C
gs
C
bd
C
bs
C
gd
I
ga
k
g T
s
( )

- 385 -
2
n n
sat
n
gs h
gs h gs h
ve
ve le
K K W W
M
2 L 2 L
.
V V
V V V V
1
1 1 0.78
V
V V
| | | |
| |
\ . \ .
= ~
( | | | |
+
+ +
( | |
\ . \ .
(4-184)
Of course, (4-183) is valid only for gate-source voltages, V
gs
, satisfying V
gs
V
h
. Moreover, it is
to be understood that for a fixed bulk-source voltage, V
bs
, threshold voltage V
h
is taken as a con-
stant in the preceding two relationships. This modeling tack is an approximation in that for ac-
tual short channel MOSFET devices, we have witnessed that DIBL serves to decrease slightly
the threshold voltage as a function of drain-source voltage V
ds
.
The effective transconductance parameter,
n
, postured by (4-184) accounts for mobil-
ity degradation deriving from strong vertical (gate to channel) electric fields through the variable,
V
ve
. It also embraces mobility degradation caused by lateral (drain to source) electric fields, as is
monitored by variable V
le
. While (4-183) suggests a relatively straightforward square law depen-
dence of drain current on the so called excess, or effective, gate-source voltage, (V
gs
V
h
),
particularly for the commonly encountered situation of (V
ds
V
dsat
) << V
, we must recognize
that coefficient
n
is inversely proportional to a quadratic function of the excess gate-source vol-
tage. Typically, V
ve
is of the order of two to twenty fold the value of V
le
and thus, the guaranteed
simplification of (4-184) to ease computational strain, while preserving modeling realism, is du-
bious.
EXAMPLE #4.5:
An NMOS transistor featuring a channel length of 0.5 m has the Level 3
HSPICE parameters itemized in Table (4.1). The transistor is to be biased
in saturation at V
ds
= 4.5 volt and I
d
1 mA to achieve a forward
transconductance of at least 4.0 mmho. Assume that the bulk terminal is
incident with the transistor source terminal. Choose a reasonable gate as-
pect ratio, W/L, which is required to achieve the 1 mA drain current target,
determine the required gate-source voltage bias, V
gs
, and estimate the
model parameters implicit to (4-183) and (4-184).
SOLUTION #4.5:
(1). The applicable circuit for computer-aided investigation is offered in Figure (4.26). The
transistor model parameters are itemized in Table (4.1), and the gate aspect ratio, W/L, is to
be determined. The null voltage source in the drain circuit of the device facilitates the extrac-
tion of the static drain current, I
d
. It is understood that for biasing purposes, the area and
perimeter parameters, A
s
, A
d
, P
s
, and P
d
, are inconsequential and can therefore be defaulted to
any convenient value. Initially, set V
gs
= 1 volt, W/L =1 and, of course, V
ds
= 4.5 volt.
The HSPICE static simulation reveals I
d
= 14.49 A, V
dsat
= 336.4 mV, V
h
= 594.6 mV, and
g
m
= 57.02 mho. Since V
gs
= 1 volt is larger than the threshold potential, V
h
= 594.6 mV,
and V
ds
= 1 volt exceeds V
dsat
= 336.4 mV, the transistor is clearly turned on and operates in
its saturated domain.
(2). With W/L = 1, the simulated drain current is a factor of 69.01-times smaller than the target
current of 1 mA. Assuming that V
gs
= 1 volt is to be sustained, this observation suggests the
need for increasing the gate aspect ratio from 1 to 69.01 in that the drain current is propor-
tional to W/L. Given L = 0.5 m, gate width W is W = (69.01)(0.5 m) = 34.51 m.

- 386 -

Figure (4.26). Circuit structure for the biasing simulation re-
quired of Example #4.5. The Level 3 HSPICE
parameters of the transistor appear in Table (4.1).
With W/L = 69.01, V
gs
= 1 volt, and V
ds
= 4.5 volt, HSPICE delivers I
d
= 1.146 mA, V
dsat
=
367.1 mV, V
h
= 566.0 mV, and g
m
= 4.21 mmho. If V
gs
is reduced to 970 mV, HSPICE pro-
duces I
d
= 1.021 mA, V
dsat
= 346.1 mV, V
h
= 566.0 mV, and g
m
= 4.04 mmho. The
transconductance satisfies the design requirement, and for government work, 1.021 mA is
close enough to a drain current of 1.0 mA. Thus, the design requirement is satisfied for
W/L = 69.01, V
gs
= 970 mV, and V
ds
= 4.5 volt.
(3). The model parameterization exercise begins by using (4-142) to compute the voltage, V
ve
.
From Table (4.1), the oxide thickness is T
ox
= 6(10
9
) meters, which is 60 . Accordingly,
V
ve
= 60/27 = 2.22 volts.
(4). The next step in the parameterization process entails operating the subject transistor at a
drain-source voltage that is close to the drain saturation voltage, V
dsat
= 346.1 mV, at which
the design requirements are satisfied. This tack reduces the last parenthesized factor on the
right hand side of (4-183) to unity, thereby simplifying the computation of the effective
transconductance parameter,
n
.
With W/L = 69.01, V
gs
= 970 mV, and V
ds
= V
dsat
= 346.1 mV, HSPICE produces I
d
= 844.20
A and V
h
= 609.2 mV. Although HSPICE currently delivers a threshold potential of 609.2
mV, V
h
is nonetheless held fast at 566.0 mV (the threshold level at the desired operating point)
since (4-183) is predicated on the presumption of constant V
h
. Thus, (4-183) surrenders
parameter
n
as
n
= 5.172 mmho/volt.
(5). Recalling that V
dsat
= 346.1 mV and (V
gs
V
h
) = (0.970 0.566) volts = 0.404 volts at the de-
sired operating point, (4-132) delivers M
sat
= 0.8567. The exact form of (4-132) can be
solved directly for corresponding parameter to yield
( )
sat
2
sat
2 1 M
0.3906 .
M
= = (E5-1)
Using (4-129), voltage metric V
le
follows as V
le
= 4.03 volts.
(6). With
n
= 5.172 mmho/volt, V
ve
= 2.22 volts, M
sat
= 0.857, V
gs
= 970 mV, V
h
= 566.0 mV, and
W/L = 69.01, the device transconductance parameter, K
n
, follows from (4-184) as K
n
= 244.4
mho/volt. In an attempt to lend credence to this calculation, recall that parameter K
n
is the
product of electron mobility and oxide capacitance density. This is to say that K
n
=
n
C
ox
,
with C
ox
= c
ox
/T
ox
= (345)(10
15
)/(600)(10
9
) = 575 nF/cm
2
. Then
n
= K
n
/C
ox
=
(270.0)(10
6
)/(575)(10
9
) = 419.8 cm
2
/volt-SEC, which is a reasonable estimate of the free
electron mobility in the inverted channel of the subject NMOS device. Typically, this elec-
tron mobility falls within the range of 350 to 500 cm
2
/volt-sec.
(7). In principle, V
ve
, V
le
, V
h
, V
dsat
, K
n
, and thus
n
, do not vary with changes in the drain-source
voltage, V
ds
. This premise implies that the ratio of the drain current (1.021 mA) for V
ds
= 4.5
+

V
gs

V
ds

I
d
0
W
/
L

=

?

- 387 -
volt to the drain current (844.20 A) at V
ds
= V
dsat
= 346.1 mV is solely attributed to the last
parenthesized factor on the right hand side of (4-142); that is,
ds
ds dsat
d
V 1.5 V
ds dsat
d
V V
I
V V 1.021mA
1.209 1 .
I 844.20 A V
=
=
= = = + (E5-2)
Thus, the channel length modulation voltage computes to be V

= 5.51 volts.
(8). In an attempt to demonstrate the propriety of the foregoing modeling exercise, the forward
static transfer characteristic of the subject transistor are modeled in HSPICE for V
ds
= 4.5
volts. The simulated results are then compared with parametric calculations using the com-
puted values of V
ve
, V
le
, and V
and the simulated disclosures for W/L and V

h
. Specifically, V
ve

= 2.22 volts, V
le
= 4.03 volts, V
= 5.51 volts, W/L = 69.01, and V

h
= 566.0 mV.
Figure (4.27) displays the results of the foregoing comparative study for V
ds
= 4.5 volt. The
calculations corroborate reasonably well with pertinent simulations in that less than 16% er-
ror is observed for 0.670 volt < V
gs
< 2.00 volts, which corresponds to a simulated drain cur-
rent range of 0.126 mA < I
d
< 7.34 mA. The error peaks to slightly less than 16% at a static
drain current of I
d
= 4.28 mA.

Figure (4.27). Simulated and calculated static characteristics curves for the MOSFET addressed in
Example #4.5. The drain-source voltage, V
ds
, is held constant at 4.5 volts.
In the second step of the foregoing computational procedure, the gate aspect ratio, W/L, func-
tions as the pivotal metric for achieving the desired transistor drain current and transconduc-
tance. If power dissipation is a design concern, W/L can be increased above the value of
69.01 discerned in this example, with the understanding that the gate-source voltage, V
gs
, can
be reduced commensurately. This tack reduces the static drain current and hence, the power
dissipation of the transistor. Of course, the primary disadvantage of a large gate aspect ratio
is a possible degradation of high frequency circuit response since the capacitance area and
periphery dimensions increase in proportion to the gate width, W.
In Step #3, the metric, V
ve
, is evaluated in terms of a purely empirical, and indeed crude first
order, relationship to the oxide thickness, T
ox
. A possible way around this dilemma is to com-
pute V
ve
and other requisite modeling parameters by curve fitting (4-183) to simulated or
measured static data. While this approach may be academically satisfying, it may be
imprudent from the perspective of design time. Keep in mind that biasing is not the
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Gate-Source Vol tage V
gs
(V)
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d

(
m
A
)
Simulated
Calculated

- 388 -
fundamental performance objective of an analog circuit design venture. Instead, biasing is
the necessary condition that supports the establishment of creative network topologies that
deliver desired dynamic responses.
The drain-saturation voltage, V
dsat
, is a nonlinear function of the excess gate voltage, (V
gs

V
h
), owing to the parameter, M
sat
. But in addition, V
dsat
changes slightly with the applied
drain-source voltage, V
ds
. Indeed, SPICE model parameters for Levels 3 and above account
for DIBL. Such an account is proper in that the interface potential throughout the entire
channel varies somewhat as a function of the charge stored in the depletion field prevailing
on the channel side of the drain volume perimeter.
It should be noted that the computed value of the channel length modulation voltage, V
=
5.51 volts, is appreciably smaller than values commonly propounded in the literature. How-
ever, V
is indeed a relatively small voltage for submicron MOS technology transistors. This
anemic voltage is the principle cause of correspondingly small drain-source channel resis-
tances. In turn small channel resistance makes the realization of high performance
transconductor amplifiers a daunting challenge. The desire for accuracy surrounding the
enumeration of V
is exacerbated by the fact that parameter V
is not the constant that is

presumed tacitly in the foregoing demonstration. Instead, and as is confirmed by (4-116), V

is functionally dependent on drain-source voltage, drain saturation voltage, and threshold vol-
tage. If V
or the drain-source channel resistance is critical in an analog circuit design endea-

vor, care must be exercised to ensure that model parameters are extracted in terms of meas-
ured or simulated data that largely mirror the desired or expected operating state of the
utilized transistor.
4.7.2. CIRCUIT DESIGN PHILOSOPHY
The lesson advanced by Example #4.5 and the modeling disclosures of preceding sec-
tions is that MOSFET design strategies that couch analog circuit performance as sensitive func-
tions of device parameters may be fraught with peril. The problem at hand is that many of the
parameters indigenous to the MOSFET device models discussed herein, and most of the parame-
ters implicit to the advanced EKV, BSIM, and other high order models of short channel transis-
tors, are hardly carefully controlled and attentively monitored. Moreover, the numerical values
of these model parameters often display a disconcertingly strong dependence on the current and
voltage levels at which transistors operate. In other words, the values of certain device parame-
ters unfortunately depend on the voltage and current levels at which measurements are taken. An
additional issue is that the lack of deterministic parametric relationships to controllable physical
phenomena all but prohibits most device parameters to be adjusted accurately as a function of
geometric scaling factors that routinely serve as designable circuit variables. This latter fact is
arguably the reason that process foundries generally supply different SPICE models for substan-
tially different geometries of the same basic transistor. Consequently, analytical uncertainties
implicitly accompany MOSFET circuit design strategies that are necessarily predicated on mod-
els that may not deterministically reflect fundamental semiconductor phenomena. These
uncertainties are exacerbated as device geometries continue to shrink to meet packing density,
power dissipation, and data and information processing requirements.
In view of inescapable modeling shortfalls, circuit design that is directed toward
minimizing circuit performance dependencies on at least the most dominant of device parameters
is laudable. Unfortunately, such a design scenario cannot always be straightforwardly executed.
In these cases, complementary design measures are adopted. Included among these subsidiary
procedures are behavioral system level simulations whose results can identify the simplest, and
thus generally, the most reproducible circuit level architectures appropriate to the reliable

- 389 -
realization of targeted circuit or system performance. Once the base line forms of these architec-
tures are established with the aid of relatively simple and mathematically tractable device mod-
els, they must undergo extensive computer-based simulations to assess the accuracy and
reproducibility of requisite circuit performance in the face of parametric uncertainties and
process vagaries. Stated quite simply, circuit performance achieved for only nominal device
parameter sets is insufficient. Instead, the desired circuit performance must be achieved despite
realistic variations in processing variables that the foundry or the design engineer is able to antic-
ipate. The circuit and system performance assessment executed in the wake of these simulations
invariably lead to circuit design modifications. They often even portend the need to adopt
topological corrections that neutralize or mitigate the impact of unavoidable uncertainties. Some
of these corrective measures are as simple as an adjustable biasing port incorporated on the chip.
More advanced corrections may entail the use of embedded digital microcontrollers or even off
chip microprocessors. Yet another design tack incorporates, when sufficient chip surface area
exists, test cells that may include individual transistors, simplified versions of circuits incorpo-
rated in the design, or even the entire version of especially critical subcircuits. These test struc-
tures allow for satisfying independent laboratory investigations that can germinate refined circuit
level models. The fruits of analyses predicated on these updated models can adjudicate perfor-
mance shortfalls, and they can pave analytical paths toward realistic performance optimization
measures.
At the risk of further depressing the neophyte circuit designer, the neutralization of the
effects of model parameter uncertainties is but one of several other issues that diligent circuit
designers must confront proactively. For example, the power supply rejection, (PSR), which
quantifies the degree to which circuit performance is dependent on the power line voltage, must
be examined. This examination is especially critical for portable electronic systems since battery
voltages naturally degrade with time. For example, we would not be happy with an iPod, a cell
telephone, or portable GPS unit that ceases to function when the battery voltage diminishes by a
mere 10% or so. The solution entails biasing cells that reduce and, within reasonable ranges of
power line voltages, eliminate a direct dependence of quiescent transistor operating points on
power supply voltage.
A second problem surrounding the power supply is transient response to sudden system
turn on. In many chips, the unfortunate progeny of power bus routing among many circuits and
subcircuits, some of which may embody both analog and digital networks, is significant parasitic
inductances in the power line. These inductances interact with device and layout capacitances to
incur potentially damaging voltage overshoots immediately subsequent to system turn on. In this
case, mitigation entails the incorporation of appropriate decoupling filters that isolate critical ac-
tive cells from excessive voltage and current transients. It may also require the utilization of spe-
cially designed startup circuits that effectively bound the potentially excessive transients to
which critical cells might otherwise be exposed. Yet another problem associated with the power
line is electrical noise that is parasitically coupled to it by robust voltage swings in proximately
located circuit cells and particularly, in digital subcircuits. A rectification of this issue entails
suitable filters or even a revised circuit layout that distances the power lines connected to critical
circuits from those subcircuits that serve as the source of noise.
Numerous other predicaments abound. For example, the circuit design may inappro-
priately exploit large resistances. These resistances may prove difficult to reproduce accurately
during processing, and they may produce thermal noise that degrades the ability of an input stage
to detect faithfully low levels of input signals. In some systems, the value of the signal source

- 390 -
resistance or the load resistance terminating the output port may be unknown or unreliable. In
these cases, the achievable voltage gain, current gain, power gain, bandwidth, and/or other
performance metrics may be affected. The source resistance is especially troublesome in radio
frequency applications since maximum signal power transfer between signal source and am-
plifier input port often commands an effective source resistance that differs from the source
resistance value that is commensurate with acceptable levels of noise.
The upshot of the matter is that the creative design of reliable and reproducible elec-
tronic networks comprises a genuinely difficult engineering undertaking. The good news is that
a design solution is never unique. It is good news because finding the small handful of appropri-
ate or possibly near optimal circuit solutions presents us with opportunities to exercise and flaunt
our design creativity, which is why circuit engineers command big buck salaries. One or more of
this handful of solutions may or may not be approach optimality in the strictest of mathematical
senses. Instead, these solutions may derive from realistic and reasonable engineering compro-
mises, wherein certain of the attributes of one or more performance metrics are traded to ensure
the acceptability of other network responses. The bottom line is that the suitability or apparent
optimality of a particular design proposal cannot be assessed satisfactorily without executing
definitive manual, computer-based, and/or laboratory-oriented analyses whose fruits are in-
sightfully understood and then creatively applied.
4.7.3. CIRCUIT EXAMPLE
A first circuits example that harmonizes with the philosophical testimony in the preced-
ing subsection is afforded by the commonly used biasing subcircuit diagrammed in Figure
(4.28a). Because the gate and drain terminals of transistor M1 in the subject circuit are con-
nected together, M1 always operates in saturation. This common drain-gate connection of a
transistor is often referred to as a diode-connected transistor. This reference is proliferated in the
archival literature despite the fact that the subject connection makes a terrible diode. Specifi-
cally, the diode-connected transistor advances the approximate square law I-V characteristic
curve,
( ) ( )
2 2
n gs1 h n ref h
I V V V V . ~ = (4-185)
whose slope, dI/dV
gs1
, is far smaller than the current versus voltage slope of a stereotypical PN
junction diode. In deference to the saturated nature of M1, (4-183) is the actual relationship for
the indicated current, I, which flows through circuit resistance R. But since the M1 drain-source
voltage, which is the indicated reference output voltage, V
ref
, is obviously identical to the gate-
source voltage of transistor M1 and is therefore relatively small, CLM is likely inconsequential.
It follows that (4-183) for the indicated current, I, which also equates to the drain current under
static conditions, is acceptably represented by the simplified relationship in (4-185).
The connection of the bulk to the source in transistor M1 obviates any BITM. There-
fore, the threshold voltage, V
h
, is theoretically constant (ignoring DIBL phenomena), indepen-
dent of device voltage levels. Kirchhoff is placated if I in (4-185) satisfies
dd ref
V V
I .
R
= (4-186)
Combining the preceding two expressions and applying the venerable quadratic formula results
in an output voltage, V
ref
, of

- 391 -

Figure (4.28). (a). Schematic diagram of a simple biasing circuit. (b). Alternative biasing architecture in
which circuit resistance R in (a) is replaced by a constant current source, I. (c). Circuit
illustrating the use of the network in (b) in a current mirroring application.
( )
n dd h
ref h
n
1 4 R V V 1
V V .
2 R
+
= + (4-187)

Figure (4.29). Static voltage response of the biasing circuit shown in Figure (4.28a).
Figure (4.29) plots (4-187) and in the process, it overviews the predicted static re-
sponse, V
ref
, of the circuit as a function of the power supply voltage, V
dd
. Parameter
n
in (4-187)
is, of course, a voltage dependent variable whose precise numerical value is elusive. Accor-
dingly, it is desirable that output voltage V
ref
be rendered as independent as possible of parameter
n
, as well as being desensitized to the supply voltage, V
dd
. The plots in Figure (4.28) indicate
that V
ref
is markedly sensitive to V
dd
if the product,
n
R, is small. Indeed, (4-187) confirms that
in the limit of very small |
n
R, V
ref
converges to the actual supply line voltage, V
dd
. On the other
hand, large
n
R results in a reduced sensitivity of V
ref
to V
dd
. For example, with |
n
R = 10, a 50%
reduction in (V
dd
V
h
) from 4 volts to 2 volts results in a 34.6% attenuation of (V
ref
V
h
). While
this sensitivity is hardly anything to text home about, it does offer better results than does the
case of
n
R = 0.2 for which we compute a corresponding sensitivity of (V
ref
V
h
) to (V
dd
V
h
)
I
R
+V
dd
V
ref
(a).
I I
I I
+V
dd
+V
dd
V
ref
(b).
V
ref
V
kk
(c).
I
2
M1 M1
M2
W/L
kW/L
M1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
dd
V
h
, (volts)
V
ref
V
h
, (volts)

- 392 -
of 44.6%. The fact that the output voltage sensitivity to power supply voltage worsens with
diminished values of the product,
n
R, hardly evokes astonishment. In particular, Figure (4.28a)
shows that for progressively smaller resistances, R, V
ref
converges to the line voltage, V
dd
,
whence a change in V
dd
is mirrored directly by V
ref
. This circuit-level observation is confirmed
by (4-187) in that
( )
( )
n
n dd h
ref h dd h
R 0
n
1 2 R V V 1
V V V V .
2 R
+
~ = (4-188)
For the case of a very large circuit resistance, R, in Figure (4.28a), the current, I, be-
comes very small, which implies, with the help of (4-187), that voltage V
ref
approaches the
transistor threshold potential, V
h
. With resistance R large, (4-187) yields
( )
( )
n dd h
dd h
ref h
R
n n n
2 R V V 1
V V I
V V .
2 R R

~ = = (4-189)
This disclosure suggests the alternative architecture in Figure (4.28b), where I is understood to
be a constant, independent current source. Voltage V
ref
in this relationship is still influenced by
the vagarious parameter,
n
, but now, we note that V
ref
is independent of voltage V
dd
. Of course,
such independence prevails only as long as V
dd
is large enough to sustain constant current in cur-
rent source I.
The circuit cell in Figure (4.28b) comprises a foundation for the so-called current mir-
ror circuit in Figure (4.28c). In this case, the design objective is the realization of a reliable and
reproducible current, I
2
, as opposed to targeting a suitable voltage, V
ref
, which now serves merely
to activate transistor M2. In the circuit diagram, the two transistors, M1 and M2, are identical,
save for the fact that the gate aspect ratio of transistor M2 is a factor of k larger than that of
transistor M4. Observe that the bulk terminals of both devices are incident with their respective
source terminals and that the gate-source voltages (V
ref
in this case) applied to both devices are
identical. The drain terminal of M2 need not be connected to the line voltage, V
dd
and, in fact, it
is preferably incident with a circuit node that supports a voltage, V
kk
, which is smaller than V
dd
.
Recalling that parameter
n
is directly proportional to gate aspect ratio, it follows from (4-183)
that the current, I
2
, is given by
( )
2
kk dsat kk dsat
2 n ref h

V V V V
I k V V 1 k I 1 ,
V V
| | | |
= + = +
| |
\ . \ .
(4-190)
where we have used (4-185). Suppose that the node voltage, V
kk
, is sufficiently close to the drain
saturation voltage, V
dsat
, of the device and/or long channel lengths are selected for each of the
two transistors. In the latter case, a large CLM voltage, V
, materializes. In either event, we

have
kk dsat
V V
1 ,
V
<< (4-191)
and (4-190) collapses to
kk dsat
2
V V
I k I 1 k I .
V
| |
= + ~
|
\ .
(4-192)
In other words, the desired current response, I
2
, is simply a scaled version of current I, where the
scaling factor, k, is a highly predictable and controllable ratio of transistor gate aspect ratios. In
effect, (4-192) asserts that the accurate control of current I
2
boils down to controlling current I,
which flows into diode-connected transistor M1. It is intriguing that current I
2
in (4-192) is

- 393 -
independent of transistor transconductance metric
n
. And to the extent that current I derives
from a presumably ideal source of current, output current I
2
is invariant with line voltage V
dd
.
Two teachings surface from the foregoing design considerations. The first of these is
that it is important to execute the design prudently so that voltage V
kk
is not substantially larger
than voltage V
ref
. Note, for example, that the gate-source voltages applied to transistors M1 and
M2 are identically equal to voltage V
ref
. In addition, the drain-source voltage applied to M1 is
also V
ref
, while the drain-source bias energizing M2 is voltage V
kk
. It follows that the closer vol-
tage V
kk
is to voltage V
ref
, the more accurate is the current mirror undergoing design. Second, it
is important to ensure that reference current I derives from a current source whose performance
is good in the sense that its current is nominally independent of line voltage and physical transis-
tor parameters. The latter observation justifies the common (but not universal) design practice of
realizing current source I off chip. Off chip, off the shelf transistors have significantly larger
geometries (inclusive of drawn channel lengths) than do their monolithic counterparts. Resul-
tantly, they can be realized and implemented with very large shunt resistances. The result of
these carefully executed design tactics is a biasing current, I
2
, which is consummately predicta-
ble, reliable, and reproducible. Much more ore information about MOSFET biasing is presented
in the next chapter.
4.8.0. REFERENCES
[1]. C. C. Enz, F. Krummenacher, and E. A. Vittoz, An Analytical MOS Model Valid in All Re-
gions of Operation and Dedicated to Low-Voltage and Low-Current Applications, Journal of
Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, 1995.
[2]. C. C. Enz and E. A. Vittoz, Basic Charge-based MOS Transistor Modeling. New York: John
Wiley & Sons, Ltd., 2006.
[3]. P. R. Gray, Basic MOS Operational Amplifier Design-An Overview, in Analog MOS Inte-
grated Circuits. New York: IEEE Press, 1980, pp. 28-49.
[4]. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: Oxford University
Press, 2002, pp. 396-402.
[5]. H. Schichman and D. Hodges, Modeling and Simulation of Insulated-Gate Field-Effect
Transistor Switching Circuits, IEEE J. of Solid State Circuits, vol. SC-3, pp. 285-289, 1968.
[6]. W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4. New York:
Wiley Interscience, 2001, pp. 247-252 and p. 256.
[7]. B. Gilbert, A Precise Four-Quadrant Multiplier With Subnanosecond Response, IEEE Jour-
nal of Solid-State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.
[8]. B. Gilbert, A High Performance Monolithic Multiplier Using Active Feedback, IEEE Journal
of Solid-State Circuits, vol. SC-9, pp. 364-373, Dec. 1974.
[9]. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons,
1997, pp. 24-27.
[10]. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits (2
nd
Ed.). Cambridge,
United Kingdom: Cambridge University Press, 2004, pp. 189-190.
[11]. S. R. Hofstein and G. Warfield, Physical Limitation on the Frequency Response of a
Semiconductor Surface Inversion Layer, Solid State Electronics, vol. 8, p. 321, 1965.
[12]. T. H. Lee, ibid. chapters 11, 12.
[13]. A. van der Ziel, Noise in Solid State Devices and Circuits. New York: John Wiley & Sons, Inc,
1986.
[14]. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Techniques for Analog and Digital Circuits.
New York: McGraw-Hill Publishing Company, 1990, pp. 174-177.


- 394 -
EXERCI SES
PROBLEM #4.1
A particular n-channel MOSFET has a bulk impurity concentration of 5(10
14
) atoms/cm
3
and oper-
ates at a bulk-source reverse bias of 2.0 volts. For gate oxide thicknesses of 50 , 100 , and 200
, plot the body effect shift in threshold voltage as a function of the oxide-bulk semiconductor
interface temperature for temperatures in the range of 0 C to 125 C. Comment on the observed
temperature sensitivity of the threshold shift in light of a transistor whose zero bias threshold vol-
tage is 500 mV. Assume that the intrinsic carrier concentration, n
i
, relates to operating temperature
T in accordance with the empirical disclosure,
( )
( )
( ) T 300.16 10 10
i
n 4.5 10 2 ,
(
=
(

where T in Kelvin degrees returns n
i
is units of atoms/cm
3
. Note that this expression projects a
doubling of the intrinsic concentration for every 10 C rise in temperature.
PROBLEM #4.2
An NMOS transistor has a gate oxide thickness of 80 and operates at room temperature. Plot the
body effect shift in threshold potential as a function of bulk-source reverse biases that vary from 0
volt to 5 volts for bulk impurity concentrations of 10
14
atoms/cm
3
, 10
15
atoms/cm
3
, and 10
16

atoms/cm
3
. Comment as to the observed dependence of the body effect shift in threshold voltage
on bulk impurity concentration.
PROBLEM #4.3
The Debye length, D
b
, is a characteristic length in semiconductors that relates to the volumetric re-
gion over which the field intensity of an electron can be observed. In NMOS this length is given
by
s T
b
A
V
D .
qN
=
Express the body effect voltage, V
u
, as an explicit function of the Debye length.
PROBLEM #4.4
Review Example (4.1), which addresses the nature of the subthreshold volt-ampere characteristic
for a particular NMOS transistor. As is suggested in the Engineering Commentary of this exam-
ple, a simple modification to the fundamental volt-ampere relationship of (4-18) can be contrived
to account, albeit to first order, for the relevant effects of drain-source bias. Study the subject
example carefully to see if you can deduce this modification. Give an analytical expression for the
resultantly modified volt-ampere characteristic in the subthreshold regime.
PROBLEM #4.5
The HSPICE Level 3 parameters for a representative NMOS transistor featuring a minimum
permissible 0.5 M channel length are itemized in Table (4.1). Using L = 2 M and W = 5 M
(and with the source and bulk terminals both grounded, use HSPICE or equivalent SPICE software
to simulate the room temperature characteristic curves, I
d
versus V
gs
for drain-source voltages, V
ds
,
of 0.5 V, 1.5 V, and 2.5 V. Using these simulated results, deduce numerical values for subthreshold
regime parameters at V
ds
= 1.5 V. Additionally, find the nominal range of gate-source voltages for
which the transistor is constrained to operate in its subthreshold regime.
PROBLEM #4.6
The HSPICE Level 3 parameters for a representative PMOS transistor featuring a minimum

- 395 -
permissible 0.5 M channel length are delineated in Table (4.2). Using L = 1 M and W = 20 M
and with the source and bulk terminals both connected to the positive supply line used to bias the
transistor, use HSPICE or equivalent SPICE software to simulate the room temperature
characteristic curves, I
d
versus V
sg
for source-drain voltages, V
sd
, of 0.5 V, 1.5 V, and 2.5 V. Using
these simulated results, deduce all subthreshold parameters used in (4-18), for V
sd
= 1.5 V. What is
the nominal range of source-gate voltages for which the transistor is constrained to operate in its
subthreshold regime?
PROBLEM #4.7
Consider a PMOS transistor whose threshold voltage (V
h
) is 650 mV and whose scaled
transconductance parameter (
p
) is 100 mho/V. Plot the common source characteristics for this
transistor and show on this plot the locus of the boundary that separates ohmic and saturation re-
gimes.
PROBLEM #4.8
Review the simulation of the network given in Figure (4.7), whose results are discussed in Section
(4.4.1). Repeat this simulation using the same data except change the power line voltage, V
dd
, to 3
V. Use the data generated by HSPICE or equivalent circuit simulation software to explain, albeit
qualitatively, any observed significant departures from I/O linearity.
PROBLEM #4.9
In the common source amplifier of Figure (4.9), assume that the quiescent voltage, V
iQ
, of the am-
plifier input port is centered in the linear region of the static transfer characteristics where both
transistors operate in their saturation regimes. Show that for such biasing, the maximum output
port signal swing, AV
omax
, and the corresponding maximum input port signal swing, AV
imax
, which
is commensurate with I/O linearity are given respectively by
( )
( )
( )
v
omax dd ho
v
dd ho
imax
v
A
V V V ,
2 A 1
V V
V ,
2 A 1
(
= (
+
(

=
+

where A
v
symbolizes the voltage gain of the amplifier at the centered Q-point.
PROBLEM #4.10
The differential amplifier in Figure (4.12) is to be designed so that it dissipates no more than 15
mW of standby power when a power supply voltage, V
dd
, of 3.7 volts is used. The quiescent vol-
tage at either of the drain output ports is to be two-thirds of the supply line voltage, while the
differential voltage gain produced by the amplifier is to be 12 dB. If device nonlinearities are to be
precluded from reducing the nominal voltage gain by no more than 1%, what is the maximum
permissible amplitude of the applied differential input signal, V
di
? If each transistor delivers
n
C
ox
/2 = 200 mho/volt, where
n
is the electron mobility in the channel of each transistor and C
ox

is the oxide capacitance density of each device, what gate aspect ratio is required of each
MOSFET?
PROBLEM #4.11
Reconsider the Gilbert multiplier in Figure (4.13) for the case when transistors M1 and M2 remain
biased in their saturation regimes, but the quad transistors, M3 through-M6, are biased for opera-
tion in their ohmic regions.
(a). Demonstrate that for this biasing mode, the differential output voltage, V
do
, is expressible as

- 396 -
( )
l x k
do x y t x y
M
R 2 I
V V V 1 V , V ,
2V
| |
(
= + |
|
\ .

where voltage V
M
is given by
( )
l x k
do x y t x y
M
R 2 I
V V V 1 V , V ,
2V
| |
(
= + |
|
\ .

In the last expression, it is understood that V
yc
is the common mode component of voltages
V
y1
and V
y2
, while V
ac
is the common mode component of the single-ended output responses,
V
a1
and V
a2
. Finally, the error function, c
t
(V
x
, V
y
), in the indicated output voltage response is
( )
2
2
y l y
x x
M k
t x y
2
y l y
M
RV
V
V 4I
V , V .
RV
1
V

In the process of arriving at the foregoing expressions, assume that the nonlinearities accrued
by V
x
and V
y
are soft, as presumed in the analysis undertaken in the text.
(b). From the perspective of nonlinearities delivered with respect to an output response that is
ideally proportional to merely the product of voltages V
x
and V
y
, what advantage does ohmic
regime biasing of the quad array enjoy over its saturation regime biasing counterpart? In
particular, determine the minimum nonlinearity error that can be achieved theoretically with
triode regime biasing.
(c). What value of tail current I
k
renders the idealized output for ohmic regime biasing of the
quad array identical to the idealized output achieved when all transistors in the Gilbert cell
operate in their saturation domains?
PROBLEM #4.12
An NMOS transistor features an average substrate impurity concentration of N
A
= (5.5)(10
14
)
atoms/cm
3
and a gate oxide thickness of T
ox
= 50 . If the zero bias threshold voltage of the device
is 600 mV, use (4-149) to evaluate and plot versus temperature the temperature coefficient, dV
h
/dT,
of the threshold voltage for bulk-source biases of V
bs
= 0 volt, 2 volts, and 3 volts. Compare
these results with the approximate temperature coefficient disclosure postured by (4-150).
PROBLEM #4.13
The NMOS transistor in Figure (P4.13) features a gate aspect ratio of q, a zero bias threshold vol-
tage of V
ho
, and a transconductance coefficient of K
n
. The applied gate-source voltage, V
gg
, is at
least as large as the transistor threshold potential.

Figure (P4.13)
(a). What steady state effect does the circuit capacitance, C, have on the drain-source voltage of
the transistor for all values of the power supply voltage V
dd
?
(b). What is the steady state drain current, I
d
, conducted by the transistor, and in what regime

V
gg

C
R
+V
dd

- 397 -
does the NMOS device operate?
(c). What net resistance, say R
n
, is established between the power supply line and circuit ground
if V
gg
= V
h
?
(d). What net resistance, say R
n
, is established between the power supply line and circuit ground
if V
gg
= 4V
h
?
PROBLEM #4.14
Analyze and simulate the static transfer characteristic, V
o
versus V
i
, of the PMOS common source
amplifier shown in Figure (4.14). Use the HSPICE parameters in Table (4.2) and let the supply
line voltage, V
ss
, be 5 volts. Assume the channel length of each transistor is 1 M and that the stage
is designed for a nominal gain of 5 volts/volt when both devices operate in their saturation do-
mains. For the analysis, use the simple Schichman-Hodges MOSFET model and ignore body ef-
fect in the load transistor.

Figure (P4.14)
PROBLEM #4.15
Repeat the simulation exercise executed in Example #4.2 with V
dd
= 5 volts and transistor channel
lengths of 5 M.
PROBLEM #4.16
Consider a PMOS transistor for which the nominal channel length is 0.18 M, the gate aspect ratio
is 50, the oxide thickness is 40 , the average impurity concentration in the bulk substrate is 10
15

atoms/cm
3
, and the average impurity concentration in the source and drain regions is (8)(10
19
)
atoms/cm
3
. With zero bias applied to the source-bulk terminals, the threshold voltage is 600 mV,
but the transistor under investigation is operated with a source to bulk bias of 2.0 volts. Generate
the static, common source, volt-ampere characteristic curves, which plot the drain current as a
function of the source-drain voltage for several values of the source-gate voltage. Assume an
operating temperature of 27 C, for which the hole mobility can be taken to be 250 cm
2
/volt-sec.
PROBLEM #4.17
Consider an NMOS transistor having a transconductance coefficient of K
n
= 350 mho/volt, a gate
aspect ratio of W/L = 20, a zero bias threshold voltage of V
ho
= 400 mV, a critical channel electric
field strength of E
c
= 4.2 volts/M, and a channel length, L = 130 nM. The transistor in question is
biased in its saturation regime with its bulk terminal returned directly to its source terminal.
(a). If channel length modulation phenomena and the effects of vertical electric fields are ig-
nored, show that in general, the small signal transconductance, g
m
, is given by
( )
d
m n d sat sat
gs sat
I 1
g 2K W L I M 1 M .
V 1 M
| | c
= +
|
c +
\ .

(b). Give a general expression for the small signal transconductance for the special case in which
the effects of lateral electric fields are tacitly ignored.
(c). Compare the exact transconductance determined in Part (a) with the approximate
M1
M2
V
o
V
i
+V
ss

- 398 -
transconductance found in Part (b) by plotting both transconductances as a function of the
drain current, I
d
, for the considered transistor. Briefly discuss the effect that lateral fields
have on the transistor transconductance.
(d). Repeat Part (d) for the case in which the channel length, L, of the subject transistor is 5 M.
PROBLEM #4.18
An NMOS transistor operated at 27 C at a bulk-source reverse bias of 1 volt and a bulk-drain re-
verse bias of 3 volts features a channel length of 1 M, a gate width of 100 M, and a gate oxide
thickness of 80 . The impurity concentration of the semiconductor bulk is 10
14
atoms/cm
3
, while
the impurity concentrations in both the source and drain implants is 10
20
atoms/cm
3
. With refer-
ence to the notation used in the text, the transistor has the capacitance-related parameters, C
gso
=
C
gdo
= 0.2 fF/M, C
j
= 560 F/m
2
, C
jsw
= 320 F/m, L
diff
= 2.5 M, M
j
= 0.5, and M
jsw
= 0.45.
Evaluate the net gate-source, gate-drain, bulk-drain, and bulk source capacitances of the transistor
in both its ohmic and saturation domains.
PROBLEM #4.19
Develop the low frequency, small signal equivalent circuit of a MOSFET that is biased for opera-
tion in its ohmic, or triode, regime.
(a). Give analytical expressions for the forward transconductance, g
m
, the bulk transconductance,
g
mb
, and the channel resistance, r
o
.
(b). Compare the small signal parameters deduced for ohmic regime operation to those that de-
rive from a presumption of operation in the saturation domain. In the course of conducting
this study, compare the ohmic and saturation values of forward transconductance and shunt
drain-source resistance.
PROBLEM #4.20
Develop the high frequency, small signal equivalent circuit of a MOSFET that is biased for opera-
tion in its ohmic, or triode, regime. Compare the ohmic and saturation regime values of all small
signal parameters and the unity gain frequency of the MOSFET.
PROBLEM #4.21
In Section (4.7.1), the circuit parameters of the low frequency, small signal MOSFET model were
evaluated in terms of the volt-ampere characteristic expressed in (4-169). The evaluation neg-
lected the effect of mobility degradation caused by lateral electric fields. Recall that the immediate
impact of this degradation is a reduction of the drain saturation voltage by a factor of M
sat
, as
prescribed in Section (4.5.2). Re-evaluate the small signal parameters, g
m
, g
mb
, and r
o
by account-
ing for the aforementioned effects of mobility degradation. Examine the results carefully to assess
the small signal significance of the reduction in drain saturation voltage.
PROBLEM #4.22
A p-channel transistor featuring a channel length of 0.5 M has the Level 3 HSPICE parameters
itemized in Table (4.2). The transistor is biased in saturation at a source-drain voltage of V
sd
= 3.5
volt and I
d
700 A to achieve a forward transconductance of at least 2.0 mmho. Assume negligi-
ble body effects. Choose a reasonable gate aspect ratio, W/L, which is required to achieve the 700
A drain current target, determine the required source-gate voltage bias, V
sg
, and estimate the
model parameters implicit to static I-V relationship,
( )
2
sd ssat
d p sg h
V V
I V V 1 .
V
| |
= +
|
\ .

PROBLEM #4.23
In the network of Figure (P4.23), the transistor is biased in saturation and is configured to ensure

- 399 -
that the only device capacitance of significant importance is the gate-source capacitance, C
gs
. Vol-
tage V
s
is a signal having no static component. The radial unity gain frequency of the transistor is
T
, and channel length modulation is deemed insignificant. For the purpose of this problem, the
inductances, L
g
, L
s
, and L
d
, can be presumed ideal in the senses that they exhibit no parasitic series
resistances, no parasitic capacitances, and no mutual coupling of electric fields.
(a). Derive, in terms of capacitance C
gs
, unity gain frequency
T
, and inductances L
g
and Ls, an
expression for the indicated input impedance, Z
in
(j).
(b). Select inductance L
g
so that the input impedance is purely resistive at a tuned center fre-
quency of
o
. Give analytical expressions for
o
and the resultant impedance, Z
in
(j
o
).
(c). Deduce an expression for inductance L
s
such that at frequency
o
, maximum signal power
transfer is achieved at the amplifier input port.

Figure (P4.23)
(d). Let the small signal component of the indicated output voltage response, V
o
, be V
os
, and let
the small signal transfer function, V
os
/V
s
, be denoted as A
v
(j). Derive expressions for the
general voltage gain, A
v
(j), and its specific value, A
v
(j
o
), at signal frequency
o
and under
the condition of maximum signal power transfer at the input port of the amplifier.
PROBLEM #4.24
Figure (P4.24) depicts a simplified schematic diagram of a source follower whose output port is
terminated in a diode-connected NMOS transistor. Transistors M1 and M2 are realized as mono-
lithic devices, but the gate aspect ratio of M1 is k
2
-times larger than the gate aspect ratio of transis-
tor M2. Assume that the net (signal plus biasing) input voltage, V
i
, and the power line supply, V
dd
,
ensure that both transistors operate in their saturation domains where their low frequency volt-am-
pere characteristics are given by the general Schichman-Hodges expression,
( )
2
d n gs hn
I V V . =
Remember that the transconductance parameter,
n
, is proportional to the product of carrier mobil-
ity and gate aspect ratio. For the purpose of this problem, ignore bulk-induced threshold voltage
modulation, channel length modulation, carrier mobility degradation, and all other high order
phenomena.
(a). Derive an expression for the static relationship between the net output voltage, V
o
, and the
net input voltage, V
i
; that is, derive the function, f(V
i
), such that at low frequencies, V
o
=
f(V
i
).
(b). Use the aforementioned functional relationship (and not a small signal equivalent circuit) to
stipulate the small signal voltage gain, say A
v
, of the amplifier.
(c). Can the network be designed for a specific voltage gain that renders the net output voltage
response independent of the threshold potentials of the transistors? If so, give this specific
+
V
gg

L
s
L
d
L
g
R
s
V
s
V
o
+V
dd
Z (j )
in


- 400 -
voltage gain, and comment as to its practicality.

Figure (P4.24)
(d). For what value of voltage V
i
does transistor M1 exit its saturation regime?
(e). To what bulk-source voltage, V
bs1
, is transistor M1 exposed? In view of this determination,
is bulk-source threshold modulation in M1 more problematic at small or at large values of
the net input voltage, V
i
?
(f). Why are carrier mobility degradation and channel length modulation likely to be more
significant in transistor M1 than in transistor M2?
PROBLEM #4.25
Respond to the following inquiries clearly, but concisely, without resorting explicitly to
equations or mathematical analyses.
(a). What significance surrounds an NMOS gate-source voltage that establishes an interfacial
potential lying between one and two Fermi levels?
(b). Give at least one operating advantage and one operating disadvantage of carrier mobility
degradation precipitated by drain-source voltage.
(c). Why is it essential for the source and drain implants to have high impurity concentrations?
(d). Explain why it is necessary to allow for decreased channel length, L, in the Shichman-
Hodges volt-ampere relationship for a MOSFET operated in its saturation regime.
(e). Explain why the gate-drain capacitance of a perfectly self-aligned gate MOSFET is essen-
tially zero when a MOSFET is operated in strong saturation.
(f). Why is the declaration proffered in (e) untrue of the ohmic operating regime.
PROBLEM #4.26

Figure (P4.26)
In the reference biasing circuit of Figure (P4.26), both transistors exhibit negligible channel length
modulation, negligible carrier mobility degradation, and negligible body effect. Observe that the
gate aspect ratio of transistor M2 is larger than the gate aspect ratio of M1 by a factor of k
2
. The
M1
M2
x 1
x k
2
+V
dd
V
i
V
o
M2
M1
x k
2
x 1
R
+V
dd
I
k
V
ref
R
out

- 401 -
constant current, I
k
, can be presumed to derive from an ideal current source.
(a). In terms of current I
k
, what condition must circuit resistance R satisfy to ensure that transis-
tor M2 operates in its saturation domain.
(b). Assuming that M2 indeed operates in saturation, determine, in terms of parameter k, the indi-
cated output resistance, R
out
.
(c). Assuming that parameter k is held as a fixed constant, give two design recommendations that
support low output resistance.
PROBLEM #4.27
An alternative way of modeling channel length modulation in short channel MOSFETs entails the
use of the modified, square law, I-V relationship,
( )
2
d n gs hn
L
I V V ,
L L
| |
=
|
\ .

where an n-channel device is presumed. In this relationship,
n
is the transconductance metric, L is
the length of the source -to- drain spacing, V
gs
is the applied gate-source voltage, and V
hn
is the
threshold potential. The threshold potential can be taken here as a constant; that is, BITM can be
ignored. The parameter, L, is advanced herewith as the relationship,
ds dsat
b
T
V V
L D 2 ,
V
| |
=
|
\ .

where D
b
is the electron Debye length (a constant), V
dsat
is the drain saturation voltage (mobility
degradation is ignored), and V
T
is the Boltzmann voltage.
(a). Derive an expression for the forward transconductance, g
m
, of the considered MOSFET.
(b). What is the engineering significance of the electron Debye length?
PROBLEM #4.28
Figure (P4.28) displays the basic schematic diagram of a simple inverter commonly exploited in
the so-called pseudo-NMOS logic family. Observe that input signal V
i
is applied to the gate of the
NMOS device, MN, which is presumed to have a threshold voltage of V
h
and a transconductance
coefficient of |
n
. The output voltage, V
o
, is extracted at the drain node of the PMOS device, MP,
whose transconductance coefficient is |
p
and whose threshold voltage is presumed in the interest
of analytical simplicity to be identical to the threshold potential of MN. In the pseudo-NMOS
logic family, logic 1 (the high logic voltage) is taken to be the supply line voltage, V
dd
, while
logic 0 (the low logic voltage) is a potential below the threshold voltage of the NMOS transistor.

Figure (P4.28)
(a). If V
i
assumes its logic 1 value, use the simple Schichman-Hodges model (channel length
modulation and all mobility degradation and DIBL ignored) to evaluate the resultant steady
state output response, say V
o
= V
ox
. Clearly state any presumptions you make about the
operating regimes of the two utilized transistors.
(b). What two requirements must be satisfied by the transconductance ratio,
p
/
n
, if the output
+
M
N
M
P
R
s
V
i
+V
dd
V
o

- 402 -
response, V
oh
, to a logic 1 input excitation is smaller than the threshold voltage, V
h
?
(c). If V
i
is now set to the voltage level, V
oh
, which is presumably smaller than V
h
, in what re-
gimes do the transistors respectively operate?
PROBLEM #4.29
In the circuit of Figure (P4.29), the MOSFETs are identical, inclusive of gate aspect ratios, and
operate in their saturation domains. In order to ensure saturation region operation, the drain
terminals of transistors M2 and M3 are connected to circuit nodes that support suitably positive
voltages, V
x1
and V
x2
, respectively. Assuming negligible bulk-induced threshold modulation and a
square law volt-ampere characteristic for each device, the differential current, (I
1
I
2
), is given by
the algebraic form,
( )
1 2 me i Q
I I G V I . =

Figure (P4.29)
(a). Derive expressions for the effective static transconductance, G
me
, and the offset current, I
Q
.
(b). In terms of transistor threshold voltage and circuit voltages V
B
and V
i
, give the requirements
that must be imposed on voltages V
x1
and V
x2
to ensure the saturation domain operation of all
transistors.
PROBLEM #4.30
In the amplifier of Figure (P4.30), I
bias
is a biasing current source, and I
s
is a signal current source.
All transistors operate in their saturation regimes. They are all nominally identical, except for the
fact that the gate aspect ratios of transistors M1, M2, and M5 are each k-times larger than that of
transistor M3. The channel resistances of all transistors can be presumed to be infinitely large.

Figure (P4.30)

V
i

M2
M3
M1

V
B

I
1
I
2
V
x1
V
x2
M1
M5
M2
M3
V
o
I
o
+V
dd
V
ss
I
s
I
bias

- 403 -
(a). In terms of the biasing current, I
bias
, what quiescent current is conducted by transistor M1?
(b). What must the gate aspect ratio, say
5
, of transistor M5 be if the quiescent output voltage,
V
oQ
, is to be zero? Express your answer in terms of transistor threshold voltage, V
hn
, k, I
bias
,
V
dd
, and the device transconductance coefficient, K
n
=
n
C
ox
.

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LECTURE SUPPLEMENT #4 . . .

, termed the body effect voltage, is

in (4-8) converges toward zero.

Chapter 4 MOSFET Models and Applications

remain given by (4-6) and (4-8), respec-

Threshold Parameter For Drain induced barrier lowering 0.02125

Threshold Parameter For Drain induced barrier lowering 0.018

, termed the channel length modulation voltage

in (4-116) abides by the previously dis-

, in (4-116), which is pertinent only to the satura-

varies from 17.057 volts at V

the same value, regardless of V

in this voltage neighborhood is

is an empirical voltage parameter lying in the range of 30 volts < V

< 55 volts. The

. We recall that the bulk transconductance, g

, can be based analytically.

and the simulated disclosures for W/L and V

= 5.51 volts, W/L = 69.01, and V

is exacerbated by the fact that parameter V

is not the constant that is

or the drain-source channel resistance is critical in an analog circuit design endea-

, materializes. In either event, we

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