TITLE: DESIGN OF CMOS COMBINATIONAL LOGICS (SCHEMATIC & LAYOUT)

OBJECTIVES

a) To compare between the netlist of CMOS NAND schematic and layout.
b) To build the CMOS NAND schematic using Silvaco Gateway Schematic Editor.
c) To design the CMOS NAND layout using Silvaco Expert Layout Processor.
d) To perform experiment in laboratory and present technical reports.
e) Work effectively in given tasks as individual or in group.

LIST OF EQUIPMENTS

a) Personal Computer
b) SILVACO EDA Tools
i. Gateway (Schematic Editor)
ii. Expert (Silvaco Layout Processor)
iii. SmartView

RESULTS

Project requirements:
The system must have 2 inputs and 1 output.
The output of the system will only be LOW when both input HIGH. Otherwise the output
will be high.
P-channel device using sizing ratio = 5.0.
N-channel device using sizing ratio = 2.5.


Figure 1: NAND CMOS circuit design


Figure 2: Test the NAND CMOS circuit


Figure 3: Define the spice analysis

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Figure 4: NAND truth table 1




Figure 5: Result from the truth table 1 when time delay is 10s

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Figure 6: NAND truth table 2


Figure 7: Result from the truth table 2 when time delay is 10.2s
1
1
0
0
0
1
0
1
1
1
0
1


Figure 8: NAND Layout design using expert


Figure 9: No error detected on DRC test



Figure 10: Run Guardian Net


DISCUSSIONS

1. Based on the circuit design above, it is a NAND gate which is a combination of AND and
NOT gate. The small circle that can be seen at the output of the AND gate shows that the
output will be invert. The meaning of the output will be invert is when the output is high
then it will be inverted to low.

2. From the result that we get, the graph follows the NAND truth table exactly. The graph
shows that, when both input are in high, then the output will be in low. Furthermore,
when both input are in low, then the output will be in high. The output was following the
given requirement.

3. On top of that, in order to prove the truth table 2, the time delay is increased so that we
can see the result is exactly the same with the truth table. From the result, we can see that
if the inputs are in high and low, the output will be high.

4. Next, for the NAND layout design, it consists of many layers, which are ndiff, pdiff,
nwell, pwell, polysilicon, and contact layer. The important thing in layout design is the
measurement of each layer need to be correct and follows the rule given.

5. After finished the layout design, we need to run the Design Rule Check (DRC) in order to
check any error with the design and then verify it. If any error occurs, we need to recheck
the design whether it follows the design rule or not.

6. So when the design passes the DRC check, we proceed to the Layout Versus Schematic
(LVS) check. The LVS is carried out to determine whether the layout design corresponds
to the schematic of the diagram.




CONLUSION

As a conclusion, we know the comparison between the netlist of CMOS NAND
schematic and layout. Next, we know steps to build the CMOS NAND schematic and layout by
using Silvaco Gateway schematic editor and Silvaco Expert layout processor. Lastly, we were
work effectively in a group and successfully done the tasks given. At the end, all the objectives
are achieved.