CHAPTER 4

Digital Logic Families

SOLUTIONS


Ans.1 (A)
The truth table shows the circuit to be an AND gate for positive logic

1

2

0

Actual Logic Actual Logic Actual Logic

1

Ans.2 (B)
The truth table show the circuit to be an OR gate for a negative logic

1

2

0

Actual Logic Actual Logic Actual Logic

0

Ans.3 (B)
If either or both of
1

2
are logic high, then
0
is high otherwise
0
= 0. Thus OR
logic.

Ans.4 (C)
Each of diode logic perform AND function
=

Ans.5 (D)
All diodes are in reverse bias hence all diode current are zero.

Ans.6 (A)
Since 1 = 25 ,
1
,
2

0
is OFF
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0
=
25 20
20.5
+
40 0.5
20.5
= 25.4

1
=
2
=
25.4 25
1
= 0.4 ,
0
= 0

Ans.7 (C)
When
1
= 0
2
= 1
0
= 5 , we assume
1
ON,

2

0

Since
0
,
0
= 5

2
us reverse biased by 20 V. Hence it is off,
1
is forward biased by 5 V hence it is ON
To have
0
ON
0
must be greater than 0

0
=

5
20
+
5 0
1
> 0
=>

+5 + 120 > 0
=>

125

Ans.8 (A)
Each diode causes a voltage level loss of 0.75 V.
Therefore 0.75 n < 2.5V
=> = 3

Ans.9 (D)
If
1
>

1
is saturated and
0
=


If
2
>

2
is saturated and
0
=


Further if
1

2
are both saturated,
0
=


However, if both
1

2
<

,
Both
1

2
are OFF and
0
=

The following truth table shows NOR logic

1

2

0

Actual Logic Actual Logic Actual Logic

1

0

0

0

1

0

Ans.10 (C
The circuit responses to actual voltage
1

2
are unchanged; however the
interpretation differs. The logic entries in the truth table in previous solution take on
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the logic complement value.
When the resulting truth table is constructed, the NAND gate function is apparent.

Ans.11 (D)

= +5,

=

= 0.2

Ans.12 (D)
If
1
>

,
1
is saturated and
01
=

. If
2
>

,
2
is saturated and

01
=

. Also if
1

2
are both saturated,
01
=

. Otherwise,
01
=

.
A truth table shows NOR logic for
01
as output

1

2

0

Actual Logic Actual Logic Actual Logic

1

0

0

0

1

0

Ans.13 (B)
The
3
stage is simply an inverted (a NOT gate). Thus output
02
is the logic compement
of
01
. Therefore, this is a OR gate.

Ans.14 (A)
When
1
is saturated,
01
is logic LOW otherwise
01
is logic HIGH. The following table
shown AND logic

1

2

1

1 1 1
0 1 0
1 0 0
0 0 0

Ans.15 (C)
The
2
stage is simply an inverter. Thus output
2
is the logic complement of
01
.

Ans.16 (C)
If
1
=
2

,
1

. If
1

2
>

, while
2

,
1
(
2
) is ON and
2
(
1
) is
OFF and
1

. If
1
=
2
>

, both
1

2
are ON and
1
2
( )
. The
truth table shows NAND logic

1

2

0

Actual Logic Actual Logic Actual Logic

1 2

0

Ans.17 (A)
The
3
stage is simple an inverter. Hence AND logic

Ans.18 (C)
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For each successive gate, that has a transistor in saturation, the current required is

=
5 0.2
50640
= 0.15
For n attached gate

=


To assume no logic error

0
=

>

= 3.5

3.5

=
5 3.5
6400.15
= 15.6 => 15

Ans.19 (A)
Let
1
=
2
= 0, then
3
will be ON,
1

2
OFF and
4
ON, hence
0
=

.
Let
1
= 0
2
=

then
3
will be ON,
1
OFF
4
OFF,
2
ON, hence

0
=

.
Let
1
=

2
= 0 , then
3
OFF,
4
ON,
2
OFF hence
0
=

Finally if
1
=
2
=

,
3

4
will be OFF and
1
,
2
will be ON.
Hence
0
= 0 . Thus the given CMOS gate satisfies the function of a negative NAND
gate.

Ans.20 (C)
If

then
1
is ON and

= 0 . If

= 0 then

3

2
are ON but
1
is OFF.
Hence

= 0 . If

= 0 and either or both

are 0 V then
1
is OFF and either or
both
2

3
will be OFF, which implies no current flowing through
4
. Hence

.
Thus given circuit satisfies the logic equation +

.

Ans.21 (A)
Let
1
=
2
= 0 = (0) then
4

3
will be ON and
2

1
OFF hence

0
=

= (1).
Let
1
= 0,
2
=

then
4

2
will be ON but
3

1
be OFF hence

0
= 0 = (0).
Let
1
=

,
2
= 0, then
4

3
will be OFF and
1
ON hence
0
= 0 = 0
Finally if
1
=
2
=

,
1

2
will be ON but
4
will be OFF hence
0
= 0 = (0).
Thus the given CMOS satisfy the function of a positive NOR gate.

Ans.22 (A)
If either one or both the inputs are 0 = 0 the corresponding FET will be OFF, the
voltage across the load FET will be 0 V, hence the output is

. If both inputs are

1 =

, both
1

2
are ON and the output is 0 = 0 . It satisfy NAND gate.

Ans.23 (B)
If both the inputs are at 0 = 0, the transistor
1

2
are OFF, hence the output
is 1 =

.
If either one or both of the inputs are at 1 =

, the corresponding FET will be ON

and the output will be 0 = 0. Hence it is a NOR gate.

Ans.24 (A)
If all inputs A, B and C are HIGH, then input to inverter us LOW and output Y is HIGH. If
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all inputs are LOW, then input to inverter is also LOW and output Y is HIGH.
In all other case the input to inverter is also LOW and output Y is LOW.
= +

= + + +

Ans.25 (B)
The operation of this circuit is given below:
A B C

Y
0 ON OFF HIGH
0 0 1 ON ON OFF OFF OFF ON HIGH
1 1 OFF OFF ON ON LOW
1 1 OFF OFF ON ON LOW
= +

Ans.26 (C)
The operation of circuit is given below
A C C D

Y
1 OFF ON LOW
0 0 ON ON OFF OFF HIGH
0 0 1 0 ON ON OFF ON OFF OFF ON OFF HIGH
0 1 1 0 ON OFF OFF ON OFF ON ON OFF LOW
1 0 1 0 OFF ON OFF ON ON OFF ON OFF LOW
1 1 1 0 OFF OFF OFF ON ON ON ON OFF LOW

= + +

Ans.27 (B)
If input E is LOW, output will not be LOW. It must be HIGH. Option (B) satisfy this
condition.

Ans.28 (A)
In this circuit parallel combination are OR gate and series combination are AND gate.
Hence
= + + +

Ans.29 (A)
When an output is HIGH, it may be as low as
( )
= 2.4 . The minimum voltage
that an input will respond to as a HIGH is
( )
= 2.0 . A negative noise spike that
can drive the actual voltage below 2.0 V if its amplitude is greater than

=
( )

( )

= 2.4 2.0 0.4

Ans.30 (A)
When an output is LOW, it may be as high as
( )
= 0.4 . The maximum voltage
that an input will respond to as a LOW is
( )
= 0.8 . A positive noise spike that
can drive the actual voltage below 0.8 V level if its amplitude is greater than

=
( )

( )

= 0.8 0.4 0.4

Ans.31 (B)
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A positive noise spike can drive the voltage above 1.0 V level if the amplitude is greater
than

=
( )

( )

= 1 0.1 = 0.9 ,
A negative noise spike can drive the voltage below 3.5 V if the amplitude is greater than

=
( )

( )

= 4.9 3.5 = 1.4

Ans.32 (B)

( )
=
( )

= 0.8 0.5 = 1.3

( )
=
( )

= 0.5 +2 = 1.5

Ans.33 (C)

=
( )

( )

=
( )

( )

= 2.7 2.0 = 0.7

= 0.8 0.5 = 0.3

Ans.34 (B)

= 2.5 2.0 = 0.5

= 0.8 0.4 = 0.4

Ans.35 (D)

( )
= 0.5

( )
= 0.3


Ans.36 (B)
=

( )

( )
=
8
0.1
= 80
=

( )

( )
=
400
20
= 20
The fanout is chosen the smaller of the two.

Ans.37 (B)
In high state the loading on the output of gate 1 is equivalent to six 74LS input load.
Hence load = 6

= 6 20 120

Ans.38 (C)
The NAND gate represent only a single input load in the LOW state. Hence only five
loads in the LOW state.
Load = 5

= 5 0.4 = 2

Ans.39 (A)
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The
2
(Integrated injection logic) has higher density of integration than TTL because
it does not required transistors with high current gain and hence they have smaller
geometry.

Ans.40 (B)
The correct order of increasing noise is
RTL, ECL, DTL, MOS,

Ans.41 (B)
The figure is as shown below

Ans.42 (D)
When any of the input or the input or all the inputs are high then transistor goes into
saturation and output will be low.
When all inputs are zero then transistor is in cut off region and output will be high. This
is a NOR gate.
= + +

Ans.43 (B)
If either A or B is low, then diode
1

2
will conduct, and point E will be at low.
If both A and B are high, diode
1

2
both are off, and point E is at high. Thus

1

2
from the AND function = and similarly =

5

6
from a OR gate, so
= +, = +

Ans.44 B

= 0 then first transistor will be cut-off and current through left resistor will drive the
second transistor into saturation
Then
0
=
,
+1.25 10
3
10
3
= 1.35

Ans.45 D

1
=
1

/ =
1
+
2

=
1
+
2

=
1
.
2


Ans.46 C
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When

= 3
1
will be in reverse active mode i.e. reverse on the
2
will be on.

Ans.47 D
Ans.48 B
Ans.49 B
Ans.50 D
Ans.51 C
TTL-Transistor logic
C MOS complementary Metal Oxide Semiconductor

Ans.52 A
(i) CMOS has the largest fan-out
(ii) CMOS has the lowest power consumption.

Ans.53 B
figure

Ans.54 B
Figure of merit (pJ)= Propagation delay time (ns) Power dissipation (mW)

Ans.55 B

Ans.56 B
Ans.57 A
Ans.58 *
The correct sequence is
A B C D
5 4 1 2

Ans.59 C
Ans.60 A
Ans.61 A
ECL gate operates in active and cut off region. The switching speed ECL gate is very high
because it does not enter in saturation and thus the propagation delay is reduced.

Ans.62 C
Ans.63 C
Ans.64 A
Ans.65 C
Ans.66 D
Ans.67 B
Ans.68 A
Ans.69 C
Ans.70 D
Ans.71 C
A. HTL - High noise immunity
B. CMOS - High fan-out
C.
2
- Lowest product of power and delay
D. ECL - Highest speed of operation

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Ans.72 B
CMOS - Lower power consumption

Ans.73 A

2
- Multiple collectors.

Ans.74 D
Totem pole refers to the output buffer.

Ans.75 D
CMOS has high input impedance and low output impedance.

Ans.76 D
ECL is fastest among all logic families.
PMOS slowest among all logic families then NMOS then CMOS.
MOS devices are slower then BJT.

Ans.77 A

Ans.78 A
=
Which is NAND Gate

Ans.79 A
TTL has

= 10 . fan out = 10
ECL is fastest logic family i.e. lowest propagation delay

2
uses multi-collector o/p-so due to this fan out increases.
NMOS required less silicon area compare to P-MOS

Ans.80 D

=
( )

=


( )


Ans.81 D
Direct coupled logic family suffers with current hogging problem diode transistor logic

= 30 ns due tot this speed of operation is slow compare to TTL, ECL etc. bus fast
compare to RTL
ECL fastest among all logic family having

= 1
RTL

= 50 slow speed of operation compare to TTL, ECL, DTL etc.

DTL is suitable for monolithic ICs

Ans.82 B
ECL highest power consuming
CMOS least power consuming