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I. INTRODUCTION
Manuscript received January 8, 2004; revised October 25, 2004. This work
was supported by the Micron Foundation as part of the Micron Campus Engineering Research Program, JuneAugust 2003. This paper was recommended
by Associate Editor N. R. Aluru.
The authors are with the Department of Electrical and Computer Engineering,
Brigham Young University, Provo, UT 84602 USA (e-mail: thollis@ieee.org).
Digital Object Identier 10.1109/TCSII.2005.850777
are better known for strongly inverted devices and the boundaries between moderate and strong inversion operation or weak
and moderate inversion operation are not immediately obvious.
The motivation for this work was not only to further the
understanding of the effects of channel length and inversion
on amplier performance, but to demonstrate that such an
understanding unlocks a new set of operating points with corresponding performance benets not realizable in the traditional
long channelstrongly inverted design.
The level of inversion and the size of the channel inuence
midband voltage gain, bandwidth, noise, matching of devices,
power dissipation, nonlinear distortion, and maximum output
current. One recent article [1] discusses guidelines involved
in choosing drain current and channel size to achieve certain
selected performance parameters. It considers the effects of
current and sizing on transconductance, layout area, output
resistance, icker noise, and other parameters involved in
amplier design. A second article [2] considers the effects
of drain current on voltage gain and nonlinear distortion.
This study extends earlier work to the 0.18- device and discusses the optimization of the voltage gain-bandwidth product
(GBW) for this device size. The following section of this article discusses the operation of MOSFETs over the three regions
of inversion and the equation used to dene the level of inversion. The third section considers the effects of channel length
and channel inversion on amplier characteristics including the
optimization of the GBW. The fourth section reports simulations for various combinations of channel length and inversion
level. The fth section presents some guidelines for selecting
device lengths and inversion levels to achieve optimum performance in terms of gain, distortion, power efciency and/or
GBW. A summary of the common-source amplier characteristics is presented using a modied four corners approach.
These four corners correspond to the use of a short-channel
device in weak inversion, short-channel device in strong inversion, long-channel device in weak inversion, and long-channel
device in strong inversion. The nal section will consist of a
summary of the ndings presented throughout this paper.
II. INVERSION LEVELS
MOS devices can effectively amplify signals in any of the
three inversion regions, yet even with this knowledge analog
circuit designers often limit device operation to the strong inversion region. While simple MOS amplier stages have much
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 52, NO. 9, SEPTEMBER 2005
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547
constant gain throughout the weak inversion region [2]. The predicted gain is found by rst considering the expression for drain
current in the weak inversion region
(3)
is proportional to the specic current.
where
Then, by denition, the transconductance is found to be
(4)
and
Voltage gain is the product of
replaced by the ratio of Early voltage
where
may be
to drain current.
Gain
(5)
After some cancellation, the following equation emerges:
Gain
(6)
(8)
where
is the critical electric eld value, typically the ratio
of the velocity saturation constant to the effective mobility, and
is a parameter related to the thickness of the oxide layer [7].
results in
Differentiating the drain current with respect to
the following approximation of transconductance:
(9)
We present (9) as an approximation in that it matches the
shape of the simulated
verses IC curve but must be scaled in
order to match the absolute value of the curve. Yet, even as an
approximation, it is a useful expression that acurately predicts
the inversion level associated with the maximum
, a necessary detail for amplier optimization.
When attempting to optimize the GBW, a simulation of the
device can be done to accurately determine the IC that results
in the maximum value. For the 0.18- device, this value of IC
may be somewhere between 10 and 100 as shown in Fig. 2.
In applications requiring high bandwidth, the bias current
should be chosen to result in an IC value that is relatively high.
This may result in a relatively low midband voltage gain as well
as a quiescent current leading to higher power dissipation, yet
the maximum bandwidth per stage will also result from this bias.
IV. SIMULATION RESULTS
All simulations completed in this study were performed
in Spectre, with TSMCs tsmc18rf-nMOS2v and nMOS3v
BSIM3.v3 models. As was mentioned previously, all of the amplier characterization was completed for the common-source
stage shown in Fig. 1. Each amplier parameter, (voltage
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Fig.2. Simulation results showing the correlation between inversion level and
midband gain for the 0.18-, 0.5-, and 2- devices.
Fig. 3. Simulation results showing the correlation between inversion level and
THD for the 0.18-, 0.5-, and 2- devices..
Fig. 4. Simulation results showing the correlation between inversion level and
gain bandwidth for the 0.18-, 0.5-, and 2- devices.
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VI. CONCLUSION
Fig. 5.
3) Optimum Bandwidth and Minimal Distortion: High bandwidth coupled with minimal distortion may be achieved
using minimum sized devices with reduced inversion level
as was shown in Fig. 3. While reducing the inversion level
will degrade the speed of the device somewhat, clearly this
is the most effective way to reduce distortion while minimizing the sacrice in bandwidth.
4) Optimum Voltage Gain: Voltage gain is proportional to
channel length and will therefore be higher in the longer
device across most of the inversion level spectrum. It was
shown, however, in Fig. 2 that at the inversion level extremes this notion does not hold. Disregarding these extreme cases, the voltage gain of the longer device may
then be optimized by targeting operation in the midrange
to higher end of the moderate inversion region, a fact discussed in [3]. If a short-channel device is to be used, then
operation well into the weak inversion region will optimize voltage gain.
5) Optimum Gain Bandwidth: There is a well-known
tradeoff between the high bandwidth/low gain of minimum sized devices and the low bandwidth/high gain
of longer devices. To some degree, the size of the device
will depend on the process technology in which the
circuit will be implemented. In older technologies, the
minimum sized device might correspond to the longer
devices presented in this study. In either case, once the
device size has been established, the GBW may still be
optimized. As was described in Section III-C, there is
a clear maximum in the GBW curve that occurs in the
strong inversion region which may be quickly identied
through simulation or by using (9) and should be targeted
to optimize for this parameter.
This work continues the characterization of the MOS amplier, specically considering voltage gain, THD, and GBW and
their relation to device-channel length and channel inversion in
the common-source stage. As has been done in past studies [1],
these performance parameters were presented as functions of
the amplifying devices inversion coefcient. By comparing the
performance of long- and short-channel devices across all three
regions of inversion, it was possible to derive a set of practical
design guidelines for optimizing MOS ampliers in terms of
particular gain, distortion and bandwidth constraints.
As was stated in the introduction, one purpose of this study
was to further uncover possible performance benets existing
outside of the traditional long channelstrongly inverted amplier design, and clearly many such benets exist. For example,
it has been shown that while gain is maximized through the
use of long-channel devices, when the gain requirement is coupled with distortion and/or bandwidth requirements, then it may
be advisable to move to a short-channel device in order to increase circuit speed and lower distortion. If bandwidth is not a
priority, then it is possible to complement the high gain of the
longer device with lower distortion simply by decreasing the
channel inversion level. Thus, optimal performance with respect
to specic design requirements is often only realizable as circuit
designers more carefully consider not only device length but inversion level as well.
While optimization for several design constraint combinations was presented, additional focus was placed on the gain
bandwidth. An expression accounting for the effects of velocity
saturation and mobility degradation was presented as well as
a discussion of how this expression may be used to identify the
maximum in the GBW behavior. Biasing the amplifying devices
to operate at the corresponding level of inversion then results in
optimum GBW performance. Similar operating points may be
found to optimize for any combination of gain, distortion and/or
bandwidth constraints based on the material presented.
This work, combined with the MOS characterization previously presented [1][4], constitutes a powerful set of design
tools that should facilitate the often complicated process of balancing circuit performance tradeoffs.
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