Acceptability of Bare boards

All boards will be inspected in accordance with IPC-A-600G

Relevant clauses are specified in brackets
Base material .
Edges of base material. (2.1)

Burrs, chips, delaminations, haloing, nicks, and other penetrations along the base material edges
of completed printed boards shall be acceptable provided the imperfection does not reduce the
edge spacing specified by more than 50 percent of the distance from the edge of the board to the
closest conductor or are greater than 2.5 mm [0.098 in! "hichever is less.
Base material edges include the e#ternal edge of the printed board, the edges of cutouts, and the
edges of non$plated$through holes. %oose metallic burrs shall not be acceptable.
Surface imperfections. (2.2)
&mperfections in the surface of the base material such as blistering, burrs, cuts, dents, e#posed
"eave, foreign materials, nicks, pits, resin starved areas, scratches, tool marks, variations in color
such as "hite spots or black spots, or other visual defects detrimental to the performance of the
base material shall be acceptable providing the follo"ing conditions are met'
(he imperfection does not bridge conductors.
(he dielectric spacing bet"een the imperfection and a conductor is not reduced belo" the
specified minimum conductor spacing re)uirements.
%ocali*ed concentration of these imperfections are no closer than +.5 mm ,.2+ inch- to
any conductor.
Surface pits and voids . (2.2.4)
.urface pits and voids in the base material shall be acceptable providing the follo"ing conditions
are met'
.urface voids are no bigger than 0.8 mm ,.0/0 inch- in the longest dimension.
(he surface voids do not bridge conductors.
(he total area of all surface voids does not e#ceed five percent of the total printed board
area.
(he surface void does not affect the performance of the base material.
Subsurface imperfections.
Subsurface imperfections. (2.3)
.ubsurface imperfections ,such as blistering, cra*ing, delamination, foreign inclusions, and
haloing- shall be acceptable providing the follo"ing conditions are met'
(he imperfections do not reduce conductor or dielectric spacing belo" the specified
minimum re)uirements.
(he imperfections do not bridge more than 25 1 of the distance bet"een ad2acent
conductors or plated$through holes and vias that are not electrically common.
3o more than one percent of the printed board area on each side shall be affected.
Measling. (2.3.1)
4easles are acceptable for all products, e#cept for high5voltage applications as defined by the
customer.
Conductive pattern .
nnular ring! e"ternal. (2.1#.2)
(he e#ternal annular ring shall be as specified.
6nnular ring measures 0.050mm or more is acceptable
7nless already at the specified minimum limit, a 20 percent reduction of the specified
e#ternal annular ring due to defects such as pits, dents, nicks, pinholes, or splay, in
isolated areas, shall be acceptable.
Bonding of conductor to base material and lifted lands . (3.3.2)
(here shall be no peeling or lifting of the conductive pattern ,lands or conductors- from the base
material.
$lating (2.%.1)
(he 8lating finish shall be as specified. 7nless other"ise specified, the follo"ing re)uirements
shall apply.
$lating coverage .
7nless other"ise specified, the conductor finish shall completely cover the e#posed conductive
pattern. 9omplete coverage does not apply to the vertical conductor edges ,gold fingers-
&old fingers
7nless other"ise specified, these re)uirements apply to the critical contact area. (he critical
contact area for edge board contacts shall be as specified.
:efects or surface imperfections in the edge board contact finish shall not e#pose base
metal in critical contact area.
(here shall be no nodules or metal bumps in the edge board contact finish in the critical
contact area.
8its, dents, or depressions in the edge board contact finish shall not e#ceed 0.05 mm
,.0059 inch- in their longest dimension. (here shall be no more than three occurrences
for each edge board contact, and no more than /0 percent of the contacts shall be
affected.
$lating overlap . (2.%.1)
7nless other"ise specified, these re)uirements apply to all 2unctions of different platings or
coatings.
(here shall be no e#posed copper in the 2unction of metallic plating;s or coatings.
6n overlap of metallic plating;s or coatings shall be acceptable if it is no greater than 0.8
mm ,.0/2 inch- in length.
<hen both solder coating and gold plating are present at a plating 2unction, a
discolouration at that plating overlap *one shall be acceptable.
Conductor finis' plating and coating voids in plated(t'roug' 'oles . (2.).4)
(he conductor finish plating and coating shall not have voids that e#ceed the follo"ing limits'
3o more than one final finish void in any plated$through hole.
3ot more than 5 percent of the plated$through holes shall have final finish voids.
6ny final finish void present is not more than 5 percent of the plated$through holes
length.
6ny final finish void present is less than 90 degrees of the circumference of the plated$
through hole.

*ire bond pads (2.%.1.1)

.urface mount lands and "ire bond pad 9ontacts are free of surface nodules, roughness,
electrical test "itness marks or scratches that e#ceed 0.8 =m [/2 =in! >4. ,root5mean5s)uare- in
the pristine area.
$'+sical dimension re,uirements. ,2.00-
(he completed printed board shall meet the interface and physical dimensions
re)uirements specified.
(he dimensional re)uirements include items such as the conductor pattern including
component lands and terminals, cutouts, overall board thickness, periphery, and other
design features as specified.
&n the event that a dimensional characteristic is not specified, the applicable class / of
&89$2220 design default for that characteristic shall apply.
Conductor pattern accurac+
9onductor pattern accuracy shall be as specified.
-ole pattern accurac+.
(he location of the hole pattern in the printed board shall be as specified.
-ole si.e.
(he hole si*e and tolerance shall be as specified.
7nless other"ise specified, hole si*e tolerance shall be applied after plating.
3odules or rough plating in plated$through holes shall not reduce the hole diameter
belo" the minimum limits specified.
Edge board contacts edge condition. (2.%.2)
(he end or beveled edge of edge board contacts shall be smooth "ith no burrs,
roughness, or lifted plating.
(here shall be no separation of the edge board contacts from the base material or any
loose reinforcement fibers on the beveled edge.
?#posed copper on the end or beveled edge of the edge board contact shall be
acceptable.
Conductor /mperfections (2.1#.1.1)
(he conductor pattern shall contain no cracks, splits, or tears. 7nless other"ise specified, any
combination of edge roughness, nicks, pinholes, cuts, or scratches e#posing the base material
shall not reduce each conductor "idth by more than 20 1of its minimum specified "idth. (here
shall be no occurrence of the 20 1 reductions greater than 0/.0 mm ,.50 inch- or 00 1 of a
conductor length, "hichever is less.
Conductor 0idt'. (2.1#.1.1)
9onductor "idth shall be as specified.
Conductor spacing. (2.1#.1.2)
9onductor spacing shall be as specified.
Conductor t'ic1ness ,/.2./-
7nless other"ise specified on the procurement documentation, the minimum total ,copper foil
plus copper plating- conductor thickness after processing shall be in accordance "ith (able /50.
>eference' 4in. 9u 8lating (hickness 9lass0@20=m[A8A =in! 9lass2@20=m[A8A =in!
9lass/@25=m[98 =in! B 8rocess allo"ance reduction does not allo" for re"ork processes for
"eights belo" 0C2 o*. Dor 0C2 o*. and above, the process allo"ance reduction allo"s for one
re"ork process.
Solder mas1.
Coverage. (2.2.1)
.older mask coverage imperfections ,such as blisters, skips, and voids- shall be acceptable
providing the imperfection meets all of the follo"ing'
(he solder mask imperfection shall not e#pose t"o ad2acent conductors "hose spacing is
less than the electrical spacing re)uired for the voltage range and environmental
condition specified in the applicable design standard.
&n areas containing parallel conductors, the solder mask imperfection shall not e#pose
t"o isolated conductors, e#cept "here space bet"een conductors is intended to be
uncovered.
(he e#posed conductor shall not be bare copper.
(he solder mask imperfection does not e#pose tented via holes.
3egistration. ,2.9.2 and 2.9./-
(he solder mask shall be registered to the land or terminal patterns in such a manner as to
meet the re)uirements specified. &f no re)uirements are specified, the follo"ing apply'
.older mask shall not encroach onto surface mount lands.
.older mask misregistration onto plated5through component hole lands ,plated5through
holes to "hich solder connections are to be made- shall not reduce the e#ternal annular
ring belo" the specified minimum re)uirements.
.older mask shall not encroach into plated5through hole barrels or onto other surface
features ,such as connector fingers or lands of unsupported holes- to "hich solder
connections "ill be made.
.older mask is permitted in plated5through holes or vias in "hich no lead is to be
soldered.
(est points "hich are intended for assembly testing shall be free of solder mask unless a
partial coverage allo"ance is specified.
4'ic1ness . ,/./.00-
.older mask thickness shall be as specified.
Solder mas1 ad'esion (2.2.))
(he cured solder mask coating shall not e#hibit tackiness, blistering, or delamination.
6fter testing in accordance "ith &895(45+50, 4ethod 2..28.0, the amount of solder
resist lifting does not e#ceed the allo"able limits of the +000 .eries.
Soda stra0 voids. (2.2.5)
(here shall be no visible soda stra" voids bet"een the solder mask and the printed board base
material surface and the edges of the conductor patterns.
6ia protection. (3.3.1))
Blind via holes should be filled or plugged "ith a polymer or solder resist to prevent solder from
entering them.
&ncomplete via fill may result in board delamination due to the rapid e#pansion of entrapped air
pockets or flu# contaminants during solder reflo" processes.
6t least +01 buried via fill "ith laminating resin or similar via fill material is acceptable
Microsection re,uirements (3.3.13)
8rinted board test specimens ,production printed boards or test coupons- shall conform to all
specified re)uirements in as applicable.
Barrel cracks, butt plating 2oints, circumferential separations, corner cracks, and cracked
copper plating shall not be acceptable.
&89$6$+00 contains figures, illustrations, and photographs that can aid in the
visuali*ation of internally observable acceptCre2ect conditions of microsectioned test
specimens.
&f a condition is not addressed herein, or specified on the printed board procurement
documentation, it shall comply "ith the class / criteria of &89$6$+00E
Base material.
7ielectric la+er t'ic1ness. (3.1)
(he minimum dielectric thickness bet"een conductor layers shall be as specified.
8aminate voids (3.1.1)
%aminate voids "ith the longest dimension of 0.08 mm ,.00/ inch- or less shall be acceptable
provided the conductor spacing is not reduced belo" the minimum dielectric spacing
re)uirements, laterally or vertically, as specified.
Met'ods of /nspection9 (3.3)
-ole Si.e (met'od optional : /$C:4M:;)#! Met'od 2.2.%)
Fptical
:ocument drill blank plug or plug gages
(apered hole gage 3ote' hole gages must be cleaned and storage oil must be removed
prior to use.
6isual 'ole 0all ,ualit+
Goids, 3odules, etc., 5 locate "ith unaided eye, use up to 00H magnification for
verification.
:iscolorations, .tains, etc., 5 use unaided eye andCor solderability tests.
Solderabilit+
6 lot sample or representative specimen should be sub2ected to a solderability test utilising
4ethods B, 9, or : of 63.&C I5.(:500/.
(he coating durability re)uirement should be pre5established. (he plated5through holes should
e#hibit good "etting and capillary action.