Affiah Digital Electronics

CHAPTER ONE
NUMBER SYSTEM AND CODES

INTRODUCTION
Number are fundamental to the function and use of computer at all levels
starting from the digital logic level and progressing through the applications
level. Numbers are used in arithmetic operation, computer instructions are
stored as a series of numbers, it may also be used as codes for letters and
special symbols. The collection of unique digits that the computer represent is
one component of its number system. Number Systems in use Symbolic
number system uses Roman numerals (I = 1, V = 5, X = 10, L = 50, C = 100, D =
500 and M = 1000) still used in some watches. The Weighted position system
includes the following; The Decimal system is the most commonly used and
Decimal numbers are based on Indian numerals and Radix used is 10. Other
weighted position systems are the binary numbers which are most extensively
used the Binary system uses radix 2, the octal system which uses radix 8 and
the hexa-decimal system which uses radix 16.
1.1 STRUCTURE OF NUMBER SYSTEMS
Most modern computers use the binary number system, which has only two
digits, 0 and 1. this system is chosen because a computer must be able to
represent each digit in some unique manner. Since there are many electronic
devices that can represent two unique states: open - closed, high - low, right -
left or on - off, binary system is the best for computers. The existence of an area
of mathematics know as Boolean algebra, which deals specifically with binary
numbers this provides a firm theoretical foundation for the development of
computer components. We are acquainted with two different number systems,
the Roman and Arabic, each digit in the Roman System always means the same
thing e.g. III represents a value three and iv means one less than five but still
represents one. The Arabic system differs from the Roman because the locati6ri
of Digits to each other is important as well as the position. The number III
considered above will represent one hundred and one in th Arabic system which
gives a different interpretation altogether when compared with the Roman
System. A special zero is needed to indicate positions that are not holding
another digit, e.g. the number five hundred and seven (507) will appear as fifty
seven (57) without Zero. Each position has a weight or value that depends on
the base (or radix) of the number systems. The radix of a number is the same as
the base of the decimal number system. For any given radix the minimum
number of characters which deals specially with binary numbers is another
reason for choosing binary system that can be found in any given combination
is equal to the radix.
1
Digital Systems. An Introductory Perspective.
Examples
(i) Radix 10 :. 0, 1,2,3,4,5,6, 7, 8, 9
(ii) Radix 8 : - 0, 1,2,3,4, 5, 6, 7
(iii) Radix 2 :- 0, 1
(iv) Radix 16 :- 0, 1,2,3,4, 5, 6, 7, 8, 9, A, B, C, D, E, F.
We use the decimal, or base 10 system in our day to day lives. The Arabic type
number system have as many unique digits, including zero, as magnitude of
base, but there is never a single digit equal to the base. Number system .
1.2 NUMBER SYSTEM
1.2a Binary System
The binary system is generally employed in digital. equipment in order to
simplify circuit design. As the binary system is based on powers of two there are
only two digits 0 and 1. this implies that the equipment recognizes only two
states as stated in section 1.1. The position of a 1- digit in a binary number
determines its weighting value, example; a 4 - digit binary number 1111 has the
following meaning:
The binary member 1111 = decimal member (8+4+2+ 1) = 15. The example we
just considered uses a positive power of the base, for those whose weight are
1 2
negative powers of the base we have (2- ,2- , etc.) which is very useful in
determining the decimal value of a binary fraction, example; determining the
decimal value of 0. 011 will give
0. 0 1 1
-3
1 of 2 = 1 x l = 0. 1 25
8
-2
1 of 2 = 1 x1= 0.250
4
-1
0 of 2 = (1) X 1 = 0. 000
1
2
The binary number 0. 011 = decimal number (0.125 + 0.250) = 0.375 Each
binary digit in a binary number is referred to as a bit. The sequence of 4 bits is
known as a nibble. 0010, 1010, 1111 are all nibbles. A group of8 bits is known as
a byte, e.g. 00011010, and 11100101. The number of bits used to convey data in
o o
1of 2 = 1x2 = 1
1 1
1of 2 = 1x2 = 2
2 2
1of 2 = 1x2 = 4
3 3
1of 2 = 1x2 = 8
2
1 1 1 1
a computer or microprocessor is known as a world length. Micro processor
based computers user a world length of a byte, simple microprocessors uses 1
nibble, which then latest uses 2 bytes . Mainframe computers uses 24 to 60 bit
word length. Consider a nibble say 1111, the right hand bit has the least
weighting known as the least significant bit (LSB), the left hand having the most
weighting and is YJ"lown as the most significant bit, (MSB). As we program from
right to left there is an increment in the weighting value in power of 2 as in
example (1).
1.3.1 Basic Binary Arithmetic
Arithmetic operations using binary numbers are far simpler than the
corresponding operations using decimal numbers due to the very elementary
rules of addition and multiplication. The rules of binary addition are
0 + 0 = 0
0+ 1 = 1
1+ 0 = 1
1 + 1 = 0 (carry 1)
As in decimal addition, the least significant bits of the addend and the augend
are added first. The result is the sum, possibly including a carry. The carry bit is
added to the sum of the digits of the next column. The process continues until
the bits of the most significant column are summed.
Example 1.6 Let us consider the addition of the decimal numbers 27 and 28 in
binary.
Decimal Binary
27 11011 Addend
+28 +11100 Augend
55 110111 Sum
11000 Carry
To verify that the sum is correct, we convert 110111 to decimal:
5 4 3 2 1 0
1 x 2 + 1 x 2 + 0 x 2 + 1 x 2 + 1 x 2 + 1 x 2
= 32 + 16 + 0 + 4 + 2 + 1
= 5
3
Example 1.7 Let us add 11 to 19 in binary. Since the addend and the augend are
negative, the sum will be negative.
Decimal Binary
19 10011
11 01011
30 11110 Sum
00011 Carry
In all digital systems, the circuitry used for performing binary addition handles
two numbers at a time. When more than two numbers have to be added, the first
two are added, then the resulting sum is added to the third number, and so on.
Binary subtraction is carried out by following the same method as in the decimal
system. Each digit in the subtrahend is deducted from the corresponding digit in
the minuend to obtain the difference. When the minuend digit is less than the
subtrahend digit, then the radix number (i.e., 2) is added to the minuend, and a
borrow 1 is added to the next subtrahend digit. The rules applied to the binary
subtraction are
0 - 0 = 0
0 - 1 = 1 (borrow 1)
1 - 0 = 1
1 - 1 = 0
Example 1.8 Let us consider the subtraction of 2110 from 2710 in binary:
Decimal Binary
27 11011 Minuend
21 10101 Subtrahend
6 00110 Difference
00100 Borrow
It can easily be verified that the difference 00110 corresponds to decimal 6.
2
Example 1.9 Let us subtract 2210 from 1710. In this case, the subtrahend is
greater than the minuend. Therefore the result will be negative.
Decimal Binary
17 10001
22 10110
5 00101 Difference
00001 Borrow
4
Binary multiplication is performed in the same way as decimal multiplication, by
multiplying, then shifting one place to the left, and finally adding the partial
products. Since the multiplier can only be 0 or 1, the partial product is either
zero or equal to the multiplicand. The rules of multiplication are
0 0 = 0
0 1 = 0
1 0 = 0
1 1 = 1
Example 1.10 Let us consider the multiplication of the decimal numbers 67 by
13 in binary:
Decimal Binary
67 1000011 Multiplicand
x13 1101 Multiplier
871 1000011 First partial product
0000000 Second partial product
1000011 Third partial product
1000011 Fourth partial product
1101100111 Final product
Example 1.11 Let us multiply 13.5 by 3.25.
Decimal Binary
13.5 1101.10 Multiplicand
x3.25 11.01 Multiplier
43.875 110110 First partial product
000000 Second partial product
110110 Third partial product
110110 Fourth partial product
101011.1110 Final product
The decimal equivalent of the final product is 43 0.50 0.25 0.125 43.875.
The process of binary division is very similar to standard decimal division.
However, division is simpler in binary because when one checks to see how
many times the divisor fits into the dividend, there are only two possibilities, 0 or
1.
Example 1.12 Let us consider the division of 101110 (4610) by 111 (710)
5
0001 Quotient
Divisor 111 101110 Dividend
0111
100
Since the divisor, 111, is greater than the first three bits of the dividend, the first
three quotient bits are 0. The divisor is less than the first four bits of the dividend;
therefore the division is possible, and the fourth quotient bit is 1. The difference is
less than the divisor, so we bring down the net bit of the dividend:
00011
111 101110
0111
1001
111
10
The difference is less than the divisor, so the next bit of the dividend is brought
down:
000110
111 101110
0111
1001
111
100 Remainder
In this case the dividend is less than the divisor; hence the next quotient bit is 0
and the division is complete. The decimal conversion yields 46/7 = 6 with
remainder 4, which is correct. The methods we discussed to perform addition,
subtraction, multiplication, and division are equivalents of the same operations
in decimal. In digital systems, all arithmetic operations are carried out in
modified forms; in fact, they use only addition as their basic operation.
direct input output operation
Digital systems operate only on binary numbers.
1.2 b Octal System
This is a base eight number system widely used in computer techniques. Its
useful properties includes that of simplicity in converting from binary to octal and
vice versa, and easy Con ersion from binary to
octal beings with the separation of the binar number into groups of three bits
starting at the radix point
v
y
.
6
7
of bits required to represent an octal digit is three. For example, octal 7 can
be represented by binary 111. Thus, if each octal digit is written as a group of
three bits, the octal number is converted into a binary number.
Example 1.15 the octal number 3248 can be converted to a binary number
as follows:
3 2 4
011 010 100
Hence 324 =110101002; the most significant 0 is dropped because it is
8
meaningless, just as 0123 is the same as 123 .
10 10
The conversion from binary to octal is also straightforward. The binary
number is partitioned into groups of three starting with the least significant
digit. Each group of three binary digits is then replaced by an appropriate
decimal digit between 0 and 7 see table 1.2.
Table 1.2 Binary to Octal Conversion
Binary Octal
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Example 1.16. Let us convert 1100111010012 to octal:
6 3 5 1
110 011 101 001
The octal representation of the binary number is 6351 . If the leftmost group of a
8
partitioned binary number does not have three digits, it is padded on the left with
0's.
8
For example, 1101010 would be divided as
001 1
101 5
010 2
The octal equivalent of the binary number is 1528. In case of a binary fraction, if
the bits cannot be grouped into 3-bit segments, the 0's are added on the right to
complete groups of three. Thus 110111.1011 can be written
110 6
111 7
101 5
100 4
As shown in the previous section, the binary equivalent of a decimal number can
be obtained by successively dividing the number by 2 and using the remainders
as the answer, the first remainder being the lowest significant bit, and so on. A
large number of divisions by 2 are required to convert from decimal to binary if
the decimal number is large. It is often more convenient to convert from decimal
to octal and then replace each digit in octal in terms of three digits in binary. For
example, let us convert 523 to binary by going through octal.
10
523/8 = 65, remainder 3
65/8 = 8, remainder 1
Thus,
(523) = ( 1 0 1 3)
10 8
= (001 000 001 011)
2
It can be verified that the decimal equivalent of 0010000010112 is 523 :
10
9 3 1 0
1 x2 + 1 x 2 +1 x 2 + 1 x 2 = 512 + 8 + 2 + 1
= 523
10
Addition and subtraction operations using octal numbers are very much similar
to that use in decimal systems. In octal addition, a carry is generated when the
sum exceeds 710.
9
For example,
153 + 327 = 502
8 8 8
3 + 7 = 10 = 2 + 1 carry first column
10
5 + 2 + 1 carry =0 + 1 carry second column
1 + 3 + 1 carry = 5 third column
In octal subtraction, a borrow requires that 810 be added to the minuend digit
and a 110 be added to the left adjacent subtrahend digit.
670 - 125 = 543
8 8 8
0 - 5 = (8 - 5 + 1 borrow) = 3 + 1 borrow first column
10
7 - (2 + 1 borrow) = 7 - 3 = 4 second column
6 - 1 = 5 third column
The octal number system has three bit digit representation and is one common
solution to the problems with binary numbers. Another solution involves using a
four bit pattern; this requires a digit for each of the 2 x 2x 2 x 2 or 16 possible bit
pattern. The radix here 16 and the system is known as hexadecimal or hex. The
least significant digit in front of the hexadecimal point is weighted 16= 1, the
2
next is 16 etc. successive as follows
-1
16 = 1/16
-2
16 = 1/256
-3
16 = 1/4096 etc.
The hexadecimal numbering system has a base 16; that is, there are 16
symbols. The decimal digits 0 to 9 are used as the first ten digits as in the
decimal system, followed by the letters A, B, C, D, E, and F, which represent the
values 10, 11, 12, 13, 14, and 15, respectively. Table 1.3 shows the relationship
between decimal, binary, octal, and hexadecimal number systems. The
conversion of a binary number to a hexadecimal number consists of partitioning
the binary numbers into groups of 4 bits, and representing each group with its
hexadecimal equivalent.
1.2c Hexadecimal Number System
10
Table 1.2 Number Equivalents
Decimal Binary Octal Hexadecimal
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
11
Using the digits available in the decimal system will give a problem in this hex
notation countering the fact that we do not write double figures in the range
between 10 and 15, instead we assign the first six letters of the alphabet giving
the following;
10 is replaced by A, 11 by B, 12 by C, 13 by D, 14 by E and 15 by F.
All the possible combination of four bits with their decimal and hexadecimal
equivalent is show in the table 1.2 below.

12
Bit pattern Hexadecimal
0000 0 0
0001 I I
0010 2 2
0011
3 3
0100

4

4
0101

5

5
0110

6

6
0111

7

7
1000

8

8
1001

9

9
1010

10

A
1011

11

B
1100 12 C
1101 13 D
1110 14 E
1111 15 F
Decimal
Examples
Binary to hexadecimal conversion
1. convert the following binary into hexadecimal
1011101010010010
Solution
1011 1010 1001 0010 Binary
B A 9 2 Hex
Hence 1011101010010010 = Ba 92
2 16

2. Convert (567. 1875)10 to Hexadecimal
Solutions
Integer Part Fractional part
0.1875 x 16 = 3.0000
16 567 35 r.7
16 35 2 r.3
16 2 0 r.2

Hence (567. 1875) = (237 . 3)
10 16
3. Convert 26810 to Hex Solution
Solution
16 268
16 16 r.12 = C
16 12 r.0
0 r.1
So 268 = 10
10 16
13
1.2d Fixed and Floating Point Numbers.
All the numbers considered up till now is based on the assumption that they are
whole numbers. This is called fixed point notation and used to indicate that the
binary point is fixed at the position where the power of the base 2 weighting
-1
changes from positive to negative i.e at the point between 2 and 2 bits.
Examples of fixed-point binary numbers are
01101111=111
10
and 01100 111.101 = 103.625 .
10
In representing very large and very small numbers we employ scientific
notation, for instance a number say 0.000000123456789 would be represented
6
by 0.123457 x 10 .
Notice only six digits are listed and the sixth digit is rounded. The number
of digits displayed in scientific notation is called the precision of the number.
The computer version of scientific notation is called floating point. In
general floating point representation of a number to any base may be written in
form;
+e
n = + m b
Where e in the exponent
m is the mantissa
and b is the base
1.2e Negative Numbers
Negative number are represented by adding a dash or minus sign to the
left of the number as in -2468.0ther approaches places the dash in the right as in
2468 -, or put parenthesis around negative numbers as in (2468). This approach
is called signed magnitude method and can be adopted for use with any number
system.
Since there are only two possible signs, the sign can be represented by a
single bit. As with the sign - and- magnitude, the most significant bit (MSB) of the
number is used as the sign bit; MSB is 0 for positive number and 1 for negative
number.
The signed magnitude representation has limitations. It is not possible to
perform basic arithmetic operations with positive and negative numbers and
automatically provide the correct sign for theresult. For example the decimal
expression 9 4 by the laws of arithmetic can be represented by 9 + (- 4) which
implies the following
14
9 =
+(-4) = 10000100
1000 II 0 I = -13
Hence addition of sign plus magnitude can produce an incorrect result.
The method representing negative numbers that will lead to the desired
arithmetic results are the radix complement (2's complement in the binary
system) and the diminished radix complement (1 's complement) methods.
One's complement of a binary number is formed by flipping all of its bits.
Every one bit in the original number is changed to a zero, and every zero to a
one. This results in the original number but with an opposite sign, for example 0
10010101 is (l06 ) will produce 01101010 or (-106 ) As with signed
2 10 10
magnitude numbers
the MSB is a sign bit.
Considering our example again, the result from 9 - 4 i.e. (9 + ( - 4) will now
be
00001001
11111011
100000100
Carry
Something seem to be wrong because the answering is still not five, it has one
more bit than the original number. The extra bit is called a carry and is when it is
generated during one's complement it must be moved from the high end to the
low end of the number Hence
1 0 0 0 0 01 0 0
+ 14
0 0 0 0 0 1 0 1
This operation is called end round early and is necessary for the production of
the correct answer in one's complement arithmetic. One's complement has a
problem of alternate representation of zeros.
00001001
2
15
To correct the problem above we create two's complement of numbers. This is
done by flipping all the bits as with one's complement and adding 1 to the result.
For example positive five in binary is 00000101 , flipping the bits produces
2
11111010 , which is -510 in two's complement. In the two's complement
2
arithmetic the carry in ignored.
1. 3 Codes and Their Conversions: Digital circuits use binary signals but are
required to handle data which may be alphabetic, numeric, or special
characters. Hence the signals that are available in some other form other than
binary have to be converted into suitable binary form before they can be
processed further by digital circuits. This means that in whatever format the
information may be available it must be converted into binary format. To achieve
this, a process of coding is required where each letter, special character, or
numeral is coded in a unique combination of 0s and 1s using a coding scheme
known as code. In digital systems a variety of codes are used to serve different
purposes, such as data entry, arithmetic operation, error detection and
correction, etc. Selection of a particular code depends on the requirement. Even
in a single digital system a number of different codes may be used for different
operations and it may even be necessary to convert data from one type of code
to another. For conversion of data, code converter circuits are required, which
will be discussed in due time. Codes can be broadly classified into five groups,
viz. (i) Weighted Binary Codes, (ii) Non weighted Codes, (iii) Error-detection
Codes, (iv) Error-correcting Codes, and (v) Alphanumeric Codes.
1.3.1. Codes: Various binary codes are used to represent data which may be
numeric, alphabetic or special characters. Codes are also used for error
detection and error correction in digital systems. Although, in digital systems in
every code used, the information is represented in binary form, but the
interpretation of the data is only possible if the code in which the data is being
represented is known. For example, the binary number 1000010 represents 66
(decimal) in straight binary, 42 (decimal) in BCD, and letter B in ASCII code.
Hence, while interpreting the data, one must be very careful regarding the code
used.
1.3.1a. Weighted Binary Codes
If each position of a number represents a specifi c weight then the coding
scheme is called weighted binary code. In such coding the bits are multiplied by
their corresponding individual weight, and then the sum of these weighted bits
gives the equivalent decimal digit.
16
BCD Code or 8421 Code The full form of BCD is Binary-Coded Decimal. Since
this is a coding scheme relating decimal and binary numbers, four bits are
required to code each decimal number. For example, (35)10 is represented as
0011 0101 using BCD code, rather than (100011) . From the example it is clear
2
that it requires more number of bits to code a decimal number using BCD code
than using the straight binary code. However, in spite of this disadvantage it is
convenient to use BCD code for input and output operations in digital systems.
The code is also known as 8-4-2-1 code. This is because 8, 4, 2, and 1 are the
weights of the four bits of the BCD code. The weight of the LSB is 20 or 1, that of
the next higher order bit is 21 or 2, that of the next higher order bit is 22 or 4, and
that of the MSB is 23 or 8. Therefore, this is a weighted code and arithmetic
operations can be performed using this code, which will be discussed later on.
The bit assignment 0101, for example, can be interpreted by the weights to
represent the decimal digit 5 because 0 8 + 1 4 + 0 2 + 1 1 = 5. Since four
binary bits are used the maximum decimal equivalent that may be coded is 1510
(i.e., 11112). But the maximum decimal digit available is 910. Hence the binary
codes 1010, 1011, 1100, 1101, 1110, 1111, representing 10, 11, 12, 13, 14, and
15 in decimal are never being used in BCD code. So these six codes are called
forbidden codes and the group of these codes is called the forbidden group in
BCD code. BCD code for decimal digits 0 to 9 is shown in Table 1.1.
Example 1.1. Give the BCD equivalent for the decimal number 589.
Solution. The decimal number is 589
BCD code is 0101 1000 1001
Hence, (589)10 = (010110001001)BCD
Example 2.2. Give the BCD equivalent for the decimal number 69.27.
Solution. The decimal number 6 9 2 7
BCD code is 0110 1001 0010 0111
Hence, (69.27)10 = (01101001.00100111)BCD
84-2-1 Code
It is also possible to assign negative weights to decimal code, as shown by the
84-2-1 code. In this case the bit combination 0101 is interpreted as the decimal
digit 3, as obtained from
0 8 + 1 4 + 0 (2) + 1 (1) = 3.
17
This is a self-complementary code, that is, the 9s complement of the decimal
number is obtained just by changing the 1s to 0s and 0s to 1s, or in effect by
getting the 1s complement of the corresponding number. For example, if we
change the 1s to 0s and 0s to 1s in the previous example we have 1010, which is
interpreted as decimal 6, as obtained from
1 8 + 0 4 + 1 (2) + 0 (1) = 6.
And 6 is the 9s complement of 3. This property is useful when arithmetic
operations are done internally with decimal numbers (in a binary code) and
subtraction is calculated by means of 9s complement.
2421 Code
Another weighted code is 2421 code. The weights assigned to the four digits are
2, 4, 2, and 1. The 2421 code is the same as that in BCD from 0 to 4; however, it
varies from 5 to 9. For example, in this case the bit combination 0100 represents
decimal 4; whereas the bit combination 1101 is interpreted as the decimal 7, as
obtained from
2 1 + 1 4 + 0 2 + 1 1 = 7.
This is also a self-complementary code, that is, the 9s complement of the
decimal number is obtained by changing the 1s to 0s and 0s to 1s. The 2421
codes for decimal numbers 0 through 9 are shown in Table 2.1.
1.3.1b. Nonweighted Codes
These codes are not positionally weighted. It basically means that each position
of the binary number is not assigned a fi xed value. Excess-3 codes and Gray
codes are such non-weighted codes.
Excess-3 Code
A decimal code that has been used in some old computers is Excess-3 code.
This is a non weighted code. This code assignment is obtained from the
corresponding value of 4-bit binary code after adding 3 to the given decimal
digit. Here the maximum value may be 11002. Since the maximum decimal digit
is 9 we have to add 3 to 9 and then get the BCD equivalent. Like 84-2-1 and
2421 codes Excess-3 is also a self-complementary code, that is, the 9s
complement of the decimal number is obtained by changing the 1s to 0s and 0s
to 1s. This self-complementary property of the code helps considerably in
performing subtraction operation in digital systems.
18
2421 codes Excess-3 is also a self-complementary code, that is, the 9s
complement of the decimal number is obtained by changing the 1s to 0s and 0s
to 1s. This self-complementary property of the code helps considerably in
performing subtraction operation in digital systems.
Example 1.3. Convert (367)10 into its Excess-3 code.
Solution. The decimal number is 3 6 7
Add 3 to each bit i.e 3 +3, 6 +3 and 7 +3
The sum now implies 6 9 and 10
Converting the above sum into 4-bit binary equivalent, we have an 4-bit binary
equivalent of 0110 1001 1010 implying 6 = 0110, 9 = 1001 and 10 = 1010
Hence, the Excess-3 code for (367)10 = 0110 1001 1010
Example 1.4. Convert (58.43)10 into its Excess-3 code.
Solution. The decimal number is 5 8 4 3
Add 3 to each bit +3 +3 +3 +3 will produce the sum 8 11 7 6
Converting the above sum into 4-bit binary equivalent, we have a 4-bit binary
equivalent of 1000 1011 0111 0110
Hence, the Excess-3 code for (367)10 = 10001011.01110110

Decimal
digit
(BCD)8421
84-2-1 2421 Excess-3

0

1

2

3

4

5

6

7

0000

0001

0010

0011

0100

0101

0110

0111

0000

0111

0110

0101

0100

1011

1010

1001

0000

0001

0010

0011

0100

1011

1100

1101

0011

0100

0101

0110

0111

1000

1001

1010

8

9
1000

1001
1000

1111
1110

1111
1011

1100

Table 1.1 Decimal digits and their Binary codes
19
Gray Code
The Gray code was designed by Frank Gray at Bell Labs and patented in 1953.
It is an un-weighted binary code in which two successive values differ only by 1
bit. Owing to this feature, the maximum error that can creep into a system using
the binary Gray code to encode data is much less than the worst-case error
encountered in the case of straight binary encoding. Table 1.2 lists the binary
and Gray code equivalents of decimal numbers 015. An examination of the
four-bit Gray code numbers, as listed in Table 1.2, shows that the last entry rolls
over to the first entry. That is, the last and the first entry also differ by only 1 bit.
This is known as the cyclic property of the Gray code. Although there can be
more than one Gray code for a given word length, the term was first applied to a
specific binary code for non-negative integers and called the binary-reflected
Gray code or simply the Gray code. There are various ways by which Gray
codes with a given number of bits can be remembered. One such way is to
remember that the least significant bit follows a repetitive pattern of 2 (11, 00,
11,.... ), the next higher adjacent bit follows a pattern of 4 (1111, 0000, 1111, ....)
and soon. We can also generate the n-bit Gray code recursively by prefixing a 0
to the Gray code for n-1 bits to obtain the first 2n-1 numbers, and then prefixing
1 to the reflected Gray code for n-1 bits to obtain the remaining 2n-1 numbers.
The reflected Gray code is nothing but the code written in reverse order.
1.3.2 BinaryGray Code /Gray - Binary Conversion
BinaryGray Code Conversion
A given binary number can be converted into its Gray code equivalent by going
through the following steps:
1. Begin with the most significant bit (MSB) of the binary number. The MSB of the
Gray code equivalent is the same as the MSB of the given binary number.
2. The second most significant bit, adjacent to the MSB, in the Gray code
number is obtained by adding the MSB and the second MSB of the binary
number and ignoring the carry, if any. That is, if the MSB and the bit adjacent to it
are both 1, then the corresponding Gray code bit would be an0.
3. The third most significant bit, adjacent to the second MSB, in the Gray code
number is obtained by adding the second MSB and the third MSB in the binary
number and ignoring the carry, if any.
4. The process continues until we obtain the LSB of the Gray code number by
the addition of the LSB and the next higher adjacent bit of the binary number.
The conversion process is further illustrated with the help of an example
showing step-by-step conversion of (1011)2 into its Gray code equivalent:
20
Binary 1011
Gray code 1- - -
Binary 1011
Gray code 11- -
Binary 1011
Gray code 111-
Binary 1011
Gray code 1110
Gray CodeBinary Conversion
A given Gray code number can be converted into its binary equivalent by going
through the following steps:
1. Begin with the most significant bit (MSB). The MSB of the binary number is
the same as the MSB
of the Gray code number.
Decimal
numbers
Binary code Gray code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

Table 1.2 Binary and Gray codes
21
2. The bit next to the MSB (the second MSB) in the binary number is obtained by
adding the MSB in the
binary number to the second MSB in the Gray code number and disregarding
the carry, if any.
3. The third MSB in the binary number is obtained by adding the second MSB in
the binary number to the third MSB in the Gray code number. Again, carry, if any,
is to be ignored.
4. The process continues until we obtain the LSB of the binary number. The
conversion process is further illustrated with the help of an example showing
step-by-step
conversion of the Gray code number 1110 into its binary equivalent:
Gray code 1110
Binary 1- - -
Gray code 1110
Binary 10 - -
Gray code 1110
Binary 101
Gray code 1110
Binary 1011
2.3.4 Applications
1. The Gray code is used in the transmission of digital signals as it minimizes the
occurrence of errors.
2. The Gray code is preferred over the straight binary code in angle-measuring
devices. Use of the Gray code almost eliminates the possibility of an angle
misread, which is likely if the angle is represented in straight binary. The cyclic
property of the Gray code is a plus in this application.
3. The Gray code is used for labeling the axes of Karnaugh maps, a graphical
technique used for minimization of Boolean expressions.
4. The use of Gray codes to address program memory in computers minimizes
power consumption. This is due to fewer address lines changing state with
advances in the program counter.
5. Gray codes are also very useful in genetic algorithms since mutations in the
code allow for mostly incremental changes. However, occasionally a one-bit
change can result in a big leap, thus leading to new properties.
22
Example 2.5. Convert (101011)2 into Gray code.
Solution.
Step 1. The MSB of the Gray code is the same as the MSB of the binary
number.
1 0 1 0 1 1 Binary
1 Gray
Step 2. Perform the ex-OR between the MSB and the second bit of the
binary. The result is 1, which is the second bit of the Gray code.
1 0 1 0 1 1 Binary
1 1 Gray
Step 3. Perform the ex-OR between the second and the third bits of the
binary. The result is 1, which is the third bit of the Gray code.
1 0 1 0 1 1 Binary
1 1 1 Gray
Step 4. Perform the ex-OR between the third and the fourth bits of the
binary. The result is 1, which is the fourth bit of the Gray code.
1 0 1 0 1 1 Binary
1 1 1 1 Gray
Step 5. Perform the ex-OR between the fourth and the fi fth bits of the
binary. The result is 1, which is the fi fth bit of the Gray code.
1 0 1 0 1 1 Binary
1 1 1 1 1 Gray
Step 6. Perform the ex-OR between the fi fth and the sixth bits of the binary.
The result is 0, which is the last bit of the Gray code.
1 0 1 0 1 1 Binary
1 1 1 1 1 0 Gray
After completing the conversion the Gray code of binary 101011 is 111110
Example 2.6. Convert (564)10 into Gray code.
Solution.
Step 1. Convert the decimal 564 into equivalent binary.
Decimal number 564
Binary number 1000110100
Step 2. The reader should try to Convert the binary number into equivalent
Gray code using the method used I example 2.5 above.
+
+
+
+
+
23
Example 2.7. Convert the Gray code 101101 into a binary number.
Solution.
Step 1. The MSB of the binary number is the same as the MSB of the Gray
code.
1 0 1 1 0 1 Gray
1 Binary
Step 2. Perform the ex-OR between the MSB of the binary number and the
second bit of the Gray code. The result is 1, which is the second bit of the
binary number.
1 0 1 1 0 1 Gray
1 1 Binary
Step 3. Perform the ex-OR between the second bit of the binary number and
the third bit of the Gray code. The result is 0, which is the third bit of the
binary number.
1 0 1 1 0 1 Gray therefore implies 1 1 0 Binary.
Example 2.4
Find (a) the Gray code equivalent of decimal 13 and (b) the binary equivalent
of Gray code number 1111.
Solution
(a) The binary equivalent of decimal 13 is 1101.
BinaryGray conversion
Binary 1101
Gray 1- - -
Binary 1101
Gray 10 - -
Binary 1101
Gray 101
Binary 1101
Gray 1011
(b) Graybinary conversion
Gray 1111
Binary 1- - -
Gray 1111
Binary 10- -
Gray 1111
Binary 101-
Gray 1111
Binary 1010
24
1.3.3 Alphanumeric Codes
Many applications of the computer require not only handling of numbers, but
also of letters. To represent letters it is necessary to have a binary code for the
alphabet. In addition, the same binary code must represent the decimal
numbers and some other special characters. An alphanumeric code is a binary
code of a group of elements consisting of ten decimal digits, the 26 letters of the
alphabet (both in uppercase and lowercase), and a certain number of special
symbols such as #, /, &, %, etc. The total number of elements in an
alphanumeric code is greater than 36. Therefore it must be coded with a
minimum number of 6 bits (26 = 64, but 25 = 32 is insufficient). One possible 6-
bit alphanumeric code is given in Table 2.5. It is used in many computers to
represent alphanumeric characters and symbols internally and therefore can be
called internal code. Frequently there is a need to represent more than 64
characters, including the lowercase letters and special control characters. For
this reason the following two codes are normally used are;
ASCII: The full form of ASCII (pronounced as-kee) is American Standard
Code for Information Interchange, used in most microcomputers. It is actually a
7-bit code, where a character is represented with seven bits. The character is
stored as one byte with one bit remaining unused. But often the extra bit is used
to extend the ASCII to represent an additional 128 characters. Some of the
codes are shown in Appendix 1.
EBCDIC: The full form of EBCDIC is Extended Binary Coded Decimal
Interchange Code. It is also an alphanumeric code generally used in IBM
equipment and in large computers for communicating alphanumeric data. For
the different alphanumeric characters the code grouping in this code is different
from the ASCII code. It is actually an 8-bit code and a ninth bit is added as the
parity bit. See appendix 2.
1.3.4 Hollerith Code
Generally this code is used in punched cards. A punched card consists of 12
rows and 80 columns. An alphanumeric character is represented by each
column of 12 bits each by punching holes in the appropriate rows. The presence
of a hole represents a 1 and its absence indicates 0. The 12 rows are marked
starting from the top, as 12, 11, 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. The fi rst three rows
25
are called the zone punch and the last nine are called the numeric punch. The
code used here is called the Hollerith code. The letters are represented as two
holes in a column, one in zone punch and the other in numeric punch; decimal
digits are represented as a single hole in a numeric punch. Special characters
are represented as one, two, or three holes in a column; while the zone is always
used, the other two holes, if used, are in a numeric punch with the eighth punch
being commonly used. The Hollerith code is BCD and hence the transition from
EBCDIC is simple. The Hollerith code is used in the card readers and punches
of large computers, while EBCDIC may be used within the computer.
1.3.5 Error Detection and Correction Codes
When we talk about digital systems, be it a digital computer or a digital
communication set-up, the issue of error detection and correction is of great
practical significance. Errors creep into the bit stream owing to noise or other
impairments during the course of its transmission from the transmitter to the
receiver. Any such error, if not detected and subsequently corrected, can be
disastrous, as digital systems are sensitive to errors and tend to malfunction if
the bit error rate is more than a certain threshold level. Error detection and
correction, as we will see below, involves the addition of extra bits, called check
bits, to the information-carrying bit stream to give the resulting bit sequence a
unique characteristic that helps in detection and localization of errors. These
additional bits are also called redundant bits as they do not carry any
information. While the addition of redundant bits helps in achieving the goal of
making transmission of information from one place to another error free or
reliable, it also makes it inefficient. In this section, we will examine some
common error detection and correction codes.

1.3.6 Parity Code
A parity bit is an extra bit added to a string of data bits in order to detect any error
that might have crept into it while it was being stored or processed and moved
from one place to another in a digital system. We have an even parity, where
the added bit is such that the total number of ls in the data bit string becomes
even, and an odd parity, where the added bit makes the total number of ls in the
data bit string odd. This added bit could be a 0 or a 1. As an example, if we
have to add an even parity bit to 01000001 (the eight-bit ASCII code for A), it will
be a 0 and the number will become 001000001. If we have to add an odd parity
bit to the same number, it will be a l and the number will become 101000001.
26
The odd parity bit is a complement of the even parity bit. The most common
convention is to use even parity, that is, the total number of 1s in the bit stream,
including the parity bit, is even. The parity check can be made at different points
to look for any possible single-bit error, as it would disturb the parity. This simple
parity code suffers from two limitations. Firstly, it cannot detect the error if the
number of bits having undergone a change is even. Although the number of bits
in error being equal to or greater than 4 is a very rare occurrence, the addition of
a single parity cannot be used to detect two-bit errors, which is a distinct
possibility in data storage media such as magnetic tapes. Secondly, the single-
bit parity code cannot be used to localize or identify the error bit even if one bit is
in error. There are several codes that provide self-single-bit error detection and
correction mechanisms, and these are discussed below.
1.3.7 Repetition Code
The repetition code makes use of repetitive transmission of each data bit in the
bit stream. In the case of threefold repetition, 1 and 0 would be transmitted as
111 and 000 respectively. If, in the received data bit stream, bits are examined
in groups of three bits, the occurrence of an error can be detected. In the case of
single-bit errors, 1 would be received as 011 or 101 or 110 instead of 111, and a
0 would be received as 100 or 010 or 001 instead of 000. In both cases, the
code becomes self-correcting if the bit in the majority is taken as the correct bit.
There are various forms in which the data are sent using the repetition code.
Usually, the data bit stream is broken into blocks of bits, and then each block of
data is sent some predetermined number of times. For example, if we want to
send eight-bit data given by 11011001, it may be broken into two blocks of four
bits each. In the case of threefold repetition, the transmitted data bit stream
would be 110111011101100110011001. However, such a repetition code where
the bit or block of bits is repeated 3 times is not capable of correcting two-bit
errors, although it can detect the occurrence of error. For this, we have to
increase the number of times each bit in the bit stream needs to be repeated. For
example, by repeating each data bit 5 times, we can detect and correct all two-bit
errors. The repetition code is highly inefficient and the information throughput
drops rapidly as we increase the number of times each data bit needs to be
repeated to build error detection and correction capability.
27
1.3.8 Cyclic Redundancy Check Code
Cyclic redundancy check (CRC) codes provide a reasonably high level of
protection at low redundancy level. The cycle code for a given data word is
generated as follows. The data word is first appended by a number of 0s equal to
the number of check bits to be added. This new data bit sequence is then divided
by a special binary word whose length equals n+1, n being the number of check
bits to be added. The remainder obtained as a result of modulo-2 division is then
added to the dividend bit sequence to get the cyclic code. The code word so
generated is completely divisible by the divisor used in the generation of the
code. Thus, when the received code word is again divided by the same divisor,
an error-free reception should lead to an all 0 remainder. A nonzero remainder
is indicative of the presence of errors. The probability of error detection depends
upon the number of check bits, n, used to construct the cyclic code. It is 100 %
for single-bit and two-bit errors. It is also 100 % when an odd number of bits are
in error and the error bursts have a length less than n + 1. The probability of
detection reduces to 1 (1/2)n-1 for an error burst length equal to n + 1, and to 1
(1/2)n for an error burst length greater than n + 1.
1.3.9 Hamming Code
We have seen, in the case of the error detection and correction codes described
above, how an increase in the number of redundant bits added to message bits
can enhance the capability of the code to detect and correct errors. If we have a
sufficient number of redundant bits, and if these bits can be arranged such that
different error bits produce different error results, then it should be possible not
only to detect the error bit but also to identify its location. In fact, the addition of
redundant bits alters the distance code parameter, which has come to be
known as the Hamming distance. The Hamming distance is nothing but the
number of bit disagreements between two code words. For example, the
addition of single-bit parity results in a code with a Hamming distance of at least
2. The smallest Hamming distance in the case of a threefold repetition code
would be 3. Hamming noticed that an increase in distance enhanced the codes
ability to detect and correct errors. Hammings code was therefore an attempt at
increasing the Hamming distance and at the same time having as high an
information throughput rate as possible.The Hamming code is capable of
correcting single-bit errors on messages of any length. Although the Hamming
code can detect two-bit errors, it cannot give the error locations. The number of
parity bits required to be transmitted along with the message, however, depends
28
upon the message length, as shown above. The number of parity bits n required
to encode m message bits is the smallest integer that satisfies the condition (2n
n > m.
29
Self Test Questions 1.
7. Express the following decimal numbers in Excess-3 code form:
(a) 245, (b) 739, (c) 4567, and (d) 532.
8. Express the following Excess-3 codes as decimals:
(a) 100000110110, (b) 0111110010010110, and 110010100011.
9. Convert the following binary numbers to Gray codes:
(a) 10110, (b) 1110111, (c) 101010001, and (d) 1001110001110.
10. Express the following decimals in Gray code form:
(a) 5, (b) 27, (c) 567, and (d) 89345.
11. Write your first name and last name in an 8-bit code made up of the seven
ASCII bits and an odd parity bit in the most significant position. Include blanks
between names.
12. Express the following decimals in (1) 2,4,2,1 code and (2) 8, 4, 2, 1 code
form: (a) 35, (b) 7, (c) 566, and (d) 8945.
13. What is the difference between ASCII and EBCDIC codes? Why are
EBCDIC codes used?
14. Why is Gray code called the reflected code? Explain.
1. What is (a)
(i) The radix of a number system and why is it important?
(ii) A radix pont
(b) Why are 'complements' used to represent negative numbers. Why is
complements used in place of sign plus magnitude to represent negative
number?
(c) Using one's complement arithmetic subtract the binary equivalent of 18 from
25 giving the final decimal result. Show all steps necessary.
3. Explain two advantage or disadvantages of binary coded decimal numbers
over true binary numbers
4. Convert
(i) The following decimal numbers to binary numbers
(a) 12.12 (b) 137
(ii) The following hexadecimal numbers to binary numbers
(a) 33FB (b) A047 (c) FDB8 (d) 2C9E
(iii) The following numbers into decimal
(a) 11118 (b) FFEE Eb
hex hex
(iv) Represents the following 8421 BED codes to decimal
numbers. (i) 1000011000000001 (ii) 010001010111
,
6. Translate the following ASCII codes into English 476F644C 75636B.
30
CHAPTER TWO
INTRODUCTION TO LOGIC GATES
2, 1 Diodes and Transistors are made from 8emiconductors, so called
because they lie between the metals aud insulators in their ability to conduct
electricity. Germanium and silicon are the most Popular semiconductors
because of their use and are hard, brittle crystal by nature. Germanium possess
a positively charged nucleus of+32 while th silicon atoms nucleus possesses
positive change of + 14. The total positive charge of the nucleus is equalized by
the total effective negative charge of the electrons, this result in an atom having
a positive or negative effective charge but neutral. ...
The electrons traveling within their respective orbits possesses energy
since they are a definite mass in motion, The energy level is detected by
electron's momentum and its physical proximity to the nucleus. The
conductivities of these materials is of greater importance have because the
more likely the chances of outermost (valence) electrons breaking away for
conduction, Conductivity can be increased by either heating the crystal or by
adding other types of materials (impurities) to the crystal when it. is formed, The
impurities may be donors such as arsenic which dona s extra free electron to the
crystal, since arsenic atom contains five electrons in its valence band, or
acceptors such as aluminum which' accepts" electrons from th crystal to
produce free holes since each aluminum atom cont(lins only three electrons in
its valence band.
A semiconductor which contains donor atoms is called an n-type
semiconductor since conduction is by virtue of free electrons (negative charge)
that which contains acceptor atoms is called a p-type semiconductor and the
conduction here is by virture of holes in the crystal (positive charger).
Diodes
If a p-type region and an n-type region are formed in the same crystal structure,
we have a device known as a diode. The boundaries between the two regions is
called a junction, the terminal connected to the p region is called the anode and
that connected to the n region is called the cathode. A diode is shown in figure
2.1. for two condition of applied voltage. In figure 2.1 a the anode is at a negative
voltage with respect to the cathode and the diode is said to be reverse based.
The holes in p-region are attracted towards to anode terminal and
electron in the n-region are attracted towards the cathode terminal congruently
two charges flow across the junction and no current will flow through the diode.
In figure 2-1 (b) the anode of the diode is at a positive voltage with respect to the
cathode and the diode is said to be forward biased. In this case, the holes in the
p region will flow across the junction and recombine with electrons in the n
31
region, similarly, the electrons in the n-region will flow across the junction and
recombine with the holes in the p- region. The net result will be a large current
through the diode for only a small applied voltage.
Figure :2.l: 'Conduction in a PN junction-diode
Transistors
A transistor is formed by a thin p-region or n-region between two n regions and
two p - regions respectively. The former is called an N PN transistor while the
later is called a P NP transistor It has three region and two junctions, the three
region are called emitter. collector and base while the junctions are emitter
junction and the collector junction. Figure 2.2 shows an N PN transistor.
Figure 2.2 NPN transistor common emitter Configuration
In most applications the transistor is. ,used in common emitter configuration; as
shown in figure.' 2.2 when the current through the output
Anode
P-region
Junction
N-refion
Cathode
Base
Collector
Vcc
Emitter
Vcc
R
E
L
B
N type collector region
P type Base region
Collector junction
N type Emitter region
Emitter junction
32
moderate input impedance (13k)
moderate output impedance (50k)
high current gain (35)
High voltage gain (-270)
highest power gain (40db)
lowest input impedance 35
highest output impedance (1M)
low current gain (-0.98)
high voltage gain (380)
moderate power gain (26db)
highest input impedance (350kW)
lowest output impedance (500kW)
high current gain (-36)
unity voltage gain (1.00)
lowest power gain (15db )
Common
Emitter (CE)
Common Base
(CB)
Common
Collector (CC)

Emitter Follower
33

BE
2.2 Diode Logic
Logic gates are used to obtain output signals that are usually pulses when
certain combination of input signals occur. Two distinct voltage levels are
provided and represent the binary number I and 0 corresponding to the true and
False logic. The diode can be used to realize the above function. Suppose there
are two inputs, A and B then the output is given by a signal A or B or both. There
are four possible combination of input A and B. and the output is related to them
and indicated in a table called the truth table.
(a) Diode Logic circuit
(b) Response with time
Figure 2.4 Diode Logic OR gate representation.
For no input (zero voltage) in fig 2 .4(a), no current flows. and the output is zero
(0). An input of +5v (1) at either terminal in A or B or both forward biases the
5
C
0
5
A
0
5
B
0
5v
A
B
A + B
34
I
I
R
voltage rises to nearly 5v (1). For two input that varies with time, the response is
show in 2.4(b). The resistor R must be large compared with the resistance of a
forward biased diode and small compared with that of the reverse biased diode,
The truth table for the OR gate just described is show in table 2.1 below;
Table 2.1: Truth Table for diode logic or gate
A B C
Positive Positive Positive
Positive No signal Positive
No signal Positive Positive
No signal No signal No signal
If the diodes in figure 2.4a are reversed, they conduct negative pulse inputs. If
the diode are reverse biased the output appears only when there are inputs at A
and B. Though there may be several input terminals, if anyone of the input is
zero (0) current flows through the reverse biased diode and the output is nearly
zero. The circuit diagram and pulse train is shown below.
(a) (b)
Figure 2.5 Diode AND gate. (a) logic circuit (b) Typical response.
5v
5v
A.B
R
L
R
5
A
0
5
B
0
5
A+B
0
t
v
35
Table 2.2. Truth table for diode AND gate
A B C
Negative Negative Negative
Negative No signal No signal
No signal Negative No signal
No signal No signal No signal
A transistor can be used to restore the levels of the signal in the OR gate since
the output is always less than the input. The result here is a NOT OR or NOR
operation as shown in figure 2.6 below;

(a) Circuit diagram

(b) Response
Figure 2.6 Diode transistor NOR gate.
A
B
C
RK
Rc (RL)
Q1
-VB
A+B
+5v
t
v
5
C= A+B
0
5
B
0
5
A
0
36
In this circuit with no inputs, the transistor switch is held off by negative base
voltage and the output is +5V( 1 ). A positive voltage terminal A or B raises the
base potential, forward biases the emitter junction, turns the transistor ON, and
drops the output close to zero(0). The transistor provides how output
resistance making this NOR element to be a supplier of inputs to many other
gates. It has a universal function of achieving all other basic logic operation with
its use alone. The diode transistor combination can be used to perform an
inverted AND function. See diagram in figure 2. 7
(a) Circuit diagram
(b) Response
Figure2.7 Diode transistor NAND gate
A
B
RB Rc
A . B
+5v
5
A
0
5
A
0
5
A.B
0
t
v
37
With positive inputs at A and B i.e. (1 AND1), the diodes are reversed biased,
and no current flows. The positive base current causes heavy collector current
and the output is nearly zero (0), if either of the inputs has a zero as their input
value, at least one diode conducts to ground, the emitter junction drops below
the critical value, no base current and hence no collector current flows, and the
output is +5v (1).
2.3 Transistor Logic Gates
Transistor transistor logic (TTL) is a very prominent logic family that uses a
bipolar junction transistor throughout for a gate.
Figure 2.8 TTL gate with resistor pull- up
The circuit in figure 2.8 is broken down to three parts, the combiner, the restore
and the buffer; The combiner consists of a multiple emitter transistor T1 (this
number can be increased). The input signals to the gate are connected to a
separate emitter which forms its junction with the base. If any base-emitter
junction is sufficiently forward biased the transistor will be in the conductive state
(i.e.. current will tend to flow in voltage supply particular base-emitter junction
will be forward biased whenever the emitter is close to ground) . Thus, the
transistor will be in the conductive state whenever any emitter has a voltage that
is low (0). In this case, a significant amount of current flows out of the emitters
that have a low voltage, which is primarily due to the base current. When all
emitters are high (1), the transistor will be cut off, which imply little current flow in
any emitter.
The Restorer consists of the transistor T2 and two resistors. The base of T2 is
connected to the collector of T so that the current in both leads is the same.
1
B
A
R
R
R
T1
T2
T3
Combiner Restorer Buffer
+5v
output
38
39
9
B
A
R
R
R
T1
T2
Combiner Restorer Buffer
+5v
TL
TH
R
40

H
Figure 2.10 Basic RTL NOR gate.
RTL NOT Gate
The NOT element is an inverter', the output is the complement of a single input.
With no input (0) the transistor in figure 2.10 switch is held open by a negative
base voltage and the output is +5v (1). A positive input voltage (1) forward biases
the emitter junction collector current flows. and the output voltage drops to few
tenths of a volt (0).For a changing input the output response is shown in figure
411.b.
(a) Transistor Circuit
A
B
C
R1
R2
R3
RE
Vcc
Output
- VBE
R
A
Rc
output
A
41
y = A.B.C
(b) Response
Figure 2.11 The transistor NOT gate.
2.5 Common Logic Systems
In this section we will attempt to describe briefly different logic systems giving
their diagrams, simple description, features and also giving suitable transistor
and diodes: RTL:
Resistor Transistor Logic (NOR)
Figure 2.12 Circuit Diagram for RTL
5
A
0
5
A
0
v
t
y = A+B+C
output
Vcc
RB
A
B
C
R1
R2
R3
42
Description:
Logic is performed by resistors Any positive input produces an inverted output
irrespective of the other inputs. Resistors R gives temperature stability.
n
Features:
The circuit design is straight forward, All logical operations can be performed
with only this circuit. Many transistors readily meet the steady state
requirements.
Germanium Silicon
High Speed Low Speed High speed Low speed
2N78 2N526 2N705 2N335
2N167 2N526A 2N711 2N656A
2N169A 2N1304 2N828
2N396A 2N1305 2N964
2N525 2N1924 2N994
Table 2.4 Suitable Transistors
RTCL: Resistor Capacitor Transistor Logic.
Description:
Same as RTL except that capacitors are used to enhance switching speed. The
capacitors increase the base current for fast collector current turn on and
minimize storage time by supplying a charge equal to the stored base charge.
Features:
Faster than RTL at the expense of additional components and stringent stored
charge requirements.
43
Figure 2.13. Circuit Diagram
Table 2.5 Suitable Transistors.
Germanium Silicon
Low speed High speed Low speed High speed
2N396A 2N705 2N1613
2N404 2N711 2N2193
2N634
DL: Diode Logic.
Description:
Logic in performed by diodes. The output is not. inverted, arnplifiers are
required to maintain the correct logic levels through several gates in series.
Features:
Several gates may be used between amplifiers. High speeds can be attained.
Non-inversion amplifiers circuit design problems. Relatively inexpensive
components are used.
y = A + B
R
B
R
A
44
(a)
(b)
Figure 2.14. Diode Logic Circuit Diagram.
A
B
C
A+B+C
A
B
C
A+B+C
+Vcc
45
Table 2.6. Suitable Transistors and Diodes.
Germanium Silicon Diode (silicon)
Low speed High speed Low speed High speed High speed
2N78 2N705 2N333 2N706 IN3604
2N167 2N711 2N337 2N708 IN3605
2N396A 2N964 2N656A 2N1613 IN1613
2N526 2N994 - 2N2193 -
2N635A
DCTL: Direct Coupled Transistor Logic.
Description:
Logic performed by transistors. V and V , measured with the transistor in
CE nl
saturation, define the two logic levels. VCI must be much less than V,\! to ensure
stability and circuit flexibility
Features:
Very low supply voltages may be used to achieve high power efficiency and
miniaturization Relatively fast switching.
(a) (b)
Figure 2.15. Circuit diagram for Direct Coupled Transistor Logic.
B
A
A.B
Vcc
B
A
A+ B
46
DTL: Diode Transistor Logic
Description:
Logic is performed by diodes. The output is inverted and the transistor acts as
an amplifier. This is essentially an extension of the logic discussed above.
Features:
High speed can be attained. the impedance and voltage levels from stage to
stage are well defined.
(a)
(b)
Figure 2.16. Circuit Diagrams for Diode Transistor Logic.
A.B.C
Vcc
A
B
C
A
B
C
A+B+C
+Vcc
47
Table 2.7. Suitable Transistors and Diodes.
TDL: Tunnel Diode Logic.
Description:
Logic is performed by tunnel diode switching from low to high voltage state.
Whether circuit represents AND or OR gate depends on the bias current
through the resistor R. Tunnel diode biased near peak current for OR gate and
close to ground for AND.
Features:
Current flowing through input resistors determines logic. Circuit is basically
simple and very high speed is obtainable.
Suitable Transistors and Diodes:
TD - lA,
TD - 2A,
TD - 3A,
TD-31IB
These are German i um Tunnel diodes.
48
Germanium Silicon Silicon diodes
Low speed High speed Low speed High speed High speed
2N78 2N705 2N333 1N3604 2N706
2N167 2N711 2N337 1N3605 2N708
2N396A 2N964 1N3606 2N914
2N526 2N994 2N1613
2N635A
2N1304
2N1305
Figure 2.1 . 7 Circuit diagram of Tunnel Diode Logic.
A
B
C
+Vcc
A+B+C
or
A.B.C
49
I. Explain the following briefly
(i) P-type material and n-type semiconductor materials
(ii) Majority and minority carriers
(iii) Impurity conduction.

2.(i) Explain with aid of a diagram conduction in a PN junction diode. (ii) What is
a truth table? Explain the diode logic OR gate and give its truth table.
3. Explain with aid of a diagram the operation of an NPN transistor in common
emitter configuration.
50
CHAPTER 3
COM BINATIONAL AND SEQUENTIAL LOGIC ELEMENTS
3.0 General Characteristics
Consider a general model of a switching system shown in figure 3.0. We have n
inputs or e~citation variables, X (t), k = 1,2, ------. n and p outputs, or response
k
variables, z, (t),i = I, 2, ----- p, all assumed to function the time. If at any instance
the present value of the inputs relay determines the output we describe this as a
combinational system.
Figure 3.0 General Model
This system can be described by the equation of form Zi = fi (X1, X2. ----------, Xn)
Here the value of variables will be those at some single time and their
dependence on time need not be indicated. On the other hand if the present
value of outputs is not solely input dependent but also on the past in story of the
system, then we call this a sequential system.
Digital computers are very important example of sequential system because
there are many levels of sequential operation involving sequential use of
subsystems that are themselves sequential. Example the addition of a number
into the accumulator of a digital computer, here the resultant sum depends on
both the number and on what has been put into the accumulator previously.
3.1 Basic Logic Gates
The term "Logic" usually used to refer to a decision-making process. A logic
gate, then is a circuit that can take a decision on whether to say yes or no at the
output based on the inputs. A logic gate is a combinational logic which the output
is controlled by the state of the input and if the inputs are changed a new output
is obtained.
X
R

(t)

Z

(t)

X
R

(t)

Switching

System

Z (t)

X
R

(t)

Zp (t)

51
L ic i cuit o nl combinational logic element ha e no memor
l ment c n be nthe zed from the basic l i ates The
basic ran e of l i tes k w b th n m D. OR OT OR and
D
The AND Logic Gate
The peration of thi g can be best de crib u in imple
switching circuit The i nal camp will il uminate onl if and B re closed or
we could sa the output F wil be logic 1 if input and input B r t logic 1 It is
sometimes called the all or nothing gate The truth table shows the output
tat r all po ible c mbinations of inputs Figure 3 Show The B i Ide
og c r s containing f o y v y,
e e s a sy si og c g
g og c ga i no y e a es A N , N
NAN
o s ate s ed by s g a s
s g y a
y A a e a .
" "
s e fo ss o s as c a
though memory .
s ,

A
.
. .1
N
.
.
. l
l

Figure 3.1 The AND Logic Gate
(b) Logic symbol
Y = A.B
(a) Circuit using switch

Inputs

Outputs

B

A

Y

Switch
Voltage

Binary

Switch
Voltage

Binary

Light

Binary

LOW

0

LOW

0

NO

0

LOW

0

HIGH

1

NO

0

HIGH

1

LOW

0

NO

0

HIGH

1

HIGH

1

YES

1

( c) Truth Table
A
B
Y
52
A short method used to represent the AND operation is called Boolean
expression (from Boolean or Logic algebra) The Boolean exprcssion is a
universal language used in digital electronics. In this expression the AND
operation is represented by a dot this means that the operation above has a
Boolean expression A . B = Y in Boolean form.
The OR Gate
This is sometime called the "any or all gate can be represented by parallel
connected switches as shown in figure 3.2 which also shows the logic symbol.
The signal lamp will only illuminate if switch A or switch B or both are closed. Y
will be logic 1 if input A or B or both inputs are at logic 1. The truth table lists the
switch and light conditions for the OR gate circuit in Fig 3. 2. The Boolean
expression t"l"lr the OR function has a plus sign as the symbol for OR.
( b) Logic Symbol and Boolean
Expression
(a) Circuit Using Switches
Figure 3.2 The OR Gate Logic.
A
B
F
Y = A + B
Inputs Outputs
B A Y
Switch Binary Switch Binary Light Binary
Open 0 Open 0 NO 0
Open 0 Closed 1 YES 1
Closed 1 Open 0 YES 1
Closed 1 Closed 1 YES 1

( c) Truth Table
A
B
53
The NOT Gate or Inverter
The NOT gate is a single input gate which gives an output that is the opposite of
the input It is often called an inverter or negator since it gives an outp hat is
not the same as the input If the input is A the output is NO which is written as
A (bar A) the mall c rcle on the output of t gate always indicate a change of
sign The truth table shows the possible state for all possible inputs in figure 3.3.
(a) Logic symbol and Boolean expression.
(b) Truth Table for the inverter.
Figure 3.3 The NOT Gate.
-
.
.
.
.
.
.
ut t
, T A
. s i he
The Buffer
This is a device that has only one input and one output and has same logic input
and output It has no effect upon the logic le els of the circuit i e the input and
output logic levels are identical It is used to interface logic circuits which
demand more current than could be suppl ed by an un buffered logic circuit
Since he output current can be much greate they exhibit current gain the
mb l and the truth table of the buffer is shown in figure 3.4.
v .
i
t r,
sy o
.
Input Output
Voltage Binary Voltage Binary
Low 0 High 1
High 1 Low 0

Input Output
0 0
1 1

(a) Logic Symbol
(b) Truth Table
Figure 3.4 The Buffer
Input
A
Y
Y = Y
Input
A
54
The NAND Gate
The NAND gateis a NOT AND, or an inverted AND Function The standard
logic symbol for the NAND gate is shown in figure 3.5 (a) the little invert bubble
(small circle) on the right means to In ert the AND The Boolean expression for
the NAND is the invert for the AND as shown in the logic diagram This gate is a
universal gate because it can be wired to create any other gate
.

v
.
" "
.
.
(a) Logic Symbol and Boolean Expression
(b) Truth Table for AND and NAND Gate
Figure 3.5 The NAND Gate.
The truth table shows that the NAND gate is developed by inverting the AND
outputs. NAND gate are usually applied in industrial practice and used
extensively in digital equipments. The NAND can be combined to form other
logic gates, hence the name the universal logic element. The reader should
attempt to realize the other gates using the NAND gate.
The NOR Gate
This is a NOT OR gate with an output of an OR gate inverted to form a NOR
gate. The logic symbol and the Boolean expression for the OR function (A + B) is
shown, the Boolean expression for the final NOR function is A + B.
A
B
y = A . B
Input Output
B A AND NAND
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

55
(a) Logic Symbol and Boolean
Expression.
(b) Truth Table for OR and NOR Gates.
Figure 3.6 The NOR gate.
The Exclusive OR (XOR) Gate.
This refers to "any but not all gate" the term exclusive is shortened using X
hence we have X OR gate. The symbol (+) means the terms are X ORed
together. The logic symbol, Boolean expression and truth table for the XOR is
shown in figure 3. 6. It produces a HIGH output only when an odd number of
HIGH inputs are present. The exclusive OR gates are used in variety of
arithmetic circuits.
(b) Truth Table for OR and NOR
gates.
Figure 3.7 The Exclusive OR Gate.
The Exclusive NOR Gate
Th is short n d X OR te It has an added n t u ble on th utput
ide Th Bo lean e press on for th X OR g te h s bar o er th A B
e pression telling us about the n ert d output Thi te is ummarized in fig
3
is e e N ga i ver ed b b e o
s e o x i e N a a a v e
x i v e s ga s
.
.
. .
.
Input Output
B A OR NOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0

A
B
F = A + B
A
F = A + B
Input Output
B A OR XOR
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 0

+
B
56
( c) Truth Table for XOR and
XNOR gates.
Figure 3.8 The Exclusive NOR gate.
Gates with more than Two Inputs.
Th t o input gates has four possible states or options hen considerin the
t uth table The Boolean expression for a two input ND ate for in tance is Y =
A B and for a three input we should h e B C Y with th s expression e
should expect an increment in th op ons of the truth table inputs If we apply
the expression 2 where n represents the number of inputs e would have it
that for a t o nput we ill ha e 2 4 and for three inp we will have 2 8 and
four input we ill ha e 2 16 inputs etc respectively Consider an A D ate with
three inputs in figure 3 9 for further expl nation The re der can de elop the
truth bl for a four input OR gat
e w w g
r A g s
av A . = i w
e ti
n
, w
2 3
w i w v ut
4
w v = N g
a a v
ta e e.
(a) Logic Symbol and Boolean Expression for a three input OR gate.
. .
.

= =
.
. .
+ F = A B
A
B
Input Output
B A XOR XNOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1

A
B
C
F = A . B . C
57
(b) Truth Table for three input AND Gate.
Figure 3.9 The Three Input AND Gate.
Since we frequently run into gates that ha e fr m t o to as much as eight or
more inputs the basics co ered her i h nd reference we need to expend
the number of inputs to a t
3.2 LOGIC NETWORK AND TIMING DIAGRAMS
Logic Network.
Individual ogic gates ma be connec ed to provide any desired output The
result of the combination Can be found by working through each gate in the
network in turn producing the truth table for the particular network Here are
some examples;
I. An AND and NOT gate are connected together, complete the truth table
for this logic network
Il A NAND gate has a NOT gate on each of its inputs Draw the circuit and
complete the truth table
Ill A logic system has three inputs as shown in the figure below develop
the truth table for this arrangement
v o w
, v e s a a y
ga e.
l y t
.
,
.
.
.
.
.
'
.
. .
,
Inputs Outputs
C B A Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

58
Figure 3. 10. Logic network for example (iii)
(iv) A logic System has three inputs as shown in the figure 3 11 Develop the
truth table
.
.
.
Figure 3.11 Logic Network For example (iv)
.

Solution:
Work out progressively from left to right through the individual gates, recall that
for any two input logic gates there are four possible combinations and for the
n
three input there are eight combinations from the expression 2 .
Figure 3.12 Logic Network
(
A
B
C
F
D
F
A
B
C
A
B
C
F
59
The truth table for figure 3.12 is given below,
(ii)
Figure 3.13 Logic Network for Question (ii).
From the network shown in figure 3.13 the truth table is as follows:
(iii) All possible combination are shown in column A B C and there will be 2
rows in the table The truth table is shown below:
, ,
.
, '

A B C F
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1" 0

A

B

A

B

F
0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 1 0 0 1

60
A
B
F
A
B

Truth Table.
(v)
Truth Table.
As we saw in example (iii) the truth table will have three inputs as shown
below:
A B C D F
0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

1

0

1

1

1

1

1

A B C D F
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

61
Timing Diagrams
In most applications, the inputs to a gate are not stationary levels but are voltage
waveforms that change frequently between HIGH and LOW logic levels. A
Timing Diagram can show graphically the transitions (Inputs [Events]) and
states (Outputs) of the switching voltage waveforms.Examples of pulsed AND
gate operation with a timing diagram showing input and output relationships
below. For each of the diagram produce their truth table
A and B are both HIGH during these four time intervals.
Therefore F is HIGH
A
B
X
1 0 1 1 0
1 1 1 0 0
1 0 1 0 0
t
1
t
2
t
3
t
4
t
5
A
B
X
A
B
A
HIGH
LOW
B
HIGH
LOW
X
HIGH
LOW

{

{

{

{
62
F
I
Figure 3.14 Boolean expressions for AND gates with two, three, and four
inputs.
A
HIGH
LOW
B
HIGH
LOW
X
HIGH
LOW
Inputs
Output
A
B
C
X
A
B
C
A
B
63
F
F
Figure 3.15 Example of pulsed OR gate operation with a timing diagram
showing input and output time relationships. For each of these diagram develop
the truth table.
Figure 3.16 TIMING DIAGRAM (Pulsed Operation)
Figuren3.16. Timing Diagram.
t
1
t
2
t
3
t
4
A
B
X
A
B
1 1 O O
1 1 O O
O 1 1 1
64
A
B
C
D
X
A
B
C
D
F
3.3 Logic Symbols
The logic symbols used so far in our discussion are the primitive ones that is
recognized by all in the electronic industry. Manufactures data manuals include
traditional logic symbols and recently the IEEE functional symbols are also
include. Those symbols are in accordance with ANSI/EEE standard 91-1984
and IEC publication 617-12. They are commonly called "dependency notation".
All the IEEE logic symbols are rectangular with an identification character
inside the rectangle. Characters outside the rectangle are not part of the
standard symbol as it may vary with manufactures. The comparison between
IEEE logic gate and primitives logic gate symbol is shown in Figure 3.17.
Logic
Function
Primitive
logic symbol
IEEE Logic
Symbol
Figure 3.17 Logic Gate Symbols
A
B
& F
A
B
>1 F
A F 1
A
B
F
A
B
>1 F
A
B
=1 F
A
B F = A.B
AND GATE
A
B F = A+B
OR GATE
A
F = A
NOT or INVERTER
A
B
F = A.B
NAND GATE
A
B
F = A+B
NOR GATE
A
B
F = A+B
EXCLUSIVE-OR GATE
Inputs
A B
Output
F
o o
o 1
1 o
1 1
o
o
o
1
A B
F
o o
o
o 1
1
1 1
o
1
1
1
o
o
A F
A
=
-
1
1
A B
A B
F
o o
o
o
1
1 1
1
o
1
1
1
F
o o
o
o
1
1
1 1
1
o
o
o
F A B
o o o
o
o
o
1
1 1
1 1
1
65
1. (a) Draw the primitive logic symbols for the following;
(I) Two input AND gate
(ii) Two input XOR gate
(iii) Two input NOR gate
(iv) Four input NAND gate
(b) Write the Boolean expression for each gate and Draw the truth
table for each gate in question.
Given 4 two input AND gate, draw how you will produce a five input AND
gate
3. Draw the IEEE standard logic symbol for a three input XNOR gate
4. Draw the logic wiring of NAND gate to realize the seven basic primitive gate
(AND OR NAND NOR, XOR and XNOR)
5. Develop the truth table for the logic Network shown below;
(I)
(ii)
2.
.
.

.
, , , .

F
D A
B
E
F
D A
B
E
66
(iii)
6. State the advantages of edge triggering and differentiate between leading `
and trailing edge triggered latches.
7. What type of logic circuit can perform basic addition and what limitation does it
have.
67
CHAPTER
BOOLEAN ALGEBRA AND DIGITAL LOGIC.
4.1. Introduction
Boolean algebra provides the foundation for both computer hardware and
software. An understanding of this mathematical system can help you better
appreciate the connection between software and hardware. Boolean algebra is
a mathematical system with its own set of rules (postulates), theorems, and
values. In many respects, boolean algebra is similar to the real-arithmetic alge-
bra you studied. In most respects, however, boolean algebra is actually easier
to learn than real arithmetic algebra. The features of any algebraic system
including operators, closure, commutativity, associativity, distribution, identity,
and inverse. Then it presents some important postulates and theorems from
boolean algebra and discusses the principle of duality that lets you easily prove
additional theorems in boolean algebra.
The Truth Table is a convenient way to visually represent a boolean function or
expression. Every boolean function (or expression) has a corresponding truth
table that provides all possible results for any combination of input values. This
chapter presents several different ways to construct boolean truth tables.
Although there are an in?nite number of boolean functions you can create given
n input values, it turns out that there are a finite number of unique functions
n
possible for a given number of inputs. In particular, there are 2^2 unique
boolean functions of n inputs. For example, there are 16 functions of two
2
variables (2^2 = 16). Since there are so few boolean functions with only two
inputs, it is easy to assign different names to each of these functions (e.g., AND,
OR, NAND, etc.). For functions of three or more variables, the number of
functions is too large to give each function its own name. Therefore, we'll assign
a number to these functions based on the bits appearing in the function's truth
table.
Algebraic manipulation of boolean functions and expression allows us to
prove new theorems in boolean algebra, simplify expressions, convert
expressions to canonical form, or show that two expressions are equivalent.
Since there are an in?nite variety of possible boolean functions, yet a ?nite
number of unique boolean functions (for a ?xed number of inputs), clearly there
are an in?nite number of different functions that compute the same results. To
avoid confusion, logic designers usually specify a boolean function using a
canonical form (the sum of minterms form and the product of maxterms
form.). If two canonical equations are different, then they represent different
boolean functions.
4
68
Although the canonical forms provide a unique representation for a given
boolean function, expressions appearing in canonical form are rarely optimal.
That is, canonical expressions often use more literals and operators than other,
equivalent, expressions. When designing an electronic circuit or a section of
software involving boolean expressions, most engineers prefer to use an
optimized circuit or program since optimized versions are less expensive and,
probably, faster. Therefore, knowing how to create an optimized form of a
boolean expression is very important. The implementation of addition,
decoders, memory, shift registers, and counters is achieved using the boolean
functions.
Key Features
The key features of Boolean Algebra are,
1. Use Of Binary Data
There are two conditions in Boolean Algebra: TRUE (or Present) and FALSE (or
Absent). These two states are represented in base 2: 1 indicates presence and
0 indicates absence.
2. Use Of Truth Table To Represent Data
In order to use Boolean Algebra as a technique of qualitative comparison, it is
necessary to construct a data matrix as a truth table.
3. Boolean Addition (OR)
In Boolean Algebra, if A + B = Z, and A = 1 and B = 1, then Z = 1. In other words 1 +
1 = 1. The basic idea in Boolean Addition is that if any of the additive terms is
satisfied (Present), then the outcome is true (Occurs). Addition in Boolean
Algebra is equivalent to the logical operator OR. Thus the statement A + B = Z
becomes: If either A equals1 OR B equals 1, then Z equals 1.
4. Boolean Multiplication (AND)
Boolean Multiplication differs substantially from normal multiplication. Boolean
Multiplication is relevant because the typical social science application of
Boolean Algebra concerns the process of simplifying expressions known as
SUMS OF PRODUCTS. A product is a specific combination of causal
conditions eg.
F = Abc + aBc + abC + ABc + AbC + aBC + ABC
5. Combinatorial Logic
The absence of a cause has the same logical status as the presence of a cause
in Boolean Analysis. Boolean Multiplication indicates that presence and
absence conditions are combined.
69
6. Boolean Minimization
If two Boolean expressions differ in only one causal condition, yet produce the
same outcome, then the causal condition that distinguishes the two
expressions can be considered irrelevant and can be removed to create a
simpler, combined expression. eg.
If Abc = F and ABc = F
Then this allows the replacement of these two terms with the single, simpler
expression:
Ac = F (ie. the value of B is irrelevant. Cause B may be either present or absent ,
F will still occur.)
7. Implication
A Boolean Expression is said to imply another if the membership of the second
term is a subset of the membership of the first.
eg. A implies Abc because A embraces all the members of Abc (That is, Abc is a
subset of A)...The membership of Abc is included in the membership of A. Thus
A implies Abc.
8. Prime Implicants And Prime Implicants Charts
The first step in the Boolean analysis of these data is to attempt to combine as
many compatible rows of the truth table as possible (See 6. Boolean
Minimization). Thus:
S = AbC + aBc + ABc + ABC (These are referred to as PRIMITIVE
EXPRESSIONS)
ABC combines with AbC to produce AC.
ABC combines with ABc to produce AB.
ABc combines with aBc to produce Bc.
Thus S = AC + AB + Bc (These equations, reduced to their lowest level are
referred to as PRIME IMPLICANTS)
Product terms such as those in the preceding equation which are produced
using this simple minimization rule - combine rows that differ on only one cause
if they have the same output values - are called PRIME IMPLICANTS. Usually
each PRIME IMPLICANT covers (that is implies) several primitive expressions
in the truth table. In the partially minimized equation given above, for example,
prime implicant AC covers two primitive Boolean expressions listed in the truth
table: ABC and AbC.
In order to determine which prime implicants are logically essential, a
minimization device known as a PRIME IMPLICANT CHART is used.
Minimization of the prime implicant chart is an optional, second phase of
70
Boolean Minimization. The goal of this second phase of the minimization
process is to cover as many of the primitive Boolean expressions as possible
with a logically minimal number of Prime Implicants. Analysis of the Prime
Implicant Chart, leads to the final reduced Boolean expression containing only
the logically 'Essential Prime Implicants.
9. Use Of De Morgans Law
It is often useful to assess the combinations of conditions associated with the
absence of an outcome. Rather than start from the very beginning.....it is
possible to apply De MORGAN?s LAW to the solution already derived for
positive outcomes to obtain the solution for negative outcomes.
Thus if S = AC + Bc to find the negative outcomes: (Two Rules)
RULE 1: Elements that are coded present in the reduced equation (Say A in the
term AC) are recoded to absent, and elements that are coded absent (Say c in
the term Bc) are recoded to present.
RULE 2: Next, logical AND (x) is recoded to logical OR (+), and logical OR (+) is
recoded to logical AND (x).
Applying these two rules:
S = AC + Bc becomes:
S = (a + c) (b + C) which goes to:
S = ab + ac + bc
?De MORGANs law thus provides a convenient shortcut for minimizing
negative instances.?
10. Necessary And Sufficient Causes
NECESSARY: A cause is defined as necessary if it must be present for a
certain outcome to occur.
SUFFICIENT: A cause is defined as sufficient if by itself it can produce a certain
outcome. Thus if: S = AC + Bc (No cause is either necessary or sufficient)
S = AC + BC (C is necessary but not sufficient)
S = AC (Both A and C are necessary but not sufficient)
S = A + Bc (A is sufficient but not necessary)
S = B (B is both necessary and sufficient)
11. Factoring Boolean Expressions
Often it is useful to factor the results of Boolean analysis. Example. if: S = AB +
AC + AD.
71
It can be factored to show that A is a NECESSARY CONDITION:
S = A (B + C + D) or in a more complex equation; if: S = abc + AbC + abd + E
this can be shown as: S = a (bc + bd + E) + A (bC +E)
4.2. Boolean Algebra
Boolean algebra is a deductive mathematical system closed over the values
zero and one (false and true). A binary operator de?ned over this set of
values accepts a pair of boolean inputs and produces a single boolean value.
For example, the boolean AND operator accepts two boolean inputs and
produces a single boolean output (the logical AND of the two inputs).
For any given algebra system, there are some initial assumptions, or
postulates, that the system follows. You can deduce additional rules, theorems,
and other properties of the system from this basic set of postulates. Boolean
algebra systems often employ the following postulates:
i. Closure. The boolean system is closed with respect to a binary operator if
for every pair of boolean values, it produces a boolean result. For
example, logical AND is closed in the boolean system because it accepts
only boolean operands and produces only boolean results.
ii. Commutativity. A binary operator is said to be commutative if AB =
BA for all possible boolean values A and B.
iii. Associativity. A binary operator is said to be associative if
(A B) C = A (B C) for all boolean values A, B, and C.
iv. Distribution. Two binary operators and % are distributive if A (B %
C) = (A B) % (A C) for all boolean values A, B, and C.
v. Identity. A boolean value I is said to be the identity element with respect to
some binary operator if A 1 = A.
vi. Inverse. A boolean value 1 is said to be the inverse element with respect
to some binary operator if A 1 = B and B,A (i.e., B is the opposite value
of A in a boolean system).
Boolean Operators and values
The two possible values in the boolean system are zero and one. Often we will
call these values false and true (respectively). The symbol . represents the

logical AND operation; e.g., A . B is the result of logically ANDing the boolean
values A and B. When using single letter variable names, this text will drop the
symbol; Therefore, AB also represents the logical AND of the variables A and B
72
(we will also call this the product of A and B).
logical OR operation; e.g., A + B is the result of logically ORing the boolean
values A and B. (We will also call this the sum of A and B.) Logical complement,
negation, or not, is a unary operator. This text will use the (') symbol to denote
logical negation. For example, A' denotes the logical NOT of A. If several
different operators appear in a single boolean expression, the result of the
expression depends on the precedence of the operators. We'll use the following
precedence (from highest to lowest) for the boolean operators: parenthesis,
logical NOT, logical AND, then logical OR. The logical AND and OR operators
are left associative. If two operators with the same precedence are adjacent, you
must evaluate them from left to right. The logical NOT operation is right
associative, although it would produce the same result using left or right
associativity since it is a unary operator.
Postulates.
Postulate 1: Boolean algebra is closed under the AND, OR, and NOT
operations.
Postulate 2: The identity element with respect to is one and + is zero. There is
no identity element with respect to logical NOT.
Postulate 3: The and + operators are commutative.
Postulate 4: and + are distributive with respect to one another. That is, A (B + C)
= (A B) + (A C) and A + (B C) = (A + B) (A + C).
Postulate 5: For every value A there exists a value A' such that AA' = 0 and A+A'
= 1. This value is the logical complement (or NOT) of A.
Postulate 6: and + are both associative. That is, (AB)C = A(BC) and (A+B)+C =
A+(B+C). You can prove all other theorems in boolean algebra using these
postulates.
Theorems.
Theorem1: A + A = A
Theorem 2: A A = A
Theorem 3: A + 0 = A
Theorem 4: A 1 = A
Theorem 5: A 0 = 0
Theorem 6: A + 1 = 1
Theorem 7: (A + B)' = A' B'
Theorem 8: (A B)' = A' + B'
Theorems seven and eight above are known as DeMorgan's Theorems.
The symbol + represents the
73
Theorem 9: A + AB = A
Theorem 10: A (A + B) = A
Theorem 11: A + A'B = A+B
Theorem 12: A' (A + B') = A'B'
Theorem 13: AB + AB' = A
Theorem 14: (A'+B') (A' + B) = A'
Theorem15: A + A' = 1
Theorem 16: A A' = 0
The theorems above appear in pairs. Each pair (e.g., 1 & 2, 3 & 4, etc.) form a
dual. Duality is an important principle in the boolean algebra system. Valid
expression created using the postulates and theorems of boolean algebra
remains valid if you interchange the operators and constants appearing in the
expression. Speci?cally, if you exchange the and + operators and swap the 0
and 1 values in an expression, you will wind up with an expression that obeys all
the rules of boolean algebra. This means that both expressions are legal in the
boolean algebra system.
4.3 Simplification of Boolean Expressions
The algebraic identities we studied in algebra class allow us to reduce algebraic
expressions (such as 10x + 2y x + 3y) to their simplest forms (9x + 5y). The
Boolean identities can be used to simplify Boolean expressions in a similar fash-
ion. We apply these identities in the following examples.
EXAMPLE 4.1 Suppose we have the function F(x,y) = xy + xy. Using the OR
form of the Idempotent Law and treating the expression xy as a Boolean
variable, we simplify the original expression to xy. Therefore, F(x,y) = xy + xy =
xy.
EXAMPLE 4.2 Given the function F(x,y,z) = xyz + xyz + xz, we simplify as

follows:
F(x,y,z)= xyz + xyz+ xz = xy(z + z) + xz (Distributive) = xy(1) + xz (Inverse) = xy +

xz (Identity)
At times, the simplification is reasonably straightforward, as in the preceding
examples. However, using the identities can be tricky, as we see in this next
example.
74
EXAMPLE 4.3 Given the function F(x,y,z) = xy + xz + yz, we simplify as
follows:
= xy + xz + yz(1) (Identity)
= xy + xz + yz(x + x) (Inverse)
= xy + xz + (yz)x + (yz)x (Distributive)
= xy + xz + x(yz) + x(zy) (Commutative)
= xy + xz + (xy)z + (xxz)y (Associative)
= xy + (xy)z + xz + (xxz)y (Commutative)
= xy(1 + z) + xz(1 + y) (Distributive)
= xy(1) + xxz(1) (Null)
= xy + xz (Identity
Example 4.4 Given the function E = (x + yz)(x + y') + (x + y)' we simplify as
follows;
Applying the distributive law to the product term and De Morgans law to the last
term leads to E2; then
E1 = (x + yz)(x + y') + (x + y)'
E2 = xx + xy' + xyz + y'yz + x'y'
E3 = x + x (y' + yz) + x'y'
E4 = x + x'y'
E5 = x + y'
A fairly complicated expression has been reduced to a rather simple one. Note
that E2 contains a term yy', which equals the identity element 0.We say the
expression is redundant. More generally, an expression will be redundant if it
contains
Repeated literals (xx or x + x)
A variable and its complement (xx' or x + x')
Explicitly shown switching constants (0 or 1)
Redundancies in expressions need never be implemented in hardware; they
can be eliminated from expressions in which they show up.
4.3.1. Minterms, Maxterms, and Canonic Forms
Given an expression dependent on n variables, there are two specific and
unique forms into which the expression can always be converted. The
expression E1 in the preceding section had mixtures of terms that were products
or sums of other terms. Furthermore, although E1 seemed to be dependent on
three variables, one of these variables was redundant. The final, equivalent form
75
was the sum of two terms, each being a single literal. In the general case,
expressions are dependent on n variables. We will consider two non-redundant
cases. In one case, an expression consists of nothing but a sum of terms, and
each term is made up of a product of literals. Naturally, this would be called a
sum-of- products (s-o-p) form. The maximum number of literals in a
nonredundant product is n. In the second case to be considered, an expression
consists of nothing but a product of terms, and each term is made up of a sum of
literals; this is the product-of-sums (p-o-s) form. Again, the maximum number
of literals in a non-redundant sum is n. Suppose that a product term in a sum-of-
products expression, or a sum term in a product-of-sums form, has fewer than
the maximum number n of literals. To distinguish such cases from one in which
each term is full, we make the following definition:
A sum-of-products or product-of-sums expression dependent on n variables is
canonic if it contains no redundant literals and each product or sum has exactly
n literals.Each product or sum term in a canonic expression has as many literals
as the number of variables.
EXAMPLE 3.4 Suppose F(x,y,z) = x + xy. We can also express F as F(x,y,z) = x +
x + xy because the Idempotent Law tells us these two expressions are thesame.
We can also express F as F(x,y,z) = x(1 + y) using the Distributive Law.
To help eliminate potential confusion, logic designers specify a Boolean function
using a canonical, or standardized, form. For any given Boolean function, there
exists a unique standardized form. However, there are different standards that
designers use. The two most common are the sum-of-products form and the
product-of-sums form.
The sum-of-products form requires that the expression be a collection of
ANDed variables (or product terms) that are ORed together. The function
F (x,y,z)= xy + yz + xyz is in sum-of-products form. The function F (x,y,z)= xy +
1 2
x(y + z) is not in sumof-products form. We apply the Distributive Law to distribute
the x variable in F , resulting in the expression xy+ xy + xz, which is now in sum-
2
of-products form. Boolean expressions stated in product-of-sums form consist
of ORed variables (sum terms) that are ANDed together. The function F (x,y,z) =
1
(x + y)(x + z)(y + z)(y + z) is in product-of-sums form. The product-of-sums form
is often preferred when the Boolean expression evaluates true in more cases
than it evaluates false. This is not the case with the function, F , so the sum-of-
1
products form is appropriate.
76
Example 4.6 simplify the following expressions:
i. F = A.B + A.B + B.C
= A. (B + B) + B.C
= A.1 + B.C
= A + B.C
ii. F = A.B.C + A.B.C + A.B.C + A.B.C
= A.B.C + A.B.C + A.B.C + A.B.C + A.B.C + A.B.C
= (A.B.C + A.B.C) + (A.B.C + A.B.C) + (A.B.C + A.B.C)
= (A + A). B.C + (B + B). C.A + (C + C). A.B
= B.C + C.A + A.B
Example 4.7 Show that A + A.B = A
A + AB
= A.1 + A.B
= A. (1 + B)
= A. 1
= A
Example 4.9 Simplify the boolean expression A=B?(C?(D+E+C)+F?C)
A=B?(D?C+E?C+C?C+F?C)
A=B?(D?C+E?C+C+F?C)
A=B?C?(D+E+1+F)
A=B?C? (1)
A=B?C
Example 3.xx Simplify the expression f = x'y'z' + x'y'z + x'yz' + x'yz + xyz' + xyz.
f = x'y'z' + x'y'z + x'yz' + x'yz + xyz' + xyz
= x'y'(z' + z) + x'y(z' + z) + xy(z' + z) distributive law
= x'y' + x'y + xy complementarity & identity
= x'(y' + y) + xy distributive law
= x' + xy complementarity & identity
= x' + y redundancy
77
Example 3.xx Simplify the expression F = ABC + ABC + ABC + ABC
F = (ABC + ABC) + (ABC + ABC)
F = A(BC + BC) + A ( BC + BC)
F = AB( C + C) + AC ( B + B)
F = AB + AC
4.3.2 Sum of Products Equation from Truth Table
Generating Canonical Sum of Products Form of Boolean Equation
The Sum of Products (SOP) representation of a truth table's Boolean equation
has the general form
Out = {(A B C )Out }+{(A B C )Out }+..+{(A B C )Out }.
0 0 0 0 1 1 1 1 7 7 7 7
Here, the subscripts represent the number of the row containing values of A, B,
and C. Row zero contains A=0,B=0,C=0. Row 5 contains A=1, B=0, C=1. And so
on. If any of the terms in {}equals1, then the output of the function is Out = 1
(since the value of Out is the OR of all the { }terms and the output of this OR is 1 if
any { }= 1). If the output for row k is zero (i.e., Out = 0), then that row does not
k
contribute to the SOP equation since its contribution
( {(A B C )Out } = {(A B C )0}= 0 is necessarily zero. For this reason, the SOP
k k k k k k k
Boolean equation is constructed by considering only the rows m with output Out
=1. For the example truth table above, only rows 0, 3, 4, and 7 contribute to the
m
SOP form of the Boolean equation. To understand the construction of the SOP
form, The table below shows a general truth table augmented by adding the row
number, the so-called minterm m (lower case "m" is used) for each row k and
k
the A,B,C products (A BC) for each row k such that this product equals 1
(needed to set the term in a SOP equation equal to 1). For example, in row 0, A =
0, B = 0, and C = 0. We need the "product" (AND) to equal 1, requiring that each
term equals 1. This requires that we negate each term (i.e., use for ABC = 000, A'
B'C' =111 =1 as shown in the table. For the example truth table given in the table
above, the output equals 1 for rows 0, 3, 4, and 7. The sum of products form is
therefore (using the expressions in the next to last column)
Out =(A' B' C') + (A' BC) + (A B'C') + (A BC)

This can also be expressed in terms of minterms as
Out = m + m + m + m
0 3 4 7
or, in more compact form
Out = m(0,3,4,7)
78
Expanded General Truth Table for SOP Generation
4.3.3 Product of Sums Equation from Truth Table
Generating Canonical Product of Sums Form of Boolean Equation
The Product of Sums (POS) representation of a truth table's Boolean equation
has the general form
Out = {(A + B + C )+ Ou }{(A + B + C )+ Out }..{(A + B + C )+ Out }.
0 0 0 0 1 1 1 1 7 7 7 7
Here, the subscripts represent the number of the row containing values of A, B,
and C. Row zero contains A=0,B=0,C=0. Row 5 contains A=1, B=0,C =1. And so
on. If all of the terms in{}equal 0, then the output of the function is Out = 0 (since
the value of Out is the AND of all the {}terms and the output of this OR is 1 only if
all {}= 1). If the output for row k is one (i.e., 1), then that row does not contribute
to the SOP equation since its contribution
( {(A + B + C )+ Out } = {(A + B + C )+1}=1
k k k k k k k
is necessarily one. For this reason, the POS Boolean equation is constructed by
considering only the rows M with output Out = 0. For the example truth table
M
above, only rows 1, 2, 5, and 6 contribute to the POS form of the Boolean
equation. To understand the construction of the POS form, The table below
shows a general truth table augmented by adding the row number, the so-called
Row

A B C Out
a*b*c equal to 1
Row
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
A B C
A B C
A B C
A B C
A B C
A B C
A B C
A B C
m
0
m
1
m
2
m
3
m
4
m
5
m
6
m
7
79
Row A B C Out
a+b+c equal to 0
Row
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
A B C
A B C
A B C
A B C
A B C
A B C
m
0
m
1
m
2
m
3
m
4
m
5
+ +
+ +
+ +
+ +
+ +
+ +
6 1 1 0
7 1 1 1
A B C
A B C
m
6
m
7
+ +
80
4.7. Description Of Kmaps And Terminology
Karnaugh maps, or Kmaps, are a graphical way to represent Boolean functions.
A map is simply a table used to enumerate the values of a given Boolean
expression for different input values. The rows and columns correspond to the
possible values of the function's inputs. Each cell represents the outputs of the
function for those possible inputs.
If a product term includes all of the variables exactly once, either complemented
or not complemented, this product term is called a minterm. For example, if
there are two input values, x and y, there are four minterms,
xy, xy, xy, and xy,

which represent all of the possible input combinations for the function. If the
input variables are x, y, and z, then there are eight minterms:
xyz, xyz, xyz, xyz, xyz, xyz, xyz, and xyz.

As an example, consider the Boolean function
F(x,y) = xy + xy.
Possible inputs for x and y are shown in Figure 3A.1. The minterm xy
represents the input pair (0,0). Similarly, the minterm xy represents (0,1), the
minterm xy represents (1,0), and xy represents (1,1). The minterms for three

variables, along with the input values they represent, are shown in Figure 3A.2.
A Kmap is a table with a cell for each minterm, which means it has a cell for each
line of the truth table for the function. Consider the function F(x,y) = xy and its
truth table, as seen in Example 3A.1.
EXAMPLE 3A.1 F(x,y) = xy

Minter m

x y
XY 0 0
XY 0 1
XY 1 0
XY 1 1
FIGURE 3A.1 Minterms for
Two Variables

Minter m

x

y

z

XYZ 0 0 0
XYZ 0 0 1
XYZ 0 1 0
XYZ 0 1 1
XYZ 1 0 0
XYZ 1 0 1
XYZ 1 1 0
XYZ 1 1 1
FIGURE 3A.2 Minterms for
Three Variables
81
The truth Table is:
The corresponding Kmap is:
Notice that the only cell in the map with a value of one occurs when x = 1 and y =
1, the same values for which xy = 1. Let's look at another example, F(x,y) = x + y.
The truth table is:
The corresponding kmap is:

x y
0 0
0 1
1 0
1 1
x y
0 0
0 1
1 0
1 1
0
0
0
0 0
1 1
1
x
y

0
0
1
0 1
1 1
1
x
y
82
f
0
0
0
1
f
0
1
1
1
Three of the minterms in the second example have a value of 1, exactly the
minterms for which the input to the function gives us a 1 for the output. To assign
1s in the Kmap, we simply place 1s where we find corresponding 1s in the truth
table. We can express the function F(x,y) = x + y as the logical OR of all
minterms for which the minterm has a value of 1. Then F(x,y) can be
represented by the expression x y + xy + xy Obviously, this expression is not

minimized (we already know this function is simply x + y).

4.4.1 The Concept of K-Maps
This is all well and good for something simple like the 2-input multiplexer. But
using Boolean algebra to reduce circuits can be difficult. Thus, we would like a
method or procedure that is easier. Therefore, we use Karnaugh maps. The
Karnaugh map (or K-map) is a visual way of detecting redundancy in the SSoP.
The K-map can be easily used for circuits with 2, 3, or 4 inputs. It consists of an
array of cells, each representing a possible combination of inputs.
The cells are arranged to that each cell's input combination differs from
adjacent cells by only a single bit.
This is called Gray code ordering it ensures that physical neighbours is
the array are logical neighbours as well. (In other words, neighbouring bit
patterns are nearly the same, differing by only 1 bit).
Consider the following arrangements of cells:

83

a. b
a. b
00 01
a . b a .

b

10 11

a.

b.c

a.

b.

c

a. b . c a. b .c
000

001

011 010
a .

b.

c

a .

b.c

a .

b . c a . b . c
100 101 111 110
2 Input 3 Input
4 Input
The cells are arranged as above, but we write them empty, like this:
Note that the numbers are not in binary order, but are arranged so that only a
single bit changes between neighbours. This one-bit change applies at the
edges, too. So cells in the same row on the left and right edges of the array also
only differ by one bit. The value of a particular cell is found by combining the
numbers at the edges of the row and column. Also, in general, it is easier to
order the inputs to a K-map so that they can be read like a binary number. So,
we have this grid. What do we do with it? We put 1's in all the cells that
represent minterms in the SoP. (In other words, we find the 1's in the truth table
output, and put 1's in the cells corresponding to the same inputs).

a.b.c.d
a.b.c.d a.b.c.d a.b.c.d
0000 0001 0011 0010
a.b.c.d a.b.c.d a.b.c.d a.b.c.d
0100 0101 0111 0110
1100 1101 1111 1110
1000 1001 1011 1010
2-input:
a
b
0 1
0
1
3-input:
a
bc
00 01 11 10
0
1
4 -input:
ab
bc
00 01 11 10
00
01
10
11
84
Rules for K-Maps
1 Each cell with a 1 must be included in at least one group.
2 Try to form the largest possible groups.
3 Try to end up with as few groups as possible.
4 Groups may be in sizes that are powers of 2:
0 1 2 3 4
2 = 1, 2 = 2, 2 = 4, 2 = 8, 2 = 16, ...
5 Groups may be square or rectangular only (including wraparound at the
grid edges). No diagonals or zig-zags can be used to form a group.
6 The larger a group is, the more redundant inputs there are:
i. A group of 1 has no redundant inputs.
ii. A group of 2 has 1 redundant input.
iii. A group of 4 has 2 redundant inputs.
Iv. A group of 8 has 3 redundant inputs.
v. A group of 16 has 4 redundant inputs.
The following simple examples illustrate rule 6 above.
for example,
a
bc
00 01 11 10
0
1
Eg. This cell
is abc = 110
85
00 01 11 10
0
1
1 1 1 1
1
BC
A 00 01 11 10
0
1
BC
A
1 1
1 1
Y = A + BC Y = C
Groups of 8 are similar.....
AB
CD
00 01 11 10
00
01
11
10
1 1 1 1
1
1
1 1
1
1
(Note the overlap
and wraparound)
Y = D + AB
4.4.2 KMAP SIMPLIFICATION
To use this map to reduce a Boolean function, we simply need to group ones.
This grouping is very similar to how we grouped terms when we reduced using
Boolean identities, except we must follow specific rules. First, we group only
ones. Second, we can group ones in the Kmap if the ones are in the same row
or in the same column, but they cannot be on the diagonal (i.e., they must be
adjacent cells). Third, we can group ones if the total number in the group is a
power of 2. The fourth rule specifies we must make the groups as large as
possible. As a fifth and final rule, all ones must be in a group (even if some are in
a group of one).See the following illustration.

1. Groups Contain Only 1s 2. Groups Cannot Be Diagonal
3. Groups Must Be Powers of 2 4. Groups must be as large
as possible.
As showh in illustration 1 - 4, (a) in the four cases above represents the
incorrect representations of variables in the kmap of any variable, while (b)
represents the correct representations.

(a)
(b)
(a)
(b)
0 0 1
1 1 1
0 1 x
y
0 0 1
1 1 1
0 1 x
y
(a)
(b)
0 0 1
1 1 1
0 1 x
y
0 0 1
1 1 1
0 1 x
y
(a)
(b)
0 0 1
1 1 1
0 1 x
y
0 0 1
1 1 1
0 1 x
y
0 0 1
1 1 1
0 1 x
y
0 0 1
1 1 1
0 1 x
y
86
Karnaugh Maps - Rules of Simplification
The Karnaugh map uses the following rules for the simplification of expressions
by together cells containing
n
Groups must cont ai n 1, 2, 4, 8, or i n general 2 cel l s.
1
That is if n = 1, a group will contain two 1's since 2 = 2.
2
If n = 2, a group will contain four 1's since 2 = 4 as shown below;
Each group should be as large as possible.
Each cell containing a must be in at least one group.
grouping ones. See the maps below for
explaination.
I .
ii.
iii.
adjacent
one
0
B
1
0 1 1
0 0 1
A
Group of 2
RIGHT
0
B
1
0 1 1
1 1 1
A
Group of 4
RIGHT
00 01 11 10
0 0 1 1 1
1 0 0 0 0
WRONG X
Group of 3
X
AB
C
00 01 11 10
0 1 1 1 1
1 0 0 0 1
WRONG X
Group of 5
X
AB
C
00 01 11 10
AB
C
0 1 1 1 1
1 1 0 0 1
RIGHT
00 01 11 10
AB
C
0 1 1 1 1
1 1 0 0 1
WRONG X
X
(Note that no Boolean laws broken,
but not sufficiently minimal)
00 01 11 10
AB
C
0 0 0 1 1
1 0 0 1 0
Group 1
Group 11
1 present in at least one group
87
1v. Groups may overlap.
V. Groups may wrap around the table. The leftmost cell in a row may be
grouped with the rightmost cell and the top cell in a column may be grouped
with the bottom cell.
vi. There should be as few groups as possible, as long as this does not
contradict any of the previous rules.
The Summary of the rules is as follows:
1. No zeros allowed.
2. No diagonals.
3. Only power of 2 number of cells in each group.
4. Groups should be as large as possible.
5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
00 01 11 10
AB
C
0 1 1 1 1
1 1 0 0 1
RIGHT
Group overlapping
00 01 11 10
C
0 1 1 1
1 1 0 0 1
WRONG X
AB
Group not overlapping
X
00 01 11 10
AB
C
0 1 1 1 1
1 1 1 1
Bottom cell
Rightmost cell
Leftmost
cell
Top cell
00 01 11 10
AB
C
0 1 1 1 1
1 1 0 0 1
RIGHT
00 01 11 10
C
0 1 1 1
1 1 0 0 1
WRONG X
AB
X
88
The Karnaugh map provides a simple and straight-forward method of
minimising boolean expressions. With the Karnaugh map Boolean expressions
having up to four and even six variables can be simplified. It provides a pictorial
method of grouping together expressions with common factors and therefore
eliminating unwanted variables. The Karnaugh map can also be described as a
special arrangement of a truth table. The diagram below illustrates the
correspondence between the Karnaugh map and the truth table for the general
case of a two variable problem
The values around the edge of the map can be thought of as coordinates. So as
an example, the square on the top right hand corner of the map in the above
diagram has coordinates A=1 and B=0. This square corresponds to the row in
the truth table where A=1 and B=0 and F=1. Note that the value in the F column
represents a particular function to which the Karnaugh map corresponds.
Examples
(i) 2-input Example
Direct from truth table: Y = A'B' + A'B + AB'
A B F
Truth Table
F
B
A
0 1
1
0 a b
c d
89
0 0 a
0 1 b
1 0 c
1 1 d

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

0

truth table
kmap
0
0
1
1
A
B
Y = B + A
(This is NAND)
1 1
1
(ii) 3-input Example
Direct from truth table: Y = A'BC' + A'BC + AB'C' + ABC' + ABC
(iii) 4-input Example

truth table
kmap

A

B

C

Y

0

0

0

0

0

0

1

0

0

1

0

1

0

1

1

1

1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

A
B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1

0

0

0

1

1

0

0

1

0

1

0

1

0

1

1

0

1

1

0

1

1

0

0

0

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

truth table
00
BC
A 01 11 10
0
1
Y = AC + B
kmap
Y = BD + DB+ABC
00 01 11 10
00
01
11
10
1 1
1
1
1
1 1
AB
CD
00 01 11 10
00
01
11
10
1 1
1
1
1
1 1
AB
CD
Y = BD + DB+ABC
OR
90
Worked Examples.
Example 1: Consider the following map. The function plotted is:
Z = f(A,B) = AB + AB
I. Note that values of the input variables form the rows and columns. That is the
logic values of the variables A and B (with one denoting true form and zero
denoting false form) form the head of the rows and columns respectively.
ii. Bear in mind that the above map is a one dimensional type which can be used
to simplify an expression in two variables.
iii. There is a two-dimensional map that can be used for up to four variables, and
a three-dimensional map for up to six variables.
Using algebraic simplification,
Z = AB' + AB
Z = A(B' + B)
Z = A
Referring to the map above, the two adjacent 1's are grouped together. Through
inspection it can be seen that variable B has its true and false form within the
group. This eliminates variable B leaving only variable A which only has its true
form. The minimized answer therefore is Z = A.
Example 2: Consider the expression Z = f(A,B) = A'B'+ A B'+ A'B
Pairs of 1's are grouped as shown above, and the simplified answer is obtained
by using the following steps: Note that two groups can be formed for the
example given above, bearing in mind that the largest rectangular clusters that
can be made consist of two 1s. Notice that a 1 can belong to more than one
group. The first group labeled I, consists of two 1s which correspond to A = 0, B =
0 and A = 1, B = 0. Put in another way, all squares in this example that
0 1
0
1
B
A
1
1
B
A
0 1
0
1
1 1
1
11
11
91
correspond to the area of the map where B = 0 contains 1s, independent of the
value of A. So when B = 0 the output is 1. The expression of the output will
contain the term B' For group labeled II corresponds to the area of the map
where A = 0. The group can therefore be defined as A'. This implies that when A =
0 the output is 1. The output is therefore 1 whenever B = 0 and A = 0
Hence the simplified answer is Z = A'+ B
Minimization of Boolean expressions using Karnaugh maps.
Given the following truth table for the majority function.
The Boolean algebraic expression is m = a'bc + ab'c + abc' + abc.
We have seen that the minimization is done as follows. m = a'bc + abc + ab'c +
abc + abc' + abc = (a' + a)bc + a(b' + b)c + ab(c' + c) = bc + ac + ab
The abc term was replicated and combined with the other terms. To use a
Karnaugh map we draw the following map which has a position (square)
corresponding to each of the 8 possible combinations of the 3 Boolean
variables. The upper left position corresponds to the 000 row of the truth table,
the lower right position corresponds to 110. Each square has two coordinates,
the vertical coordinate corresponds to the value of variable a and the horizontal
corresponds to the values of b and c.
abc m
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
00 01 11 10
bc
a
a
b
0
1
1
1 1 1
92
The 1s are in the same places as they were in the original truth table. The 1 in the
first row is at position 011 (a = 0, b = 1, c = 1). The vertical coordinate, variable a,
has the value 0. The horizontal coordinates, the variables b and c, have the
values 1 and 1. The minimization is done by drawing circles around sets of
adjacent 1s. Adjacency is horizontal, vertical, or both. The circles must always
n
contain 2 1s where n is an integer.
We have circled two 1s. The fact that the circle spans the two possible values of
a (0 and 1) means that the a term is eliminated from the Boolean expression
corresponding to this circle. The bracketing lines shown above correspond to
the positions on the map for which the given variable has the value 1. The
bracket delimits the set of squares for which the variable has the value 1. We
see that the two circled 1s are at the intersection of sets b and c, this means that
the Boolean expression for this set is bc.
Now we have drawn circles around all the 1s. The left bottom circle is the term
ac. Note that the circle spans the two possible values of b, thus eliminating the b
term. Another way to think of it is that the set of squares in the circle contains the
same squares as the set a intersected with the set c. The other circle (lower
right) corresponds to the term ab. Thus the expression reduces to bc + ac +
ab as we saw before. Notice that the 1 at position 111 was used by all 3 circles.
This 1 corresponds to the abc term that was replicated in the original algebraic
minimization. Adjacency of 2 1s means that the terms corresponding to those 1s
00 01 11 10
bc
a
a
b
0
1
1
1 1 1
bracketing line
c
00 01 11 10
bc
a
a
b
0
1
1
1 1 1
c
93
differ in one variable only. In one case that variable is negated and in the other it
is not. For example, in the first map above, the one with only 1 circle. The upper 1
is the term a'bc and the lower is abc. Obviously they combine to form
bc ( a'bc + abc = (a' + a)bc = bc ).
That is exactly what we got using the map. The map is easier than algebraic
minimization because we just have to recognize patterns of 1s in the map
instead of using the algebraic manipulations. Adjacency also applies to the
edges of the m.
Let's try another 3 variable map.
At first it may seem that we have two sets, one on the left of the map and the
other on the right. Actually there is only 1 set because the left and right are
adjacent as are the top and bottom. The expression for all 4 1s is c'. Notice that
the 4 1s span both values of a (0 and 1) and both values of b (0 and 1). Thus, only
the c value is left. The variable c is 0 for all the 1s, thus we have c'. The other way
to look at it is that the 1's overlap the horizontal b line and the short vertical a line,
but they all lay outside the horizontal c line, so they correspond to c'. (The
horizontal c line delimits the c set. The c' set consists of all squares outside the c
set. Since the circle includes all the squares in c', they are defined by c'. Again,
notice that both values of a and b are spanned, thus eliminating those terms.)
00 01 11 10
bc
a
a
b
0
1
1
c
1
1
1
94
Now for 4 Boolean variables. The Karnaugh map is drawn as shown below.
The following corresponds to the Boolean expression
q = a'bc'd + a'bcd + abc'd' + abc'd + abcd + abcd' + ab'cd + ab'cd'
RULE: Minimization is achieved by drawing the smallest possible number of
circles, each containing the largest possible number of 1s.
Grouping the 1s together results in the following.
00 01 11 10
bc
a
a
b
0
1
1
c
1
1
1
00 01 11 10
00
00
00
00
c
a
b
d
cd
ab
00 01 11 10
00
00
00
00
c
a
b
d
cd
ab
1 1
1 1 1 1
1 1
95
The expression for the groupings above is
q = bd + ac + ab
This expression requires 3 2-input and gates and 1 3-input or gate. We could
have accounted for all the 1s in the map as shown below, but that results in a
more complex expression requiring a more complex gate.
The expression for the above is bd + ac + abc'd'. This requires 2 2-input and
gates, a 4-input and gate, and a 3 input or gate. Thus, one of the and gates is
more complex (has two additional inputs) than required above. Two inverters
are also needed.
Don't Cares
Sometimes we do not care whether a 1 or 0 occurs for a certain set of inputs. It
may be that those inputs will never occur so it makes no difference what the
output is. For example, we might have a bcd (binary coded decimal) code which
00 01 11 10
00
00
00
00
c
a
b
d
cd
ab
1 1
1 1 1 1
1 1
bd
cd
abc d
96
consists of 4 bits to encode the digits 0 (0000) through 9 (1001). The remaining
codes (1010 through 1111) are not used. If we had a truth table for the prime
numbers 0 through 9, it would be ;
The d's in the above stand for "don't care", we don't care whether a 1 or 0 is the
value for that combination of inputs because (in this case) the inputs will never
occur.
The circle made entirely of 1s corresponds to the expression a'd and the
combined 1 and d circle (actually a combination of arcs) is b'c. Thus, if the
disallowed input 1011 did occur, the output would be 1 but if the disallowed input
1100 occurs, its output would be 0. The minimized expression is p = a'd + b'c
Notice that if we had ignored the ds and only made a circle around the 2 1's, the
resulting expression would have been more complex, a'b'c instead of b'c.
abcd
p
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
1
1
0
1
0
1
0
0
d
d
d
d
d
d
00 01 11 10
00
01
11
10
c
a
b
d
cd
ab
1
1
1
1
1
d d d d
d d
97
Questions.
3.
1. Using Boolean algebra simplify each of the following logic expressions as
much as possible:
(a) Z= A(A + AB) (A + ABC) (A + ABCD)
(b)C = (XX '+X 'X)'
F(xyz,)=2367
F(A,B,C,D)= (7,13,14,15)
How many possible (unique) boolean functions are there if the function has
(a) one input
(b) two inputs
three inputs d) four inputs
(e) ?ve inputs
4. Simplify the following boolean functions using algebraic transformations.
Show your work.
(a) F = AB + AB'
(b) F = ABC + BC' + AC + ABC'
F = A'B'C'D' + A'B'C'D + A'B'CD + A'B'CD'
(d) F = A'BC + ABC' + A'BC' + AB'C' + ABC + AB'C
5. Provide implementations of an AND gate, OR gate, and inverter gate using
one or more NOR gates.
6. What is the principle of duality? What does it do for us?
7. Build a single truth table that provides the outputs for the following three
boolean functions of three variables:
F = A + BC
x
F - AB + C'B
y
F = A'B'C' + ABC + C'B'A
z
2. Obtain the simplified expression in s-of-p for the following Boolean functions:
(a) ABD + A'C'D' + A'B + ACD + AB'D'
(b)
(c)
98
CHAPTER FIVE
INTEGRATED CIRCUIT LOGIC GATES
5.1 Digital Integrated Circuit (IC)
The logic gates and memory elements described in chapter three are a il ble
in IC form with the following advantages
* Small size
* Low power consumption
* Low cost
The act ve elements may be the bipolar junction transistors family which the TIL
is a handy example or the metal oxide semiconductor field effect transistors
family using either n - channel or p - channel devices in enhancement or
depletion modes. Integrated circuits contains many hundreds and even
thousands of gates in a single chip and this gives us the idea of the various
scales of integration for ICs.
va a
i
:
.
Digital logic and electronic circuits derive their
name and functionality from electronic switches called transistors. The
transistor can be likened to an electronically controlled valve whereby energy
applied to one connection of the valve enables energy to flow between two other
connections. By combining multiple transistors, digital logic building blocks
such as AND gates and flip-flops are formed. Transistors, in turn, are made from
semiconductors, they are called semiconductors because of their ability to
behave as both vented a means of fabricating multiple transistors on a single
slab of semiconductor material. Their invention would come to be known as the
integrated circuit or IC, which is the foundation of our modern computerized
world. An IC is so called because it integrates multiple transistors and diodes
onto the same small semiconductor chip. Instead of having to solder individual
wires between discrete components, an IC contains many small components
that are already wired together in the desired topology to form a circuit. A typical
IC, without its plastic or ceramic package, is a square or rectangular silicon die
measuring from 2 to 15 mm on an edge. Depending on the level of technology
used to manufacture the IC, there may be anywhere from a dozen to tens of
millions of individual transistors on this small chip. This amazing density of
electronic components indicates that the transistors and the wires that connect
them are extremely small in size. Dimensions on an IC are measured in units of
micrometers, with one micrometer (1 m) being one millionth of a meter. To
serve as a reference point, a human hair is roughly 100 m in diameter. Some
99
reduce these feature sizes to pack more transistors into the same silicon area.
Many individual chemical process steps are involved in fabricating an IC. The
process begins with a thin, clean, polished semiconductor wafer most often
silicon that is usually one of three standard diameters: 100, 200, or 300 mm.
The circular wafer is cut from a cylindrical ingot of solid silicon that has a perfect
crystal structure. This perfect crystal base structure is necessary to promote
the formation of other crystals that will be deposited by subsequent processing
steps. Many dice are arranged on the wafer in a grid, each die is an identical
copy of a master pattern and will eventually be sliced from the wafer and
packaged as an IC. An IC designer determines how different portions of the
silicon wafer should be modified to create transistors, diodes, resistors,
capacitors, and wires.
5.1.1 Packaging
There are many variations of the packaging technologies, most packages
comply with industry standard dimensions, but others are proprietary.
Semiconductor manufacturers provide detailed drawings of their packages to
enable the proper design of circuit boards for their products.
When the wafer has completed its final process step, it is tested and then sliced
up to separate the individual dice. Dice that fail the initial testing are quickly
discarded. Those that pass inspection are readied for packaging. A package is
necessary for several reasons, including protection of the die and the creation of
electro mechanical connections with other circuitry. ICs are almost always
mounted onto a circuit board, and it is usually difficult to mount unpackaged ICs
directly to the board. Plastic and ceramic are the two most common materials
used in an IC package. They surround the die and its lead frame. The lead frame
is a structure of metal wires that fan out from the die and extend to the package
exterior as pins for connection to a circuit board. Plastic packages are generally
lower in cost as compared to ceramics, but they have poorer thermal
performance. Thermal characteristics are important for ICs that handle large
currents and dissipate large quantities of heat. To prevent the IC from
overheating, the heat must be conducted and radiated away as ef?ciently as
possible. Ceramic material conducts heat far better than plastic. A very
common package is the dual in-line package, or DIP, shown in Fig. 2.5. A DIP
has two parallel rows of pins that are spaced on 0.1-in centers. Each pin extends
roughly 0.2 in below the bottom of the plastic or ceramic body. Pins are
numbered sequentially from 1 going left to right along one side and resuming on
the opposite side from right to left. There is usually at least one pin 1 marker at
one end of the package. It is either a dot near pin 1 or a semicircular DIPs are
100
commonly manufactured in standard sizes ranging from 6 to 48 pins, and some
manufacturers go beyond 48 pins. Smaller pin-count devices have 0.3-in wide
packages, and larger devices are 0.6 in wide. Because of the ubiquity of the DIP,
there are many variations of pin counts and package widths. For many years,
the DIP accounted for the vast majority of digital logic packages. Common logic
ICs were manufactured in 14- and 16-pin DIPs. Memory ICs were manufactured
in 16-, 18-, 24-, and 28-pin DIPs. Microprocessors were available in 40-, 44-,
and 48-pin DIPs. DIPs are still widely available today, but their use as a
End view
Side view
Figure 2.6 DIP Lead Frame
FIGURE 2.5 A 16-pin dual in-line package.
die
Top view 16 9
8
pin 1
101
percentage of the total IC market has declined markedly. However, the bene?ts
of the DIP remain: they are inexpensive and easy to work with by hand,
eliminating the need for costly assembly tools. If you were to carefully crack
open a DIP, you would be able to see the mechanical assembly of the die and
lead frame. This is illustrated in Fig. 2.6. The die is cemented in the center of a
stamped metal frame and is connected to the individual pins with extremely
thin wires. Once the electrical connections are made, the fragile assembly is
encased in a plastic or ceramic body for protection and the exterior portions of
the pins are folded vertically. All other IC packages are variations on this theme.
Some packages use a similar lead-frame structure, whereas more advanced
packages utilize very high-quality miniature circuit boards made from either
ceramic or fiberglass. An oft-quoted attribute of ICs is that their density doubles
every 18 months as a result of improvements in process technology. This
prediction was made in 1965 by Dr. Gordon Moore, a co-founder of Intel. It has
since come to be known as Moores law, because the semiconductor industry
has matched this prediction over time. Before to the explosion of IC density, the
semiconductor industry classified ICs into several categories depending on the
number of logic gates on the device: smallscale integration (SSI), medium-scale
integration (MSI), large-scale integration (LSI), and, finally, very large-scale
integration (VLSI). Figure 2.7 provides a rough definition of these terms. As the
density of ICs continued to grow at a rapid pace, it became rather ridiculous to
keep adding words like very and extra to these categories, and the terms
widespread use declined. ICs are now often categorized based on their
minimum feature size and metal process. For example, one might refer to an IC
as 0.25 m, three-layer metal (aluminum) or 0.13 m, six-layer copper. As IC
densities grew at this tremendous pace, the number of pins on each IC and the
speed at which they operated began to increase as well. DIPs soon become a
limiting factor in the performance of ICs. First, the addition of more pins made the
package longer, because there are only two rows of pins. However, most chips
are relatively square in shape to minimize on-chip interconnection distances.
This creates a conflict: a long, narrow package that is unsuitable for increasing
square die sizes. Second, the lengths of some pins in the DIP lead frame,
especially those near the corners, are relatively long. This has an adverse
impact on the quality of high-speed signals. Third, the 0.1-in pin spacing on DIPs
keeps them artificially large as circuit board technologies continue improving to
handle smaller contacts. One solution to the pin density problem was the
development of the pin grid array , or PGA, package. Shown in Fig. 2.8, the PGA
is akin to a two-dimensional DIP with pins spaced on 0.1-in centers. Very high
pin counts are achievable with a PGA, because all of its area is usable rather
102
than just the perimeter. Being a square, the PGA is compatible with large ICs,
because it more closely matches the proportions of a silicon chip. The PGA
provides high pin density, but its but its drawback is relatively high cost. Two
lower-cost packages were developed for ICs that require more pins than DIPs
but fewer pins than found on a PGA: the small outline integrated circuit (SOIC)
and the plastic leaded chip carrier (PLCC). Examples of SOIC and PLCC
packages are shown in Fig. 2.9. Both SOICs and PLCCs feature pins on a 0.05-
in pitch half that of a DIP or PGA. The SOIC is basically a shrunken DIP with
shorter pins that are folded parallel to the plane of the package instead of
protruding down vertically. This enables the SOIC to be surface mounted onto
the circuit board by soldering the pins directly to metal pads on the board. By
contrast, a DIP requires that holes be drilled in the board for the pins to be
soldered into. The SOIC represents an improvement in packaging density and
ease of manufacture over DIPs, but it is still limited to relatively simple ICs due to
its one-dimensional pin arrangement.
FIGURE 2.8 Pin grid array package.
FIGURE 2.9 SOIC and PLCC.
top view top view
pin 1
44 - pin PLCC
pin 1
FIGURE 2.9 SOIC and LCC.
103
Digital circuits are constructed with integrated circuits (ICs). An IC is a small
semiconductor crystal, called a chip, containing the electronic components for
the digital gates. The various gates are interconnected inside the chip to the
required digital function. The chip itself is mounted in a ceramic or plastic
container, and connections are welded to external pins to form the IC. The
number of pins may range from 14 in a small IC package (e.g. 4 dual input NAND
gates) to 132 or more (e.g. complex microprocessors).
5.1.2 Levels (scales) of Integration.
As the technology of ICs has improved, the number of gates that can be put in a
single silicon chip has increased considerably. The differentiation between the
number of gates per chip is shown below.
Small scale integration (SSI) contain several independent gates in a single
package. The inputs and outputs of the gates are connected directly to the pins
in the package. The number of gates is limited by the number of external pins on
the IC.
Medium scale integration (MSI) devices have a complexity of approximately
10 to 100 gates per package. They usually perform specific elementary digital
functions, serving as decoders, multiplexers, adders, flip-flops, and registers.
Large scale integration (LSI) devices contain between 100 and a few
thousand gates per package. They include memory chips, programmable
modules, and processors.
Very large scale integration (VLSI) devices contain thousands of gates per
package. Examples are complex microprocessors, large memory arrays, and
sophisticated controllers. Because of their small size and low cost, VLSI devices
have had a tremendous impact on digital system design, giving the designer the
capabilities to create systems that were previously not economical.
5.2 Digital Logic Families
Digital ICs are classified not only by their logical operation but also by the
specific circuit technology to which they belong. The circuit technology is
referred to as a digital logic family. Each logic family has its own basic electronic
circuit upon which more complex digital circuits and functions are developed.
The basic circuit in each technology is a NAND, a NOR, or an inverter gate. The
electronic components used in the construction of the basic circuit are usually
used as the name of the technology. The most widely known digital logic families
are: TTL- Transistor-transistor logic, ECL- Emitter-coupled logic, MOS- Metal-
Oxide semiconductor and CMOS- Complementary metal-oxide semiconductor
105
The characteristics of logic families are usually compared by analyzing the
circuit of the basic gate (e.g. the NAND gate) in each family. The most important
parameters that are evaluated and compared are defined as follows.
Fan-out (loading factor) specifies the number of standard loads that the output
of a typical gate can drive without impairing its normal operation. A standard load
is usually defined as the amount of current needed by an input of another similar
gate of the same family.
Power-dissipation is the power consumed by the gate.
Propagation delay is the average transition delay time for the signal to
propagate from input to output when the input signal changes in value.
. The operating speed in inversely proportional to the
propagation delay.
Noise margin is the
minimum external noise voltage that causes an undesirable change in the
circuit operation. It can also be defined as
.
Operating power supply (supply voltage) is the recommended voltage for a
particular device in which if exceeded can damage the component.
Fan- In is the number of input that logic can handle, for instance an eight input
gate that required one unit load for input means it has a fan-in of 8
it is the
accumulation of all of the rise times, delay times and storage times associated
with any logic circuit
is also called the safety margin or noise immunity and
the unwanted voltage signals picked
up by various wire connected to the circuit This can be described as the amount
of noise a logic system can handle without being amplified beyond necessary.
Noise can cause the logic circuit to switch to an undesirable state at an im proper
time.
The characteristics of logic families is shown in the table 5.1
.
105
5.3 IC Fundamentals
This section provides a brief introduction to the basic electronic circuit
components used to construct digital ICs.

Logic Family Characteristics
Transistor Transistor Logic (TTL) Supply voltage = 5 + 10%
Propagation Delay = 10ns
Power Dissipation = 10mW
Fan Out = 10
Noise Immunity High = 1.0v
Diode Transistor Logic (DTL) Supply voltage = 4.7v
Propagation Delay 30ns
Power Dissipation = between 9mW to
12mW
Fan out = 5
Noise Margin = 0.3v
Resistor Transistor Logic(
R,TL)

Supply voltage = 3.6v
Propagation Delay =
25ns Power
Dissipation = 12mW
Fan-Out =5
Noise Margin = 0.3V

Direct coupled Transistor Logic
(DCTL)

The configurations look like
that of RT L, except that the
base resistors area omitted.

CMOS Logic

Supply voltage +3v to 18v
Power dissipation = 0.0005 to
1mW
Fan out = 50 or more.
Propagation delay = 65ns
Table 5.1.Logic family characteristics.
106
Diode Characteristics
The semiconductor diode can be thought of as analogous to a simple switch. In
the forward direction, the ideal diode is 0 ohms of resistance, acting as a short
circuit (i.e. conducting). In the reverse direction, the ideal diode has infinite
resistance, acting as a open circuit (i.e. not conducting). These relationships are
diagramed below. Figure 5.1 shows the characteristics of a diode.
Figure 5.1 Diode characteristics
The diode isnt an ideal device which causes some problems. Firstly, when it is
conducting, there is a voltage drop across it due to a small forward resistance.
Silicon diodes operating at 5 volts have a 0.7V drop across them. This means
the voltage on the other side of the diode is only 4.3V.
Figure 5.2. 2 input diode logic with voltage level.
In positive true logic, a logic 1 is defined as + 5V and a logic 0 is 0V. Since there is
a voltage drop across the diode, the manufacturers define the logic levels within
a range instead of an exact voltage. When using diode gates, even with a range
of voltages defining the logic levels, we can have enough degeneration of the
signals to cause the problem illustrated below. Ultimately a logic 1 would
become a logic 0.
V
1
V
2
i
Diode Symbol
V
1
V
2
i
When V <V it acts like
1 2
a short circuit (conducting)
V
1
V
2
an open circuit (non-conducting)
A
B
5.0 V
0 V
4.3 V
C
107
Figure 5.3. Four input logic with voltage levels
Thus, after every two levels of gates, amplifiers are used to boost the voltage
levels back up. A second problem with diode use is a relatively large
propagation delay due to the capacitance inherent in diodes. Capacitors do not
allow voltage levels to change instantly. A third problem is that diode gates have
limited fan-out even after amplification.
8.3.2 Transistor Characteristics
Transistors overcome the problem of diode voltage degeneration by their
inherent amplification of input signals. They also make an excellent switch since
the transition from cutoff (i.e. not conducting) to saturation (i.e. conducting) is
faster than the response of the diode. Thus they make a faster gate than the
diode. Transistor gates also have a much higher fan-out when cascaded in a
circuit design. The first commercial ICs were made with RTL technology
(resistor transistor logic). This technology was then replaced by DTL ICs; (diode
transistor technology). A DTL circuit that implements a NAND gate is presented
below because it is a starting point to discuss the operation of the TTL gate.
B
A
C
D
0 v
0 v
+5 v
+5 v
+4.3 v +3.6 v +2.9 v
E
(a) Schematic
A
B
C
D
0
0
1
1
1
1
1
E
(a) Logic Diagram
108
Figure 5.4 Transistor Characteristics.
An analysis of its operation is straightforward. If any input to the gate is low, the
diode will conduct, preventing any base current from being provided to the
transistor Q1. This puts Q1 into cutoff and puts the output voltage (Y) to + 5V, or
logic 1. If all inputs are high, the transistor is driven into saturation (i.e.
conducts), which drops the output to a low voltage level, or logic 0.
+V
I
C R
C
I
B
V
0
R
B
V
i
I
E
When V = 0, V = V
i 0
When V = V, V = V
i 0
Cutoff (open circuit)
Saturation (closed circuit)
Transistor Diagram
Figure 5.5 DTL Implementation of a NAND gate
A
B
C
D
1
D
2
5 KW
5 KW
2 KW
Q
1
V = 5 V
CC
Y = ABC
109
8.3.3 TTL Logic
The TTL version of the basic NAND gate is shown below. The circuit operates as
follows. If both A and B are high, Q1 has no emitter current; however its base-
collector junction is forward biased, supplying base current to Q2, turning it on.
This, in turn, feeds base current to Q4, causing it to conduct. However, the Q2
collector will go low, cutting off Q3, Therefore, we have Q4 conducting and Q3
cut off. This will cause the output C to be low. If either A or B goes low, Q1 will
have base-emitter current, saturating it and pulling Q2 base to ground, cutting it
off. This will cause Q3 to conduct and Q4 to cut off resulting in C being high. The
original TTL gate was a slight improvement over the DTL gate. As TTL
technology progressed, additional improvements were added to the point
where this logic family became the most widely used type in digital systems.
There are many versions of the TTL basic gate. The names and characteristics
of these different versions appear in the table below. In addition to these, there is
advanced Schottky (AS), advanced low-power Schottky (ALS), and Fast (F)
versions, which are improvements over the ones in the table. Each
V = 5V
cc
4 K
1.6 K W
130 W
A
B
b
c
e
Q
1
Q
2
Q
3
Q
4
C
1K W
Totem-pole output
(Q3 site on Q )
4
This circuit acts like a two
input AND gate.
The rest of the circuit acts like
and inverter, based upon the input
current to Q2.
Figure 5.6. Transistor Transistor Logic (TTL) NAND Gate
110
improvement results in faster propagation delays, or lower power consumption,
or both. Although the naming specifications for TTL parts varies, based upon
manufacturer codes for temperature ranges, package types, etc., the basic
naming convention is as follows: nnMMxx where nn is a series number (54 for
military temperature ranges, 74 for commercial temperature range), MM is a
mnemonic representing the version number as described above (e.g. LS), and
xx is the functional number of the part (e.g. 00 for 4 dual input NAND gates).
Thus, a 54LS138 and a 74AS138 are functionally the same part (a 3-to-8
decoder). The first is a mil-spec part implemented with low-power Schottky
technology, whereas the latter is a commercial-spec part implemented with
advanced Schottky technology.
A common type of TTL output is known as an open collector output. The circuit
shown in figure 5.7 below is a two-input NAND gate with an open collector
output in which the output is taken from the open collector of Q3. Because the
collector of Q3 is open, the gate will not work properly without an external pull-up
resistor. If any input is low, the corresponding base-emitter junction in Q1 is
forward biased, cutting off Q2 and Q3, leaving the output Y at logic high. If both
Name

Abbreviation

Mnemonic

Propagation

Delay

Power
dissipation
(mW)

Standard
TTL

TTL

NONE

10

10

Low-power
TTL

LTTL

L

33

1

High-speed
TTL

HTTL

S

6

22

Schottky TTL

STTL

H

3

19
Low-power
Schottky TTL

LSTTL

LS

9.5

2

111
inputs are high the base-collector junction of Q1 is forward biased, allowing
both Q2 and Q3 to conduct and saturate. This pulls the output Y to logic low. The
outputs of open-collector gates can be wired together and connected to a
common pull-up resistor. This is known as a wired-AND configuration (also
called wired-OR) shown in figure 5.8. Remember that the AND function gives a
high level only if all the variables are high. With the outputs of open-collector
gates connected together, the common output is high only when all the output
transistors are off (or high). If any output transistor conducts, it forces the output
to a low state.
Figure 5.8, Wired AND Connection and graphic Symbols
Figure 5.7. TTL NAND gate with Open Collector Output
V = 5V
CC
4 KW1.6 KW
Q
1
A
B
Q
2
Q
3
1 KW
V = 6V
CC
R
L
Y
External pull-up resistor
supplied by the designer
V
CC
A
B
C
D
oc
oc
Y
A
B
C
D
oc
oc
Y
(a) Wired-AND physical connection
(b) Wired-AND logic graphic symbol
112
The AND gate in the graphical symbol is not a physical AND gate but only a
symbol to designate the function obtained from the indicated connection. The
Boolean function obtained from the circuit is the AND operation between the
output of the two NAND gates: Y = (AB) (CD) = (AB + CD)
The second expression is preferred since it shows an operation commonly
referred to as an AND-OR-INVERT function (hence the reference to wired-OR).
It should be noted that although the above diagram shows only two open-
collector gates connected together, many can be connected together (e.g. 16)
creating a large AND function. The outputs of gates with totem-pole outputs
cannot be connected together as in open-collector outputs. When two totem-
poles are wired together with the output of one gate high and the output of the
second gate low, the excessive amount of current drawn can produce enough
heat to damage the transistors in the circuit. There is, however, a special type of
totem-pole output that allows the wired connection of outputs for the purpose of
forming a common-bus system. When a totem-pole output has this property, it is
called a three-state (or tri-state) device. A tri-state device exhibits three output
states: (1) logic low, (2) logic high, and (3) high impedance (Hi-Z) state. This third
state allows a direct wire connection of many outputs to a common line shown in
figure 5.9.
Figure 5.9. Tri state gates.
All tri-state devices have a control input, designated C above, that enables or
disables the device. If the device is enabled, its output takes on either a logic low
or logic high. If the device is disabled, the output is an open circuit, which gives a
high impedance (i.e. infinite resistance), regardless of the value of the input(s).
Wiring several tri-state devices together creates a tri-state bus. At any given
time, only one control input is enabled while all the other devices are disabled.
The single device not in Hi-Z state can transmit binary information on the
common bus. All the other devices are, in effect, disconnected from the bus.
If C=0 then Y=A
If C=0 then Y is Hi-Z
Y
A
C
If C=0 then Y=A
If C=1 then Y is Hi-Z
(a) Tri-state buffer gate (B) Tri-state inverter gate
113
Common bus configurations are commonly used in microprocessor based
designs where a common data bus connects many memory and peripheral
devices.
5.7 PIN CONNECTION AND IC IDENTIFICATION
Two main families of digital logic have emerged as the most popular with
designers of general purpose digital circuit in recent ties. These are the TTL and
the Cmos families, the farmer the TIL family was introduced in 1964 by
Texas'lnstrument Limited, while the Cmos - complimentary metal oxide semi
conductor fanlily, Cmos (pronounced as see - mos) was introduced in 1968.
The TTL family is designated the 74 series while the Cmos is designated the
4000 series and are both housed in the 14 pin DIL package. See figure 5.10.
(a) 74 logic family (b) 4011B CMOS logic family.
Figure 5.10 Logic Family.
Figure 4.2a is the 7400 IC contains a quad 2input NAND gate meaning it
contains four NAND gates each with two: ;lputS and one output. Figure 4.2b is a
4011B, a quad 2 - input NAND gate. Through they look similar but the pin
connections is different aild therefore the TTL can not replace the Cmos
package. As mentioned earlier on, for each of the family there is a unique
number for its identification. The TTL family begins with the 74 and followed by
two other numbers. The final two numbers indicate the type of logic gate for
example 7432 implies quad 2 - input OR gate, 7411 implies a tripple 3 - input
AND gate. See appendix B. This explanation holds for the Cmos family and the
last two numbers the logic family, for ~xample 4011. Quad 2 - input NOR gate
and 4001 implies quad 2 input NAND gate. Manufacturers of IC's provide pin
diagram which helps us in the use of IC's. The power connections to IC are the
AND (pin 1) and V cc (Pin 14) pins. All other pins are the input and out puts to the
gates that makers up the IC as shown in figure 4.2. The top of a typical TTL form
14 13 12 11 10 9 8
1 2 3 4 5 6 7
V
CC 14 13 12 11 10 9 8
1 2 3 4 5 6 7
V
DD
V
55
114
and Cmos digital Ic's carry an identification number. The prefix "DM" is a
manufacturers code representing National Semiconductor, whereas "SN" on
the IC stands for the manufacturer, Texas Instrument. As an example if we
consider the following IC's (i) DM 7408N (ii) SN 74LS08J (iii) CD 4081 BE can be
describes as follows:
(i) DM - manufacturers code
7408 - represent c are part number where 74 represents TTL I C family and
08 represents the function of the i.e. in this case two - input AND gate. The
core part number is same for all manufacturers. Suffix "N" - manufacturers
code for dual - in -line package.
(ii) SN - represents the manufacturers code.
74 LS08J - represents the core part number with the following description 74
tells us it is 7400 TTL series, LS Tells us it is the low power schotky type and
the 08 gives the function of the digital IC and suffix J stands for ceramic DIP
packaging. This typically is referred to as the commercial grade.
(iii) CD - represents the manufacturers code for Cmos digital IC's.
4081 BE - represents the core part number, where 40 tells us it of the 4000
Cmos series, 81 Gives the function of the IC (quadruple two - input AND
gate). The letter B represent the buffered version of the original 4000A
series, which provides the 4000B with greater output drive and some static
electricity protection. Suffix E stands for the manufacturers code for
plastic dual- in line package.
Typical internal letters are descri bed in the table 4.2. Below
115
AC - FACTS Fairchild Advanced Cmos famiily. This is a
Newer advanced Cmos family.
ACT - FACTS Fairchild Advance Cmos Technology logic.
This is a newer advanced Cmos family with
TTL Logic levels .
ALS - Advanced low-power sc hottky TTL logic
S - Advance Schottky TTL logic
C - Cmos logic, this is an early form of Cmos.
.
F - FAST Fairchild Advanced Schottky TTL logic
The new subfamily of TTL
FCT - FACT Fairchild Advanced Schottky TTL lOgIC.
Th a new family of Cmos with TTL logic levels
H - High speed TTL logic
HC - High speed Cmos logic
HCT - High speed Cmos logic. This is a fan1ily of
Cmos with TTL inputs
L - Low - power schottky TTL logic.
S - Schottky TTL logic
From the table ALS, AS H L, LS and S are all classified under the subfamily of
TTL Data manuals from respective manufacturers contain pin diagrams,
packaging information, details on part numbering and other valuable data for
those in practice and students.
is .
.

, , ,
116
Internal
Letter
Description
The most common manufacturers and their designation are given in the table
below.
Table 5.3. Manufacturers Designation
Designation Manufacturer
Mc Motorola
LM National
SN Texas Instrument
IM Signetics.
MM Monolithic Memories
P Intel
H Hades
F Fairchild
AM Advanced Micro devices.
117
5.8. Merits and Demerits Of Logic Families.
(a) TTL Gates :
Merits:
1. It is the fastest saturating logic family. TTL gates are available in the form of
high-speed Schottky, low-power, low-power Schottky and a variety of other
types.
2. Typical supply voltage is 5V with a permitted variation of 0.25V. Recent
advances show a trend towards the 3 volts and even to 1.5V supply
3. It has good noise immunity. Typical noise-margin is about 0.4 V.
4. power dissipation is in the megawatt range. With low-power Schottky, this is
reduced to 2m W / gate.
5. It is compatible with other logic families.
6. Commercial and military versions of TTL gates are available.
7. Freely available in the open market. It is more easily available than most
other logic families.
8. Good fan-out; can drive up to 10 gates.
9. Almost all functions are available in TTL family of gates.
10. Low output impedance for high/low states.
Drawbacks

1.Noise immunity is not very- high, hence it cannot be used in areas where large
noise voltage prevail.
2.Because of isolation problems, VLSI circuits are not possible.
3.Power dissipation is much higher than MOS gates.
4.Cost is higher than the CMOS when MSI and LSI gate are considered.
5.It generates transient voltages at switching instants.
Wired-OR capabilities is not possible for the standard TTL.
(b) ECL Gates
Merits
1. Since transistors operate in the active region, this family has the higher speed
among all logic families.
2. Complementary output (OR-NOR) are available.
3. Current switching spikes are not present in power supply leads. Outputs can
be tied together to give the wired-OR function.
4. Parameters do not vary much with temperature.
118
5. The number of functions available is high.
6. Typical supply voltage is -5 .2V.
Drawbacks
1. Very low noise-margin ( 200m V).
2. Highest power dissipation among all logic gates.
3. Level shifters are required for interfacing with other logic families.
4. Capacitive loading limits fan-out. Higher cost.
5. VLSI is design difficult as ECL gate require resistors also to be fabricated.
2
(c) I L Gates
Merits
2
1. Since I L gates are made up of bipolar junction transistors, they have high
speed of operation.
2
2. Because only transistors are used for construction. I L gates have high
packing density and are hence suitable for the construction of VLSI circuits.
3. Very low power supply required.
4. Lw power dissipation.
5. Process steps required are less. Hence cost per gate is low.
6. Several functions are possible on the same chip.
2
7. U sing standard bipolar technology, it is possible to combine I L logic with
other logic families.
Drawbacks
1. Very low voltage swing.
2. Lower jacking density than CMOS.
3. Low noise margin.
4. External resistance required for proper functioning.
2
5. I L technology is dormant are present.
(d) CMOS Gates
Merits
1. Extremely large fan-out capability (> 50).
2. Lower power dissipation of all gates (a few nano watts).
3. Very high noise-immunity and noise-margin.
4. Low propagation delay.
5. High speed.
119
6. Large logic swing.
7. Single power supply required.
8. Directly compatible with TTL gates.
9. Temperature stability is excellent.
Drawbacks
1. Increased cost due to additional processing steps.
2. Low packing density
3. MOS chip must be protected from acquiring static charges by keeping the
leads shorted. Static charges acquired in leads will destroy the chip.
5.9. Comparison of various performance characteristics of important
logic families.
Table 5.4 Comparison of various performance characteristics of important logic
families.
120
Logic family

Supply voltage

Typical

Worst-case

Speed power

Maximum

(V)

propagation

noise

product (pI)

Flip-flop

delay (ns)

margin (V)

toggle

frequency

(MHz)
TTL

Standard

17

0.4

100

35

L

60

0.3

33

3

H

10

0.4

132

50

S

5

0.3

57

125

LS

15

0.3

18

45

ALS

10

0.3

4.8

70

AS

4.5

0.3

13.6

200

F

6

0.3

10

125

CMOS

4000

150

1.0

5

12

74C

50

1.4

5

12

74HC

8

0.9

1.4

40

74HCf

8

1.4

1.4

40

74AC

4.7

0.7

0.37

100

74ACT 4.7 0.72.9 0.37 100

ECL

MECLill

1

0.2

60

500

MECL 10K 2.5

0.2

50

200

MECL IOH I

0.15

25

250

ECUNPS 0.5

0.15

10

1000

ECUNPS 0.2 0.15 10 2800

LITE

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5.5

4.5 to 5
.
5

3 to 15
3to13

2to-6

4.5 to 5.5

2 to 6

45 to 5.5
.

-5.1 to -5.3

-4.68 to -5.72

-4.94 to -5.46

-4.2 to -5.5

-4.2 to -5.5

Pin configuration diagrams for some common fixed-function IC gate
configurations.
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

0
8
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

2
1
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

8
6
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

0
4
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

2
0
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

3
2
V
C
C
V
C
C
1
4

1
4

1
3
1
3
1
2
1
2
1
1
1
1
1
0
1
0
9
9
8
8
1
1
2
2
3
3
4
4
5
5
6
6
7

7

G
N
D

G
N
D

1
1
1
0
0
2
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

3
0
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

0
0
V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

2
7

V
C
C
1
4

1
3
1
2
1
1
1
0
9
8
1
2
3
4
5
6
7

G
N
D

121
5.11. TTL Family Variations
There are several subfamilies of TTL leased on two basic circuit configuration
One involves the power levels, and the other involves the use of schottky
devices
The Standard and Low - Power TTL
TTL is made according to specifications that are uniform an10ng
manufacturers, one of such specification is the standard TTL and the other is
the low - power TTL They have the same voltage levels representing the two
logic values, which for outputs are a maximum of 0Av for logic level zero and a
minimum of 2v for logic level one They both have the same supply voltage
requirement of +5v, however, they differ in their input current output current
capability, power and power dissipation. Appreciable current flows only at the
low - voltage level (logic zero) for either type At logic zero, the input lines of the
standard TTL require nominally 1 6mA of current and the output lines are
capable of producing 16mA The fan out of standard TTL is therefore 10 For
low - power TIL, the logic zero input current requirement is 0 36mA, and the
output current capability is 8mA The fan out is approximately 22. The most
outstanding characteristic in this comparison is the lower input current
requirement of the low power compared to the standard TTL (less than one -
fourth). This makes the connection of TTL components to microprocessors
which usually have a low current capability in their output lines. Another
difference is the power dissipated by each gate. The power dissipation for low -
power TIL is about one - tenth of that for standard TTL The low power TTL has
the disadvantage of being
.
.
.
.
.
. .
.
.
.
.
slower than the standard TTL i.e about one tenth the
speed. This is basically due to the fact that the lower operating currents of low-
Power TTL result in a longer time needed to charge or discharge various
capacitors in the circuit for agate.
Schottky TTL
This variation of TTL makes use of schottky diodes. Schottky diode is formed
from a junction between a metal and n type semiconductor material shown in
figure The majority charge carriers both metal and semiconductor are
electrons. Electrons in the semiconductor occupy higher energy states than
those in the metal, hence, they diffuse across the junction and occupy energy
states in the metal by dissipating some of their energy The electrons from the
metal are inhibited from crossing the junction because of the higher energy
states in the semiconductor. The electron diffusion described above results in
the development of a potential across the junction that retards this diffusion
This initial potential can be counteracted by applying an external voltage to the
5.11 in
.
.
122
diode that makes the metal positive with respect to the semiconductor The
current flows as a result of the increase in the opposition and this is very little.
The schottky diode therefore exhibits rectifying carriers in both regions.
Apart from the improved switching speed, schottky diodes demonstrate a lower
forward voltage drop than the pn junction odes (about 0 2 to 0 30) which leads
to ts use with BIT to nhance their switching speeds If a schottky is connected
across the ase collector junction of a transistor oriented with the same polarity
s shown in figure 5.12, it will prevent the forward bias of the Juncti n from
reaching 0 7V hence the transistor will be kept from going deeply into
saturation
As a result the on-to-off switching of the transistor will be alleviated This
configuration is called schottky transIstor and the symbol is shown in figure
. Schottky TTL is available in both standard and low - power form
.
di .
i 's e .
b
a o
. , ,
.
.
5.12b
.
.
metal n type
(b) diode symbol
Figure 5.11 Schottky Diode
(a) Schottky Diode realized from the junction
between a metal and semiconductor.
B
C
(a) transistor with schottky
(b) circuit symbol
Figure 5.12 NPN Schottky
Anode Cathode
123
They show an Improvement in witching speed of about three to four times over
their non - schottky orms Hence the switching speed of low - power schottky
TTL is herefore, about the same as that of standard non - schottky TTL
5.12. Interfacing
s
f
t
.
.
.
.
Figure 5-13(af ) shows six examples of CMOS Ics
driving LED indicators. Figures 5-13(a) and (b) show the CMOS supply voltage
at 5 V. At this low voltage, no limiting resistors are needed in series with the
LEDs. In Fig. 5-13(a), when the output of the CMOS inverter goes HIGH, the
LED output indicator lights. The opposite is true in Fig. 5-13(b): when the CMOS
output goes LOW, the LED indicator lights. Figures 5-13(c) and (d) show the
4000 series CMOS ICs being operated on a higher supply voltage (10 to 15 V).
Because of the higher voltage, a 1kWlimiting resistor is placed in series with the
LED output indicator lights. When the output of the CMOS inverter in Fig. 5-13
goes HIGH, the LED output indicator lights. In Fig. 5-13(d), however, the LED
indicator is activated by a LOW at the CMOS output. Figures 5-13(e) and ( f )
show CMOS buffers being used to drive LED indicators. The circuits may
This is the process of connecting two components or system that are not
naturally compatible to function together, their current or voltage profile not with
standing. In this regard we have simple switch interface and debounce circuits,
using TTL with LED S, TTL - to - Cmos and Cmos - to TTL, TTL and Cmos
interface with buzzers, relays, motors and solenoids, etc. A fundamental
knowledge of simple interfacing methods is required when working with digital
circuits Most logic circuits are of no use if they are not interfaced with the "real
world" de ices We will consider interfacing TTL and Cmos LED sand TTL with
Cmos ICs.
Interfacing TTL and Cmos with LED's.
Most of our laboratory experiments using digital I C's require an output The light
emitting diode (LED) is fit for this job because it operates at low current and
voltages The maximum current for most LED's is about 20 to 30mA with 2V
applied. The LED will light dimly with a voltage of 1.78 to 1 8v and2mA
Interfacing 4000 series Cmos with Simple LED is very easy Figure 5.13
explains this interfaces
.
v .
'
.
.
.
.
124
Figure 5.13. Simple CMOS- and TTL-to-LED interfacing. (a) CMOS active
HIGH. (b) CMOS active-LOW. (c) CMOS active HIGH, supply voltage 10 to 15
V. (d) CMOS active LOW, supply voltage 10 to 15 V. (e) CMOS inverting buffer
to LED interfacing. (f ) CMOS noninverting buffer to LED interfacing. (g) TTL
active-HIGH. (h) TTL active-LOW.
+5V
OUTPUT
Light = HIGH
CMOS
V
DD
V
SS
(a)
CMOS
CMOS
INPUT
Light = LOW
OUTPUT
V
DD
V
SS
(b)
OUTPUT
Light = HIGH
V
DD
V
SS
CMOS
+10 to +15V
1 KW
(c)
CMOS
INPUT
CMOS
V
DD
V
SS
OUTPUT
Light = LOW
+10V to+15V
1 KW
(d)
OUTPUT
Light = HIGH
1 KW
CMOS
buffer
V
DD
V
SS
+5 to+15V
(e)
CMOS
INPUT
CMOS
buffer
Light = LOW
OUTPUT
1 KW
+5 to +15V
4049
4050
OUTPUT
Light = HIGH
LED
7404
Standard
TTL
150 W
(g)
A
K
INPUT
OUTPUT
LED
Light = LOW
A
K 7404
Standard
TTL
15V
150 W
(f )
(h)
125
operate on voltages from 5 to 15 V. Figure 5-13(e) shows the use of an inverting
CMOS buffer (like the 4049 IC), while Fig. 5-13( f ) uses the non-inverting buffer
(like the 4050 IC). In both cases, a 1kWlimiting resistor must be used in series
with the LED output indicator.
TTL-To-LED Interfacing
Standard TTL gates are sometimes used to drive LEDs directly. Two examples
are illustrated in Figs. 5.13(g) and (h). When the output of the inverter in Fig.
5.13(g) goes HIGH, current will flow through the LED causing it to light. The
indicator light in Fig. 5.13(h) only lights when the output of the 7404 inverter
goes LOW. The circuits in Fig. 5.13 are not recommended for critical uses
because they exceed the output current ratings of the ICs. However, the circuits
in Fig. 5.13 have been tested and work properly as simple output indicators.
Interfacing to LEDs using a transistor driver circuit
The transistor drivers can be used with either CMOS or TTL. The LED in Fig.
5.14(a) lights when the output of the inverter goes HIGH. The LED indicator
circuits in Figs. 5.14 (a) and (b) are combined in Fig. 5.14(b). The red light
(LED1) will light when the inverters output is HIGH. During this time LED2 will
be off. When the output of the inverter goes LOW, transistor Q1 turns off while
Q2 turns on. The green light (LED2) lights when the output of the inverter is
LOW. The circuit in Fig. 5.14(b) is a very basic logic probe. However, its
accuracy is less than most logic probes.
Interfacing TTL to CMOS
he output
drive currents for the standard TTL are more than adequate to drive CMOS
inputs. However, the voltage profiles do not match(figure a). The LOW
outputs from the TTL are compatible because they fit within the wider LOW input
band on the CMOS IC. There is a range of possible HIGH outputs from the TTL
IC (2.4 to 3.5 V) that do not fit within the HIGH range of the CMOS IC. This
incompatibility could cause problems. These problems can be solved by using a
pull-up resistor between gates to pull the HIGH output of the standard TTL up
closer to 5 V. A completed circuit for interfacing standard TTL to CMOS is shown
in Fig. .
The logic levels and current requirements for TTL and Cmos are different from
each other hence they cannot simply b conne te to one another. T
5.15
5.16a Th riv urr n for standard TTL ar more a quate to drive the
e c d
e d e c e t e de
126
(a) Active-HIGH output using a NPN transistor driver

(b) HIGH-LOW indicator circuit (simplified logic probe).
Figure 5.14 Interfacing to LEDs using a transistor driver circuit.
5v
150
Input
CMOS or
CMOS or
OUTPUT
Light = HIGH
2N3904
NPN
K
A
B
C
E
33KW
(a)
CMOS
or
TTL
INPUT
LED
1
(Red)
2N3904
Light = HIGH
OUTPUT
Light = LOW
150 W 150 W
LED
2
(Green)
33KW
PNP
2N3906
B
C
Q-
1
B
Q-
2
(C)
E
C
127
Figure 5.15 Visualizing compatibility using TTL output and Cmos input profiles.
(a) Standard TTL to Cmos Interfacing
Cmos inputs but the voltage profiles does not match. The low outputs from the
TTL are compatible but there are high outputs from the TTL i.e that do not fit and
this causes problems. To interface a TTL with a Cmos we require a pull up
resistor' between the gates to pull the high output of the standard TTL up closer
to +5V, Figure 5.16.
OUTPUT
(Standard TTL)
+5 V
+3 V
+4 V
+2 V
+1 V
GND
LOW
Undefined
HIGH
2.4 v
0.8v
16 mA
400 mA HIGH
LOW
+5 V
+3 V
+4 V
+2 V
+1 V
Undefined
1 mA
1 mA
3.5 v
1.5 v
INPUT
(CMOS)
GND
INPUT
Standard TTL CMOS
OUTPUT
V
CC
V
DD
V
SS
1 KW
128
(b) Low power schottky TTL to Cmos interfacing
Figure 5.16 Interfacing using the pull up resistor
Figure 5.17. (a) Cmos to TTL interfacing using the 4050 non-inverting buffer.
Notice that the use of the 2 2k resistor is to pull the TTL high up near +5V so that
it will be compatible with the input voltage of the Cmos IC's. Interfacing Cmos
with TTL with the common 5V supply is shown in detail in figure 5.17.
The buffer gives the nverter en ugh drive current to ope ate the tandard TTL
I C
.
i o r s
. Apart from the one's explained here one of the common means of imputing
information into a digital system is the use of switches or a keyboard Examples
are switches on a digital clock, calculator keys the keyboard used with
microcomputers etc. In all these pressing the push button switch will either drop
the input to low or float at a high Float inputs are not dependable A resistor can
be added to make sure the input to the TTL goes high when the switch is open
This is the pull up resistor with the function of pulling up the input voltage up to
+5V.
.
,
. .
,
.
Low powe r(LS)
TTL input
Cmos Output
Cmos
input
Output
To any TTL
V
CC
V
SS
V
DD
2.2 KW
GND
LS
TTL
CMOS
V
CC
GND
V
SS
V
SS
V
DD
V
DD
CMOS
buffer
CMOS
Standard
TTL
129

Figure 5.17 (b) Cmos to TTL interface: cmos drives LS TTL directly without
special interfacing
Figure 5.17 Interfacing Cmos with TTL
Interfacing TTL and CMOS with Switches
One of the most common means of entering information into a digital system is
the use of switches or a keyboard. Examples might be the switches on a digital
clock, the keys on a calculator, or the keyboard on a microcomputer. This
section will detail several methods of using a switch to enter data into either TTL
or CMOS digital circuits. Three simple switch interface circuits are depicted in
Fig. 5.18. Pressing the push-button switch in Fig. 5.18(a) will drop the input of
the TTL inverter to ground level or LOW. Releasing the push-button switch in
Fig. 5.18(a) opens the switch. The input to the TTL inverter now is allowed to
float. In TTL, inputs usually float at a HIGH logic level. Floating inputs on TTL
are not dependable. Figure 5.18(b) is a slight refinement of the switch input
circuit in Fig. 5.18(a). The 10-k resistor has been added to make sure the input to
the TTL inverter goes HIGH when the switch is open. The 10kWresistor is called
a pull-up resistor. Its purpose is to pull the input voltage up to 5 V when the input
switch is open. Both circuits in Figs. 5.18(a) and (b) illustrate active LOW
switches. They are called active LOW switches because the inputs go LOW only
when the switch is activated. An active HIGH input switch is sketched in Fig.
5.18(c). When the input switch is activated, the 5 V is connected directly to the
input of the TTL inverter. When the switch is released (opened) the input is
pulled LOW by the pull-down resistor. The value of the pulldown resistor is
relatively low because the input current required by a standard TTL gate may be
Cmos
input
Output
Low power TTL
V
DD
V
CC
V
SS
GND
130
as high as 1.6 mA (see Fig. 5.18 (c).
Figure 5.18 Switch-to-TTL interfaces.
(a) Simple active-LOW switch interface
(b) Active-LOW switch interface using pull-up resistor.
Active-HIGH switch interface using pull-down resistor.
Output
TTL
Input
10 KW
+5v
Output
TTL
Input
10 KW
+5v
TTL
+5v +5v
Output Input
330W
131
1. Explain the following terms in relation to IC logic gates
(i) Supply voltage
(ii) Noise margin
(iii) Propagation delay
(iv) Fan in and fan out
2. What is the scale of integration of a digital IC. Explain the different types
briefly
3. Explain the functions of the different pins of a digital IC
4. Apart from the manufacturers code, which other information does an Ic
number convey to the user?
(i) Explain the operation of the schottky diode
(ii) How does the schottky modify the switching speed of a transistor.
6. What is Interfacing?
Explain briefly input information from the keyboard to a microcomputer.
7. What is another name for the high - low indicator circuit? Explain the
operation of this circuit
:
'
.
5.
132
CHAPTER 6
MEASURING AND TEST INSTRUMENTS.
6.1. Introduction.
Measuring and Test instruments are devices used to observe, measure, control,
compute or communicate to the user the state of the instrument under test or
check. These instruments extend or supplement human facilities and abilities to
sense, perceive, communicate, remember, calculate or reason. The remaining
part of this chapter will consider the principles of operations and application of
selected instruments as well as some test instrument relevant to the computer
system and their application in trouble shooting. Some of the instruments to be
considered includes; the multimeter, oscilloscope, logic probe, logic pulser,
logic clip, current tracer, signature and logic analyzers.
6.2. The Multimeter
A multimeter combines the features of a voltmeter, ammeter and ohmmeter in a
single instrument having but one meter movement. It can be used to measure
voltage, current and resistance within the limits of several ranges of values.
Construction and Principle of operation
The multimeter consists of three basic sections, namely, the meter, circuitry and
the front panel. The meter coil moves a pointer across a calibrated scale to a
mark that indicates the measurement value. The circuitry is a network of
components that determines the function (voltmeter, ammeter or ohmmeter)
and ranges. The front panel contains the controls and jacks that permit
operation of the instrument. Most meters (analog) have moving coil
movements. As the name implies, the movement has a coil of wire that is free to
rotate between the north and south seeking poles of a permanent magnet.
Current flowing through the coil sets up a magnetic field which reacts with the
field existing between the Poles of the magnet, causing the coil to rotate. A
pointer attached to the coil moves to a position on the meter scale, the position
depending on the amount of current passing through the coil.
133
Figure 6.1 Constructional Features.
Meter Torque
.
.
When a small current passes through the coil, a weak magnetic field s
p oduced This causes a small turn ng force (torque) to exist e een the coil
field and the permanent magnetic field This causes the coil and hence the
pointer to rotate by a small amount A larger current will cause more rotation
because there is a production of a stronger magnetic field around the coil
Meter coil
This is formed from a fine wire wrapped on a rectangular aluminum frame The
coil frame is mounted so that it can freely rotate in the air gap between the core
and the poles. In some meters, a screw on the front panel permits accurate adj
ustment of the pointer position
Meter Sensitivity
This is expressed in two ways current sensitivity and ohm per - volt sensitivity
The current sensitivity is determined by the amount of current required by the
meter movement to cause a full scale deflection of the pointer. Current
sensitivity depends on the number of turns in the meter coil and the strength of
i
r i b tw
.
.
.
.
.
Scale
Spring
Pointer
S
Permanent magnet
Rotating coil of N turns
Stationary iron core
Spring
134
the permanent-magnet field. It is expressed as the number of mill-amperes
(mA) or micro-amperes (A) required for full scale deflection of the meter
needle Typical meter movements have current sensitivities of 1 mA and 50 A
Illustration in figure 6.2 (a). ohm per volt sensitivity is determined by the total
resistance that must be in series in the meter circuit to obtain full scale deflection
when 1 volt is applied. This resistance can be calculated using ohms law as
follows:
R(ohms/volt)= E (l volt)/ I (current sensitivity)
For a 50 A meter, the resistance is 1/ 0 00005
or 20,000 ohms, resulting in a sensitivity of 20,000 ohm per volt See
figure 2(b)
.
.
.
.
6
.
.
.
( ) i ivi y
( ) v i ivi y
i ur vi y.
au
a i ns f u ing multimet r f r s ng ny m i y n a y
t inf rma i n c n ain i i s i r t y the i cuit
ag am an l a w i n cte K ron n l an.
i m i r ja ks m y a t s h f r curr nt Thr g i l
a current sens t t
b Ohm - per- olt sens t t
F g e 6.2 Meter sensiti t
6.3 General Prec tions For Using A Multimeter
Prec ut o or s a e be o e u i a ult meter stud a d ppl
he o t o o t ed n t nst uction book S ud ncluded cir
di r d e rn ho the circu ts are con e d eep the f t pa e cle
D rt or o stu e around the c a c a a s unt o e ou h t ooks
.
1mA
Sensitivity
1mA
Full Scale
Deflection
50 pA sensitivity
50 pA
-
+
-
+
50 pA
1mA
Iv Iv
R = 1V = 1000W/volt
0.001
R = 1V = 20000W /volt
0.00005
135
r gg , l i fr t n controls caref y
s itch y ir s ps K ur han s away from the metal tips of
the t r Y r b y i an will make th ohmme er r ings
in iv urin
l
,
" "
t
,
e
e

i r
u ed hand e it w th care Handle the on pa el ull Do not try to
rotate w be ond the to eep yo d
est p obes ou od res st ce e t ead
accurate apart from this you may rece e an electrical shock when meas g
voltage or current
Voltmeter and Milliameter Functions
If you must measure voltage of great amounts stand on dry insu ated material
and observe the following
(i) Turn the equipment off
(ii) Discharge any capacitor near test point
(iii) Clip the meter leads onto the test points connecting the
(iv) common lead first, and then the hot lead
(v) Turn on the equipment
(vi) Take the meter reading
(vii) Turn the equipment off before removing the meter test leads
Never place a milliameter circuit across a voltage source A small amount of
voltage may force an excessive current through he meter coil To measure
current connect the milliameter in series with the circuit
Always connect the voltmeter in parallel with the circuit voltage source, or circuit
component. Observe the polarity, plac the negative test probe (usually black)
on the negative side of th element and the positive probe (red) on the positive
side.
Ohmmeter Function
Do not measure resistance in an energized circuit, turn off appropriate
switches, disconnect battery terminals and remove power plugs or any other
source that will introduce voltage to the circuit A very small voltage added to
that of the ohmmeter battery may damage the meter coils and other
components. When taking resistance readings in a circuitry to determine if the
element being measured in shunted by another component to avoid this
affecting the reading: with this condition (i) remove one of the component leads
from its terminal before measuring or (ii) use point- to- point resistance values
contained n the instruction book o
. .
.
.
:
.
.
.
.

.
.
.
.
.

technical manual for the equipment under
test When testing capac t rs other than electrolytic use the highest resistance
range of the meter This range will supply more voltage than others If the
capacitor is good, the meter pointer will deflect slightly and, then, return to
infinity as the capacitor charges from the ohmmeter battery If there is no
det1ection, the capacitor may be open or have too small a value for the size of
the ohmmeter battery Full scale deflection with no return indicates a shorted
i o
.
.
.
.
136
capacitor Leakage is indicated by a steady deflection to some part of the
scale
6.4. Digital Multimeters
Digital instruments have become more popular in area of electronics. A digital
multimeter is one type of a widely used instrument They do not have calibrated
scale as the analogue instrument rather the measurements here are indicated
directly as numerical read out or display on the front panel of the instrument
These numbers are formed using (light emitting diode) (LEDs) or Liquid crystal
displays (LCDs) Apart from the fact that it provides more function, better
accuracy greater ease of reading and greater reliability than the analogue
instruments, the analogue instrument has the advantage of being able to track
short term variations and trends in a measured quantity than many digital
multimeters (DMM) which are too slow in their response
The functions found in most DMM are
(i) Ohms
(ii) Dc voltage and current
(iii) Ac voltage and current
(iv) Transistor and diode tests
(v) Power measurement and
(v ) Decibel measurement for audio amplifier test Today some of these
DMM are provided with automatic range selection (Auto range).
6.4. DMM configurations
The basic arrangement of a DMM is shown in the block diagram in figure 5 3 It
includes a signal conditioner, an analogue to - digital (ADC) converter and a
display section The signal conditioner, contains the function switch that selects
both the type of measurement (ohms, positive or negative d c, a c or current)
and the range Some dmm have auto-range and auto-polarity selection The
signal conditioner also includes the rectifier for changing an a c voltage to ad c
voltage before it goes to the ADC The ADC changes the analogue signal to a
digital signal (signal that is represented by a series of pulses). There are several
types of ADC circuits in use which includes
(i) linear single - slope
(ii) dual slope
(iii) star ease - slope and
(iv) integrating types
The single slope and dual slope types are more often used.
.
.
.

.
,
.
i
.
,
.
. .
.
;
.
.
.
137
Figure 6.3 Block diagram of DMM
6.4.2. DMM Specifications
Range:
The DMM has different ranges over which it will operate and these ranges are
generally arranged in multiples of 10. We might have typical ranges as follows:
200m V, 2 V, 20V, 200V and 2000V. While "2" is a common factor in all of these
ranges, the leftmost digit. generally does not exceed 1. With the above the
highest readings will be 199mV, 1.99V, 19. 99V, 199V and 1999V for the
respective ranges given above.
Over ranging:
To explain this, term, a manufacturer might consider a 200 m V range to really be
a 100m V range with 100% over ranging capability.
Ratings:
This is expressed in terms of digits and half digits. A instrument that has a
maximum reading of 199 is called a 2 digit DMM, while if it has a maximum
reading of 1999, it is a 3 - digit meter. If its maximum value is 19999, it is called
a 4 digit DMM see figure 6.4.
19.9 2 digit display
1999 3 digit display

1999.9 4 digit display
Figure 5.4 Digital Displays
Test
leads
Signal
Conditioning
Analogue to
Digital
converter
Display
138
2
1
The half designation is because the leftmost digit is normally limited to instead
of 2, such as 1 999 for 3 digit dmm rather than 2 000 the displayed value is
dependent on the range switch setting and decimal point placement
Accuracy:
DMM's have an accuracy rating of 0 1 %, plus or minus one least significant
digit Take a voltage of 0 044; A dmm ha ing a rating of 0 1 % + one least
significant digit could provide a reading error by as much as 0.00144, where
0.00044 is 1 % of 0 044 and 0.001 is one digit which total to 0 00144 The actual
value will be any value between 0.04256 and 0.04544.
Resistance Specification:
Some dmm an handle up to 20 mega ohms or more as well as having from
design the capability of measuring low ohms such as the continuity between a
ground conductor and actual ground. There is always a period of instability until
the read-out stabilizes when taking measurements, this is a disadvantage
when making continuity checks The audible indication from the tone generator
in built, gives the user an indication of good continuity between the two points
under check
6.5 Basic Measurement Techniques Using The Multimeter
Measuring current with the multimeter : To measure current, the meter must
be set to the ammeter function. The circuit must be broken in order for the
ammeter to be connected in series current
(a) Digital Multimeter
. . .
v .
. . .
c
.
.
.
-
.
.

.
'
-
139
(b). Circuit under test
Figure 6.4 Measuring current with multi meter
The circuit. is broken at point B, figure 6.4 (b), and the multimeter leads inserted
according to the configuration in the circuit and the current is read off on the
meter front panel as shown m figure 6.4 (a).
(ii). Measuring voltage
The meter in 6.4 (a) is set to the voltmeter function (i.e the V Point.) to measure
voltage. The voltmeter is connected to the two points across which voltage is to
be measured. From figure 6.4 (b) the probes (leads) of the multi meter will be
connected to a new configuration in points C and D and the value displayed on
the LCD read out of the meter.
(iii). Measuring Resistance
The meter must be set to the ohmmeter function to measure resistance. Before
the connection of the ohmmeter the resistance to be measured must be
disconnected from the circuit. Remember to turn off the power supply before
disconnecting any component. The meter function selector is turned to the ohm
function (i.e. the" W point). The probes are connected across point E and F and
the Value IS displayed on the LCD screen and read of in ohms
Measurement of in coil resistance
Here we will consider how to use the meter to test an inductor for an open
winding and for shorted winding. To check for an open, the coil should be
removed from the circuits. If there is an open, the meter (use as an ohmmeter)
will show infinite resistance. The illustration is shown in figure 6.5 (a) Note that
the value of the winding resistance depends on the wire size and the length of
the coil. In (b) above, if you watch the movement of the needle more closely as
you measure the resistance, you will observe the following:
Sw 2
1 E R
B
F
X X
C
1
D
2
V 12V
140
Figure 6.5. Measurement of coil resistance using the multimeter
The time taken to measure the resistance of the inductor is longer than that
required for the resistor This is so because the inductor opposes the flow of
alternating current, meaning that it opposes any change of current, and, when
you connect the leads of
.
.
th in
chang f o ero o y r y r
n o e t g ow r h i a l

, h
x i i
t r :
v t war the
i h-r a ce a c a g eter
bat a xtremely
rom t y a g
v , w t r di ate m or
e ductor, the current through the
inductor es r m z t a stead eading recorded b the mete The
i ductor opp s d he r th of this current th ough t e nductor l the while it
was charging
Multimeter Test of capacitors
To test a capacitor when there is a suspected problem the first t ing to do is to
remove the capacitor from the circuit and check with a meter. Set the meter to
the high ohm range say, lM ( f us ng analogue multimeter) and connect the
probes of the multimeter to he leads of the capacito and observe following
The pointer should be zero ohms initially and then b"egil1s to mo e o d
h esist n end of the scale as the cap citor h r es from the ohm
tery it is fully charged, the meter will indicate n high
resistance Since it charges he meter batter the l r e the capacitance
alue the more d b eter motion F small
multi meter to the
.
s
g m
. When e
. f ,
slo ly i will cha ge as n c y i .
(a) Coil open Meter

reads infinity
:
(b) Good Coil M ter

reads winding
r sistance
: e
e
Short d winding
Meter reads zer or a
lower resistance
depending on the numb r
of turns that ar short d
e
o
e
e e
:

.
R x 1
R x 1
R x 1
141
v capac tors the respons of h ay i he
ch ng ac ion
* f i o i sta th r
n rm .
* i i
i i
i tru h i i y
v s f i s n i i , e
imi a i r w a v in on the ariation in r
i a tim a v T main ain troublesh ot an r air
c ron q ip nt m en nce ers ne t l k t the
m of a s nal p e fr m e ircu nother h e is
n t p ovi quir reli e re s n a io o the ig l
h lp the p son l to k th s system u i ope
ncti n f y earn
h a eas ly
. a u
its ys e av . co r gna
s a he w e form
e s all con i th o w
, od
v
6.6b. ma or
v a w ile oriz tal s t i
s ale
alue e t e meter m not be sufficient to ind cate
argi t
Note: I the capac t r is nternally shorted, the meter will go to e e but if it
is leaky, the final reading will be less than o al
If the capac tor is open, no charging action w ll be observed and the
meter will nd cate infinite resistance.
6.6. The Oscilloscope
This s a test ins ment (Indicator) that has t e capab l t to show the
wa eform s nusoidal and non- i uso dal s gnals Hence it overcom s the
l t t ons of multimete s hich c nnot gi e formation te ms
of ampl tude nd e of wa eform t d ep
ele ic e u me p
s c T
eeded o de the re ed pre e t t s nal This
e er e tate of the nder repair All sc llosc
in accordance with the same set of fundamentals I ou l how one
oscilloscope works and ow it can be used, you c i learn how to operate
others All oscilloscopes contain cathode-ray tube (crt) and a p of control
circu The crt displa th eform The n cuit presents the si l to
the crt and a set of te t le ds brings t to the control circuits
W h der e scilloscope under the follo ing The scilloscope
screen the cath e ray tube and the front panel controls
The oscilloscope screen
This is divided into ten horizontal divisions and eight ertical divisions as shown
in figure Each j division is divided into five small or minor divisions on
both axes The ertical xis is the voltage scale h the h on he t me
c
i t
.
y
o .
v
. o , o
t , the aint a onnel eds o oo a
wavefor ig s it ass o on it to a e Oscilloscop
r abl n f wi l
a now o s
fu o .
n
gro
w trol ci
av .
s o
. i
.
a
.
:
.
.
.
,
(a) the oscilloscope
142
6.6.2. The Cathode-Ray Tube
The construction of the tube for the purpose of the crt is shown in figure 5 8
Electrons are emitted by the heated filament F The anodes A , A and A are
1 2 3
kept at positive potentials with respect to the filan1ent The electron beam is
therefore accelerated down t e axis of the tube which is highly evacuated The
shapes and potential of the anodes are chosen so that the electric field between
than converge the beam to a fine spot on the fluorescent screen S The filament
is surrounded by a cylindrical electrode G called. the grid of the cathode-ray
tube and kept at a negative potential with respect to F This potential controls the
proportion of electrons emitted to reach the hole in the first anode AI, controlling
the br ghtness of the spot on the screen The side walls beyond the last anode
are usually coated with a conducting layer of graphite, which is electrically
continuous with a conductll1g film on the inside of the fluorescent screen
These are connected to the final anode and provide a return path for the
electrons to complete the anode circuit The tube has two pa rs of deflector
. .
h
.
.
.
.
.
.
.
i .
i
.
143
Minor
Division Marks Major
Division
}
(b) The oscilloscope screen
Figure 6.6. The Oscilloscope
plates, X and X, for horizontal and Y and Y for vertical deflection One of each
J 1 2
of the plates is connected to the final anode A The deflection of the spot of light
as proportional to the p difference between the pair of deflector plates
F gure 5 8 the cathode-ray tube. The beam may also be deflected magnetically
using cu rents n coils mounted round the neck of the tube Th s method s
applicable to television tubes
6.6.3. The front panel controls
The volts /Division controls This sets the number of olt to be represented by
each major division on the vertical scale Fo example, if the switch in set to the
1V mark it means that each of th major vertical divisions is 1V, if the volt per div
is 2 volts for instance each division will now be 2 volts as against 1V Hence we
count the number of major div sions from zero crossing to the peak of the wave
form and multiply with the volts/div value to measure the peak value of the
w e displayed. The time (seconds) /Division Control Th s el s the
number of seconds, micro or milliseconds represented by each major division
on the horizontal scale. This controls how fast the electron beam scopes
horizontally across the screen To measure the period of a waveform, count the
number of major divisions covered by one cycle and multiply by the SEC DIV
value. Use f= l/T to calculate the frequency
Power switch:
This turns the scope on or off with a light indicating when the power is on.
Intensity control knob: This varies the brightness of the trace on the screen.
The intensity should not be left to high for a long time when the beam forms a dot
.
3
.
i .
r i i i
v s
r
e

i
av form i s ect
.
/
.
.
otential
.
.
:
.
.
:

144
Electron gun
Triode
Section Focusing Deflection
Post deflection
acceleration Aquadag
Screen
Resistive
helix
Vertical
deflection
shield
Grid
Glass
envelop
A
1
A
2
A
3
Cathode
Filament
Isolation
shield
Horizontal
deflecting
plates
Focus control: This focuses the beam to converge to a tiny point at the screen.
Horizontal Position: Also called the coarse or fine, adjusts the neutral horizontal
position of the beam They are used to reposition horizontally a waveform
display for convenience of viewing or measurement.
Vertical Position: This control moves each trace up or down for easier
measurement or observation
AC - GND - DC Switch: Located below the volt/div control, allows the input
signal to be ac coupled, dc coupled or grounded While the ac coupling
eliminates any dc component on the input signals, the dc coupling permits dc
values to be displayed The ground position allows a OV reference to be
established on the screen
Mode Switch: This provides for the display of either or both channel inputs,
inverting channel signals, adding two wavefolms and selecting between
alternate and chopped mode of sweep:
Trigger Control: This offers a wide range of controls such as VAR HOLD OFF,
MODE, SLOPE, LEVEL and SOURCE This controls allows the beam to be
triggered from various sources. Triggering causes the beam to begin to sweep
across the screen It can be triggered from an internally generated signal ie input
or line voltage, also from an externally applied trigger signal The modes of
triggering are: auto, norn1al, single sweep and TV The auto mode: sweep
occurs in the absence of an adequate trigger signal
The normal mode: A trigger signal must be present for sweep to occur
TV mode: Pro ides triggering on the TV field orTV line signals The slope switch
allows the triggering to occur on either positive or negative-going slope of the
trigger waveform The level control selects the voltage level on the trigger signal
at which the triggering occurs In summary, the trigger controls provide for
synchronization of the horizontal sweep waveform and the input signal
waveform, resulting in a display signal that is stable on the screen
Signal inputs: Connections to the oscilloscope is usually done with probes that
reduces the loading effect of the scopes input resistance on circuit being
measured. Voltage probes are either none attenuating i) o attenuating say, by
10 (x 10). When the xl 0 probe is u e he olt div setting must be multiplied by
10.
"
.
.
.
.
.
.
.
.
.
.
.
v .
.
.
.
(x r
s d, t v /
.
145
6.6.4. Testing With The Oscilloscope
The graticules on an oscilloscope display can be used to measure amplitude
and time as shown in figure 6.8a(i). This time/amplitude measuring ability of the
oscilloscope enable us to measure almost every characteristic of a digital
signal. To begin with, the vertical scale can be used to measure the HIGH/LOW
logic levels as shown in fig. 6.8a(ii). On the other hand, the horizontal scale can
be used to measure the periodic rise time, fall time, and pulse width of a digital
signal as shown in fig. 6.8a(iii). Once the period of a cycle has been calculated,
the frequency can be determined (since f = 1/t). Some of the more common
digital circuit tests using the oscilloscope include the following:
(a) You can use the oscilloscope to check the clock or master timing signal
within a digital system to see that it is present at every point in the circuit
and that its frequency, wave shape and amplitude are correct.
(b) You will also use the oscilloscope to monitor two or more signals
simultaneously as shown in fig. 6.8a(iv). In this instance, an input and
output waveform are being compared to determine the NAND gate's
propagation delay time.
(c) The oscilloscope can be used to measure waveform distortions such as
the ringing shown in fig.6.8a(v) to see if these undershoots or overshoots
are causing any false' operations such as incorrectly triggering a logic
gate.
6.6.5. Measurement Of Pulse Using The Oscilloscope:
When working with digital equipment pulse measurement s r important A
digital pulse contains the following parameters
i ve y
:
.
* Pulse rate.
* Duty cycle.
* Pulse width.
* Fall time.
To measure pulse say, a square wave using an oscilloscope, the set up in figure
6.8b is used.
From the display shown in figure 6.8(ii), the rise and fall times are measured
146
(a) Oscilloscope Measurements
Amplitude
Time
(i)
Period
Pulse width
Rise
Time
Fall
Time
(iii)
+5V
SW
1
SW
2
SW
3
SW
4
D
0
D
1
D
2
D
3
0
1
0
1
Input Board
OSCILLOSCOPE
+ 5V
0V
(ii)
+ 5V
1
2
U15
3
Input
Output
t = propagation
pd
delay time. t
pd
t
pd
CHB CHA
(iv)
147
b (i) Test setup for pulse measurement
b (ii) Display and pulse measurement parameters
Figure 6.8. Oscilloscope measurement techniques.
Along the horizontal axis with the TIME/DIV set at 0.1s, the rise time and fall
time values are
t = 0 7 x l00ns = 70ns
r
..
t = 0.9 x l00ns = 90ns
f
The pulse width (pw) is measured from the 50% mark, while the time period (T)
is the time required to complete one full cycle:

.

Pulse
Generator
Trigger Pulse
Out Out
Circuit
Under test
in out
10:1
probe
Oscilloscope
Vertical
Input
A B
External
Trigger input
Pulse width
(PW)
Input pulse
Output pulse
Fall time (b)
Rise time (b)
Delay
time (a)
Pulse amplitude
907
10%
AV
T
148
P = 450ns and T = 800ns
w
Pulse repetition frequency, PRF = 1/T = 1/800 X 10 = 1.25MHz
The duty cycle = PW/T= PW X PRF.
To measure the rise time accurately, stretch out the pulse so that the leading
edge alone is visible on the screen. We consider two factors rise time of the
signal generator tr gen and that of the scope. The true rise time of the circuit
under test can be derived from
2 2 2 2
t = (t measured t scope - t gen)
r r r r
Example: A pulse generator used for test have t = 2ns and the oscilloscope
r
bandwidth is 100MHZ. The measured rise time is 5ns, determine the actual rise
time.
Solution:
t scope = 0.35 / BW
r
= 0.35/1 x 10
= 3.5ns.

2 2 2
T = (5 3.5 - 2 )
r
= (25 12.25 - 2)
-9
= 2.96 x 10 or 2.96ns
6.6.6. Pulse waveform
A pulse is a very rapid transition (leading edge) from one voltage or current level
(baseline) to an amplitude level, and after an interval of time, a very rapid
transition (trailing edge) back to its baseline level. It is made up of two steps
positive going called the leading edge and negative going called the falling edge
and separated by a time interval called pulse width. The height of the pulse is
called the amplitude. We have just described an ideal pulse shown in fig. 6.8.
Figure 6.9Ideal Pulse
Pulse
amplitude
Pulse
width
Leading (rising)
edge Trailing (falling)
edge
Base line
Leading (rising)
edge
Trailing (falling)
edge
Base line
Pulse
amplitude
Pulse
width
(a) positive going pulse (b) Negative going pulse
149
Actu l pu ses f ure 6.9 are never deal and possess o ta cha acter st c that
ma es them different from ideal pulses The me equ ed fo the pulse to go
from 10% of its full (amplitude) to 90% of its full value is called Rise time (t ). The
r
time required for the pulse to go from 90% of its full amplitude to 10% is called the
fall time (t ). The pulse width is the time between the point on rising and alling
f
edge where the value is 50% of full amplitude.
Figure 6.10 Actual pulse showing rise and fall time (Pw is the pulse width).
The other characteristic are the pulse repetition frequency (PRF) which is the
rate the pulse repeats. It is the waveforms fundamental frequency expressed in
hertz or pulse per second The time from one pulse to the corresponding point in
the next pulse is the period, T
Finally, the duty cycle is the ratio of the pulse width Pw to the period (T)
expressed in percentage.
% duty cycle = Pw / T x 100.
a l ig i c n in r i i s
k ti r ir r
f
.
I.e,
.
150
Pulse
width
90%
50%
10%
V
Delay
time (t )
d Rise time (t )
r
Fall time (t )
r
(Pw)
6.7. The Logic Probe
This is a hand - held instrument designed to detect the logic state at a point
normally referred to as the node in a digital circuit (see circuit diagram in figure
5.14). Figure 6.12 slows the sketch of a typical logic probe, which can be used
to defect high, low and bad logic levels and also the presence of digital pulse
train in both TTL and CMOS IC's.
Figure 6.11 Basic Logic Probe
The switch selects between CMOS and TTL logic.
The probe can be powered by an external supply but it is better connected to
use the power supply of the system under test. To test logic activity at any node
in a circuit, place the probe tip to make contact with the node. The indicator lamp
on the probe proves one of the following observations:
(i) Lamp off indicates that node is below logic zero
(ii). Lamp dim indicates a logic state between 0 and 1 state, e.g. a "bad" level
such as a fault or the "correct" level for a flashing output at a tri-state or wired -or
gate
iii). Lamp bright indicates that the node is above logic 1
(iv). Lamp flashing indicates dynamic changes at the node e.g. pulse trains
passing through node.
6.8. The Logic Pulser
This instrument has the same appearance to the logic probe and is used for
injecting controlled pulses into a nodal point of a digital logic by breaking-in does
not disturb anything. The device produces an output of relatively short
Black (-)
Red (+)
L
O
G
I
C

P
R
O
B
E

C
M
O
S

T
T
L

M
E
M
O
R
Y

P
U
L
S
E

P
U
L
S
E

H
I

L
O

151
duration (few milliseconds) of either positive or negative polarity on operation of
a control button. In operation the pulser forces the existing test point condition
to conform with the pulser output i e. it "toggles" the input to the gate under test
Thus producing some sort of reaction regardless of the previous logical state of
the input The pulse being of short term duration, does not damage the previous
stage making it unnecessary to break the circuit to isolate the connection
between gates
. .
.
.
Figure 5.12 Plan view of the logic clip.
.
6.9. The Logic Clip
Th s is used to test the logic levels present at each pin of a d gital IC When
clipped the LEDs or indicator lamps on the display show the state at each pin.
Lamp off indicates logic 0 lamp on indicates logic 1, whilst dynamic operation
logic activity is indicated by flashing Figure 6.12 shows the logic clip plan view
6.10. Current Tracer
Provides a means of sensing and indicating the relative Magnitudes of the
current present in circuit board tracks without having to break the track to insert
a micro ammeter As such it resembles the logic pulser in that no circuit
interruption is necessary It operates on either the principle of voltage drop
along a short length of printed track carrying a current sensed by two probes
contacts spaced a short distance apart figure 6.13 (a), or Hall effect
semiconductor clip sensing the magnetic field surrounding a current carrying
conductor figure 6 13(b) In both cases the input is amplified and operates an
LED display or an analogue meter as an indication of the presence and relative
magnitude of the circuit current. If in moving along the current carrying t c
t ent tracer indication suddenly reduce or disappears po t hort
c rcuit has been detected
i i
'
,
.
.
.
ra k
he rr s a in of s -
i
.
.
.
:
cu ,
.
14 13 12 11 10 9 8
1 2 3 4 5 6 7
LEDS or
lamps
Pin
number
152
Figure 6.13 Principle of current tracer.
6.11. Analyzers
The logic test instruments described above finds important application in testing
and trouble shooting More powerful tools i.e. usually required for testing the
performance of complete microprocessor systems Two important test aids
have been developed and they are the signature and logic analyzers
Signature Analyzers:
This analysis is a method used to identify faulty nodes in a microprocessor
system by reducing or compressing the complex data bit streams into a simple
signature The Signature displayed on the analyzer test equipment indicates
directly whether or not the node under test is operating correctly Sets of
characters e g. 0- 9 A, C F P etc. is used and for a given microprocessors the
nodes are identi ied by a four digit signature e g. AOC2 and P666 to epresent
say node and etc
.
" "
, , ,
f r
1 2
.
.
.
.
.
. It mu t be emphas ed he e that the test program is used
for onl the sy te t as de eloped for and each node has a unique signature
hen e the sign tu e s either right or wrong .e. if the s gnature does n t agree
there is a faulty in the node n question Once the faulty node s located signal
path are then traced back from this node until correct ones are found localizing
the faul At thi point w can then resor to using logic probe logic pul e cur e
e et to locate the faulty component
Logic Analyzers:
Whereas the osc loscope is principally a time domain strument for displaying
oltage waveform as a function of time, a lo c n lyzer d spla s part of
programs (data) and timing diagrams for the systems digital control (timing
signals) It has between 16 and 32 inputs which can detect logic gnals (bits of
digital information flowing along the buses of the microprocessor system It can
trigger on a particular address signal and capture any portion of
s iz r
y s m i w v
c a r i i i o
i . i ,
,
t s e t , s r, r nt
trac r c.
il in
v gi a a i y
'
. si
.
.
.

PD set up
between
probes
Current flow
track
track
(a) Voltage drop
(b) Hall effect
Hall
place
Magnetic
field
153
the program currently executed by the system undergoing test and display 16
lines of the program content immediately after or before the trigger. By choosing
a faulty system operation to be the trigger for instance, the events that lead to the
fault may be observed and analyzed The analyzer can also be triggered by a
control or data signal and use the clock of the circuit under test for timing In
summary the logic analyzer allows specific portions of a program sequence to
be examined and are especially useful for trouble shooting new circuit designs
Unlike signature analyzers, they are not necessarily designed for a particular
system and provide more detailed data and timing information for analysis
.
.
.
.
6.12. Testing With The Logic Clip Or Probe
(a) Logic Clip
The logic clip which is shown in fig (a) was spec ally designed for
troubleshooting digital circuits It consists of a spring loaded cl p that lamps
onto a standard IC package where it makes contact with all the pins f the IC as
shown in fig (b). These contacts are then available at the end of he clip
such that a
(a) The Logic Clip.
. 6.14
. c
. 6.14
i
i
o
t
multimeter or an oscilloscope probe can easily b connected. Some
logi lip ha e nn ctions on the top o he lip while other have light -emitting
diodes (L D nd testing point on the top of the clip a hown in ig. 6.14(a).
The LEDs gi quick indication of the binary level on the pins o the with a
logic turni n LED OFF and a logic 1 tur an L D ON.
e
c c s v co e f t c
E s) a s s s f
ve a f
0 ng a n E
Ie
Testing Pins
1
2
3
4
5
6
7

154
(B) Testing with the logic clip
Figure 6.14. The Logic clip and testing
(B) The Logic Probe.
In order for the probe to op rate i red and black power leads must be
connected to a power source. This pow r sou normally be obt ined from
the circuit b ing tested as shown in ig .15 the pow r d av b n
n c ed, h l gic probe i n t
e , ts
e rce an a
e f . 6 Once e lea h e ee
co ne t t e o s ready to se se h
c
; s
e
"
vol age at any po nt in a igita
circ it an give an indication as to wheth th oltage is a valid binary 1 or 0.
The and LO LEDs on the l gic pr be ar u ed to indicate the logi levels as
shown in fig. 5.16 Since the voltag thre hold f r a b nary 0 or 1 can be
different, most ogic probes have a selector t h t select internal thres old
etection for , ECL an CM S. In addition to be ng a e to p r orm stati
tests (constant or non-changing high and low signals) like those of t e
multimeter, the logic probe can al o perform dynamic test (changing signals)
ike t ose of the oscilloscope uch a detectin a ingl momentar pulse (a
single pulse) or a train of pulses (s qu nc of pul such as a clock signal
t i d l
u d
HI
i
l h
d TTL d O i bl e f c
h
l h
er e v
o o e s c
. e s s o
swi c o
s s
s s g s e y
e e e ses)
'
.
16 PIN
16 PIN
Probe
GND
DECODER
BOARD
155
Figure 6.15 Testing with the Logic probe
The logic probe can al o perform dynamic test (changing signals) ike t ose of
the oscilloscope uch a detectin a ingl momentar pulse (a single pulse) or
a train of pulses (s qu nc of pul such as a clock signal
s s
s s g s e y
e e e ses)
l h
'
. The logic probe can
also detect i a ingle pulse has oc urr d even if t w d h of h puls i so small
that the ope ator wa unabl to e the pul L blink In thi instance
memory circuit can be n bled using the me y t that n pul e will
turn ON and keep ON th pul e LED
T tin Wi h he Logi Puls r Or urre r
o ic Pulser
ul r i ign l g ner tio design d p du e eithe l pu
ul r in It appear nce simil r to he l p obe a i equire uppl
v ltage to op t nd has a pr b i u l pu t th cir uit
under te t. as h n in figure l i ul at d by simpl
tou hing the probe tip to an c nducting p int n i h n pressin the
f s c e he i t t e e s
r s e se se ED . s , a
e a mor swi ch so a y s
e s
es g t T c e C nt T acer
(a) L g
A logic p se s a s a e a n e to ro c r a sing e lse or
p se t a . s a is a t ogic s t r s a s y
o era e a o e wh ch is ed app y lses o e c
s s ow 6.16 The og c p s r oper e e
c y o o o a circu t an t e g
a
s to
e is
d
r
LOGIC
PROBE
CMOS
TTL
MEMORY
PULSE
PULSE
HI LO
+5V
0
0
0V
0V
U2
U2
U1
Logic
Probe
HI LO
PULSE
LO LED is ON and
PULSE LED is flashing
indicating a positive
going pulse.
156
SINGLE PULSE button for a single pulse r l i th RAIN itch
po ition f r a constant sequence of pulses.
o se ect ng e PULS T sw
s o
E
Figure 6.16 Testing with the logic pulser.
The logic probe is generally used in conjunction with the logic pulser to sense
the pulse or pulses generated by the logic pulser. This ability of the logic pulser
to sense the logic level present at any point and then pulse the line to its opposite
state means that the operator does not have to determine these logic levels
before a point is tested thus making the logic pulser a fast and easy instrument to
use. The logic pulser achieves this feature with an internal circuit that will
override the logic level in the circuit under test and either source current or sink
current when a pulse needs to be generated. This complete in-circuit testing
ability means that components do not need to be removed and input and output
paths do not need to be opened in order to carry out a test.
(b) Current Tracer
The logic pulser can also be used in conjunction with another very useful test
instrument called a current tracer which is shown in fig. 6.18 (a). Like the logic
probe, the current tracer is also a sensing test instrument but unlike the logic
probes, the current tracer senses the relative values of current in a conductor. It
achieves this by using an insulated inductive pick-up tip which senses the
magnetic field generated by the current in a conductor. By adjusting the
sensitivity control on the current tracer and observing the lamps intensity when
the probe is placed on a pulsating logic signal line, a shorted path can be found
by simply tracing the path of high current. To troubleshoot a short in an IC's
Power supply voltage5 to 15v.
Black (-)
Red (+)
L
O
G
I
C

P
R
O
B
E

P
U
L
S
E

5
0
0

P
P
S

I
P
P
5

S
I
N
G
L
E

P
U
L
S
E

S
I
N
G
L
E

P
U
L
S
E

P
H
A
S
E

T
R
A
I
N

158
(a) The current tracer
Input or output circuit, or a power supply or a printed circuit board (PCB) track or
cable, we would traditionally have to cut PCB tracks, snip pins or open
component leads. This would isolate the short since the excessive current path
or short would be broken when the path was open. The current tracer allows the
troubleshooter to isolate the shorted path without tampering with the circuit.
Figure 6.17(b) illustrates how the current tracer should be correctly aligned on a
conducting PCB track. Like the logic probe and logic pulser, the current tracer
can use the same supply voltage as the circuit under test. Since the tip is
insulated, it can be placed directly on the track,
Current
Tracer
(b) Illustration figure 6.17a directly
Power supply voltage5 to 15v.
Black (-)
Red (+)
C
U
R
R
E
N
T

Insulated Inductive
Pick-Up Probe
C
U
R
R
E
N
T

T
R
A
C
E
R
158
Figure: 6.17. Current tracing
159
W
0

V

A

1

2
3
4
5 6
7
8

9

1
0

2
3
1
3
0
0
0

1
0
0
0
5
0
0
2
0
0
1
0
0

5
0
4
0
30 20 10
1
0

W
1

2
3
4

~
Chapter 6 Questions
Question 1: In the figure below, fill in the values for the meter readings
shown by the pointer.
Pointer Position 1 Pointer Position 2
Scale Value
Wx1
A.C. IKV
A.C. 600V
D.C. 3V
Scale Value
A.C. 300V
D.C. IKV
A.C. 10A
D.C. 0.3mA
Multi - Meter: Reading of Value in different scales
Pointer Position 3 Pointer Position 4
Scale Value Scale Value
D.C 300V
D.C 300V
Wx 100
D.C 30V
A.C 10V
D.C 100V
A.C 0.01A
D.C. 1A
160
Question 2:
CHAPTER 7
TROUBLE SHOOTING AND FAULT FINDING
7.1 Need For Trouble Shooting
Trouble shooting is the practical application of theoretical theorical
principles in a logical manner to locate a fault that causes a piece of equipment
to operate at less than the designed performance It is aimed at narrowing the
problem by identifying the "good" parts of a circuit as rapid as possible by
eliminating in order to reveal the "bad" parts for close and detailed checking.
Good troubleshooting is not a talent a person is born with but a skill that
can be acquired by anyone with a suitable electronics background and requires
the following prerequisites:
(i) sufficient electronic knowledge to learn how a piece of equipment works
(ii) suitable skill in reading and interpreting data contained in the technical
manual or service folder.
(iii) suitable skill in operating test equipment and interpreting test readings.
(iv) Ability to troubleshoot in a logical manner.
Since all electronic equipment is made up of selected electronic circuits,
which in turn operates in accordance with the fundamental principles of voltage
and current, and the characteristics. If you reduce any electr0nic equipment to
the bare essentials, you will find that the equipment operates the way it does
because of the circuit arrangement of the components and their effect on
current and voltage.
This brings us to the conclusion that trouble shooting is the method of
isolating the fault in a malfunctioning piece of equipment using electronic
principles, ability to extract data from a technical publication, and the skill in
using test equipment. The isolation of The fault is done in a series of sequential
steps and each step is based on valid deductions that systematically narrow
down the trouble to the faulty part, wire, or connection, Figure 7.1 show the use
of series of sequential steps to narrow down trouble to Smaller areas.

Figure7.1: use of series of sequential steps to narrow down trouble to Smaller
areas.
Faulty
Equipment
Faulty
Function
Faulty
Circuit
Faulty
Part.
161
Five steps have been proven to be the most reliable approach to fault finding
any equipment, regardless of size, and the steps in proper order are shown in
figure 7.2.
5 Seek out cause and verify
4 Pick out faulty circuit
3 Expose faulty function
2 Trace out probabilities
1 Search for symptoms
Figure 6.2: Five steps for logical troubleshooting
Step 1: A symptom can be said to be an outward indication of the abnormal, or
non function of a piece of equipment. So in searching for the symptom,
experience (set of instruction needed to Gain greater skill) over the years have
proven that question must be asked about the genesis of the problem.
Application of the human sense of sight (look for any broken or burnt area or
part) small: (for unusual odor because many device have their characteristic
odor when over-heated ). Hearing: (listen to any strange sound, crackling,
arching, hissing, humming etc) and touch; (feel the parts e.g power resistors
should not be very hot, a hot electrolytic capacitor in circuit is dead for
instance)., Is inevitable.
Step 2: A function is the purpose of the equipment, a group of circuits, or circuit.
In the narrowing-down feature of logical troubleshooting, the idea is to pick out
a few of the several functional circuit groups in which the trouble most probably
lies. When this is done, the search is narrowed down to a smaller area. During
this step symptoms information is used to make logical technical deductions
to identify the functional areas of equipment that may contain the trouble.
Step 3: Up to step 2 above you have neither entered the equipment nor used
any external testing devices. In step 3 equipment is tested to determine which
of the probable faulty function contains the trouble.
Measurements made here are either static or dynamic.

Static measurement: This is made on equipment with no signal input and
sometime no power supply. The measurements made here include, voltage,
Order of
steps
162
resistance and current. Voltage measurement is very important as it is the
easiest to make and will normally indicate the position of the fault if it is
determined by static test.
Dynamic measurements: This is made with suitable signal applied. The signal
being traced through the equipment ,until the fault is located.
Note: A board containing different functions can be treated as a single
functional entity and in this case it may involving swapping a new board or
device for a bad one.
Step 4: Narrowing - down continues in the fourth step by working toward the
faulty circuit within a functional group. This is carried out by making technical
deductions from accumulated symptoms and test data. This deductions result
from studying the servicing block diagram and, then closing in on the
malfunctioning circuit.
The servicing block diagram consists of blocks representing each circuit within
the functional group and are interconnected to show the direction of signal flow,
input and output test points as the case may be. Some diagrams goes a step
further to show the waveform data at important points within the diagram.
Step 5: Troubleshooting procedure in steps I to 4 above has narrowed the
trouble to a single circuit consisting of a few electronic parts. The seek out
portion of the final step suggests that the faulty part be found and verified as the
cause of the trouble. The trouble can be narrowed down by analyzing the output
waveform of the circuit, making voltage or resistance checks, and / or by
substituting a good part for a suspected or bad one.
7.2 . TROUBLESHOOTING
The most basic piece of test equipment used in digital troubleshooting
today is the logic probe we have earlier described in chapter five. In trouble
shooting the first step is the use of our senses by feeling the flat top of the IC to
determine if it is hot, since some IC operate cool and others warm. Look for
broken connection, bent pin, broken PC board traces and look out for broken
solder bridges. Smell for possible over-heating and look out for discolorations or
charring.
163
The several step is to check whether the IC has power using the logic
probe. With the probe connected to power" check the points label A, B, C and in
figure 7.3 The nodes A and B should give a HIGH light while C and should give
LOW light in the logic probe
Note: when using the logic probe for testing, the red lead is connected to the
positive of the power supply while the black lead is connected the negative
(GND) of the power supply. After powering the logic probe the need le- like probe
is touched to a test point or node in the circuit. The light will be either HIGH or
LOW, if neither indicator lights it means the voltage is somewhere between the
HIGH and LOW:
The third step is to trace the path of the logic through the circuit. In figure 7.3 if A
is HIGH and B (pin 14 of lC) is low this will Indicate an open circuit in the PC
board trace or a faulty solder joint between points A and B
Figure 7.3 Test IC mounted on a printed circuit (PC) board.
If pins 1, 2 and 3 shows a LOW and no reading at pin 4 will mean that he input
(pin 4) is not, connected and is considered to be a HIGH by the TTL circuitry
inside the 7408IC: The output of the first AND gate (pin 3) is suppose to pull the
input to the second AND gate (pin 4) LOW. If it does not, the fault could be in the
PC board trace, solder connections or a bent IG pins. Internal opens and shots
also occur in digital IC's as will be considered in the next section.
164
D
G
N
D
C
E
7
4
0
8

V
CC
VC
C
A
B
7.2.1. Trouble-shorting Simple Combinational Logic Circuits
Consider the combination logic circuit mounted in the printed circuit
board in figure 7.4 when two NAND gates are feeding an OR gate, this is an
equivalent of a four input NAND gate function. To trouble shoot the circuit to find
the fault the following steps are employed.
(i) Set logic probe to TTL mode and connect to power.
(ii) Test nodes 1 and 2 and note the result
(iii) Test nodes 3 and 4 and note the result. The result here should give
information on the state of power in the IC.
(iv) Test the four - input NAND circuit's unique state, inputs A, B, C and D
should all be HlGH. Now test pins 1,2,4, and 5 of the 7400 IC and note
down the result.
(v) Test the outputs of the NAND gate at pins 3 and 6 of the 7400 IC and note
C down the result.
(vi) Test the inputs to the OR gate at pin 1 and 2 of the 74321 IC and note
down the result.
(vi) Test the inputs to the OR gate at pin 1 and 2 of the 74321 IC and note
down the result.
Figure 7.4: Testing a faulty combinational circuit mounted on a on PC board.
The result for the respective troubleshooting on the, circuit is"as, follows: ,
(ii) The two nodes are both HIGH
(iii) Both are LOW indicating the two IC's have power.
(iv) All the inputs are HIGH but LED still glows and indicates a
HIGH output indicating that the four - input NAND circuit is faulty.
(v) The outputs at pins 3 and 6 of the 7400 IC are low meaning the NAND
gate are functioning well.
165
VCC
7408
G
N
D
VCC
GND
7432
VCC
3
2
4
1
A

B
C
D

(vi) Inputs at pins 1 and 2 of 7432 IC are LOW, this is correct but the output is
incorrect. Therefore the OR gate is faulty and the 7432IC ne ed to be
changed.
7.2.2. Trouble-shooting The Computer System.
The troubleshooting process here does not fall short of what we discussed in
section 7.1. Applying the procedures the following steps will be employed to
troubleshoot a faulty computer.
Routine Checking:
- Computer fails to come on: check and be sure that the power cord is
properly plugged both on the supply and computer side and ensure that the
voltage resolution switch on the rear of the power supply is set for the proper
voltage.
- Computer in on and no display on the monitor: check for the following; the
monitor cord connection between the computer and monitor, adjust the
brightness and contras controls on the monitor and make sure the display
adopter is properly installed in the expansion slot where applicable.
_ Keyboard Failure: check for the following; keyboard compatibility with
system unit, make sure keyboard is properly plugged into the system and check
to be sure, the XT/AT switch on the rear of the keyboard is set to the proper
position where applicable.
- Flicker or Waver Image on Screen: check for defective or loose video
cable.
The Procedure:
For effective fault finding the procedure is very necessary to narrow down the
problem to source. This will include visual and audible observation, odor
detection and touch. To perform proper trouble shooting the covers of cabinets
has to be removed after the routine checks, have been carried out for proper
inspection.
Upon opening the cabinet, the internal component must be checked for
discolorations or other visible damage, this extends to the mechanical parts.
Listen and observe any abnormal sound like grinding or rubbing during power
up, while system is on or during disk access and vibration of transformer
lamination and arcing.
The computer during normal functioning produces heat and associated
odor. that is not pungent or offensive: If an offensive burning odor is detected,
166
the system should be removed from power immediately.
Touching has its disadvantage if done carelessly, because electrostatic
discharge (ESD) from our body could damage some of the clips inside the
system. Against this the following could be observed by touch:
(i) heat is given off by RAM and CPU clips when power is on hence cold clips
may indicate a problem.
(ii) The hard drive motor would be active when power is on
(iii) The motor vibration indicates proper functioning.
(iv) sluggish or stuck keys on the keyboard is detected by touch.
Knowing the appropriate path to a destination can get you to your
destination with lesser problem and time spending, hence knowing the
procedure to repairing a system makes the job easier and less time consuming.
Now consider four basic procedure;
1. The Power Supply
If the power supply is suspected to be the source of the problem, simple
measurements should be used to confirm whether it is bad or not. To test the
power supply check the voltage between pins 1 and 5 (ground) for the 2.4 to 5.4
dc voltage on the system connectors. If the measurement is not within range it is
bad. Continue measuring to confirm the voltages shown in the tables below.
Table 1
Voltages Pins
Minimum Maximum -Leads +Leads
-4.8 +5.2 P8 - 5 P9 - 4
-4.5 +5.4 P9 -3 P8 - 3
-11.5 +12.6 P9 -1 P8 - 3
-10.8 +12.9 P8 - 4 P9 - 2
Table 7.1 Mother board Connector Measurements.
167
Table 2
Voltages Pins
Minimum Maximum -Leads +Leads
+4.8 +5.2 2 4
+11.5 +12.6 3 1
Table 7.2 Disk Drive Connector Measurements
If these voltage are not as shown in the tables above replace the power
supply. These measurements are made with correct supply and the system
running.
The Switching power supplies is used in these systems. If you remove
the power supply from the system unit and power it, the supply will shut itself
down.
Problems:
All devices in a PC derive their DC power from the power supply and a cooling
fan in a system is a predictor of a power supply failure due to the subsequent
overheated components. The supply failure is often noticed as a burning smell
just the system shuts down.
The cooling fan failure causes overheating as a result some component
get damage or blown in some case. The hotter the computer temperature, the
shorter its life of span.
The summary of the problems associated with the power supply are:
(i) System start up failure or lockups
(ii) Re-booting or intermittent lockups during normal operation.
(iii) Intermittent parity check and other memory type errors
(iv) The + 121 will not be supplied causing non spinning of the hard disk.
(v) Overheating due to fan failure
(vi) Electric shock on system case
(vii) Slight static disturbs system operation.
The remedy to the problems mentioned above is to replace the power
supply unit and ensuring adequate air - flow to cool the system properly.
168
2. The System Board
The motherboard failure is sometime difficult to detect because the
system is simply none functioning. If the system is partly or completely non
functional the failure should be attributed to the mother board and the following
troubleshooting guide is useful to solve the problem.
(i) Check all connectors to be sure they are correctly plugged in.
(ii) Confirm that the wall outlet is a working outlet.
(iii) Look for foreign objects and make sure the board itself is clean.
(iv) Check for correct switch setting in the system board.
v) Run an advanced diagnostic system board test. An error is always
displayed on the screen for you to know the nature of the problem.
3. The Battery
The easiest way to determine a defective battery is to replace (A
defective battery is usually indicated during the power on self-test (POST) with
a 161 error.
If you run a SET UP program and it does not correct the problem
disconnect the battery from the system board. Note that the voltage between
pins 1 and 4 on the battery connector should be 6.0 Vdc at least.
4. Hard disk/ Drive Failures
Only two disk problems can be fixed easily namely, the drive speed and
dirty drives which requires speed adjustment and "wet" cleaning respectively.
The major failure in the hard disk is mainly that of head crashing which damages
both the head and the surface of the disk.
This damage is permanent and causes complete loss of data. This crashing
happens when the disk rotating at a speed of 3600 p.m. touches the head.
Turning the system off while the hard or floppy disk drive is performing a
write operation can cause head crash and destroy the drive.
The circuit board is another essential component of the hard drive that
helps in proper operation. Since the board contains the circuits controlling the
speed of rotating the disk, movement of the read and write leads as well as
encoding / decoding of data, a failure on the board can cause severe drive
failure.
The symptoms of the board failure are as follows:
(i) excessive seek failures error
(ii) sector not found error.
This continues until the drive is grounded.
169
7.3. Circuit Repair
Note here that the word repair was not used in any section of our analysis up till
now. Repair is the replacing of a part, resetting an adjustment, or restoring a
connection in a system that has gone through the process of troubleshooting.
Repair is made once the trouble has been found and verified. Isolating the faulty
component will always take a lot longer than repairing the circuit once the
problem has been found. Some repairs are simple such as replacing a cable,
removing a solder bridge from a PCB, reseating a connector or adjusting a
variable resistor. In most instances, however, the repair will involve replacing a
component such as an integrated circuit, a transistor, diode, resistor or
capacitor. This will mean that you will need to use the soldering iron to remove
the component from the PCB. When soldering and desoldering components to
and from a PCB, always remember the following points:
(a) Make a note of the component's orientation in the PCB since certain
components such as ICs, diodes, transistors, and electrolytic capacitor
have; to be correctly oriented.
(b) When desoldering components, use either a vacuum bulb or solder wick
to remove the solder.
(c) Be extremely careful not to overheat the PCB or the component being
soldered or desoldered.
(d) Avoid using too much or too little solder because this may cause
additional problems.
(e) Use a grounded soldering iron and a grounded strap when working with
MOS devices to prevent any damage to the IC from static discharge.
Once the equipment has been repaired, always "final test" the equipment
to see if it is now fully operational. Check that the system operates correctly in all
aspects, especially in the area that was previously malfunctioning and then
reassemble the system.
7.3.1. Internal IC Opens
An internal open gate input or an open gate output are very common internal IC
failures. These failures are generally caused by the very thin wires connecting
the IC to the pins of the package becoming loose or burning out due to
excessive values of current or voltage.
Figure 7.5 illustrates how a logic probe .and logic pulser can be used to
isolate an internal open NAND gate input In fig. 7.5 (a), the open input or pin 10
170
has been jumper connected to V cc and the other gate input (pin 9) is being
driven by the logic pulser. As you know any low input to a NAND gate will
produce a high output and only when both inputs are high will the output be low
as shown in the inset of fig. 7.5 (a). The logic probe which is monitoring the gate
on pin 8 indicates that a negative going pulse waveform is present at the output
and therefore the gate seems to be functioning normally. When the jumpers
and pulsers inputs are reversed as shown in fig. 7.5 (b), the output remains
permanently low. These conditions could only occur if the pin 10 input was
permanently high. Recall that an open or floating input is equivalent to high
input. The cause therefore must be either an internal open at pin 10 (since this is
equivalent to a high input) or a Vcc short to the pin 10 input of this gate. In either
case, the logic gate IC has an internal failure and will have to be replaced.
.
Figure 7.5. an Internal Open Gate Input
Figure 7.6 shows how a logic pulser and logic probe can be used to
isolate an internal open gate output. In fig. 7.6 (a), the logic gate's input at pin 10
has been jumper connected to V cc and the other input at pin 9 is being driven by
the logic pulser. The logic probe which is monitoring the output on pint 8 has
171
Open pin 10
Input produces
an equivalent
HI inputs to
gate
(10) (9) (8)
0
0
1
1
0
0
1
1 0
1
1
1
IC Pins
NAND
Logic Probe
Logic Pulser
(a)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7400-TTL
+V
cc
HI
LO
(b)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7400-TTL
+V
cc
HI
HI
LO
Figure 7.6. an Internal Open Gate Output
None of its indicator LEDs ON. This indicates that the logic level is neither a
valid logic 1 or a valid logic 0 (line is' probably floating). In fig. 7.6 (b), the inputs
have been reversed, however, the logic probe is still indicating the same effect.
This test highlights the failure which is an open gate output. Once again the logic
gate IC will have to be replaced.
(b) Internal IC Shorts
Internal logic gate shorts to either Vcc or ground will cause the inputs or output to
be stuck either high or low. These internal shorts are sometimes difficult to
172
(10) (9) (8)
0
0
1
1
0
0
1
1 0
0
0
0
IC Pins
NAND
Logic Probe
Logic Pulser
(a)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7400-TTL
+V
cc
HI
LO
(b)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
7400-TTL
+V
cc
HI
LO
Low
High
High
Low
+V
CC
+V
CC
A
B
(a)
Low
High
+V
CC
A
Low
+V
CC
(b)
B
Low
Figure 7.7 Internal Open Gate Input
isolate. Figure 7.7 (a) shows the effect an internal input lead short to ground will
have on a digital logic gate circuit. The input to gate B is shorted to ground thus
this input is being pulled down. This low between A output and B input makes it
appear as though gate A is malfunctioning since it has two high inputs and
therefore should be producing a high output. The problem is solved by
disconnecting gate A from gate B. Since gate A's output will go high when it is no
longer being pulled down by gate B, the fault will be isolated to a short at the
input of gate B. In fig. 7.7 (b), the output of gate A has shorted to Vcc' This circuit
condition gives the impression that gate A is malfunctioning however, if the B
gate input had shorted to Vcc we should get the same symptoms. Once again,
we will have to isolate by disconnecting the A output from the B input to
determine which gate is faulty.
173
Chapter VI Question
1(a). What are the pre-reqiusites of good trouble shooting
(b). Trouble shooting is isolating a fault using electronic principles. Explain

2. Mention and explain briefly the order of steps required for fault finding
any equipment.
3(a). Differentiate between "trouble shooting" and "repair"
(b) Explain briefly how to troubleshooting a logic circuit using the logic
probe
(4). For a suspected faulty logic circuit, what are the three basic steps to
take for effective troubleshooting
5. Explain the five procedures involved in troubleshooting a faulty
computer.
6 (a). What is the disadvantage of touching in the computer circuitry when
done carelessly.
(b). Enumerate four observation done by touching.
7 (a) What is the disadvantage of the cooling fan failure in a computer
system
(b) Enumerate the problems associated with power supply in a computer
system.
8 Explain the hard disk/drive failures in a computer system.
9. What could be the possible fault in the circuit shown below;
174
Low
A
B
1/6 of a 7404
1/4 of a 7400
1
2
REFERENCES
1. M. C Scroggie
Foundations of wireless and Electronics, Tent Edition, ELBS, 1984.
2. DC Green
Electronic III 3rd Edition, ELBS/LONGMAN, 1985.
3. Vernon John
Introduction to Engineering Materials 3rd Edition Palgrave, 1992.
4. Fredrick J. Hill and Gerald R Peterson
Introduction to switching theory and logical design third Edition, John
Wiley and Sons 1981.
5. Ralph J. Smith
Circuit, Devices and Systems, Fourth Edition John Wiley & Sons,
1984.
6. RJMaddock and D.M Calcutt,
Electronics, A Course for Engineers, ELBS/Longman, 1989
7. S. A Knight
Electronics 3, Second Edition Butterworth Heinemann Ltd, 1989
8. T. J. Bayers
Electronic Test Equipment, Principles and Applications.
Mc Graw-Hill Book Company 1987.

9. Thorn Luce
Computer Hardware, System Software, and Architecture Me Graw-Hill
Inc,1989
10. R Meadow, A. J. Parsons
Micro processors: Essentials, Components and Systems
Pitman Publishing, 1988.
175
176
REFERENCES
177
REFERENCES
Appendix A1
The ASCII (American Standard Code for Information Interchange) code for
numbers, alphabet letters and other common symbols.
o
1
2
3
..
5
6
7
8
9
Other
symbols
:
;
<
=
>
?
Space
I
.
#
$
%
&
(
)
*
+
011 0000
0110001
0110010
011 0011
011 0100
0110101
011 0110
011 0111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
0100000
0100001 .
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
30
31
32
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
@
A (8)
B (b)
C (c)
D (d)
E (e)
F (f)
G (g)
H (h)
1 (i)
J (j)
K (k)
L (I)
M (m)
N (n)
o (0)
p (p)
Q (q)
R (r)
S (5)
T (t)
U (u)
V (v)
W (w)
X (x)
y (y)
Z (z)
[
\
]
100 0000
100 0001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
100111 0
1 001111
1010000
101 0001
1010010
1010011
1010100
1010101
1010110
1010111
101 1 000
1011001
1011010
101 1011
101 1100
101 1101
101 1110
1011111
41 (61)
42 (62)
43 (63)
44 (64)
45 (65)
46 (66)
47 (67)
48 (68)
49 (69)
4A (6A)
4B (6B)
4C (6C)
40 (6D)
4E C6E)
4F (6F)
50 (70)
51 (71)
52 (72)
53 (73)
54 (74)
55 (75)
56 . (76)
57 (77)
58 (78)
59 (79)
5A (7 A)
56
5C
5D
5E
5F
Decimal
numbers
ASCII code
in binary
ASCII code
in binary
Alphabetical
characters In hex In hex
178
Appendix A2
The ASCII code also includes the following control signal codes:
NUL
SOH
STX
EOT
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
SI
DLE
Dc1
Null
Start of heading
Start of text
End of text
End of tranSmission
Enquiry
Acknowledge
Bell (audio sound)
Backspace
Horizontal tabulation
Une feed
Vertical tabulation
Form feed
Carriage return
Shift out
Shift in
Data link escape
Device control 1
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
0001000
000 1001
0001010
000 1011
000 1100
000 1101
000 1110
0001111
001 0000
001 0001
Dc2
Dc3
Dc4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
DEL
Device control 2
Device control 3
Device control 4
Negative acknowl-
edge .
Synchronous idle
End of transm.
block
Cancel
End of medium
Substitute
Escape
File separator
Group separator
Record separator
Unit separator
Delete
001 0010
001 0011
001 0100
001 0101

0010110
0010111
0011000
0011001 .
0011010
0011011
0011100
0011101
0011110
0011111
1111111
The ASCII code is now very widely employed and is virtually the
international standard for data communication and storage.
Control signal
meaning
ASCII
code
Control signal
meaning
ASCII
code
179
14 13 12 11
10 9 8
V
CC
GND
7 6 5 4 3 2 1
PIN CONNECTION
TOP VIEW
Appendix B: Integrated Circuits
QUADRUPLE TWO-INPUT NAND GATE
GENERAL DESCRIPTION
Employing TTL(Transistor-Transistor-Logic) to achieve high speed at
moderate power dissipation, these gates provide the basic functions used in
the implementation of digital integrated circuit systems. Characteristics of the
circuits include high noise immunity, low output impedance, good capacitive
drive capability. And mini mal variation in switching times with temperature.
FEATURES
. GuaranteedNoiselmmunity400mV . Typical Noise Immunity IV
. Average Propagation Delay 13 ns . Fan Out 10
. Average Power Dissipation I0mW per gate
RS 7400
276-1801.
180
PIN CONNECTION
TOP VIEW
14 13 12 11 10 9 8
V
CC
GND
7 6 5 4 3 2 1
QUAD TWO-INPUT NOR GATE

GENERAL DESCRIPTION
The 7402 is a qual 2 -input NOR gate utilizing TTL. (Transistor-Transistor
Logic) to achieve high speed at nominal power dissipation.
FEATURES
. Input Clamping Diodes . Guaranteed Noise Immunity 400 m V
. Typical Noise Immunity IV Fan-out 10
. Allowable Power Supply Variation 4.7 5V to 5.25V
. Average Propagation Delay 12 ns(with50 pF)
. Average Power Dissipation 14mWpergate
RS 7402
276-1811
181
PIN CONNECTION
TOP VIEW
14 13 12 11 10 9 8
V
CC
GND
7 6 5 4 3 2 1

HEX INVERTER
GENERAL DESCRIPTION
The 7404 is a hex inverter utilizing TTL. Achieve high speed at nominal power
dissipation. It is totally compatible with other Series 74 devices.
FEATURES
.Input clamping diodes Guaranteed NoiseImmunity400mV
Typical Noise Immunity IV . Fan-out 10
. Allowable Power Supply Variation 4. 7SV to S.2SV
Average Propagation Delay 12 ns (with SO pF)
Average Power4 Dissipation 10 m W per gate
RS 7404
276-1802
182
14 13 12 11 10 9 8
V
CC
GND
7 6 5 4 3 2 1
14 13 12 11 10 9 8
V
CC
GND
7 6 5 4 3 2 1
1A 1B 1Y 2A 2B 2Y
4B 4A 4Y 3B 3A 3Y
TOP VIEW
HEX INVERTER BUFFER/DRIVER
GENERAL DESCRIPTION
The TTL hex inverter buffer/driver is fully compatible for use with TTL and DTL
logic circuits: Each inverter features high-voltage, open-collector
outputs (30 volts mini!'lum breakdown.)
FEATURES
. Input clamp diodes 15 ns typical propagation delay time
High voltage open-collector outs 30V
Highsinkcurrentcapability40mA PIN CONNECTION
TOP VIEW
GENERAL DESCRIPTION
7408 provides the noninverting AND function in the popular quad 2-input
Pin configuration
PIN CONNECTION
RS 7410
276-1821
183
TRIPLE THREE- INPUT NAND GATE
GENERAL DESCRIPTION
Employing TTL (Transistor - T transistor-Logic) to achieve high speed at
moderate power dissipation, these gates provide the basic functions used in
the implementation of digital integrated circuit systems. Characteristics of the
circuits include high noise immunity, low output impedance, good capacitive
drive capability, and minimal variation in switching times with temperature.
FEATURES
. Typical Noise Immunity 1 V
. Guaranteed Noise Immunity 400 m V
. Fan Out 10
. Average Propagation Delay 13 ns
. Average Power Dissipation 10m W per gate
RS 7406
276-1807
PIN CONNECTION
TOP VIEW
14 13 12 11 10 9 8
V
CC
GND
7 6 5 4 3 2 1
Dual-in-Line Package
184
PIN CONNECTION
TOP VIEW
14 13 12 11 10 9 8
7 6 5 4 3 2 1
V
CC
2
CLEAR
2
CLOCK
2
PRESET
2D
2Q 2Q
1 1D 1 1 1Q
1Q
GND CLEAR CLOCK PRESET
POSITIVE LOGIC
Low Input to preset sets Q to logical 1
Low input to clear sets Q to logical 0
Preset and clear are independent of clock
TRUTH TABLE (Each Flip-Flop)
t
n
t
n +1
INPUT OUTPUT OUTPUT
D
0
1
Q
0
1
Q
0
1
NOTES: 1. t =bit time before clock pulse.
n
2. t =bit time after clock pulse.
n

DUAL D FLIP FLOP
GENERAL DESCRIPTION
The 7474 is designed for use where the flexibility of 2 inputs is not required. It
has only a single DATA (D) input. The logical level applied to this input is
transferred to the Q out put when the clock pulse voltage rises to a logical I.
Since only one pin is used for data entry, fully asynchronous (both PRESET and
CLEAR) capability can be provided in a 14 pin dual-in- line package.
RS 7474
276-1818
185
PIN CONNECTION
TOP VIEW
16 15 14 13 12 11 10 9
Q1 Q2 Q2 12 GNDQ3 Q3
1 2 3 4 5 6 7 8
ENABLE
Q1 D1 D2 ENABLE V
CCD3 D4 Q4
TO
OTHER
LATCH
Q
LOGIC DIAGRAM (Each Latch)
ENABLE DATA
Q
TRUTH TABLE (Each Latch)
INPUT
D
OUTPUT
G Q
Q
L
H
X
H
H
L
L
H
Q0
L
H
Q0
H = High level, L = Low level, x = Dont Care
Q0 = The level of Q Before the High -to-
Low Transition of G
INTEGRATED CIRCUITS
QUAD LATCH

GENERAL DESCRIPTION
This latch is ideally suited for use as temporary storage for binary information
bot ween processing units and input/output or indicator unity. Information
present at a data (D) input is transferred to the Q output when the enable (0) is
high, and the Q output will follow the data input as long as the enable remains
high. When the enable goes low, the information (that was present at the data
input at the time the transition occurred) is retained at the Q output unity the
enable is permitted to go high. The 7475, features complementary Q and Q -
outputs from a 4-bit latch, and are available in 16-pin packages.
RS.7475
276-1806
186
INTEGRATED CIRCUITS
DECADE, DIVIDE BY 12, AND BINARY COUNTER
GENERAL DESCRIPTION
This monolithic counter contains four master-slave nip flops and additional
gating to provide a divide-hy-two counter and a three-stage binary counter for
which the count cycle length is divide by six.
This counter has a gated zero reset.
To use maximum count length (decade, divide-by-twel ve, or four- bit binary),
the B input is connected to the Q output. The input count pulses are Applied to
A
input A and the outputs are as described in the appropriate truth
Table
TRUTH TABLES
COUNT SEQUENCE (See Note A)
COUNT
OUTPUT
QD QC QB QA
0
1
2
3
4
5
6
7
8
9
10
11
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
RESET/COUNT TRUTH TABLE
RESET INPUT OUTPUT
QD QCQB QA RO (1) RO (2)
H H L L L L
COUNT
COUNT
L X
L X
PIN CONNECTION
TOP VIEW
INPUT
A NC QA QB GND QO QD
INPUT NC NC NC VccRo(1) Ro(2)
14 13 12 11 10 9 8
7 6 5 4 3 2 1
B
187
Index
A
acceptor, 31
ACT, 116, 120
activated, 124, 130
addend, 3-4
adding, 5, 14, 16, 18, 20, 22, 31, 78-79, 102, 145
algebra, 1, 53, 68, 72-74, 83, 98
algebraic, 68, 74, 91-94, 98
algorithms, 22
allowed, 88, 130
Alphanumeric, 16, 25
ammeter, 133, 139, 152
amperes, 135
amplification, 108
amplified, 105, 152
amplifier, 47, 137
amplifiers, 44, 108
amplitude, 142, 146, 148-150
analogue, 137, 141, 152
analysis, 70-71, 109, 153-154, 170
analyzer, 153-154
analyzers, 133, 153-154
anode, 31, 143-144
ANSI, 65
application, 22, 69, 133, 153, 161
applications, 1, 25, 32, 62
Aquadag, 144
arithmetic, 1, 6, 14-18, 30, 56, 68
array, 83-84, 102-103
ASCII, 16, 25-26, 30
associative, 72-73
augend, 3-4
augmented, 78-79
B
bandwidth, 149
battery, 136, 141, 169
BCD, 16-19, 26
bias, 48, 123
biases, 34, 37, 41
binary, 1-6, 8-10, 13-25, 28, 30, 34, 72, 84, 96, 113,
154-155
bipolar, 38, 99, 119
bit, 25
Boolean, 1, 22, 53-57, 63, 66, 68-74, 76, 78-79, 81,
83, 86-87, 89, 92-93, 95, 98, 113
bracketing, 93
buffer, 38, 54, 113, 125-126, 129
buffered, 54, 115
byte, 2-3, 25
C
cable, 158, 166, 170
calibrated, 133, 137
canonical, 68-69, 76
capacitance, 108, 141
capacitor, 136-137, 141-142, 162, 170
capacitors, 43, 100, 122, 136, 141-142
carriers, 50, 122-123
cathode, 31, 142-144
cell, 81-85, 87-88
cells, 83-84, 86-88
Index
ceramic, 99-100, 102, 104, 115
ceramics, 100
chip, 99, 102-104, 119-120
chips, 102, 104
circuit, 2, 34-35, 37-38, 43-44, 46, 48, 51-54, 58, 67,
69, 99-100, 102-111, 113-114, 122-123, 126-127,
130, 132, 135-136, 139-143, 145-146, 149,
151-152, 154-158, 161-165, 169-170, 173-174
circuitry, 4, 100, 133, 136, 164, 174
circuits, 16, 52, 54, 56, 83, 99, 104, 118-119, 124,
126, 130, 135, 137, 140, 142, 154, 161-162, 169
Clip, 136, 152, 154
clip, 133, 152, 154-155
CMOS, 104, 106, 114, 118-120, 124-130, 151,
155-156
code, 16-28, 30, 83, 96, 115, 132
Coded, 17, 25
coded, 16-17, 25, 30, 71, 96
codes, 1, 16-22, 25-28, 30, 97, 111
coding, 16-17
coil, 133-134, 136, 140-141
coils, 136, 144
collector, 32, 38, 41, 43, 110-113, 123
column, 3, 10, 25-26, 60, 78, 84, 86, 88-89
columns, 25, 81, 91
combination, 1, 12, 16-18, 34, 37, 58, 60, 68-69, 83,
97, 165
combinational, 51-52, 165
combinations, 52, 59, 71, 81, 92
commutative, 72-73
compatible, 70, 103, 118, 120, 124, 126, 128-129
complement, 15-16, 18-19, 27, 30, 41, 73, 75
Complementary, 104, 118
complemented, 81
complements, 30
components, 1, 43-44, 99, 104, 106, 122, 124, 133,
136, 157, 161, 168, 170
computer, 1, 3, 6, 14, 25-26, 51, 68, 133, 166, 168, 174
computers, 1, 3, 18, 22, 25-26, 51
conduct, 31, 35, 109-110, 112
conducting, 107-108, 110, 143, 156, 158
conduction, 31, 50
conductor, 114, 139, 152, 157
configuration, 32, 50, 112, 121-123, 140
configurations, 106, 114, 121, 137
connected, 31, 38, 53, 58, 102, 104-105, 112-113, 123,
126, 130, 135, 139-140, 143-144, 151, 154-155,
164, 171
connection, 68, 99-100, 112-113, 122, 140, 152, 161,
163, 166, 170
connections, 99-100, 102, 104, 114, 154, 164
connectors, 167, 169
constructed, 78-79, 104
construction, 78-79, 104, 119, 143
Constructional, 134
consumption, 22, 99, 111
controllers, 104
converter, 16, 137-138
cooling, 168, 174
coordinates, 89, 92-93
core, 115, 134
coupled, 104, 106, 145
coupling, 145
CPU, 167
crept, 26
critical, 38, 126
crt, 142-143
Cutoff, 109
cutoff, 108-109
cycle, 28, 144, 146, 148-150
cyclic, 20, 22, 28
cylindrical, 100, 143
D
data, 2, 16, 20, 25-28, 65, 69-70, 114, 116, 130,
153-154, 161, 163, 169
DCTL, 46, 106
debounce, 124
Decibel, 137
decoders, 69, 104
deflection, 134-137, 144
deflector, 143-144
DeMorgan, 73
detect, 26-28, 151, 153, 156, 169
detected, 26-27, 31, 152, 166-167
detecting, 83, 155-156
detection, 16, 26-28, 155, 166
device, 31, 54, 70, 102, 105, 107, 113, 151, 162-163
devices, 1, 22, 99, 101, 104, 113-114, 117, 122, 124,
133, 162, 168, 170
diagnostic, 169
diagram, 35-37, 46, 49-50, 55, 62, 64, 89, 113-114,
135, 137-138, 151, 163
diagrams, 42, 116, 121, 153, 163
diameter, 99
digit, 1-2, 4, 8-10, 14, 16-19, 138-139, 153
digital, 1-2, 4, 6, 16-19, 22, 26, 51, 53, 55, 99, 101,
104, 106, 110, 114-115, 124, 129-130, 132, 137,
146, 151-155, 163-164, 173
digits, 1-3, 8-10, 12, 14, 17-19, 25-26, 97, 138
dimensional, 91, 102-103
diode, 31-32, 34-38, 48, 50, 107-109, 122-124, 132,
137, 170
diodes, 35, 38, 42, 44, 47-48, 99-100, 107-108,
122-123, 154, 170
DIP, 100-103, 115
disk, 166, 168-169, 174
display, 137-138, 145-146, 152, 154, 166
displayed, 14, 139-140, 144-145, 153, 169
Index
displays, 137, 142, 153
dissipation, 105-106, 111, 118-119, 122
distortions, 146
Distribution, 72
distributive, 72-73, 75, 77
dividend, 5-6, 28
division, 5-6, 28, 142, 144
divisions, 9, 142, 144
divisor, 5-6, 28
DMM, 137-139
domain, 153
donor, 31
donors, 31
dormant, 119
dot, 53, 100, 144
driver, 126-127
drivers, 126
DTL, 47, 106, 108-110
dual, 74, 100-101, 104, 111, 115, 137
duality, 68, 98
E
EBCDIC, 25-26, 30
ECL, 104, 118-120, 155
electricity, 31, 115
electrolytic, 136, 162, 170
electron, 31, 122, 143-144
electrons, 31-32, 122, 143
electrostatic, 167
emitter, 32, 37-38, 41, 50, 110-111
emitting, 124, 137, 154
enabled, 113, 156
encode, 20, 29, 97
encoding, 20, 169
energy, 31, 99, 122
engineers, 69
equipment, 2, 25, 136, 142, 146, 153, 161-163, 170,
174
error, 16, 20, 26-28, 139, 169
errors, 22, 26-28, 168
ESD, 167
experiments, 124
exponent, 14
expression, 14, 53-57, 59, 66, 68-71, 73-78, 81, 83,
91-98, 113
expressions, 22, 63, 68-71, 74-78, 87, 89, 92, 98
F
fabricating, 99-100
fairly, 75
fan, 100, 105, 108, 116, 118-119, 122, 132, 168, 174
fault, 151, 153-154, 161-166, 173-174
faulty, 153-154, 161-166, 170, 173-174
FCT, 116
Features, 43-44, 46-48, 69, 134
fiberglass, 102
Flicker, 166
frequency, 120, 144, 146, 149-150
functional, 65, 111, 162-163, 169
functioning, 119, 165-167, 169, 171
G
gain, 33, 54
gate, 34-38, 41-42, 48, 50-58, 62, 64-66, 96, 98,
104-105, 108-115, 118-119, 121-122, 130, 146,
151-152, 164-166, 170-173
generate, 20
generated, 9, 15, 28, 145, 157
generates, 118
generation, 28, 156
generator, 139, 149
Germanium, 31, 43-44, 46, 48
GND, 121, 128-130, 145, 155, 164-165
graphical, 22, 81, 113
graphite, 143
graticules, 146
grid, 84-85, 100, 102-103, 143
grouping, 25, 86-87, 89
H
Hades, 117
Hamming, 28
hardware, 68, 75
HC, 116, 120
HCT, 116
hertz, 150
hex, 10, 12, 30
hexadecimal, 10, 12-13, 30
holes, 25-26, 31-32, 103
Index
Hollerith, 25-26
horizontally, 144-145
I
IBM, 25
IC, 99-100, 102, 104, 106, 114-115, 121, 124, 126,
129, 132, 151-152, 154, 157, 163-166, 170-172
ICs, 100-104, 106, 108, 124, 126, 170
Idempotent, 74, 76
identification, 65, 114-115
identities, 74, 86
identity, 68, 72-73, 75, 77
IEC, 65
IEEE, 65-66
IM, 117
immunity, 105, 118-119
impairments, 26
impedance, 33, 47, 113, 118
implementation, 69
implementations, 98
implemented, 75, 111
implicants, 70
Implication, 70
impurities, 31
IN, 46
indicator, 124, 126-127, 132, 151-152, 164, 172
indicators, 124, 126
inductor, 140-141
infinite, 107, 113, 140, 142
infinity, 136, 141
information, 16, 26-28, 113, 116, 129-130, 132, 135,
142, 153-154, 162, 165
input, 6, 17, 33-36, 38, 41, 43, 48, 51-54, 57-59, 62,
64, 66, 68, 81, 83-85, 89-91, 96-98, 104-105,
107-111, 113-115, 122, 126, 128-130, 132,
145-146, 148, 152, 157, 162-165, 170-171, 173
inputs, 34-35, 37-38, 43, 51-54, 56-59, 61-63, 68, 72,
81, 83-85, 96-98, 104, 109, 112, 116, 126, 128-130,
145, 153, 165, 171-173
insulators, 31
integer, 29, 93
integers, 20
integrated, 99, 103-104, 170
integrating, 137
integration, 99, 102, 104, 132
Intel, 102, 117
interface, 54, 124, 128, 130-131
Interfacing, 124, 126-130, 132
internally, 18, 25, 142, 145
inverted, 37, 43-44, 47, 55-56
inverter, 41, 54, 98, 104, 110, 113, 124, 126, 129-130
inverters, 96
inverting, 55, 125-126, 129, 145
J
junction, 31-32, 37-38, 41, 50, 99, 110-112, 119,
122-123
K
Karnaugh, 22, 81, 83, 87, 89, 92, 95
keyboard, 129-130, 132, 166-167
kmap, 82, 86, 89-90
Kmaps, 81
L
LCDs, 137
LED, 124-127, 152, 154, 156, 165
LEDs, 124, 126-127, 137, 154-155, 172
logic, 1, 34-35, 37-38, 42, 44, 46-48, 50-56, 58-59, 62,
65-68, 76, 91, 98-99, 101-102, 104-105, 107-114,
116, 118-120, 122, 124, 126-127, 130, 132-133,
146, 151-158, 163-165, 170-174
logical, 43, 69, 71-73, 83, 104, 152, 161-162
logically, 70-73
LS, 111, 115-116, 120, 129-130
LSB, 3, 17, 20, 22
LSI, 102, 104, 118
M
mA, 122, 124, 128, 131, 135, 159
magnet, 133-135
magnetic, 27, 133-134, 152, 157
magnitude, 2, 14-15, 30, 152
Mainframe, 3
maintenance, 142
majority, 27, 92, 101, 122
Index
malfunctioning, 161, 163, 170, 173
mantissa, 14
manufacturer, 111, 115, 138
manufacturers, 100-101, 107, 115-117, 122, 132
map, 81-84, 86-87, 89, 91-96
maps, 22, 81, 83, 87, 92
margin, 105, 118-119, 132
mathematical, 68, 72
matrix, 69
maximum, 17-18, 20, 76, 122, 124, 138
Maxterms, 75
measurement, 133, 137, 145-146, 148, 162-163, 167
measurements, 137, 139, 162-163, 167-168
Measuring, 133, 139-140
mechanical, 100, 102, 166
metal, 99-100, 102-104, 114, 122-123, 136
meter, 99, 133-136, 138-142, 152, 159
meters, 133-134
MHz, 120, 149
micro, 135, 144, 152
microcomputer, 130, 132
microcomputers, 25, 129
micrometer, 99
microprocessor, 3, 114, 153
microprocessors, 3, 104, 122, 153
milliameter, 136
milliseconds, 144, 152
miniaturization, 46
minimising, 89
minimization, 22, 70-71, 92-94
minimize, 43, 102
minimized, 70, 83, 91, 97
minimum, 1, 25, 102, 105, 122
minority, 50
minterm, 78, 81, 83
minterms, 68, 78, 81, 83-84
minuend, 4, 10
MM, 111, 117
Mnemonic, 111
mode, 145, 165
modules, 104
monitor, 146, 166
Monolithic, 117
MOS, 104, 118, 120, 170
motherboard, 169
Motorola, 117
MSB, 3, 14-15, 17, 20-24
MSI, 102, 104, 118
multimeter, 133, 135, 137, 139-141, 154-155
multimeters, 137, 142
multiplexer, 83
multiplexers, 104
Multiplicand, 5
multiplication, 3, 5-6, 69
Multiplier, 5
mV, 138
mW, 106, 111
N
NAND, 37, 52, 55, 58, 65-66, 68, 89, 104-105,
108-114, 146, 165, 170-172
nano, 119
network, 58-60, 133
nibble, 2-3
nibbles, 2
node, 151, 153, 164
nodes, 153, 164-165
noise, 26, 105, 118-120
noninverting, 125
nonredundant, 76
Nonweighted, 18
nonzero, 28
notation, 12, 14, 65
NPN, 32, 50, 123, 127
nucleus, 31
numerals, 1
O
octal, 1, 6, 8-10
ohm, 134-135, 140-141
ohmmeter, 133, 136, 140-141
ohms, 107, 135, 137, 139-141
operands, 72
operator, 69, 72-73, 156-157
operators, 68-69, 72-74
orbits, 31
ORed, 56, 76
ORing, 73
oscilloscope, 133, 142-143, 145-146, 149, 153-156
output, 6, 17, 32-38, 41-44, 47, 51-52, 54-56, 58, 62,
64, 70, 72, 78-79, 83-84, 92, 96-97, 105, 109-115,
118, 122, 124, 126-128, 146, 151-152, 157-158,
163-166, 170-173
outputs, 51, 55, 81, 98, 104, 112-113, 122, 126, 128,
165
overlap, 85, 88, 94
overlapping, 88
oxide, 99, 104, 114
Index
P
package, 99-104, 111, 114-115, 154, 170
packages, 100-103
packaging, 100, 103, 115-116
packing, 119-120
panel, 133-137, 140, 142, 144
parameters, 105, 146, 148
parenthesis, 14, 73
parity, 25-30, 168
pattern, 10, 12, 20, 100
patterns, 83, 94
PC, 163-165, 168
PCB, 158, 170
PGA, 102-103
phase, 70-71
PN, 32, 50
PNP, 127
pointer, 133-134, 136, 141, 159
polarity, 123, 136-137, 152
pole, 110, 113
poles, 133-134
POS, 79
postulates, 68, 72-74
precision, 14
predetermined, 27
prefix, 115
PRF, 149-150
primitive, 65-66, 70-71
principle, 68, 74, 98, 152
principles, 133, 161, 174
printed, 152, 158, 164-165
probability, 28
probe, 126-127, 133, 136, 145, 148, 151, 153-158,
163-165, 170-172, 174
probes, 126, 136, 140-141, 145, 152-153, 155, 157
procedure, 83, 163, 166-167
procedures, 166, 174
processor, 3
processors, 104
profiles, 126, 128
programmable, 104
propagate, 105
propagation, 105, 108, 111, 119-120, 146-147
proximity, 31
pulse, 35, 146, 148-152, 155-157, 171
pulser, 133, 152-153, 156-158, 170-171
pulsers, 171
pulses, 34, 137, 150-151, 155-157
Pw, 150
Q
quad, 114
quadruple, 115
quotient, 6
R
radix, 1, 4, 6, 10, 15, 30
rectangular, 65, 85, 91, 99, 134
redundancy, 28, 77, 83
registers, 69, 104
relays, 124
repetition, 27-28, 149-150
repetitive, 20, 27
resistance, 35, 37, 107, 113, 119, 133, 135-136,
140-142, 145, 163
Resistive, 144
resistor, 35, 38, 48, 108, 111-112, 124, 126, 128-131,
141, 170
resistors, 38, 43, 48, 100, 106, 119, 124, 162
resolution, 166
response, 35, 41, 51, 108, 137, 142
Restorer, 38, 40
RTCL, 43
RTL, 41-43, 108
S
Schematic, 108
Schottky, 110-111, 116, 118, 122-123
scope, 144, 149
screen, 140, 142-145, 149, 169
semiconductor, 31, 50, 99-100, 102, 104, 107,
122-123, 152
semiconductors, 31, 99
sensitivity, 134-135, 157
sequential, 51, 161
signal, 34-36, 52-53, 105, 137, 142, 145-146, 149,
153-157, 162-163
signals, 16, 22, 34, 38, 102, 105, 107-108, 142,
145-146, 153, 155-156
signature, 133, 153-154
signed, 14-15
Signetics, 117
Index
simplification, 74, 87, 91
SN, 115, 117
software, 68-69
SOIC, 103
SOICs, 103
soldering, 103, 170
solenoids, 124
SOP, 78-79
spec, 111
specifications, 111, 122
SS, 125, 128-130
SSI, 102, 104
subfamily, 116
subscripts, 78-79
subtraction, 4, 6, 9-10, 18-19
subtrahend, 4, 10
Suffix, 115
sum, 3-4, 9, 16, 19, 51, 68, 73, 76, 78
sums, 75-76
surface, 103, 169
switching, 43, 46, 48, 51-52, 62, 75, 118, 123-124, 132
symbol, 52-56, 65-66, 72-73, 112-113, 123
symbols, 1, 10, 25, 65-66
synchronization, 145
T
TDL, 48
techniques, 6, 148
technologies, 100, 102
technology, 99, 102, 104, 108, 110-111, 119
temperature, 43, 111, 118, 168
testing, 100, 136, 153-155, 157, 162, 164
Theorem, 73-74
theorems, 68, 72-74
theoretical, 1, 161
timing, 62, 64, 146, 153-154
totem, 113
tracer, 133, 152-153, 157-158
tracing, 157-158
transformations, 98
transformer, 166
transient, 118
Transistor, 38, 41-43, 46-47, 104, 106, 108-110, 137
transistor, 32, 36-38, 41-42, 46-47, 50, 99, 104,
108-109, 112, 123, 126-127, 132, 170
transistors, 43, 46, 99-100, 112-113, 118-119, 170
transition, 26, 105, 108, 149
transmission, 22, 26-27
transmit, 113
transmitted, 27-28
transmitter, 26
trigger, 145, 153-154
triggering, 67, 145-146
Triode, 144
troubleshoot, 142, 157, 161, 166
troubleshooting, 154, 161-163, 165-166, 169-170, 174
truth, 34-35, 50, 52-62, 64, 66, 68-70, 78-79, 81-84,
89-90, 92-93, 97-98
TTL, 38, 104, 106, 108, 110-112, 114-116, 118, 120,
122-131, 151, 155-156, 164-165, 171-172
tube, 142-144
Tunnel, 48-49
V
valence, 31
valve, 99
VAR, 145
variation, 118, 122, 142
variations, 100-102, 137
VBE, 41
Vcc, 32, 41-42, 45-47, 49, 171-173
VDD, 125, 128
versa, 6
versions, 69, 110, 118
VLSI, 102, 104, 118-119
volt, 41, 134-135, 144-145
voltage, 31-35, 37-38, 41, 47-48, 62, 105-109,
118-120, 122-126, 128-130, 132-133, 136-137,
139-140, 142, 145, 149, 152-153, 155-158,
161-164, 166-170
voltages, 46, 107, 118, 124, 126, 167
voltmeter, 133, 136, 140
volts, 107, 118, 144
W
wafer, 100
watts, 119
waveform, 142, 144-146, 149, 153, 163, 171
waveforms, 62, 142, 150
Waver, 166
Index
X
xed, 18, 68
xl, 145
xlM, 141
XNOR, 56-57, 66
XOR, 56-57, 66
xy, 74-77, 81-83
Z
zero, 1-2, 5, 15, 34-35, 37-38, 72-73, 78-79, 91, 122,
141, 144, 151

A, 135
Index
A
acceptor, 31
ACT, 116, 120
activated, 124, 130
addend, 3-4
adding, 5, 14, 16, 18, 20, 22, 31, 78-79, 102, 145
algebra, 1, 53, 68, 72-74, 83, 98
algebraic, 68, 74, 91-94, 98
algorithms, 22
allowed, 88, 130
ammeter, 133, 139, 152
amperes, 135
amplification, 108
amplified, 105, 152
amplifier, 47, 137
amplifiers, 44, 108
amplitude, 142, 146, 148-150
analogue, 137, 141, 152
analysis, 70-71, 109, 153-154, 170
analyzer, 153-154
analyzers, 133, 153-154
anode, 31, 143-144
ANSI, 65
application, 22, 69, 133, 153, 161
Aquadag, 144
arithmetic, 1, 6, 14-18, 30, 56, 68
array, 83-84, 102-103
ASCII, 16, 25-26, 30
associative, 72-73
augend, 3-4
augmented, 78-79
B
bandwidth, 149
battery, 136, 141, 169
BCD, 16-19, 26
bias, 48, 123
biases, 34, 37, 41
binary, 1-6, 8-10, 13-25, 28, 30, 34, 72, 84, 96, 113,
154-155
bipolar, 38, 99, 119
bit, 25
Boolean, 1, 22, 53-57, 63, 66, 68-74, 76, 78-79, 81,
83, 86-87, 89, 92-93, 95, 98, 113
bracketing, 93
buffer, 38, 54, 113, 125-126, 129
buffered, 54, 115
byte, 2-3, 25
C
cable, 158, 166, 170
capacitor, 136-137, 141-142, 162, 170
capacitors, 43, 100, 122, 136, 141-142
carriers, 50, 122-123
cathode, 31, 142-144
cell, 81-85, 87-88
cells, 83-84, 86-88
Index
ceramic, 99-100, 102, 104, 115
ceramics, 100
chip, 99, 102-104, 119-120
chips, 102, 104
circuit, 2, 34-35, 37-38, 43-44, 46, 48, 51-54, 58, 67,
69, 99-100, 102-111, 113-114, 122-123, 126-127,
130, 132, 135-136, 139-143, 145-146, 149,
151-152, 154-158, 161-165, 169-170, 173-174
circuitry, 4, 100, 133, 136, 164, 174
circuits, 16, 52, 54, 56, 83, 99, 104, 118-119, 124,
126, 130, 135, 137, 140, 142, 154, 161-162, 169
Clip, 136, 152, 154
clip, 133, 152, 154-155
CMOS, 104, 106, 114, 118-120, 124-130, 151,
155-156
code, 16-28, 30, 83, 96, 115, 132
Coded, 17, 25
coded, 16-17, 25, 30, 71, 96
codes, 1, 16-22, 25-28, 30, 97, 111
coding, 16-17
coil, 133-134, 136, 140-141
coils, 136, 144
collector, 32, 38, 41, 43, 110-113, 123
column, 3, 10, 25-26, 60, 78, 84, 86, 88-89
columns, 25, 81, 91
combination, 1, 12, 16-18, 34, 37, 58, 60, 68-69, 83,
97, 165
combinations, 52, 59, 71, 81, 92
commutative, 72-73
compatible, 70, 103, 118, 120, 124, 126, 128-129
complement, 15-16, 18-19, 27, 30, 41, 73, 75
complemented, 81
complements, 30
components, 1, 43-44, 99, 104, 106, 122, 124, 133,
136, 157, 161, 168, 170
computer, 1, 3, 6, 14, 25-26, 51, 68, 133, 166, 168, 174
computers, 1, 3, 18, 22, 25-26, 51
conduct, 31, 35, 109-110, 112
conducting, 107-108, 110, 143, 156, 158
conduction, 31, 50
conductor, 114, 139, 152, 157
configuration, 32, 50, 112, 121-123, 140
connected, 31, 38, 53, 58, 102, 104-105, 112-113, 123,
126, 130, 135, 139-140, 143-144, 151, 154-155,
164, 171
connection, 68, 99-100, 112-113, 122, 140, 152, 161,
163, 166, 170
connections, 99-100, 102, 104, 114, 154, 164
construction, 78-79, 104, 119, 143
Constructional, 134
controllers, 104
cooling, 168, 174
core, 115, 134
coupled, 104, 106, 145
coupling, 145
CPU, 167
crept, 26
critical, 38, 126
crt, 142-143
Cutoff, 109
cutoff, 108-109
cycle, 28, 144, 146, 148-150
cyclic, 20, 22, 28
D
data, 2, 16, 20, 25-28, 65, 69-70, 114, 116, 130,
153-154, 161, 163, 169
DCTL, 46, 106
debounce, 124
Decibel, 137
decoders, 69, 104
deflector, 143-144
DeMorgan, 73
detect, 26-28, 151, 153, 156, 169
detected, 26-27, 31, 152, 166-167
detection, 16, 26-28, 155, 166
device, 31, 54, 70, 102, 105, 107, 113, 151, 162-163
devices, 1, 22, 99, 101, 104, 113-114, 117, 122, 124,
133, 162, 168, 170
diagnostic, 169
diagram, 35-37, 46, 49-50, 55, 62, 64, 89, 113-114,
135, 137-138, 151, 163
diagrams, 42, 116, 121, 153, 163
diameter, 99
digit, 1-2, 4, 8-10, 14, 16-19, 138-139, 153
digital, 1-2, 4, 6, 16-19, 22, 26, 51, 53, 55, 99, 101,
104, 106, 110, 114-115, 124, 129-130, 132, 137,
146, 151-155, 163-164, 173
digits, 1-3, 8-10, 12, 14, 17-19, 25-26, 97, 138
diode, 31-32, 34-38, 48, 50, 107-109, 122-124, 132,
137, 170
diodes, 35, 38, 42, 44, 47-48, 99-100, 107-108,
122-123, 154, 170
DIP, 100-103, 115
disk, 166, 168-169, 174
display, 137-138, 145-146, 152, 154, 166
displayed, 14, 139-140, 144-145, 153, 169
Index
displays, 137, 142, 153
dissipation, 105-106, 111, 118-119, 122
distortions, 146
Distribution, 72
dividend, 5-6, 28
division, 5-6, 28, 142, 144
divisor, 5-6, 28
DMM, 137-139
domain, 153
donor, 31
donors, 31
dormant, 119
dot, 53, 100, 144
driver, 126-127
drivers, 126
DTL, 47, 106, 108-110
dual, 74, 100-101, 104, 111, 115, 137
duality, 68, 98
E
EBCDIC, 25-26, 30
ECL, 104, 118-120, 155
electron, 31, 122, 143-144
electrons, 31-32, 122, 143
electrostatic, 167
emitter, 32, 37-38, 41, 50, 110-111
emitting, 124, 137, 154
enabled, 113, 156
encode, 20, 29, 97
encoding, 20, 169
energy, 31, 99, 122
engineers, 69
equipment, 2, 25, 136, 142, 146, 153, 161-163, 170,
174
error, 16, 20, 26-28, 139, 169
errors, 22, 26-28, 168
ESD, 167
experiments, 124
exponent, 14
expression, 14, 53-57, 59, 66, 68-71, 73-78, 81, 83,
91-98, 113
expressions, 22, 63, 68-71, 74-78, 87, 89, 92, 98
F
fabricating, 99-100
fairly, 75
fan, 100, 105, 108, 116, 118-119, 122, 132, 168, 174
fault, 151, 153-154, 161-166, 173-174
faulty, 153-154, 161-166, 170, 173-174
FCT, 116
Features, 43-44, 46-48, 69, 134
fiberglass, 102
Flicker, 166
frequency, 120, 144, 146, 149-150
functional, 65, 111, 162-163, 169
functioning, 119, 165-167, 169, 171
G
gain, 33, 54
gate, 34-38, 41-42, 48, 50-58, 62, 64-66, 96, 98,
104-105, 108-115, 118-119, 121-122, 130, 146,
151-152, 164-166, 170-173
generate, 20
generated, 9, 15, 28, 145, 157
generates, 118
generation, 28, 156
generator, 139, 149
Germanium, 31, 43-44, 46, 48
GND, 121, 128-130, 145, 155, 164-165
graphite, 143
graticules, 146
grid, 84-85, 100, 102-103, 143
grouping, 25, 86-87, 89
H
Hades, 117
Hamming, 28
hardware, 68, 75
HC, 116, 120
HCT, 116
hertz, 150
hex, 10, 12, 30
holes, 25-26, 31-32, 103
Index
Hollerith, 25-26
I
IBM, 25
IC, 99-100, 102, 104, 106, 114-115, 121, 124, 126,
129, 132, 151-152, 154, 157, 163-166, 170-172
ICs, 100-104, 106, 108, 124, 126, 170
Idempotent, 74, 76
identities, 74, 86
identity, 68, 72-73, 75, 77
IEC, 65
IEEE, 65-66
IM, 117
immunity, 105, 118-119
impairments, 26
impedance, 33, 47, 113, 118
implementation, 69
implementations, 98
implicants, 70
Implication, 70
impurities, 31
IN, 46
indicator, 124, 126-127, 132, 151-152, 164, 172
inductor, 140-141
infinite, 107, 113, 140, 142
infinity, 136, 141
information, 16, 26-28, 113, 116, 129-130, 132, 135,
142, 153-154, 162, 165
input, 6, 17, 33-36, 38, 41, 43, 48, 51-54, 57-59, 62,
64, 66, 68, 81, 83-85, 89-91, 96-98, 104-105,
107-111, 113-115, 122, 126, 128-130, 132,
145-146, 148, 152, 157, 162-165, 170-171, 173
inputs, 34-35, 37-38, 43, 51-54, 56-59, 61-63, 68, 72,
81, 83-85, 96-98, 104, 109, 112, 116, 126, 128-130,
145, 153, 165, 171-173
insulators, 31
integer, 29, 93
integers, 20
integrated, 99, 103-104, 170
integrating, 137
integration, 99, 102, 104, 132
Intel, 102, 117
interface, 54, 124, 128, 130-131
Interfacing, 124, 126-130, 132
internally, 18, 25, 142, 145
inverted, 37, 43-44, 47, 55-56
inverter, 41, 54, 98, 104, 110, 113, 124, 126, 129-130
inverters, 96
inverting, 55, 125-126, 129, 145
J
junction, 31-32, 37-38, 41, 50, 99, 110-112, 119,
122-123
K
Karnaugh, 22, 81, 83, 87, 89, 92, 95
keyboard, 129-130, 132, 166-167
kmap, 82, 86, 89-90
Kmaps, 81
L
LCDs, 137
LED, 124-127, 152, 154, 156, 165
LEDs, 124, 126-127, 137, 154-155, 172
logic, 1, 34-35, 37-38, 42, 44, 46-48, 50-56, 58-59, 62,
65-68, 76, 91, 98-99, 101-102, 104-105, 107-114,
116, 118-120, 122, 124, 126-127, 130, 132-133,
146, 151-158, 163-165, 170-174
logical, 43, 69, 71-73, 83, 104, 152, 161-162
logically, 70-73
LS, 111, 115-116, 120, 129-130
LSB, 3, 17, 20, 22
LSI, 102, 104, 118
M
mA, 122, 124, 128, 131, 135, 159
magnet, 133-135
magnetic, 27, 133-134, 152, 157
magnitude, 2, 14-15, 30, 152
Mainframe, 3
maintenance, 142
majority, 27, 92, 101, 122
Index
mantissa, 14
manufacturers, 100-101, 107, 115-117, 122, 132
map, 81-84, 86-87, 89, 91-96
maps, 22, 81, 83, 87, 92
margin, 105, 118-119, 132
matrix, 69
maximum, 17-18, 20, 76, 122, 124, 138
Maxterms, 75
measurement, 133, 137, 145-146, 148, 162-163, 167
measurements, 137, 139, 162-163, 167-168
Measuring, 133, 139-140
metal, 99-100, 102-104, 114, 122-123, 136
meter, 99, 133-136, 138-142, 152, 159
meters, 133-134
MHz, 120, 149
micro, 135, 144, 152
micrometer, 99
milliameter, 136
miniaturization, 46
minimising, 89
minimize, 43, 102
minimized, 70, 83, 91, 97
minimum, 1, 25, 102, 105, 122
minority, 50
minterm, 78, 81, 83
minterms, 68, 78, 81, 83-84
minuend, 4, 10
MM, 111, 117
Mnemonic, 111
mode, 145, 165
modules, 104
monitor, 146, 166
Monolithic, 117
MOS, 104, 118, 120, 170
motherboard, 169
Motorola, 117
MSB, 3, 14-15, 17, 20-24
MSI, 102, 104, 118
multimeter, 133, 135, 137, 139-141, 154-155
multiplexer, 83
multiplexers, 104
Multiplicand, 5
Multiplier, 5
mV, 138
mW, 106, 111
N
NAND, 37, 52, 55, 58, 65-66, 68, 89, 104-105,
108-114, 146, 165, 170-172
nano, 119
network, 58-60, 133
nibble, 2-3
nibbles, 2
node, 151, 153, 164
nodes, 153, 164-165
noise, 26, 105, 118-120
noninverting, 125
nonredundant, 76
Nonweighted, 18
nonzero, 28
NPN, 32, 50, 123, 127
nucleus, 31
numerals, 1
O
octal, 1, 6, 8-10
ohm, 134-135, 140-141
ohmmeter, 133, 136, 140-141
ohms, 107, 135, 137, 139-141
operands, 72
operator, 69, 72-73, 156-157
operators, 68-69, 72-74
orbits, 31
ORed, 56, 76
ORing, 73
oscilloscope, 133, 142-143, 145-146, 149, 153-156
output, 6, 17, 32-38, 41-44, 47, 51-52, 54-56, 58, 62,
64, 70, 72, 78-79, 83-84, 92, 96-97, 105, 109-115,
118, 122, 124, 126-128, 146, 151-152, 157-158,
163-166, 170-173
outputs, 51, 55, 81, 98, 104, 112-113, 122, 126, 128,
165
overlap, 85, 88, 94
overlapping, 88
oxide, 99, 104, 114
Index
P
package, 99-104, 111, 114-115, 154, 170
packages, 100-103
packaging, 100, 103, 115-116
packing, 119-120
panel, 133-137, 140, 142, 144
parenthesis, 14, 73
parity, 25-30, 168
pattern, 10, 12, 20, 100
patterns, 83, 94
PC, 163-165, 168
PCB, 158, 170
PGA, 102-103
phase, 70-71
PN, 32, 50
PNP, 127
pointer, 133-134, 136, 141, 159
polarity, 123, 136-137, 152
pole, 110, 113
poles, 133-134
POS, 79
precision, 14
predetermined, 27
prefix, 115
PRF, 149-150
primitive, 65-66, 70-71
principle, 68, 74, 98, 152
printed, 152, 158, 164-165
probability, 28
probe, 126-127, 133, 136, 145, 148, 151, 153-158,
163-165, 170-172, 174
probes, 126, 136, 140-141, 145, 152-153, 155, 157
procedure, 83, 163, 166-167
processor, 3
processors, 104
profiles, 126, 128
programmable, 104
propagate, 105
propagation, 105, 108, 111, 119-120, 146-147
proximity, 31
pulse, 35, 146, 148-152, 155-157, 171
pulser, 133, 152-153, 156-158, 170-171
pulsers, 171
pulses, 34, 137, 150-151, 155-157
Pw, 150
Q
quad, 114
quadruple, 115
quotient, 6
R
radix, 1, 4, 6, 10, 15, 30
rectangular, 65, 85, 91, 99, 134
registers, 69, 104
relays, 124
repetition, 27-28, 149-150
repetitive, 20, 27
resistance, 35, 37, 107, 113, 119, 133, 135-136,
140-142, 145, 163
Resistive, 144
resistor, 35, 38, 48, 108, 111-112, 124, 126, 128-131,
141, 170
resistors, 38, 43, 48, 100, 106, 119, 124, 162
resolution, 166
response, 35, 41, 51, 108, 137, 142
Restorer, 38, 40
RTCL, 43
RTL, 41-43, 108
S
Schematic, 108
Schottky, 110-111, 116, 118, 122-123
scope, 144, 149
screen, 140, 142-145, 149, 169
semiconductor, 31, 50, 99-100, 102, 104, 107,
122-123, 152
sequential, 51, 161
signal, 34-36, 52-53, 105, 137, 142, 145-146, 149,
153-157, 162-163
signals, 16, 22, 34, 38, 102, 105, 107-108, 142,
145-146, 153, 155-156
signature, 133, 153-154
signed, 14-15
Signetics, 117
Index
SN, 115, 117
software, 68-69
SOIC, 103
SOICs, 103
soldering, 103, 170
solenoids, 124
SOP, 78-79
spec, 111
SS, 125, 128-130
SSI, 102, 104
subfamily, 116
subscripts, 78-79
subtraction, 4, 6, 9-10, 18-19
subtrahend, 4, 10
Suffix, 115
sum, 3-4, 9, 16, 19, 51, 68, 73, 76, 78
sums, 75-76
surface, 103, 169
switching, 43, 46, 48, 51-52, 62, 75, 118, 123-124, 132
symbol, 52-56, 65-66, 72-73, 112-113, 123
symbols, 1, 10, 25, 65-66
T
TDL, 48
techniques, 6, 148
technology, 99, 102, 104, 108, 110-111, 119
temperature, 43, 111, 118, 168
testing, 100, 136, 153-155, 157, 162, 164
Theorem, 73-74
theorems, 68, 72-74
theoretical, 1, 161
timing, 62, 64, 146, 153-154
totem, 113
tracer, 133, 152-153, 157-158
tracing, 157-158
transformations, 98
transformer, 166
transient, 118
Transistor, 38, 41-43, 46-47, 104, 106, 108-110, 137
transistor, 32, 36-38, 41-42, 46-47, 50, 99, 104,
108-109, 112, 123, 126-127, 132, 170
transistors, 43, 46, 99-100, 112-113, 118-119, 170
transition, 26, 105, 108, 149
transmit, 113
transmitted, 27-28
transmitter, 26
trigger, 145, 153-154
Triode, 144
troubleshoot, 142, 157, 161, 166
truth, 34-35, 50, 52-62, 64, 66, 68-70, 78-79, 81-84,
89-90, 92-93, 97-98
TTL, 38, 104, 106, 108, 110-112, 114-116, 118, 120,
122-131, 151, 155-156, 164-165, 171-172
tube, 142-144
Tunnel, 48-49
V
valence, 31
valve, 99
VAR, 145
variation, 118, 122, 142
VBE, 41
Vcc, 32, 41-42, 45-47, 49, 171-173
VDD, 125, 128
versa, 6
versions, 69, 110, 118
VLSI, 102, 104, 118-119
volt, 41, 134-135, 144-145
voltage, 31-35, 37-38, 41, 47-48, 62, 105-109,
118-120, 122-126, 128-130, 132-133, 136-137,
139-140, 142, 145, 149, 152-153, 155-158,
161-164, 166-170
voltages, 46, 107, 118, 124, 126, 167
voltmeter, 133, 136, 140
volts, 107, 118, 144
W
wafer, 100
watts, 119
waveform, 142, 144-146, 149, 153, 163, 171
waveforms, 62, 142, 150
Waver, 166
Index
X
xed, 18, 68
xl, 145
xlM, 141
XNOR, 56-57, 66
XOR, 56-57, 66
xy, 74-77, 81-83
Z
zero, 1-2, 5, 15, 34-35, 37-38, 72-73, 78-79, 91, 122,
141, 144, 151

A, 135
Index
A
acceptor, 31
ACT, 116, 120
activated, 124, 130
addend, 3-4
adding, 5, 14, 16, 18, 20, 22, 31, 78-79, 102, 145
algebra, 1, 53, 68, 72-74, 83, 98
algebraic, 68, 74, 91-94, 98
algorithms, 22
allowed, 88, 130
ammeter, 133, 139, 152
amperes, 135
amplification, 108
amplified, 105, 152
amplifier, 47, 137
amplifiers, 44, 108
amplitude, 142, 146, 148-150
analogue, 137, 141, 152
analysis, 70-71, 109, 153-154, 170
analyzer, 153-154
analyzers, 133, 153-154
anode, 31, 143-144
ANSI, 65
application, 22, 69, 133, 153, 161
Aquadag, 144
arithmetic, 1, 6, 14-18, 30, 56, 68
array, 83-84, 102-103
ASCII, 16, 25-26, 30
associative, 72-73
augend, 3-4
augmented, 78-79
B
bandwidth, 149
battery, 136, 141, 169
BCD, 16-19, 26
bias, 48, 123
biases, 34, 37, 41
binary, 1-6, 8-10, 13-25, 28, 30, 34, 72, 84, 96, 113,
154-155
bipolar, 38, 99, 119
bit, 25
Boolean, 1, 22, 53-57, 63, 66, 68-74, 76, 78-79, 81,
83, 86-87, 89, 92-93, 95, 98, 113
bracketing, 93
buffer, 38, 54, 113, 125-126, 129
buffered, 54, 115
byte, 2-3, 25
C
cable, 158, 166, 170
capacitor, 136-137, 141-142, 162, 170
capacitors, 43, 100, 122, 136, 141-142
carriers, 50, 122-123
cathode, 31, 142-144
cell, 81-85, 87-88
cells, 83-84, 86-88
Index
ceramic, 99-100, 102, 104, 115
ceramics, 100
chip, 99, 102-104, 119-120
chips, 102, 104
circuit, 2, 34-35, 37-38, 43-44, 46, 48, 51-54, 58, 67,
69, 99-100, 102-111, 113-114, 122-123, 126-127,
130, 132, 135-136, 139-143, 145-146, 149,
151-152, 154-158, 161-165, 169-170, 173-174
circuitry, 4, 100, 133, 136, 164, 174
circuits, 16, 52, 54, 56, 83, 99, 104, 118-119, 124,
126, 130, 135, 137, 140, 142, 154, 161-162, 169
Clip, 136, 152, 154
clip, 133, 152, 154-155
CMOS, 104, 106, 114, 118-120, 124-130, 151,
155-156
code, 16-28, 30, 83, 96, 115, 132
Coded, 17, 25
coded, 16-17, 25, 30, 71, 96
codes, 1, 16-22, 25-28, 30, 97, 111
coding, 16-17
coil, 133-134, 136, 140-141
coils, 136, 144
collector, 32, 38, 41, 43, 110-113, 123
column, 3, 10, 25-26, 60, 78, 84, 86, 88-89
columns, 25, 81, 91
combination, 1, 12, 16-18, 34, 37, 58, 60, 68-69, 83,
97, 165
combinations, 52, 59, 71, 81, 92
commutative, 72-73
compatible, 70, 103, 118, 120, 124, 126, 128-129
complement, 15-16, 18-19, 27, 30, 41, 73, 75
complemented, 81
complements, 30
components, 1, 43-44, 99, 104, 106, 122, 124, 133,
136, 157, 161, 168, 170
computer, 1, 3, 6, 14, 25-26, 51, 68, 133, 166, 168, 174
computers, 1, 3, 18, 22, 25-26, 51
conduct, 31, 35, 109-110, 112
conducting, 107-108, 110, 143, 156, 158
conduction, 31, 50
conductor, 114, 139, 152, 157
configuration, 32, 50, 112, 121-123, 140
connected, 31, 38, 53, 58, 102, 104-105, 112-113, 123,
126, 130, 135, 139-140, 143-144, 151, 154-155,
164, 171
connection, 68, 99-100, 112-113, 122, 140, 152, 161,
163, 166, 170
connections, 99-100, 102, 104, 114, 154, 164
construction, 78-79, 104, 119, 143
Constructional, 134
controllers, 104
cooling, 168, 174
core, 115, 134
coupled, 104, 106, 145
coupling, 145
CPU, 167
crept, 26
critical, 38, 126
crt, 142-143
Cutoff, 109
cutoff, 108-109
cycle, 28, 144, 146, 148-150
cyclic, 20, 22, 28
D
data, 2, 16, 20, 25-28, 65, 69-70, 114, 116, 130,
153-154, 161, 163, 169
DCTL, 46, 106
debounce, 124
Decibel, 137
decoders, 69, 104
deflector, 143-144
DeMorgan, 73
detect, 26-28, 151, 153, 156, 169
detected, 26-27, 31, 152, 166-167
detection, 16, 26-28, 155, 166
device, 31, 54, 70, 102, 105, 107, 113, 151, 162-163
devices, 1, 22, 99, 101, 104, 113-114, 117, 122, 124,
133, 162, 168, 170
diagnostic, 169
diagram, 35-37, 46, 49-50, 55, 62, 64, 89, 113-114,
135, 137-138, 151, 163
diagrams, 42, 116, 121, 153, 163
diameter, 99
digit, 1-2, 4, 8-10, 14, 16-19, 138-139, 153
digital, 1-2, 4, 6, 16-19, 22, 26, 51, 53, 55, 99, 101,
104, 106, 110, 114-115, 124, 129-130, 132, 137,
146, 151-155, 163-164, 173
digits, 1-3, 8-10, 12, 14, 17-19, 25-26, 97, 138
diode, 31-32, 34-38, 48, 50, 107-109, 122-124, 132,
137, 170
diodes, 35, 38, 42, 44, 47-48, 99-100, 107-108,
122-123, 154, 170
DIP, 100-103, 115
disk, 166, 168-169, 174
display, 137-138, 145-146, 152, 154, 166
displayed, 14, 139-140, 144-145, 153, 169
Index
displays, 137, 142, 153
dissipation, 105-106, 111, 118-119, 122
distortions, 146
Distribution, 72
dividend, 5-6, 28
division, 5-6, 28, 142, 144
divisor, 5-6, 28
DMM, 137-139
domain, 153
donor, 31
donors, 31
dormant, 119
dot, 53, 100, 144
driver, 126-127
drivers, 126
DTL, 47, 106, 108-110
dual, 74, 100-101, 104, 111, 115, 137
duality, 68, 98
E
EBCDIC, 25-26, 30
ECL, 104, 118-120, 155
electron, 31, 122, 143-144
electrons, 31-32, 122, 143
electrostatic, 167
emitter, 32, 37-38, 41, 50, 110-111
emitting, 124, 137, 154
enabled, 113, 156
encode, 20, 29, 97
encoding, 20, 169
energy, 31, 99, 122
engineers, 69
equipment, 2, 25, 136, 142, 146, 153, 161-163, 170,
174
error, 16, 20, 26-28, 139, 169
errors, 22, 26-28, 168
ESD, 167
experiments, 124
exponent, 14
expression, 14, 53-57, 59, 66, 68-71, 73-78, 81, 83,
91-98, 113
expressions, 22, 63, 68-71, 74-78, 87, 89, 92, 98
F
fabricating, 99-100
fairly, 75
fan, 100, 105, 108, 116, 118-119, 122, 132, 168, 174
fault, 151, 153-154, 161-166, 173-174
faulty, 153-154, 161-166, 170, 173-174
FCT, 116
Features, 43-44, 46-48, 69, 134
fiberglass, 102
Flicker, 166
frequency, 120, 144, 146, 149-150
functional, 65, 111, 162-163, 169
functioning, 119, 165-167, 169, 171
G
gain, 33, 54
gate, 34-38, 41-42, 48, 50-58, 62, 64-66, 96, 98,
104-105, 108-115, 118-119, 121-122, 130, 146,
151-152, 164-166, 170-173
generate, 20
generated, 9, 15, 28, 145, 157
generates, 118
generation, 28, 156
generator, 139, 149
Germanium, 31, 43-44, 46, 48
GND, 121, 128-130, 145, 155, 164-165
graphite, 143
graticules, 146
grid, 84-85, 100, 102-103, 143
grouping, 25, 86-87, 89
H
Hades, 117
Hamming, 28
hardware, 68, 75
HC, 116, 120
HCT, 116
hertz, 150
hex, 10, 12, 30
holes, 25-26, 31-32, 103
Index
Hollerith, 25-26
I
IBM, 25
IC, 99-100, 102, 104, 106, 114-115, 121, 124, 126,
129, 132, 151-152, 154, 157, 163-166, 170-172
ICs, 100-104, 106, 108, 124, 126, 170
Idempotent, 74, 76
identities, 74, 86
identity, 68, 72-73, 75, 77
IEC, 65
IEEE, 65-66
IM, 117
immunity, 105, 118-119
impairments, 26
impedance, 33, 47, 113, 118
implementation, 69
implementations, 98
implicants, 70
Implication, 70
impurities, 31
IN, 46
indicator, 124, 126-127, 132, 151-152, 164, 172
inductor, 140-141
infinite, 107, 113, 140, 142
infinity, 136, 141
information, 16, 26-28, 113, 116, 129-130, 132, 135,
142, 153-154, 162, 165
input, 6, 17, 33-36, 38, 41, 43, 48, 51-54, 57-59, 62,
64, 66, 68, 81, 83-85, 89-91, 96-98, 104-105,
107-111, 113-115, 122, 126, 128-130, 132,
145-146, 148, 152, 157, 162-165, 170-171, 173
inputs, 34-35, 37-38, 43, 51-54, 56-59, 61-63, 68, 72,
81, 83-85, 96-98, 104, 109, 112, 116, 126, 128-130,
145, 153, 165, 171-173
insulators, 31
integer, 29, 93
integers, 20
integrated, 99, 103-104, 170
integrating, 137
integration, 99, 102, 104, 132
Intel, 102, 117
interface, 54, 124, 128, 130-131
Interfacing, 124, 126-130, 132
internally, 18, 25, 142, 145
inverted, 37, 43-44, 47, 55-56
inverter, 41, 54, 98, 104, 110, 113, 124, 126, 129-130
inverters, 96
inverting, 55, 125-126, 129, 145
J
junction, 31-32, 37-38, 41, 50, 99, 110-112, 119,
122-123
K
Karnaugh, 22, 81, 83, 87, 89, 92, 95
keyboard, 129-130, 132, 166-167
kmap, 82, 86, 89-90
Kmaps, 81
L
LCDs, 137
LED, 124-127, 152, 154, 156, 165
LEDs, 124, 126-127, 137, 154-155, 172
logic, 1, 34-35, 37-38, 42, 44, 46-48, 50-56, 58-59, 62,
65-68, 76, 91, 98-99, 101-102, 104-105, 107-114,
116, 118-120, 122, 124, 126-127, 130, 132-133,
146, 151-158, 163-165, 170-174
logical, 43, 69, 71-73, 83, 104, 152, 161-162
logically, 70-73
LS, 111, 115-116, 120, 129-130
LSB, 3, 17, 20, 22
LSI, 102, 104, 118
M
mA, 122, 124, 128, 131, 135, 159
magnet, 133-135
magnetic, 27, 133-134, 152, 157
magnitude, 2, 14-15, 30, 152
Mainframe, 3
maintenance, 142
majority, 27, 92, 101, 122
Index
mantissa, 14
manufacturers, 100-101, 107, 115-117, 122, 132
map, 81-84, 86-87, 89, 91-96
maps, 22, 81, 83, 87, 92
margin, 105, 118-119, 132
matrix, 69
maximum, 17-18, 20, 76, 122, 124, 138
Maxterms, 75
measurement, 133, 137, 145-146, 148, 162-163, 167
measurements, 137, 139, 162-163, 167-168
Measuring, 133, 139-140
metal, 99-100, 102-104, 114, 122-123, 136
meter, 99, 133-136, 138-142, 152, 159
meters, 133-134
MHz, 120, 149
micro, 135, 144, 152
micrometer, 99
milliameter, 136
miniaturization, 46
minimising, 89
minimize, 43, 102
minimized, 70, 83, 91, 97
minimum, 1, 25, 102, 105, 122
minority, 50
minterm, 78, 81, 83
minterms, 68, 78, 81, 83-84
minuend, 4, 10
MM, 111, 117
Mnemonic, 111
mode, 145, 165
modules, 104
monitor, 146, 166
Monolithic, 117
MOS, 104, 118, 120, 170
motherboard, 169
Motorola, 117
MSB, 3, 14-15, 17, 20-24
MSI, 102, 104, 118
multimeter, 133, 135, 137, 139-141, 154-155
multiplexer, 83
multiplexers, 104
Multiplicand, 5
Multiplier, 5
mV, 138
mW, 106, 111
N
NAND, 37, 52, 55, 58, 65-66, 68, 89, 104-105,
108-114, 146, 165, 170-172
nano, 119
network, 58-60, 133
nibble, 2-3
nibbles, 2
node, 151, 153, 164
nodes, 153, 164-165
noise, 26, 105, 118-120
noninverting, 125
nonredundant, 76
Nonweighted, 18
nonzero, 28
NPN, 32, 50, 123, 127
nucleus, 31
numerals, 1
O
octal, 1, 6, 8-10
ohm, 134-135, 140-141
ohmmeter, 133, 136, 140-141
ohms, 107, 135, 137, 139-141
operands, 72
operator, 69, 72-73, 156-157
operators, 68-69, 72-74
orbits, 31
ORed, 56, 76
ORing, 73
oscilloscope, 133, 142-143, 145-146, 149, 153-156
output, 6, 17, 32-38, 41-44, 47, 51-52, 54-56, 58, 62,
64, 70, 72, 78-79, 83-84, 92, 96-97, 105, 109-115,
118, 122, 124, 126-128, 146, 151-152, 157-158,
163-166, 170-173
outputs, 51, 55, 81, 98, 104, 112-113, 122, 126, 128,
165
overlap, 85, 88, 94
overlapping, 88
oxide, 99, 104, 114
Index
P
package, 99-104, 111, 114-115, 154, 170
packages, 100-103
packaging, 100, 103, 115-116
packing, 119-120
panel, 133-137, 140, 142, 144
parenthesis, 14, 73
parity, 25-30, 168
pattern, 10, 12, 20, 100
patterns, 83, 94
PC, 163-165, 168
PCB, 158, 170
PGA, 102-103
phase, 70-71
PN, 32, 50
PNP, 127
pointer, 133-134, 136, 141, 159
polarity, 123, 136-137, 152
pole, 110, 113
poles, 133-134
POS, 79
precision, 14
predetermined, 27
prefix, 115
PRF, 149-150
primitive, 65-66, 70-71
principle, 68, 74, 98, 152
printed, 152, 158, 164-165
probability, 28
probe, 126-127, 133, 136, 145, 148, 151, 153-158,
163-165, 170-172, 174
probes, 126, 136, 140-141, 145, 152-153, 155, 157
procedure, 83, 163, 166-167
processor, 3
processors, 104
profiles, 126, 128
programmable, 104
propagate, 105
propagation, 105, 108, 111, 119-120, 146-147
proximity, 31
pulse, 35, 146, 148-152, 155-157, 171
pulser, 133, 152-153, 156-158, 170-171
pulsers, 171
pulses, 34, 137, 150-151, 155-157
Pw, 150
Q
quad, 114
quadruple, 115
quotient, 6
R
radix, 1, 4, 6, 10, 15, 30
rectangular, 65, 85, 91, 99, 134
registers, 69, 104
relays, 124
repetition, 27-28, 149-150
repetitive, 20, 27
resistance, 35, 37, 107, 113, 119, 133, 135-136,
140-142, 145, 163
Resistive, 144
resistor, 35, 38, 48, 108, 111-112, 124, 126, 128-131,
141, 170
resistors, 38, 43, 48, 100, 106, 119, 124, 162
resolution, 166
response, 35, 41, 51, 108, 137, 142
Restorer, 38, 40
RTCL, 43
RTL, 41-43, 108
S
Schematic, 108
Schottky, 110-111, 116, 118, 122-123
scope, 144, 149
screen, 140, 142-145, 149, 169
semiconductor, 31, 50, 99-100, 102, 104, 107,
122-123, 152
sequential, 51, 161
signal, 34-36, 52-53, 105, 137, 142, 145-146, 149,
153-157, 162-163
signals, 16, 22, 34, 38, 102, 105, 107-108, 142,
145-146, 153, 155-156
signature, 133, 153-154
signed, 14-15
Signetics, 117
Index
SN, 115, 117
software, 68-69
SOIC, 103
SOICs, 103
soldering, 103, 170
solenoids, 124
SOP, 78-79
spec, 111
SS, 125, 128-130
SSI, 102, 104
subfamily, 116
subscripts, 78-79
subtraction, 4, 6, 9-10, 18-19
subtrahend, 4, 10
Suffix, 115
sum, 3-4, 9, 16, 19, 51, 68, 73, 76, 78
sums, 75-76
surface, 103, 169
switching, 43, 46, 48, 51-52, 62, 75, 118, 123-124, 132
symbol, 52-56, 65-66, 72-73, 112-113, 123
symbols, 1, 10, 25, 65-66
T
TDL, 48
techniques, 6, 148
technology, 99, 102, 104, 108, 110-111, 119
temperature, 43, 111, 118, 168
testing, 100, 136, 153-155, 157, 162, 164
Theorem, 73-74
theorems, 68, 72-74
theoretical, 1, 161
timing, 62, 64, 146, 153-154
totem, 113
tracer, 133, 152-153, 157-158
tracing, 157-158
transformations, 98
transformer, 166
transient, 118
Transistor, 38, 41-43, 46-47, 104, 106, 108-110, 137
transistor, 32, 36-38, 41-42, 46-47, 50, 99, 104,
108-109, 112, 123, 126-127, 132, 170
transistors, 43, 46, 99-100, 112-113, 118-119, 170
transition, 26, 105, 108, 149
transmit, 113
transmitted, 27-28
transmitter, 26
trigger, 145, 153-154
Triode, 144
troubleshoot, 142, 157, 161, 166
truth, 34-35, 50, 52-62, 64, 66, 68-70, 78-79, 81-84,
89-90, 92-93, 97-98
TTL, 38, 104, 106, 108, 110-112, 114-116, 118, 120,
122-131, 151, 155-156, 164-165, 171-172
tube, 142-144
Tunnel, 48-49
V
valence, 31
valve, 99
VAR, 145
variation, 118, 122, 142
VBE, 41
Vcc, 32, 41-42, 45-47, 49, 171-173
VDD, 125, 128
versa, 6
versions, 69, 110, 118
VLSI, 102, 104, 118-119
volt, 41, 134-135, 144-145
voltage, 31-35, 37-38, 41, 47-48, 62, 105-109,
118-120, 122-126, 128-130, 132-133, 136-137,
139-140, 142, 145, 149, 152-153, 155-158,
161-164, 166-170
voltages, 46, 107, 118, 124, 126, 167
voltmeter, 133, 136, 140
volts, 107, 118, 144
W
wafer, 100
watts, 119
waveform, 142, 144-146, 149, 153, 163, 171
waveforms, 62, 142, 150
Waver, 166
Index
X
xed, 18, 68
xl, 145
xlM, 141
XNOR, 56-57, 66
XOR, 56-57, 66
xy, 74-77, 81-83
Z
zero, 1-2, 5, 15, 34-35, 37-38, 72-73, 78-79, 91, 122,
141, 144, 151

A, 135

Affiah Digital Electronics

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Affiah Digital Electronics

Caricato da

Copyright:

Formati disponibili

CHAPTER ONE

NUMBER SYSTEM AND CODES

Potrebbero piacerti anche