VLSI TEST LAB.

NCKU-EE KJLEE
Advisor: Kuen-Jong Lee
Presenter: Wei-Cheng Lien
E-mail: lwz98@beethoven.ee.ncku.edu.tw
Logic Synthesis with
Synopsys Design Vision
Reference:
1. Synopsys Manual (Version X-2005.09, September 2005)
2. CIC Training Manual J an.-2007
3. Synopsys Online Support
4. CIC News
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Cell-Based Design Flow
Matlab/ C/ C++/
System C/ System Verilog
/ ADS/ ConvergenSC
NC-Verilog/ Verilog XL/
ModelSim/ VCS
Design/ Power Compiler
SOC Encounter/ Astro
NC-Verilog/ Verilog XL/
ModelSim/ VCS
DFT Compiler/ TetraMAX
Verilog/ VHDL
DRC/ LVS (Calibre)
Calibre Xrc/ NaroSim/
TimeMill & PowerMill/
Star RCXT
Memory Compiler
SynTest
Physical Compiler/
Mgama Blast
Tap out
Logic Synthesis &
formal verification
Conformal LEC/
Assertain ABV
/ Formality
Gate-level post-layout
simulation
transition-level post-layout
simulation
RTL-level
Design
Hard I P
Soft I P
Post-layout
Verification
Layout-level
Design
Gate-level
Simulation
Design for
Testing
System-level
Design
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How to Set CAD Tool Environment
Unix% cp /home4/classuser/sys0701/sys0701ta1/.cshrc .
Unix% cp /home4/classuser/sys0701/sys0701ta1/.synopsys_dc.setup .
Unix% cp /home4/classuser/sys0701/sys0701ta1/setup.csh . (Source CAD Tool license)
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Outline
Basic concepts of logic synthesis [6]
Synthesis with Synopsys design vision [52]
Synthesizable/good coding styles [7]
Conclusions [2]
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Chapter 1
Basic concepts of logic synthesis
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Logic Synthesis
Synthesis=translation+optimization+mapping
(HDL Compiler)
No timing info.
Timing info.
(Design Compiler)
RTL
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Logic Synthesis Flow Overview
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Module Structure
1.Module name & Port list
2. Definitions (I / O, wire, reg,
function, parameter, integer)
3.Module instantiations
4. Module statements & constructs
HDL Compiler (1/2)
HDL Compiler translates verilog HDL descriptions
into a netlist with GTECH library (the synopsys
default)
HDL
Compiler
Symbol View
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HDL Compiler (2/2)
In schematic view, we can see the verilog file is translated
with a GTECH library
Schematic View
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Design Compiler
+
Technology
Library
=
TSMC13.v, UMC18.vetc
fast.db, slow.dbetc
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Chapter 2
Synthesis with Synopsys design vision
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Synthesis Step
1. Edit Your Code for
Synthesis [0]
2. Read in & Set library [2]
3. Design View [2]
5. Apply Design Constraints [7]
4. Set Design Environment [8]
6. Compile Design [6]
7. Report & Analysis [7]
8. Simulation & Wave View [4]
Layout
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Start to Use Design Vision (1/2)
Unix% cp -r /home4/classuser/sys0701/sys0701ta1/student .
(Example)
Unix% more .synopsys_dc.setup :
Menu File Setup
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Start to Use Design Vision (2/2)
Invoke Design Vision
(1) XG Mode (After 2005/9)
Unix% dv (&)
(2) DB Mode (Before 2004/12)
Unix%
design_vision db_mode
(3) dcsh Mode (Before 1999)
Unix%
design_vision dcsh_mode
You can use -no_gui option
to stop GUI
Unix% Exit (or quit) for leave
XG Mode Supports
1. enhanced DB format
(.ddc) format & db
2. Tool Command Language (Tcl)
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Tcl (Tool Command Language)
Tcl changes your life.
Tcl Script = A sequence Tcl Commands
design_vision-xg-t> Tcl commands
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Step 2: Read File (1/3)
design_vision-xg-t>
read_file -format verilog "../ add4.v"
current_design [module_name]
link
2
1
Menu File Setup
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Step 2: Read File (2/3)
Check if any errors or warnings appear
Modify your designs according to the error or
warning messages
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Step 2: Read File (3/3)
Read Files with different Methods.
(1) Menu File Read
(2) Menu File Analyze
(2) Menu File Elaborate
design_vision-xg-t>
analyze -library WORK -format verilog {top.v timer.v }
elaborate top -architecture verilog -library WORK
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Step 3: Symbol View
2
1
2
design_vision-xg-t> current_design top
You can see the I / O pins
and number of bits they occupied
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Step 3: Schematic View
1
2
Cell Name
I nstance Name
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Real World Environment (1/2)
The defaults are not realistic conditions

Input drive is not infinite

Capacitive loading is usually not zero

Process, Voltage, and Temperature (PVT) variation
The operating environment affects

Characteristics of components selected from target
library

Timing through your design
The operating environment you specify
describes the conditions that the circuit will
operate in field.
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Real World Environment (2/2)
Target Design Another
Design
Another
Design
Input Drive Strength
Input Delay
Output Loading
Output Delay
Specify these parameters and use the synthesis tool to make
your design meet the real condition and constrains
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Step 4: Setting Design Environment
(1) Setting Operating Condition [1]
(2) Setting Input Driving Strength [2]
(3) Setting Output Loading [1]
(4) Setting Input/Output Delay [2]
(5) Setting Wire Load Model [1]
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(1) Set Operating Environment
Attributes Operating Environment Operation Conditions
design_vision-xg-t>
set_operating_conditions -min_library fast -min fast -max_library slow -max slow
For Setup Time Check
For Hold Time Check
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(2) Set Input Drive Impedance (1/2)
Switch to symbol view
Choose the targeted input ports
Attributes Operating Environment Drive Strength
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(2) Set Input Drive Impedance (2/2)
1
6
2
5
3
4
design_vision-xg-t>
set_driving_cell -library slow -lib_cell BUFX4 -pin {Y} [get_ports clk]
set_driving_cell -library slow -lib_cell DFFX1 -pin {Q} [remove_from_collection [all_inputs] [get_ports clk]]
not want to scale the
port drive capability
Derive design rule attributes from the driving
cell and apply them to the ports the cell drives
1. SoC Design uses DFF
for partition
2. Clock can model
by ring buffer
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(3) Set Output Loading
Choose the targeted output ports
Attributes Operating Environment Load
1. How to find the cell load ?
Choose the cell in library
2. Apply to output loading
design_vision-xg-t>
set_load [load_of "slow/ DFFX1/ D"] [all_outputs]
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(4) Setting Input/Output Delay (1/2)
1. Choose input pins except clock.
2. Attributes Operating Environment Input Delay
design_vision-xg-t> set_input_delay -max 1 -clock clk [all_inputs]
set_input_delay -min 0.2 -clock clk [all_inputs]
Attention!
The step should execute
after clock specify (Step 5) !
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(4) Setting Input/Output Delay (2/2)
1. Choose output pins
2. Attributes Operating Environment Output Delay
design_vision-xg-t> set_output_delay -max 1 -clock clk [all_outputs]
set_output_delay -min 0.1 -clock clk [all_outputs]
Attention!
The step should execute
after clock specify (Step 5) clock specify (Step 5) !
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(5) Setting Wire Load Model
Attributes Operating Environment Wire Lode
design_vision-xg-t> set auto_wire_load_selection false (Turn Off WLM selection)
set_wire_load_model -name tsmc13_wl10 -library slow
set_wire_load_mode top
Wire Load Model (WLM):
Estimate of a nets RC parasitics
based on the nets fanout.
But WLM isnt useful today.
We use Topographical Mode to replace.
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Step 5: Apply Design Constraints
Constraints are goals that the Design Compiler uses
to optimize a design with target technology library.
During compile, Design Compiler attempts to meet
all constraints.
(1) Set Design Constraint [2]
(2) Maximum Delay Constraints [1]
(3) Specify Clock [2]
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(1) Set Design Constraint (1/2)
1. Choose all top design
2. Attributes Optimization Constraints Design Constrains
design_vision-xg-t> set_max_total_power 0.0 uw
set_max_dynamic_power 0.0 uw
set_max_leakage_power 0.0 uw
set_max_area 6000
set_max_fanout 2 [all_inputs]
set_max_transition 0.3 [all_inputs]
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How to know gate count of your design?
(1) Set Design Constraint (2/2)
First See the area your design after synthesis use
MENU Design Report Area or
design_vision-xg-t> report_area
Gate counts =
Chip Report Area/ NOR2 Area
Quick View
NOR2(NAND2) Area =
5 for 0.13um library
10 for 0.18um library
tsmc13g.pdf
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(2) Maximum Delay Constraints
Choose start and end points of timing path
(push ctrl bottom to choose them)
Attributes Optimization Constraints Timing Constrains
For Combinational circuit
primarily
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(3) Specify Clock (1/2)
1. Choose input port clock
2. Attributes Specify Clocks
But some times the Tool will disappear
when you check the option, we use
command instead GUI.
1
2
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(3) Specify Clock (2/2)
1
2
3
4
5
6
Basic constraints for clock
design_vision-xg-t>
create_clock clock period 5 -waveform {2.5 5}
set_fix_hold clock
set_dont_touch_network clock
Other constraints for clock
design_vision-xg-t>
set_clock_uncertainty 0.1 [get_clocks clock]
set_clock_latency -source 0 [get_clocks clock]
set_clock_latency 1 [get_clocks clock]
set_input_transition 0.3 [all_inputs]
set_clock_transition 0.3 [all_clocks]
Not re-buffer the clock
Automatic solve hold time violation
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Clock Network Effects
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Check Design
Menu Design Check Design
1
3
2
4
5
design_vision-xg-t> check_design
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Some Warnings Solution
Whats wrong after design check?
(1) multiple design instance
Sol: 1. Select the most top design of the hierarchy
2. Hierarchy/Uniquify/ Hierarchy
design_vision-xg-t> uniquify
(2) assignment problem
design_vision-xg-t> set_fix_multiple_port_nets all buffer_constants
complie
(3) does not drive any nets dont care!
For more detail
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Save Script File for Constraints
MENU File Save Info Design Setup
1
2
3
4
design_vision-xg-t> write_script > / / chip.dc
Attention! You should add uniquify to the dc file
and solve Multiple I nstance
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Execute Script File
Setup Execute Script
1
2
3
4
design_vision-xg-t> source / / chip.dc
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Step 6: Compile Overview
Logic Level Optimization
Gate Level Optimization
Map
Flatten Structure
For Area/ Speed
For Area
(Default: ON)
Form SOP terms
(Default: OFF, Only for timing
goal and banishing dont care)
Replace GTECH cells
from target library
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Apply Structure & Flattern
Attributes Optimization Directives Design
Consider timing constrains
Use boolean algebra to reduce size
Computer resource
Output Sharing
Use Karnaugh map
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Mapping (Compile Design) (1/3)
1
2
Menu Design Compile Design
design_vision-xg-t>
compile -map_effort medium -area_effort medium
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Mapping (Compile Design) (2/3)
Mapping current
Design with library
Set amount of
CPU time
Set area recovery
phase
Reference: Design Manual
Use only local
improvement
no mapping
Remove all designs
except dont_touch
optimizes across all
hierarchical boundaries
sequential elements in optimized
design must exactly match RTL
replaces all sequential elements
with scan-equivalent cells
fix design rule violations
without performing
design optimization.
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Mapping (Compile Design) (3/3)
Check if any errors or warnings exist!
2. DC-Ulrta
1. General Compile
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High Performance Designs
This command requires a DC-Ultra license and a
DesignWare (technology-indep soft macros)
Foundation license.
4 addition options in new versions (DC 2005.09-SP3)
Menu Design Compile Ultra
design_vision-xg-t>
compile_ultra scan -no_uniquify -no_autoungroup
compiler optimizes designs
that have multiple instantiations
perform a test-ready compile
automatically removes
levels of hierarchy
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Step 7: Report & Analysis
(1) Timing Report
(2) Area Report
(3) Power Report
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(1) Timing Report (1/2)
Menu Timing Report Timing
1
2
3
design_vision-xg-t> report_timing -path full -delay \
max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group
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(1) Timing Report (2/2)
Unit: ns
Slack (Setup, Max delay) =
Data Required Time Data Arrival Time0
Slack (Hold, Min delay) =
Data Arrival Time Data Required Time0
Max for setup
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(2) Area Report (1/2)
Menu Design Report Area
1
2
3
design_vision-xg-t> report_area -nosplit
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(2) Area Report (2/2)
Unit: um*um (CIC Default)
Dont care net area.
Report for this.
Gate counts =
Chip Report Area/ NOR2 Area
= 2480 / 5 = 496
Quick View
NOR2(NAND2) Area =
5 for 0.13um library
10 for 0.18um library
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(3) Power Report (1/2)
Menu Design Report Power
1
2
3
design_vision-xg-t> report_power
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(3) Power Report (2/2)
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Highlight
Menu View Highlight Critical Path
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Save Design (1/2)
Menu File Save As
Remember to check the Save all designs in hierarchy bottom
1
2
3
4
design_vision-xg-t>
write -hierarchy -format verilog -output / ../ top_compile.v
5
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Save Design(2/2)
The .ddc format saves only the logical design information. (not
save physical information)
The .db format saves both information.
Menu File Save As
design_vision-xg-t>
write -format ddc -hierarchy
design_vision-xg-t>
write -format db -xg_force_db -hierarchy
design_vision-xg-t>
read_db [design_name].db
design_vision-xg-t>
read_ddc [design_name].ddc
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Supported Database Formats by Tool
Reference:
XG Mode User Guide
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Save Design - Timing File
Synopsys Design Constraints (SDC) is a format used to specify the
design intent, including the timing and area constraints for a design.
SDC is based on the tool command language (Tcl).
design_vision-xg-t>
write_sdf version 1.0 context verilog chip.sdf
1
3
4
2
5
6
7
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Step 8: Verilog Simulation (1/2)
Add initial $sdf_annotate( chip.sdf" , top);
Delay effect
Modify the testfixture
Unix% verilog testfixture.v top_compile.v /../tsmc13.v +neg_tchk
Or use `include directive then Unix% verilog testfixture.v
timescale should appear in both the design file and textfixture file
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Step 8: Verilog Simulation (2/2)
*** SDF Annotator version 2.2.4
*** SDF Interface version 5.2.1
*** SDF file: add16_3.sdf
*** Back-annotation scope:
test_adder.Add
*** No configuration file specified -
using default options
*** SDF Annotator log file: sdf.log
*** No MTM selection parameter
specified
*** No SCALE FACTORS
parameter specified
*** No SCALE TYPE parameter
specified
Configuring for back-annotation...
Reading SDF file and back-
annotating
timing data...
*** SDF back-annotation successfully
completed
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Chapter 3
Synthesizable/ good coding styles
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Unsupported definitions and declarations
- primitive user-definition
- time declaration
- event declaration
- triand, trior, tri1
- tri0, trireg net types
- Ranges and arrays for integers
Unsupported statements
- initial statement
- repeat statement
- delay control
- event control
- wait statement
- fork statement
- deassign statement
- force statement
- release statement
Unsupported Verilog Language Constructs
Reference: HDL Compiler (Presto Verilog) Reference Manual
Unsupported operators
-Case equality &
-inequality operators (=== and !==)
Unsupported gate-level constructs
- nmos, pmos, cmos, rnmos,
- rpmos, rcmos
- pullup, pulldown, tranif0,
- tranif1, rtran, rtrainf0,
- rtrainf1 gate types
Unsupported miscellaneous constructs
- hierarchical names within a module
If you use an unsupported construct,
Presto Verilog issues a syntax error
such as
event is not supported
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Unsynthesizable Coding Style
Verilog code is not pure RTL code.

Cannot use # delay command
Ex:always@(posedge clk) begin
#20 a=c;
end

Cannot use initial block in your design.
Ex: module count(clk,c);
initial begin
c=0;
end
Cannot use the same reg in different always blocks.
Ex: always@(posedge clk) begin
a=c;
end
always@(posedge clk or negedge reset) begin
a=d; end
# delay cannot be
synthesis to gate
Initial block only can be
used in testfixture
One value cannot be driven
by 2 condition
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Warning/Error Messages for Unsynthesizable Codes
The warning message like cant read verilog
file will appear when opening a verilog code that
cannot be synthesized by Synopsys Design Vision.
Carefully check the messages when warned during
synthesis and then make corresponding
modifications.
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Good Coding Style for Synthesis
Try to use always block and wire and assign
command.
When you write Verilog code, at first you must consider
the actual hardware.
always @ (posedge clk) Flip-Flop
always @ (posedge clk or posedge reset) Flip-Flop with Reset
if (reset)
always @ (a or b) Latch or Combinational
wire a=(c=1)?b:d; Mux
wire a=b*c; Combinational
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Unknown Simulation Results
Testfixture doesnt have $sdf_annotate declaration
Your testfixture file must have :
initial $sdf_annotate( g-bist4b4hs2.sdf ,bist_sd);
Timing violation
How can it happen? (a FlipFlop)
Try to slow down the
clock or re-design
clk
D
Q
How can it happen? ( a Latch)
En
in
out
Try to re-design
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Blocking and Non-Blocking (1/2)
Using blocking assignments within combinational always
block
always @(a or b or x) begin
x = a & b;
y = x | b;
x = a;
end
you
expect
always @(a or b or x) begin
x<=a & b;
y<=x | b;
x<=a;
end
May not meet
what you expect
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Blocking and Non-Blocking (2/2)
Using nonblocking assignments within sequential always
block
always @(posedge clock) begin
x <= a;
y <= x;
z <= y;
end
you
expect
always @(posedge clock) begin
x = a;
y = x;
z = y;
end
May not meet
what you expect
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Conclusions
Logic synthesis transforms verilog codes to
gate-level netlists at a more realistic level.
The EDA tool, Synopsys Design Vision, helps
users to synthesize their own designs
according to default/user specified
conditions/constraints.
Good coding styles lead to synthesizable
designs that meet specifications.
Art of Writing TestBenches
http://www.asic-world.com/verilog/art_testbench_writing.html
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Synopsys Documentation
On Line documentation in Synopsys Web Site:
http://www.synopsys.com/support/dotw.html
Off Line documentation (DIR: \usr\cad\synopsys\doc\online\dc\...)
Use Tool Option Menu Help Design Vision Online Help