C

o v e r i f y o
http://coverify.com info@coverify.com +91-124-4086612
Open Source Verification Language
with UVM and MULTICORE Support
l ang
About Vlang
Vlang is an open source, high productivity, high
performance, multi-paradigm verification lan-
guage built on top of Dprogramming language.
Vlang Features at a Glance
Multicore Vlang enables concurrent program-
ming. End user can fine-tune the number
of concurrently running threads at module
level. Vlang also enables concurrency at
a higher abstraction by allowing multiple
simulators running in parallel.
Constrained Randomization Full blown and ei-
cient. Concurrency enabled.
UVMCompliance Word-to-word translation of
SystemVerilog UVM. More eicient and
user-friendly due to generic programming.
Object Oriented Programming Support for func-
tion/operator overloading.
Safety and Productivity Automatic Garbage Col-
lection. Exception Handling. Unittests.
Systems Programming Allows lowlevel access to
hardware resources. Allows embedded as-
sembly language.
Interface with other Languages Full blown C++
interface. VHPI/VPI bindings with VHDL and
SystemVerilog.
Licensing Provided free under open source boost
license. Vlang UVMlibrary is available under
Apache2 license.
Documentation
http://vlang.org
Development
http://github.com/coverify/vlang
http://github.com/coverify/vlang-uvm
Maintainer
Puneet Goel <puneet@vlang.org>
Moore's lawis dead! Long live Amdahl's law!!
Does your Verification IP Scale?
Till year 2005 (thanks to the good health of Moore's Lawback then), pro-
cessor speed would double every year and a half. As a result you did not
have todoanything toget a faster verificationenvironment for your next
(bigger) chip. But since then, processors have stopped running faster.
Instead processor companies are putting more processor cores in the
servers. In another couple of years, servers running your functional re-
gression are projected to have more than a hundred processor cores.
And if you do not change the way you verify, you will be utilizing pre-
cisely one of these hundred processors.
You want to change that? Give Vlang a try
Verification with Vlang
Even as the chip complexity keeps increasing, we continue to rely on
same old RTL methodology to design our chips. As a result the abstrac-
tiongapbetweenthedesignandthespecificationis increasingexponen-
tially.
Vlang attempts to bridge this gap by providing you a high productivity
and high performance verification environment.
Verilog
VHDL
SystemVerilog
SystemC VLANG
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PRODUCTIVITY & SAFETY
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TIME & EFFORT
Higher Productivity
helps you start
early
Higher Performance
helps you cover
faster
Higher Productivity means that you take less time in building your veri-
fication infrastructure and higher performance means that your regres-
sion runs much faster.
If you have ESL as part of your SoC development flow, there are addi-
tional reasons that youshoulduseVlangtoverifyyour ESLmodels. Vlang
supports much better integration with C++ compared to SystemVerilog.
Vlang is ABI compatible with C/C++. Vlang also allows you to call any
method (including virtual methods) on C++ objects right from Vlang
without any boilerplate code. In comparison SystemVerilog DPI inter-
face is limited to C language. As a result any interface between SystemC
and SystemVerilog tends to be highly ineicient.
Yet another advantage is that Vlang is free and open source just like your
SystemC simulator.
C
o v e r i f y o
http://coverify.com info@coverify.com +91-124-4086612
Vlang Features
Feature Vlang
System-
Verilog
SystemC Remarks
Performance Enablers
Concurrent Threads Yes No No Use -version=MULTICORE to enable
Multiple Concurrent Simulators Yes No No
Native Compilation Yes No Yes
Generic Library Support Yes No Yes No standard library for SV
Coding Productivity
Compile Time Fastest Slow Fast
Incremental Compile Yes Partial Yes Huge elaboration time for SV
Pointer-less Programming Yes Yes No
Automatic Garbage Collection Yes Yes No
Every significant language born afer year 2000
provides for a decent GC
User-friendly Containers Yes Yes No
Associative arrays vs C++ std::map<>
[][] vs multi-dimensional vectors in C++
Runtime Safety
Array Bound Check Yes No No
Check for Integral Overflow Yes No No
Support for Unittests builtin library library Vlang supports localized Unittests.
Exception Handling Yes No Yes
Contract-based Programming Yes No No
Systems Programming Features
Low level hardware/device ac-
cess
Yes No Yes Essential for Virtual Platforms andCoverification
Custommemory allocation Yes No Yes
Eicient File IO Yes No Yes
Parsing tools/libraries Yes No Yes SV can not parse even XML by itself
Embedded Assembly Code Yes No Yes
Reflections and Generative Programming
Support for Data Introspection
and Reflections
Yes No No Very useful for UVMautomation
Generative and Metaprogram-
ming Support
Yes No Limited
UVMSupport
Base Class Libraries Yes Yes Yes
Support for Sequences Yes Yes Limited SystemC lacks randomize with
Register Abstraction Layer No Yes No RAL package for Vlang is under development
TLM1 Support Yes Yes Yes
TLM2 Support No Yes Yes
TLM2 support in SystemVerilog is limited
Support for Vlang TLM2 in the works
Verification Features
Transaction Randomization Yes Yes Limited
SystemC relies on external constraint libraries,
none of which is user friendly
Sequence Randomization Yes Yes No
Coverage Support No Yes No
Coverage will be available in next release of
Vlang