Class: 11ES

Group 1:
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1. Introduction
In this report, we will handle the third part of the Lab. It is Part 3:
Executing a Design from a Set of Requirement. Firstly, we will show the
Verilog codes for implementation. Next, we use Modelsim for
simulation to prove our code works properly. Then we indicate the
procedure of how we can download the Verilog codes to the board
Altera DE1.



2. Implementation


Inputs:
SYSON: the photographic system is turned on.
TAKE: capture the currently selected image.
SELFLASH: enable the advanced built-in light system.
NOFLASH: sensor that detects that the use of artificial lighting is
prohibited.
~INFOCUS: sensor that detects if the image is in focus.
~LOWLIGHT: sensor that detects a low ambient light condition.

The inputs SYSON, TAKE, SELFLASH, and NOFLASH, are
active high.
The inputs, ~INFOCUS and ~LOWLIGHT are active low.
Outputs:
Four outputs: ~CAPTURE, ~OUTOFFOCUS, ~FLASH, and
~THERMO are active low.


From the conditions in Operation section of Lab 2 Instruction (page
5), we have a compact truth table.


Condition
sysOn take selFlash noFlash _inFocus
(~inFocus)
_lowLight
(~lowLight)
Capture output
is asserted
(_capture=0)
1 1 0 X 1 0
1 1 1 0 1 1
Out of focus
output is
asserted
(_outFocus=0)

1 1 X X 0 X
Flash output is
asserted
(_flash=0)
1 1 1 0 1 X
1 1 X 0 1 1
Thermonuclear
device output
is asserted
(_thermo=0)
1 1 1 1 X X
We apply technique POS (product of sums) to write verilog code to
implement the Cameras functions. The codes are in the following page.



Verilog Code: These codes are from the file Camera.v







Module Camera contains:
Input: sysOn, take, selFlash, noFlash, _inFocus (~inFocus),
_lowLight (~lowLight).
Output: _capture (~Capture), _outFocus (~OutOfFocus), _flash
(~Flash), _thermo (~ThermoNuclearDevice).
We also create module TestBench for simulation.
In the initial block, we concatenate all the inputs to be a 6bit
(6b000000) input.
Then in the always block, we make that 6bit input increases its
value by 1 after every 5 unit times.

Simulation:


The screenshot indicates one case that sysOn=1, take=1, selFlash=0,
noFlash=0, _inFocus=1 and _lowLight=0. The table and the screenshot
both show the same results for 4 outputs (_capture=0, _outFocus=1,
_flash=1 and _thermo=1).

Then we take another case when sysOn=1, take=1, selFlash=1,
noFlash=1, _inFocus=0 and _lowLight=0.

Again, the values of simulation match the ones from the table, which are
_capture=1, _outFocus=0, _flash=1 and _thermo=0. Obviously, the
result is correct.
From two screenshots displayed above, we can conclude that our
Verilog code works perfectly.
After doing the simulation on Modelsim, we use Quartus to download
the Verilog code to the board Altera DE1. Here is the procedure.

Step 1: We create a project named Camera. During this step, we
choose a device: Cyclone II EP2C20F484C7.

Step 2: We add file Camera.v (only module Camera) into the
project and compile it.

Step 3: After completing the compilation, we follow this path
Assignments-> Pin Planner to open Pin Planner window in
order to assign inputs and outputs to switches and leds of the
board.




Step 4: We compile the module again and go to the Programmer
window (Tools-> Programmer). After choosing the proper
hardware, we click Start and wait for Quartus to download the
codes to the board. This is our configuration on Altera DE1.


We take an example that already mentioned above. The inputs are:
sysOn=1, take=1, selFlash=1, noFlash=1, _inFocus=0 and _lowLight=0.
The outputs are: _capture=1, _outFocus=0, _flash=1 and _thermo=0.
From the board, led3 (_capture) and led1 (_flash) are turned on while
led2 (_outFocus) and led0 (_thermo) are off, which indicates the value
1010 as showed in the second screenshot of simulation.
We continued to test with other cases and the board always showed the
accurate results. Thus, we can conclude that our codes are correct and
the board works properly.