IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO.

3, MARCH 2010 189

Enhancement-Mode GaN MIS-HEMTs With
n-GaN/i-AlN/n-GaN Triple Cap Layer and
High-k Gate Dielectrics
Masahito Kanamura, Toshihiro Ohki, Toshihide Kikkawa, Kenji Imanishi,
Tadahiro Imada, Atsushi Yamada, and Naoki Hara
AbstractThis letter presents details of high-performance
enhancement-mode GaN MIS high-electron-mobility transistor
(MIS-HEMT) devices. Devices with an n-GaN/i-AlN/n-GaN triple
cap layer, a recessed-gate structure, and high-k gate dielectrics
show high drain current and complete enhancement-mode opera-
tion. The maximum drain current and threshold voltage (V
th
) are
800 mA/mm and +3 V, respectively. These results indicate that a
recessed AlGaN/GaN MIS-HEMT with the triple cap could be a
promising new technology for future device applications.
Index TermsALD, enhancement mode, GaN, MIS high-
electron-mobility transistor (MIS-HEMT).
I. INTRODUCTION
D
EVICES that are GaN-based are attractive candidates for
high-power applications such as next-generation wireless
base stations and power switching devices [1]. For wireless
base station applications, high-efciency WiMAX base stations
using GaN high-electron-mobility transistor (HEMT) ampli-
ers have already been released. On the other hand, there are
several issues that must be solved for GaN-based power switch-
ing applications. Generally, power electronic devices need to
have low ON-resistance, high OFF-state breakdown voltage, and
large current handling capabilities. GaN HEMT is suitable for
these power devices because of its excellent material parame-
ters. However, the conventional GaN HEMT is unsuitable for
enhancement-mode operation due to its strong piezoelectric ef-
fect. Therefore, many reported devices showed a V
th
of around
0 V, despite a relatively high drain current (I
ds
) being obtained.
In order to obtain an enhancement-mode operation, it is effec-
tive to use a MOSFET structure. However, MOSFET devices
which make use of an inverted channel suffer from a low drain
current due to their low electron mobility. There are several
approaches to realizing an enhancement-mode operation for
GaN HEMTs such as a gate-recess structure, F-treatment [2],
[14], and an introduction of a cap layer [3]. In this experiment,
to realize an enhancement-mode operation and improve the
transfer characteristics, a combination of a recessed-gate and
an insulated-gate structure was used.
Manuscript received October 28, 2009; revised December 3, 2009. First
published February 8, 2010; current version published February 24, 2010. The
review of this letter was arranged by Editor J. A. del Alamo.
The authors are with Fujitsu Laboratories Ltd., Atsugi 243-0197, Japan
(e-mail: kanamura.masahi@jp.fujitsu.com).
Color versions of one or more of the gures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/LED.2009.2039026
Fig. 1. Schematic cross-sectional view of an AlGaN/GaN MIS-HEMT with a
triple cap layer, a recessed-gate structure, and high-k dielectrics.
II. DEVICE FABRICATION
An AlGaN/GaN MIS-HEMT structure was grown on a
3-in Si-SiC substrate using the MOCVD method. Fig. 1 shows
the cross-sectional view of the GaN MIS-HEMT structure
used in this work. We introduced an n-GaN (2 nm, N
d
=
2 10
18
cm
3
)/i-AlN (2 nm)/n-GaN (2 nm, N
d
= 2
10
18
cm
3
) thin triple cap layer on the n-AlGaN (20 nm,
Al: 20%, N
d
= 2 10
18
cm
3
)/i-GaN (1 m) heterostruc-
ture. This triple cap layer was effective in enhancing the device
performance [4]. The upper n-GaN layer was introduced to
keep a smooth surface morphology by terminating the surface
without an Al-containing layer. The role of the inserted i-AlN
layer is to increase the 2DEG density using the piezoelectric
effect between the i-AlN and lower n-GaN layer. In this struc-
ture, the 2DEG density increased by 80% compared to that of
the conventional AlGaN/GaN HEMT with an n-GaN cap. The
sheet resistance was 500 /sq. This value was 20% lower than
our conventional n-GaN/AlGaN/i-GaN structure.
The device process started with device isolation by ion
implantation. The ohmic and gate electrodes were Ti/Al and
Ni/Au, respectively. The typical gate length and gate width
were 0.8 and 40 m, respectively. The gate-to-drain space was
5 m. Prior to gate metal deposition, gate-recess etching was
carried out by Cl-based RIE and deposition of 20-nm Al
2
O
3
gate dielectrics by plasma-enhanced ALD at 350

C. The ALD
method is superior to the CVD method in terms of surface
roughness and lm thickness control. TMA and an O
2
plasma
were used as the metal precursor and oxidant, respectively.
After deposition, the lm was annealed at 650

C for 1 min.
0741-3106/$26.00 2010 IEEE

190 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 3, MARCH 2010
Fig. 2. V
th
dependence of the gate-recess etching depth for an AlGaN/GaN
MIS-HEMT. The gate width was 40 m.
Fig. 3. Drain current and transconductance as a function of gate voltage.
MIS-HEMT. The gate width was 40 m.
In this letter, intentional surface treatment was not carried out
before deposition.
III. DEVICE PERFORMANCE
Fig. 2 shows the V
th
dependence of the gate-recess etching
depth. As the recess etching depth increases, V
th
changes
linearly, and devices show enhancement-mode operation at a
recess etching deeper than 14 nm.
The I
ds
V
gs
characteristics for the recessed and nonrecessed
devices are shown in Fig. 3. The gate-recessed structure dra-
matically changed the V
th
from 5.8 to +3 V without any
degradation of the maximum drain current. The recessed GaN
MIS-HEMT clearly shows the enhancement-mode operation
with a high maximum drain current of 800 mA/mm at V
gs
=
10 V. The drain current at V
gs
= 0 V was 9 A/mm. The
maximum transconductance was 155 mS/mm. The gate-recess
etching depth was 24 nm.
The suppression of dc-to-RF dispersion (current collapse)
is a key issue for the GaN-based devices. We investigated the
dispersion characteristics using a DiVA
TM
265 dynamic pulsed
IV analyzer. Fig. 4 shows a result of the pulsed IV mea-
surements. We carried out the measurements under two initial
bias conditions of (V
gs
, V
ds
) = (0 V, 0 V) and (V
gs
, V
ds
) =
(0 V, 50 V) to evaluate the effect of the interface trap on the
ON-resistance. The pulsewidth and pulse separation were 1 s
and 1 ms, respectively.
The drain current at V
ds
= 10 V and V
gs
= 10 V under
a pulsed stress condition of (V
gs
, V
ds
) = (0 V, 50 V) was
735 mA/mm. This value was only 5% lower than that of
(V
gs
, V
ds
) = (0 V, 0 V). These pulsed IV results indicate
that the fabricated enhancement-mode MIS-HEMT has good
interface quality, leading to a very small dc-to-RF dispersion.
Fig. 4. Pulsed IV characteristics under two bias conditions. The pulsewidth
was 1 s, and the pulse separation was 1 ms. The initial bias points were
(V
ds
, V
gs
) = (0 V, 0 V) and (50 V, 0 V). The gate width was 40 m.
Fig. 5. Three-terminal OFF-state breakdown characteristics. The gate width
was 40 m.
Fig. 6. Benchmark of I
ds
and V
th
for GaN-based FETs with a breakdown
voltage over 90 V.
From these measurements, the ON-resistance of 6.2 mm was
obtained.
The two-terminal gate-to-drain leakage current was 1 nA/mm
at V
gd
= 100 V. The three-terminal OFF-state breakdown char-
acteristics are shown in Fig. 5. An OFF-state breakdown voltage
of 320 V was obtained at V
gs
= 0 V. The gate-to-drain space is
5 m.
Fig. 6 shows the benchmark of I
ds
and V
th
for the published
enhancement-mode GaN FETs which have high three-terminal
breakdown voltages over 90 V [5][13]. Both a high I
ds
of
800 mA/mm and a V
th
of 3 V were achieved in this work.
IV. CONCLUSION
This letter has presented a demonstration of enhancement-
mode GaN MIS-HEMTs with a high drain current of
800 mA/mm at V
gs
= 10 V and a threshold voltage of 3 V. The
introduction of an n-GaN/i-AlN/n-GaN triple cap layer, gate-
recess etching, and atomic-layer-deposited high-k dielectrics

KANAMURA et al.: ENHANCEMENT-MODE GaN MIS-HEMTs 191
leads to the enhancement of the device performance. The three-
terminal OFF-state breakdown voltage was 320 V.
ACKNOWLEDGMENT
The authors would like to thank Dr. N. Okamoto,
K. Makiyama, and Dr. K. Joshin for the fabrication support and
useful discussion.
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