Bangalore Off: # 68, 15th Cross, 1st Block, R. T.

Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
Description
WARP v3 Kit
WARP v3 is the latest generation of WARP hardware, integrating a high performance FPGA, two
flexible RF interfaces and multiple peripherals to facilitate rapid prototyping of custom wireless designs.


Key Features:
Xilinx Virtex-6 LX240T FPGA
(XC6LX240T-2FFG1156C)
2 programmable RF interfaces, each with:
MAX2829 2.4/5GHz transceiver
AD9963 ADC/DAC (12-bit resolution; 170MSps DACs, 100MSps ADCs)
Dual-band PA (20dBm Tx power)
Shared clocking for MIMO applications
2 10/100/1000 Ethernet interfaces (Marvell 88E1121R dual-PHY)
FMC HPC slot
DDR3 SO-DIMM slot (2GB SO-DIMM included with kit)
FPGA configuration via JTAG, SD card or on-board flash
User I/O:






Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
USB-UART (FTDI FT230X)
12 LEDs
2 seven-segment displays
4 push buttons
4-bit DIP switch
16-bit 2.5v I/O header
FPGA
At the heart of WARP v3 is a Virtex-6 FPGA (LX240T), which provides a significant boost in processing
power over previous generations of WARP hardware. The table below summarizes the FPGA resources
available across hardware generations.
FPGA Resources
Resource
WARP v3
XC6VLX240T
WARP v2
XC4VFX100
WARP v1
XC2VP70
Slice LUTs
150,720
6-input LUTs
84,352
4-input LUTs
66,176
4-input LUTs
Slice Registers 301,440 84,352 66,176
Block RAMs
832
RAMB18E1
376
RAMB16
328
RAMB16
Multipliers
768
DSP48E1
160
DSP48
328
MUTLT18
For a real-world example of the resource boost with the Virtex-6 FPGA, we ported the WARP OFDM
Reference Design to WARP v3. The table below summarizes the resource usage of the design across all






Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
three generations of WARP hardware.
FPGA Resource Utilization: OFDM Reference Design
Resource
WARP v3
XC6VLX240T
WARP v2
XC4VFX100
WARP v1
XC2VP70
Slice LUTs 27% 60% 71%
Slice Registers 12% 39% 60%
Block RAMs 40% 78% 91%
Multipliers 19% 97% 59%
For the detailed breakdown of resource usage across hardware versions, we've posted the MAP design
summariesfor the OFDM reference design across all three FPGAs.
This comparison is somewhat conservative. The WARP v3 port uses a MicroBlaze processor in place of
the hard PPC405 cores in WARP v1/v2 and integrates no design optimizations for the new FPGA (like
faster clocking for more resource sharing in the PHY). Real-world applications optimized for the Virtex-6
would realize even more benefit from the extra resources.
RF Interfaces
The RF interfaces on WARP v3 operate in the 2.4 and 5GHz bands with up to 40MHz bandwidth each.
The digital I/Q interfaces are tied directly to the FPGA, enabling fully programmable waveform generation
and processing. The two interfaces share sampling and RF reference clocks to enable MIMO applications.
Kit Contents






Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
The WARP v3 kit contains:
WARP v3 board (hardware rev 1.1)
2GB DDR3 SO-DIMM
SD card (pre-formatted)
Power supply (100-240VAC to 12VDC)
2 50 ohm SMA terminators
The WARP v3 kit does not include antennas or RF cables. We found that users' applications vary too
widely to standardize on any one antenna. We have had good experiences with antennas from L-com and
cables/attenuators from Pasternack and Crystek. The RF connectors on WARP v3 are standard polarity
SMA jacks.
The WARP v3 kit also does not include a JTAG programming cable. We recommend the Digilent XUP-
USB-JTAG orJTAG-HS1. Both are supported by the Xilinx tools and connect directly to the JTAG
connector on the WARP v3 board. It is possible to configure the WARP v3 FPGA using only the SD card.
However we strongly recommend having a JTAG cable to enable real-time debugging via the Xilinx SDK
and ChipScope Analyzer.














Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125

ADD-ON-MODULES FOR WARP V3
FMC-RF-2X245: Dual-Radio FMC Module
The FMC-RF-2X245 is an FMC module with integrates two fully programmable RF interfaces. This
module is designed to enable 4-radio designs on WARP v3.


Key Features:
2 programmable RF interfaces, each with:
o MAX2829 2.4/5GHz transceiver
o AD9963 ADC/DAC (12-bit resolution; 170MSps DACs, 100MSps ADCs)
o Dual-band PA (20dBm Tx power)
o Shared clocking for MIMO applications
4 SATA connectors for board-to-board multi-gigabit links







Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
RF Interfaces
The RF interfaces on the FMC-RF-2X245 module are based on the same design as the RF interfaces
on the WARP v3 board. Each interface operates in the 2.4 and 5GHz bands with up to 40MHz
bandwidth. The digital I/Q interfaces are tied directly to the FMC header, enabling fully
programmable waveform generation and processing. The two interfaces share sampling and RF
reference clocks to enable MIMO applications. Both clocks are driven by the host WARP v3 hoard
via the FMC connector. Building a 4-radio node requires only a WARP v3 kit and the FMC-RF-
2X245 module.
Additional Documentation
FMC-RF-2X245 User Guide
WARP v3 User Guide
FMC-RF-2X245 Schematics
FMC-BB-4DA: Quad-DAC FMC Module

The FMC-BB-4DA is an FMC module with four digital-to-analog (DAC) channels. The module is
built around two AD9116 12-bit dual-DACs. This module is designed to enable real-time observation
and debugging of PHY signals on WARP v3 kits.


Key Features:
4 digital-to-analog (DAC) channels (12 bits, 125MSps max)
Independent clocking per DAC pair (one clock per AD9116 IC)
Parallel digital interfaces for easy design integration
1 Vp-p analog outputs (digital [0,1] maps to [0,1]v)






Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125
MCX jacks for analog connections
IIC EEPROM (per FMC standard)
Compatible with FMC LPC and HPC carriers
CM-MMCX: WARP v3 Clock Module with MMCX connectors
The CM-MMCX is a simple clock module for WARP v3 which enables sourcing and sinking the
sampling and RF reference clocks.


Key Features:
Coaxial (MMCX) connectors for:
o RF reference clock input
o RF reference clock output
o Sampling clock input
o Sampling clock output
2-position switch (tied to FPGA I/O)
Clock I/O
The CM-MMCX module provides connectors for sourcing and sinking the WARP v3 node's RF
reference and sampling clocks. Each clock signal is routed to an MMCX connector. All four signals
are connected directly to the WARP v3 clock buffers. See the WARP v3 clocking user guide for more
details on these buffers.
The CM-MMCX module is available with either MMCX jacks or MMCX plugs. The image below
illustrates the options:






Bangalore Off: # 68, 15th Cross, 1st Block, R. T. Nagar, Bangalore 32
PH: +91-080-23535125, Fax: +91-080-23535125



For most WARP v3 users we recommend the version with MMCX jacks, allowing use of readily-
available cable assemblies with MMCX plugs (like Digi-Key J735-ND).
The version with MMCX plugs is available for users needing to share clocks between a WARP v3 kit
and a WARP v1/v2 kit. The original WARP Clock Board (on WARP v1/v2 kits) uses MMCX plugs
for clock I/O. The corresponding cable assemblies (with MMCX jacks) are usually special order.
Additional Documentation
CM-MMCX User Guide
WARP v3 User Guide
CM-MMCX Schematics