ARM Processor Course Report Analysis

SEMESTER CLOSING REPORT - SCR
Course: ARM Processor[EC424]

Semester : VII semester Division : A,B Duration: 16 weeks ( 20/08/2013 06/12/2013)
Course Teacher : Mr. Sunil S. Mathad Department : Electronics & Communication
No. of Classes held : 43 % of syllabus covered : 100 %
Topics not covered and reasons : - NA -

General Information / observations:

1. General opinion about the text book from students was,
it was like a handbook.
2. One from a generation as a typical model like, they have
studied 8051 as a typical example of microcontroller
would have been matter .i.e A base on A RM7TDMI
processor then additional chapter just depicting the
further enhancements or changes on to the basic model.
3. Some concepts not directly related to ARM, more
related to Computer architecture such as Memory and
Cache were difficult to convey, as somewhere there is a
feeling Computer Architecture should be a Prerequisite.
4. Unless there are labs or Practical students will not be
able to appreciate the subject.
5. Some kind of self-drive is required by the students to
learn the subject.
Recommendations for deletion from syllabus:

Not Recommended
Recommendations for addition to syllabus:

Project Based teaching learning with another course which may be an
application/product development will make the subject interesting as well as
prominent.

Submitted to DUGC- ECE Dept. Signature of the Faculty Member

PEOs POs COs
CAT-1 CAT-2 CAT-3 Average
Match SUPPORT CONFIDENCE Match SUPPORT CONFIDENCE Match SUPPORT CONFIDENCE SUPPORT CONFIDENCE
I, II,III C,J 1,6,5 51.93 70.086 63.12 77.97 55.32 75.91 56.79 57.26
I,II K 2,4 - - 75 68.35 - - 60.37
73.26
III D,K 3,4 - - - - - 45.74 78.16 45.74
78.16
VII Semester
Division A
Attempted
Attempted
Satisfactorly Attempted
Attempted
Attempted
Attempted
Attempted
Attempted
Satisfactorly
1 2SD10EC003 Achyut Patil 0 0 0 0 0 0 0 0 0 0 0 0
2 2SD10EC004 Adarsh R Kulkarni 1 1 1 1 1 0 0 0 1 1 1 0
4 2SD10EC006 Ajit nadumani 0 0 0 0 0 0 0 0 0 0 0 0
5 2SD10EC009 Anand Ilkal 0 0 0 0 0 0 0 0 0 0 0 0
6 2SD10EC012 Miss.Anusha K R 0 0 0 0 1 1 1 1 1 1 0
7 2SD10EC013 Miss.Arati R Katekar 1 1 1 1 0 0 0 0 1 0 1 0
8 2SD10EC014 Miss.Ashwini S Doddamani 1 1 1 1 0 0 0 0 0 0 0 0
9 2SD10EC017 Chaitanya A Kulkarni 1 1 1 1 0 0 0 0 1 0 1 1
10 2SD10EC019 Miss.Manojna C H 1 1 1 1 0 0 0 0 1 1 1 1
11 2SD10EC020 Chinnappa P. kalyal 1 1 1 1 0 0 0 0 1 0 1 0
12 2SD10EC023 Durgappa 0 0 0 0 1 1 1 1 1 0 1 0
13 2SD10EC026 Govind Kumar Mali 1 1 1 1 0 0 0 0 1 0 1 0
14 2SD10EC028 Guru Shashank H N 0 0 0 0 0 0 0 0 0 0 0 0
15 2SD10EC029 Hanamant Nagappa Mangasuli 1 1 1 1 0 0 0 0 1 0 1 0
16 2SD10EC037 J.V. Manjunath 1 1 1 1 0 0 0 0 0 0 0 0
17 2SD10EC043 Miss.Karishma Kunder 0 0 0 0 1 1 1 1 1 0 1 1
18 2SD10EC045 Kunal Karan 0 0 0 0 1 0 1 1 1 0 1 1
19 2SD10EC048 Mahamedyusoof M 1 1 1 1 0 0 0 0 1 1 1 1
20 2SD10EC055 Miss.Medha R. 1 1 1 1 0 0 0 0 1 0 0 0
21 2SD10EC057 Shreyas Anil Nadagouda 1 0 1 0 0 0 0 0 0 0 1 1
22 2SD10EC059 Naik Avinash Y 0 0 0 0 1 1 1 1 1 0 0 0
23 2SD10EC065 Nikit Mahesh Gadag 1 0 1 1 0 0 0 0 1 0 1 1
24 2SD10EC123 Miss.Kamalaxi N Naganur 1 1 1 1 0 0 0 0 1 0 1 0
25 2SD11EC401 Amaresh Chavadi 1 0 1 1 0 0 0 0 1 0 1 0
26 2SD11EC414 Maltesh Pujar 1 1 1 1 0 0 0 0 0 0 1 0
27 2SD11EC426 Sachin Revannavar 0 0 1 1 0 0 0 0 0 0 0 0
28 2SD11EC432 ShivarajKumar Sonnad 1 1 1 1 0 0 0 0 0 0 1 1
29 2SD11EC434 Sunil B Bilagi 1 0 0 0 1 1 1 0 0 0 1 0
30 2SD11EC435 Sunil Kumar M Ijeri 0 0 0 0 1 1 1 1 0 0 1 0
31 2SD09EC067 PraveenKumar V Bhave 1 1 1 0 0 0 0 0 1 0 0 0
32 2SD10EC068 Nitesh Mahto 0 0 0 0 1 1 1 1 1 1 1 0
33 2SD10EC071 Miss.Poornima M 1 1 1 1 0 0 0 0 1 1 1 1
34 2SD10EC072 Pradeep Singh Yadav 0 0 0 0 1 1 1 1 1 0 1 0
35 2SD10EC078 Rajkumar M Walikar 1 1 1 1 0 0 0 0 1 0 1 1
36 2SD10EC079 Miss.Raksha S. 0 0 0 0 0 0 0 0 0 0 0 0
37 2SD10EC086 Ravikiran B Desai 0 0 0 0 1 1 1 1 1 1 1 1
38 2SD10EC092 Sandeep Kumar 1 1 1 1 0 0 0 0 1 0 1 0
39 2SD10EC093 Sangeet Suman 0 0 0 0 0 0 0 0 0 0 0 0
40 2SD10EC096 Sarvesh Anand 0 0 0 0 1 1 1 1 0 0 1 0
41 2SD10EC099 Shashank Jagadish 1 1 1 1 0 0 0 0 1 0 1 0
42 2SD10EC100 Shashank N Hegde 1 1 1 1 0 0 0 0 1 0 1 0
43 2SD10EC049 Miss.Maitri R Patil 0 0 1 1 1 1 0 0 1 0 1 0
44 2SD10EC113 Miss.Varsha D Shiveshwar 1 1 1 1 0 0 0 0 1 0 1 0
45 2SD10EC118 Vinay S G 0 0 0 0 1 1 1 1 0 0 1 0
46 2SD11EC400 Ali Asgar N Ritti 0 0 0 0 1 1 1 1 1 1 1 0
47 2SD11EC420 Naveen Kumar Hosmani 1 1 1 1 0 0 0 0 1 1 1 1
48 2SD11EC429 Satish Kumbari 0 0 0 0 1 1 1 1 1 0 1 1
26 22 27 25 16 14 14 13 31 8 35 13
strength 55.3191 56.25 33.3333 29.1667 64.5833 72.9167
confidence 84.6154 92.5926 87.5 92.8571 25.8065 37.1429
Avg Strength 51.9282
Avg Confidence 70.0857
CO: 1 PO: c,j
CAT-I
CO: c,j PO: CO: c,j PO: CO: c,j PO:
S.D.M College of Engineering & Technology, Dharwad
Worksheet for CLOCAM
Sl.NO USN
Q1.a Q1.b Q2.a Q2.b Q3.a Q3.b
CO: c,j PO: Name of the Candidates CO: 1 PO: c,j
VII Semester
Division A
Attempted
Attempted
Attempted
Attempted
Attempted
Attempted
Attempted
Satisfactorly
4 2SD10EC009 Anand Ilkal 1 1 1 1 0 0 0 0 1 0 1 1
5 2SD10EC012 Miss.Anusha K R 0 0 0 0 1 0 1 0 1 0 1 1
11 2SD10EC023 Durgappa 1 1 1 0 0 0 0 0 1 0 1 0
17 2SD10EC045 Kunal Karan 1 1 1 1 0 0 0 0 1 0 1 0
19 2SD10EC055 Miss.Medha R. 0 0 0 1 1 1 1 0 1 0 1 1
26 2SD11EC426 Sachin Revannavar
0 0 1 1 0 0 0 0 0 0 0 0
28 2SD11EC434 Sunil B Bilagi
0 0 0 0 1 1 1 1 1 0 1 1
29 2SD11EC435 Sunil Kumar M Ijeri
0 0 0 0 1 1 1 1 1 0 1 1
42 2SD10EC049 Miss.Maitri R Patil
0 0 0 0 1 1 1 1 1 0 1 0
44 2SD10EC118 Vinay S G 0 0 0 0 1 1 1 1 1 0 1 1
45 2SD11EC400 Ali Asgar N Ritti
1 1 1 1 0 0 0 0 1 0 1 1
46 2SD11EC420 Naveen Kumar Hosmani
1 1 1 1 0 0 0 0 1 0 1 1
47 2SD11EC429 Satish Kumbari
1 1 1 1 0 0 0 0 1 0 1 1
18 17 19 19 29 27 27 25 43 7 42 30
Strength 38.29787 40.42553 61.70213 57.44681 91.48936 89.3617 75
Confidence 94.44444 100 93.10345 92.59259 16.27907 71.42857 68.35092
CO: c,j PO:
CAT-II
Sl.NO USN
CO: c,j PO: Name of the Candidates CO: 1 PO: c,j CO: 1 PO: c,j CO: c,j PO: CO: c,j PO:
VII Semester
Division A
Attempted
Attempted
Satisfactorl
y Attempted
Attempted
Attempted
Attempted
Attempted
Attempted
Satisfactorly
4 2SD10EC009 Anand Ilkal 1 1 1 1 0 0 0 0 1 1 1 1
5 2SD10EC012 Miss.Anusha K R 1 1 1 1 0 0 0 0 1 0 1 1
11 2SD10EC023 Durgappa 1 0 1 1 0 0 0 0 1 0 1 1
17 2SD10EC045 Kunal Karan 1 0 0 0 1 1 1 1 1 0 1 0
19 2SD10EC055 Miss.Medha R. 1 0 1 1 0 0 0 0 1 1 1 1
26 2SD11EC426 Sachin Revannavar 1 1 1 1 0 0 0 0 1 1 1 1
28 2SD11EC434 Sunil B Bilagi 1 1 1 0 0 0 0 0 1 1 1 1
29 2SD11EC435 Sunil Kumar M Ijeri 1 1 1 1 0 0 0 0 1 1 1 1
42 2SD10EC049 Miss.Maitri R Patil 1 0 0 0 1 1 0 0 1 0 1 0
44 2SD10EC118 Vinay S G 1 1 1 1 0 0 0 0 1 1 1 1
45 2SD11EC400 Ali Asgar N Ritti 1 1 1 1 0 0 0 0 1 1 1 1
46 2SD11EC420 Naveen Kumar Hosmani 1 1 1 1 0 0 0 0 1 1 1 1
47 2SD11EC429 Satish Kumbari 1 0 1 1 0 0 0 0 0 0 0 0
37 24 31 30 5 3 5 4 38 29 40 31
Strength 78.7234 65.9574 10.6383 10.6383 80.85106 85.10638
Confidence 64.8649 96.7742 60 80 76.31579 77.5
CO: c,j PO:
CAT-III
Sl.NO USN
CO: c,j PO: Name of the Candidates CO: 1 PO: c,j CO: 1 PO: c,j CO: c,j PO: CO: c,j PO:
SDM College of Engineering and Technology, Dharwad
Department of Electronics and Communication
B.E. Electronics and Communication Engineering
Continuous Assessment Test-I
Semester: VII Date: 21/09/2013
Course Title: ARM Processors
Course Code: EC424 Duration: 60 min
Course Instructor: Mr.Sunil S Mathad. Max Marks: 20

All Questions carry equal marks
1. Describe Instruction Set for Embedded Systems with respect to ARM Design Philosophy.
Or
Describe Embedded System Hardware with ARM based embedded Device as an example
2. Elaborate upon ARM processor modes and banked registers with complete ARM register set.
Or
Explain about Memory hierarchy, type, width with respect to embedded systems taking ARM
based system as an example.
3. Briefly explain about the ARM Nomenclature. If an ARM processor is numbered as ARM926EJ-
S what can be inferred from the numbers.
----x----

Or
Or
3. Briefly explain about the ARM Nomenclature. If an ARM processor is numbered as ARM926EJ-
S what can be inferred from the numbers.
----x----
Continuous Assessment Test-I I

Q3 is compulsory. Answer anyone from Q1 and Q2
1. A) Brief about ARM Program Status Register(PSR) along with the fields, neatly depicting their
positions in the bit pattern. 4M
B) Demonstrate the usage of LDR and SDR instructions for single byte, halfword and Word
transfer. 6M
OR
2. A) Write an Assembly language Program to compute GCD of two numbers 5M
B) Tabulate the summary of thumb register usage 5M
3. A) With an example explain ARM-Thumb interleaving 5M
B) Elaborate upon addressing methods for stack operations 5M

----x----

Continuous Assessment Test-II

positions in the bit pattern. 4M
B) Demonstrate the usage of LDR and SDR instructions for single byte, halfword and Word
transfer. 6M
OR

----x----

Continuous Assessment Test-III

1. A) Elaborate upon efficient use of C types 5M

B) With a flow chart explain the working of nested interrupt handler. 5M

OR
2. A) Explain about the Prioritized Direct Interrupt Handler 4M
B) For the following piece of structures draw the memory layouts 6M
(i) struct {
char a;
int b;
char c;
short d;
}
(ii) struct {
char a;
char c;
short d;
int b;
}

(iii)__packed struct {
char a;
int b;
char c;
short d;
}

3. A) Elaborate upon writing loops efficiently in C for ARM 5M
B) Explain about the IRQ and FIQ exceptions. What makes FIQ different from IRQ ? why FIQ
is Fast Interrupt Request? 5M


The ARM instruction set differs from the pure RISC definition in several ways that make
the ARM instruction set suitable for embedded applications:
Variable cycle execution for certain instructionsNot every ARM instruction executes in
a single cycle. For example, load-store-multiple instructions vary in the number of execution
cycles depending upon the number of registers being transferred. The transfer can occur on
sequential memory addresses, which increases performance since sequential memory
accesses are often faster than random accesses. Code density is also improved since multiple
register transfers are common operations at the start and end of functions.
Inline barrel shifter leading to more complex instructionsThe inline barrel shifter is a
hardware component that preprocesses one of the input registers before it is used by a n
instruction. This expands the capability of many instructions to improve core performance
and code density.
Thumb 16-bit instruction setARM enhanced the processor core by adding a second 16-
bit instruction set called Thumb that permits the ARM core to execute either 16- or 32-bit
instructions. The 16-bit instructions improve code density by about 30% over 32-bit fixed-
length instructions.
Conditional executionAn instruction is only executed when a specific condition has been
satisfied. This feature improves performance and code density by r educing branch
instructions.
Enhanced instructionsThe enhanced digital signal processor (DSP) instructions were
added to the standard ARM instruction set to support fast 1616-bit multiplier operations and
saturation. These instructions allow a f aster-performing ARM processor in some cases to
replace the traditional combinations of a processor plus a DSP.
Or


Or
Hierarchy

Type
ROM, Flash ROM,DRAM, SRAM, SDRAM
Width
The memory width is the number of bits the memory returns on each accesstypically
8, 16, 32, or 64 bits. The memory width has a direct effect on the overall performance and
cost ratio.

3. a . Briefly explain about the ARM Nomenclature. If an ARM processor is numbered as
ARM926EJ-S what can be inferred from the numbers.

ARM926EJ-S
9-Family
2-Cache and MMU
6-include tightly coupled SRAM memory
b. Explain about the Interrupts and Exceptions of ARM processors
Reset vector is the location of the first instruction executed by the processor when power is
applied. This instruction branches to the initialization code.

Undefined instruction vector is used when the processor cannot decode an instruction.

Software interrupt vector is called when you execute a SWI instruction. The SWI instruction is
frequently used as the mechanism to invoke an operating system routine.

Prefetch abort vector occurs when the processor attempts to fetch an instruction from an address
without the correct access permissions. The actual abort occurs in the decode stage.

Data abort vector is similar to a prefetch abort but is raised when an instruction attempts to
access data memory without the correct access permissions.

Interrupt request vector is used by external hardware to interrupt the normal execution flow of
the processor. It can only be raised if IRQs are not masked in the cpsr.

Priority
Address Exception type Exception Mode (1=high,6=low)
0x00000000 Reset Supervisor 1
0x00000004 Undefined instruction Undefined 6
0x00000008 Software Interrupt Supervisor 6
0x0000000C Abort (prefetch) Abort 5
0x00000010 Abort (data) Abort 2
0x00000014 Reserved Reserved Not applicable
0x00000018 IRQ IRQ 4
0x0000001C FIQ FIQ 3


positions in the bit pattern.

B) Demonstrate the usage of LDR and STR instructions for single byte, halfword and Word
transfer. 6M

OR

Or
gcd
CMP r1, r2
SUBGT r1, r1, r2
SUBLT r2, r2, r1
BNE gcd

Summary of Thumb register usage.
Registers Access
r0r7 fully accessible
r8r12 only accessible by MOV, ADD, and CMP
r13 sp limited accessibility
r14 lr limited accessibility
r15 pc limited accessibility
cpsr only indirect access
spsr no access
return address in the link register lr:
CODE32
LDR r0, =thumbRoutine+1 ; enter Thumb state
BLX r0 ; jump to Thumb code
; continue here
CODE16
thumbRoutine
ADD r1, #1
BX r14 ; return to ARM code and state

Continuous Assessment Test-III

1. A) Elaborate upon efficient use of C types 5M
The Efficient Use of C Types
For local variables held in registers, dont use a char or short type unless 8-bit or 16-bit
modular arithmetic is necessary. Use the signed or unsigned int types instead. Unsigned
types are faster when you use divisions.
For array entries and global variables held in main memory, use the type with the
smallest size possible to hold the required data. This saves memory footprint. The ARMv4
architecture is efficient at loading and storing all data widths provided you traverse arrays by
incrementing the array pointer. Avoid using offsets from the base of the array with short type
arrays, as LDRH does not support this.
Use explicit casts when reading array entries or global variables into local variables,
or writing local variables out to array entries. The casts make it clear that for fast operation
you are taking a narrow width type stored in memory and expanding it to a wider type in the
registers. Switch on implicit narrowing cast warnings in the compiler to detect implicit casts.
Avoid implicit or explicit narrowing casts in expressions because they usually cost
extra cycles. Casts on loads or stores are usually free because the load or store instruction
performs the cast for you.
Avoid char and short types for function arguments or return values. Instead use the int
type even if the range of the parameter is smaller. This prevents the compiler performing
unnecessary casts.

B) With a flow chart explain the working of nested interrupt handler. 5M

OR
2. A) Explain about the Prioritized Direct Interrupt Handler 4M
Prioritized Direct Interrupt Handler
Handles higher-priority interrupts in a shorter time. Goes directly to the specific ISR.
Low interrupt latency.
Advantage: uses a single jump and saves valuable cycles to go to the ISR.
Disadvantage: each ISR has a mechanism to set the external interrupt mask to stop
lower- priority interrupts from halting the current ISR, which adds extra code to each ISR

B) For the following piece of structures draw the memory layouts 6M
(i) struct {
char a;
int b;
char c;
short d;
}

(ii) struct {
char a;
char c;
short d;
int b;
}

(iii)__packed struct {
char a;
int b;
char c;
short d;
}

3. A) Elaborate upon writing loops efficiently in C for ARM 5M

Writing Loops Efficiently
Use loops that count down to zero. Then the compiler does not need to allocate
a register to hold the termination value, and the comparison with zero is free.
Use unsigned loop counters by default and the continuation condition i!=0
rather than i>0. This will ensure that the loop overhead is only two instructions.
Use do-while loops rather than for loops when you know the loop will iterate at
least once. This saves the compiler checking to see if the loop count is zero.
Unroll important loops to reduce the loop overhead. Do not overunroll. If the
loop overhead is small as a proportion of the total, then unrolling will increase
code size and hurt the performance of the cache.
Try to arrange that the number of elements in arrays are multiples of four or
eight. You can then unroll loops easily by two, four, or eight times without
worrying about the leftover array elements.

B) Explain about the IRQ and FIQ exceptions. What makes FIQ different from IRQ ? why FIQ
is Fast Interrupt Request? 5M

An IRQ or FIQ exception causes the processor hardware to go through a standard
procedure (provided the interrupts are not masked):
1. The processor changes to a specific interrupt request mode, which reflects the
interrupt being raised.
2. The previous modes cpsr is saved into the spsr of the new interrupt request
mode.
3. The pc is saved in the lr of the new interrupt request mode.
4. Interrupt/s are disabledeither the IRQ or both IRQ and FIQ exceptions are
disabled in the cpsr. This immediately stops another interrupt request of the same
type being raised.
5. The processor branches to a specific entry in the vector table.

FIQ has more banked registers and hence context saving latency can be avoided and
while serving FIQ service routine it disables further IRQ and FIQs and known or predictable
latency.

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SEMESTER CLOSING REPORT - SCR

Course: ARM Processor[EC424]

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