P2-2

Boosting the on-current of silicon nanowire tunnel-FETs

1,2Anne S. Verhulst, 1,2W.G. Vandenberghe, 1,3Stefan De Gendt, 2Karen Maex and 1,2Guido Groeseneken
JlMEC, Kapeldreef75, 3001 Leuven, Belgium; 2Department of Electrical Engineering, K.U.Leuven, Kasteelpark Arenberg 10,
3001 Leuven, Belgium; 3Department of Chemistry, Kcl.Ll.euven, Celestijnenlaan 200 D, 3001 Leuven, Belgium
Abstract
Tunnel-FETs are potential successors of MOSFETs because
of the absence of short-channel effects and of a subthreshold-
slope limit. As a solution to the low on-currents reported for
silicon-based tunnel devices, we have simulated both gate
configuration modifications as well as source material modifi-
cations. These modifications are ideally suited for implemen-
tations in vertical nanowire-based transistor architectures. We
demonstrate that the on-current of a silicon tunnel-FET with a
germanium heterojunction at the source reaches the same lev-
el as state-of-the-art MOSFET's.
Introduction
One of the most promising candidates to replace the MOS-
FET in future technology nodes is the tunnel-FET (TFET) [1-
3]. Due to its built-in tunnel barrier, the TFET does not suffer
from short-channel effects. Moreover, the subthreshold slope
of TFETs is not limited to 60 mVIdec, the physical limit of
MOSFETs, such that the supply voltage may be further re-
duced. The major advantage of the TFET concept is that both
effects result in decreased power consumption, and therefore
allow a higher on-chip device density. This advantage can be
especially exploited in vertical nanowire-based transistor im-
plementations with 3-dimensional stacking capability (see
Fig. I). At the same time, the structural similarity of the
TFET with the MOSFET has resulted in TFET implementa-
tions with standard CMOS processing techniques [I].
The biggest problem of silicon TFETs, however, is their low-
er on-currents than silicon MOSFETs, which is due to the
small tunneling efficiency in silicon. The purpose of our pa-
per is to investigate both gate and material modifications to
the conventional TFET in order to boost the on-current. These
investigations are based on device simulations with MEDICI
[4]. We focus on TFETs with a silicon-channel, such that
practical implementations can fully exploit the existing sili-
con-expertise. Our analysis results in a nanowire-based het-
erostructure TFET with an on-current in the order of 0.5
mA/J.1m effective width at an off-current of 1 nA/J.1m, which
is of the same level as the competing MOSFET device.
Simulation parameters
For our conceptual investigation, we have used the ITRS
2003 spec for low-operating power: = 60 nm, Vdd = 1 V
(-? V
ds
= 1 V), Ion = 0.5 mA/J.1m, Ioff = I nA/J.1m. The TFET
has a double-gate configuration (see Fig. 2(a) [5]. Other pa-
rameters are N
source
= N
drain
= 1020/cc, Nchannel = 101S/cc, tdielectric =
4 nm (Hf02) , tchannel = 100 run.
Gate modifications
A. Short-gate (Fig. 2(b))
The short-gate concept is briefly summarized, as it returns in
the remainder of the analysis, but this gate modification does
not affect the on-current. The gate of a TFET can be short-
ened without affecting the de-performance in the normal op-
erating regime [3]. For the TFET under consideration (Lgale =
60 nm).. shortening of the gate down to = 15 nm is possi-
ble, resulting in a decrease of the gate delay with a factor 4.
The short-gate configuration therefore has the same effect on
gate delay as an increased on-current.
B. Shifted-gate
As a second gate modification, we have shifted the gate over
the source (see Fig. 2(c)). This results in an additional line-
tunneling component inside the source region, which boosts
the on-current [6,7]. In Fig. 3, the de-performance of TFETs
with a gate-shift of 40 om is shown for different source dop-
ing levels. Even though the shifted-gate TFETs display cur-
rent increases with a factor 10 to 50, for the most relevant
doping levels (N
source
= 1020/cc) the current boost is pushed
outside the supply voltage window of I V (Fig. 3).
Heterostructure TFET
In order to boost the on-current of the TFET, the material of
the TFET can be changed: the on-current of an all-germanium
TFET is about 100 times larger than the on-current of an all-
silicon TFET for the configuration of our analysis (see Fig.
4). This is due to the lower tunneling probability in silicon
caused by its larger bandgap (EG,Si = 1.12 eV, EG,Ge = 0.66 eV)
and larger reduced mass (mr.Si ;::::: 3mr.Ge). The all-Ge TFET,
however, also has high off-currents (see Fig. 4) and the fabri-
cation of high-quality Ge-compatible gate dielectrics is not as
mature as the fabrication of Si-compatible gate dielectrics.
Since we only focus on TFET configurations with a Si-chan-
nel, we have introduced a Ge/Si heterojunction at the source
(see Fig. 2(d)). Such material modifications can be imple-
mented in nanowire-based configurations, where high-quality
heterostructures can be formed.
Fig. 5 shows the de-performance of a Si-TFET with SioGet-
source (Si-Ge, has all properties of Si but with the bandgap of
Ge). As can be seen, the on-current of this device is the same
as the on-current of the all-SizGe, TFET. A detailed analysis
of the device's band structure shows that this is due to the al-
most identical position of the valence band in the source re-
gion and of the conduction band in the channel region (which
is gate-controlled) for both configurations, such that the tun-
nel probability from source to channel is similar as well. Fig.
6 then displays that the Ge-source TFET has an even larger
on-current than the SioGel-source TFET. A detailed analysis
shows that this is mainly due to the beneficial difference in
electron affinity between Si and Ge. The on-current of the
Ge-source TFET is more than a factor 10 larger then the on-
current of the all-Si TFET. Most importantly, the on-current
is up to the same level of about 0.5 mA/J.1m effective width as
the MOSFET, while the off-current is at the required specifi-
cation of I nA/J,lm [5].
Summary and conclusions
The on-curent of a silicon-based TFET can be boosted with
over an order of magnitude to the same level as the MOSFET
when vertical nanowire-based transistor implementations are
used with high-quality heterostructures. Only the source ma-
terial of such a TFET is modified such that a Si-compatible
gate dielectric can be used on the Si-channel. This result re-
moves the major drawback of Si-based TFETs, while main-
taining its largest advantage of low power consumption. On
the other hand, a short-gate and shifted-gate setup result re-
spectively in speed increases and modest current increases.
.. ...s,OGe, TFET I
_ ..SioGe,-source TFET
References:
[I) T. Nirschl, et ai, "The tunneling field effect transistor (TFET) as
an add-on for ultra-low-voltage analog and digital processes",
IEDM,2004.
[2J J. Appenzeller, YoM. Lin, J. Knoch , Z. Chen, and P. Avouris,
"Compari ng carbon nanotube transistors - The ideal choice: a novel
tunneling device design", IEEE Trans. Elec. Dev., Vol. 52, pp. 2568
- 2576 , 2005 .
[3) A.S. Verhulst, W.G. Vandenberghe, K. Maex, and G. Groe-
seneken, "Tunnel field-effect transistor without gate-drain overlap",
Appl. Phys. Lett., Vol 91, pp. 0531021-3,2007.
[4) MEDICI , Synopsys, v. 2007.03. Earlier versions of this program
give incorrect solutions for TFETs including a heterostructure.
[5J The simulated current per unit width for a double-gate configura-
tion is twice the effective current per unit width .
[6) W.G. Vandenberghe. A.S. Verhulst, G. Groeseneken, B. Soree,
and W. Magnus. "Analytical model for a tunnel field-effect transis-
tor". accepted for IEEE MELECON 2008.
[7) P-F Wang, "Complementary tunneling-FETs (CTFET) in CMOS
technology". Ph.D. thesis, TV Munchen, Germany, 2003 .
gate dielectric
gate or source/drain electrode
n-doped source/drain region
Cd p-dopedsource/drain region
D intrinsic channel region
Acknowledgements: the authors acknowledge W. Magnus for use-
ful discussions. A. Verhulst acknowledges the support of a Marie
Curie International Reintegration Grant within the 6
th
European
Community Framework Programme, as well as a postdoctoral fel-
lowship of the Fund for Scientific Research - Flanders. This work
was also supported by IMEC's Industrial Affiliation Program.
j 10\0 j
- I
j
10
20
l \ GSi TFETI i

0.5
vgsM
Fig. 4. Simulated dc output characteristics of an all-Si TFET and an all-
Ge TFET. The 1,,-V.' curve of the all-Ge TFET is shifted to the left with
150 mV for better comparison.
,......- .
.,. ... .......
<.
-,\/
!
".....J
E
Ge. s ource TFET
.._SioGe ( source TFET
- all-Si TFET
0.5
10"
-0.5 0 0.5 1.5
VgsM
Fig. 5. Simulated dc output characteristics of an all-Si-Ge, TFET and a
Si-TFET with SioGe,-source (with SisGe, an artificial material with the
bandgap of germanium, but with all other properties of silicon).
0.5
Vgs [V]
Fig. 6. (a) Simulated de output characteristics of a Si-TFET with Ge-
source and with SioGet-source and an all-Si TFET. (b) Zoom-in of Fig.
7(a) with a left-shift of the all-Si curve. The dashed lines indicate the
ITRS targets of1_ and L for the MOSFET, while the black rectangle in-
dicate a potential operating regime given that V... =I V.
onset point
tunnel ing
_ conv. gate N
s
=: 10
20
/ cc . L
g
= 60 nm
....... - N
s
= 2.10
1
' /CC
gggg N
s
= lOI '/CC
- shift. gate N
s
= 10
20/cc
- shift of 40 nm
......... N
s
= 2.10
1
' /cc
gggg N
s
= 10
1
'/ ce
Fig. I. Illustration of 3D-stacking capability of vertical nanowire-based
transistors.
(a) (b) (e) (d)
Fig. 2. (a) ConventionalTFET (= gated pin-diode). (b) Short-gateTFET. (c)
Shifted-gateTFET. (d) Heterostructure TFET(dashed p-doped region out of
other semiconductor material (e.g. Ge) thansolid i- and n-dopedregions (e.g.
Si)). Same materialcoloringas in Fig. I.
0.5 0 0.5 1.5
Vgs M
Fig. 3. Simulated de output characteristicsof conventional TFET compared
to shifted-gateTFET for 3 values of sourcedopingN
s
.