3- IogIques u tvunsIstovs MOS

1- Ruppe!s tecLno!ogIques, mod!IsutIon

2- Invevseuvs MOS. IogIque NMOS
3- IogIque CMOS
4- IonctIons !ogIques CMOS
Circuito intgro numriqueo
- IrIncIos
- Irocoss CMOS
- !ogIos do dossIn
- TochnoIogIo CMOS: fondnncos
- IndusfrIo du somIconducfour
- IncnsuInfIon
IOGIQ\S A TRANSISTORS MOS : IABRICATION
S CIRC\ITS INTGRS (vuppe!s tecLno!ogIques)
IA IIIIR SIIICI\M
LINGOT 5" - 6" - 7" - 8"
(Croissance cristalline)
DECOUPE DES TRANCHE
(Wafer)
FONDERIE
(Process)
PURIFICATION
(Fusion de zone)
DECOUPE
ENCAPSULATION
(Packaging)
SABLE
Si
300mm
ssentIu!
Iov Cost
IIectIven
ess
300mm
200mm
Capacity and Cost Benefits: more die/wafer
lower cost per die
Capacity and Cost Benefits: more die/wafer Capacity and Cost Benefits: more die/wafer
lower cost per die lower cost per die
Tvends In ownscu!Ing
SiIicon
Foundry
Integruted Circuit Design und Munufucturing
Chip
Pockoging
Tesf
IC
"Specificutions"
"Loyouf"
Design
HW
SW
Munufucturing
Euros /
mm
Z
Conception d 'un circuit intgr spcifique : tupes
Niveau
CIRCUIT
architecture
Niveau
Physique
Niveau
Systme
Niveau
Logique
?
Co-design
Matriel/Logiciel
Synthse
architecturale
Synthse
physique
APPLICATION
SPECIFICATIONS
P
R
O
C
E
S
S
E
U
R
M
E
M
ASIC
M
E
M
ASIC
FABRICATION
Synthse
logique
oxidation
optical
mask
process
step
photoresist coating photoresist
removal (ashing)
spin, rinse, dry
acid etch
photoresist
stepper exposure
development
Typical operations in a single
photolithographic cycle (from [Fullman]).
PLoto-IItLogvupLIc Pvocess
Figure 1,1u : Etupes de fubricution d'un inverseur CMOS
Subsfrof n
Mosque de puifs
Mosque de ;one ocfive
Mosque de poIysiIicium
Subsfrof n
Subsfrof n
Puifs p
Figure 1,1b : Etupes de fubricution d'un inverseur CMOS
Mosque de diffusion p
Mosque de diffusion n
Mosque de confocf
Subsfrof n
Subsfrof n
Subsfrof n
Mosque de mefoI
Subsfrof n
Techno, CMOS
Mosque de puifs
Mosque de ;one
ocfive
Mosque de
poIysiIicium
Mosque de
diffusion p
Mosque de
diffusion n
Mosque de
confocf
Mosque de
mefoI
n+ n+
substrat p
S G D
V
GS
-V
T
V
DS
V
GS
I
D
L
W
Druin Source
SriIIe

CunuI
Modle ?
TvunsIstov MOS
L = 0,28m
W = 1m
tox = 10nm
Oxyde (SiO2)
Diffusion N (Silicium dop N)
Poly (Silicium polycristallin)
Alu 1 (Premire couche)
P-
N+
L
W
ox
t
3 PevspectIve
Pn!ysI!Icnn
A!umInum
Teono1ogg speed Teono1ogg speed J J L J J L
2 2
Source Source
DraIn DraIn
Gate Gate
CbanneI CbanneI
TransIstor = EIementary BIock
TransIstor = EIementary BIock TransIstor = EIementary BIock
L L
DIeIectrIc (SIO DIeIectrIc (SIO
2 2
) )
MOSFT (Me1o1 MOSFT (Me1o1 - - O1de O1de - - Sem1oonduo1or) Sem1oonduo1or)
CRR S TRANSISTORS MOS u gvI!!e
"po!ysI!IcIum"
POLYSILICIUM
ZONE DOPEE
D
L < 0,5m
100
IMPLANTATION IONIQUE
DEPOT
POLYSILICIUM
CRATION S TRANSISTORS
POLYSILICIUM
ZONE DOPEE
essIn des musques
S
D
Vue en coupe
CRATION S TRANSISTORS
POLYSILICIUM
ZONE DOPEE
S
D
CRATION S TRANSISTORS
POLYSILICIUM
ZONE DOPEE
S
D
CROISSANC '\N OXY 'ISOIATION
POLYSILICIUM
ZONE DOPEE
S
D
PRCAG S CONTACTS
CONTACT
POLYSILICIUM
ZONE DOPEE
S
D
POT 'AI\MINI\M : PRMIR NIVA\
'INTRCONNXION
ALU1
POLYSILICIUM
ZONE DOPEE
CONTACT
S
D
POT '\N OXY 'ISOIATION
S
D
S
D
ALU1
POLYSILICIUM
ZONE DOPEE
CONTACT
PRCAG S VIAS
S
D
VIA
ALU1
POLYSILICIUM
ZONE DOPEE
CONTACT
POT 'AI\MINI\M : SCON NIVA\
'INTRCONNXION
S
D
ALU2
VIA
ALU1
POLYSILICIUM
ZONE DOPEE
CONTACT
SSIN S MASQ\S T PHOTO '\N POINT MMOIR
IntevIuce between desIgnev und
pvocess engIneev
GuIde!Ines Iov constvuctIng pvocess
musks
\nIt dImensIon: MInImum !Ine
wIdtL
oculuhle deoign ruleo: lumhdu
purumeter
uhoolute dimenoiono (micron
Rg!es de dessIn des musques
tecLno!ogIques ("desIgn vu!es")
CMOS Pvocess Iuyevs
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+)
Green
Iuyevs In 0.25 m CMOS
pvocess
Intvu-Iuyev esIgn Ru!es
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
DiIIerent Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
TvunsIstov Iuyout
1
2
5
3
T
r
a
n
s
i
s
t
o
r
VIus und Contucts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
Se!ect Iuyev
1
3 3
2
2
2
Well
Substrate
Select
3
5
CMOS Invevtev Iuyout
A A`
n
p-substrate Field
Oxide
p

In
Out
GND V
DD
(a) Layout
(b) Cross-Section along A-A`
A
A`
Iuyout dItov
esIgn Ru!e CLeckev
poly_not_fet to all_diff minimum spacing = 0.14 um.
StIcks Iugvum
1
3
In
Out
V
DD
GND
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by
compaction program
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
V
out2
vo!utIons
de !u
tecLno!ogIe
CMOS
A Modevn CMOS Pvocess
p-well n-well
p
p-epi
SiO
2
AlCu
poly
n
SiO
2
p
gate-oxide
Tungsten
TiSi
2
Dual Dual- -Well Trench Well Trench- -Isolated CMOS Process Isolated CMOS Process
009 m LM
> 100 MT
> 3 SHz
Techno, CMOS : Z004
, > Z010
00 m {0nm}
> 4 ST
> 10 SHz
Advunced Metu!!IzutIon
Advunced Metu!!IzutIon
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1980 1990 2000 2010
4004
8080
8086
8008
Pentium Processor
486DX Processor
386Processor
286
Pentium II Processor
Pentium III Processor
Pentium 4 Processor
0.18 m 0.13 m
Heading toward 1 billion transistors in 2007
Moove's Iuw
Intel is doubling transistors every 2 years
Intel is doubling transistors every 2 years
Tho Mooro's !nw rojocfIon
x
# Transistors
per Die
1980
ItaniumTM
PentiumR4
1985
PentiumRIII
4G
2G
1G
512M
256M
128M
64M
256K
16M
64K
4M
16K
1M
1M
1B
100M
10M
1K
PentiumRII
Pentium
I486TM
I386TM
80286
8086
8080
4004
1K
10K
100K
10B
1995 1990 1975 1970 2000 2005
Memory
Microprocessor
Before 75
projection
Ref : Intel Dev Forum Feb 03
1 MHz
1 GHz
The number of transistors on chip double each 18 months.."
Gordon Moore Circa 1975
100 MHz
10 MHz
x
2


e
a
c
h
2

y
e
a
r
s
IBM Power 4
TvunsIstovs
0,001
0,01
0,1
1
10
100
1000
1970 1980 1990 2000 2010 2020
Million
Transistors
1 Billion
Transistors
8080
8086
386
Pentium proc
Pentium 4 proc
There will be billion transistor integration capacity
There will be billion transistor integration capacity There will be billion transistor integration capacity
90 nm
130 nm
180 nm
250 nm
500 nm
Rduction de la taille des circuits
TochnIquos fo nchIovo confInunfIon of fho Mooro's Inw
SOI devices
deliver higher
performance
at same litho
generation
and Vdd
Bulk CMOS and Al interconnect: Performance saturates
because of device nonscalability and interconnect delay
1
10
1995 2000 2005
Copper and low-k
dielectric reduce
interconnect delay
Low
Temperature
(-30C)CMOS
Functional
Integration :
embedded DRAM
circuit/architecture
Innovations
2010 2015
Relative performance
Double Gate FET - 3D
?
New structures are needed to maintain CMOS device performance...
Iocu!It et g!obu!It
Sources. Motorola, Universitv of Illinois, and Silicon Metrics
Temperature Map
30 C change

7 change in delay & slew
S
l
e
w
1emperature
Voltage (IR Drop)
5 voltage change

15 change in slew
S
l
e
w
Joltage
50 density change

15 change in slew
Transistor Density
S
l
e
w
1ransistor Density
Scu!Ing oI ImensIons
Gate
Source Drain
Body
L
Tox
Gate
Source Drain
Body
L
Tox
Gate
Source Drain
Body
L
Tox
Gate
Source Drain
Body
L
Tox
Gate
Source Drain
Body
0.7 L
0.7 Tox
Gate
Source Drain
Body
0.7 L
0.7 Tox
Gate
Source Drain
Body
0.7 L
0.7 Tox
Gate
Source Drain
Body
0.7 L
0.7 Tox
1
1
0.49
0.49
0.7
0.7
0.7
0.7
1
1
1
1
1 Freq
1 Delay
=
=
43 . 1
7 . 0
1
Freq
7 . 0 Delay
=

30nm Prototype
(IEDM2000)
20nm Prototype
(VLSI2001)
25 nm
15nm
15nm Prototype 15nm Prototype
(IEDM2001) (IEDM2001)
50nm Length
(IEDM2002)
65nm Node
2005
45nm Node
2007
90nm Node
2003
32nm Node
2009
22nm Node
2011
10nm Prototype 10nm Prototype
(ITJ 2002) (ITJ 2002)
Inte!'s TvunsIstov ReseuvcL In
eep NunotecLno!ogy Spuce
Experimental transistors for Experimental transistors for
future process generations future process generations
Introducing a new
Introducing a new
process generation
process generation
every 2 years
every 2 years
Inte!'s 15 nm Bu!k
TvunsIstov
25 nm
15nm
R. Chau et al., IEDM 2000
0
100
200
300
400
500
0 0.2 0.4 0.6 0.8
Drain Voltage (V)
D
r
a
i
n

C
u
r
r
e
n
t

(

A
/

m
)
Vg = 0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
Intels 15nm NMOS
0
100
200
300
400
500
0 0.2 0.4 0.6 0.8
Drain Voltage (V)
D
r
a
i
n

C
u
r
r
e
n
t

(

A
/

m
)
Vg = 0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
Intels 15nm NMOS
50nm 50nm
Transistor for Transistor for
90nm Process 90nm Process
Source: Intel Source: Intel
Influenza virus Influenza virus
Source: CDC Source: CDC
100nm 100nm
SI!Icon evIces SLvInk to VIvus SIze
90nm process is deep in
90nm process is deep in
nanotechnology era
nanotechnology era

Si-epi
S/D
Si-channel
BOX
Poly
80nm
16 nm 16 nm Gate Gate NMOS : NMOS :
Published Published @ IEDM2001 @ IEDM2001
80 nm SON 80 nm SON
NMOS transistor NMOS transistor
0.12 m CMOS
eDRAM memory cell
0.12 m CMOS
eDRAM memory cell
BiCMOS BiCMOS SiGe SiGe:C :C
Copper Layers
Copper Layers
90 nm CMOS
High density SRAM
1.36 m2 cell
90 nm CMOS
High density SRAM
1.36 m2 cell
Acc!vutIon : de !u R& u !u IubvIcutIon
20-35% performance
gains
Scaling to sub-
100nm generations
Ultra low power
applications
Breakthrough - Silicon-On-Insulator (SOI)
Oxide

p
n+
Silicon On Insulator
No junction capacitance
No conventional silicon
MOS "body effect"
20-35% performance gain or 2-3x power
reduction for SOI over conventional silicon
at a given lithographic generation.
Float
n+
n+

p
Conventional Silicon
Gnd
n+
Cross-section schematic of a n-channel SSOI MOSFET
70% increase in electron mobility (inter Atoms distance increase)
35% electrical current increase
30% faster microprocessor with strained silicon transistors
The Near Future: Strained Si
"Strained" Silicon
Silicon Germanium
4.1?% IattIce 4.1?% IattIce
mIsmatcb between mIsmatcb between
SI SI and and Ge Ge
SI SI IattIce constraIned by IattIce constraIned by
underIyIng underIyIng SIGe SIGe
substrate substrate
"StraIned sIIIcon" (SI grown on SIGe substrate)
Increase oI cbarge carrIers mobIIIty In straIned Increase oI cbarge carrIers mobIIIty In straIned SI SI
Increased cbIp perIormances Increased cbIp perIormances
StraIned SIIIcon
StraIned SIIIcon StraIned SIIIcon
11p:JJ 11p:JJuuu.1bm.oom uuu.1bm.oomJreseoroJs111oon JreseoroJs111oon
StraIned SIIIcon In TransIstor
CbanneI
StraIned SIIIcon In TransIstor StraIned SIIIcon In TransIstor
CbanneI CbanneI
SI SI (1?S (1?S tbIck) on tbIck) on SIGe SIGe
GaIn oI ?0% In mobIIIty GaIn oI ?0% In mobIIIty
3S% Increase oI cbIp speed 3S% Increase oI cbIp speed
Enbanced PerIormances
Enbanced PerIormances Enbanced PerIormances
Iutuve PevspectIves
25 nn IINILT MOS liansisloi
3D: 60nm Double-gate Transistor (FinFET)
- Scalable to the smallest channel length
- World-record double-gate FET device performance
gate delay = 0.92 ps
Cross-section of 60 nm channel length FET
Gate Pad
(Poly Si)
Gate Line
Source
Pad
Drain
Pad
Crystal-Si
Fin
Semiconductors: more for Iess,,,
Todays semiconductors are a million
times cheaper than in the seventies
75 000 euros Price of 1 Mbit of memory
5 000 euros
400 euros
120 euros
30 euros
5 euros
0,5 euro
0,05 euro
1973
1977
1981
1984
1987
1990
1995
2000
Source : Siemens
TLe SemIconductov Industvy: oome fucto
WuIev sIze movIng to 300 mm
Iub cost IncveusIng to 2-3 IIIIIon of $
Musk cost IncveusIng to 1 MIIIIon of $
90 nm pvoductIon In 2003 wItL 3 GHz MIcvopvocessov >100 MI!!Ion
TvunsIstovs
Centre de recherche commun
ST/Philips/Motorola Crolles
300 mm / 90 nm -> 32 nm
MRAM : A tvue!y unIvevsu! memovy ?
Spintec / LETI technology
Magnetic Tunnel junction
Insulator
Pinned layer
Store layer
I
Word line
Bit line
Digit line
Coll. ST Microelectronics, ATMEL, Cvpress
DR/R~50 in 10 Oe with R~k
!es mmoIves mugntIques u uccs u!utoIve (M-RAM)
Potentiel :
M - RAM
= RAM
"universelle" ?
DRAM SRAM FLASH FeRAM OUM MRAM
Write speed Moderate Fast Slow Moderate Moderate Fast
Read speed Moderate Fast Fast Moderate Fast Fast
Density High Low High Medium High High
Endurability Good Good Poor Poor Good Good
Power High Low Low Low Low Low
Refresh Yes No No No No No
Retention No No Yes Partially Yes Yes
Scalability Bad Good Good Medium Good Good
Write/Erase
Charge
(Capacitance)
CMOS Logic Charge
(Tunneling)
Ferroelectric Phase
transition
Magnetization
Consortiums
industriels
ST Micro + Motorola
IBM + Infineon + Altis
Ind. Japonais
Atmel
Alditech

multimdia, applications spcifiques,

mmoires embarques, .
RAM haute densit
MRAM
M-RAM : WLeve ?
M-PGA ?
Novel devices
Carbon Nanotubes Carbon Nanotubes
Organic Transistors
Quantum Computing Quantum Computing
Molecular Molecular
Devices Devices
CO Molecular
Domino
2 way sort
circuit
Source . Microelectronics Advanced Research Initiative (Nanoelectronics roadmap)
Demain ?
PuckugIng
ncupsu!utIon
PUCE
(Chip, die)
BOITIER
(Package)
PATTE
(Pin, lead)
FIL DE MONTAGE
(Bond wire)
PLOT
(Pad)
PuckugIng RequIvements
IIocfrIcnI: !ow nrnsIfIcs
MochnnIcnI: !oIInbIo nnd robusf
ThormnI: IffIcIonf honf romovnI
IconomIcnI: Chon
BondIng TecLnIques
Lead Frame
Substrate
Die
Pad
Wire Bonding
Tupe-Automuted BondIng (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder Bump
Film + Pattern
Sprocket
hole
Polymer film
Lead
frame
Test
pads
I!Ip-CLIp BondIng
Solder bumps
Substrate
Die
Interconnect
layers
Puckuge-to-Bouvd Intevconnect
(a) Through-Hole Mounting
(b) SurIace Mount
Puckuge Puvumetevs
New Puckuge InnovutIons
Ihe Fockoge hos Evo|ved to Meet the
Ihe Fockoge hos Evo|ved to Meet the
Industry Cho||enges
Industry Cho||enges
H|gh H|gh
Low Low
' '75 75 ' '80 80 ' '85 85 ' '0 0 ' '5 5
Fer|ormonce Fer|ormonce
DIP
High Pwr Area Array
CPGA
BGA
MCM
Ceramic Ceramic
To Organic To Organic
Wire Wire- -bond bond
To Flip Chip To Flip Chip
Peripheral to Area Peripheral to Area
Array & Chip Scale Array & Chip Scale
Small Form Factor
PLCC
TSOP
Fine Pitch
QFP
Peripheral Array
Chip Scale
Package
QFP
IBM Power 4 RISC processor MCM packaging
Multi Chip Module: 2200 I / O, 5100 Board pads, 4 proc.
Copper
Hat
Die x4
Glass Ceramic
LGA spring connector
Board
624 W module
624 W module
85 x85 mm
85 x85 mm
Powev = Puckuge Cost
Integruted Heut
Spreuder
Heut Sink
Processor
Processor
Pins
OLSA Pins
Fun
DecoupIing
Cupucitors
Interposer
Puckuge Pins
Modern processor packaging is complex and adds signiIicantly to product cost.
Mu!tI-CLIp Modu!es
Powev Amp!IIIev Modu!e
Antenna switch, high Q inductors, variable capacitors, resonators & filters
4 to 5 Die 4 to 5 Die
1 to 1.2 mm 1 to 1.2 mm
Thick Thick
2 to 3 Die 2 to 3 Die
1.2mm 1.2mm
Thick Thick
>150 M Units >150 M Units
Shipped Shipped
Under Research Under Research
8 Die Stack 8 Die Stack
50 50 m Die m Die
75 75 m Die Thinness m Die Thinness
125 125 - - 175 175 m Die m Die
Thickness Thickness
Ultrathin Ultrathin Stacked Stacked
Chip Scale Packaging Chip Scale Packaging
2003 2003
IntegvutIon vIu PuckugIng (SIP)
STACK CHIPS