Digital Communication

Dept.
of Electronics & Telecommunication Page 1

EXPERIMENT NO. 01

Title: - The combinational circuit
Objective: - To Design, implement and Simulate logic the combinational circuit for the function

I. Practical Significance: - - A Boolean algebra is an algebraic system consisting of the set {0, 1},
the binary operations lied OR, AND, or NOT denoted by the symbols "+" "." and "prime". Thus
Boolean algebra is valuable in binary variables in relation to OR, AND, and NOT operation and in
e analysis and design of all types of digital systems.

II. Competency Skill: - Simplify Logic Circuits (Mapping).
III. Experiment Objective: - To Design and verify the truth table for given function.
IV. Theoretical Background: In Boolean algebra, the system of the mathematical logic differs
from both ordinary as well as binary system.
Product term: Product term is the logical product of several variables in its true or
complemented form. Example: The term (A.B.C) is the product term; of three variables A, B,
and C in true forms where as the term (A. B.C) is the product term in its complemented forms.
Sum term: Sum term is the logical sum of several variables in its true or complemented form.
Example: The term (A+B+C) is the sum term of three variables A, B and C in its true arm where

Shri Shankaracharya Institute of Professional
Management & Technology, Raipur
DEPARMENT OF ELECTRONICS & TELECOMMUNICATION

Subject Name & Code: Digital Circuit Simulation Lab
328823(28)
Branch: ET&T Semester: 8

Dept. of Electronics & Telecommunication Page 2

as the term (A+B+C) is the sum term in its complemented form. However, the term (A+B.C) is
neither the product term nor the sum term.

Canonical Forms: Boolean algebra states that any Boolean function can be expressed either as
sum (OR) of product (AND) called (SOP) form or product (AND) of sum (OR) called (POS) form of
all the variables used in the Boolean function. However, these variables can be either in the
true (A) or complemented (A') form. Each product term in the SOP form is called the minterm.
Since each term in the SOP form is called minterm, each term in the POS is called the Maxterm.

K-Map: Karmlugh-map (Maurice_ Karmlugh) is a graphical representation of the truth table
consisting of squares or rectangular array of adjacent cells. A Boolean function utilizing 'n'
Variables require a K-map made up of 2
n
cells. Each cell possesses a unique address, specified
by the number of row and column in which the cell resides. This type of two dimensional plot
was given the name K-map in recognition of Maurice Kamaughs work.
V. Experimental Set Up: -

A B C D
1
2
3 4
5
6
7
8
9
10
11
12
13
14


VI. Resource required: - Computer and Multisim S/W

VII. Precautions: -
a) ON and 'OFF' the computer safely.
b) Draw the circuit diagram properly using Multisim Software.

VIII. Procedure: -
a) Double click the Multisim in the desktop.
b) Draw the circuit using tools in the Multisim as shown in the circuit diagram.
c) Analyzes the circuit using RUN icon or ON/OFF switch button.

IX. Observation & calculation: -

X. Result: -


XI. Interpretation of result:

XII. Conclusion: -

XIII. Experiment Related Questions. -
Q.1 What is K-MAP?
Q.2 What effect is of Don't care in design point of view?
Q3 What do you understand by universal gate?



328823(28)

EXPERIMENT NO 02.
Title: - Full Adder.
Objectives: - To Design, implement and Simulate the Full adder using two half adder.
I. Practical Significance: - The simplest combinational circuit which performs the arithmetic
addition of three binary digits.
II. Competency Skill: - Logical designing skill.
III. Experiment Objective: -Design a full adder circuit using two half adder and verify its truth
table.
IV. Theoretical Background: - A logic circuit that performs addition of three bit numbers is
referred as a full adder. A full adder circuit has three inputs and two outputs. The three inputs
are the three single-bit number X, Y and Z; and the two outputs are the sum denoted by S and
carry denoted by C.
V. Experimental Set Up: -



VII. Precautions: -
c) ON and 'OFF' the computer safely.
d) Draw the circuit diagram properly using Multisim Software.

VIII. Procedure: -
d) Double click the Multisim in the desktop.
e) Draw the circuit using tools in the Multisim as shown in the circuit diagram.
f) Analyzes the circuit using RUN icon or ON/OFF switch button.



X. Result: -


XII. Conclusion: -

Q.1 Is full Adder combinational circuit?
Q.2 What is difference between combinational circuit and sequential circuit?
Q.3 How many NAND gates required to design full adder?



328823(28)

EXPERIMENT NO 03.
Title: - 8 bit adder
Objective: - To Design, implement and Simulate the 8 bit adder using Full adder.
I. Practical Significance: - The simplest combinational circuit which performs the arithmetic 8
bit adder using Full adder.
II. Competency Skill: Logical designing skill.

III. Experiment Objective: Design a the 8 bit adder using Full adder and verify its truth table.

IV. Theoretical Background: - A logic circuit that performs subtraction of two bit numbers is
referred as a half subtractor. A half-subtractor circuit has two inputs and two outputs. The two
inputs are the two bit number X and Y and the two outputs are the difference denoted by D and
borrow denoted by B.


V. EXPERIMENTAL SET UP: -



VII. Precautions: -
A. ON and 'OFF' the computer safely.
B. Draw the circuit diagram properly using Multisim Software.

VIII. Procedure: -
A. Double click the Multisim in the desktop.
B. Draw the circuit using tools in the Multisim as shown in the circuit diagram.
C. Analyzes the circuit using RUN icon or ON/OFF switch button.


X. Result: -



XII. Conclusion: -

Q.1 what problems occur in used logic circuit in the Experiment.
Q.2 what is solution of above Qus. Problem.
Q.3 Give the IC number which is used in the experiment?



328823(28)

EXPERIMENT NO. 4
Title: - Decoder.
Objective: - To Design, implement and simulate the 3: 8 Decoder.
I. Practical Significance: - The simplest combinational circuit which performs the arithmetic the
Decoder of three binary digits. A binary code of n bits is capable of representing up to two
distinct elements of the coded information
III. Experiment Objective: Design a 3 : 8 Decoder circuit using IC and verify its truth table.
IV. Theoretical Background: A decoder is a combinational circuit that converts binary
information from n input lines into a maximum of two output lines. The decoders are also
known as binary to decimal converters. Consider the given circuit in which A and B are the
inputs. Depending on the combination of the inputs one of the output lines is high.
For e.g., if A = 0, B = 0 then the AND gate I whose inputs are A and B alone will give a high
output while all the other gates will have a low output. Thus Y
0
which is the decimal equivalent
of 0 alone is high.


V. Experimental setup: -

A B C
U4
AND3
U5
AND3
U6
AND3
U7
AND3
U8
AND3
U9
AND3
U10
AND3
U11
AND3
X1
2.5 V
X2
2.5 V
X3
2.5 V
X4
2.5 V
X5
2.5 V
X6
2.5 V
X7
2.5 V
X8
2.5 V
J4
VCC
5V


VII. Precautions: -
VIII. Procedure: -

X. Result: -



XII. Conclusion: -

Q.1 Define 3: 8 Decoder.
Q.2 What is application of Decoder?
Q3. What is the difference between a Decoder and a de-multiplexer?



328823(28)

EXPERIMENT NO 5.
Title: - 16: 1 Multiplexer
Objective: - To Design, implement and Simulate the 16 : 1 Multiplexer using 4 : 1 Multiplexer.
I. Practical Significance: Multiplexers and De-multiplexers are some of the most useful logic
devices and they can be used for numerous applications. Multiplexers can select any one of a
number of inputs and route them to a single output. De-multiplexers have a single input and
many outputs. The input of a de-multiplexer can be routed to any of the output channels. For
this reason a de-multiplexer is also known as a data distributor.
III. Experiment Objective: Design a 16 : 1 Multiplexer using 4 : 1 Multiplexer and verify its truth
table.
IV. Theory:
The term 'multiplex' means "many into one." Multiplexing is the process of transmitting a large
number of information over a single line. A digital multiplexer (MUX) is a combinational circuit
that selects one digital information from several sources and transmits the selected information
on a single Output line. A multiplexer is also called a data selector since it selects one of many
inputs and steers the information to the output.


The multiplexer has several data-input lines and a single output line. The selection of a
particular input line is controlled by a set of selection lines. The block diagram of a
multiplexer with n input lines, m select signals and one output line is shown. The selection
lines decide the number of input lines of a particular multiplexer. If the number of n input
lines is equal to 2
m
, then m select lines are required to select one of the n input lines. For
example, to select lout of 4 input lines, two select lines are required; to select I of 8 input
lines, three select lines are required and so on.
The multiplexer acts like a digitally controlled multiposition switch where binary code
applied to the select inputs, controls the data input that will be switched on to the output.
V. Experiment of set up: -


VII. Precautions: -
C. ON and 'OFF' the computer safely.
D. Draw the circuit diagram properly using Multisim Software.
VIII. Procedure: -
D. Double click the Multisim in the desktop.
E. Draw the circuit using tools in the Multisim as shown in the circuit diagram.
F. Analyzes the circuit using RUN icon or ON/OFF switch button.


X. Result:


XII. Conclusion: -

Q.1 To design 16:1 MUX how many 2:1 MUX required.
Q.2 What is application of MUX?
Q.3 What is the difference between a Encoder and a multiplexer?



328823(28)

EXPERIMENT NO. 6
Title: - Flip Flop.
Objective: - To Design, implement and simulate the Flip-Flop.
Practical Significance: - The outputs of the digital circuits considered previously are dependent
entirely on their inputs. That is, if an input changes state, an output may also change state.
However, there are requirements for a digital device or circuit whose output will remain
unchanged, once set, even if there is a change in input level(s). Such a device could be used to
store a binary number. A flip-flop is one such circuit. Flip-flops are used in the construction of
registers and counters, and in numerous other applications. The elimination of switch contact
bounce is a clever application utilizing the unique operating characteristics of flip-flops.
Competency/skill: - Logical designing skill.
Experiment Objective: - To verify the Operation of a Clocked S-R Flip Flop, J. K. Flip Flop.
Theoretical Background: - A Sequential circuit consists of a combinational circuit to which
memory elements are connected to form a feedback path. The memory elements used in
clocked sequential circuits are called flip-flops. These circuits are binary cells capable of storing
one bit of information. It has two stable states which are known as the 1 state & 0 state. It can
be obtained by using NAND or NOR gates. A flip-flop circuit has two outputs, one for normal


value & one for complement value of bit stored in it. A flip-flop can maintain a binary state as
long as power is delivered to the circuit.
S-R FLIP-FLOP:
The flip-flop has two outputs Q & Q and two inputs set & reset. By adding gates to the input of
basic circuit, flip-flop can be made to respond to input levels during the occurrence of a clock
pulse. When the clock pulse goes to 1,informatioin of S & R inputs is allowed to reach the basic
flip-flop. The set state is reached with S = 1 & R = 0 and CP = 1. To change to clear state, the
inputs must be S= 0 & R= 1, the occurrence of clock pulse causes both outs puts to momentarily
go to 0.
JK FLIP-FLOP:
The uncertainty in the states SR flip-flop ]]\when S=R=1 can be eliminated by converting it into
a JK flip-flop. A JK flip flop is an improved logic circuit of the RS flip-flop. When 1, are applied in
both J and K inputs simultaneously the flip-flop switch to compliment state that is Q=1 is
switched to Q=0 and vice-versa.

V. EXPERIMENTAL SETUP: -



VII. Precautions: -
VIII. Procedure: -


U1
U2
U3
U4
Q
Q'
K
J
CLK
CLOCKED JK FLIP-FLOP
U1
U2
U3
U4
Q
Q'
S
R
CLOCKED RS FLIP-FLOP
EN


X. Result: -


XII. Conclusion: -

Q.1 Define Clocked S-R Flip Flop and J. K. Flip Flop.
Q.2 What is the primary difference between a JK and an RS flip-flop?
Q.3 What are the applications of flip-flops?



328823(28)

EXPERIMENT NO 7.
Title: - Decade Counter.
Objective: - To Design, implement and Simulate the Decade counter using D-Flip-Flop.
I. Practical Significance: - - A decade counter is also known as mode10 counter or BCD counter.
It counts from 0 to 9. Thus, it requires 10 pulses for resetting. It is used in frequency counter,
digital voltmeters, wristwatches, etc
II. Competency/skill: - Logical designing skill.
III. Experiment Objective: - To verify the function of Decade counter and also its counting
sequence.
IV. Theoretical Background: - A decade counter is counts from 0 to 9. It requires 10 pulses for
resetting. It is seen that in many respects it is similar to a ripple counter. However, it skips the
10 to 15 states.
This is possible because on the tenth clock pulse it generates its own clear signal and resets to
0000. It uses four D flip flops, eight AND gate, four OR gate and one NAND gate. Initially, low
CLR causes Q = 0000. When CLR is high, the counter is ready to start.
It is seen that the inputs of NAND gates are 01 and 03 so that Y, the output of NAND gate is Y =
Q1Q3. The counter operates as usual while counting from 0 to 9. On the tenth clock pulse, the
output Q= 1010, i.e., both Q1 and Q3 are high. This forces Y to be low which in turn resets the
counter and its output Q = 0000. Then Y goes high and counter starts again.


(b)

Fig. . Decade counter state diagram

The circuit of decade counter skips states 10 to 15 (i.e., binary states 1010 to 1111). The
state diagram is shown in Fig. 12.4 (b). After reaching state 1001, it jumps back to 0000. How is
the countable to do this. Because of NAND gate the counter can be reset by low Y. Initially CLR
goes low t: produce

Q= 0000
When CLR goes High, the counter is ready to start. It is seen that output of NAND gate is
Y= Q3Q1
The output Y is High for the states 0000 to 1001. On the tenth clock pulse, the 0 output is
Q =1010
It is seen that now 03 and 01 are high. Therefore, Y goes Low forcing the counter to reset to
Q= 0000
Then Y goes High again and the counter is ready to start the next cycle.

The output frequency of 03 is one-tenth of the clock frequency. Thus a decade counter is divide
by 10 circuits.


V. Experimental setup: -

Decade counter using D-Flip-Flop

D D
D
D
Q0 Q0
Q1 Q2


Decade counter using D-Flip-Flop (Interfacing with 7 Segment Display using 7447N)

D Q
~Q
RESET
CLK
SET
D Q
~Q
RESET
CLK
SET
D Q
~Q
RESET
CLK
SET
D Q
~Q
RESET
CLK
SET
FF1
FF3 FF0
FF2
A
7
B
1
C
2
D
6
OA
13
OD
10
OE
9
OF
15
OC
11
OB
12
OG
14
~LT
3
~RBI
5
~BI/RBO
4
A B C D E F G
CA


VII. Precautions: -
VIII. Procedure: -

X. Result: -


XII. Conclusion: -

Q1. How many types of Counter you know?
Q2.What is application of Decade Counter?
Q3. How different decade counter by other counter?



328823(28)

EXPERIMENT NO. 8
Title: - Magnitude Comparator circuit.

Objective:. To Design, implement and Simulate the 4 bit comparator.

Practical Significance: A combinational circuit that compares the magnitudes of two quantities
in order to determine the relationship of those quantities.

Competency Skill: Logical designing skill.

Experimental Objective: Design a 4-bit parity checker circuit using IC and verify its truth table.

Theoretical Background: - The basic function of a magnitude comparator is to compare the
magnitudes of two quantities in order to determine the relationship of those quantities. In its
simplest form, a comparator circuit determines whether two numbers are equal.


The exclusive-OR gate is a basic comparator because its output is a 1 if its two input bits
are not equal and a 0 if the inputs are equal.
Experimental Setup: -

Single Bit comparator circuit
SN74LS86
SN74LS08
SN74LS08
SN7404
SN7404
A B
A = B
A < B
A > B
COMPARATOR CIRCUIT


U2
AND2
U3
AND2
U4
AND3
U5
AND3
U6
AND4
U8
AND4
U10
AND4
U11
ENOR2
U12
ENOR2
U13
ENOR2
U14
ENOR2
U15
OR4
U16
OR4
A
B
VCC
5V
VCC
A0
A3
B3
B0
U17
NOT
9
U18
NOT
U19
NOT
10
U20
NOT
12
U21
NOT
13
U22
NOT
14
U23
NOT
5
U7
AND5
U9
AND5
15
U24
NOT
11
6
18
16
1
17
3
21
22
23
24
25
26
27
28
8
7
4
2
X1
2.5 V
29
X2
2.5 V
30
20
19
X3
2.5 V
31


VII. Precautions: -

VIII. Procedure: -


X. Result: -


XII. Conclusion: -

Q.1 What are the practical applications of magnitude comparator?
Q.2 What is the IC used for 4-bit magnitude comparator?
Q.3 What is meant by a magnitude comparator?



328823(28)

EXPERIMENT NO. 9
Title: - Moore method

Objective:. To Design, implement and simulate the Finite State Machine by Moore method

I. Practical Significance: In a sequential circuit the output and the next state depend on the
present state of the circuit and the external inputs. Moore method used to represent
these circuits.


III. Experimental Objective: Design a 4-bit parity checker circuit using IC and verify its truth
table.

IV. Theoretical Background: In Moore model the next state is a function of present state
and inputs and output is action of present state. The output states are written in a
separate column. In a Moore machine the outputs depend only on the present state as shown
in Figure 2. A combinational logic block maps the inputs and the current state into the


necessary flip-flop inputs to store the appropriate next state just like Mealy machine. However,
the outputs are computed by a combinational logic block whose inputs are only the flip-flops
state outputs. The outputs change synchronously with the state transition triggered by the
active clock edge.

Figure 1: Moore Type Machine


Table: Moore Model
In this Fig shows the state diagram of Moore model. The states are shown inside the
circles as A, B, C, D. The 0 and 1 shown inside the circle represent the output which is 0 for
states A, B, C and 1 for output D.

Fig: State Diagram of Moore Model
The 0 and 1 shown along with arrows are the input E. If input 0, A remains in state A.
However, if input is 1, circuit transitions to state B (with output 0 written as B/0).
We will use JK and D flip-flops for the Moore circuit implementation. The excitation tables for JK
and D flip-flops (Table 3 & 4) are referenced to tabulate excitation table (See Table 5).


Simplifying Table 5 using maps, we get the following equations:
o JA = X.B
o KA = X
o DB =X(A + B)
o Z = A . B
There is no false output in a Moore model, since the output depends only on the state of the
flop flops, which are synchronized with clock. The outputs remain valid throughout the logic
state in Moore model.


V. Experimental Setup: -

or


VII. Precautions: -


VIII. Procedure: -


X. Result: -


XII. Conclusion: -

Q.1 What different between Moore and Mealy model?
Q2. Explain State Diagram of Moore Circuit?
Q3. Draw Mealy and Moore State Diagrams for '10' Sequence Detector?



328823(28)

EXPERIMENT NO. 10
Title: - Mealy method
Objective: To Design, implement and simulate the Finite State Machine by Mealy circuit.
I. Practical Significance: In a sequential circuit the output and the next state depend on the
present state of the circuit and the external inputs. Moore method used to represent
these circuits.
III. Experimental Objective: Design a Mealy circuit using Flip-flop IC and verify its truth table.
IV. Theoretical Background: In a Mealy machine, the outputs are a function of the present
state and the value of the inputs as shown in Figure 1.Accordingly, the outputs may change
asynchronously in response to any change in the inputs.


Figure 1: Mealy Type Machine
shown in Table outputs are written along with next states for both inputs E=0 and E=1. Fig.
shows the state diagram. Accordingly, the outputs may change asynchronously in response to
any change in the inputs. Note that there is no reset condition in the state machine that
employs two flip-flops. This means that the state machine can enter its unused state 11 on
start up. To make sure that machine gets reset ted to a valid state, we use a Reset signal. The
logic diagram for this state machine is shown in Figure 5. Note that negative edge triggered flip-
flops are used. Since the output in Mealy model is a combination of present state and input
values, an unsynchronized input with triggering clock may result in invalid output, as in the
present case. Consider the present case where input x remains high for sometime after state
AB = 10 is reached. This results in False Output, also known as Output Glitch.

Figure: Mealy State Machine for '111' Sequence Detector
V. Experimental Setup: -


VII. Precautions: -
VIII. Procedure: -

X. Result: -



XII. Conclusion: -

Q.1 Which one is the best in between Mealy and Moore model?
Q.2 Define Present and Next state?
Q3. In which place used Mealy machine?

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