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Friday, April 8, 2011

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"Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b)
Index Chapter1 Introduction Part2 Part6a Chapter2 Static Timing Analysis Part3a Part6b Part3b Part6c Part3c Part7a Chapter3 Signal Integrity Part4a Part7b Part4b Part7c Part4c Part 8 Part5a

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Part1 Part5b

Static Timing analysis is divided into several parts: Part1 -> Timing Paths Part2 -> Time Borrowing Part3a -> Basic Concept Of Setup and Hold Part3b -> Basic Concept of Setup and Hold Violation Part3c -> Practical Examples for Setup and Hold Time / Violation Part4a -> Delay - Timing Path Delay Part4b -> Delay - Interconnect Delay Models Part4c -> Delay - Wire Load Model Part5a -> Maximum Clock Frequency Part5b -> Examples to calculate the Maximum Clock Frequency for different circuits. Part 6a -> How to solve Setup and Hold Violation (basic example) Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples) Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples) Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew) Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew) Part 8 -> 10 ways to fix Setup and Hold Violation.
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Here we will discuss how to calculate the Setup and Hold Violation for a design. Till now we have discussed setup and hold violation with respect to the single flipflop, now lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2).

"Timing Paths" : Static Timing Analysis (STA) basic (Part 1) "Examples Of Setup and Hold time" : Static Timing Analysis (STA) basic (Part 3c) "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) "Time Borrowing" : Static Timing Analysis (STA) basic (Part 2)

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"Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts
Synopsys Design Constraints (SDC) Basics Antenna Effects Basic of Timing Analysis in Physical Design Delay - "Interconnect Delay Models" : Static Timing Analysis (STA) basic (Part 4b) "Delay - Timing path Delay" : Static Timing Analysis (STA) basic (Part 4a)

Single-Cycle Setup and Hold For Flip-Flops

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Few important things to note down hereData is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C. At FF2/D , input data is coming from FF1/Q through a combinational logic. Data is capturing at FF2/D, at the positive clock edge at FF2/C. So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2. So Data path is FF1/C --> FF1/Q --> FF2/D For a single cycle circuit- Signal has to be propagate through Data path in one clock cycle. Means if data is launched at time=0ns from FF1 then it should be captured at time=10ns by FF2. So for Setup analysis at FF2, Data should be stable "Ts" time before the positive edge at FF2/C. Where "Ts" is the Setup time of FF2. If Ts=0ns, then , data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=10ns. If data takes too long ( greater then 10ns) to arrive (means it is not stable before clock edge at FF2) , it is reported as Setup Violation. If Ts=1ns, then, data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=(10ns-1ns)=9ns. If data takes too long (greater then 9ns) to arrive (means it is not stable before 1ns of clock edge at FF2), it is reported as Setup Violation. For Hold Analysis at FF2, Data should be stable "Th" time after the positive edge at FF2/C. Where "Th" is the Hold time of FF2. Means there should not be any change in the Input data at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th. To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time. If Th=0.5ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5)=10.5ns ( Or say it should reach from FF1 to FF2 with in 0.5ns). If data arrive so soon (means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time=0.5ns after the clock edge at FF2), its reported Hold violation. With the above explanation I can say 2 important points: 1. Setup is check ed at next clock edge. 2. Hold is check ed at same clock edge. Setup Check timing can be more clear for the above Flip-flop combination with the help of following explanation.

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Setup Check Timing

In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation. From the Fig its clear that if Slack= Required Time - Arrival time < 0 (-ive) , then there is a Setup violation at FF2. Hold Check timing can be more clear with the help of following circuit and explanation.

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Hold Check Timing

In the above fig you can see that there is a delay in the CLK and CLKB because of the delay introduced by the series of buffer in the clock path. Now Flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2. You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violation. This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or by increasing the delay in the data path. Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path ,Gated clock, Flip-flop using different clocks, Latches in place of Flip-Flop. We will discuss all these later sometime.

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25 comments:
Anonymous February 2, 2012 at 2:57 AM should not the launch edge be the second rising edge of CLK, since hold checks are done for the same clock cycle? Reply Replies your VLSI Hi, I didn't get you question very clearly. Please elaborate it. February 7, 2012 at 10:18 AM

Anonymous May 19, 2012 at 9:20 AM dear clock checks ideally should be done at the rising or capturing edge of clock b only.. but sir has written and shown in the diagram that the data is arriving at the ff2 d before the clock b and it is in the transition region..which is a hold violation and we l loose data.. at the end sir has written that to avoid it.. either decrease the buffers in the clock path or increase the delay in the data so that the data arrives at or before the capturing edge of the clock b.. just to show the

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hold violation sir has made the same in the diagram Reply

Anonymous February 15, 2012 at 4:42 PM I think there is misprint in hold time analysis Reply Replies your VLSI February 16, 2012 at 12:10 AM

can you please let me know what's that misprint?

Anonymous April 29, 2012 at 12:46 PM 3rd Paragraph from last. It has" because of very short logic delay between FF1/Q and FF1/D" Its FF2/D

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May 2, 2012 at 11:44 AM

thanks man ... You are right.. It should be FF2/D.

power PufF! June 13, 2012 at 10:38 PM Thank you so much for the excellent tutorial, sir! Can you please correct the misprint in the original post just in case readers do not see the comment? Thanks again! Reply

hairol March 3, 2012 at 11:53 AM Thank you very much. Reply

Sravan Tekuru July 13, 2012 at 12:38 AM hi , do u have nay idea about datapulse violations Reply

jigs October 26, 2012 at 10:20 AM is setup and hold time for given input slew is constant? Reply

jigs October 26, 2012 at 10:21 AM i:e Ts+Th=constant Reply Replies your VLSI Hi Jigs, For a particular FF, these numbers are always constant. October 26, 2012 at 12:00 PM

jigs January 15, 2013 at 7:10 AM plz can u explain me ? Reply

Anonymous March 7, 2013 at 3:20 PM thank you Reply

Anonymous March 14, 2013 at 5:00 PM sir i don't understand.. setup check at next clock edge and hold check at same clock edge.. while launching and capturing edge are different.. plz explain

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Reply Replies your VLSI

"Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts

March 14, 2013 at 11:26 PM

Clock edge at Launching FF - considered as launching edge but when this edge reaches capturing FF, it become Capturing Edge. Now in setup and hold we are talking every thing on the Capturing FF, means every thing is related to Capturing edge. I hope you got my point. Still If some confusion, please write in detail about your confusion. Reply

Anonymous March 26, 2013 at 7:56 PM Thank you sir, I got your point.. Reply

Anonymous May 14, 2013 at 8:30 PM Hi VLSI Expert, You have mentioned that we need to reduce the delay of the clock to avoid the hold time violation right. Could you please clarify me if you are talking about reducing the CLKB clock width? Reply

Anonymous August 30, 2013 at 3:51 PM yyyy Reply

Anonymous October 4, 2013 at 9:18 AM In the Hold Check Timing diagram, it looks like the first transition of FF2/D (1 > 0) happens at about the same time as the first rising edge of CLKB. So this will result in setup violation (and maybe hold violation too), even before we get to the second rising edge of CLKB. Reply

mrmittal January 21, 2014 at 5:21 PM Can you please elaborate why setup check at next clock edge and hold check at same clock edge ? from CLK1 .. We check both at next clock edge and calculate also like that but why we say diffrently? Please elaborate Reply Replies Anonymous February 23, 2014 at 11:46 PM Data can arrive at the following flip flop only at the next clock edge. At T1, FF1 generated its output to data D1, whereas FF2 was processing FF1's output to data D0. FF2 will be able to process FF1's output to D1 only at the next clock edge, T2 = T1 + T(clk). Hold analysis is done only after the data has already arrived, and so naturally for the same clock cycle. As for the figures posted above, I think the one for Hold Time is perhaps erroneous, since T(launch) and T(capture) must be at the same clock cycle. I've already posted a comment below, highlighting the same. Awaiting yourVLSI's reply! Reply

Anonymous February 23, 2014 at 11:40 PM In the Hold Time diagram, the Capture edge has been shown one clock cycle after Launch edge, whereas it should be at the same clock edge (delayed by buffers). The Set-up Time diagram, too uses the same clock edges, which though, is correct. Reply Replies your VLSI February 24, 2014 at 1:51 PM

For the same data Capture and launch edges are always one clock cycle. But for analysis purpose of Hold - you analysis the whole concept at the same edge. I would say - check the pic more closely and you will crack this figure also. Reply

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