ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

SEMICONDUCTOR CIRCUITS (ECE-650) PROJECT REPORT

FULL DIFFERENTIAL AMPLIFIER BY SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI UNDER PROFESSOR

TIMOTHY W .STEELE

New Jersey Institute of Technology

ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

A Fully-Differential High-Speed High-Precision Amplifier Design

SUMMARY Two fully-differential amplifiers need to be designed which have a mid-band gain of 8, differential output swing of 1.6V, gain error<1%, supply voltage=1.8V and the load capacitance is 0.7pF. The first design has a power budget of 15mW and aims to minimize the large-signal settling time to 0.5% accuracy. The second design targets a 0.5% large-signal settling time of 25ns and aims to minimize power dissipation. The problem is first explained at the block level, then opamp topologies are compared and a suitable topologyis selected for the high-gain amplifier. The consistency between simulated and calculated values verifies the accuracy of the calculations. The settling time is obtained to be 1.47ns for the high speed configuration and the power dissipation is obtained to be 295 W for the low power configuration. CIRCUIT DIAGRAM

Fig 1. Schematic of the fully differential amplifier used in this project.

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 1a. Calculation of gain for the above circuit

The control system block for the above topology is as shown:

Fig 2. Block diagram of amplifier. The open loop amplifier is shown as a transconductor Gm followed by its output impedance Ro. The feedback network consists of the feedback capacitor Cf (=C3=C4) and the input capacitance Cin (=C1=C2). The parasitic capacitance seen at the input of the amplifier and the bottom plate parasitic capacitance of the external capacitors Cin and Cf is seen at the input terminals of the open loop amplifier, modelled by CP. The open loop and closed loop transfer functions of the above amplifier are shown in Figure 3.

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ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 3. Transfer functions of open and closed loop systems From the above bode plots, assuming that the open loop amplifier is a single pole system, the unity gain bandwidth of the open loop system is given by- UGB 0 P1 = A where Ao is the open loop dc gain and p1 is the dominant pole of the open loop system. The feedback factor of the above system is given by loop UGB = Hence the unity loop gain frequency of the system with feedback factor is given by This is also the -3dB bandwidth of the closed loop system, and the settling time for an input step is given by loop settling time t 5 To meet the mid-band voltage gain requirement-= = 8finCClosedLoopGain C The dominant pole and the open loop gain are given by moLp A G RR C= = 001 1 ;If Cf=0.3pF, thenfmLmUGB pF CGCG+= =0.7 To meet the gain error requirement-1 0.010= <A GainErroror 100A0 >

MINIMIZING SETTLING TIME WITH A POWER BUDGET

To minimize settling time, the unity loop gain bandwidth loop and hence the unity gain bandwidth UGB should be maximized. To maximize the unity gain bandwidth, Gm of the open loop amplifier should be maximized. A. Choice of High Gain Amplifier topology Single stage Telescopic amp: Achieving the required swing of 1.6V, given that the input and output common mode levels are the same, is difficult with a single telescopic stage. Folded cascode with gain boosting: The folded cascode topology is shown in Figure 4. Gain boosting will be required to achieve the given open loop gain. Assuming an approximate value of the parasitic capacitance from the

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ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 4. Folded cascode input transistors of the open loop amplifier 2pF (from simulations)-17.4 1 From the above figure, pFgCg mLmloop 17.4 1 = 1,2 = 1 1,2 Given that the power budget=15mW and the supplyvoltage=1.8V, the available current 8mA. Slew rate calculation: The load capacitance is about 1pF and the maximum single ended swing=0.8V. Since the open loop gain is of the order of 103, maximum single ended swing at the input node800V. Hence during maximum swing, both input transistors will be in saturation. Assuming a rise time of 1nsmA nspF V dt I C dV L 1 1= = 1 0.8

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103 From Figure 4 when the output swing is maximum, current drawn from the load capacitors = IP-Iss/2. Hence to prevent slewing, current in the load arms = 1mA X2. From the remaining 6mA, 5.5mA can be used for the input transistors and the remaining 0.5mA can be used for the gain boosting stages. Hence current through each input transistor = 2.75mA. Assuming gm/ID 17.5 (from simulations for NMOS input devices with W=800um, L=180nm, ID=2.75mA) gm=48.125mA/V.Hence MHzt ns pF settlingtime loop 440 ; 1.81 2 1 48.125 10 17.4 1 2 3 = = Since settling time is 1.81ns and the circuit is designed for a minimum settling time of 1ns (from slew calculations), more current can be used in the input arm. If 0.5mA X2 is used in the load arms ns I dt C dV L 1.6 min = = Using 3.25mA X2 for the input transistors and using 0.5mA X2 for the load arms, gm=56.875mA/V. Hence MHz t nspF settlingtime loop 520 ; 1.53 2 1 6.875 10 17.4 1 2 3 = = Since the slew rate and settling time are almost equal, the system should settle in ~1.6ns. Two stage opamp: The two-stage opamp with Miller compensation is shown in Figure 5. In the first stage, a cascode amplifier is used to achieve the open loop gain required to meet the gain error requirements.

Fig 5. Two stage opamp topology used in the High Speed configuration (R=460)

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ECE650 From Figure 5-

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

1,2 1 9,10 2 A g R g R o m m = (( ) ) 1 9,10 2 9,10 1 1 1 m c gs p R g R + C + C = 9,10 9,10 9,10 29,10 2 1 c gs c gs L c gs c m p C C C C C C C R g C + + + + Hence assuming a single pole response loop UGBc m UGB p C g = A 1,2 ; 0 1 If the second pole is at p2=2loop, a 40% increase in the closed loop bandwidth (2 loop) is achieved as per the Butterworth response. But the Butterworth response rings in the time domain and the specifications require a settling accuracy of 0.5% of the final value. If the second pole is at p2=4loop, the fastest settling time without overshooting is achieved as per critically damped response. So the second pole is approximately positioned at p23loop. C pF C g c c m p ; 0.3 17.4 3 1 1,2 2 = = If C C pF c gs 0.3 9,10 = , then ( ) pF gm p 2 1.15 1,2 2 Therefore 1.317 1,2 9,10 = m m gg Assuming (gm/ID) =17.5 for both transistors, and given that ID1+ID2<=4mA, ID1=1.726mA and ID2=2.273mA.Hence gm1,2=30.2mA/V, gm9,10=39.8mA/V. Hence921 ; 2 loop = MHz t ns settlingtime = 0.87 and p 2.75GHz 2 2 For ID2=2.273mA, slew rate calculations give rise to a minimum settling time of 0.35ns. From simulations, itwas found that C C pF c gs 0.5 9,10 = is a better approximation (Cgd9,100.2pF). With this assumption1.165 1 1,2 9,10 = m m g g Assuming (gm/ID) =17.5 (from simulations) is the same for both transistors, and given that ID1+ID2<=4mA, ID12.15mA and ID2=1.85mA. Hence gm1,2=37.625mA/V and gm9,10=32.375mA/V. Hence688 ; 2 loop = MHz t ns settlingtime = 1.16 p 2GHz 2 2 For ID2=1.85mA, slew rate calculations give rise to a minimum settling time of 0.432ns, hence there should be no slewing. The 2nd stage CSA consumes minimal voltage head room, thus providing enough swing to satisfy the requirements. Since this topology gives a faster settling time, the high gain amplifier is designed as a two- tage amplifier.

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ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103 MINIMIZING POWER FOR A SETTLING TIME OF 25ns

As in the previous section, a two-stage topology with Miller compensation is used to design the high gain stage. Since lower currents are used, the first stage need not be a cascode stage to achieve high gain. The PMOS input devices are cascoded to reduce the Miller capacitance seen at the input.

Fig 6. Two stage opamp topology used in the Low Power configuration (R=20k)

Fig 7. Full circuit for differential amplifier

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

For a settling time of 25 ns-5 25 322looploopns MHz The feedback factor is approximated to- 110 = This approximation results from the reduced junction and parasitic capacitances from the input transistors due to their small size (as compared to Section II). Thus the open loop unity gain bandwidth can be determined-1 3202UGBloop MHz = = Hence gm1,2 can be determined-1,21,2 600 /0.3mUGB mgg A VpF = The second pole is positioned at2 3 1002 2p loop MHz = Hence gm7,8 can be determined- g VC CC CCgmC gsC gsLmp 820 7,87,82 ++=

Assuming that gm/Id~17.5 for both devices, the total current flowing in the opamp can be estimated as(820 600)2 162TOT 17.5 I A+= = Thus the power drawn by the opamp is 292W. This does not include the power drawn by the common mode feedback circuitry and the biasing circuitry.

COMMON MODE FEEDBACK

The two stage opamp used in this project uses a resistor load in the 2nd stage CSA. Hence if the common mode level of the 1st stage output is set, the common mode level of the 2 nd stage output and hence the input common mode level is set. The 1st stage output nodes experience 1.6V/10 ~ 160mV differential swing when the output nodes experience full swing. Hence a common mode feedback circuit that can tolerate about +-40mV input swing will be sufficient. The circuit shown in Figure 7 is used to bias the NMOS load devices of the 1st stage. As a result of shorting the drains of the 2 input transistors, any differential input will produce no net current, but the amplifier will generate

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103 a voltage proportional to the common mode input, thus providing negative feedback. The gain of the common mode feedback amplifier is given by Acmfb~gmp/gmn. Since this amplifier is part of a loop with a cascode stage, the CMFB amplifier requires a relatively low gain ~0.5.

Fig 7. CMFB amplifier V. SIMULATIONS AND RESULTS Using the estimated values of currents and trans conductances from the previous section, the two designs were simulated. The operating points of the transistors of the high speed and low power configurations are shown. The graphs showing the output settling time at full swing for a step input, the gain error and the frequency response are shown in Figure 8 and Figure 9. The total current drawn from the power supply during simulations includes the current drawn by the CMFB amplifier. In the high power configuration, about 300A of current is left from the maximum allowed value, which can be used in the biasing circuits.

Fig 9a. Transient response of the high speed amplifier at full swing

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ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 9b. Frequency response of the high speed amplifier

New Jersey Institute of Technology

ECE650

SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 10a. Magnitude and phase response design

New Jersey Institute of Technology

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103

Fig 10b. Transient reaponse

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SACHIN BASAVARAJAPPA KENCHAMMANAGATHIHALLI 31085103 CONCLUSION

The high speed and low power configurations of the amplifier have been simulated and the results show that the requirements have been met. The simulated results consistently match the corresponding estimated values, thus verifying the accuracy of the calculations used in Section II and III. For the high speed configuration, a settling time of 1.47ns is obtained and for the low power configuration, the power dissipated is 295.2W.

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