INDEX

S.NO.
1(a) 1(b) 1(c) 1(d) 1(e) 1(f) 1(g) 2(a) 2(b) 3(a)

EXPERIMENT NAME
TO WRITE VHDL PROGRAM FOR OR GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR AND GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR NOR GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR NAND GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR NOT GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR XOR GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR XNOR GATE AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR HALF ADDER CIRCUIT AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR FULL ADDER CIRCUIT AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR HALF SUBSTRACTOR CIRCUIT AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR FULL SUBSTRACTOR CIRCUIT AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR 8:1 MULTIPLEXER AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR 1:4 DEMULTIPLEXER AND VERIFY THE WAVEFORM. TO WRITE VHDL PROGRAM FOR 4:2 ENPROGRAMR AND VERIFY THE WAVEFORM TO WRITE VHDL PROGRAM FOR BCD TO 7SEGMENT DEPROGRAMR AND VERIFY THE WAVEFORM TO WRITE VHDL PROGRAM FOR BINARY TO GRAY PROGRAM CONVERTOR AND VERIFY THE WAVEFORM TO WRITE VHDL PROGRAM FOR GRAY TO BINARY PROGRAM CONVERTOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR 2-BIT COMPARATOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR 4-BIT COMPARATOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR ALU OPERATION AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR SR FLIP FLOP AND VERIFY THE WAVEFORM 407/EC/11

DATE
3/3/14 3/3/14 3/3/14 3/3/14 3/3/14 3/3/14 3/3/14 3/3/14 3/3/14 3/3/14

TEACHERS SIGNATURE

3(b)

3/3/14

4(a) 4(b) 5(a) 5(b)

3/3/14 3/3/14 31/3/14 31/3/14

6(a)

31/3/14

6(b)

31/3/14

7(a) 7(b) 8 9(a)

31/4/14 31/4/14 31/4/14 21/4/14

AMIT KUMAR

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9(b) 9(c ) 9(d) 10(a) 10(b) 10(c) 10(d) 11

WRITE VHDL PROGRAM FOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR AND VERIFY THE WAVEFORM

JK FLIP FLOP D-FLIP FLOP T-FLIP FLOP SISO SHIFT REGISTER

21/4/14 21/4/14 21/4/14 21/4/14

WRITE VHDL PROGRAM FOR SIPO SHIFT REGISTER 21/4/14 AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR PISO SHIFT REGISTER 21/4/14 AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR PIPO SHIFT REGISTER AND VERIFY THE WAVEFORM WRITE VHDL PROGRAM FOR UPDOWN ASYNCHRONOUS COUNTER AND VERIFY THE WAVEFORM 21/4/14 21/4/14

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STEPS

Double-Click on the Icon of Active-HDL 7.2. Click on create on New Workspace. Enter the Workspace name and click OK. Create New Design and click ok. Then enter Design name and click ok. Right click on the Add New File on the Left side column of the window. Clcik on New and select VHDL Source. When a window pop up click Next Now enter source file name, entity name and architecture name and click next. Now enter input and output ports and click Finish. Now the needed program code appears on the window. Scroll down and enter the design logic in the architecture section of program code. Click on Simulation on the top bar of the screen and click on Initialize Simulation. After getting result that no Error and Warning Found at the bottom. Click on entity name in the left column and the input and output port appears in the column just below the entity column. Select all ports and add to waveform. Now give Clock Signal to each input port and click on simulation on the top bar. Click on Run Until and enter the time for which u want to get waveform. After getting desired output, End the Simulation process and save the file. Close the workspace.

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PROGRAM-1(a)

DATE- 3/3/2014

AIM-Write the VHDL program for OR gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

OR GATE

SOURCE CODE-

-- Title : OR1 -- Design : OR -- Author : Amit -- Company :Vce -- File : OR.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.2 -----------------------------------------------------------------------{entity {OR1} architecture {OR2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity OR1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end OR1; architecture OR2 of OR1 is begin Process(A,B) begin Y<=A OR B; end process; end OR2;

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WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 0 1 1 1

RESULT- OR logic gate has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-1(b)

DATE-3/3/2014

AIM-Write the VHDL program for AND gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

AND GATE

SOURCE CODE--Title : AND1 --Design : AND --Author : Amit --Company : Vce -- File : AND.vhdl -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {AND1} architecture {AND2}} library IEEE use IEEE.STD_LOGIC_1164.all; entity AND1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end AND1; architecture AND2 of AND1 is begin Process(A,B) begin Y<=A AND B; end process; end AND2;
AMIT KUMAR 407/EC/11 Page 6

WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 0 0 0 1

RESULT- AND logic gate has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-1(C)

DATE- 3/3/2014

AIM-Write the VHDL program for NOR gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

NOR GATE

SOURCE CODE-- Title : NOR1 -- Design : NOR -- Author : Amit -- Company :Vce -- File : NOR.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 -------------------------------------------------------------------------------{entity {NOR1} architecture {NOR2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity NOR1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end NOR1; architecture NOR2 of NOR1 is begin Process(A,B) begin Y<=A NOR B; end process; end NOR2;
AMIT KUMAR 407/EC/11 Page 8

WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 1 0 0 0

RESULT- NOR logic gate has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-1(d)

DATE- 3/3/2014

AIM-Write the VHDL program for NAND gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

NAND GATE

SOURCE CODE-- Title : NAND1 -- Design : NAND -- Author : Amit -- Company :Vce -- File : NAND.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 -------------------------------------------------------------------------------{entity {NAND1} architecture {NAND2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity NAND1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end NAND1; architecture NAND2 of NAND1 is begin process(A,B) begin Y<=A NAND B; end process; end NAND2;

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WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 1 1 1 0

RESULT- NAND logic gate has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-1(e)

DATE- 3/3/2014

AIM-Write the VHDL program for NOT gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

NOT GATE

SOURCE CODE-- Title : NOT1 -- Design : NOT -- Author : Amit -- Company : Vce -- File : NOT.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 ----------------------------------------------------------------------{entity {NOT1} architecture {NOT2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity NOT1 is port( A : in STD_LOGIC; Y : out STD_LOGIC ); end NOT1; architecture NOT2 of NOT1 is begin Process(A) Y<=NOT A; end process; end NOT2;

WAVEFORMAMIT KUMAR 407/EC/11 Page 12

TRUTH TABLEA 0 1
S

Y 1 0

RESULT- NOT logic gate has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-1(f)

DATE- 3/3/2014

AIM-Write the VHDL program for XOR gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL7.2 CIRCUIT DIAGRAM-

XOR GATE

SOURCE CODE-- Title : XOR1 -- Design : XOR -- Author :Amit -- Company :Vce -- File : XOR.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {XOR1} architecture {XOR2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity XOR1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end XOR1; architecture XOR2 of XOR1 is begin Process(A,B) begin Y<=A XOR B; end process; end XOR2;

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WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 0 1 1 0

RESULT- XOR logic gate has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-1(g)

DATE- 3/3/2014

AIM-Write the VHDL program for XNOR gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL7.2 CIRCUIT DIAGRAM-

XNOR GATE

SOURCE CODE-- Title : XNOR1 -- Design : XNOR -- Author : Amit -- Company :Vce -- File : XNOR.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {XNOR1} architectu-- Description : library IEEE; use IEEE.STD_LOGIC_1164.all; entity XNOR1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC ); end XNOR1; architecture XNOR2 of XNOR1 is begin Process(A,B) begin Y<=A XNOR B; end process; end XNOR2;

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WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 Y 1 0 0 1

RESULT- XNOR logic gate has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-2(A)

DATE- 3/3/2014

AIM-Write the VHDL program for HALFADDER gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7,2 CIRCUIT DIAGRAM-

HALF ADDER

SOURCE CODE-- Title : HALFADDER1 -- Design : HALF ADDER -- Author : Amit -- Company :Vce -- File : HALFADDER.vhd -- Generated : Sun Mar 9 16:35:41 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 ----------------------------------------------------------------------------------{entity {HALFADDER1} architecture {HALFADDER2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity HALFADDER1 is port( A : in STD_LOGIC; B : in STD_LOGIC; S : out STD_LOGIC; C : out STD_LOGIC ); end HALFADDER1; architecture HALFADDER2 of HALFADDER1 is begin Process(A,B) begin
AMIT KUMAR 407/EC/11 Page 18

S<=A XOR B; C<=A AND B; end process; end HALFADDER2;

WAVEFORM-

TRUTH TABLEA 0 0 1 1 B 0 1 0 1 S(SUM) 0 1 1 0 C(CARRY) 0 0 0 1

RESULT- HALFADDER has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-2(B)

DATE-3/3/2014

AIM-Write the VHDL program for FULLADDER gate and VERIFY the waveforms. REQUIREMENTS-Active VHDL7.2 CIRCUIT DIAGRAM-

FULLADDER

SOURCE CODE-- Title : full1 -- Design : full -- Author :Amit --company :Vce -- File : full.vhd -- From : interface description file -- By : Itf2Vhdl ver. 1.20 ----------------------------------------------------------------------------------{entity {full1} architecture {full2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity full1 is port( A : in STD_LOGIC; B : in STD_LOGIC; Cin: in STD_LOGIC; S : out STD_LOGIC; Cout : out STD_LOGIC ); end full1; architecture full2 of full1 is begin Process(A,B,C) S<= A xor B xor Cin;
AMIT KUMAR 407/EC/11 Page 20

Cout<=(A and B) or (B and C) or (C and A); end process; end full2;

WAVEFORM-

TRUTH TABLEA 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

RESULT- FULLADDER has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-3(A)

DATE-3/3/2014

AIM-Write the VHDL program for HALFSUBTRACTOR and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : halfsubtractor -- Design : half subtractor -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : half subtractor.vhd -- Generated : Wed Apr 2 15:03:09 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 -------------------------------------------------------------------------------- Description : --{{ Section below this comment is automatically maintained -- and may be overwritten --{entity {halfsubtractor1} architecture {halfsubtractor2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity halfsubtractor1 is port( a : in STD_LOGIC; b : in STD_LOGIC; d : out STD_LOGIC; bo : out STD_LOGIC ); end halfsubtractor1; --}} End of automatically maintained section architecture halfsubtractor2 of halfsubtractor1 is begin
AMIT KUMAR 407/EC/11 Page 22

-- enter your statements here -process(a,b) begin d<=a xor b; bo<=((not a) and b); end process; end halfsubtractor2;

WAAVEFORM-

TRUTH TABLE-

RESULT- HALFSUBTRACTOR has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-3(B)

DATE-3/3/2014

AIM-Write the VHDL program for FULLSUBTRACTOR and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE--- Title :full subtractor -- Design : full -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : full.vhd -- Generated : Wed Apr 2 15:03:09 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {full1} architecture {full2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity full1 is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : out STD_LOGIC; bo : out STD_LOGIC ); end full1; architecture full2 of full1 is begin process(a,b,c) begin
AMIT KUMAR 407/EC/11 Page 24

d<=a xor b xor c; bo<=((not a) and b) or((a xor b) and c); end process; end full2;

WAVEFORM-

TRUTH TABLE-

RESULT- FULLSUBTACTER has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-4(A)

DATE-3/3/2014

AIM-Write the VHDL program for 8*1 MULTIPLEXER and VERIFY the waveforms. REQUIREMENTS-Active VHDL7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : MUX -- Design : MUX -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : MUX.vhd -- Generated : Thu Apr 3 13:55:23 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {MUX} architecture {MUX}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX is PORT(i:IN std_logic_vector(0 to 7); s:IN std_logic_vector(0 to 2); y:OUT std_logic); end MUX; architecture MUX of MUX is begin process(i,s) begin
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case s is when "000"=> y<=i(0); when "001"=> y<=i(1); when "010"=> y<=i(2); when "011"=> y<=i(3); when "100"=> y<=i(4); when "101"=> y<=i(5); when "110"=> y<=i(6); when others=>y<=i(7); end case; end process; end MUX;

WAVEFORM-

RESULT- 8*1 MULTIPLEXER has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-4(B)

DATE-3/3/2014

AIM-Write the VHDL program for 1*4 DEMULTIPLEXER and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : demultiplexer -- Design : demultiplexer -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : demultiplexer.vhd -- Generated : Fri Apr 4 11:57:07 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {demultiplexer} architecture {demultiplexer}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity demultiplexer is port( a : in STD_LOGIC; s0 : in STD_LOGIC; s1: in STD_LOGIC; y1 : out STD_LOGIC; y2 : out STD_LOGIC; y3 : out STD_LOGIC; y4 : out STD_LOGIC ); end demultiplexer;
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architecture demultiplexer of demultiplexer is begin process(a,s0,s1) begin if s0='0'and s1='0' then y1<= (a and ((not s0) and (not s1))); elsif s0='0'and s1='1' then y2<=(a and ((not s0) and s1)); elsif s0='1' and s1='0'then y3<= (a and (s0 and (not s1))); else y4<=(a and (s0 and s1)); end if; end process; end demultiplexer;

WAVEFORM-

RESULT- 1*4 DEMULTIPLEXER has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-5(A)

DATE- 31/3/2014

AIM-Write the VHDL program for ENCODER and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : encoder -- Design : encoder -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : encoder.vhd -- Generated : Mon Apr 7 09:39:42 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {encoder} architecture {encoder}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity encoder is port( i : in STD_LOGIC_vector(0 to 3); a : out STD_LOGIC_vector(0 to 1) ); end d; architecture encoder of encoder is begin process(i) begin if i="1000" then a<="00"; elsif i="0100" then
AMIT KUMAR 407/EC/11 Page 30

a<="01"; elsif i="0010" then a<="10"; elsif i="0001" then a<="11"; else a <= "00" ; end if; end process; end encoder;

WAVEFORM-

RESULT- ENCODER has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-5(B)
the waveforms.

DATE- 31/3/2014

AIM-Write the VHDL program for BCD TO SEVEN SEGMENT DECODER and VERIFY REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : bcd to ss -- Design : bcd to ss -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : bcd to ss.vhd -- Generated : Fri Apr 4 13:19:46 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {bcd to ss} architecture {bcd to ss}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity bcd to ss is port( i : in STD_LOGIC_vector(0 to 3); y : out STD_LOGIC_vector(0 to 6) ); end bcd to ss; architecture bcd to ss of bcd to ss is begin process(i) begin case i is
AMIT KUMAR 407/EC/11 Page 32

when "0000"=>y<="1111110"; when "0001"=>y<="0110000"; when "0010"=>y<="1101101"; when "0011"=>y<="1111001"; when "0100"=>y<="0110011"; when "0101"=>y<="1011011"; when "0110"=>y<="1011111"; when "0111"=>y<="1110000"; when "1000"=>y<="1111111"; when "1001"=>y<="1110011"; when others =>y <="0000000"; end case; end process; end bcd to ss;

WAVEFORM-

RESULT-BCD TO SEVEN SEGMENT DECODR has been designed and waveform is

verified using Active VHDL Software.

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PROGRAM-6(A)
waveforms.

DATE- 31/3/2014

AIM-Write the VHDL program for BINARY TO GRAY CONVERSION and VERIFY the REQUIREMENTS-Active VHDL7.2 CIRCUIT DIAGRAM-

BINARY TO GRAY CONVERTOR

SOURCE CODE-- Title : btog1 -- Design : btog -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : btog.vhd -- Generated : Wed Apr 2 15:39:46 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {btog1} architecture {btog2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity btog1 is port( b0 : in STD_LOGIC; b1 : in STD_LOGIC; b2 : in STD_LOGIC; b3 : in STD_LOGIC; g0 : out STD_LOGIC; g1 : out STD_LOGIC; g2 : out STD_LOGIC; g3 : out STD_LOGIC
AMIT KUMAR 407/EC/11 Page 34

); end btog1; architecture btog2 of btog1 is begin process(b0,b1,b2,b3) begin g0<=b0; g1<=b1 xor b0; g2<=b2 xor b1; g3<=b3 xor b2; end process; end btog2;

WAVEFORM-

RESULT- BINARY TO GRAY CONVERTOR has been designed and waveform is

verified using Active VHDL Software.

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PROGRAM-6(B)
waveforms.

DATE- 31/3/2014

AIM-Write the VHDL program for GRAY TO BINARY CONVERSION and VERIFY the REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

GRAY TO BINARY CONVERTOR

SOURCE CODE-- Title : gtob1 -- Design : gtob -- Author : Amit -- Company : Vce --------------------------------------------------------------------------------- File : gtob.vhd -- Generated : Thu Apr 3 13:33:44 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {gtob1} architecture {gtob2}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity gtob1 is port( g0 : in STD_LOGIC; g1 : in STD_LOGIC; g2 : in STD_LOGIC; g3 : in STD_LOGIC; b0 : out STD_LOGIC; b1 : out STD_LOGIC; b2 : out STD_LOGIC; b3 : out STD_LOGIC );
AMIT KUMAR 407/EC/11 Page 36

end gtob1; architecture gtob2 of gtob1 is begin process(g0,g1,g2,g3) begin b0<=g0; b1<=g0 xor g1; b2<=g0 xor g2 xor g1; b3<=(((g0 xor g1) xor g2) xor g3); end process; end gtob2;

WAVEFORM-

RESULT- GREY TO BINARY CONVERTOR has been designed and waveform is

verified using Active VHDL Software.

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PROGRAM-7(A)

DATE- 31/3/2014

AIM-Write the VHDL program for 1-BIT COMPARATOR and VERIFY the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : comparator -- Design : comarator -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : comparator.vhd -- Generated : Fri Apr 4 12:24:22 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {comparator} architecture {comparator}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity comparator is port( a : in STD_LOGIC; b : in STD_LOGIC; agb : out STD_LOGIC; alb : out STD_LOGIC; aeb : out STD_LOGIC ); end comparator; architecture comparator of comparator is beginenter your statements here -process (a,b) begin if a=b then aeb<='1';
AMIT KUMAR 407/EC/11 Page 38

agb<='0'; alb<='0'; elsif a>b then aeb<='0'; agb<='1'; alb<='0'; else aeb<='0'; agb<='0'; alb<='1'; end if; end process; end comparator;

WAVEFORM-

RESULT- 1-BIT COMPARATOR has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM- 7(B)

DATE-31/3/2014

AIM-Write the VHDL program for 4-BIT COMPARATOR and VERIFY the waveforms. REQUIREMENTS- Active VHDL.7.2 CIR UIT DIAGRAM-

SOURCE CODE-- Title : 4BIT COMPARATOR -- Design : BIT COMPARATOR -- Author : Amit -- Company : vce -------------------------------------------------------------------------------- File : 4BIT COMPARATOR.vhd -- Generated : Fri Apr 18 05:03:55 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {4BIT COMPARATOR} architecture {4BIT COMPARATOR}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity 4BIT COMPARATOR is port( a:in std_logic_vector(0 to 3); b: in std_logic_vector(0 to 3); agb: out std_logic; aeb: out std_logic; alb: out std_logic); end 4BIT COMPARATOR; architecture 4BIT COMPARATOR of 4BIT COMPARATOR is begin process(a,b) begin if a=b then aeb<='1'; agb<='0';
AMIT KUMAR 407/EC/11 Page 40

alb<='0'; elsif a>b then aeb<='0'; agb<='1'; alb<='0'; else aeb<='0'; agb<='0'; alb<='1'; end if; end process; end 4BIT COMPARATOR;

WAVEFORM-

RESULT- 4-BIT COMPARATOR has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-8

DATE-31/3/2014

AIM: Write the VHDL program for ALU operations and check the waveform. REQUIREMENTS- Active VHDL.7.2 SOURCE CODE-- Title : aluoperation 2 -- Design : alu operation2 -- Author : Amit -- Company : vce ---------------------------------------------------------------------------------- File : aluoperation 2.vhd -- Generated : Wed Apr 23 02:08:03 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {\aluoperation 2\} architecture {\aluoperation 2\}} library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity \aluoperation 2\ is port( i: in std_logic_vector(3 downto 0); a,b:in std_logic_vector(7 downto 0); c: in std_logic; y: inout std_logic_vector(7 downto 0)); end \aluoperation 2\; architecture \aluoperation 2\ of \aluoperation 2\ is signal airth,logic:std_logic_vector(7 downto 0); begin with i(2 downto 0) select airth<= a when "000" ,a+1 when "001", a-1 when "010", b when "011", b+1 when "100", b-1 when "101", a+b when "110", a+b+c when others; with i(2 downto 0)select logic<=not a when"000" ,not b when"001", a and b when "010", a or b when"011" , a nand b when"100", a nor b when"101" ,a xor b when "110", a xnor b when others; with i(3)select y<=airth when'0' ,logic when others; end \aluoperation 2\;

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WAVEFORM-

RESULT-ALU OPERATIONS has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-9(A)

DATE-21/4/2014

AIM- Write the VHDL program for SR-FLIP FLOP and verify the waveform. REQUIREMENTS- Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE--Title -- Design -- Author -- Company : srff : srff : Amit : Vce

--------------------------------------------------------------------------------- File : srff.vhd

-- Generated : Mon Apr 21 14:35:27 2014 -- From -- By : interface description file : Itf2Vhdl ver. 1.20

--{entity {srff} architecture {srff}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity srff is port( s : in STD_LOGIC; r : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC ); end srff; architecture srff of srff is
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begin process(s,r,clk) begin if(clk'event and clk= '1') then if (s='0' and r='0')then q<= q; elsif(s='0' and r='1') then q<='0'; elsif (s='1' and r='0') then q<='1'; else q<='X'; end if; else q<=q; end if; end process end srff; ;

WAVEFORM-

RESULT- SR-FLIP FLOP has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-9(B)

DATE-21/4/2014

AIM- Write the VHDL Program for JK-FLIP FLOP and check the waveform. REQUIREMENTS- Active VHDL 7.2 CIRCUIT DIAGRAM-

JK FLIP FLOP SOURCE CODE-- Title : jkff -- Design : jkff -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : jkff.vhd -- Generated : Mon Apr 21 14:58:26 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 ---------------------------------------------------------------------------------{entity {jkff} architecture {jkff}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity jkff is port( j : in STD_LOGIC; k : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC ); end jkff; architecture jkff of jkff is begin process(j,k,clk) begin
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if(clk'event and clk= '1') then if (j='0' and k='0')then q<= q; elsif(j='0' and k='1') then q<='0'; elsif (j='1' and k='0') then q<='1'; else q<= not q; end if; else q<=q; end if; end process ; end jkff;

WAVEFORM-

RESULT- JK-FLIP FLOP has been designed and waveform is verified using Active
VHDL Software.

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PROGRAM-9(C)

DATE-21/4/2014

AIM- Write the VHDL program for D-FLIP FLOP and verify the waveform. REQUIREMENTS- Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : dff -- Design : dff -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : dff.vhd -- Generated : Mon Apr 21 15:39:25 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 ---------------------------------------------------------------------------------{entity {dff} architecture {dff}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity dff is port( d : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC ); end dff; architecture dff of dff is begin process(d,clk) begin if(clk'event and clk='1')then q<= d; else q<= q;
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end if; end process; end dff;

WAVEFORM-

RESULT- D-FLIP FLOP has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-9(D)

DATE-21/4/2014

AIM- Write the VHDL program for T-FLIP FLOP and verify the waveform. REQUIREMENTS- Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : toggle -- Design : toggle -- Author : Amit -- Company : Vce -------------------------------------------------------------------------------- File : toggle.vhd -- Generated : Mon Apr 21 15:53:30 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {toggle} architecture {toggle}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity toggle is port( t : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC ); end toggle; architecture toggle of toggle is begin process(t,clk) begin if (clk'event and clk= '1') then q<= not t ; else
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q<= q; end if; end process; end toggle;

WAVEFORM-

RESULT- T-FLIP FLOP has been designed and waveform is verified using Active VHDL
Software.

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PROGRAM-10(A)

Date-21/4/2014

AIM-Write the VHDL program for SISO SHIFT REGISTER and verify the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : siso2 -- Design : siso1 -- Author : Amit -- Company : vce -------------------------------------------------------------------------------- File : siso1.vhd -- Generated : Thu Apr 24 01:39:21 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {siso2} architecture {siso3}} library IEEE; use IEEE.STD_LOGIC_1164.all; useIEEE.STD_LOGIC_ARITH.all; entity siso2 is port( pr : in STD_LOGIC; cr : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; y : out STD_LOGIC );
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end siso2; architecture siso3 of siso2 is signal q0,q1,q2:STD_LOGIC; begin process (clk,pr,cr) begin if(pr='1' and cr='1' and clk'event and clk='1')then q0 <=d; q1<=q0; q2<=q1; y<= q2; elsif (pr='1' and cr='0' and clk='1' and clk'event) then q0<='0'; q1<='0' ; q2<='0'; y<='0'; elsif(pr='0' and cr='1' and clk='1' and clk'event)then q0<='1'; q1<='1' ; q2<='1'; y<='1'; else q0<='X'; q1<='X'; q2<='X'; y<='X'; end if; end process; end siso3;

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WAVEFORM-

RESULT- SISO SHIFT REGISTER has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-10(B)

Date-21/4/20114

AIM-Write the VHDL program for SIPO REGISTER and verify the waveforms. REQUIREMENTS-Active VHDL 7.2 . CIRCUIT DIAGRAM-

SOURCE CODE-- Title : sipo a -- Design : sipo a -- Author : Amit -- Company : vce -------------------------------------------------------------------------------- File : sipo a.vhd -- Generated : Thu Apr 24 02:56:21 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {sipo a} architecture {sipo a}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity sipo a is port( d : in STD_LOGIC; pr : in STD_LOGIC; cr : in STD_LOGIC; clk : in STD_LOGIC; q :inoutSTD_LOGIC_vector(0 to 2) ); end sipo a; architecture sipo a of sipo a is begin process(pr,cr,clk,d)
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begin if(pr='1' and cr='1' and clk='1' and clk'event)then q(0)<=d; q(1)<=q(0); q(2)<=q(1); elsif(pr='1' and cr='0')then q(0)<='0'; q(1)<='0'; q(2)<='0'; elsif(pr='0' and cr='1')then q(0)<='1'; q(1)<='1'; q(2)<='1'; elsif(pr='0' and cr='0')then q(0)<='1'; q(1)<='1'; q(2)<='1'; end if; end process; end sipo a;

Waveform-

RESULT- SIPO SHIFT REGISTER has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-10(B)

Date-21/4/2014

AIM-Write the VHDL program for PISO SHIFT REGISTER and verify the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : piso 1 -- Design : piso -- Author : Amit -- Company : vce -------------------------------------------------------------------------------- File : piso.vhd -- Generated : Thu Apr 24 03:12:23 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --------------------------------------------------------------------------------{entity {piso 1} architecture {piso 1}} library IEEE; use IEEE.STD_LOGIC_1164.all; useieee.std_logic_arith.all; entity piso 1 is port( clk : in STD_LOGIC; cr : in STD_LOGIC; pr : in STD_LOGIC; d : in STD_LOGIC_VECTOR(2 downto 0); q : out STD_LOGIC );
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end piso 1; architecture piso 1 of piso 1 is signal q0,q1,q2:STD_LOGIC; begin process (d,clk,pr,cr) begin if(pr='1' and cr='1' and clk'event and clk='1')then q0 <=d(0); q1<=d(1); q2<=d(2); q<= q2; elsif (pr='1' and cr='0' and clk='1' and clk'event) then q0<='0'; q1<='0'; q2<='0'; q<='0'; elsif(pr='0' and cr='1' and clk='1' and clk'event)then q0<='1'; q1<='1'; q2<='1'; q<='1'; else q0<='X'; q1<='X'; q2<='X'; q<='X'; end if; end process; end piso 1;

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Waveform-

RESULT- PISO SHIFT REGISTER has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-10(A)

Date-21/4/2014

AIM-Write the VHDL program for PIPO SHIFT REGISTER and verify the waveforms. REQUIREMENTS-Active VHDL 7.2 CIRCUIT DIAGRAM-

SOURCE CODE-- Title : PIPO -- Design : PIPO1 -- Author : Amit -- Company : vce -------------------------------------------------------------------------------- File : PIPO.vhd -- Generated : Thu Apr 24 02:13:06 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 -------------------------------------------------------------------------------{entity {PIPO} architecture {PIPO}} library IEEE; use IEEE.STD_LOGIC_1164.all; entity PIPO is port( pr : in STD_LOGIC; cr : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC_vector(0 to 2); q : out STD_LOGIC_vector(0 to 2) ); end PIPO;
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architecture PIPO of PIPO is begin process(cr,clk,d,pr) begin if(pr='0' and cr='1') then q<="111"; elsif(pr='1' and cr='0') then q<="000"; elsif(pr='0' and cr='0')then q<="111"; elsif(pr='1' and cr='1' and clk='0'and clk'event)then q<=d; end if; end process; end PIPO;

Waveform-

RESULT- PIPO SHIFT REGISTER has been designed and waveform is verified using
Active VHDL Software.

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PROGRAM-11
REQUIREMENTS-Active VHDL 7.2 SOURCE CODE-- Title : \up down counter\ -- Design : up down counter -- Author : Amit -- Company : vce ------------------------------------------------------------------------------- File : up down counter.vhd -- Generated : Fri Apr 25 19:20:05 2014 -- From : interface description file -- By : Itf2Vhdl ver. 1.20 --{entity {\up down counter\} architecture {\up down counter\}} library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee. std_logic_unsigned.all; entity \up down counter\ is port( up : in STD_LOGIC; dn : in STD_LOGIC; cr : in STD_LOGIC; clk : in STD_LOGIC; t : in STD_LOGIC; q : inout STD_LOGIC_VECTOR(0 to 2) ); end \up down counter\; architecture \up down counter\ of \up down counter\ is begin process(cr,clk,up,dn) variable s1,s2,s3,s4,s5,s6,s7,s8:std_logic; begin s1:=not q(0); s2:=up and q(0); s3:= s1 and dn; s4:= s2 and s3; s5:= not q(1); s6:= up and q(1); s7:= s5 and dn; s8:= s6 or s7; if( cr='1') then
AMIT KUMAR 407/EC/11

DATE-21/4/2014

AIM-Write the VHDL program for UP-DOWN COUNTER and verify the waveforms.

Page 62

q<="000"; elsif( cr='0' and up='1'and dn='0' and clk='0' and clk'event)then q<=q-"001"; elsif( cr='0' and up='0'and dn='1' and clk='0' and clk'event)then q<= q+"001"; else q<=q; end if; end process; end \up down counter\;

WAVEFORM-

RESULT-UP-DOWN COUNTER has been designed and waveform is verified using active
VHDL Software.

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