160 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 7, NO.
2, JUNE 2009
Radio Frequency Low Noise Amplifier with
Linearizing Bias Circuit
Wen-Tao Han, Qi Yu, Song Ye, and Mo-Hua Yang
Abstract⎯A 1.34 GHz±60 MHz low noise amplifier
(LNA) designed in a 0.35 μm SiGe process is presented.
The designed LNA exhibits a power gain of 21.46 dB and
a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity
is improved with an active biasing technique. The
post-layout simulation shows an input referred 1-dB
compression point (IP1dB) of −11.52 dBm. Compared
with the recent reported high gain LNAs, the proposed
LNA has a much better linearity without degrading
other performance. The LNA draws 10 mA current from
a 3.3 V power supply.
Index Terms⎯Impedance matching, linear circuits,
low noise amplifier.
1. Introduction
Low noise amplifier (LNA) is the first stage of a radio
frequency (RF) receiver and its noise characteristic
dominates the overal1 noise performance of the receiver. In
general, the requirements of a LNA are, apart from low
noise, sufficiently high gain to suppress noise contributions
from subsequent stages, high linearity to restrain gain
compression, and well-defined input impedance to match
the input source[1].
Due to rapid progress and high quality demands in radio
communication, the design trends for LNA are high
linearity, high gain, low noise, and low power consumption.
However, it is well known that the achievement of high
linearity will cause the gain to decrease along with the
increase of noise figure (NF) and power consumption.
Therefore, how to trade off among high linearity, high gain,
and low NF while not increasing power consumption and
chip size is the most important design challenge nowadays.
Many methodologies are reported to improve the
linearity of a LNA, such as harmonic tuning using a low
frequency trap[2], third order cancellation using transistors
Manuscript received August 13, 2008; revised October 20, 2008.
W.-T. Han, Q. Yu, and M.-H. Yang are with State Key Laboratory of
Electronic Thin Films and Integrated Devices, University of Electronic
Science and Technology of China, Chengdu, 610054, China (e-mail:
hanwentao@gmail.com).
S. Ye is with BroadGalaxy Electronics Technology Ltd., Chengdu,
610065, China. (e-mail: sye@broadgalaxy.com).
with different Gm[3],[4] and predistortion method[5],[6].
However, these methods either require precise control or
involve complex circuits, so most times they cannot be
easily utilized in practical applications.
This paper presents a high linearity high gain single-
ended LNA for a radar receiver by using a linearizing bias
circuit. Through steadying the bias point, the linearizing
bias circuit offers good linearity performance without
degrading other performance. The paper is organized as
follows. In section 2, the biasing technique is introduced.
Section 3 presents the LNA circuit design and imple-
mentation. Simulation results are summarized in Section 4.
2. Biasing Technique
Linearity is a crucial consideration in LNA design,
because a circuit’s nonlinearity brings a lot of problems
such as gain compression and inter-modulation, which is
undesirable. Usually, the small-signal gain of circuit is
obtained with the assumption that harmonics are negligible.
However, as the signal amplitude increases, the gain begins
to vary. In fact, nonlinearity can be viewed as variation of
the small-signal gain with the input level. The output is a
compressive or saturating function of the input. This effect
is quantified by the IP1dB, defined as the input signal level
that causes the small-signal gain to drop by 1 dB. At high
input signal levels, a high IP1dB is required to ensure
linearity. For RF amplifiers with BJT devices including
SiGe HBT devices, the design of base bias circuit is a key
issue to achieve high IP1dB [6]. Hence, the bias circuit is one
of the most important parts of this design.
Fig. 1 shows the bias circuits for HBTs. Traditional
passive mode is composed of two dividing resistors, as
shown in Fig. 1 (a). When input power increases, the
voltage and current applied to the base-emitter diode will
be restrained owing to the clamping characteristic of the
diode. The average DC current rectified by the base-emitter
diode will increase with the input power. However, the
base-emitter voltage Vbe will decrease by ΔVbe. This will
result in transconductance drop or gain reduction, which
means poor linearity. Consequently, in order to obtain a
good linearity performance, the bias point should maintain
a constant level when input power changes. An effective
HAN et al.: Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit 161

way to compensate the ΔVbe is to adopt the active biasing Applying Taylor series in (5), Vbe is obtained as
technique[7]. As shown in Fig. 1 (b), the linearizing active
β ( β + 1) I ref
bias circuit is used as a predistorter in this design. N1 and Vbe = VT ln
N2 indicate the emitter area factors of corresponding I S ( β ( β + 1) + 1 + N 2 N1 )
transistors. The virtual current model ΔIbe shows the VT ΔI be
− − ΔI be R2 . (6)
increase of base current in the large-signal region. To I b1 ( β ( β + 1) + 1 + N 2 N1 )
simplify the analysis, it is assumed that all transistors in the
bias circuit have the same forward current gain β and Equation (6) can be rewritten as
saturation current IS. The ratio of the transistor size used in Vbe = C1 − (C2 + R2 )ΔI be (7)
the bias circuit and the LNA is N1: N2. In order to mirror the
with
current correctly, the resistors ought to satisfy R1N2 = R2N1,
β ( β + 1) I ref
and the relation of the currents is IbeN1 = N2Ib1. The current C1 = VT ln
IR3 is ignored as R3 is usually very large. I S ( β ( β + 1) + 1 + N 2 N1 )
A HBT’s V-I equation is VT
C2 = ,
⎛I ⎞ I b1 ( β ( β + 1) + 1 + N 2 N1 )
Vbe = VT ln ⎜ c1 ⎟ (1)
⎝ IS ⎠ where C1 and C2 are constant. Equation (7) shows that Vbe
where VT is the thermal voltage (kT/q), 26 mV in room is almost independent of ΔIbe if R2 is chosen as the
temperature. minimum value that satisfies the correct current division.
According to Kirchhoff laws, the currents flow at each Then the LNA will have a good linearity performance
node are expressed as because its operating point is hardly changed. However, a
small R2 will result in bad NF because it can not effectively
I c1 = I ref − I b 2 (2a)
prevent RF leakage signal from going into the bias circuit.
Ie2 Therefore, the value of R2 should be traded off between NF
I b2 = (2b)
β +1 and linearity.
Ie2 = I b1 + I be + ΔI be (2c)

Ib1 =
I c1
. (2d) 3. LNA Circuit Design and
β Implementation
By using (1) and (2), Vb1 is expressed as
Fig. 2 shows the architecture of the proposed LNA. The
⎪⎧ 1 ⎡ β ( β + 1) I ref ⎤ ⎪⎫ cascode configuration is adopted because of its good
Vb1 = VT ln ⎨ ⎢ ⎥ ⎬ . (3) trade-off among low noise, high gain, and good isolation[8].
⎪⎩ I S ⎣ β ( β + 1) + 1 + N 2 N1 + ΔI be I b1 ⎦ ⎪⎭
Emitter degeneration is employed to achieve good input
From Fig. 1 (b), Vbe can be expressed as matching and low noise figure at the resonance frequency
Vbe = Vb1 − ΔI be R2 . (4) of the input network and improve the linearity of the LNA.
The matching networks are outlined with the dashed
Substituting (3) into (4) gives
boxes[9] in Fig. 2. The input matching network is designed
⎧⎪ 1 ⎡ β (β + 1) Iref ⎤ ⎫⎪ to synthesize the optimum reflection coefficient for mini-
Vbe = VT ln ⎨ ⎢ ⎥ ⎬ − ΔIbe R2 . (5)
⎩⎪ I S ⎣ β (β + 1) + 1 + N2 N1 + ΔI be Ib1 ⎦ ⎭⎪ Vout

Lc
Iref Ic2
Ib2 L
Vb Q2 C RL
R1
Ic1 Vb2 Ie2 Output
− Vin
Ib1 Ibe1 Ibe matching
R1 R2 Lb
N1 N2 RS
Vbe VS Input
IR3 Vbe − Q1
R2 Vb1
ΔIbe matching
Vref R3 Zin
Le

(a) (b)
Fig. 1. Bias circuit: (a) traditional passive and (b) linearizing
active mode. Fig. 2. Cascode architecture with matching networks.
162 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, VOL. 7, NO. 2, JUNE 2009

mum noise figure from the characteristic impedance[10]. A
conventional series-connected inductor Lb is inserted
between the source and the input to match the input to 50 Ω.
The input impedance can be expressed as
⎡ ⎤
g m Le 1
Z in = + j ⎢ω ( Lb + Le ) −
Cπ ⎣ ω C π
The degeneration inductor Le achieves the real part
input matching[11]. The series-connected inductor Lb
provides the imaginary-part input matching combined with
Le. To realize input matching, the real part of (8) should be
50 Ω, whereas the imaginary part should be zero at the
required operating frequency. According to (8), the
required base inductor Lb is usually very large to make the
imaginary part be zero. Since integrated inductors with
large values exhibit low quality factor and contribute much
thermal noise as a result of parasitic resistances. To save
the chip area, Lb is realized by off-chip inductors taking
into account parasitic inductance due to bonding wires.
There are various impedance matching networks to realize
output matching, such as L-match, T-match and π-match.
An L-match network making up of L and C is introduced to
make the output impedance matched in this design. The
L-match has least components so that it eases the output
matching.
Fig. 3 shows the final circuit of the proposed LNA. The
amplification of signal is provided two cascode transistors
Q1 and Q2 with inductive degeneration Le. The RF input
signal comes into the circuit through the base of Q1. The
output signal is accessed from the collector of Q2. The
cascode transistor Q2 improves reverse isolation between
input and output terminals and lowers Miller multiplied
capacitance. Iref1 and Iref2 are reference currents from
bandgap current reference. R1 offers a voltage bias to Q2.
Q3, Q4, R2, and R3 consist of the bias circuit for Q1. Q1 and
Q3 compose a current mirror. To achieve a complete mirror,
R2 is N times of R3. And R3 needs to be bigger enough to
prevent RF leakage signal from going into the bias circuit.
Q3 should be one Nth of Q1 to lower the power
consumption. Q4 offers a base compensation of Q1. Bypass
capacitors C1 and C2 are introduced to filter the RF signal
⎥. (8) in the bias circuit. Q5 and R4 provide a DC loop to ground.
⎦ The designed LNA shows an IP1dB of −11.52 dBm, a power
gain of 21.46 dB, and a NF of 1.27 dB. The amplifier draws
10 mA from a 3.3 V supply.
The proposed LNA is designed in a 0.35 μm SiGe
BiCMOS process. This process is chosen because of its
balance among performance, cost, and complexity.
4. Simulation Results
The small signal S-parameters (S11, S12, S21, and S22),
NF, and IP1dB of the proposed LNA are simulated with
Cadence Spectre RF. The operating frequency of the LNA
is 1.34 GHz±60 MHz. Post-simulation results show that the
LNA achieves comparable performance than previous
results with the linearizing bias circuit.
Fig. 4 shows the layout of the LNA. The parasitic
effects are extracted and taken into account in the post-
layout simulations. The die size is 0.26 mm×0.20 mm
including the bias circuits.

Fig. 4. Layout of the proposed LNA.

Iref2 Lc
Iref1
21.6 1.32
R4
Q4 C2
Q2 Cout
C
21.3 1.29
R1 R2
Q3 Q1
NF (dB)
S21 (dB)

NF (dB)

L
Q5 C1
Le rfout 21.0 1.26
S21
R3 Lb NF

Cin
20.7 1.23
1.28 1.32 1.36 1.40
rfin
Frequency (GHz)

Fig. 3. Simplified schematic of the proposed LNA. Fig. 5. Post-layout simulations of S21 and NF against frequency.
HAN et al.: Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit 163
−13 −6 degrading other performance. The linearity enhancement
S11 mainly owe to the use of the linearizing bias circuit.
S22 Moreover, the proposed LNA has a higher gain, lower NF,
−14 −9
better linearity, and smaller area compared to the
previously reported works. Good trade-off is obtained while
S11 (dB)

S22 (dB)
S22 (dB)
dB)
−15 −12
not increasing power consumption.

5. Conclusions
−16 −15
1.28 1.32 1.36 1.40 A high gain LNA with a linearizing bias circuit is
Frequency (GHz)
presented in this paper. The active biasing technique has
Fig. 6. Post-layout simulations of S11 and S22 against frequency. been expounded and compared with traditional passive
biasing technique. Formula derivation is also given to
12
Input referred 1dB compression = −11.52
explain the principle of linearity enhancement. Since the
linearizing bias circuit does not need any area consumptive
devices, it can be easily realized on chip. Based on the
Output power (dBm)

8 1st order
1dB/dB active biasing technique, both high linearity and high gain
characteristic can be obtained with the linearizing bias
4
circuit but no deterioration of other performance. Proved by
post-layout simulation results, the proposed LNA achieves
1st order freqency = 1.34 GHz a good trade-off among high linearity, high gain, and low
0
NF while not increasing power consumption and chip size.
−20 −18 −16 −14 −12 −10 It shows an IP1dB of −11.52 dBm, a power gain of 21.46 dB,
Input power (dBm)
and a NF of 1.27 dB with a current consumption of 10 mA
Fig. 7. Post-layout simulation of the IP1dB. from a 3.3 V supply.
Table 1: Comparison with previous work
Freq. S21 NF IP1dB Area BiCMOS Acknowledgment
Ref.
(GHz) (dB) (dB) (dBm) (mm2) (μm)
The authors would like to thank BroadGalaxy Electronics
[12] 3-5 11.8 <3.0 −16 1.13 0.35
Technology Ltd. for technical assistance. The authors would also
[13] 5-6 20 <2.5 −16.5 1.56 0.35
like to thank Da Chen, Dong Li, and Lu Shen for their kind help.
[14] 5 18.3 1.65 −12.25 N/A 0.5
[7] 2.14 20 1.65 −12.3 0.83 0.35
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Wen-Tao Han was born in Shaanxi Province,
China, in 1983. She received the B.S. degree in
microelectronics from the University of
Electronic Science and Technology of China
(UESTC), Chengdu, in 2006. She is currently
pursuing the M.S. degree with State Key
Laboratory of Electronic Thin Films and
Integrated Devices, UESTC. Her research interests focus on RF
ICs.
Qi Yu was born in Shandong Province, China,
in 1972. He received the B.S. and M.S. degrees
from UESTC, in 1994 and 1997, respectively,
all in microelectronic. Currently he is an
associate professor with State Key Laboratory
of Electronic Thin Films and Integrated
Devices, UESTC. His research interests
include VDSM circuit and SOC, ADC/DAC, and ULSI reliability
simulation & monitoring.
Song Ye received the M.S.E.E. in Communi-
cations and M.A.Sc. in Microelectronics from
the University of Toronto. From 1996 to 2004,
he had been with OKI Semiconductor,
Motorola, SpaceBridge, and Engim where he
has developed RF and analog chips for mobile
communications, radars, and satellites. He is a
committee member of IEEE-ISCAS. Currently he is a jointed
professor with Southeast University, and the chief technology
director with BroadGalaxy Electronics Technology Ltd. His
research interests are in wireless RF IC architectures and their
building block integrations as well as mixed-signal design using
SiGe, CMOS, and GaAs process.
Mo-Hua Yang was born in Sichuan Province,
China, in 1945. He received the B.S. degree in
radio-electronics from Sichuan University and
M.S. degree in microelectronics from UESTC,
in 1967 and 1981, respectively. He is currently
a professor and Ph.D. advisor with School of
Microelectronics and Solid-State Electronics,
UESTC. His research interests include ULSI mixed signal
processing, GaN/SiGe device and circuits, and nano-electronics.