CSE45401 VLSI Design Lab

Spring 2004

CSE45401 VLSI Design Lab

Lab #3 Standard Cell Design This lab has to be completed in one lab session

Introduction
Creating a custom design for a complex logic function may prove to be quite expensive and time consuming. So, a number of relatively inexpensive design methods have been adopted to create complex designs that minimize the design time. One of the most popular design methods is the standard cell methodology. The rationale for using standard cells relates to the desire to minimize the time-to-market for a new IC design; hence, a premium is placed upon reuse. Most complex logic functions can be implemented using a limited number of gates (NAND, NOR, Inverter, etc). These gates are laid out in L-Edit using strict guidelines and are called standard cells. A few hundred of these standard cells are usually designed, verified, documented and then placed in a standard cell library. A typical library may contain cells such as inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. These gates can be interconnected with each other to create a more complex logic function with little effort. This hierarchical design process allows the designer to save time and cost by using the standard cells for many designs. This also allows the process of designing complex logic functions to be highly automated. However, this approach does not allow a designer to fine tune the design for best performance. In this laboratory you will first learn about standard cell layouts using the Tanner Research Standard Cell Library. Next you design an inverter in standard cell format. Then a timing analysis of the inverter will be made using Spice simulation. Finally, the new cell that you designed will be added to the standard cell library.

Procedure
Dissect a Standard Cell
To learn how to layout standard cells in L-Edit, you will first dissect one of Tanners standard cells. To begin, start L-Edit and then open the library.tdb file. This file contains a number of circuits in standard cell format that can be used repeatedly in large circuits. Use the cell browser to open the cell Inv [View > Cell Browser > Inv]. This cell contains a digital inverter. You will use this cell to learn how and why a standard cell is constructed. Print out a copy of this cell to take notes. Move your cursor to the very bottom of the circuit. The bottom edge is at y = -8. The blue metal 1 line running horizontally is the GS2 line, one of two unidirectional signal lines in the cell, the other one, the GS1 line runs along the top of the circuit at y = 74. Both are 5 wide and run the length of the cell. Label both of these lines on your printout. Next note the Vdd and GND lines. They also run horizontally and are just inside the GS2 and GS1 lines. Use your cursor to determine their locations and widths, and label them on your printout. In every standard cell in this library, these four lines are in the same positions and have the
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Spring 2003 same widths. Only their lengths will change to fit each unique cell. By following this standard, larger circuits can be created simply by placing standard cells adjacent to one another in a new cell. The common nodes of each will line up to create connections. Along with having the signal and power lines align, the N-Well and select layers must also line up. On your printout, label the top and bottom y-coordinate of the N-Well, the pMOS bulk N-Select, the pMOS source and drain P- Select, the nMOS bulk P-Select, the nMOS source and drain N-Select. Now open one of the other circuit cells in the library and verify that these layers are in the same location. You will also see ports labeled in this cell. The GND, VDD, GS1, and GS2 ports define the circuit connections for Spice, while the port Abut defines the outline of the circuit so that L-Edit may place the standard cell into a circuit automatically during an Autoroute.

Layout of a Standard Cell

Open a new file based on library.tdb [Click the Browse button and select library.tdb for Copy TDB setup from file:], and then click OK. For this Lab you will be laying out a CMOS inverter in standard cell format. Since many of the pieces of a standard cell are universal, it saves time to start with a template that contains these pieces. Create a new cell for this template [Cell > New] and name the new cell ABCtempl, where you replace ABC with your initials and click OK. To copy the template from the library.tdb file, Open the instancing menu [Cell > Instance] the select library.tdb file. It opens up a list of all the cells in the library file. , select Celltempl and click [OK]. You should now have an instance of the cell Celltempl in your ABCtempl cell. As above the layers of the cell must be paced at the proper coordinates within the cell. To do this, move the circuit so that the bottom left hand corner of the GND bus is at (0,0). Now the instance must be broken so that this cell is independent of the others. Do this by flattening the cell [Cell > Flatten]. Now you have a template for designing custom standard cells. All of the basic layers are included with the proper heights and placement. Now you can begin your inverter. Create a new cell [Cell > New] and name it ABCInv. Instance your template cell into the new cell, position the circuit at the origin and flatten the cell. You are now ready to layout the gate and active regions of the inverter. Consider the structure of the inverter circuit. The gates of both transistors are connected and constructed of the same material so lets start with the gates of both the transistors. Draw a rectangle of Poly reaching from y = -2 to y = 68 with a width of 2 and center it in the x-direction (Bottom left corner of Poly at (8,-2)). Now active regions need to be placed over the N-Select and P-Select regions to create the sources and drains of the nMOS and pMOS transistors. First draw the active of the nMOS by placing a rectangle of Active from (2,0) > (14,28). Note: this notation specifies the lower left-hand corner and the upper right hand corner of the rectangle. Since a rectangle is symmetric this completely defines the rectangle and will be the notation used from now on to specify rectangular elements. Add two more rectangles of Active, one from (0,0) >( 2,6), and another from (14,10) > (16,28). This completes the Active for the nMOS transistor. Now 2

Spring 2003 draw the Active of the pMOS from (2,38) > (14,66). Now add two more rectangles in Active, one from (0,60) > 2,66) and the other from (14,38) > (16,56). This completes the Active for pMOS. Now the sources of the transistors need to be connected to their respective rails (GND and Vdd). To connect from Metal 1 rails to the sources, which are on Active, contacts need to be placed on the Active to connect to Metal 1. Either the left or right sides of your transistors could be used as the source, but for now we will choose the left side to be the source and the right side to be the drain. This is an arbitrary decision; however, and should be left to the judgment of the designer in future cells. To make the nMOS connections, draw a Metal 1 rectangle from (3,8) > (7,20) and then place three 22 squares of Active Contacts centered on this vertical GND Metal 1 layer at y= 9, y= 13, and y= 17. For the pMOS connections, first draw a Metal1 rectangle from (3,39) > (7,58) and then place four 22 squares of Active Contacts centered on this vertical Vdd Metal 1 layer at y= 40, y= 44, y= 48, and y= 52. Now the drains of both the nMOS and pMOS need to be connected together. Draw Metal 1 from (11,11) > (15,55). Place eight 22 squares of Active Contacts centered on this vertical Metal 1 layer at y= 12, y= 16, y= 20, y= 24, y= 40, y= 44, y= 48, and y= 52. Lastly, the bulk contacts for the pMOS and nMOS transistors are to be made. This is done by placing 22 squares of two Active contacts, one from (2,2) > (4,4) and the other from (2,62) > (4,64). At this point run the DRC to insure that you have not violated any design rules. If there are any violations, then fix those violations before continuing. The basic circuit is now complete; however, if the circuit were left as is, it would be difficult to connect it to other circuits. In standard cell design vertical lines of Metal 2 are used to make signal connections to and between standard cells. Ports are used to specify where Metal 2 can be placed for connecting the circuit. Thus any port that will be connected outside of the circuit must be placed on Metal 2. For an inverter these are the In and Out signals. Start with the Out signal, this is the connection between the two drains and is already on Metal 1, so now it needs to be brought up to Metal 2. This is done using a Via. Vias are similar to contacts as they connect between two layers and must be 22. Place a square of Via in the center of the Metal 1 rectangle connecting the two drains. Now place a square of Metal 2 with the dimensions 44 directly over the Via. Now the In signal must be brought to Metal 2. This will be more difficult. The In signal is on the gates of the transistor, which are on the Poly layer. There is no way to go directly from Poly to Metal 2, so instead we will go from Poly to Metal 1 and then from Metal 1 to Metal 2. First we need to create an area of Poly for the contact. Place a rectangle of Poly from (3,31) > (8,37). Next place a 22 Poly Contact over this Poly from (5,33) > (7,35). Add a 5 wide Metal 1 rectangle from (3,23) > (8,36). Now place a 22 square of Via from (4,24) > (6,26). Finally place a square of Metal 2 with the dimensions 44 directly over the Via.

Spring 2003 The last layers to be added to the circuit are the port layers. These layers do not change the circuit in any way. They are used only to help the program in making connections and extracting netlists. Many of the ports are already defined. Look for the GND, GS1, GS2, and Vdd ports that are already present in the circuit. This leaves the ports for In and Out to be placed. These ports will be different from the others since they are signal ports, not Global ports. The Global ports (GND, Vdd, etc.) run horizontally and are placed on the edges of Metal 1. The signal ports run vertically and are on Metal 2. Using the two metals allow connections to be made without creating short circuits. There are three steps in creating a signal port. The first is to draw a port line through the center of the port. Find the Port tool on the toolbar. It is an A with a box above it. Select this tool and select Metal2 from the palette and draw a horizontal line through the center of Metal 2 of In. A dialog box will appear after you have drawn the port. Give the Port name as In. Now draw vertical rectangles 4 wide centered on this line. One will go from the line to the top of Vdd. Another will go from the line to the bottom of GND. Give the same port name In for both. Repeat this for the Out connection and your circuit is complete. If you are unsure on where to place your ports, look at your printout of Tanners standard inverter. The last step to meet standard cell requirements is the placement of the subcircuit ID layer and the Abut port. Draw a rectangle of Icon/Outline layer from (0,0) > 18,66). Now use the port tool to draw a port over the same rectangle. Place the port on Icon/Outline layer and name the port Abut. This layer and associated port tell L-Edit where your circuit is. Run the DRC to verify that there are no violations in your design. This inverter is functionally correct; however it is far from ideal. Examine this inverter and suggest ways in which it can be improved.

Create a New Library

Now that you have a custom circuit it needs to be placed into a library with other cells. We will use the Tanner Library as the base and add your cell to it. Open up library.tdb in L-Edit. Since we do not want to change the original file, re-save the file under the name ABClib.tdb, where ABC has been replaced with your initials. This can be done by clicking [File > Save As]. Now create a new cell and call it Temp. Open the instancing menu and instance your inverter from the file you created above. File > Save once. Now view the Cell Browser [View > Cell Browser]. Scroll through the list of cells and look for ABCInv. You will see that your circuit has been copied into this file. Now you can delete the cell Temp.

Extract Netlist
Re-open your inverter cell if you have closed it. To extract a Spice netlist of this circuit, select [Tools > Extract] from the main menu. The circuit-extraction window will appear

Spring 2003 as an overlay to the Working area. Set the options in this window (as in your Lab#1 handout) and extract the circuit. In Extract Output Filename enter the entire path for the location you would like the file placed, along with filename ending in *.spc extracted text file. To avoid problems, the name of the file must be kept under 8 characters with no spaces. Always select the Write Node Names in Comments option. This is very helpful because it places these comment lines in the *.sp portion of the *.spc extracted text file. This will assist you in error checking. It also helps provide good documentation so that others can evaluate the designed circuit. Select the Write Device Coordinates (Locator Units) option. This will allow you to relate specific devices on output listing to the physical layout. Select Names in the Write Nodes As option. These will then be the node names in the extracted *.spc extracted text file. Select the Write Verbose Spice option. With this option, a significant number of comment statements are added to the output file to help understand the relationship between the original Spice netlist and the extracted netlist.

Spice Simulation
Once the circuit is extracted add additional statements as required (refer to Lab #1 handout) and perform Spice analysis. For timing analysis, use the following input signal. Vin In 0 Pulse (0 5 0 0.01n 0.01n 10n 20n) And run simulation at 0.1ns steps for a total duration of 30ns. Measure the propagation delay (tPHL and tPLH ) and the rise and fall times of the output waveform. There is no formal report submission for this lab, but everything has to be entered in your lab notebook.