Enabling success from the center of technology

I nt r oduc t i on t o Xi l i nx
FPGA Desi gn
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
2
Goals
Understand basic Xilinx FPGA architecture, families,
and tool solutions
Understand the ISE 9.1i design flow for an FPGA
design using an HDL
Understand what resources Avnet and Xilinx have to
help make your next FPGA design a success
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
3
Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
4
Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
5
FPGA and CPLD Overview
Low-cost
FPGA
High-performance
FPGA CPLD
..
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
6
Basic FGPA Architecture
Reg
Reg
DDR mux
3-State
Reg
Reg
DDR mux
PAD
Reg
Reg
Input
Output
I3
I1
I2
I0
O
D Q
S
E
T
R
S
T
C
E
D
Q
S
E
T
R
S
T
C
E
0 1
I3
I1
I2
I0
O
0 1
CLKA
DIPA
ADDRA
DOPA
CLKB
ADDRB
DIA DOA
DIPB DOPB
DIB DOB
CLKIN CLK0
CLK90
CLKFX
Clocking
Memory
Logic
IO Blocks
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
7
Example Product Matrix Spartan-3A
....
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
8
Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
9
Xilinx Design Flow
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
10
ISE 9.1i Project Navigator
Sources
in project
Processes
for source
Message
Console
Viewing Area
....
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
11
Demonstration Block Diagram
Counter
XC3S700A
Input_Clock
Counter_Reset
Counter_Enable
Switches
50MHz
Clock
LEDs
Digital Clock Manager GC
IOBs
IOB
IOB
LED[0..7]
Spartan-3A Starter Board
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
12
Demo 1 Create a New ISE 9.1 Project
Create a new HDL project
Configure the project through the New Project
Wizard
Setup the designs I/O ports
View the generated code skeleton
Examine the Help menu
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
13
Design Entry
Enter the logic for the design
ISE Project Navigator features
assist with entry
Integrated text editor
Language templates
Example code
State machine editor
Cores
Architecture wizards
Clocks
SERDES
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
14
Demonstration 2 Design Entry
Create the counter using the
language template
Create the DCM instantiation using
the DCM wizard
Add HDL code to combine the
design
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
15
Simulation
Test Bench WaveformGenerator
or
Text Editor
Simulator
Results
(WaveformViewer)
Stimulus
Target System(UUT)
Other Models (e.g. Memory)
Testbench
Results (Text)
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
16
Demonstration 3 - Simulation
Create stimulus using waveform
editor
Run simulation
View waveform
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
17
Synthesis
Xilinx Synthesis Tool
Verilog and Verilog 2001
VHDL 1993
Mixed Verilog and VHDL
Plug-in provision for 3
rd
party
synthesizers
Check Syntax
Syntactical Checker
View design content
RTL Viewer
Technology Viewer
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
18
Demonstration 4 Synthesis
Check syntax
Synthesize
Use technology view to show
design
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
19
User Constraints
User Constraints File (UCF)
File extension is .ucf
Project file for constraints
Pin Location
Assign pin locations using Assign
Package Pins or text editor
Drag and drop capable
Timing
Assign timing constraints using
Create Timing Constraints or text
editor
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
20
Demonstration 5 User Constraints
Assign package pins
Create global timing constraint
View UCF file
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
21
Implementation
Push button flow works for many
designs
J ust double clickto implement
Primary implementation phases
Translate
Map
Place And Route (PAR)
Timing analysis
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
22
Design Summary
Build results shown in
Design Summary
Key elements
Status
Device utilization
Performance
Reports links
....
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
23
Timing Analyzer
Launch after PAR
completes
View results for each
timing constraint
Failing constraints
shown in red
Interactive mode
Try different speed
grade
Look for specific
timing paths
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
24
Demonstration 6 - Implementation
Run push button flow
Double click implementation
View design summary
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
25
When the FPGA is powered on, it has no
identity
Configuration is the process of loading the
FPGA SRAM with an identity
This identity is called a bitstream
Non-volatile
Memory
SRAM-based
FPGA
Bitstream
This can be done two ways
PC connection to the FPGA Good for debug
Non-volatile, on-board memory Required for
an embedded system
Configuration
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
26
Configuration Process
Generate Programming File
Bitstream (.bit) for FPGA
PROM image file (.mcs) for non-volatile memory
Configure Device
Use a J TAG download cable
Load bitstream directly to FPGA
Load PROM image file to non-volatile memory
Using a PROM
Serial or Parallel Interface
Xilinx or 3
rd
party solutions
ISE
iMPACT
9.1i
JTAG
Xilinx Cable
Xilinx Cable
PC Board
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
27
Demonstration 7 Configure Device
Create FPGA bitstream
Download bitstream directly to FPGA
using JTAG
Verify design is operational
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
28
Agenda
Introduction to Xilinx devices and tools
Create and build a design
Where to go from here
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
29
Xilinx Available Resources
Documentation
Datasheets
Application
notes
Design
guidelines
Support database
Reference
designs
Training and
tutorials
Tools to simplify
design
Soft IP
www.xilinx.com
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
30
Avnet Available Resources
Avnet Field Application Engineers
Local Xilinx FAE
Regional Specialists
I/O, DSP, and embedded processing
Trainings
On-ramps (1-2 hour)
Speedways (1/2 and full day)
Design Resource Center
Development boards
Avnet Engineering Services
www.em.avnet.com/drc
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
31
Xilinx Tool Summary
ISE Foundation
Windows, Linux, Solaris
support
ISE Simulator Lite
Evaluation versions
ISE WebPACK
Windows & Linux support
ISE Simulator Lite
Limited Virtex series FPGAs
FREE Web download or DVD
FPGA real-time
debug via
embedded logic
analyzer
ModelTech
HDL simulator
X-Fest Specials
ChipScope Pro MXE-III FPGA Kits
For I SE Foundation
HDL simulator
Full ISE Simulator
Optional Accessories
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
32
Summary
Xilinx offers multiple FPGA families
and tool solutions for your next
design
The ISE 9.1i design flow has been
explained and demonstrated in a
real design
Avnet and Xilinx both have
extensive resources to assist with
your design efforts
Design Entry
Simulation
Synthesis
User Constraints
Implementation
Configuration
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
33
Whats Next?
Contact your FAE
Get Xilinx tools
ISE WebPACK can be downloaded free
Get a development board
Spartan-3A Starter Board highlighted in this session
Create your own design
Or attend an Avnet Speedway workshop in your area
Enabling success from the center of technology
Thank You!
Any Quest i ons?
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
35
Third Party Tools
Synthesis
Synplicity
Mentor
Simulation
Mentor
Aldec
JTAG
Universal Scan
Many more than could be listed
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
36
Advanced Capabilities
Tools
ChipScope Pro
XPower
PlanAhead
Embedded Development Kit
Sysgen for DSP
Features
SmartPreview
SmartGuide
Partitions
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
37
ChipScope Pro
Real-time verification tools provide on-chip debug
Analyze any internal FPGA signal, including
embedded processor busses
Reduce overall design time
Access signals and nodes on-chip
Verify design in hardware
50X faster than simulation
Integrated with the Xilinx design flow
Add ChipScope Pro as a project source
Modify signal probes in minutes
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
38
ChipScope Pro Interface Makes FPGA Debug Easy
Access ChipScope cores via JTAG or user defined
Trace port
Configure FPGA, define trigger conditions, and view
data via ChipScope Pro analyzer running on a PC
ChipScope Pro Analyzer functions as a logic
analyzer, bus analyzer, and control console
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
39
XPower
XPower provides power and thermal estimates after
for FPGA and CPLD designs
Estimates power
consumption by net, logic
element, or hierarchical
block
Verifies junction
temperature limits are not
exceeded
Included in all ISE configurations
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
40
PlanAhead
Hierarchical Design and
Analysis
Visually comprehend
design
Correct design issues early
Flexible Floorplanning
Block level implementation
Enables Block-based
Methodology
Team design
Powerful Addition to ISE
PlanAhead Flow
RTL
Synthesis
ISE P&R
PlanAhead:
Analysis &
Floorplanning
PlanAhead Flow
RTL
Synthesis
ISE P&R
PlanAhead
Analysis &
Floorplanning
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
41
Embedded Development Kit (EDK)
Embedded Development Kit
Single development tool for Microprocessor hardware
and software development
Xilinx Platform Studio Integrated Design Environment
SW Development
Download to Board
SW Debug
Industry Standard SW
Development Flow
Industry Standard
HW Development Flow
Logic Development
Place and Route
Download to FPGA
HW Debug
Create Processor, Bus &
Peripheral Subsystem,
Software Drivers,
BSP
Innovative Technology
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
42
Xilinx System Generator for DSP
System Generator for
DSP
Tightly integrated with
MATLAB and ISE 8.2i
IP Toolbox plug-in for
simulink
Full hardware design
and simulation
MATLAB
TM
Algorithm Development
and Analysis
System-Level Design
Simulink
TM
3
rd
party prototype
and development
boards
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
43
SmartCompile - SmartPreview
SmartPreview allows Pause/Resume in PAR
Saving and viewing of intermediate results
Easily identify timing critical regions within the design
SmartPreview allows users to
Create bitstream for lab debug
Preserve latest results as snapshot
and continue processing
Exit process immediately
Latest results will be saved
Cancel current iteration and move to next iterations
Applicable to Multi-Pass Place and Route (MPPR) runs only
Provides Greater Visibility into Implementation
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
44
SmartCompile - SmartGuide
When to use SmartGuide?
Minimize impact of a small change
Faster runtime (2X average; up to 4X)
Is it easy to use SmartGuide?
Absolutely, no need for methodology or constraint
changes
Simply turn-on SmartGuide in ISE (Source -> Use
SmartGuide)
Why will SmartGuide work?
Synthesis: New algorithms to maximize
naming repeatability and maintain performance
Implementation: New algorithms to maximize
layout preservation while meeting timing goals
and ensuring design routability
Testing: Thorough testing using 150+ customer
HDL test cases
Physical Layout
Physical Layout with
small design change
SmartGuide
Small
Change
Small
Change
Enabling success from the center of technology
Copyright 2007. Avnet, Inc. All rights reserved.
45
SmartCompile - Partitions
When to use Partitions?
Want exact preservation of unchanged partitions
Want faster runtime
2.5X average; up to 6X
Design has natural hierarchy
Is it easy to use Partitions?
Yes! Simply right-click in ProjNav sources view
Why will Partitions work?
Database copy and paste
Customizable preservation level: just synthesis
or everything down to routing
Automatic dependency management
Top
A1 A2
B C
Logical Design (HDL)
A
Physical Layout after change
Original Physical Layout