CHAPTER 5 DESIGN VERIFICATION PROCEDURES

The logic design and design correctness validation of this design is done using Modelsim simulator; synthesis and timing simulation is done usingXilinx ISE and Modelsim simulator software. Following sections elaborate the steps required to perform the design verification.

5.1 DESIGN SYNTHESIS

Synthesis is the process of translating, or compiling HDL code into a network of logic gates. Upon finishing the design synthesis, Xilinx ISE reports the compilation results. The most important results needed are: i. Logic elements ii. Critical path delay iii. Maximum frequency, fMAX iv. Memory bits used Logic elementis the generic term for a basic building block of all devices supported by the Xilinx software. A logic element is also generally known as a logic cell. It also determines the area used by the design. Lower count of logic element means a smaller design is produced. Critical pathis a circuit part in the design with the longest overall duration, determining the shortest time to complete the circuit calculation. The duration of the critical path determines the highest possible speed that can be achieved by the complete design. It is important for the design performance and if the delay is too high, designer may need to redesign the critical path and so that the design performance would be better. Maximum frequencyor fMAX is the maximum clock frequency that can be achieved without violating internal setup (tSU) and hold (tH) time requirements. The Xilinx software analyzes and reports fMAX following timing analysis. The Timing Analyzer calculates fMAX using the following equation: fMAX = 1 / (<register to register delay > - <clock skew delay > + <micro setup delay > + <micro clock to output delay>) Where clock skew delay is calculated with the following equation: (clock to destination register delay) (clock to source register delay)

Memory bit isan individual memory address in a memory block that isRandom Access Memory (RAM)), Read Only Memory (ROM), or Content- Addressable Memory (CAM). For example, the content5_[4..0] memory word defines a byte of memory in which the individual memory bits are content5_4,content5_3, content5_2, content5_1, and
content5_0.

To perform the design synthesis in Xilinx, few steps are involved: 1. Create a project and load the design Verilog source file 2. Set the targeted hardware and parameters 3. Compile the design

5.2 Functional and Timing Simulation

From functional simulation, the design correctness as expected is verified. Starting from the smallest modules in the lowest hierarchy of the hardware component, waveform simulations are performed for all the modules in the hardware design. Test vectors are used for this purpose. Few important parameters are obtained from waveform simulation, which are: i. Clock cycle ii. Time taken iii. Throughput Clock cycle is the total number of clock cycle taken to complete the design simulation. Time taken is the overall time for the design to produce a correct output. Throughput is the number of bits that can be processed by the design within a time of one second. These three parameters depend on the targeted hardware and the supported frequency for the hardware. Normally, clock cycle is counted from the moment of the circuit starts to process the initial data or input until it can produced the final desired output or results. Then, time taken is a multiplication of the number of clock cycle and the hardware frequency. The design throughputis calculated based on the following formula Throughput = average number of bits processed clock period

5.3 Implementation Tools

Simulation: Modelsim 10.1 Synthesis : Xilinx ISE 12.1

5.3.1 XILINX ISE 12.1 Implementing Verilog HDL Designs Using Xilinx ISE This following shows how to create, implement and synthesize Verilog HDL designs for implementation in FPGA chips using Xilinx ISE 12.1 1. Launch Xilinx ISE from either the shortcut on your desktop or from your start menu under Programs Xilinx ISE 12.1 Project Navigator.

2.

Start a new project by clicking File New Project

3.

In the resulting window, verify the Top-Level Source Type is VHDL. Change the Project Location to a suitable directory and give it what ever name you choose

4.

The next window shows the details of the project and the target FPGA. We will be synthesizing designs into FPGA. so it important to match the target with the

particular board/chip you will be using. It will be done in Virtex6 XC6VCX240T chip that comes in a FF1156package with a speed grade of -1 as shown below

5.

Since we are starting a new design the next couple of pop-up windows arent relevant, just click next and next and Finish. You should now be in the main Project Navigator window. Select Project Add source from the menu.

6.

7.

The Verilog files to be added from the specified folder.

8.

Next window shows the successfully added source files.

9.

The source files which are added to the Top module are get synthesized by synthesize XST

10.

Synthesized report can be obtained on the console and device utilization also estimated

From the console the maximum frequency obtained is 339.328MHz. which is used to calculate the Throughput as mentioned in section 4.2 Throughput = 339.328MHz 128 = 43.43Gbps

SIMULATION RESULTS
For simulation using the Modelsim simulator of version 10.1c 1. ModelSim should successfully launch and will open several subwindows by default. For now we just need the Wave and Transcript subwindows, so close the other subwindows. 2. To conduct the simulation we basically need to know two commands, force and run. Force is used to set the value of any input variable. Then Run the

simulation for a specific amount of time.

To use a Force command, in the

transcript window simply type Force, space, logic variable you wish to set, space, the value you wish to assign (0 or 1). Encryption
add wave -r /* force -freeze sim:/top/clk 1 0, 0 {50 force -freeze sim:/top/rst 1 0 force -freeze sim:/top/e_dbar 1 0 force -freeze sim:/top/start_cipher 1 force -freeze sim:/top/key_data 128'h2b7e151628aed2a6abf7158809cf4f3c force -freeze sim:/top/cipher_in_text 128'h3243f6a8885a308d313198a2e0370734 run run run run force -freeze sim:/top/rst 0 0 run force -freeze sim:/top/start_cipher 0 run 6600 ns ns} -r 100 0 0 0

Decryption
add wave -r /* force -freeze sim:/top/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/top/rst 1 0 force -freeze sim:/top/e_dbar 0 0 force -freeze sim:/top/start_cipher 1 0 force -freeze sim:/top/key_data 128'h2b7e151628aed2a6abf7158809cf4f3c 0 force -freeze sim:/top/cipher_in_text 128'hd3925841d02dc09fbdc118597196a0b32 0 run force -freeze sim:/top/start_cipher 0 0 run run run force -freeze sim:/top/rst 0 0 run 6600 ns

Simulation Result For Joint Encryptor And Decryptor

KeyData : 2b7e151628aed2a6abf7158809cf4f3c PlainText : 3243f6a8885a308d313198a2e0370734 CipherText : 3925841d02dc09fbdc118597196a0b32

Encryption Transformationfor every round Round1 : 19a09ae93df4c6f8ee28d48be2b2a08 Round2 : a4686b029c9f5b6a7f3ea50f22b4349 Round3 : aa6182688fddd22fe34a4603efd29a Round4 : 48674dd66c1de3f4e9db158ee0d38e7 Round5 : e0c8d985926b1b87f65bee8c05001 Round6 : f1c17cd0092c8b56f4c8bd555ef320c Round7 : 263de8fd0e4164d22eb7728b177da925 Round8 : 5a19a37a4149e08c42dc1904b11f6c Round9 : ea0465858455d965c3398b0f02dadc5 Round10 : eb5a8b1bb402ea1c3f23813421e84e7d2

Decryption Transformation for every round Round1 : eacb3baf3132e097d2c89075725f94 Round2 : 87f24d976e4c90ec46e74ac3a68cd895 Round3 : bed40adabe16483d4f22c86fec8c04d Round4 : f72279b54843b5ab403d31a93ff0ffd3 Round5 : a178104c4fe8d5633d03a829fefcdf23 Round6 : e1e83597fbc86c4f96aed2fb7c9bba53 Round7 : 5285e3f6a411cf50c86a2f5e9428d707 Round8 : acef1345c1b52373d65acf11b87bdfb5 Round9 : 49457577db3902de8753d2963b89f11a Round10 : d4e0b81ebfb441275d52119830aef1e5

KeyTransformation Round1 : a088232afa54a36cfe2c397617b13905 Round2 : f27a5973c296355995b980f6f2437a7f Round3 : d471e6d8016237a47fe7e887d3e443b Round4 : efa8b6db4452710ba55b25ad417f3b00 Round5 : d47cca11d1833f2f9c69db815f887bcbc Round6 : 6d11dbca880bf900a33e86937afd41fd Round7 : 4e5f844e545fa6a6f7c94fdc0ef3b24f Round8 : eab531fcd28d2b8d73baf52921d2602f Round9 : ac19285777fad15c66dc2900f321416e Round10 : d0c9e1b614ee3f63f9250c0ca889c8a6

Table 5.3 : Comparision with Other FPGA implementation

Design Existing(r=6) Proposed(r=6) Existing(r=6) Proposed (r=6) Prop Enc(r=6) PropJoint Enc/Dec(r=6) Target FPGA Device Virtex-E XCV1000e-8 Virtex-E XCV600e-8 Virtex-2 pro XC2VP20-7 Virtex-2 pro XC2VP20-7 Virtex-6 XC6VCX240T-1 Virtex-6 XC6VCX240T-1 Frequency MHz 170.01 181.32 341.53 373.74 546.44 339.32 Slices 8099 10112 7865 9966 12221 12281 Throughput Gbps 21.76 23.26 43.71 47.83 69.94 43.43