The MOS Transistor

Debdeep Mukhopadhyay IIT Madras

Introduction
So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (V/t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means

MOS Characteristics
MOS majority carrier device Carriers: e-- in nMOS, holes in pMOS Vt channel threshold voltage (cuts off for voltages < Vt)

nMOS Enhancement Transistor

Moderately doped p type Si substrate 2 Heavily doped n+ regions

I vs. V Plots
Enhancement and depletion transistors
CMOS uses only enhancement transistors nMOS uses both

Materials and Dopants

SiO2 low loss, high dielectric strength
High gate fields are possible

n type impurities: P, As, Sb p type impurities: B, Al, Ga, In

Bipolar vs. MOS

Bipolar p-n junction metallurgical MOS
Inversion layer / substrate junction field-induced Voltage-controlled switch, conducts when Vgs Vt e-- swept along channel when Vds > 0 by horizontal component of E Pinch-off conduction by e- drift mechanism caused by positive drain voltage Pinched-off channel voltage: Vgs Vt (saturated) Reverse-biased p-n junction insulates from the substrate

MOSFET Transistors
MOSFET For given Vds & Vgs, Ids controlled by:
Distance between source & drain L Channel width W Threshold VoltageVt Gate oxide thickness tox dielectric constant of gate oxide Carrier mobility

MOS Capacitor
Gate and body form MOS capacitor Operating modes
Vg < 0

polysilicon gate silicon dioxide insulator p-type body

Accumulation Depletion Inversion

+ -

(a)

0 < Vg < Vt + depletion region

(b)

Vg > Vt + inversion region depletion region

(c)

Terminal Voltages
Mode of operation depends on Vg, Vd, Vs + Vgs Vgs = Vg Vs Vgd = Vg Vd Vs Vds = Vd Vs = Vgs - Vgd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation
Vg + Vgd Vds + Vd

nMOS Cutoff
No channel Ids = 0
Vgs = 0

+ s n+

+ d n+

Vgd

p-type body b

nMOS Linear
Channel forms Current flows from d to s e- from s to d Ids increases with Vds Similar to linear resistor At drain end of channel, only difference between gate & drain voltages effective for channel creation
Vgs > Vt Vgd = Vgs

+ s n+

+ d n+

Vds = 0

p-type body b

Vgs > Vt

+ s n+

+ d n+

Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt

p-type body b

nMOS Saturation
Channel pinches off Ids independent of Vds We say current saturates Similar to current source
Vgs > Vt

+ -

+ -

Vgd < Vt

d Ids Vds > Vgs-Vt

n+ p-type body b

n+

I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel? How fast is the charge moving?

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Qchannel =
polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Qchannel = CV C=
polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Qchannel = CV C = Cg = oxWL/tox = CoxWL V=

polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

Cox = ox / tox

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel
Cox = ox / tox Qchannel = CV C = Cg = oxWL/tox = CoxWL V = Vgc Vt = (Vgs Vds/2) Vt
polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.9)

+ + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body

gate Vg

Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v=

Carrier Velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E=

Carrier Velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E = Vds/L Time for carrier to cross channel:
t=

Carrier Velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E = Vds/L Time for carrier to cross channel:
t=L/v

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross I ds =

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross
Qchannel I ds = t =

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross
Qchannel I ds = t W = Cox L

V V Vds gs t 2 Vds V V Vds = gs t 2

V ds

W = Cox L

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt

Now drain voltage no longer increases current

I ds =

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt

Now drain voltage no longer increases current V

I ds = Vgs Vt
dsat

V dsat 2

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt

Now drain voltage no longer increases current

Vdsat I ds = V V gs t 2 = V dsat

V ( 2

gs

Vt )

nMOS I-V Summary

Shockley transistor models 0 V I ds = Vgs Vt ds 2 2 Vgs Vt ) ( 2
Note the dependencies on W, L

Vgs < Vt V V < V ds ds dsat Vds > Vdsat

cutoff linear saturation

Cg ins 0 WL W = K ,K = , Cg = L WL D

Activity
1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change

MOS as switch
MOS can be viewed as switches. The switches are electrically controlled.

NMOS as a switch
Gate=Vdd Vin=Vdd I Load Capacitor Ground Gate=Vdd Vin=0 I Load Capacitor Ground Vgs Vout=Vdd Vgs Vout

Assume capacitor (CL) is initially discharged Gate=1, Vin=1

CL begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt) Signal is degraded

Gate=1, Vin=0
CL begins to discharge toward 0 Good passer of 0.

CMOS Signal Transfer Property

Source Gate Drain pMOS

Gate 0 1

Path Closed Open

Transmits 1 well Transmits 0 poorly

Drain Gate Source nMOS

Gate 0 1

Path Open Closed

Transmits 0 well Transmits 1 poorly

CMOS Transmission Gate

Transmit signal from INPUT to OUTPUT when Gate is closed
Gate (complementary of Gate) Gate

Gate
Source Drain

pMOS OFF ON

nMOS OFF ON

OUTPUT Z INPUT

INPUT

OUTPUT

0 1

Gate

Z : High-Impedance State, consider the terminal is floating

CMOS Inverter
Vcc

Vin

Combines the best of both.

nMOS Operation
Cutoff Vgsn < Linear Vgsn > Vdsn < Saturated Vgsn > Vdsn >
VDD Vin Idsp Idsn Vout

nMOS Operation
Cutoff
Vgsn < Vtn

Linear
Vgsn > Vtn Vdsn < Vgsn Vtn

Saturated
Vgsn > Vtn Vdsn > Vgsn Vtn

VDD Vin Idsp Idsn Vout

nMOS Operation
Cutoff
Vgsn < Vtn

Linear
Vgsn > Vtn Vdsn < Vgsn Vtn

Saturated
Vgsn > Vtn Vdsn > Vgsn Vtn

Vgsn = Vin Vdsn = Vout

Vin

VDD Idsp Idsn Vout

nMOS Operation
Cutoff
Vgsn < Vtn Vin < Vtn

Linear
Vgsn > Vtn Vin > Vtn Vdsn < Vgsn Vtn Vout < Vin - Vtn

Saturated
Vgsn > Vtn Vin > Vtn Vdsn > Vgsn Vtn Vout > Vin - Vtn
VDD Vin Idsp Idsn Vout

Vgsn = Vin Vdsn = Vout

pMOS Operation
Cutoff
Vgsp >

Linear
Vgsp < Vdsp >

Saturated
Vgsp < Vdsp <

VDD Vin Idsp Idsn Vout

pMOS Operation
Cutoff
Vgsp > Vtp

Linear
Vgsp < Vtp Vdsp > Vgsp Vtp

Saturated
Vgsp < Vtp Vdsp < Vgsp Vtp

VDD Vin Idsp Idsn Vout

pMOS Operation
Cutoff
Vgsp > Vtp

Linear
Vgsp < Vtp Vdsp > Vgsp Vtp

Saturated
Vgsp < Vtp Vdsp < Vgsp Vtp

VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD

Vtp < 0
Vin

Idsp Idsn

Vout

pMOS Operation
Cutoff
Vgsp > Vtp Vin > VDD + Vtp

Linear
Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp Vtp Vout > Vin - Vtp Vtp < 0
Vin

Saturated
Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp Vtp Vout < Vin - Vtp
VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD

Idsp Idsn

Vout

CMOS Inverter Voltage Transfer Characteristic

Vou t 5 NMOS off PMOS lin NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat

NMOS lin PMOS off 5 Vin

3 INPUT CMOS NAND GATE

PULL UP NETWORK A B C PULL DOWN NETWORK

Y=~ABC

Key Points
There is always a path from VDD or GND to the output. There is no path from the VDD to GND (for our purpose). Thus this gate has a very low power consumption. Fully restored logic (why?)

Complex CMOS gates

Design F=ab+bc+ac

Design the complementary logic

Exercises
Design an AND OR Inverter gate:

Tristate Inverter
EN 0 0 1 1 Inp 0 1 0 1 Out Z Z 1 0

What will be the CMOS level circuit for the above?

Tristate Inverter