FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

LAB 07 SEQUENTIAL CIRCUITS

Computers and other digital systems that have memory or that execute a sequence of operations under the direction of stored information are referred to as sequential machines and their circuitry is modeled by sequential logic. Sequential machines do not behave like combinational logic because the outputs of a sequential machine depend on the history of the applied inputs as well as on their present value. The history of the inputs applied to a sequential machine is represented by the state of the machine and requires hardware elements that store information that is! it requires memory to store the state of the machine as an encoded binary word.

Lab Overview
"n this lab you will# $lip flop designs %&$$ '(&$$ T&$$ Sequential machine design using flip flop

Background:
There are two main types of sequential circuits and their classification depends on the timing of their signals. ). * synchronous sequential circuit is a system whose behavior can be defind from the knowledge of its signals at discrete instant of time +. The behavior of an asynchronous sequential circuit depends upon the input signals at any time and the order in which the inputs change.
The storage elements used in clocked sequential circuit are called flip flops. * flip flop is a binary storage device capable of storing one bit of information. The state of a flip flop can change only during a clock pulse transition. ,atches are used to model asynchronous circuits. * latch also holds one bit value but the state of the latch can change with changes in inputs and does not require synchroni-ation with clock pulse. "n this lab we will learn to model different flip flops using .erilog. %&$$! '(&$$ and T&$$ are the common flip flops used in synchronous sequential circuits. $unction table are used to describe different flip flops. %&$$ is the simplest of the flip/flops because its next state is equal to its present state

Table ) % $lip/$lop
D 0 1 Q(t+1) 0 1

VLSI System Design

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

'(&$$ has its next state equal to its present state when inputs ' and ( are both equal to 0. 1hen (2) and '20! the clock resets the flip/flop and 34t5)6 2 0. 1ith '2) and (20! the flip/flops sets and 34t5)6 2). 1hen both ' and k are equal to )! the next state changes to the complement of the present state.

Table + '( $lip/$lop

J 0 0 1 1 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t+1)

T&$$ toggles when the T2) otherwise the state of T&ff does not change.

Table 7 T $lip/$lop
T 0 1 Q(t+1) Q(t) Q(t+1)

Lab Tasks:
). 1rite verilog code for % flip flop and write a test bench to verify the design. +. 1rite verilog code for '( flip flop and write a test bench to verify the design. 7. 1rite verilog code for T flip flop and write a test bench to verify the design. 8. 1rite verilog code for the figure ). 9. 1rite a test bench to verify the design as shown in the table 8.

$igure )
VLSI System Design

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

Table 8 :C% to ;xess/7 code

Decimal Digit 8-4-2-1 code (BCD) 0 1 2 3 4 5 6 7 8 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Excess-3 code

Documentation
Submit the codes along with the wave diagrams for the %! '(! T flip flops and :C% to excess/7 code converter.

VLSI System Design

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

LAB 08 SEQUENTIAL CIRCUITS II

<nlike combinational logic! whose output is an immediate function of only its present inputs! sequential logic depends on the history of its inputs. This dependency is expressed by the concept of state The future behavior of a sequential machine is completely characteri-ed by its input and its present state.

Lab Overview
"n this lab you will learn# State machines State diagrams State machine design in .erilog

Background:
$inite State =achines are used to model Sequential circuits since the states of the sequential circuits change depending upon the inputs at the clock edge. * state diagram is used to describe the sequential behavior of the circuit showing the transition of states according to the inputs. >ere a traffic light controller example is presented to show the .erilog coding of $inite state machine.

Example: Traffic light controller

The following specifications must be considered: 1. The traffic signal for the main highway gets highest priority because cars are continuously present on the main highway. Thus, the main highway signal remains green by default. 2. Occasionally, cars from the country road arrive at the traffic signal. The traffic signal for the country road must turn green only long enough to let the cars on the country road go. 3. As soon as there are no cars on the country road, the country road traffic signal turns yellow and then red and the traffic signal on the main highway turn green again. 4. There is a sensor to detect cars waiting on the country road. The sensor sends a signal X as input to the controller. X = 1 if there are cars on the country road; otherwise, X= 0. The state machine diagram and the state definitions for the traffic signal controller are shown in the following figure

VLSI System Design

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

$igure 9.+ State diagram Table 9.) State and output signals

Lab Tasks:
). 1rite verilog code. +. 1rite a test bench to verify the design

Documentation
Submit the code along with the wave diagrams for the sequence detector

VLSI System Design

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY ISLAMABAD

VLSI System Design