PEDS 2007

Carrier Based Single-state PWM Technique In multilevel Inverter

Nguyen Van NhoI, Quach Thanh Hai2 HochiminhCity University Of Technology Department of Electrical Engineering 268 LyThuongKiet, District 10, Hochiminh City Email: nvnhoghcmut.edu.vn
Abstract- In the paper, a novel analysis of carrier based PWM methods for multilevel inverters is presented. The space vector PWM and carrier based PWM correlations are investigated in a nominal two-level switching diagram. The obtained results will be applied to design various carrier PWM techniques. In this paper, a carrier based single-state PWM technique, which reduces number of switchings and optimizes active voltage errors will be presented. This technique can be advantageous in high level inverters. The carrier base PWM approach shows a flexible offset control. The proposed method is mathematically formulated and demonstrated by simulation and experimental results.

Hong Hee Lee3 University Of Ulsan Department of Electrical Engineering 680-749 San 29, Muger 2-dong, Ulsan, Korea Email: hhleegmail.ulsan.ac.kr

INTRODUCTION Nowadays, for increasing use in practice and fast developing of high power devices and related control techniques, multilevel inverters have become more attractive to researchers and industrial companies. Two common inverter topologies are NPC and cascaded multilevel inverters (Fig. 1 and 2). In recent days, for reducing hardware construction cost, it has been shown a try to develop prospective hybrid multilevel inverters. There are basically three PWM schemes for controlling multilevel inverters as: Carrier based PWM, space vector PWM and selective harmonics elimination PWM methods.
I.

Figure 2: 3-phase Cascaded multilevel inverter

.4y!

4,,

Fig. 1: a) 4-leg 5-level NPC inverter; b) c) and d) Analysis of inverter voltages

The comprehensive correlation between carrier based PWM and SVPWM have been derived in the recent work [1],[2]. Compared to the space vector PWM methods, the carrier based PWM methods can be advantageously utilised in: 1) controlling common mode voltage, 2) controlling of complicated inverter topologies as 4-leg, 5-leg-,... multilevel inverters, 3) compensation of unbalanced dc sources. It will be shown that the carrier PWM technique can become a possible solution for some approximate PWM methods, which use one or two switching states in a switching state sequence and produce reference voltages with certain voltage error. The drawbacks as nonlinear control characteristics and existence of low-order harmonics of output voltages will be compensated by reduced number of switchings in each sampling time period. A common characteristic of carrier based approximate PWM methods is that the offset function can be properly designed to control the PWM performance. Single state space vector PWM method has been described in some recent paper [3], one of its drawback is the limitation of output voltage range. The methods of selecting the voltage vector in Direct torque control and hysteresis current loop control for AC motor drive systems are some typical and well-known applications of single state PWM technique. In the paper, the carrier based single state PWM will be proposed for minimum voltage error. The only controllable parameter ofthis method

1-4244-0645-5/07/$20.002007 IEEE

828

is the offset voltage, which does not influence on the active voltage but able to set approximately common mode voltage and balance switching losses. In the paper, it will be shown that any PWM scheme of multilevel inverter can be centered in a nominal two-level switching state diagram. This makes the PWM study to become more advantageous and comfortable. The proposed method is explained for NPC inverters, its proper modifying can be also applied to cascade topologies.
II. AND CIRCUIT DESCRIPTION NOMINAL SWITCHING DIAGRAM IN MULTILEVEL INVERTER FOR
BALANCE DC VOLTAGE SOURCES

where n(x) = Int(vxref );x

a,b,c.

(7)

Assumption. each dc voltage cell is constant and equal to a unit. Define reference leg voltages between output and dc-neutral point "0", consisting of active voltages vxI2 x - , b, c and reference common mode Voref (Fig.4) as:
Vxref = VxI2 + VOref* Or in the vector form as:
Vref
=

Each components of vector L = [La , Lb L, ] presents possibly a lower level of phase leg voltage in a switching state sequence. Nominal switching time diagram. To investigate commutation process in a triangle period, a vertical shift of coordinates by the vector L = [La Lb Lc ]T can be implemented as shown in Fig.4. Three-phase active PD carrier bands are overlapped. The diagram is redrawn in a nominal two-level switching time diagram as shown in Fig.5. In this nominal diagram, the commutation instants occur depending on the relative voltage level termed nominal modulating signals Sx , x = a, b, c defined as:

4x Or

< 1; < X. Vxref -L(XO;

(8).

(1)

V12 + VOref I

Active voltages, which exist at the three phase load voltages can be determinedfrom the amplitude and phase angle of voltage vector as follows:
Val2
=

Nominal switching states sequence. The nominal two-level switching diagram in Fig.5 shown that switching time digram in multilevel inverters can be explained using that of two-level inverter. Therefore, in nominal switching diagram, let's define nominal switching states as:
4

=Vref -L

Vref COS 6

Ts

0I

Ts

H(a),H(b),H(c)

Vbl2 = Vref cos(6 -2T/3) ;

(2)
V4 v

[2,170,

V3

x1

Lvaref
Ivbrej

= Vref Cos(6 - 4fT/3) Vc=2

Define Max and Min as maximum and minimum values from three phase active voltages as:

[2 1 1]T

Max = Max(val2, Vbl2, VcI2 ) Min = Min(va(l2 Vbl2 , Vcl2 )

(3)

El 0 O]T

[ i,0 2 ,g l tftT
V

veref

K4

a)

SI S2 S3 S4S4 S3 S2 SI

b)

Reference common mode voltage can be proposed of any value, varying within the limits of VOMaX and VOMin: VOMax = (n -1) - Max

Figure 3: a) reference vector in vector triangle, b) Switching time diagrams in multicarrier PWM.
S1

['']

VOMin

-Min
and

(4)

S2

=[S2a ,S2b, S2c ]

=

, S3b, S3c ] s3 = [S3a

(9)

where Vref = [Varef , Vbref ' Vcref

V12 = [Val2 , Vbl2 , Vc12

54
(

[1,,l1]T

Active Lowlor High level. each reference leg voltage Vxref is produced by subsequent alternating between the two lower and higher active levels as L(x) and H(x), for which the following conditions will be satisfied as: 0 < vxref < (n 1) (6) vxrf = (n-1)

H(_)JLn(x) n(x)-1iif
H(X) = L(x) + I

The first and last states as s1 V4 remind two active zero redundant states in switching state sequence of two-level inverter. For the remaining two states as s2; s3, the vector components can be determined from relative positions of nominal modulating signals Xx . Define maximum, medium and minimum values of the three phase nominal modulating signals as:

829

CMax = MaX(;a

c)

XMid
XAhn

Mid (;a b n c )(I 0) =Min (;a n b nc)

can

PROPOSED SINGLE STATE PWM METHOD In single-state PWMtechnique, there is no commutation in a sampling period. The reference vector vief will be modified
III.

The components of vectors s2; s3

S2x{=

be derived as follows:

if

4x

Max

and attain one from 4 relevant vectors defined as (Fig.5b): Vref = Si; j e {1,2,3,4}
[21O]T

S1,

S2 S3 and S4,

(16)
[2 10]T

I
S3x ={

if
else

;x 2 CAhd

(1

V3

Switching state sequence in multilevel inverter can be easily deduced from active low s1, S2, S3, S4 :
voltage
level L and nominal

K
[2
1

switching

states

as

Si

=L+W1
time

(12)
duties.-

[I lfl]T

]T

a)

[010]T

[1gg]T

2 1 I]T

b)

[0,0]

Switching

Reference voltage

vector

can

be

Figure 5: a) Reference vector in single-state switching and function Kmax in a triangle, and b) Principle of single-state PWM method.

described as:

Kref -KS +K2S2 +K3S3 +K4S4 (13) The switching time duties as K1, K2' K3, K4 can be
determined easily from nominal switching diagram as:

Define function KMax

of K14,K2 and K3:

as

the largest from three time duties

Kax = Max(KI4, K2K3)

The value of

(17)

K1 = 1- Max'; K2 Mid; K3
4Max

KMax in a triangle area is described in Fig.5a.

4Mid

4Min; K4

JMin
(14)

In sub-area, where the reference vector

Vref

is located and

K14 =1

max + emin
=

the condition
if

KMax, KK

j e {14,2,3}is satisfied, the

Vref = S1. Particularly,

K1 +K2 +K3 +K4

Conventional PWM techniques attain zero active voltage error. For improving output quality, the offset can be regulated within the range of (voMm,voMAx). An extra adjustment of the offset within the range defined in (15) can be implemented in various modified PWM methods.

KMax

K14, both vectors S1 and S4 have the

and minimizing the offset
error

same

active

error e12 as

eo can be

considered

condition for selecting the vector Vref . For

example, the vector S1 is select if

-K4 < VOadd

|4 Ts

eO

= 4Oadd

< K1
r

(15)

Offset(S

ref ) < Offset(S4

Vref)

(18)

t|

H($H()

Or K2 +2K3+ 3K4 <1- (K2+ 2K3+ 3K4) 3 3

Table 1: Algorithm for single-state PWM method
A

Ki

KL

K2

K2
I:

Conditions K14> K3 K14K14>K *K14 2 K2 +2K3 +3K4 <1.5

K2 >
>

Selected vectors

I\/
4~~~~~~~~~~~A~

K
K3

7~~

~~~~

Mi,

j
d

K3
K4

K1 -= VrefSI

X
s1 s2 s3 AA; ;s s2 s1 b)

2> K14

SI S2 S3 S4S4 S3 S2 SI
a)

L(zL

A?3 >K2;K3>K314
K2+ +2K3 +3K4 >1.5
K14 K2
> K3 K2;K 14> *K4

Vref

Figure 4: a) Switching time diagram deduced in a) new defined coordinates and b) Nominal switching time diagram.

e -= K3 V>ref=S4

V;ref

S2

S3

830

Table 2: Relation between active errors and corresponding selected vectors

1.00.9-

Active voltage error e

Vref

o .8o .7-

2
3

2 K

K2+K3

+K2K3

0.o

o .5-

0.4-

UK, +K K2 +KK,Kl
K +K +K K
2

S2
|

l
l

o .3-

0 .20.1-

3VK22+ff32+ff2ff3
2

~~~S3
S4

0.0ol c

c2

o3

A error

K2+K> K2K3

The corresponding active errors are deduced in Table 2 and drawn in Fig.6.
If reference vector is located at the center of triangle, i.e.

K14 =K2 =K3= 1/3 , active error can achieve a

maximum value of

e12

=2/(3X;3). ax-

(19)

R oi

A c2

c3 o3

IN

error

The influence of offset control is demonstrated by corresponding reference modulating signals for 5-level inverter in Fig.7. There have been calculated reference modulating signals for cases of minimum common mode (Fig.7a, c and e) and medium common mode (Fig.7b, d and f). From the study, single state PWM with minimum common mode offset presents advantageous compared to that of medium common mode for reduced number of extra commutations in a large modulation index range.
IV. OVERMODULATION IN SINGLE-STATE PWM
METHODS

Figure 6: 5-level inverter. Active errors a cl,c2,c3 and "error" in single-state PWM for using corresponding vectors V1V2 V3 3 and Vpruue oposed

The active voltages in single-state carrier overmodulation can be deduced from the principle control between two-limit trajectories [1], for which the active modulating signals corresponding modulating index of m, mA < m < mB can be deduced from the active signals ofthe corresponding limit modulation indexes of m A, mB as:

Because of producing output voltage with nonzero error, the single-state PWM method has a non-linear control characteristic and generates low-order harmonic voltages for the whole modulation range. Compared to conventional PWM methods, overmodulation in single-state PWM method losses its original meaning. However, overmodulation can be supposed to be an approach to extend the reference fundamental voltage Vl)mref to a maximum value in

Vxl2,m

(1

-)Vx12,A + 7vxl2,B
-

Where 7 = (m -mA)/(mB

mA)

six-step mode, i.e., attaining a value of 2 V.That is, the

overmodulation happens if the reference fundamental voltage V1)mref exceeds the value of Vs / | .3

Compared to limit deduced in [3], the carrier based single-state PWM approach can help to get a maximum modulation index up to that of six-step method. Three limit active modulating signals corresponding to modulation indexes of 1,1.055 and 1.1 are proposed (Fig.8). In Fig. 8d, reference modulating signal is deduced for mref =1.03.
V. SIMULATION AND EXPERIMENTAL RESULTS

Diagrams of the phase leg voltage and line-line voltage in five-level inverter for several modulation indexes in underand over-modulation have been calculated and drawn in Fig.9,10 and 11. The voltage quality can be more precisely evaluated through the following diagrams of Fourier

831

analysis of low harmonic components and THD factor as shown in Fig. 12 and Fig. 13. For comparison, corresponding diagrams for 7-level inverter are also included in Fig. 14 and 16. The single-state PWM\ method can be advantageously operated at medium and high modulation index, where harmonic amplitude can be reduced to about 500 to index of 0.45 for 7 level inverter, while this happens around index of
0.8 for 5-level inverter.

32-

val2ref

321-

val2ref

0-1-243-

0-1-2-

Varef

43-

Varef

210-3 10 40

2-

Control characteristics.- The diagrams of nonlinear control characteristics of five- and seven-level inverters are calculated and drawn in Fig. 15 and Fig. 16. A better linearity characteristic is obviously obtained for higher level inverters.

0-

10 5 lo 15 20 25 TIME 30 35

10

16

20 25 TIME

30

35

-3 10 40

321-

Val2ref

a) me

b) -,,,f =1.oss

Experimental results: A harware set - Five-level cascaded inverter has been built to validate the theoretical analysis. The hardware parameters are as following: IGBT IRG45OUD, three-phase load R 20 Q ; each dc source Vdc=35.6Vdc; the measuring osciloscope TDS2012 and Control kit eZdsp TMS320F2812. The diagrams of leg voltage, line-line voltage and its FFT analysis for modulation indexes of 0.4, 0.85 and 1.05 are measured and shown in Fig. 17,18 and 19. These diagrams are similar to the simulated waveforms in Fig.9- 11.

-143210-

0-

Varef

LL
10 15

LL
20 25 TIME 30 35 40

10
d)

C) Me

Me= 1.03

Figure 8: a),b) and c) Diagrams of A-phase active voltage and leg voltage for limit modulation indexes of 1,1.055 and 1.1 with minimum common mode and d) derivation of reference modulating signals for m--1.03.

Figure9:riv-lee inverter Siuato reuls Diarasolevltgan line-line oltage fo m -.4........

Figure 7: 5-level inverter: Diagrams of leg-pole voltage for single-state PWM method with minimum CM offset for a) Mref = 0. 5 , c)

Mre =0.9
M ref

and with medium CM offset for

and e)

and for b)

=0. 5 ,d) mref =0.9

f) overmodulation.

832

ou

Single-Vector PWVM 2 mode minimumCM 5 Ieel

45
40
35

f6M
-1/i

A 3/v

30

-25

201
15

V2vOvfdiv

M5rns

10

5
n

0.2

0.4 m

0.6

., ".,

'I',

X: '. '''''1'
0.8
rI

.,

I,

L-.!.

Figure 12: diagrams

Single-state PWM for 5-level inverter. Harmonic voltage

Single-Vector PWM 2 mode mediumCM 5 level

45
40

V50v/chv

M5ms

35
30

Figure 10: Five-level inverter. Simulation results. Diagrams of leg voltage and line-line voltage for mre,fO.85.

H7I
20 15
10

Figure 13: 5-level inverter. Diagram of voltage THD factor

Single-Vector PWM for 7-level inverter
45

V20vdiv

M5ihs

40

35

30
2 15

20
15

10

62

04

06

0n

GUydiv VIo

M5Ins

Figure 14: 7-level inverter. Single state PWM method: Fourier analysis diagram of harmonic voltage components.

Figure 11: Five-level inverter. Simulation results. Diagrams of leg voltage and line-line voltage for mref-1.05.

833

Mi

12-

Two- state PWM

single- state PV7M

0.41

0.21

0.0
0

0 2

0.4

001

0.8

1.0

1.2

Figure

15:

5-level

inverter.

Diagrams

of

control

characteristics

of and
MD rn

fundamental

voltages

for entire modulation index range in

single-state

two-state PWM methods.

Single-Vector PWM 2

mode mediumoCM 7 level

7Treikk.I

M"5

UQF

4M70

mo1 ninglevectorI
0.

A0A..

18 i6
14

0.

Figure
0

17: Five-level inverter.

Experimental

results.

Diagrams

of leg for

voltage,
0.2 0.4 0.6
1

line-line

voltage

and Fourier

analysis

of line-line

voltage

1.2

mref-O0.4.
rEAL 3Trg`
Pa:

Figure

16:

Single

state

PWM\

method: Control characteristics

00JAt

for 7-level inverter

Tpe
VI.

CONCLUSIONS

Miede
In the paper, the carrier based

single-state
for

PWM\

method for

mm

reducing
been

the

switching

losses

multilevel inverter has

felk lTrV
P0s 200-

Coupling
-2-00V 1HE TRIGGER

proposed. It has been introduced a proper tranformation of switching state diagram of multicarr ier modulation into a nominal switching time diagram. The proposed PWM
method
can

Type

mm
Source

be extended to full

mode. The distribution

can

PWM\

voltage range to six-step performance as switching losses and its

common

=a

be

on switching devices and improved by corresponding

mode

voltage

Slope
PoIlude

selection of

common

mode

voltage.
n0

mm

ummmmum[m
REFERENCES

Coupling

[feI
study
on

[1]

N.V.Nho,
vector

M.J.Youn,"

Comprehensive

Space

PWM and carrier based PWM correlation in multilevel

"

invertors

IE

Proceedings

Electric Power

Applications,
PWM

Vol. 153, No. 1, pp. 149-15 8, Jan. 2006

[2]

N.V.Nho,H.H.Lee,"
2006

Optimised

Discontinuous

for

multilevel inverter with variable load power

factor", PESC

[31

Jose

Silva,"A

and Cesar Rodriguez, Luis Mordin, Pablo Correa Vector Control Technique for Medium-Voltage

Multilevel

Inverters',

WEEE

TRANSACTIONS

ON

Figure

18: Five-level inverter.

Experimental

results.

Diagrams

of

leg
for

INDUSTRIAL 2002

ELECTRONICS, VOL. 49, NO. 4, AUGUST

voltage,

line-line

voltage

and Fourier

analysis

of line-line

voltage

mrefO-.85.

834

Tblk

J.

n
.. B

TflgM
B

M Pos:

200XA

TRIGGR

w~ ~ T pe

* n. aW1 A TgEWW11ig"b IbIL

1 iMbE Pos: 50

TRIGGE

>

> B

~~~~~~~~~~~~~Coupi-in

Vkr
Soroo

am
O EM
FT Z
r

Figure 19: Five-level inverter. Experimental results. Diagrams of leg voltage, line-line voltage and Fourier analysis of line-line voltage for mref 1 0 5

835