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SystemC Tutorial

Author: Silvio Veloso svfn@cin.ufpe.br

Contents
Needed tools Starting example Introduction SystemC highlights Differences Modules, processes, ports, signals, clocks and data types

Needed tools
SystemC library package v2.0.1 Download in www.systemc.org Linux platform GCC compiler GTKWave Waveform tool some text editor

Starting Example:Full Adder


FullAdder.h SC_MODULE( FullAdder ) { sc_in< sc_uint<16> > A; sc_in< sc_uint<16> > B; sc_out< sc_uint<17> > result; void doIt( void ); SC_CTOR( FullAdder ) { SC_METHOD( doIt ); sensitive << A; sensitive << B; } }; void FullAdder::doIt( void ) { sc_int<16> tmp_A, tmp_B; sc_int<17> tmp_R; tmp_A = (sc_int<16>) A.read(); tmp_B = (sc_int<16>) B.read(); tmp_R = tmp_A + tmp_B; result.write( (sc_uint<16>) tmp_R.range(15,0) ); } FullAdder.cpp

Introduction
What is SystemC ?
SystemC is a C++ class library and methodology that can effectively be used to create a cycleaccurate model of a system consisting of software, hardware and their interfaces.

Introduction
Where can I use SystemC ?
In creating an executable specification of the system to be developed.

What should I know to learn SystemC ?


Notions of C++ programming and VHDL helps you a lot.

SystemC highlights
Supports hardware and software co-design Developing an executable specification avoids inconsistency and errors Avoids wrong interpretation of the specification SystemC has a rich set of data types for you to model your systems It allows multiple abstraction levels, from high level design down to cycle-accurate RTL level

Why is SystemC different ?


Current design methodology

Manual conversion creates errors The C model is not more used Many tests are needed to validate

Why is SystemC different ?


SystemC design methodology

Better methodology, translate is not necessary Written in only one language

Modules
Modules are the basic building blocks to partition a design Modules allow to partition complex systems in smaller components Modules hide internal data representation, use interfaces Modules are classes in C++ Modules are similar to entity in VHDL

Modules
SC_MODULE(module_name)
{
// Ports declaration // Signals declaration // Module constructor : SC_CTOR // Process constructors and sensibility list // SC_METHOD // Sub-Modules creation and port mappings // Signals initialization

}
They can contain ports, signals, local data, other modules, processes and constructors.

Modules
Module constructor Similar to architecture in VHDL
Example: Full Adder constructor

SC_CTOR( FullAdder ) { SC_METHOD( doIt ); sensitive << A; sensitive << B; }

Modules
Sub-modules instantiation:
Instantiate module
Module_type Inst_module (label);

Instantiate module as a pointer


Module_type *pInst_module;
// Instantiate at the module constructor SC_CTOR

pInst_module = new module_type (label);

Modules
How to connect sub-modules ?
Named Connection or Positional Connection

Modules
Named Connection
Inst_module.a(s); Inst_module.b(c); Inst_module.q(q); pInst_module -> a(s); pInst_module -> b(c); pInst_module -> q(q);

Modules
Positional Connection

Inst_module << s << c << q; (*pInst_module)(s,c,q);

Modules
Internal Data Storage Local variables: can not be used to connect ports Allowed data types
C++ types SystemC types User defined types

Modules

SC_MODULE( Mux21 ) { sc_in< sc_uint<8> > in1; sc_in< sc_uint<8> > in2; sc_in< bool > selection; sc_out< sc_uint<8> > out;

Example: Mux 2:1

void doIt( void ); SC_CTOR( Mux21 ) { SC_METHOD( doIt ); sensitive << selection; sensitive << in1; sensitive << in2; } };

Modules
Example:
q sample din dout s mult s1 a q coeff cout c b m1

SC_MODULE(filter) { // Sub-modules : components sample *s1; coeff *c1; mult *m1; sc_signal<sc_uint 32> > q, s, c; // Signals // Constructor : architecture SC_CTOR(filter) { // Sub-modules instantiation and mapping s1 = new sample (s1); s1->din(q); // named mapping s1->dout(s); c1 = new coeff(c1); c1->out(c); // named mapping

c1

filter filter

m1 = new mult (m1); (*m1)(s, c, q); // Positional mapping } }

Processes
Processes are functions that are identified to the SystemC kernel. They are called if one signal of the sensitivity list changes its value. Processes implement the funcionality of modules Processes are very similar to a C++ function or method Processes can be Methods, Threads and CThreads

Processes
Methods
When activated, executes and returns - SC_METHOD(process_name)

Threads
Can be suspended and reactivated - wait() -> suspends - one sensitivity list event -> activates - SC_THREAD(process_name)

CThreads
Are activated in the clock pulse - SC_CTHREAD(process_name, clock value);

Processes
Type Activates Exec. Suspends Exec. Infinite Loop suspended/ reactivated by Constructor & Sensibility definition

SC_METHOD Event in sensit. list NO NO N.D.

SC_THREAD Event in sensit. List YES YES wait()

SC_CTHREAD Clock pulse YES YES wait() wait_until()


SC_CTHREAD( call_back, clock.pos() ); SC_CTHREAD( call_back, clock.neg());

SC_METHOD(call_back); sensitive(signals); sensitive_pos(signals); sensitive_neg(signals);

SC_THREAD(call_back); sensitive(signals); sensitive_pos(signals); sensitive_neg(signals);

Processes
Process Example
Into the .H file void doIt( void ); SC_CTOR( Mux21 ) { SC_METHOD( doIt ); sensitive << selection; sensitive << in1; sensitive << in2; } } Into the .CPP file void Mux21::doIt( void ) { sc_uint<8> out_tmp; if( selection.read() ) { out_tmp = in2.read(); } else { out_tmp = in1.read(); } out.write( out_tmp );

Ports and Signals


Ports of a module are the external interfaces that pass information to and from a module In SystemC one port can be IN, OUT or INOUT Signals are used to connect module ports allowing modules to communicate Very similar to ports and signals in VHDL

Ports and Signals


Types of ports and signals:
All natives C/C++ types All SystemC types User defined types

How to declare
IN : sc_in<port_typ> OUT : sc_out<port_type> Bi-Directional : sc_inout<port_type>

Ports and Signals


How to read and write a port ?
Methods read( ); and write( );

Examples:
in_tmp = in.read( ); //reads the port in to in_tmp out.write(out_temp); //writes out_temp in the out port

Clocks
Special object How to create ? sc_clock clock_name ( clock_label, period, duty_ratio, offset, initial_value ); Clock connection f1.clk( clk_signal ); //where f1 is a module Clock example: sc_clock clock1 ("clock1", 20, 0.5, 2, true);

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Data Types
SystemC supports:
C/C++ native types SystemC types

SystemC types
Types for systems modelling 2 values (0,1) 4 values (0,1,Z,X) Arbitrary size integer (Signed/Unsigned) Fixed point types

SystemC types
Type
sc_logic sc_int sc_uint sc_bigint sc_biguint sc_bv sc_lv sc_fixed sc_ufixed sc_fix sc_ufix

Description
Simple bit with 4 values(0/1/X/Z) Signed Integer from 1-64 bits Unsigned Integer from 1-64 bits Arbitrary size signed integer Arbitrary size unsigned integer Arbitrary size 2-values vector Arbitrary size 4-values vector templated signed fixed point templated unsigned fixed point untemplated signed fixed point untemplated unsigned fixed point

SystemC types
Simple bit type Assignment similar to char
my_bit = 1;

Declaration
bool my_bit;
Operators Bitwise Assignment Equality & (and) = == | (or) &= != ^ (xor) |= ~ (not) ^=

SystemC types
SC_LOGIC type More general than bool, 4 values :
(0 (false), 1 (true), X (undefined) , Z(high-impedance) )

Assignment like bool


my_logic = 0; my_logic = Z;

Simulation time bigger than bool Operators like bool Declaration


sc_logic my_logic;

SystemC types
Fixed precision integers Used when arithmetic operations need fixed size arithmetic operands INT can be converted in UINT and vice-versa int in C++
The size depends on the machine Faster in the simulation

1-64 bits integer


sc_int<n> -- signed integer with n-bits sc_uint<n> -- unsigned integer with n-bits

SystemC types
Operators of fixed precision types
Bitwise Arithmetics Assignement Equality Relational Auto-Inc/Dec Bit selection Part select Concatenation ~ + = == < ++ [x] range() (,) & += != <= -ex) mybit = myint[7] ex) myrange = myint.range(7,4) ex) intc = (inta, intb);

| * -= >

^ /

>> %

<< %= &= |= ^=

*= /= > =

SystemC types
Arbitrary precision integers Integer bigger than 64 bits
sc_bigint<n> sc_biguint<n>

More precision, slow simulation Operators like SC_LOGIC Can be used together with:
Integer C++ sc_int, sc_uint

SystemC types
Bit vector
sc_bv<n> 2-value vector (0/1) Not used in arithmetics operations Faster simulation than sc_lv

Logic Vector
sc_lv<n> Vector to the sc_logic type

Assignment operator (=)


my_vector = XZ01 Conversion between vector and integer (int or uint) Assignment between sc_bv and sc_lv Additional Operators Reduction Conversion and_reduction() to_string() or_reduction() xor_reduction()

SystemC types
Examples:
sc_bit y, sc_bv<8> x; y = x[6]; sc_bv<16> x, sc_bv<8> y; y = x.range(0,7); sc_bv<64> databus, sc_logic result; result = databus.or_reduce(); sc_lv<32> bus2; cout << bus = << bus2.to_string();

User defined types


Comparation operator
Operator Built-in == cant be used function inline must be defined for user types
inline bool operator == (const packet_type& rhs) const { return (rhs.info==info && rhs.seq==seq && rhs.retry==retry); }

User defined types


Example
#include "systemc.h" struct packet_type { long info; int seq; int retry; inline bool operator == (const packet_type& rhs) const { return (rhs.info == info && rhs.seq == seq && rhs.retry == retry); } };

#endif

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