74AHC00; 74AHCT00

Quad 2-input NAND gate

Rev. 03 8 January 2008 Product data sheet

1. General description
The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard JESD7-A. The 74AHC00; 74AHCT00 provides the quad 2-input NAND function.

2. Features
I I I I I I Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accepts voltages higher than VCC For 74AHC00 only: operates with CMOS input levels For 74AHCT00 only: operates with TTL input levels ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specied from 40 C to +85 C and from 40 C to +125 C

3. Ordering information
Table 1. Ordering information Package Temperature range 74AHC00D 74AHCT00D 74AHC00PW 74AHCT00PW 74AHC00BQ 74AHCT00BQ 40 C to +125 C 40 C to +125 C TSSOP14 40 C to +125 C Name SO14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 SOT762-1 Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad at package; no leads; 14 terminals; body 2.5 3 0.85 mm

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

4. Functional diagram
1 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2 4 2Y 6 5 9 10 12 13
mna212

&

&

3Y 8

&

8
A

4Y 11

&
mna246

11
B

Y
mna211

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram (one gate)

5. Pinning information
5.1 Pinning
terminal 1 index area 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 1B 1Y 2A 2B 2Y 2 3 4 5 6 7 GND 3Y 8 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A
001aac939

00

11 4Y 10 3B 9 8 3A 3Y

GND (1)

001aac938

Transparent top view

(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.

Fig 4. Pin conguration SO14 and TSSOP14

Fig 5. Pin conguration DHVQFN14

5.2 Pin description

Table 2. Symbol 1A 1B 1Y 2A 2B 2Y GND
74AHC_AHCT00_3

Pin description Pin 1 2 3 4 5 6 7 Description data input data input data output data input data input data output ground (0 V)
NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

1A

00

2 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

Table 2. Symbol 3Y 3A 3B 4Y 4A 4B VCC

Pin description continued Pin 8 9 10 11 12 13 14 Description data output data input data input data output data input data input supply voltage

6. Functional description
Table 3. Input nA L X H
[1]

Function selection[1] Output nB X L H nY H H L

H = HIGH voltage level; L = LOW voltage level; X = dont care

7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation SO14 package TSSOP14 package DHVQFN14 package
[1] [2] [3] [4]

Conditions

Min 0.5 0.5

Max +7.0 +7.0 20 25 75 +150 500 500 500

Unit V V mA mA mA mA mA C mW mW mW

VI < 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V)

[1] [1]

20 75 65

Tamb = 40 C to +125 C
[2] [3] [4]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 8 mW/K above 70 C. Ptot derates linearly with 5.5 mW/K above 60 C. Ptot derates linearly with 4.5 mW/K above 60 C.

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

3 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V Conditions 74AHC00 Min 2.0 0 0 40 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 74AHCT00 Min 4.5 0 0 40 Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V C ns/V ns/V Unit

9. Static characteristics
Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHC00 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VIL LOW-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.5 2.1 3.85 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 0 0 0 3.0 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 2.0 10 1.5 2.1 3.85 1.9 2.9 4.4 2.48 3.8 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 20 10 1.5 2.1 3.85 1.9 2.9 4.4 2.4 3.7 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V V V V A A pF Conditions Min 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max

supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

4 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

Table 6. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter For type 74AHCT00 VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2.0 0.8 2.0 0.8 2.0 0.8 V V Conditions Min 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max

HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V

4.4 3.94 -

4.5 0 -

0.1 0.36 0.1 2.0 1.35

4.4 3.8 -

0.1 0.44 1.0 20 1.5

4.4 3.7 -

0.1 0.55 2.0 40 1.5

V V V V A A mA

VOL

II ICC ICC

supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; supply current VI = VCC 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V input capacitance

CI

3.0

10

10

10

pF

10. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure 7. Symbol Parameter For type 74AHC00 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance
[3] [2]

Conditions Min

25 C Typ[1] Max

40 C to +85 C 40 C to +125 C Unit Min Max Min Max

4.5 6.0 3.2 4.5 7.0

7.9 11.4 5.5 7.5 -

1.0 1.0 1.0 1.0 -

9.5 13.0 6.5 8.5 -

1.0 1.0 1.0 1.0 -

10.0 14.5 7.0 9.5 -

ns ns ns ns pF

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

5 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

Table 7. Dynamic characteristics continued GND = 0 V; For test circuit see Figure 7. Symbol Parameter For type 74AHCT00 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance
[3] [2]

Conditions Min

25 C Typ[1] Max

40 C to +85 C 40 C to +125 C Unit Min Max Min Max

3.3 4.5 7.0

6.9 7.9 -

1.0 1.0 -

8.0 9.0 -

1.0 1.0 -

9.0 10.0 -

ns ns pF

[1] [2] [3]

Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs.

11. Waveforms
VI nA, nB input GND tPLH VOH nY output VOL VM
001aah088

VM

tPHL

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6. The input (nA, nB) to output (nY) propagation delays Table 8. Type 74AHC00 74AHCT00 Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

VI negative pulse 0V

tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM

VI positive pulse 0V

VCC

VCC

PULSE GENERATOR

VI

VO

RL

S1

DUT
RT CL

open

001aad983

Test data is given in Table 9. Denitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.

Fig 7. Load circuit for switching times Table 9. Type 74AHC00 74AHCT00 Test data Input VI VCC 3.0 V tr, tf 3.0 ns 3.0 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

7 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

A X

c y HE v M A

Z 14 8

Q A2 pin 1 index Lp 1 e bp 7 w M L detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 inches 0.069 0.004 0.049

0.019 0.0100 0.35 0.014 0.0075 0.34

0.244 0.039 0.041 0.228 0.016

0.028 0.004 0.012

8 o 0

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 8. Package outline SOT108-1 (SO14)

74AHC_AHCT00_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

8 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

c y HE v M A

14

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

7
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o

Fig 9. Package outline SOT402-1 (TSSOP14)

74AHC_AHCT00_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

9 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm

A A1 E c

terminal 1 index area

detail X

terminal 1 index area e 2 L

e1 b 6 v M C A B w M C y1 C

C y

1 Eh 14

7 e 8

13 Dh 0

9 X 2.5 scale 5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27

Fig 10. Package outline SOT762-1 (DHVQFN14)

74AHC_AHCT00_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

10 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

13. Abbreviations
Table 10. Acronym CMOS LSTTL ESD HBM MM CDM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Low-power Schottky Transistor-Transistor Logic ElectroStatic Discharge Human Body Model Machine Model Charge Device Model Transistor-Transistor Logic

14. Revision history

Table 11. Revision history Release date 20080108 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT00_2 Document ID 74AHC_AHCT00_3 Modications:

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 8: derating values added for DHVQFN14 package. Section 12: outline drawing added for DHVQFN14 package. Product specication Product specication 74AHC_AHCT00_1 -

74AHC_AHCT00_2 74AHC_AHCT00_1

19990923 19981209

74AHC_AHCT00_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

11 of 13

NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

15. Legal information

15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com

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NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74AHC00; 74AHCT00
Quad 2-input NAND gate

17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 January 2008 Document identifier: 74AHC_AHCT00_3