Lab 7 turn in: Please turn in Lab 7 during the first hour or your usual lab session

during finals week

Wed 19
th
12-1pm
Wed 19
th
7-8pm
Thurs 20
th
12-1pm
If you cannot make your usual time, hand it in at one of the other session
time and let the TAs know
During these times all 6 TAs will be there for office hours
My office hours will remain in Finals week email for appointment if you need
to meet at other times
Wk10 Discussion solution are on the class website
Please arrive on time!
Bring cheat-sheet, updated after the quizzes. (V
T
, stability equations, etc , etc)
Hand written or printed ok, 2 sides of 1 sheet of paper.
You can bring the printed AmpSummary sheet (2 pages) in addition to this.
Bring calculator
Look at / do the practice final, go over the quizzes. Go over at least some problems
from all of the Additional Course notes
Use recipes for solving circuits
Quizzes and the practice final are a very good guide (6 questions, 3 hours)
Topics not on the final: Derivation of pn junction current from semi-conductor physics
Multi-stage amplifier circuits
Suggestions for the final Thursday 20
th
March 7-10pm, Ctr Hall 101
ECE65 Course Summary
ECE 65, Winter2014, S. Bott-Suzuki
Devices
Diode iv characteristics equation
I
S
: Reverse Saturation Current
(10
-9
to 10
-18
A)
V
T
: Volt-equivalent temperature
(= 26 mV at roomtemperature)
n: Emission coefficient
(1 n 2 for Si ICs)
For |v
D
| 3nV
T
= I (e
v
D
/ nV
T
1)
D S
i
Reversebias: i
D
I
S
Sensitive to temperature:
I
S
doubles for every 7
o
C increase
V
T
= T(k) /11,600
Forwardbias: i
D
I
S
e
v
D
/nV
T
Diode piecewise-linear model:
Diode iv is approximated by two lines
Constant Voltage Model
"cut- in"voltage, V
D0
= 0.6 0.7V for Si
OFF:
and i
D
0
and v
D
<V
D0
v
D
= V
D0
i
D
= 0
DiodeON:
DiodeOFF:
Circuit Models:
ON:
Diode ON
Diode OFF
V
D0
Zener Diode piecewise-linear model
and i
D
0
and V
Z
< v
D
<V
D0
and i
D
0
DiodeON:
DiodeOFF:
Zener:
v
D
= V
D0
i
D
= 0
v
D
= V
Z
Diode ON
Diode OFF
V
D0
Zener
Circuit Models:
ON:
OFF:
Zener:
Recipe for solving diode circuits
Recipe:
1. Drawa circuit for each state of diode(s).
2. Solve each circuit with its corresponding diode equation.
3. Use the inequality for that diode state (range of validity) to
check:
o if the solution is valid if circuit parameters are all known.
o to find the range of circuit variable which leads to that
state.
Accuracy of Constant-Voltage Model
Constant Voltage
Model
Diode ON
Diode OFF
V
D0
Diode can be in forward bias with v
D
as
small as 0.4 V when i
D
is small (Lab 4)
In forward bias, cut-in voltage (V
D0
)
can vary between 0.6 & 0.8 V ( 0.1 V)
In forward bias, diode voltage changes
slightly as current changes
BJT iv characteristics includes four parameters
BC is reverse biased
(Deep) Saturation:
CE
| + =
v /V
NPN transistor
i
B
= e
Two transistor parameters can be
written in terms of the other four:
KCL : i
E
= i
C
+ i
B
KVL : v
BC
= v
BE
v
CE
BJT iv characteristics equations are:
i
B
= f (v
BE
)
i
C
= g (i
B
,v
CE
)
Cut-off :
i = 0, i = 0
BE is reverse biased
B C
i =
i
C
=
I
S
e
v
BE
/V
T
Active:
B

BE is forward biased
| v |
i I e
BE T
1
C S
\
V
A .
I
S
v /V
BE T
BE is forward biased

BC is foward biased
v
CE
V
sat
, i
C
< i
B
Arrow on the
emitter
Transistor operates like a valve:
i
C
& v
CE
are controlled by i
B
Controller part:
Circuit connected to BE sets i
B
Controlled part:
i
C
& v
CE
are set by
transistor state (&
outside circuit)
BJT Linear Model
Cut-off
Active

(i
B
= 0, v
BE
< V
D0
):
(i
B
> 0, v
BE
= V
D0
):
Valve Closed i
C
= 0,
Valve partially open i
C
= i
B,
v
CE
> V
D0
Saturation (i
B
> 0 , v
BE
= V
D0
): Valve open i
C
< i
B,
v
CE
= V
sat
For PNP transistor, replace v
BE
with v
EB
and replace v
CE
with v
EC
in the above.
ForSi, V
D0
= 0.7 V, V
sat
= 0.2 V
* BJT Linear model is based on a diode constant-voltage
model for the BE junction and ignores Early effect.
Recipe for solving BJT circuits
(State of BJT is unknown before solving the circuit)
1. Write down BE-KVL and CE-KVL (check for NPN/PNP!):
2. Assume BJT is OFF, Use BE-KVL to check:
a. BJT OFF: Set i
C
= 0, use CE-KVL to find v
CE
(Done!)
b. BJT ON: Compute i
B
3. Assume BJT in active. Set i
C
= i
B
. Use CE-KVL to find v
CE
.
If v
CE
V
D0
, Assumption Correct, otherwise in saturation:
4. BJT in Saturation. Set v
CE
= V
sat
. Use CE-KVL to find i
C
.
(Double-check i
C
< i
B
)
NOTE:
o For circuits with R
E
, both BE-KVL & CE-KVL have to be solved
simultaneously.
MOS i-v Characteristics Equations
NMOS (V
OV
= v
GS
V
tn
)
o For PMOS set V
OV
= v
SG
|V
tp
| & replace v
DS
with v
SD
in the above
i = 0.5 C
W
|2V v v
2
|
|1+ v
DS
| V
OV
0 andv
DS
V
OV
i
D
= 0.5
n
C
ox
V
OV
DS OV DS D n ox OV
V
OV
0 andv
DS
V
i
D
= 0 V
OV
L
W
L
0
Saturation:
Triode:
Cut-Off :
2
NMOS PMOS
Arrow on the
source
MOS operation is Conceptually similar to a
BJT -- i
D
& v
DS
are controlled by v
GS
Controller part:
Circuit connected to GS
sets v
GS
(or V
OV
)
Controlled part:
i
D
& v
DS
are set by
transistor state (&
outside circuit)
A similar solution method to BJT:
o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve
with the corresponding MOS equation and validate the assumption.
MOS circuits are simpler to solve because i
G
= 0 !
o However, we get a quadratic equation to solve if MOS in triode (check MOS in
saturation first!)
Foundation of Transistor Amplifiers
MOS is always in saturation (BJT in active)
Input to transistor is made of a constant
bias part (V
GS
) and a signal (v
gs
):
v
GS
= V
GS
+ v
gs
Response (v
o
= v
DS
) is also made of a
constant part (V
DS
) and a signal response
part (v
ds
): v
DS
= V
DS
+ v
ds
V
DS
, is ONLY related to V
GS
:
o i.e., if v
gs
= 0, then v
ds
= 0
The response to the signal is linear, i.e.,
v
ds
/ v
gs
= const. But
o
o
v
GS
/ v
DS
V
GS
/ V
DS
is NOT a constant!
is NOT a constant!
Issues in developing a transistor amplifier:
1. Find the iv characteristics of the elements for the signal (which
can be different than their characteristics equation for bias).
o This will lead to different circuit configurations for bias versus signal
2. Compute circuit response to the signal
o Focus on fundamental transistor amplifier configurations
3. How to establish a Bias point (bias is the state of the system
when there is no signal).
o Stable and robust bias point should be resilient to variations in

n
C
ox
(W/L),V
t
(or for BJT) due to temperature and/or
manufacturing variability.
o Bias point details impact small signal response (e.g., gain of the
amplifier).
Summary of signal circuit elements
i
d
r = nV /I
d T D
Diode Small Signal Model
v
D
v
d
i
D
Resistors& capacitors:
o Capacitor act as open circuit in the bias circuit.
The Same
Independent voltage source (e.g., V
DD
) : Effectively grounded
Independent current source: Effectively open circuit
Dependent sources: The Same
Non-linear Elements:
o Diodes & transistors ?
Different!
Transistor Small Signal Models
1
=
2 I
D
D
r
o

OV
m
I V
g
Comparison of MOS and BJT small-signal circuit models:
1. MOS has an infinite resistor in the input (v
gs
) while BJT has a finite resistor, r

(typically several k).

2. BJT g
m
is substantially larger than that of a MOS (BJT has a much higher gain).
3. r
o
values are typically similar (10s of k). g
m
r
o
>> 1 for both.
NMOS/PMOS
C
r
V
A
o
T
g =
I
C
=

m
B
=
V
T
I V r I
r

NPN/PNP BJT
V
T
= 26 mV at room temperature
Transistor Biasing
To make bias point independent of changes in transistor
parameters (e.g. ,) the bias circuit should set I
C
and NOT I
B
!
Emitter Degeneration (BJT):
Requires a resistor in the emitter circuit.
Requirements:
1. R
B
<< (
min
+1)R
E
2. I
E
R
E
1V
Source Degeneration (MOS):
Requires a resistor in the source circuit.
Requirement:
1. R
S
I
D
>V
GS
Current source:
Emitter-degeneration bias circuits
Basic Arrangement Bias with one power supply
(voltage divider)
Bias with two power supplies
MOS source-degeneration bias circuits are identical
To solve circuits with voltage divider bias:
1. BJT: replace voltage divider with its Thevenin equivalent.
2. MOS: Since i
G
= 0, calculate V
G
directly.
BJT Current Mirrors are based on two identical
transistor with v
BE,ref
= v
BE1
Identical BJTs Q
ref
is always in active since
Identical BJTs and v
BE,ref
= v
BE1
o BJTs will have the same i
B
and the
same i
C
(ignoring Early effect)
=V
D0
V
CE,ref
=V
BE,ref
i
C,ref
>0

+2i =i +2
i
C
B C C,ref ref
KCL: I =i
I
1
=i
C
= I
ref
1+2/
I
ref
Since I
1
= const. regardless of
V
C1
, this is a current source!
For the current mirror to work, Q1
should be in active:
V
CE1
=V
C1
+V
EE
V
D0
MOS Current-Steering Circuit are based on two
identical transistor with v
ov,ref
= v
ov1
Q
ref
is always in saturation since

V
DS,ref
=V
GS,ref
>V
GS,ref
V
GS,ref
=V
GS1
=V
GS
V
OV,ref
=V
OV1
=V
OV
V
t
I =i =0.5C (W/L) V
2
1 D1 n ox 1 OV
V
2
I
ref
=i
D,ref
(W/L) =0.5C
ref OV n ox
I
1
=
(W/L)
1
(W/L)
ref
I
ref
Identical MOS:
Same C
ox
and V
t
Since I = const. regardless of
1
V
D1
, this is a current source!
For the current steering circuit to
work, Q1 should be in saturation:
V
DS1
>V
OV
=V
GS
V
t
How to add signal to the bias
Bias & Signal
v
GS
= V
GS
+ v
gs
Bias & Signal
v
DS
= V
DS
+ v
ds
1. Direct Coupling
Use bias with 2 voltage supplies
o For the first stage, bias such that
V
GS
= 0
o For follow-up stages, match bias
voltages between stages
Difficult biasing problem
Used in ICs
Amplifies DC signals!
2. Capacitive Coupling
Use a capacitor to separate bias
voltage fromthe signal.
Simplified biasing problem.
Used in discrete circuits
Only amplifies AC signals
Discrete CE and CS Amplifiers
R
i
= R
G
R
o
= R
D
||r
o
= g
m
(r
o
|| R
D
||R
L
)
v
o
v
i
v
i
R
i

v
o
v
sig
R
i
+R
sig
v
o
=
R
i
= R
B
|| r

R
o
= R
C
||r
o
r

= g
m
(r
o
||R
C
||R
L
)
v
o
v
i
BJT
MOS
v
i
at base, v
o
at collector
Discrete CE and CS Amplifiers with R
E
/ R
S
R
i
= R
G
R
o
= R
D
|||r
o
(1+g
m
R
S
)|
v
o
v
i
1+ g
m
R
S
+ (R
D
||R
L
)/ r
o
g
m
(R
D
|| R
L
)
=
r

+ R
E
+ R
B
||R
sig
.
(

|
(
|
(

R
o
= R
C
||r
o

1+

|
\
|
(
1+[(R
C
||R
L
)/ r
o
]

(
R = R ||

r + R +

v
o
v
i
1+ g
m
R
E
+[(R
C
||R
L
)/ r
o
](1+ R
E
/ r

)
=
E
E
i B E
g
m
(R
C
||R
L
)
R
R
v
o
R
i

v
o
=
v
sig
R
i
+R
sig
v
i
BJT
MOS
v
i
at base, v
o
at collector
Discrete CB and CG Amplifiers
R = R ||{r [1+g (r ||R ||R )] }
1+ g
m
r
o
r
o
+ (R
C
||R
L
)(
R
i
= R
E
||r

||
= +g
m
(r
o
|| R
C
|| R
L
)
sig E o C o m
v
o
v
i
(

R = R ||{r [1+g (R ||R )] }

1+ g
m
r
o
r + (R ||R )(
||
o D L
= +g
m
(r
o
|| R
D
||R
L
)
m S sig o D o
S i
v
o
v
i
R = R
(

r

v
o
R
i

v
o
=
v
sig
R
i
+R
sig
v
i
BJT
MOS
v
i
at emitter, v
o
at collector
Discrete CC and CD Amplifiers
R = R ||
1
v
i
1+ g
m
(r
o
||R
S
||R
L
)
R
i
= R
G
v
o
g
m
(r
o
||R
S
||R
L
)
g
m
o S
=
v
i
1+ g
m
(r
o
||R
E
||R
L
)
R
i
= R
B
|||r

+ (r
o
||R
E
||R
L
)|
||r
o
r

+ R
B
||R
sig
R
o
R
E
||
v
o
g
m
(r
o
||R
E
||R
L
)

=
v
o
R
i

v
o
=
v
sig
R
i
+R
sig
v
i
BJT
MOS
v
i
at base, v
o
at emitter
Gain of a multi-stage amplifier
Example: A 3-stage amplifier
v
i,1
v
o,1
v
o,2
v v v v
=
o,3
=
o,1

o,2

o,3
v
i,1
v
i,1
v
o
A ...
v3
A
v1
A
v2
v R +R
=
sig sig i
R
i
v
o
But we need to know R
L,1
, R
L,2
,
R
L,3
, in order to find A
M
s.
v
o,1
= v
i,2
v
o,2
= v
i,3
v
o
= v
o,3 i i,1
i,1 sig
R
i,1
v
=
i,1
, R =R
sig sig
v
i
R +R v v
=
R
o
= R
o,3
= A A
v2
A
v3 v1
i,3
o,1

o,2

o,3
i,2 i,1 i,1
o
=
v v
v
v v
v v
v
v
o1
= v
i 2
v
o2
= v
i3
What are R
L
and R
sig
for each stage?
Amp Model for Stage j-1
R
sig, j
= R
o, j 1
R
L, j
= R
i, j +1
R
L
for each stage is the input resistance of the following stage.
R
sig
for each stage is the output resistance of the previous stage.
Amp Model for Stage j+1
Procedure for Solving multi-stage
Amplifiers
Gain & R
i
:
1. Start fromthe load side (n
th
stage),
o Find the gain A
v,n
= (v
o
/v
i
)
n
and R
i,n
.
2. For (n-1)
th
stage, set R
L,n-1
= R
i,n
o Find the gain A
v,n-1
= (v
o
/v
i
)
n-1
and R
i ,n-1
.
3. Repeat until reaching to the first stage. Then,
R
o
:
1. Start fromthe source side (1
st
stage). Find R
o,1
.
2. Go to the second stage. Set R
sig,2
= R
o,1
. Find R
o,2
3. Continue to the last stage (n
th
stage). Then, R
o
= R
o,n
A
v1
A
v2
A
v3
...
R
i
=R
i,1
=
v R +R
sig i
v
o
R
i
sig
Cut-off frequency of a capacitively coupled
amplifier
Similar to a single-stage amplifier, each
capacitor introduces a pole:
1) Coupling capacitor at the input:
2) Coupling capacitor at the output:
3) Coupling capacitor between stages j-1 and j
4) By-pass capacitors for stage j (if exists)
5) Then:
i sig c1
f
p1
=
2(R +R )C
1
by pass by pass
f
p,bypass
=
2 R
C
1
o L co
f
po
=
2(R +R )C
1
i, j o, j 1 cj
f
pj
=
2(R +R )C
1
f
p
f
p1
+ f
p2
+...
Diode Functional Circuits
Rectifier & Clipper Circuits
Half-wave rectifier
(DiodeON)
(DiodeOFF)
For v
i
V
D0
, v
o
= v
i
V
D0
For v
i
< V
D0
, v
o
= 0
Clipper
(DiodeON)
(DiodeOFF)
For v
i
V
D0
, v
o
= V
D0
For v
i
< V
D0
, v
o
= v
i
Clipping voltage can be adjusted
v
o
limited to V
D0
+ V
DC
v
o
limited to V
D0
+ V
Z
v
o
limited to V
D0
V
DC
v
o
limited V
D0
V
Z
Both top & bottom portions of the signal
can be clipped simultaneously
v
o
limited to V
D0
+ V
DC1
and V
D0
V
DC2
v
o
limited to V
D0
+ V
Z1
and V
D0
V
Z2
Clamp Circuit
Peak Detector & Clamp Circuits
ideal peak detector: /T
Good peak detector: /T >> 1
v
o
is equal to v
i
but shifted
downward by (V
+
V
D0
)
Peak Detector Circuit
v
o
shifted downward
Voltage shift in a clamp circuit can be adjusted!
V
Z
V
D0
) v
o
= v
i
(V
+
v
o
= v
i
(V V
DC
V
D0
)
+
v
o
shifted upward
v
o
= v
i
+ (V V
Z
V
D0
)

v
o
= v
i
+ (V V
DC
V
D0
)

BJT as a switch
Use: Logic gate can turn loads ON (BJT in saturation) or OFF
(BJT in cut-off)
i
c
is uniquely set by CE circuit (as v
ce
= V
sat
)
R
B
is chosen such that BJT is in deep saturation with a wide
margin (e.g., i
B
= 0.2 i
c
/)
*Lab 4 circuit
Load is placed in
collector circuit
Solved in Lecture notes (problems 12 & 13)
BJT as a Digital Gate
Other variants: Diode-transistor logic (DTL) and transistor-transistor logic (TTL)
BJT logic gates are not used anymore except for high-speed emitter-coupled
logic circuits because of
o Low speed (switching to saturation is quite slow).
o Large space and power requirements on ICs
RTL NOT gate (V
L
= V
sat
, V
H
= V
CC
)
Resistor-Transistor logic (RTL)
RTL NOR gate* RTL NAND gate*
*Solved in Lecture notes (problems 14 & 15)
NMOS Functional circuits
Similar to a BJTs in the active mode,
NMOS behaves rather linearly in
the saturation region
Transition fromcut-off to triode can
be used to build NMOS switch
circuits.
o Voltage at point C (see graph)
depends on NMOS parameters and
the circuit (in BJT v
o
= V
sat
)!
We can also built NMOS logic gate
similar to a RTL. But there is are
much better gates based on CMOS
technology!
Complementary MOS (CMOS) is based on
NMOS/PMOS pairs
Maximumsignal swing: Low State: 0, High State: V
DD
o Independent of MOS device parameters!
Zero static power dissipation (i
D
= 0 in each state).
o It uses the fact that if a MOS is ON and i
D
= 0
only if MOS is in triode and v
DS
= 0
CMOS Inverter
CMOS NAND Gate
How to Solve Problems
1. What is Known?
(comes from problem
description.)
2. What is the aim?
(Identify circuit
parameters that have
to be calculated.)
3. How to get there?
(use recipes!)
First, write down all equations that govern the
circuit.
Make sure that you have enough equations to
solve for the unknowns.
Make sure that your solutions will give you the
answer to the problem.
Only then, start solving the equations.