Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
) )( )( ( G E A G F E D C B A + + + + + + +
48
Boolean Expression from Truth Table
For SOP (sum of products) and POS (product of
sums) canonical expressions, the corresponding
circuit implementation is always a two-level gate
network
=> input signals pass through maximum of 2
gates (excluding input variable inversions)
49
Boolean Expression from Truth Table
'SUM-OF-PRODUCTS' NETWORKS
'AND OR' gate 2-level system
D
E
F
A
B
C
ABC
DEF
ABC+DEF
50
Boolean Expression from Truth Table
or using only NAND gates, we get
A
B
D
C
E
F
ABC +DEF
ABC
DEF
51
Boolean Expression from Truth Table
'PRODUCT-OF-SUMS' NETWORKS
'OR AND' gate 2-level system
52
Boolean Expression from Truth Table
using only NOR gates,
A
B
D
C
E
F
(A+B+C)(D+E+F)
A+B+C
D+E+F
53
Simplification of Boolean expression
More than 1 Boolean expression can be derived for a
given combinational logic problem
Redundancies may exist
Example:
54
Simplification of Boolean expression
Simpler circuit with the same logic
55
Simplification of Boolean expression
Example : Consider
ABC BC A C B A C AB Z + + + =
Redundant in B and C
C A AB Z + =
X X and
X X
=
= +
1 .
1
) ( ) ( B B C A C C AB Z + + + =
56
Simplification using Boolean Algebra
Example:
XZ
Z X X
Z X X X
Z X XY Y X X
Z X Y Y XY Y X XX Z X Y X Y X
=
+ =
+ + =
+ + + + =
+ + + + = + + +
) (
) ))( 1 ( (
) )( 0 (
) )( ( ) )( )( (
57
Simplification using Boolean Algebra
Using Boolean Algebra approach sometimes
lead to a blind alley, e.g.
C A C B A B
C A C A B
C A C A A B
C AB C A B A
C AB C B A
C AB C B B A
C AB B A C B A
C AB C C B A C B A
C AB BC A C B A C B A Z
+ + =
+ + =
+ + =
+ + =
+ + =
+ + =
+ + =
+ + + =
+ + + =
) (
) (
12) (rule ) (
) (
) (
No further reduction appears possible!
58
Simplification using Boolean Algebra
If we know there are 2 redundancies B and A,
C B C A
C AB BC A C B A C B A Z
+ =
+ + + =
59
Simplification using Karnaugh Map
Systematic technique to obtain the minimal
form (suggested by Maurice Karnaugh)
Graphical approach consists of array of
squares
Based on:
Assume expression is in SOP form
1 = + A A
Maurice Karnaugh
(1924- )
60
Simplification using Karnaugh Map
Three variables map (8 squares/cells)
C B A
C B A
C AB
C B A
C B A
BC A ABC C B A
B A B A AB
B A
C
C
Remark: Only one variable changes between
two adjacent cells or squares
61
Simplification using Karnaugh Map
Another way to label the map
C B A
C B A C AB
C B A
C B A
BC A
ABC
C B A
00
AB
0
C
1
01 11 10
From SOP expression, 1 is input to map for
each of its term
62
Simplification using Karnaugh Map
Example : Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
Z ABC ABC ABC ABC = + + +
63
Simplification using Karnaugh Map
Example (cont): Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
Z AC = +
Z ABC ABC ABC ABC = + + +
64
Simplification using Karnaugh Map
Example (cont): Two-cell groups (redundant of one
variable)
1
1 1 1
00
AB
0
C
1
01
11 10
AB
+
Z ABC ABC ABC ABC = + + +
Z AC =
65
Simplification using Karnaugh Map
Example : Four-cell groups (redundant of two variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
Z ABC ABC ABC ABC ABC ABC = + + + + +
66
Simplification using Karnaugh Map
Example (cont) : Four-cell groups (redundant of two
variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
Z C =
+
Z ABC ABC ABC ABC ABC ABC = + + + + +
67
Simplification using Karnaugh Map
Example (cont): Four-cell groups (redundant of two
variables)
1 1 1 1
1 1
00
AB
0
C
1
01 11 10
A + Z C =
Z ABC ABC ABC ABC ABC ABC = + + + + +
68
Simplification using Karnaugh Map
Example : Four-cell groups (redundant of two variables)
1 1
1 1
00
AB
0
C
1
01 11 10
Z B =
Z ABC ABC ABC ABC = + + +
69
Simplification using Karnaugh Map
Example :
1
1 1 1
00
AB
0
C
1
01 11 10
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
70
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
+
71
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
AB
+
+
72
Simplification using Karnaugh Map
Example (cont):
1
1 1 1
00
AB
0
C
1
01 11 10
BC
( ) ( ) ( )
( ) 1 1 1
0 1 1 1 0 1 1 1 0
C
C C C F
B A
+ B A + B A + B A =
AC
AB
+
+
73
Simplification using Karnaugh Map
Example :
1 1
1 1
00
AB
0
C
1
01
11 10
Z ABC ABC ABC ABC = + + +
74
Simplification using Karnaugh Map
Example (cont):
1 1
1 1
00
AB
0
C
1
01
11 10
C A
+
Z ABC ABC ABC ABC = + + +
75
Simplification using Karnaugh Map
Example (cont):
1 1
1 1
00
AB
0
C
1
01
11 10
C A C B
+
Z ABC ABC ABC ABC = + + +
76
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
77
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
78
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
+
Z=
79
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
A
+
+
Z=
80
Simplification using Karnaugh Map
Example :
Z A B B = C + +ABC + C
C
A
B
+
+
Z=
86
Simplification using Karnaugh Map
Four variables map (16 Squares)
D C B A
D C B A D C AB
D C B A
D C B A
ABCD
B A B A
AB
B A
D C
D C
CD
D C
D C B A D C AB D C B A
BCD A
CD B A
CD B A
D C B A D BC A
D ABC D C B A
87
Simplification using Karnaugh Map
Four variables map
D C B A D C B A D C AB
D C B A
D C B A
ABCD
AB
CD
D C B A D C AB D C B A
BCD A
CD B A
CD B A
D C B A D BC A
D ABC D C B A
00
01 11 10
00
01
11
10
88
Simplification using Karnaugh Map
Group of 2 (1 redundant variable)
89
Simplification using Karnaugh Map
Group of 2 (1 redundant variable)
90
Simplification using Karnaugh Map
Group of 4 (2 redundant variables)
91
Simplification using Karnaugh Map
Group of 4 (2 redundant variables)
92
Simplification using Karnaugh Map
Group of 8 (3 redundant variables)
93
Simplification using Karnaugh Map
Group of 8 (3 redundant variables)
94
Simplification using Karnaugh Map
Example :
F ABCD ABCD ABCD ABCD = + + +
( ) ( ) ( ) ( ) 1100 1110 0001 1001
= + F ABD BCD imal form (min )
95
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
96
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
1 = C B A
Set:
1
97
Simplification using Karnaugh Map
Dont Care States
Example:
A B C Z
0 0 0 1
0 0 1 X
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 0
AB
C 0 1
00
01
11
10
0
X
X
0
0
1
1 1
1 = C B A
Set:
minimal expression
=
B
1
101
Procedure for Combinatorial Logic
implementation
Procedure:
Obtain truth table for problem
Obtain Boolean expression from truth table
Minimization of Boolean expression (by
Boolean algebra or Karnaugh map)
Circuit implementation
102
Procedure for Combinatorial Logic
implementation
EXAMPLE
The 4Ks company comprises four partners, P1, P2, P3 and
P4 who own 35%, 30%, 15%and 20%of the business,
respectively.
Company decisions are made by voting and a total vote of at
least 70% of the ownership is required to pass a motion.
Each partner has a 2-position switch which must be
switched ON to vote YES.
A lamp will light up if the total voted is YES.
Draw up a truth table for the voting scheme and design
combinational logic circuit for the scheme.
Input
Output
103
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
104
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
105
Procedure for Combinatorial Logic
implementation
P1
35%
A
P2
30%
B
P3
20%
C
P4
15%
D
Total
Vote
%
Lamp
L
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
15
20
35
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
30
45
50
65
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
35
50
55
70
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
65
80
85
100
0
1
1
1
Example (cont)
Solution:
PARTNER'S
SWITCHES A, B, C, D :
ON = 1 (YES)
OFF = 0 (NO)
LAMP L:
ON=1 (YES)
OFF=0 (NO)
106
Procedure for Combinatorial Logic
implementation
Example (cont):
1
1 1
1
AB
CD
00
01 11 10
00
01
11
10
L ABD ACD ABC = + +
CD B A D ABC ABCD D C AB L + + + =
Minimalization of Boolean Expression
107
Procedure for Combinatorial Logic
implementation
Example (cont):
Circuit implementation:
L ABD ACD ABC = + +
A B C D
ABD
ACD
ABC
L
108
Procedure for Combinatorial Logic
implementation
NAND and NOR gates are universal
building blocks
To implement logic circuit using only
NAND or NOR gates.
DeMorgans theoremis used to convert
expression convenient for
implementation
109
Procedure for Combinatorial Logic
implementation
Example
Implement Boolean expression
using only NAND gates.
AD AB Z + =
AD AB
AD AB Z
- =
+ =
Solution:
Using De Morgans theorem,
so that desired circuit is
A
B
D
Z
AB
AD
TTL and CMOS Integrated Circuits
TTL (Transistor-Transistor Logic) (based on BJ T
technology):
Digital Input:
Logic zero (0) or low (L): less than 0.8V
Logic one (1) or high (H): greater than 2.0V
Voltage range 0.8V to 2.0V is a dead zone where the input
state is undefined.
Digital output: ranges between 0 and 0.5V for low and
between 2.7V and 5V for high.
110
TTL and CMOS Integrated Circuits
CMOS (Complementary Metal Oxide
Semiconductor) (based on FET technology):
The logic levels depend on the supply voltage.
Very little power consumption, but susceptibility to
damage from static electricity.
111
TTL and CMOS input and
output levels (assume that
both devices are powered
by a 5 V DC supply)
Manufacturer IC Data Sheets
Labeling System of TTL IC - AAxxyzz
AA: manufacturers prefix (SN: TI and others; DM:
National Semiconductor)
xx: military (xx=54) and industrial (xx=74) quality
y: different internal designs (no letter: standard TTL; L:
low power dissipation; H: high power dissipation; S:
Schottky type; AS: advanced Schottky; LS: low power
Schottky; ALS: advanced low power Schottky)
(Schottky devices have faster switching speeds and
require less power.)
zz: sequence number in data book (For example,
DM74ALS00 (QUAD NAND))
112
Digital IC Output Configurations
Open collector output type TTL devices (e.g., 7401,
7403, 7405, 7406)
Normally, a pull-up resistor is added to the output.
114
117
The Data Sheets for 5400 and 7400 NAND
gate IC
118
The Data Sheets for 5400 and 7400 NAND
gate IC
119
The Data Sheets for 5400 and 7400 NAND
gate IC