3.4.

Output Capacitor
The output capacitance stores energy through its electrical field. The capacitance

size also determines the voltage overshoot and ripple tolerances at the converter output. Overshoot and Ripple Figure 3.13 shows the capacitor charging and discharging during one switching clock period. The average inductor current flows through the load impedance while the inductor current ripple flows through the capacitor. As a result, the capacitor effectively has zero average current. Ideally the output capacitor voltage is given by: Vc,max = Vout + Vout 2

Where V is the voltage ripple. The worst-case peak-to-peak output voltage ripple is: Vout = During the off duration, T Ton : IL = Substituting IL into Vout yields: Vout = T Vout (1 D) T 8C L Vout L (1 D) T Q 1 1 IL T = C C2 2 2

It is convenient to express the output voltage ripple as: Vout 1 T 2 (1 D) 2 = = (1 D) 8 LC 2 Vout fc fsw
2

(3.12)

Where fc =

1 2 LC

. There are several ways to minimize the output voltage overshoot and

ripple content[9]: Choose a sufficiently large capacitor. Choose a sufficiently high switching frequency. Choose a capacitor with a low effective series resistance (ESR) and inductance. Capacitors can be placed in parallel in order to reduce the ESR. Choose a sufficiently large inductor to minimize current ripple.

Figure 3.13: Inductor current and capacitor voltage waveforms.

Capacitor Rating The capacitor should have sufficient voltage rating to support the maximum output voltage. The maximum capacitor RMS current is given by: Iout IC rms,max = 3

Using the definition of RMS voltage a conservative estimate for the capacitor RMS voltage rating is: Vc,max = 1.5Vout (3.13)

3.4.3

Switch Rating
Figure 3.14 shows the switch current waveform. The switch conducts inductor

current when it closes and zero current when it opens. Non-ideal MOSFET transistors with fast switching times are desirable with a voltage rating sufficient to withstand the oscillatory ringing transients (voltage spikes) that occur. A conservative estimate for the voltage rating is twice the input, 2Vin . Since the current through the high-side PMOS switch is almost identical to the current through the inductor for large duty cycles, the MOSFET RMS current rating equals the inductor RMS current rating given by Equation

3.4.4

Flywheel Rating
As with the switch, the flywheel device also suffers from oscillatory ringing tran-

sients. A conservative voltage rating for a MOSFET or Schottky diode is twice the input, 2Vin . Figure 3.15 shows the diode current waveform. It is clear from the Figure that the diode current equals the inductor current when the switch opens. A conservative estimate

of the RMS current rating for the diode (assuming a small duty cycle) is the same as the RMS current rating for the inductor given by Equation

3.6

Component Selection
A good design starting point when selecting component values is to look at the

trade-off between converter efficiency and area consumption through component selection. Simulation results from Table 3.2 indicate that the converter efficiency is strongly dependent on switching frequency, corner frequency, and inductor size [10]. From the design specifications in Table 3.1 the switching frequency was chosen to be fsw = 147MHz with a LC cutoff frequency of fc = 16MHz. A good rule of thumb is to choose a corner frequency approximately one-tenth the switching frequency. A low corner frequency results in poor transient response and a high corner frequency could push the converter towards instability, making it more difficult to compensate for the closed-loop

response.

3.6.1

Inductor
From Tables 3.1 and 3.2 an inductor value of L = 250nH was selected to meet

converter specifications. For standard Buck converters the optimum efficiency occurs at the boundary of CCM and DCM. Recall from Equation (3.10) that to ensure CCM for all duty cycle values: The inductor size is much larger than the selected and would not be a practical design choice. Using a synchronous topology ensures the converter always operates in CCM regardless of inductor size.

3.6.2

Capacitor
The capacitor size can be calculated given the inductance value L = 250nH and

an LC cutoff frequency of fc = 16MHz: C= 1 2 4L2 f c = 1 4 (250 109 ) 2 (16 106 )2 = 395.786pF 400pF

Integrated energy storage capacitors can be exploited to function as an output filter capacitor. An equivalent circuit for the cross-section of a 90nm CMOS photodiode is shown in Figure 3.16. Diode Dpsubnw results from P-type substrate to N-well junction and Dpdif nw results from the P-type diffusion to N-well junction [3]. The total capacitance of one photodiode is approximately Cpd = Cm + Cd = 7.741pF + 0.460pF = 8.201pF. Calculating the number of cascaded photodiodes needed to obtain a effective capacitance of C = 400pF yields K =
400pF C pd

= 48.26.

The worst-case peak-to-peak output voltage ripple for Vout = 1.0V can be calculated using the following equations:

3.6.3

Switch
Ideal transistor models were used for both the high-side/low-side switches. To

match the technology node used for the PV cells, 90nm transistor models would be used in practice. The standard threshold voltage is Vth = 1.0V so the maximum sawtooth voltage was set to Vsawtooth = 1.2V to ensure the transistors operate in saturation during the switching cycles.

3.6.4

Summary
Table 3.3 summarizes the selection of the design components for the power stage.

CHAPTER 3. BUCK CONVERTER 41 The parasitic equivalent series resistance with the inductor and capacitor were selected to be rdcr = resr = 0.1 to meet converter specifications.

3.7

Closed-Loop Buck Converter Design

The closed-loop system will automatically adjust the output to the desired voltage

level under varying input and load transients using a control loop as shown in Figure 3.17. The modulator block consists of the PWM comparator and switch [13]. From Figure 3.18 the transfer function of the Buck converter (PWM generator and output filter) is: G (s) = G1 (s) G2 (s) = Vin Vsawtooth 1 + sresr C 1 + s (resr + rdcr ) C + s2 LC

The total compensated transfer function of the Buck converter is

3.7.1

Compensation Network
A schematic of the closed-loop Buck converter is shown in Figure 3.19. The ob-

jective of the control loop is to continuously adjust the duty cycle of the PWM comparator until Verror is driven to zero in which case Vout = Vref . A Type III compensation network (lead-lag compensation) was utilized to increase the phase margin of the open-loop response. A low parasitic resr calls for a lead-lag network to sufficiently stabilize the system. The transfer function of the compensation network is Where z1 =
1 R 2 C2 , 1 (R 1 +R3 )C3 1 , R1 (C1 +C2 ) C1 +C2 , R2 C1 C2 1 R 3 C3

z2 =

, p1 =

p2 =

and p3 =

. The

magnitude of the compensation network transfer function is: |D(s)|dB = 10 log 1 + (2f R2 C2 ) 2 20 log [2f R1 (C1 + C2 )] 10 log 1 + 2f R2 C1 C2 C1 + C2
2

+10 log 1 + (2f (R1 + R3 ) C3 ) 2 10 log 1 + (2f R3 C3 )2

The phase of the compensation network transfer function is: D (s) = 900 + tan1 [2f R2 C2 ] tan1 2f R2 C1 C2 C1 + C2 l

+tan1 [2f (R1 + R3 ) C3 ] tan1 [2f R3 C3 ] Magnitude and phase profiles for the compensation network transfer function D (s) is shown in Figure 3.20. The type III compensation network uses two zeros providing a phase boost of 180 to remedy the negative effects of the underdamped resonance of the openloop converter response at the double pole [13]. The general guidelines for pole and zero placement for a type III compensation network are [13]: 1: Choose a value for R1 , usually between 2k and 5k for discrete implementations. For

CHAPTER 3. BUCK CONVERTER

42

on-chip implementations, R1 is downscaled by an nth order factor to meet system design requirements and specifications. 2: Pick a gain
R2 R1

that will shift the open loop gain up to give the desired bandwidth

(DBW). This will allow the 0dB crossover to occur in the frequency range where the Type III network has its second flat phase. The following equation will calculate an R2 that will accomplish this given the system parameters, chosen R1 , and a chosen output filter double pole frequency, fc . R2 = DBW fc Vsawtooth Vin R1

3: Calculate C2 by placing the zero at 50% of the output filter pole frequency, fc : C2 = 1 R 2 fc

CHAPTER 3. BUCK CONVERTER

43

4: Calculate C1 by placing the first pole at the resr zero frequency:

5: Set the second pole at half the switching frequency and set the second zero at the output filter pole frequency, fc . This combination will yield the following component calculations:

figure 3.21 shows the Bode diagrams of the open-loop response, compensation network transfer function, and the total closed-loop response of the converter. The total response of the system has an infinite gain margin and a phase margin of 29.1 which is inadequate to ensure stability of the system. The compensator network transfer function and corresponding component values are:

Figure 3.21: Type III compensated Buck converter Bode diagram.

CHAPTER 3. BUCK CONVERTER

44

Notice that the value of C1 is approximately five-hundred times larger than C2 and C3 . Therefore, C2 and C3 can be implemented by cascading C1 five-hundred times (parallel configuration). To ensure stability of the system a phase margin of 45 -60 is desirable. This was accomplished by shifting the poles and zeros of the system to optimize the compensator transfer function [13] to 47.8 of phase margin. The optimized compensator transfer function is: The component values can be recalculated by equating coefficients of the the polynomial D (s)opt to the expanded form of the general compensator transfer function D (s) in Equation

3.7.2

Simulation Results
The input voltage (Vin ) was set to 1.45V and the reference voltage (Vref ) was

adjusted to achieve the desired output voltage (Vout ) range of Vout = 0.3 1.0V. The range of Vout corresponds to a duty cycle range of D=20.69-68.97% and the switching frequency (fsw ) for all the simulations was set to 147MHz. Figure 3.24 shows Vout of the Buck converter for the case when Vref is equal to 1V. Vout initially begins to rise and overshoots the desired voltage level of 1V before quickly settling after a brief period. The output capacitor was chosen correctly to minimize the output voltage ripple.

CHAPTER 3. BUCK CONVERTER

45

Figure 3.25 shows the sawtooth (Vsawtooth ), error (Verror ), and PWM signals (Vpwm ). The duty cycle of the PWM self-adjusts depending on the whether the error signal is below or above the sawtooth waveform. For the time period when Verror > Vsawtooth the PWM signal Vpwm = 1V and Vpwm = 0V when Verror < Vsawtooth . Eventually the Verror is driven to zero after a brief period of time once Vout = Vref . Using Figure 3.25, an apwhich corresponds to an output voltage of Vout = 1V.

CHAPTER 4. MAXIMUM POWER POINT TRACKING

52

Table 3.5 summarizes the simulation results for the continuous-time Buck converter. Figure 3.26 and 3.27 shows the inductor and output currents respectively. The inductor current is continuous implying the Buck converter is operating in CCM for output voltage levels 0.3-1.0V. Following Ohms law the output current waveform is identical to the output voltage waveform scaled by the load resistance.
The settling time was calculated as the time required for the output voltage to settle within 2% of its final value. In addition, the peak-to-peak inductor current ripple was determined at a reference time of t=2fLs. Analysis of the simulation results show low settling times, voltage overshoot, and ripple in the output.

Maximum Power Point Tracking

A comparative study of common MPPT techniques used in PV-based energy harvesting systems is presented in this chapter. The I-V characteristics of a photodiode are a strong function of environmental conditions including variations in the solar irradiance as well as temperature. In addition, load transients also induce undesired changes in the system operating point. MPPT techniques were developed for high-power solar arrays (e.g., rooftop systems) but can be adapted for smaller scale and lower power PV arrays. MPP tracking was achieved in two regulating stages using a DC-DC switching power regulator.

4.1

Basic Theory
The power curve and respective MPP data for a single 90nm PV cell model is

shown in Figure 4.1. Points A and B represent particular PV operating points at some time. Under varying conditions the operating point of the PV array will not be at the MPP. The objective of any MPPT method is to ensure the the PV array operates at peak maximum power at location (PM
PP

,VM P P ) despite varying source and load conditions due

to variations in solar insolation, temperature fluctuations, load transients, etc.

CHAPTER 4. MAXIMUM POWER POINT TRACKING

53

A common metric used to measure MPP efficiency is: Where Pactual is the actual (measured) power output of the PV array with MPPT control and Pmax is the true MPP of the PV array for a given temperature and irradiance value[15].

4.2

MPPT Techniques
There are more than nineteen known MPPT methods that have been developed

and each can be classified in the following categories:

CHAPTER 4. MAXIMUM POWER POINT TRACKING

54

a: Hill-climbing/P &O Algorithm This method is a very widely used MPPT algorithm due too its simple structure and lower implementation complexity relative to most other techniques. Hill climbing refers to perturbing the duty ratio of the power converter, and equivalently, perturb & observe (P&O) refers to perturbing the operating voltage of the PV cell (or array). A summary of the logic for the P&O algorithm follows the logic given in Table 4.1 where a positive perturbation is equivalent to incrementing the reference control variable (voltage or current) and a negative perturbation is equivalent to decrementing the reference control variable of the PV array. This process of incrementing and decrementing reference control variable shifts the operating point of the PV array as to converge eventually upon the MPP.

b: Incremental Conductance This technique can track the MPP by exploiting the nonlinear power curve of the PV array. At the MPP location the slope is equal to
dP dP zero ( dV = 0), on the left of the MPP the slope is positive ( dV > 0), and towards the dP right of the MPP the slope is negative ( dV < 0). The MPP is tracked by comparing I I the instantaneous conductance ( V ) term to the incremental conductance ( V ) term

and adjusts (increments or decrements) the reference operating voltage until it converges upon the MPP voltage. The convergence speed of the algorithm depends on the resolution (increment size) of the reference voltage adjustments. A larger incremental size allows for faster convergence at the cost of poorer MPP efficiency resulting from large oscillations. On the other hand, a small increment size yields a more accurate MPP operating point with very little oscillation but the rate of convergence is degraded. Typically, a digital signal processing (DSP) module or microcontroller is used to implement this technique.

CHAPTER 4. MAXIMUM POWER POINT TRACKING

55

c: Fractional Open-Circuit Voltage This technique is also referred to as the open circuit voltage (VOC ) method. The relationship between the MPP voltage is VM P P k1 VOC where k1 is a proportionality constant. This constant is a function of the PV array characteristics and as a result needs to be determined for a number of different solar irradiance values and temperature levels prior to operating the PV array. This constant can be experimentally determined through trial and error. It has been shown that k1 lies somewhere between 0.71-0.78. This technique is not considered to be a true MPPT method since the system will never exactly operate at the MPP since k1 is only an approximation. This also implies that it is not necessary to use a DSP or microcontroller to implement the technique. Implementation complexity and power loss are two major potential problems with this method when partial shading of the solar panel is taken into consideration. d: Fractional Short-Circuit Current As with the fractional VOC method, the fractional ISC MPPT technique exploits the fact that IM P P k2 ISC . The proportionality constant k2 needs to be determined beforehand and is different for different PV arrays. It has been experimentally determined that the value of k2 is between 0.78-0.92. The disadvantage of this method lies in the difficulty of measuring ISC since it requires additional circuitry and subsequently raises the cost of the system. Similar to the fractional VOC technique, this technique is also not a true MPPT method. e: Fuzzy Logic Control This method of control for MPPT requires use of a microcontroller. There are three essential stages to fuzzy logic control: fuzzification, rule base table lookup, and defuzzification. MPPT fuzzy logic controllers have demonstrated fast convergence at the cost of implementation complexity in the digital domain. In addition, the the performance of fuzzy logic control can vary depending on the knowledge of the user to determine the correct error computation and fuzzy rule base table. f: Neural Network Similar to fuzzy logic control, this method of MPPT requires use of a microcontroller which implies that a digital implementation is necessary. There are three common layers to a neural network: input, hidden, and output layers. PV arrays have varying characteristics resulting in a neural network being specific only to

CHAPTER 4. MAXIMUM POWER POINT TRACKING

56

the particular PV array that it was trained for. In addition, PV array characteristics change overtime and so neural networks need to undergo periodic training to ensure MPPT accuracy