RANGKAIAN ELEKTRONIKA

(ELECTRONIC CIRCUITS) oleh: Dr. Ir. Retno Wigajatri Purnamaningsih, MT

Tomy Abuzairi, ST, MT, M.Sc

1/89

Reference Books: 1. Robert L. Boylestad and Louis Nashelsky, Electronic Devices and Circuit Theory, Pearson Education, Inc., Uppersaddle River, New Jersey 07458, USA, 2006. 2. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Singapore, 2003.

1/89

2/89

Reference Books: [1] Robert L. Boylestad and Louis Nashelsky, Electronic Devices and Circuit Theory, Pearson Education, Inc., Uppersaddle River, New Jersey 07458, USA, 2006. [2] Jacob Millman and Christos C. Halkias, Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill International Book Co., 1972. [3] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., Singapore, 2003. [4] Jacob Millman dan Arvin Grabel, Microelectronics, McGraw Hill International Editions, Electronic Engineering Series, Singapore, 1988. [5] Roger T. Howe dan Charles G. Sodini, Microelectronics An Integrated Approach, Prentice Hall Electronics and VLSI Series, Prentice Hall, Inc., Uppersaddle River, New Jersey 07458, USA, 1997.

3/89

DAFTAR BAHAN KULIAH

Semiconductor Diodes Diode Applications Bipolar Junction Transistors DC Biasing - BJTs BJT AC Analysis Field-Effect Transistors FET Biasing FET Amplifier BJT and JFET Frequency Response Operational Amplifier Op-Amp Applications Power Amplifiers Linear-Digital ICs Feedback and Oscillator Circuits Power Supplies (Voltage Regulators)

CHAPTER 1. CHAPTER 2. CHAPTER 3. CHAPTER 4. CHAPTER 5. CHAPTER 6. CHAPTER 7. CHAPTER 8. CHAPTER 9. CHAPTER 10. CHAPTER 11. CHAPTER 12. CHAPTER 13. CHAPTER 14. CHAPTER 15.

4/89

DAFTAR BAHAN KULIAH

Semiconductor Diodes Diode Applications Bipolar Junction Transistors DC Biasing - BJTs BJT AC Analysis Field-Effect Transistors FET Biasing FET Amplifier BJT and JFET Frequency Response Operational Amplifier Op-Amp Applications Power Amplifiers Linear-Digital ICs Feedback and Oscillator Circuits Power Supplies (Voltage Regulators)

CHAPTER 1. CHAPTER 2. CHAPTER 3. CHAPTER 4. CHAPTER 5. CHAPTER 6. CHAPTER 7. CHAPTER 8. CHAPTER 9. CHAPTER 10. CHAPTER 11. CHAPTER 12. CHAPTER 13. CHAPTER 14. CHAPTER 15.

5/89

FET Amplifiers

1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17)

Introduction FET Small-Signal Model JFET Fixed-Bias Configuration JFET Self-Bias Configuration JFET Voltage-Divider Configuration JFET Source-Follower (Common-Drain) Configuration JFET Common-Gate Configuration Depletion-Type MOSFETs Enhancement-Type MOSFETs E-MOSFET Drain-Feedback Configuration E-MOSFET Voltage-Divider Configuration Designing FET Amplifier Networks Summary Table Effect of RL and Rsig Cascade Configuration Trouble Shooting Practical Applications

6/89

8.1. Introduction

Review 7. FET Biasing

ELECTRONIC CIRCUIT
7/89
The level of VDS can be determined by applying Kirchhoffs voltage law to the output circuit, with the result that

CHAPTER 7. FET BIASING 7.3. SELF-BIAS CONFIGURATION

KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

7/89

Applying Kirchhoggs voltage law in clockwise direction to indicate loop of FIG. 7.22 result in

ELECTRONIC CIRCUIT
CHAPTER 7. FET BIASING 7.4. VOLTAGE-DIVIDER CONFIGURATION

8/89

Substituting

KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

8/89

ELECTRONIC CIRCUIT
9/89

CHAPTER 7. FET BIASING 7.6. ENHANCEMENT-TYPE MOSFETs

KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

9/89

10/89

8.1. Introduction

8. FET AMPLIFIERS 8.1. Introduction

11/89

8.1. Introduction

FET Amplifiers provide an excellent voltage gain with the added feature of a high input impedance, low-power consumption configurations with good frequency range and minimal size and weight JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers having similar voltage gains The depletion MOSFET (MESFET) circuit, however, has a much higher input impedance than a similar JFET configuration

Whereas a BJT device controls a large output (collector) current by means of a relatively small input (base) current, the FET device controls an output (drain) current by means of a small input (gate-voltage) In general, therefore, the BJT is a CURRENT-CONTROLLED device and the FET is a VOLTAGE-CONTROLLED device
The FET can be used as a linear amplifier or as a digital device in logic circuits In fact, the enhancement MOSFET is quite popular in digital circuitry, especially in CMOS circuits that require very low power consumption FET device are also widely used in high-frequency applications and in buffering (interfacing) applications

12/89

8.2. FET Small-Signal Model

8. FET AMPLIFIERS 8.2. FET Small-Signal Model

13/89
The gate-to-source voltage controls the drainto-source (channel) current of an FET

8.2. FET Small-Signal Model

And the change in collector current that will result from a change in gate-to-source voltage can be determined using transconductance factor gm as follows

Graphical determination of gm (see Fig. 8.1)

14/89

8.2. FET Small-Signal Model

15/89
Mathematical definition of gm (the derivative of a function at a point is equal to the slope of the tangent line drawn at that point)

8.2. FET Small-Signal Model

The maximum of the slope is happened at VGS = 0 V, therefore,

And the general equation of Eq. (8.4) will be

On specification sheets, gm is provided as yfs, where y indicates it is part of an admitance equivalent circuit, the f signifies forward transfer parameter, and the s indicates that it is connected to the source terminal

16/89

8.2. FET Small-Signal Model

17/89
Plotting gm versus VGS

8.2. FET Small-Signal Model

Effect of ID on gm

18/89
FET input impedance Zi

8.2. FET Small-Signal Model

For a JFET a practical value of 109 (1000 M) is typical, whereas a value of 1012 to 1015 is typical for MOSFETs and MESFETs.

FET output impedance Zo On FET specification sheets, the output impedance will typically appear as yos with the unit of S
The parameter yos is a component of an admittance equivalent circuit, with the subscript o signifying an output network parameter and s ther terminal (source) to which it is attached in the model Yos has a range of 10 to 50 S or 20 to 100 K

19/89

8.2. FET Small-Signal Model

20/89

8.2. FET Small-Signal Model

21/89
FET AC Equivalent Circuit

8.2. FET Small-Signal Model

22/89

8.2. FET Small-Signal Model

23/89

8.3. JFET Fixed-Bias Configuration

8. FET AMPLIFIERS 8.3. JFET Fixed-Bias Configuration

24/89

8.3. JFET Fixed-Bias Configuration

Zi

25/89

8.3. JFET Fixed-Bias Configuration

Zo, Setting Vi = 0 V as required by definition of Zo will establish VGS = 0 V also

Av

Phase Relationship The negative sign in the resulting equation for Av clearly reveals a phase shift of 180 between input and output voltages

26/89

8.3. JFET Fixed-Bias Configuration

27/89

8.4. JFET Self-Bias Configuration

8. FET AMPLIFIERS 8.4. JFET Self-Bias Configuration

28/89
Bypassed RS

8.4. JFET Self-Bias Configuration

Zi

Zo

29/89
Bypassed RS

8.4. JFET Self-Bias Configuration

Av

30/89
Unbypassed RS Rd =

8.4. JFET Self-Bias Configuration

Zi

Zo

31/89
Unbypassed RS Rd included in the network

8.4. JFET Self-Bias Configuration

32/89
Unbypassed RS Rd included in the network

8.4. JFET Self-Bias Configuration

Av

33/89
Unbypassed RS Rd included in the network

8.4. JFET Self-Bias Configuration

Phase Relationship
The negative sign in Eq. (8.26) again reveals a 180 phase shift will exist between Vi and Vo

34/89

8.4. JFET Self-Bias Configuration

35/89

8.4. JFET Self-Bias Configuration

36/89

8.5. JFET Voltage-Divider Configuration

8. FET AMPLIFIERS 8.5. JFET Voltage-Divider Configuration

37/89

8.5. JFET Voltage-Divider Configuration

Zi
Zo

38/89

8.5. JFET Voltage-Divider Configuration

Av

39/89

8.8. Depletion-Type MOSFETs

8. FET AMPLIFIERS 8.8. Depletion-type MOSFETs

40/89

8.8. Depletion-Type MOSFETs

41/89

8.8. Depletion-Type MOSFETs

42/89

8.8. Depletion-Type MOSFETs

43/89

8.9. Enhancement-Type MOSFETs

8. FET AMPLIFIERS 8.9. Enhancement-type MOSFETs

44/89

8.9. Enhancement-Type MOSFETs

45/89

8.11. EMOSFET Voltage-Divider Configuration

8. FET AMPLIFIERS 8.11. E-MOSFET Voltage-Divider Configuration

46/89

8.11. EMOSFET Voltage-Divider Configuration

Zo

Zi

Av

47/89

8.13. Summary Tables

8. FET AMPLIFIERS 8.13. Summary Tables

48/89

8.13. Summary Tables

49/89

8.13. Summary Tables

50/89

8.13. Summary Tables

51/89

8.13. Summary Tables

52/89

8.14. Effects of RL and Rsig

8. FET AMPLIFIERS
8.14. Effects of RL and Rsig

53/89
All of the two-port equations developed for the BJT transistor apply to FET networks also because the quantities of interest are defined at the input and output terminals and not the components of the system

8.14. Effects of RL and Rsig

54/89

8.14. Effects of RL and Rsig

55/89
Avs

8.14. Effects of RL and Rsig

56/89

8.14. Effects of RL and Rsig

57/89

8.14. Effects of RL and Rsig

58/89

8.14. Effects of RL and Rsig

59/89

8.15. Cascade Configuration

8. FET AMPLIFIERS
8.15. Cascade Configuration

60/89
The total gain is the product of the gain of each stage including the load effects of the following stage

8.15. Cascade Configuration

61/89

8.15. Cascade Configuration

62/89

8.15. Cascade Configuration

63/89

8.15. Cascade Configuration

64/89

8.17. Practical Applications

8. FET AMPLIFIERS
8.17. Practical Applications

65/89

8.17. Practical Applications

THREE CHANNEL AUDIO MIXER

A three channel JFET audio mixer which the three input signals can come from different sources such as a microphone, a musical instrument, background sound generators, and so on All signals can be applied to the same gate terminal because the input impedance of the JFET is so high that can be approximated by an open circuit In general, the input impedance is 100 M (109 ) or better for JFETs and 100 millions (1014 ) or better for MOSFETs

If BJTs were employed instead of JFETs, the lower input impedance would require a transistor amplifier for each channel or at least an emitter-follower as the first stage to provide a higher input impedance
The 10-F capacitors are there to prevent any dc biasing levels on the input signal from appearing at the gate of the JFET, and the 1-M potentiometers are the volume controls for each channel The need for the 100-K resistors for each channel is less obvious. Their purpose is to ensure that one channel does not load down the other channels and severely reduce or distort the signal at the gate

66/89

8.17. Practical Applications

In general, therefore, the 100-K resistors compensate for any difference in signal impedance to ensure that one does not load down the other and develop a mixed level of signals at the amplifier. Technically, they are often called SIGNAL ISOLATION RESISTORS

67/89

8.17. Practical Applications

SILENT SWITCHING

Any electronic system that incorporates mechanical switching such as shown in Fig. 8.55 is prone to developing noise on the line that will reduce the signal-to-noise ratio One effective method to essentially eliminate this source of noise is to use electronic switching such as shown in Fig. 8.56a for a twochannel mixing network In Fig. 8.56a, the signals to be mixed are applied to the drain side of each JFET, and the dc control is connected directly to the gate terminal of each JFET With 0 V at each control terminal, both JFETs are heavily ON, and the resistance from D1 to S1 and from D2 to S2 is relatively small, say, 100 for this discussion Both electronic switches can be put in the OFF state by applying a voltage that is more negative than the PINCH-OFF LEVEL as indicated by the 10 V in Fig. 8.56a

68/89
The level of OFF resistance can approach 10,000 M, which certainly can be approximated by an open circuit for most applications

8.17. Practical Applications

SILENT SWITCHING

Since both channels are isolated, one can be ON while the other is OFF The speed of operation of a JFET switch is controlled by the substrate (those due to the device construction) and stray capacitance levels and the low ON resistance of the JFET
Maximum speeds for JFETs are about 100 MHz, with 10 MHz being more typical However, this speed is critically reduced by the input resistance and capacitance of the design In Fig. 8.56a, the 1-M resistor and the 47-nF capacitors have a time constant of = RC = 47 ms = 0.047 s for the dc charging network that is controlling the voltage at the gate If we assume two time constants to charge to the pinch-off level, the total time is 0.094 s, or a switching speed of 1/0.094 s 10.6 per-second

69/89

8.17. Practical Applications

SILENT SWITCHING

Compared to the typical switching speed of the JFET at 10 million times in 1 s, this number is extremely small Keep in mind, however, that the application is the important consideration, and for a typical mixer, switching is not going at speeds greater than 10.6 per-second unless we have some radical input signals It is necessary to have the RC time constant period of time before pinch-off level is reached Any spike on the line will not be present long enough to charge the capacitor and switch the state of the JFET It is important to realize that THE JFET SWITCH IS A BILATERAL SWITH (signals in the ON state can pass through the drain-source region in either direction) Compared to the diode which is not a bilateral switch because it can conduct current at low voltages in only one direction It should be noted that because the state of the JFETs can be controlled by a dc level

70/89

8.17. Practical Applications

SILENT SWITCHING

71/89

8.17. Practical Applications

PHASE-SHIFT NETWORKS

Using the voltage-controlled drain-to-source resistance characteristic of a JFET, we can control the phase angle of a signal using the configurations of Fig. 8.58a Fig. 5.58a is a PHASE-ADVANCE NETWORK which adds an angle to the signal, while Fig. 5.58b is a PHASE-RETARD CONFIGURATION, which creates a negative phase shift

72/89

8.17. Practical Applications

PHASE-SHIFT NETWORKS

For example, let us consider the effect of RDS on an input signal having a frequency such as 10 KHz if we apply it to the network of Fig. 5.58a with the drain-to-source resistance of 2 K due to an applied gate-to-source voltage of -3V

An output signal that is 78.2% of its applied signal but with a phase shift of 38.52

73/89
For the network of Fig. 8.58b,

8.17. Practical Applications

PHASE-SHIFT NETWORKS

TUGAS RANGKAIAN ELEKTRONIKA

Chapter 8. FET Amplifier
1. 8.3 JFET Fixed-Bias Configuration (no. 18) 2. 8.4 Self-Bias Configuration (no. 20)

74/89

3. 8.5 JFET Voltage-Divider Configuration (no. 23) 4. 8.8 Depletion-Type Mosfet (no. 37) 5. 8.15 Cascade Configuration (no. 50)

KULIAH RANGKAIAN ELEKTRONIKA (SEMESTER III S1 INTERNATIONAL 2008) DEPARTEMEN TEKNIK ELEKTRO FTUI

74/89