No.1, Qun Yi Road, Jhunan, Miaoli, Taiwan 350, R.O.C. Tel : +886-37-586-896 Email : sales@phison.com Fax : +886-37-587-868 kspua@phison.

com

Phison Electronics Corporation

USB 2.0 Flash Controller Specification

PS2251-33
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Version 1.2

All rights are strictly reserved.

Any portion of this paper shall not be reproduced, copied, or translated to

any other forms without permission from Phison Electronics Corporation.

Document Number : S-09003

Phison Electronics Corporation

No.1, Qun Yi Road, Jhunan, Miaoli, Taiwan 350, R.O.C. Tel : +886-37-586-896 Fax : +886-37-587-868

Table of Contents
A. B. C. D. General Description ............................................................................ 1 Controller Features ............................................................................. 2 BLOCK DIAGRAM ............................................................................... 4 Pin Assignment and Description ....................................................... 5 D1. Pin Assignment - 64pins ......................................................................5 D2. Pins Listed in Numeric Order 64pins ..............................................6 D3. Pin Assignment - 48pins ......................................................................7 D4. Pins Listed in Numeric Order 48pins ..............................................8 D5. Pin Description.......................................................................................9 System Power Consumption ........................................................... 10 Electrical Specifications................................................................... 10 DC Characters ................................................................................... 11 AC Characters ................................................................................... 12
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E. F. G. H. I.

Package Information......................................................................... 16 I1. 48 Pins ..................................................................................................16 I2. 64 Pins ..................................................................................................17

Revision History

Revision 1.0 New Release

History

Date 14-Jan-2009

DCC.: S-09003

Phison Electronics Corporation

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A. General Description
The PHISON!s PS2251-33 micro-controller supports USB 2.0 & 1.1 and interface to NAND Flash Memory. This chip is specially designed for portable storage device or build-in to the PC / Notebook / IA system. It is pin-to-pin compatible to previous controllers. (eg : PS2136 & PS2231 & PS2232"..etc)

PS2251-33 controller implements with PRAM (program RAM) architecture, which can upgrade firmware code anytime if required. This is very helpful for time-to-market & Mass Production solution.

By using this single chip solution, it will reduce a lot of efforts which was needed
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from R/D to production, as well as simplifying the RMA problems. With the USB plug & play function and driver-less solution with most of the operating systems, this solution provides not only easy to install, but also fast, easy to use and low cost way for user.

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B. Controller Features

Support Host Interfaces : USB 2.0 & 1.1 Interface Fully compatible with USB Specification Version 2.0 & 1.1 High speed 480Mbit/second supporting Full speed 12Mbit/second supporting Support one CONTROL transfer, one INTERRUPT transfer and two BULK transfer Support four Endpoints : Endpoint 0 : 64 Bytes CONTROL transfer Endpoint 1 : 512 Bytes BULK transfer for IN transaction Endpoint 2 : 512 Bytes BULK transfer for OUT transaction Endpoint 3 : 64 Bytes INTERRUPT transfer for IN transaction Support Data Payload Endpoint 0 : max 64 bytes Endpoint 1 : max 512 bytes Endpoint 2 : max 512 bytes Endpoint 3 : max 64 bytes Support USB power saving mode
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Build-In NAND Flash Memory Interface Build-in hardware ECC circuit. Support SLC (Single level cell) 2k-page large block NAND Flash. Support SLC (Single level cell) 4k-page large block NAND Flash. Support MLC (Multi level cell) 2k-page Large Block NAND flash. Support MLC (Multi level cell) 4k-page Large Block NAND flash. Support MLC (Multi level cell) 8k-page Large Block NAND flash. Support 3.3V Flash I/O: Internal 3.3V regulator can supply current for controller analog circuit, controller I/O and Flash. Support 1.8V Flash I/O: Internal 1.8V regulator can supply the current for controller core, controller I/O and Flash.

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Support In-System Programming through USB Port Buffer SRAM : Build-in regulator 48-pins / 64-pins QFP Package Operating Voltage: 4.5V ~ 5.5V. USB bus-powered capability. Power Saving implemented. Working Frequency: 12MHz. 16 buffers for performance improvement

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C. BLOCK DIAGRAM

PC

USB Cable
USB PHY

USB
USB CONTROLLER

Flash Data Control Module

NAND Flash

External ROM Code

Micro Processor

EXT IO Port

SRAM_EB Ring Oscillator Mask ROM RAM

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SRAM_BUF

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D. Pin Assignment and Description

D1. Pin Assignment - 64pins

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D2. Pins Listed in Numeric Order Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 V33 V18,VCCK PO_FLH_CEB[2] PO_FLH_CEB[3] VCCK PB_FLH_DIO[8] PO_FLH_WEB1 PB_FLH_DIO[0] PO_FLH_REB1 PO_FLH_CLE0 PO_FLH_CLE1 PO_FLH_ALE0 PO_FLH_ALE1 PO_FLH_WEB0 VDET,VCC3IO VSSK,VSSIO PO_FLH_REB0 PB_FLH_DIO[1] PB_FLH_DIO[9] PB_FLH_DIO[2] PB_FLH_DIO[10] PB_FLH_DIO[3] Signal Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

64pins Signal Pin 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VCC3IO PO_FLH_CEB[5] PI_TEST_SEL0 PB_GPIO[3] PI_TEST_MODE_N PO_FLH_CEB[6] PO_FLH_CEB[7] VCCK XSCI XSCO AVDDHP,AVDDH_USB AGNDP,AGND_USB NC DM DP NC VSSK GNDA VCC5A Signal VSSK,VSSIO

PB_FLH_DIO[11] PO_FLH_CEB[0] PI_FLH_RDY VCC3IO VSSIO,VSSK VCCK PO_FLH_CEB[1] PB_FLH_DIO[4] PB_FLH_DIO[12] PB_FLH_DIO[5] PB_FLH_DIO[13] PB_FLH_DIO[6] PB_FLH_DIO[14] PB_FLH_DIO[7] PB_FLH_DIO[15]
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PO_FLH_WPB PO_FLH_CEB[4] PB_GPIO[0] PB_GPIO[1] PB_GPIO[2] PI_RST_N PI_TEST_SEL1

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D3. Pin Assignment - 48pins

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D4. Pins Listed in Numeric Order Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal

V33 V18,VCCK PO_FLH_CEB[2] PO_FLH_CEB[3] PB_FLH_DIO[8] PB_FLH_DIO[0] PO_FLH_CLE0 PO_FLH_ALE0 PO_FLH_WEB0 VDET,VCC3IO PO_FLH_REB0 PB_FLH_DIO[1] PB_FLH_DIO[9] PB_FLH_DIO[2] PB_FLH_DIO[10] PB_FLH_DIO[3]

48pins Signal Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Signal

PI_RST_N PI_TEST_SEL1 VCC3IO PI_TEST_SEL0 PI_TEST_MODE_N VCCK XSCI XSCO AVDDHP,AVDDH_USB AGNDP,AGND_USB NC DM DP NC VSSK,GNDA VCC5A

Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PB_FLH_DIO[11] PO_FLH_CEB[0] PI_FLH_RDY PO_FLH_CEB[1] PB_FLH_DIO[4] PB_FLH_DIO[12] PB_FLH_DIO[5] PB_FLH_DIO[13] PB_FLH_DIO[6] PB_FLH_DIO[14] PB_FLH_DIO[7] PB_FLH_DIO[15] PO_FLH_WPB PB_GPIO[0] PB_GPIO[1]
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PB_GPIO[2]

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D5. Pin Description Pin Name V18 V33 VCC5A GNDA DP DM

AVDDHP,AVDDH_USB AGNDP,AGND_USB

Dir. VCC18 VCC33 VCC5 GND I/O I/O VCC33 GND VCC33 O I I

USB + Regulator Interface Pin Description 1.8V regulator power supply 3.3V regulator power supply 5.0V regulator power input 0V regulator ground reference input USB 2.0 data in positive pin terminal. USB 2.0 data in negative pin terminal. USB 2.0 PHY power (3.3V) USB 2.0 PHY ground reference (0V) USB 2.0 PLL ground (0V) Crystal oscillator output Crystal oscillator input USB 2.0 core power (1.8V) No Connection FLASH Interface Pin Description Flash chip enable, low active. Flash data bus
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VSSK XSCO XSCI VCCK NC

Pin Name PO_FLH_CEB [7:0] PB_FLH_DIO [15:0] PO_FLH_ALE0, PO_FLH_ALE1 PO_FLH_CLE0, PO_FLH_CLE1 PO_FLH_REB0, PO_FLH_REB1 PO_FLH_WEB0, PO_FLH_WEB1 PO_FLH_WPB PI_FLH_RDY

Dir. O I/O O O O O O I

Flash address latch enable, high active. Flash command latch enable, high active. Flash read control signal, low active. Flash write control signal, low active. Flash write protect control signal, low active. Flash ready/busy signal input Global Signal

Pin Name PI_RST_N PI_TEST_SEL0 PI_TEST_SEL1

PI_TEST_MODE_N

Dir. I I I I I/O VCC33 VCC18 GND GND Reset Signal

Pin Description Test Mode Signal. EAMODE Select Signal. USB VBUS input 4-bit GPIO 3.3V IO power 1.8V digital core power 0V IO ground reference 0V digital core ground reference
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PB_GPIO[0:3] VCC3IO VCCK VSSIO VSSK

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E. System Power Consumption

Item Normal Suspend Sleep Read Write Power Consumption (mA) 1 * Flash 61.07 0.356 0.361 106.90 155.80 2 * Flash 62.28 0.402 0.387 121.98 181.99

The above values are for reference only, it may change according to the flash memory used.

F. Electrical Specifications
Absolute Maximum Rating Item 1 2 3 4 5 6 Symbol VDD-VSS VIN Ta Ta Tst Tst Parameter DC Power Supply Input Voltage Operating Temperature (Commercial) Operating Temperature (Industrial) Storage Temperature (Commercial) Storage Temperature (Industrial)
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MIN -0.3 VSS-0.3 0 -40 -40 -50

MAX +5.5 VDD+0.3 +70 +85 +85 +125

Unit V V

Parameter Operating Temperature (Commercial) Operating Temperature (Industrial) VDD Voltage

Symbol Ta Ta VDD

Min 0 -40 3.0 4.5

Typ +25 +25 3.3 5.0

MAX +70 +85 3.6 5.5

Unit

V V

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G. DC Characters
DC characteristics of 3.3V I/O Cells Symbol Parameter Conditions Core Area 3.3V I/O LVTTL 0.8 LVTTL 1.6 |Iol| = 2 ~ 16 mA |Ioh| = 2 ~ 16 mA
VCC3IO - 0.4

MIN 1.62 3.0 0

TYP 1.8 3.3 25 1.5 1.1

MAX 1.98 3.6 115

Unit V V V V

VCCK Core Power Supply VCC3IO Power Supply Temp Vt VtVt+ Vol Voh Rpu Rpd Iin Ioz Junction Temperature Switching threshold Schmitt Trigger Negative Going threshold voltage Schmitt Trigger Positive Going threshold voltage Output Low voltage Output High voltage

2.0 0.4

V V V

Input Pull-Up Resistance PU=high, PD=low Input Pull-Down Resistance Input Leakage Current Tri-state Output Leakage Current PU=high, PD=low
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40 40

75 75

190 190 1

K K !A !A

Vin = VCC3I or 0 -10 "1

10

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H. AC Characters
H1. Flash Memory Interface Timing
NAND Flash Memory Interface Timing

Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Read Cycle Time /RE Pulse Width /RE High Hold Time Ready to /RE Low

Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRC tRP tREH tRR
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Min 0 10 0 10 25 0 10 20 10 45 15 50 25 15 60

Max -

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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H1.1 Command Latch Cycle

H1.2 Address Latch Cycle

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H1.3 Input Data Latch Cycle

H1.4 Sequential Out Cycle after Read (CLE=L, /WE=H, ALE=L)

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H1.5 EDO mode for data latch

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I. Package Information
I1. 48 Pins

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I2.

64 Pins

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