NT_N MOAT NOISE ANALYSIS

A detailed analysis of a NT_N guard ring structure

Adrian OShaughnessy Expert Layout IC April 2014

| Adrian OShaughnessy

SUMMARY The purpose of this report is to provide a detailed example and analysis of a N_TN guard ring structure. This scheme could be used to separate the analog and digital domains on chip, and thus used for noise attenuation and noise collection. Furthermore this report will hypothesis additional noise performance improvements that could be made for added noise isolation.

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1.0

INTRODUCTION

The noise isolation scheme I propose follows the format: NWELL GR PTAP GR N_TN PTAP GR NWELL GR This report will break this guard ring strategy down into cross sectional views and will highlight the various parasitic components created. Each component will be analyzed in detail. The goal of this report is to further educate Layout Engineers on noise isolation construction and to highlight the critical importance of understanding the concepts of cross sectional views. 2.0 2.1 GUARD RING LAYERS NT_N (Native) Layer

This layer is used for mask making rather than process requirements. It is defined as a non-PWell and a non-Nwell region. In other words, the area covered by NT_N will NOT get doped either P or N. This is important to understand because typical CMOS design takes place on heavily doped P-Substrate (Psub). Heavily doped Psub has low resistivity. The reason being, Psub that is low in resistance will provide good latch up protection. The flip side to this is that its bad for noise isolation. However if we cover an area of Psub with NT_N, this area wont get doped and will therefore resemble intrinsic silicon.
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Intrinsic silicon by its very nature is highly resistive. It should also be noted the N_TN drawn layer adds no process cost and does not consist of an extra mask. 2.2 Nwell Guard Ring

Nwell and Ptap guard rings are sometimes misunderstood and are therefore not implemented correctly. The purpose of the Nwell guard ring is to provide noise attenuation. With this is mind, its vital the guard rings attributes are maximized. This will be discussed in detail later. 2.2 Ptap Guard Ring

As previously mentioned, Ptap guard rings are also often misunderstood and are therefore executed poorly. The purpose of this guard ring is to collect noise. For this reason they are commonly known as sacrificial collectors. Its crucial certain factors of this guard ring are followed in order for it to fulfill its purpose efficiently. This will also be discussed later in detail.

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3.0

MOAT CONSTRUCTION

Ok lets take a look at the Moat guard ring:

A N A L O G

N W E LL G R

P T A P G R

NT_N

P T A P G R

N W E LL G R

D I G I T A L

Figure 1: Isolation Scheme

N W

P
C1 R4 C3 R3 R5

P
C2

N W

R1

PSUB

NT_N Area

PSUB

R2

Figure 2: Cross sectional view

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3.1

Noise Guard Ring Parasitic Components

In order to fully understand how the above guard ring performs as a noise isolator, we must first consider and investigate the capacitive and resistive elements associated with its construction. 3.1.1 Capacitive Elements C1 & C2 Capacitors C1 & C2 are created by the sidewall P-N junctions. Remember a capacitor consists of two conducting plates, at different potentials, separated by an insulating material called the dielectric. In this case C1 is tied to VDDA/ GNDA and C2 is tied to VDDD/GNDD. The dielectric in both cases is Psub. The value of these caps is also important and therefore the spacing X in figure1, comes into play. Lets recap on how to determine the capacitance of a capacitor:

Where:
= Capacitance of capacitor = dielectric constant of the material between the plates = electric constant = Area overlap of the plates = Thickness of the dielectric

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Its crucial to note at low frequencies, capacitors act like an open, while at high frequencies they act as a short. Ever wondered why this is? Its to do with the reactance of the capacitor. This is critically important to understand. A capacitors reactance is determined by:

Where:
= Reactance of capacitor = Frequency = Capacitance of capacitor

It can be seen from the equation that capacitor reactance is inversely proportional to frequency. In other words, as the frequency goes up, the reactance of the capacitor goes down and eventually resembles a short. It can also be deduced from the above equation that the capacitance value is important. The higher the capacitor value, the lower the capacitor reactance. If we now apply our new found knowledge of reactance to the noise isolation scheme, we can say at high frequencies, capacitors C1&C2 will act as shorts. But is this good or bad? This will be discussed in detail later on. What about the capacitor C3? We have two conductors (Ptaps) at different potentials (star connections), separated by a dielectric which in this case is almost intrinsic silicon. If C1&C2 act like shorts at high frequency, then C3 could potentially short all noise across the domains! Thankfully because the plates are so far removed etc.
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the capacitor C3 is negligible. Therefore the width of NT_N is important. The width of NT_N also determines the resistive barrier between the domains. 3.1.2 Resistive Elements R1,R2, R3,R4 & R5 Weve already said the width of NT_N determines the size of R3. But we also need to consider the Nwell resistances R1&R2. Whenever I see a Nwell guard ring used around a block, I always wonder about its purpose. Why is it there? Some colorful answers have been given. So what is the purpose of an Nwell GR? Well its purpose is to provide noise attenuation. Because Psups resistance is not uniform, i.e. it gets more resistive the deeper it goes, noise usually travels close to the top. As the noise hits the Nwell barrier, its forced deeper into substrate. Depending on the width of the guard ring, it will get further attenuated. Therefore Nwell width is crucially important. It should also be noted the Nwells resistive integrity is important. We can now understand the role of the Nwell guard rings in this particular isolation scheme -> noise attenuation. Now lets look at the resistors R4&R5. These represent the resistance of the Ptap guard rings. Again we need to fully understand the role of the Ptaps in the full isolation scheme. Unlike Nwell GR structures, Ptap GRs are used as noise collectors. Their job is to collect up any stray noise and provide a path for it off chip.
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We should now understand that its key to have this path as low in impedance as possible. Usually Ptap GRs are star connected back to local GND pads. To summarize: Nwell GRs -> Noise attenuation Ptap GRs -> Noise collectors 3.2 Moat Guard Ring theory

In section 3.1.1, I asked the question regarding C1&C2 acting as shorts at higher frequencies and was it good or a bad thing? Well now we can look at this question in the overall context of the isolation design: The Nwell guard rings are used to provide noise attenuation. However the worst case scenario is some noise will still get through. The Ptap guard rings placed beside the Nwell guard ring can now do their job and collect any stray noise. Capacitors C1&C2 provide an added benefit because they act as shorts at high frequencies. Therefore noise from the Nwell guard ring gets directed injected into the Ptap rings. This is an excellent added bonus in our noise isolation strategy. Again the worst case scenario would be the Ptap GRs dont get all the noise. Now the un-doped substrate comes into play. As weve said, intrinsic silicon is highly resistive and therefore provides excellent noise attenuation. Any stray noise at this point will be further dissipated .

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It can now be seen from Figure 1, excellent noise attenuation and filtering can be obtained. 4.0 NOISE ISOLATION IMPROVMENTS

However could we further improve this already robust scheme? I believe so by adding in further Ptap guard ring and N_TN placements:

A N A L O G

P T A P G R

N T N

N W E LL G R

P T A P G R

NT_N

P T A P G R

N W E LL G R

N T N

P T A P G R

D I G I T A L

Figure 3: Extra Ptap GRs and NT_N areas

N T N

N W

P
C1 C3 R3

N W

N T N

PSUB

NT_N Area

C2

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Ok lets discuss the possibility of improving the current isolation scheme by adding extra Ptaps guard rings to the other sides of their respective Nwell guard rings. As weve stated, Ptap rings are used as noise collectors (also known as sacrificial collectors). I believe by adding one to each side of the Nwell ring, greater noise isolation can be achieved. However some important points should be considered. Unlike the original Ptap ring, we do NOT want a short to the Nwell tap. We want the new Ptap ring to collect noise but we also want as much attenuation as possible before noise hits the Nwell ring. We therefore need to ensure the sidewall junction capacitance (C2 in figure 3), is as small as possible. Remember - small capacitance will equate to larger capacitor reactance. We need the capacitor reactance to remain high for as long as possible. Lets recap on the equations: Capacitor reactance

Capacitor capacitance

So how can we ensure the capacitor C2 is as small as possible?

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Heres some suggestions: Distance between the new Ptap ring and Nwell ring should be as wide as possible. This will ensure a greater dielectric thickness. Changing the dielectric constant:
= dielectric constant of the material between the plates

By introducing a new NT_N region between the new Ptap and Nwell rings, weve changed the dielectric constant and effectively decreased the value of the cap. The new NT_N region will also have the added benefit of providing a highly resistive substrate between the new Ptap and Nwell ring to ensure further noise attenuation. Unfortunately theres a price to pay for these added benefits; Space burn! Its important to note that NT_N comes with some DRC baggage. Spacing requirements to such layers as OD and Nwell are needed. However with some added floor planning considerations, I believe this modification could be achieved. 4.1 Triple Well Isolation

Using a buried Nwell layer (Deep Nwell) is an excellent technique for noise isolation. Typically though this approach needs to be adopted at the beginning of a layout design as its not easily migrated too later on in the design cycle.

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Triple well isolation is a paper on its own, but heres a quick summary: Used to isolate noisy NMOS devices. The MOS sits within a standard PW doped silicon region, labeled RW, and isolated from the rest of the P-type substrate. The isolation is the NW ring in contact with the DNW base which forms a barrier of N-type doped material. It is imperative the RW substrate is star-connected back to the GND pad and NOT connected to the local GND substrate. Doing this will effectively short out the DNW region and all noise isolation will be lost. Its also important to note DNW is an extra mask and therefore would incur extra cost. 5.0 CONCLUSIONS AND RECOMMENDATIONS

Having investigated the Moat guard ring strategy in detail, we can conclude from a theory perspective, that the isolation scheme currently being used seems sound and robust. We can also conclude the placement of the Pwell taps in respect to the Nwell guard rings is crucial to the success of the scheme. NT_N and Nwell widths are also critical, as is the impedance of the Pwell guard ring. These must work hand-in-hand with each other to ensure optimal noise attenuation and collection. Ive recommended additional Pwell straps and additional NT_N to further improve noise isolation. However this may prove space prohibitive. Ive also recommended using a triple well scheme and highlighted its potential advantages.

Adrian O'Shaughnessy
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