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A High Linearity and Eciency Doherty Power Amplier for Retrodirective Communication
Xiaoqun Chen, Yuchun Guo, and Xiaowei Shi National Key Laboratory of Antennas and Microwave Technology, Xidian University Xian 710071, China

Abstract This paper presents a Doherty power amplier with advanced design methods
for high eciency and linearity applied to retrodirective communication system for high peak to average power ratio (PAR). A special inverted Doherty topology is proposed in order to optimize the average eciency of Doherty amplier. Also we develop Doherty power amplier with uneven power drive which is provided more input power to the peak amplier than carrier amplier for full power operation and appropriate load modulation. These methods are applied to implement Doherty power amplier using GaAs FET. The amplier is optimized at large power back-o. The power added eciency (PAE) and adjacent channel leakage ratio (ACLR) are 33.1% and 47 dBc, which improves about 3.2% and 5 dB respectively, its third-order intermodulation distortion (IMD3) has 2.5 dB improvement compared with conventional Doherty power amplier.

1. INTRODUCTION

Recently, microwave retrodirective wireless communication has become a hot research area. It shows that the retrodirective array can simultaneously respond to each individual signal proving its usefulness in mobile wireless applications where multiple signal tracking is required [1]. Phase conjugation is a known key technique that applied to retrodirective communication systems [2]. The classical approach to achieve the phase conjugation necessary for these antennas is to use a low noise amplier, a high linear power amplier and a mixer arrangement [2]. Highly ecient and linear Power amplier is a key component in the systems. However, there is an obstacle in such system makes the use of amplier dicult, the high peakto-average power ratio (PAPR) caused by the large number of independent subcarriers with random phase and amplitude added together at the modulator [3]. The communication systems are reduced in both size and cost, but required the quality of communication [4, 5]. According to IEEE 802.11a, so a power amplier with high linearity and eciency is great of importance. The simplest method is to back-o signals form the saturation region to the linear region at the cost of power eciency, usually in an eciency form 12% to 20%. Another may use predistortion methods or elimination and restoration techniques or feedforward [6]. However, these techniques which need additional
Carrier Amplifier Input Matching Network Input Matching Network Z0 =50 L = /4 Z0 =50 L = /4 Input Matching Network Input Matching Network

Power Splitter

Z0 =35 L = /4

Z L=50

Peak Amplifier

Figure 1: The classical Doherty power amplier.

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components result in an increase in cost, size, and power dissipation [7]. In order to solve these problems, a Doherty amplier is the most promising candidate with simple fabrication and high eciency for the application, as Fig. 1 shown. The fundamental operation theory has been well described in [811]. The simplest Doherty amplier operation can be achieved using two cells with a class-AB biased carrier amplier cell and a class-C biased peak amplier cell with respective input matching network and output matching network. It has a high linearity and eciency across the wideband signal has been studied extensively for the application due to its high eciency. However, the conventional Doherty power amplier has its limitation. Due to its lower bias point, the current level of the peaking cell is always lower than that of the carrier cell. The load impedances of both cells cannot be fully modulated to the value of the optimum impedance for a high power match. Thus, neither cell can generate full output power. In this paper, two advanced methods are good approaches to solve these problems well. The implementation of the amplier is simple and results show excellent performance.
2. ADVANCE DESIGN METHODS 2.1. Inverted Doherty Power Amplier

As it is mentioned above, carrier amplier operational theories indicated that the best eciency at average envelop power actually occurred with load impedance closer to 25 than 100 . In order to achieve maximum eciency at 100 , approximately one-quarter wavelength of 50 line will be applied to the carrier ampliers output matching network in Fig. 1. Similarly, the ostate impedance presented by the peak amplier is so low that this also suggests appending /4 wavelength of 50 line to peak ampliers output matching network to guarantee high impedance at the combining node. Size and loss constraints make this approach undesirable. By reversing the Doherty combining point, a 25 maximum eciency load is provided for the carrier amplier at average envelop power. The impedance inversion previously accomplished with the 50 , /4 line is incorporated into peak output matching network, which constrains S 21 = 90 deg. As the peak cell, a 50, /4 line becomes the o-state impedance rotation appended to. Then output is taken from the carrier amplier side of the combining node as shown in Fig. 2, called inverted Doherty topology.
Carrier Amplifier Input Matching Network Input Matching Network

Z0=50 L = /4 Power Splitter

Z0 =35 L = /4 Z0 =50 L = /4

Z L= 50

Input Matching Network

Input Matching Network

Peak Amplifier

Figure 2: Inverted Doherty power amplier topology.

This inverted Doherty will guarantee the high eciency at the low drive lever. But most challenge of the Doherty design is the carrier amplier output match. In addition to the 90 degree phase requirement mentioned above, the gain of the carrier amplier must decrease by 3 dB as its output power transitions between average envelope power and half of peak envelope power. This can be understood by noting the carrier ampliers input power ranges from average envelope power to peak envelope power, while the required output power range is average envelope power to half of peak envelope power. The gain reduction is necessary to accommodate the half of peak envelope power of the peaking amplier. With uneven drive, more power will deliver to the peak cell. This creates a constant gain for the composite Doherty amplier at lower power regain, which is an important linearity consideration. To optimize the Doherty ampliers average eciency, the carrier ampliers output match must be designed for best eciency performance at

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average envelope power. For the inverted topology, this occurs at 25 . Maximum carrier amplier eciency is limited by the linearity which results when it is operated together with the Class C peaking amplier. The carrier amplier design is thus constrained by gain, phase, eciency, linearity, and absolute power requirements. When peak amplier operates at class C, its transfer characteristic must be smooth, without evidence of discontinuities. The adjacent channel leakage and IMD problems are obvious with two tone test. Design of bypassing and decoupling networks as well as the bias circuit are crucial to avoiding this problem with bypassing capacitors. The output contribution of the peaking amplier is expected to range from zero to half of peak envelope power for the same drive range which causes the carrier amplier to deliver average envelope power to half of peak envelope power. It is set to provide equal phase lengths in both signal paths. The nal phase length is optimized for best linearity and gain atness.
2.2. Uneven Power Drive

The basic operation principle of Doherty power amplier has been well described in [12, 13]. Fig. 3 depicts the load impedance of both ampliers versus input voltage. ZT 2 , 0 < Vin < Vin, max/2 ZL 2 ZT (1) ZC = , Vin, max/2 < Vin < Vin, max I ZL 1 + P IC 0 < Vin < Vin, max/2 , IP (2) ZP = , Vin, max/2 < Vin < Vin, max ZL 1 + IC where ZL is the load impedance of the Doherty amplier; IC and IP represent the fundamental currents of the carrier and peaking ampliers, respectively; and ZC and ZP are the output load impedances of the carrier and peaking ampliers, respectively, as Fig. 3 shown. In the low power region, the linearity of the amplier is entirely determined by the carrier cell. Therefore, the carrier cell should be highly linear for its careful optimized load impedance. In the high-power region, the current level of the peaking cell plays an important role in determining the load modulation of the amplier. For the asymmetric amplier with even power drive, the fundamental current of the peaking cell is insucient to achieve the full load modulation. The load impedances of both cells are larger than the optimum values in the high-power region. As a result,

6Zopt

Zp, Peak Amplifier

5Zopt

Load Impedence (Ohm)

4Zopt

3Zopt

2Zopt

Zc,Carrier Amplifier

Zopt

Vin,max/2 Input Voltage Amplitude

Vin,max

Figure 3: Load impedance versus input drive.

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the carrier and peaking cells are driven into saturation without producing full power. Thus, the amplier is seriously aected by linearity, as well as power level. In order to enhance the output power from the peak amplier, a Doherty amplier with uneven power drive is proposed, applied more power to the peak cell. As the amplier with uneven power drive, the linearity of the amplier is improved due to proper power operation without severe saturation. The linearity is further enhanced by the harmonic cancellation of from the two cells at appropriate gate biases. The carrier cell, which is biased at class AB, has the gain compression at high output power levels, while the class-C biased peak cell has the gain expansion. Hence, the gain expansion of the peak cell can compensate the gain compression of the carrier cell. Specically, the third-order intermodulation (IM3) level from the carrier cell increases and the phase of IM3 is decreased because the gain of the carrier cell is compressed. On the other hand, when the gain of the peak cell is expanded with uneven drive, both the IM3 level and phase increase. To cancel out IM3s from the two cells, the components must be 180 deg. out-of-phase with the same amplitudes. Therefore, the peak cell should be designed appropriately to cancel the harmonics of the carrier cell.
3. AMPLIFIER IMPLEMENTATION AND RESULTS

The proposed Doherty power amplier is designed with cascaded structure. It consists of three stages pre-driver, driver and nal stage, the novel Doherty amplier. The pre-driver and driver two stages are used to enhance higher output and power gain. They both work in class A, since this method makes the two stages under the small signal situation [14]. We put the emphases on the nal stage. Although power ampliers vary in saturation output power by changing drain dc voltage, this dc-voltage change preserves the power added eciency (PAE) for the various saturation, and PAE is Pout Pin Pout Pin = (3) P AEtotal = PDC PDC 1 + PDC 2 + PDC 3 For PDC is the total power consumption of the DPA PDC = VDDC IDQC + VDDP IDQP (4)

In Equation (4), VDDC and VDDP represent voltage supply for carrier and peak ampliers, IDDC and IDDP represent current supply for carrier and peak amplier respectively. The power amplier is shown in Fig. 4 and the performance of the Doherty power amplier not only considers the linearity, but also its eciency. To satisfy these demands, we use Freescale MFR6S21050L. We also fabricated a conventional Doherty amplier for comparison.

Figure 4: The photograph of cascaded Doherty power amplier.

Figure 5 depicted the gain and the PAE of the proposed Doherty power amplier and an ordinarily Doherty power amplier with even drive. Its gain achieves 44 dB and keeps a good at performance than the conventional Dohertys. As uneven power drive (1 : 2.5), the carrier cell is compressed early and the peaking cell expanded early and the region is wider than the usual Doherty amplier. Therefore, the amplier with an uneven drive generates more linear power because the early gain expansion of the peaking cell compensates the gain compression of the carrier cell over the wide power range although the power gain of the uneven case keeps a better linearity

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compared to the even drive case. The PAE of the uneven drive achieves 33.1% at the output of 45 dBm which enhances 3.2% at the average output of 37 dBm with the inverted structure due to load impedance modulation optimum.
Even Drive Uneven Driven Even Drive Uneven Driven Gain (dB) PAE(%)
IMD3 of Even Drive IMD3 of Uneven Drive ACLR of Even Drive ACLR of Uneven Drive

Output Power (dBm)

IMD3 (dBc) and ACLR (dBc)

Output Power (dBm)

Figure 5: Gain and power added eciency (PAE) for two types of Doherty power amplier.

Figure 6: IMD3 and ACLR performances for twotone signal with 5 MHz tone-spacing.

Figure 6 shows the measured IMD3 and ACLR of two types Doherty amplier. In comparison with even case, the uneven case with inverted output structure delivers ACLR performance at 47 dBc at 45 dBm output with 5 dB improvement for two-tone test at 5 MHz. IMD3 has 2.5 dB improvements too. These results that represent the proposed bypassing and decoupling networks in output matching network provides better output with adjacent channel leakage performance.

Output Back-off (dB)

Figure 7: PAE versus EVM with output back-o.

Figure 7 shows that the power added eciency of the cascaded Doherty power amplier with dierent output back-o and error-vector-magnitudes (EVM). According to the specication of the IEEE 802.11a WLAN, which requires an Error Vector Magnitude (EVM) no greater than 25 dB (i.e., less than or equal 5.6%) in order to meet consortium specications. The eciency of the inverted Doherty amplier achieves 32.8% with 5.6% EVM. The PAE maintains 31.5% with 10 dB output power back-o and 30% with 12 dB back-o. The power amplier performance evident demonstrates an excellent performance than a conventional Doherty power amplier.
4. CONCLUSIONS

In this paper, a high linearity and eciency three stages cascaded Doherty power amplier is proposed and fabricated with uneven power drive and inverted topology. Its PAE achieves 33.1%, which performs 3.2% better in the whole range than even drive case. With the inverted structure and the oset line in output matching network, it performs better in linearity and eciency than even case. The ACLR presents 47 dBc at 45 dBm output power which has 5 dB improvements

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at with 5 MHz two-tone test. The proposed amplier has IMD3 of 42 dBc which presents 2.5 dB improvements over the even case with appropriately cancellation of the carrier cell harmonics. The PAE maintains 30% while 12 dB Output back-o for low EVM. These experimental results clearly demonstrate the superior performance of the proposed Doherty power amplier compared to the conventional Doherty power ampliers. The proposed design methods are suited for retrodirective communication with high eciency and high linearity operation.
ACKNOWLEDGMENT

This work is supported by the National Natural Science Foundation of China under Contract No. 60571057.
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